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277bb6a2 NT |
1 | /* |
2 | * Imagination Technologies Pulse Width Modulator driver | |
3 | * | |
4 | * Copyright (c) 2014-2015, Imagination Technologies | |
5 | * | |
6 | * Based on drivers/pwm/pwm-tegra.c, Copyright (c) 2010, NVIDIA Corporation | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License. | |
11 | */ | |
12 | ||
13 | #include <linux/clk.h> | |
14 | #include <linux/err.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/mfd/syscon.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/of.h> | |
1e70897d | 19 | #include <linux/of_device.h> |
277bb6a2 NT |
20 | #include <linux/platform_device.h> |
21 | #include <linux/pwm.h> | |
22 | #include <linux/regmap.h> | |
23 | #include <linux/slab.h> | |
24 | ||
25 | /* PWM registers */ | |
26 | #define PWM_CTRL_CFG 0x0000 | |
27 | #define PWM_CTRL_CFG_NO_SUB_DIV 0 | |
28 | #define PWM_CTRL_CFG_SUB_DIV0 1 | |
29 | #define PWM_CTRL_CFG_SUB_DIV1 2 | |
30 | #define PWM_CTRL_CFG_SUB_DIV0_DIV1 3 | |
31 | #define PWM_CTRL_CFG_DIV_SHIFT(ch) ((ch) * 2 + 4) | |
32 | #define PWM_CTRL_CFG_DIV_MASK 0x3 | |
33 | ||
34 | #define PWM_CH_CFG(ch) (0x4 + (ch) * 4) | |
35 | #define PWM_CH_CFG_TMBASE_SHIFT 0 | |
36 | #define PWM_CH_CFG_DUTY_SHIFT 16 | |
37 | ||
38 | #define PERIP_PWM_PDM_CONTROL 0x0140 | |
39 | #define PERIP_PWM_PDM_CONTROL_CH_MASK 0x1 | |
40 | #define PERIP_PWM_PDM_CONTROL_CH_SHIFT(ch) ((ch) * 4) | |
41 | ||
1e70897d NT |
42 | /* |
43 | * PWM period is specified with a timebase register, | |
44 | * in number of step periods. The PWM duty cycle is also | |
45 | * specified in step periods, in the [0, $timebase] range. | |
46 | * In other words, the timebase imposes the duty cycle | |
47 | * resolution. Therefore, let's constraint the timebase to | |
48 | * a minimum value to allow a sane range of duty cycle values. | |
49 | * Imposing a minimum timebase, will impose a maximum PWM frequency. | |
50 | * | |
51 | * The value chosen is completely arbitrary. | |
52 | */ | |
53 | #define MIN_TMBASE_STEPS 16 | |
54 | ||
55 | struct img_pwm_soc_data { | |
56 | u32 max_timebase; | |
57 | }; | |
277bb6a2 NT |
58 | |
59 | struct img_pwm_chip { | |
60 | struct device *dev; | |
61 | struct pwm_chip chip; | |
62 | struct clk *pwm_clk; | |
63 | struct clk *sys_clk; | |
64 | void __iomem *base; | |
65 | struct regmap *periph_regs; | |
1e70897d NT |
66 | int max_period_ns; |
67 | int min_period_ns; | |
68 | const struct img_pwm_soc_data *data; | |
277bb6a2 NT |
69 | }; |
70 | ||
71 | static inline struct img_pwm_chip *to_img_pwm_chip(struct pwm_chip *chip) | |
72 | { | |
73 | return container_of(chip, struct img_pwm_chip, chip); | |
74 | } | |
75 | ||
76 | static inline void img_pwm_writel(struct img_pwm_chip *chip, | |
77 | u32 reg, u32 val) | |
78 | { | |
79 | writel(val, chip->base + reg); | |
80 | } | |
81 | ||
82 | static inline u32 img_pwm_readl(struct img_pwm_chip *chip, | |
83 | u32 reg) | |
84 | { | |
85 | return readl(chip->base + reg); | |
86 | } | |
87 | ||
88 | static int img_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, | |
89 | int duty_ns, int period_ns) | |
90 | { | |
91 | u32 val, div, duty, timebase; | |
92 | unsigned long mul, output_clk_hz, input_clk_hz; | |
93 | struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip); | |
1e70897d NT |
94 | unsigned int max_timebase = pwm_chip->data->max_timebase; |
95 | ||
96 | if (period_ns < pwm_chip->min_period_ns || | |
97 | period_ns > pwm_chip->max_period_ns) { | |
98 | dev_err(chip->dev, "configured period not in range\n"); | |
99 | return -ERANGE; | |
100 | } | |
277bb6a2 NT |
101 | |
102 | input_clk_hz = clk_get_rate(pwm_chip->pwm_clk); | |
103 | output_clk_hz = DIV_ROUND_UP(NSEC_PER_SEC, period_ns); | |
104 | ||
105 | mul = DIV_ROUND_UP(input_clk_hz, output_clk_hz); | |
1e70897d | 106 | if (mul <= max_timebase) { |
277bb6a2 NT |
107 | div = PWM_CTRL_CFG_NO_SUB_DIV; |
108 | timebase = DIV_ROUND_UP(mul, 1); | |
1e70897d | 109 | } else if (mul <= max_timebase * 8) { |
277bb6a2 NT |
110 | div = PWM_CTRL_CFG_SUB_DIV0; |
111 | timebase = DIV_ROUND_UP(mul, 8); | |
1e70897d | 112 | } else if (mul <= max_timebase * 64) { |
277bb6a2 NT |
113 | div = PWM_CTRL_CFG_SUB_DIV1; |
114 | timebase = DIV_ROUND_UP(mul, 64); | |
1e70897d | 115 | } else if (mul <= max_timebase * 512) { |
277bb6a2 NT |
116 | div = PWM_CTRL_CFG_SUB_DIV0_DIV1; |
117 | timebase = DIV_ROUND_UP(mul, 512); | |
1e70897d | 118 | } else if (mul > max_timebase * 512) { |
277bb6a2 NT |
119 | dev_err(chip->dev, |
120 | "failed to configure timebase steps/divider value\n"); | |
121 | return -EINVAL; | |
122 | } | |
123 | ||
124 | duty = DIV_ROUND_UP(timebase * duty_ns, period_ns); | |
125 | ||
126 | val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG); | |
127 | val &= ~(PWM_CTRL_CFG_DIV_MASK << PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm)); | |
128 | val |= (div & PWM_CTRL_CFG_DIV_MASK) << | |
129 | PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm); | |
130 | img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val); | |
131 | ||
132 | val = (duty << PWM_CH_CFG_DUTY_SHIFT) | | |
133 | (timebase << PWM_CH_CFG_TMBASE_SHIFT); | |
134 | img_pwm_writel(pwm_chip, PWM_CH_CFG(pwm->hwpwm), val); | |
135 | ||
136 | return 0; | |
137 | } | |
138 | ||
139 | static int img_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) | |
140 | { | |
141 | u32 val; | |
142 | struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip); | |
143 | ||
144 | val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG); | |
145 | val |= BIT(pwm->hwpwm); | |
146 | img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val); | |
147 | ||
148 | regmap_update_bits(pwm_chip->periph_regs, PERIP_PWM_PDM_CONTROL, | |
149 | PERIP_PWM_PDM_CONTROL_CH_MASK << | |
150 | PERIP_PWM_PDM_CONTROL_CH_SHIFT(pwm->hwpwm), 0); | |
151 | ||
152 | return 0; | |
153 | } | |
154 | ||
155 | static void img_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) | |
156 | { | |
157 | u32 val; | |
158 | struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip); | |
159 | ||
160 | val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG); | |
161 | val &= ~BIT(pwm->hwpwm); | |
162 | img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val); | |
163 | } | |
164 | ||
165 | static const struct pwm_ops img_pwm_ops = { | |
166 | .config = img_pwm_config, | |
167 | .enable = img_pwm_enable, | |
168 | .disable = img_pwm_disable, | |
169 | .owner = THIS_MODULE, | |
170 | }; | |
171 | ||
1e70897d NT |
172 | static const struct img_pwm_soc_data pistachio_pwm = { |
173 | .max_timebase = 255, | |
174 | }; | |
175 | ||
176 | static const struct of_device_id img_pwm_of_match[] = { | |
177 | { | |
178 | .compatible = "img,pistachio-pwm", | |
179 | .data = &pistachio_pwm, | |
180 | }, | |
181 | { } | |
182 | }; | |
183 | MODULE_DEVICE_TABLE(of, img_pwm_of_match); | |
184 | ||
277bb6a2 NT |
185 | static int img_pwm_probe(struct platform_device *pdev) |
186 | { | |
187 | int ret; | |
1e70897d NT |
188 | u64 val; |
189 | unsigned long clk_rate; | |
277bb6a2 NT |
190 | struct resource *res; |
191 | struct img_pwm_chip *pwm; | |
1e70897d | 192 | const struct of_device_id *of_dev_id; |
277bb6a2 NT |
193 | |
194 | pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL); | |
195 | if (!pwm) | |
196 | return -ENOMEM; | |
197 | ||
198 | pwm->dev = &pdev->dev; | |
199 | ||
200 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
201 | pwm->base = devm_ioremap_resource(&pdev->dev, res); | |
202 | if (IS_ERR(pwm->base)) | |
203 | return PTR_ERR(pwm->base); | |
204 | ||
1e70897d NT |
205 | of_dev_id = of_match_device(img_pwm_of_match, &pdev->dev); |
206 | if (!of_dev_id) | |
207 | return -ENODEV; | |
208 | pwm->data = of_dev_id->data; | |
209 | ||
277bb6a2 NT |
210 | pwm->periph_regs = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, |
211 | "img,cr-periph"); | |
212 | if (IS_ERR(pwm->periph_regs)) | |
213 | return PTR_ERR(pwm->periph_regs); | |
214 | ||
215 | pwm->sys_clk = devm_clk_get(&pdev->dev, "sys"); | |
216 | if (IS_ERR(pwm->sys_clk)) { | |
217 | dev_err(&pdev->dev, "failed to get system clock\n"); | |
218 | return PTR_ERR(pwm->sys_clk); | |
219 | } | |
220 | ||
221 | pwm->pwm_clk = devm_clk_get(&pdev->dev, "pwm"); | |
222 | if (IS_ERR(pwm->pwm_clk)) { | |
223 | dev_err(&pdev->dev, "failed to get pwm clock\n"); | |
224 | return PTR_ERR(pwm->pwm_clk); | |
225 | } | |
226 | ||
227 | ret = clk_prepare_enable(pwm->sys_clk); | |
228 | if (ret < 0) { | |
229 | dev_err(&pdev->dev, "could not prepare or enable sys clock\n"); | |
230 | return ret; | |
231 | } | |
232 | ||
233 | ret = clk_prepare_enable(pwm->pwm_clk); | |
234 | if (ret < 0) { | |
235 | dev_err(&pdev->dev, "could not prepare or enable pwm clock\n"); | |
236 | goto disable_sysclk; | |
237 | } | |
238 | ||
1e70897d | 239 | clk_rate = clk_get_rate(pwm->pwm_clk); |
bea307c1 WS |
240 | if (!clk_rate) { |
241 | dev_err(&pdev->dev, "pwm clock has no frequency\n"); | |
242 | ret = -EINVAL; | |
243 | goto disable_pwmclk; | |
244 | } | |
1e70897d NT |
245 | |
246 | /* The maximum input clock divider is 512 */ | |
247 | val = (u64)NSEC_PER_SEC * 512 * pwm->data->max_timebase; | |
248 | do_div(val, clk_rate); | |
249 | pwm->max_period_ns = val; | |
250 | ||
251 | val = (u64)NSEC_PER_SEC * MIN_TMBASE_STEPS; | |
252 | do_div(val, clk_rate); | |
253 | pwm->min_period_ns = val; | |
254 | ||
277bb6a2 NT |
255 | pwm->chip.dev = &pdev->dev; |
256 | pwm->chip.ops = &img_pwm_ops; | |
257 | pwm->chip.base = -1; | |
258 | pwm->chip.npwm = 4; | |
259 | ||
260 | ret = pwmchip_add(&pwm->chip); | |
261 | if (ret < 0) { | |
262 | dev_err(&pdev->dev, "pwmchip_add failed: %d\n", ret); | |
263 | goto disable_pwmclk; | |
264 | } | |
265 | ||
266 | platform_set_drvdata(pdev, pwm); | |
267 | return 0; | |
268 | ||
269 | disable_pwmclk: | |
270 | clk_disable_unprepare(pwm->pwm_clk); | |
271 | disable_sysclk: | |
272 | clk_disable_unprepare(pwm->sys_clk); | |
273 | return ret; | |
274 | } | |
275 | ||
276 | static int img_pwm_remove(struct platform_device *pdev) | |
277 | { | |
278 | struct img_pwm_chip *pwm_chip = platform_get_drvdata(pdev); | |
279 | u32 val; | |
280 | unsigned int i; | |
281 | ||
282 | for (i = 0; i < pwm_chip->chip.npwm; i++) { | |
283 | val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG); | |
284 | val &= ~BIT(i); | |
285 | img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val); | |
286 | } | |
287 | ||
288 | clk_disable_unprepare(pwm_chip->pwm_clk); | |
289 | clk_disable_unprepare(pwm_chip->sys_clk); | |
290 | ||
291 | return pwmchip_remove(&pwm_chip->chip); | |
292 | } | |
293 | ||
277bb6a2 NT |
294 | static struct platform_driver img_pwm_driver = { |
295 | .driver = { | |
296 | .name = "img-pwm", | |
297 | .of_match_table = img_pwm_of_match, | |
298 | }, | |
299 | .probe = img_pwm_probe, | |
300 | .remove = img_pwm_remove, | |
301 | }; | |
302 | module_platform_driver(img_pwm_driver); | |
303 | ||
304 | MODULE_AUTHOR("Sai Masarapu <Sai.Masarapu@imgtec.com>"); | |
305 | MODULE_DESCRIPTION("Imagination Technologies PWM DAC driver"); | |
306 | MODULE_LICENSE("GPL v2"); |