Commit | Line | Data |
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166091b1 SH |
1 | /* |
2 | * simple driver for PWM (Pulse Width Modulator) controller | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com> | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/platform_device.h> | |
5a0e3ad6 | 14 | #include <linux/slab.h> |
166091b1 SH |
15 | #include <linux/err.h> |
16 | #include <linux/clk.h> | |
137fd45f | 17 | #include <linux/delay.h> |
166091b1 SH |
18 | #include <linux/io.h> |
19 | #include <linux/pwm.h> | |
2a8876cf | 20 | #include <linux/of.h> |
479e2e30 | 21 | #include <linux/of_device.h> |
c010dba8 | 22 | |
c010dba8 HS |
23 | /* i.MX1 and i.MX21 share the same PWM function block: */ |
24 | ||
40f260c2 LY |
25 | #define MX1_PWMC 0x00 /* PWM Control Register */ |
26 | #define MX1_PWMS 0x04 /* PWM Sample Register */ | |
27 | #define MX1_PWMP 0x08 /* PWM Period Register */ | |
c010dba8 | 28 | |
40f260c2 | 29 | #define MX1_PWMC_EN (1 << 4) |
c010dba8 HS |
30 | |
31 | /* i.MX27, i.MX31, i.MX35 share the same PWM function block: */ | |
32 | ||
40f260c2 | 33 | #define MX3_PWMCR 0x00 /* PWM Control Register */ |
137fd45f | 34 | #define MX3_PWMSR 0x04 /* PWM Status Register */ |
40f260c2 LY |
35 | #define MX3_PWMSAR 0x0C /* PWM Sample Register */ |
36 | #define MX3_PWMPR 0x10 /* PWM Period Register */ | |
37 | #define MX3_PWMCR_PRESCALER(x) ((((x) - 1) & 0xFFF) << 4) | |
38 | #define MX3_PWMCR_DOZEEN (1 << 24) | |
39 | #define MX3_PWMCR_WAITEN (1 << 23) | |
c0d96aed | 40 | #define MX3_PWMCR_DBGEN (1 << 22) |
40f260c2 LY |
41 | #define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16) |
42 | #define MX3_PWMCR_CLKSRC_IPG (1 << 16) | |
137fd45f | 43 | #define MX3_PWMCR_SWR (1 << 3) |
40f260c2 | 44 | #define MX3_PWMCR_EN (1 << 0) |
137fd45f LY |
45 | #define MX3_PWMSR_FIFOAV_4WORDS 0x4 |
46 | #define MX3_PWMSR_FIFOAV_MASK 0x7 | |
47 | ||
48 | #define MX3_PWM_SWR_LOOP 5 | |
c010dba8 | 49 | |
29693248 | 50 | struct imx_chip { |
7b27c160 PZ |
51 | struct clk *clk_per; |
52 | struct clk *clk_ipg; | |
166091b1 | 53 | |
166091b1 SH |
54 | void __iomem *mmio_base; |
55 | ||
29693248 | 56 | struct pwm_chip chip; |
19e73333 SH |
57 | |
58 | int (*config)(struct pwm_chip *chip, | |
59 | struct pwm_device *pwm, int duty_ns, int period_ns); | |
66ad6a61 | 60 | void (*set_enable)(struct pwm_chip *chip, bool enable); |
166091b1 SH |
61 | }; |
62 | ||
29693248 SH |
63 | #define to_imx_chip(chip) container_of(chip, struct imx_chip, chip) |
64 | ||
19e73333 | 65 | static int imx_pwm_config_v1(struct pwm_chip *chip, |
29693248 | 66 | struct pwm_device *pwm, int duty_ns, int period_ns) |
166091b1 | 67 | { |
29693248 | 68 | struct imx_chip *imx = to_imx_chip(chip); |
166091b1 | 69 | |
19e73333 SH |
70 | /* |
71 | * The PWM subsystem allows for exact frequencies. However, | |
72 | * I cannot connect a scope on my device to the PWM line and | |
73 | * thus cannot provide the program the PWM controller | |
74 | * exactly. Instead, I'm relying on the fact that the | |
75 | * Bootloader (u-boot or WinCE+haret) has programmed the PWM | |
76 | * function group already. So I'll just modify the PWM sample | |
77 | * register to follow the ratio of duty_ns vs. period_ns | |
78 | * accordingly. | |
79 | * | |
80 | * This is good enough for programming the brightness of | |
81 | * the LCD backlight. | |
82 | * | |
83 | * The real implementation would divide PERCLK[0] first by | |
84 | * both the prescaler (/1 .. /128) and then by CLKSEL | |
85 | * (/2 .. /16). | |
86 | */ | |
87 | u32 max = readl(imx->mmio_base + MX1_PWMP); | |
88 | u32 p = max * duty_ns / period_ns; | |
89 | writel(max - p, imx->mmio_base + MX1_PWMS); | |
90 | ||
91 | return 0; | |
92 | } | |
93 | ||
66ad6a61 SH |
94 | static void imx_pwm_set_enable_v1(struct pwm_chip *chip, bool enable) |
95 | { | |
96 | struct imx_chip *imx = to_imx_chip(chip); | |
97 | u32 val; | |
98 | ||
99 | val = readl(imx->mmio_base + MX1_PWMC); | |
100 | ||
101 | if (enable) | |
102 | val |= MX1_PWMC_EN; | |
103 | else | |
104 | val &= ~MX1_PWMC_EN; | |
105 | ||
106 | writel(val, imx->mmio_base + MX1_PWMC); | |
107 | } | |
108 | ||
19e73333 SH |
109 | static int imx_pwm_config_v2(struct pwm_chip *chip, |
110 | struct pwm_device *pwm, int duty_ns, int period_ns) | |
111 | { | |
112 | struct imx_chip *imx = to_imx_chip(chip); | |
137fd45f | 113 | struct device *dev = chip->dev; |
19e73333 SH |
114 | unsigned long long c; |
115 | unsigned long period_cycles, duty_cycles, prescale; | |
137fd45f LY |
116 | unsigned int period_ms; |
117 | bool enable = test_bit(PWMF_ENABLED, &pwm->flags); | |
118 | int wait_count = 0, fifoav; | |
119 | u32 cr, sr; | |
120 | ||
121 | /* | |
122 | * i.MX PWMv2 has a 4-word sample FIFO. | |
123 | * In order to avoid FIFO overflow issue, we do software reset | |
124 | * to clear all sample FIFO if the controller is disabled or | |
125 | * wait for a full PWM cycle to get a relinquished FIFO slot | |
126 | * when the controller is enabled and the FIFO is fully loaded. | |
127 | */ | |
128 | if (enable) { | |
129 | sr = readl(imx->mmio_base + MX3_PWMSR); | |
130 | fifoav = sr & MX3_PWMSR_FIFOAV_MASK; | |
131 | if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) { | |
132 | period_ms = DIV_ROUND_UP(pwm->period, NSEC_PER_MSEC); | |
133 | msleep(period_ms); | |
134 | ||
135 | sr = readl(imx->mmio_base + MX3_PWMSR); | |
136 | if (fifoav == (sr & MX3_PWMSR_FIFOAV_MASK)) | |
137 | dev_warn(dev, "there is no free FIFO slot\n"); | |
138 | } | |
139 | } else { | |
140 | writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR); | |
141 | do { | |
142 | usleep_range(200, 1000); | |
143 | cr = readl(imx->mmio_base + MX3_PWMCR); | |
144 | } while ((cr & MX3_PWMCR_SWR) && | |
145 | (wait_count++ < MX3_PWM_SWR_LOOP)); | |
146 | ||
147 | if (cr & MX3_PWMCR_SWR) | |
148 | dev_warn(dev, "software reset timeout\n"); | |
149 | } | |
19e73333 | 150 | |
7b27c160 | 151 | c = clk_get_rate(imx->clk_per); |
19e73333 SH |
152 | c = c * period_ns; |
153 | do_div(c, 1000000000); | |
154 | period_cycles = c; | |
155 | ||
156 | prescale = period_cycles / 0x10000 + 1; | |
157 | ||
158 | period_cycles /= prescale; | |
159 | c = (unsigned long long)period_cycles * duty_ns; | |
160 | do_div(c, period_ns); | |
161 | duty_cycles = c; | |
162 | ||
163 | /* | |
164 | * according to imx pwm RM, the real period value should be | |
165 | * PERIOD value in PWMPR plus 2. | |
166 | */ | |
167 | if (period_cycles > 2) | |
168 | period_cycles -= 2; | |
169 | else | |
170 | period_cycles = 0; | |
171 | ||
172 | writel(duty_cycles, imx->mmio_base + MX3_PWMSAR); | |
173 | writel(period_cycles, imx->mmio_base + MX3_PWMPR); | |
174 | ||
175 | cr = MX3_PWMCR_PRESCALER(prescale) | | |
176 | MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN | | |
8d1c24bf | 177 | MX3_PWMCR_DBGEN | MX3_PWMCR_CLKSRC_IPG_HIGH; |
66ad6a61 | 178 | |
137fd45f | 179 | if (enable) |
66ad6a61 | 180 | cr |= MX3_PWMCR_EN; |
19e73333 | 181 | |
19e73333 | 182 | writel(cr, imx->mmio_base + MX3_PWMCR); |
166091b1 SH |
183 | |
184 | return 0; | |
185 | } | |
166091b1 | 186 | |
66ad6a61 SH |
187 | static void imx_pwm_set_enable_v2(struct pwm_chip *chip, bool enable) |
188 | { | |
189 | struct imx_chip *imx = to_imx_chip(chip); | |
190 | u32 val; | |
191 | ||
192 | val = readl(imx->mmio_base + MX3_PWMCR); | |
193 | ||
194 | if (enable) | |
195 | val |= MX3_PWMCR_EN; | |
196 | else | |
197 | val &= ~MX3_PWMCR_EN; | |
198 | ||
199 | writel(val, imx->mmio_base + MX3_PWMCR); | |
200 | } | |
201 | ||
19e73333 SH |
202 | static int imx_pwm_config(struct pwm_chip *chip, |
203 | struct pwm_device *pwm, int duty_ns, int period_ns) | |
204 | { | |
205 | struct imx_chip *imx = to_imx_chip(chip); | |
7b27c160 PZ |
206 | int ret; |
207 | ||
208 | ret = clk_prepare_enable(imx->clk_ipg); | |
209 | if (ret) | |
210 | return ret; | |
19e73333 | 211 | |
7b27c160 PZ |
212 | ret = imx->config(chip, pwm, duty_ns, period_ns); |
213 | ||
214 | clk_disable_unprepare(imx->clk_ipg); | |
215 | ||
216 | return ret; | |
19e73333 SH |
217 | } |
218 | ||
29693248 | 219 | static int imx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) |
166091b1 | 220 | { |
29693248 | 221 | struct imx_chip *imx = to_imx_chip(chip); |
140827c1 | 222 | int ret; |
166091b1 | 223 | |
7b27c160 | 224 | ret = clk_prepare_enable(imx->clk_per); |
140827c1 SH |
225 | if (ret) |
226 | return ret; | |
227 | ||
66ad6a61 SH |
228 | imx->set_enable(chip, true); |
229 | ||
140827c1 | 230 | return 0; |
166091b1 | 231 | } |
166091b1 | 232 | |
29693248 | 233 | static void imx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) |
166091b1 | 234 | { |
29693248 | 235 | struct imx_chip *imx = to_imx_chip(chip); |
166091b1 | 236 | |
66ad6a61 | 237 | imx->set_enable(chip, false); |
166091b1 | 238 | |
7b27c160 | 239 | clk_disable_unprepare(imx->clk_per); |
166091b1 | 240 | } |
166091b1 | 241 | |
29693248 SH |
242 | static struct pwm_ops imx_pwm_ops = { |
243 | .enable = imx_pwm_enable, | |
244 | .disable = imx_pwm_disable, | |
245 | .config = imx_pwm_config, | |
246 | .owner = THIS_MODULE, | |
247 | }; | |
166091b1 | 248 | |
479e2e30 PZ |
249 | struct imx_pwm_data { |
250 | int (*config)(struct pwm_chip *chip, | |
251 | struct pwm_device *pwm, int duty_ns, int period_ns); | |
252 | void (*set_enable)(struct pwm_chip *chip, bool enable); | |
253 | }; | |
254 | ||
255 | static struct imx_pwm_data imx_pwm_data_v1 = { | |
256 | .config = imx_pwm_config_v1, | |
257 | .set_enable = imx_pwm_set_enable_v1, | |
258 | }; | |
259 | ||
260 | static struct imx_pwm_data imx_pwm_data_v2 = { | |
261 | .config = imx_pwm_config_v2, | |
262 | .set_enable = imx_pwm_set_enable_v2, | |
263 | }; | |
264 | ||
265 | static const struct of_device_id imx_pwm_dt_ids[] = { | |
266 | { .compatible = "fsl,imx1-pwm", .data = &imx_pwm_data_v1, }, | |
267 | { .compatible = "fsl,imx27-pwm", .data = &imx_pwm_data_v2, }, | |
268 | { /* sentinel */ } | |
269 | }; | |
270 | MODULE_DEVICE_TABLE(of, imx_pwm_dt_ids); | |
271 | ||
3e9fe83d | 272 | static int imx_pwm_probe(struct platform_device *pdev) |
166091b1 | 273 | { |
479e2e30 PZ |
274 | const struct of_device_id *of_id = |
275 | of_match_device(imx_pwm_dt_ids, &pdev->dev); | |
983290b0 | 276 | const struct imx_pwm_data *data; |
29693248 | 277 | struct imx_chip *imx; |
166091b1 SH |
278 | struct resource *r; |
279 | int ret = 0; | |
280 | ||
479e2e30 PZ |
281 | if (!of_id) |
282 | return -ENODEV; | |
283 | ||
a9970e3b | 284 | imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL); |
1cbec749 | 285 | if (imx == NULL) |
166091b1 | 286 | return -ENOMEM; |
166091b1 | 287 | |
7b27c160 PZ |
288 | imx->clk_per = devm_clk_get(&pdev->dev, "per"); |
289 | if (IS_ERR(imx->clk_per)) { | |
290 | dev_err(&pdev->dev, "getting per clock failed with %ld\n", | |
291 | PTR_ERR(imx->clk_per)); | |
292 | return PTR_ERR(imx->clk_per); | |
293 | } | |
166091b1 | 294 | |
7b27c160 PZ |
295 | imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
296 | if (IS_ERR(imx->clk_ipg)) { | |
297 | dev_err(&pdev->dev, "getting ipg clock failed with %ld\n", | |
298 | PTR_ERR(imx->clk_ipg)); | |
299 | return PTR_ERR(imx->clk_ipg); | |
300 | } | |
166091b1 | 301 | |
29693248 SH |
302 | imx->chip.ops = &imx_pwm_ops; |
303 | imx->chip.dev = &pdev->dev; | |
304 | imx->chip.base = -1; | |
305 | imx->chip.npwm = 1; | |
31c4fa34 | 306 | imx->chip.can_sleep = true; |
166091b1 | 307 | |
166091b1 | 308 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
6d4294d1 TR |
309 | imx->mmio_base = devm_ioremap_resource(&pdev->dev, r); |
310 | if (IS_ERR(imx->mmio_base)) | |
311 | return PTR_ERR(imx->mmio_base); | |
166091b1 | 312 | |
479e2e30 PZ |
313 | data = of_id->data; |
314 | imx->config = data->config; | |
315 | imx->set_enable = data->set_enable; | |
19e73333 | 316 | |
29693248 SH |
317 | ret = pwmchip_add(&imx->chip); |
318 | if (ret < 0) | |
a9970e3b | 319 | return ret; |
166091b1 | 320 | |
29693248 | 321 | platform_set_drvdata(pdev, imx); |
166091b1 | 322 | return 0; |
166091b1 SH |
323 | } |
324 | ||
77f37917 | 325 | static int imx_pwm_remove(struct platform_device *pdev) |
166091b1 | 326 | { |
29693248 | 327 | struct imx_chip *imx; |
166091b1 | 328 | |
29693248 SH |
329 | imx = platform_get_drvdata(pdev); |
330 | if (imx == NULL) | |
166091b1 SH |
331 | return -ENODEV; |
332 | ||
a9970e3b | 333 | return pwmchip_remove(&imx->chip); |
166091b1 SH |
334 | } |
335 | ||
29693248 | 336 | static struct platform_driver imx_pwm_driver = { |
166091b1 | 337 | .driver = { |
479e2e30 | 338 | .name = "imx-pwm", |
becbca13 | 339 | .of_match_table = imx_pwm_dt_ids, |
166091b1 | 340 | }, |
29693248 | 341 | .probe = imx_pwm_probe, |
fd109112 | 342 | .remove = imx_pwm_remove, |
166091b1 SH |
343 | }; |
344 | ||
208d038f | 345 | module_platform_driver(imx_pwm_driver); |
166091b1 SH |
346 | |
347 | MODULE_LICENSE("GPL v2"); | |
348 | MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); |