[deliverable/linux.git] / drivers / pwm / pwm-lpss.c

/*
 * Intel Low Power Subsystem PWM controller driver
 *
 * Copyright (C) 2014, Intel Corporation
 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
 * Author: Chew Kean Ho <kean.ho.chew@intel.com>
 * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
 * Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
 * Author: Alan Cox <alan@linux.intel.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>

#include "pwm-lpss.h"

#define PWM				0x00000000
#define PWM_ENABLE			BIT(31)
#define PWM_SW_UPDATE			BIT(30)
#define PWM_BASE_UNIT_SHIFT		8
#define PWM_BASE_UNIT_MASK		0x00ffff00
#define PWM_ON_TIME_DIV_MASK		0x000000ff
#define PWM_DIVISION_CORRECTION		0x2
#define PWM_LIMIT			(0x8000 + PWM_DIVISION_CORRECTION)
#define NSECS_PER_SEC			1000000000UL

/* Size of each PWM register space if multiple */
#define PWM_SIZE			0x400

struct pwm_lpss_chip {
	struct pwm_chip chip;
	void __iomem *regs;
	unsigned long clk_rate;
};

/* BayTrail */
const struct pwm_lpss_boardinfo pwm_lpss_byt_info = {
	.clk_rate = 25000000,
	.npwm = 1,
};
EXPORT_SYMBOL_GPL(pwm_lpss_byt_info);

/* Braswell */
const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = {
	.clk_rate = 19200000,
	.npwm = 1,
};
EXPORT_SYMBOL_GPL(pwm_lpss_bsw_info);

/* Broxton */
const struct pwm_lpss_boardinfo pwm_lpss_bxt_info = {
	.clk_rate = 19200000,
	.npwm = 4,
};
EXPORT_SYMBOL_GPL(pwm_lpss_bxt_info);

static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
{
	return container_of(chip, struct pwm_lpss_chip, chip);
}

static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
{
	struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);

	return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
}

static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
{
	struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);

	writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
}

static int pwm_lpss_config(struct pwm_chip *chip, struct pwm_device *pwm,
			   int duty_ns, int period_ns)
{
	struct pwm_lpss_chip *lpwm = to_lpwm(chip);
	u8 on_time_div;
	unsigned long c;
	unsigned long long base_unit, freq = NSECS_PER_SEC;
	u32 ctrl;

	do_div(freq, period_ns);

	/* The equation is: base_unit = ((freq / c) * 65536) + correction */
	base_unit = freq * 65536;

	c = lpwm->clk_rate;
	if (!c)
		return -EINVAL;

	do_div(base_unit, c);
	base_unit += PWM_DIVISION_CORRECTION;
	if (base_unit > PWM_LIMIT)
		return -EINVAL;

	if (duty_ns <= 0)
		duty_ns = 1;
	on_time_div = 255 - (255 * duty_ns / period_ns);

	pm_runtime_get_sync(chip->dev);

	ctrl = pwm_lpss_read(pwm);
	ctrl &= ~(PWM_BASE_UNIT_MASK | PWM_ON_TIME_DIV_MASK);
	ctrl |= (u16) base_unit << PWM_BASE_UNIT_SHIFT;
	ctrl |= on_time_div;
	/* request PWM to update on next cycle */
	ctrl |= PWM_SW_UPDATE;
	pwm_lpss_write(pwm, ctrl);

	pm_runtime_put(chip->dev);

	return 0;
}

static int pwm_lpss_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	pm_runtime_get_sync(chip->dev);
	pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
	return 0;
}

static void pwm_lpss_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
	pm_runtime_put(chip->dev);
}

static const struct pwm_ops pwm_lpss_ops = {
	.free = pwm_lpss_disable,
	.config = pwm_lpss_config,
	.enable = pwm_lpss_enable,
	.disable = pwm_lpss_disable,
	.owner = THIS_MODULE,
};

struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
				     const struct pwm_lpss_boardinfo *info)
{
	struct pwm_lpss_chip *lpwm;
	int ret;

	lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
	if (!lpwm)
		return ERR_PTR(-ENOMEM);

	lpwm->regs = devm_ioremap_resource(dev, r);
	if (IS_ERR(lpwm->regs))
		return ERR_CAST(lpwm->regs);

	lpwm->clk_rate = info->clk_rate;
	lpwm->chip.dev = dev;
	lpwm->chip.ops = &pwm_lpss_ops;
	lpwm->chip.base = -1;
	lpwm->chip.npwm = info->npwm;

	ret = pwmchip_add(&lpwm->chip);
	if (ret) {
		dev_err(dev, "failed to add PWM chip: %d\n", ret);
		return ERR_PTR(ret);
	}

	return lpwm;
}
EXPORT_SYMBOL_GPL(pwm_lpss_probe);

int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
{
	return pwmchip_remove(&lpwm->chip);
}
EXPORT_SYMBOL_GPL(pwm_lpss_remove);

MODULE_DESCRIPTION("PWM driver for Intel LPSS");
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
d16a5aa9 MW	1	/*
	2	* Intel Low Power Subsystem PWM controller driver
	3	*
	4	* Copyright (C) 2014, Intel Corporation
	5	* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
	6	* Author: Chew Kean Ho <kean.ho.chew@intel.com>
	7	* Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
	8	* Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
093e00bb	9	* Author: Alan Cox <alan@linux.intel.com>
d16a5aa9 MW	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
e0c86a3b	16	#include <linux/io.h>
d16a5aa9 MW	17	#include <linux/kernel.h>
d16a5aa9 MW	18	#include <linux/module.h>
f080be27	19	#include <linux/pm_runtime.h>
093e00bb	20
c558e39e	21	#include "pwm-lpss.h"
d16a5aa9 MW	22
	23	#define PWM 0x00000000
	24	#define PWM_ENABLE BIT(31)
	25	#define PWM_SW_UPDATE BIT(30)
	26	#define PWM_BASE_UNIT_SHIFT 8
	27	#define PWM_BASE_UNIT_MASK 0x00ffff00
	28	#define PWM_ON_TIME_DIV_MASK 0x000000ff
	29	#define PWM_DIVISION_CORRECTION 0x2
	30	#define PWM_LIMIT (0x8000 + PWM_DIVISION_CORRECTION)
	31	#define NSECS_PER_SEC 1000000000UL
	32
4e11f5ac MW	33	/* Size of each PWM register space if multiple */
	34	#define PWM_SIZE 0x400
	35
d16a5aa9 MW	36	struct pwm_lpss_chip {
	37	struct pwm_chip chip;
	38	void __iomem *regs;
093e00bb AC	39	unsigned long clk_rate;
	40	};
	41
093e00bb	42	/* BayTrail */
c558e39e	43	const struct pwm_lpss_boardinfo pwm_lpss_byt_info = {
4e11f5ac MW	44	.clk_rate = 25000000,
4e11f5ac MW	45	.npwm = 1,
d16a5aa9	46	};
c558e39e	47	EXPORT_SYMBOL_GPL(pwm_lpss_byt_info);
d16a5aa9	48
373c5782	49	/* Braswell */
c558e39e	50	const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = {
4e11f5ac MW	51	.clk_rate = 19200000,
4e11f5ac MW	52	.npwm = 1,
373c5782	53	};
c558e39e	54	EXPORT_SYMBOL_GPL(pwm_lpss_bsw_info);
373c5782	55
87219cb4 MW	56	/* Broxton */
	57	const struct pwm_lpss_boardinfo pwm_lpss_bxt_info = {
	58	.clk_rate = 19200000,
	59	.npwm = 4,
	60	};
	61	EXPORT_SYMBOL_GPL(pwm_lpss_bxt_info);
	62
d16a5aa9 MW	63	static inline struct pwm_lpss_chip to_lpwm(struct pwm_chip chip)
	64	{
	65	return container_of(chip, struct pwm_lpss_chip, chip);
	66	}
	67
4e11f5ac MW	68	static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
	69	{
	70	struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
	71
	72	return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
	73	}
	74
	75	static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
	76	{
	77	struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
	78
	79	writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
	80	}
	81
d16a5aa9 MW	82	static int pwm_lpss_config(struct pwm_chip chip, struct pwm_device pwm,
	83	int duty_ns, int period_ns)
	84	{
	85	struct pwm_lpss_chip *lpwm = to_lpwm(chip);
	86	u8 on_time_div;
	87	unsigned long c;
	88	unsigned long long base_unit, freq = NSECS_PER_SEC;
	89	u32 ctrl;
	90
	91	do_div(freq, period_ns);
	92
	93	/* The equation is: base_unit = ((freq / c) * 65536) + correction */
	94	base_unit = freq * 65536;
	95
093e00bb	96	c = lpwm->clk_rate;
d16a5aa9 MW	97	if (!c)
	98	return -EINVAL;
	99
	100	do_div(base_unit, c);
	101	base_unit += PWM_DIVISION_CORRECTION;
	102	if (base_unit > PWM_LIMIT)
	103	return -EINVAL;
	104
	105	if (duty_ns <= 0)
	106	duty_ns = 1;
	107	on_time_div = 255 - (255 * duty_ns / period_ns);
	108
f080be27 QZ	109	pm_runtime_get_sync(chip->dev);
f080be27 QZ	110
4e11f5ac	111	ctrl = pwm_lpss_read(pwm);
d16a5aa9 MW	112	ctrl &= ~(PWM_BASE_UNIT_MASK \| PWM_ON_TIME_DIV_MASK);
	113	ctrl \|= (u16) base_unit << PWM_BASE_UNIT_SHIFT;
	114	ctrl \|= on_time_div;
	115	/* request PWM to update on next cycle */
	116	ctrl \|= PWM_SW_UPDATE;
4e11f5ac	117	pwm_lpss_write(pwm, ctrl);
d16a5aa9	118
f080be27 QZ	119	pm_runtime_put(chip->dev);
f080be27 QZ	120
d16a5aa9 MW	121	return 0;
	122	}
	123
	124	static int pwm_lpss_enable(struct pwm_chip chip, struct pwm_device pwm)
	125	{
f080be27	126	pm_runtime_get_sync(chip->dev);
4e11f5ac	127	pwm_lpss_write(pwm, pwm_lpss_read(pwm) \| PWM_ENABLE);
d16a5aa9 MW	128	return 0;
	129	}
	130
	131	static void pwm_lpss_disable(struct pwm_chip chip, struct pwm_device pwm)
	132	{
4e11f5ac	133	pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
f080be27	134	pm_runtime_put(chip->dev);
d16a5aa9 MW	135	}
	136
	137	static const struct pwm_ops pwm_lpss_ops = {
4e11f5ac	138	.free = pwm_lpss_disable,
d16a5aa9 MW	139	.config = pwm_lpss_config,
	140	.enable = pwm_lpss_enable,
	141	.disable = pwm_lpss_disable,
	142	.owner = THIS_MODULE,
	143	};
	144
c558e39e AS	145	struct pwm_lpss_chip pwm_lpss_probe(struct device dev, struct resource *r,
c558e39e AS	146	const struct pwm_lpss_boardinfo *info)
d16a5aa9 MW	147	{
d16a5aa9 MW	148	struct pwm_lpss_chip *lpwm;
d16a5aa9 MW	149	int ret;
d16a5aa9 MW	150
093e00bb	151	lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
d16a5aa9	152	if (!lpwm)
093e00bb	153	return ERR_PTR(-ENOMEM);
d16a5aa9	154
093e00bb	155	lpwm->regs = devm_ioremap_resource(dev, r);
d16a5aa9	156	if (IS_ERR(lpwm->regs))
89c0339e	157	return ERR_CAST(lpwm->regs);
093e00bb	158
65accd87	159	lpwm->clk_rate = info->clk_rate;
093e00bb	160	lpwm->chip.dev = dev;
d16a5aa9 MW	161	lpwm->chip.ops = &pwm_lpss_ops;
d16a5aa9 MW	162	lpwm->chip.base = -1;
4e11f5ac	163	lpwm->chip.npwm = info->npwm;
d16a5aa9 MW	164
	165	ret = pwmchip_add(&lpwm->chip);
	166	if (ret) {
093e00bb AC	167	dev_err(dev, "failed to add PWM chip: %d\n", ret);
093e00bb AC	168	return ERR_PTR(ret);
d16a5aa9 MW	169	}
d16a5aa9 MW	170
093e00bb	171	return lpwm;
d16a5aa9	172	}
c558e39e	173	EXPORT_SYMBOL_GPL(pwm_lpss_probe);
d16a5aa9	174
c558e39e	175	int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
d16a5aa9	176	{
d16a5aa9 MW	177	return pwmchip_remove(&lpwm->chip);
d16a5aa9 MW	178	}
c558e39e	179	EXPORT_SYMBOL_GPL(pwm_lpss_remove);
d16a5aa9 MW	180
	181	MODULE_DESCRIPTION("PWM driver for Intel LPSS");
	182	MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
	183	MODULE_LICENSE("GPL v2");