[deliverable/linux.git] / drivers / pwm / pwm-samsung.c

/* drivers/pwm/pwm-samsung.c
 *
 * Copyright (c) 2007 Ben Dooks
 * Copyright (c) 2008 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
 *
 * S3C series PWM device core
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License.
*/

#define pr_fmt(fmt) "pwm-samsung: " fmt

#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/pwm.h>

#include <mach/map.h>

#include <plat/regs-timer.h>

struct s3c_chip {
	struct platform_device	*pdev;

	struct clk		*clk_div;
	struct clk		*clk;
	const char		*label;

	unsigned int		 period_ns;
	unsigned int		 duty_ns;

	unsigned char		 tcon_base;
	unsigned char		 pwm_id;
	struct pwm_chip		 chip;
};

#define to_s3c_chip(chip)	container_of(chip, struct s3c_chip, chip)

#define pwm_dbg(_pwm, msg...) dev_dbg(&(_pwm)->pdev->dev, msg)

static struct clk *clk_scaler[2];

static inline int pwm_is_tdiv(struct s3c_chip *chip)
{
	return clk_get_parent(chip->clk) == chip->clk_div;
}

#define pwm_tcon_start(pwm) (1 << (pwm->tcon_base + 0))
#define pwm_tcon_invert(pwm) (1 << (pwm->tcon_base + 2))
#define pwm_tcon_autoreload(pwm) (1 << (pwm->tcon_base + 3))
#define pwm_tcon_manulupdate(pwm) (1 << (pwm->tcon_base + 1))

static int s3c_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct s3c_chip *s3c = to_s3c_chip(chip);
	unsigned long flags;
	unsigned long tcon;

	local_irq_save(flags);

	tcon = __raw_readl(S3C2410_TCON);
	tcon |= pwm_tcon_start(s3c);
	__raw_writel(tcon, S3C2410_TCON);

	local_irq_restore(flags);

	return 0;
}

static void s3c_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct s3c_chip *s3c = to_s3c_chip(chip);
	unsigned long flags;
	unsigned long tcon;

	local_irq_save(flags);

	tcon = __raw_readl(S3C2410_TCON);
	tcon &= ~pwm_tcon_start(s3c);
	__raw_writel(tcon, S3C2410_TCON);

	local_irq_restore(flags);
}

static unsigned long pwm_calc_tin(struct s3c_chip *s3c, unsigned long freq)
{
	unsigned long tin_parent_rate;
	unsigned int div;

	tin_parent_rate = clk_get_rate(clk_get_parent(s3c->clk_div));
	pwm_dbg(s3c, "tin parent at %lu\n", tin_parent_rate);

	for (div = 2; div <= 16; div *= 2) {
		if ((tin_parent_rate / (div << 16)) < freq)
			return tin_parent_rate / div;
	}

	return tin_parent_rate / 16;
}

#define NS_IN_HZ (1000000000UL)

static int s3c_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
		int duty_ns, int period_ns)
{
	struct s3c_chip *s3c = to_s3c_chip(chip);
	unsigned long tin_rate;
	unsigned long tin_ns;
	unsigned long period;
	unsigned long flags;
	unsigned long tcon;
	unsigned long tcnt;
	long tcmp;

	/* We currently avoid using 64bit arithmetic by using the
	 * fact that anything faster than 1Hz is easily representable
	 * by 32bits. */

	if (period_ns > NS_IN_HZ || duty_ns > NS_IN_HZ)
		return -ERANGE;

	if (duty_ns > period_ns)
		return -EINVAL;

	if (period_ns == s3c->period_ns &&
	    duty_ns == s3c->duty_ns)
		return 0;

	/* The TCMP and TCNT can be read without a lock, they're not
	 * shared between the timers. */

	tcmp = __raw_readl(S3C2410_TCMPB(s3c->pwm_id));
	tcnt = __raw_readl(S3C2410_TCNTB(s3c->pwm_id));

	period = NS_IN_HZ / period_ns;

	pwm_dbg(s3c, "duty_ns=%d, period_ns=%d (%lu)\n",
		duty_ns, period_ns, period);

	/* Check to see if we are changing the clock rate of the PWM */

	if (s3c->period_ns != period_ns) {
		if (pwm_is_tdiv(s3c)) {
			tin_rate = pwm_calc_tin(s3c, period);
			clk_set_rate(s3c->clk_div, tin_rate);
		} else
			tin_rate = clk_get_rate(s3c->clk);

		s3c->period_ns = period_ns;

		pwm_dbg(s3c, "tin_rate=%lu\n", tin_rate);

		tin_ns = NS_IN_HZ / tin_rate;
		tcnt = period_ns / tin_ns;
	} else
		tin_ns = NS_IN_HZ / clk_get_rate(s3c->clk);

	/* Note, counters count down */

	tcmp = duty_ns / tin_ns;
	tcmp = tcnt - tcmp;
	/* the pwm hw only checks the compare register after a decrement,
	   so the pin never toggles if tcmp = tcnt */
	if (tcmp == tcnt)
		tcmp--;

	pwm_dbg(s3c, "tin_ns=%lu, tcmp=%ld/%lu\n", tin_ns, tcmp, tcnt);

	if (tcmp < 0)
		tcmp = 0;

	/* Update the PWM register block. */

	local_irq_save(flags);

	__raw_writel(tcmp, S3C2410_TCMPB(s3c->pwm_id));
	__raw_writel(tcnt, S3C2410_TCNTB(s3c->pwm_id));

	tcon = __raw_readl(S3C2410_TCON);
	tcon |= pwm_tcon_manulupdate(s3c);
	tcon |= pwm_tcon_autoreload(s3c);
	__raw_writel(tcon, S3C2410_TCON);

	tcon &= ~pwm_tcon_manulupdate(s3c);
	__raw_writel(tcon, S3C2410_TCON);

	local_irq_restore(flags);

	return 0;
}

static struct pwm_ops s3c_pwm_ops = {
	.enable = s3c_pwm_enable,
	.disable = s3c_pwm_disable,
	.config = s3c_pwm_config,
	.owner = THIS_MODULE,
};

static int s3c_pwm_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct s3c_chip *s3c;
	unsigned long flags;
	unsigned long tcon;
	unsigned int id = pdev->id;
	int ret;

	if (id == 4) {
		dev_err(dev, "TIMER4 is currently not supported\n");
		return -ENXIO;
	}

	s3c = devm_kzalloc(&pdev->dev, sizeof(*s3c), GFP_KERNEL);
	if (s3c == NULL) {
		dev_err(dev, "failed to allocate pwm_device\n");
		return -ENOMEM;
	}

	/* calculate base of control bits in TCON */
	s3c->tcon_base = id == 0 ? 0 : (id * 4) + 4;
	s3c->chip.ops = &s3c_pwm_ops;
	s3c->chip.base = -1;
	s3c->chip.npwm = 1;

	s3c->clk = devm_clk_get(dev, "pwm-tin");
	if (IS_ERR(s3c->clk)) {
		dev_err(dev, "failed to get pwm tin clk\n");
		return PTR_ERR(s3c->clk);
	}

	s3c->clk_div = devm_clk_get(dev, "pwm-tdiv");
	if (IS_ERR(s3c->clk_div)) {
		dev_err(dev, "failed to get pwm tdiv clk\n");
		return PTR_ERR(s3c->clk_div);
	}

	clk_enable(s3c->clk);
	clk_enable(s3c->clk_div);

	local_irq_save(flags);

	tcon = __raw_readl(S3C2410_TCON);
	tcon |= pwm_tcon_invert(s3c);
	__raw_writel(tcon, S3C2410_TCON);

	local_irq_restore(flags);

	ret = pwmchip_add(&s3c->chip);
	if (ret < 0) {
		dev_err(dev, "failed to register pwm\n");
		goto err_clk_tdiv;
	}

	pwm_dbg(s3c, "config bits %02x\n",
		(__raw_readl(S3C2410_TCON) >> s3c->tcon_base) & 0x0f);

	dev_info(dev, "tin at %lu, tdiv at %lu, tin=%sclk, base %d\n",
		 clk_get_rate(s3c->clk),
		 clk_get_rate(s3c->clk_div),
		 pwm_is_tdiv(s3c) ? "div" : "ext", s3c->tcon_base);

	platform_set_drvdata(pdev, s3c);
	return 0;

 err_clk_tdiv:
	clk_disable(s3c->clk_div);
	clk_disable(s3c->clk);
	return ret;
}

static int __devexit s3c_pwm_remove(struct platform_device *pdev)
{
	struct s3c_chip *s3c = platform_get_drvdata(pdev);
	int err;

	err = pwmchip_remove(&s3c->chip);
	if (err < 0)
		return err;

	clk_disable(s3c->clk_div);
	clk_disable(s3c->clk);

	return 0;
}

#ifdef CONFIG_PM
static int s3c_pwm_suspend(struct platform_device *pdev, pm_message_t state)
{
	struct s3c_chip *s3c = platform_get_drvdata(pdev);

	/* No one preserve these values during suspend so reset them
	 * Otherwise driver leaves PWM unconfigured if same values
	 * passed to pwm_config
	 */
	s3c->period_ns = 0;
	s3c->duty_ns = 0;

	return 0;
}

static int s3c_pwm_resume(struct platform_device *pdev)
{
	struct s3c_chip *s3c = platform_get_drvdata(pdev);
	unsigned long tcon;

	/* Restore invertion */
	tcon = __raw_readl(S3C2410_TCON);
	tcon |= pwm_tcon_invert(s3c);
	__raw_writel(tcon, S3C2410_TCON);

	return 0;
}

#else
#define s3c_pwm_suspend NULL
#define s3c_pwm_resume NULL
#endif

static struct platform_driver s3c_pwm_driver = {
	.driver		= {
		.name	= "s3c24xx-pwm",
		.owner	= THIS_MODULE,
	},
	.probe		= s3c_pwm_probe,
	.remove		= __devexit_p(s3c_pwm_remove),
	.suspend	= s3c_pwm_suspend,
	.resume		= s3c_pwm_resume,
};

static int __init pwm_init(void)
{
	int ret;

	clk_scaler[0] = clk_get(NULL, "pwm-scaler0");
	clk_scaler[1] = clk_get(NULL, "pwm-scaler1");

	if (IS_ERR(clk_scaler[0]) || IS_ERR(clk_scaler[1])) {
		pr_err("failed to get scaler clocks\n");
		return -EINVAL;
	}

	ret = platform_driver_register(&s3c_pwm_driver);
	if (ret)
		pr_err("failed to add pwm driver\n");

	return ret;
}

arch_initcall(pwm_init);
Commit	Line	Data
6192fa87	1	/* drivers/pwm/pwm-samsung.c
6fc601e3 BD	2	*
	3	* Copyright (c) 2007 Ben Dooks
	4	* Copyright (c) 2008 Simtec Electronics
	5	* Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
	6	*
b5ead1cd	7	* S3C series PWM device core
6fc601e3 BD	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License.
	12	*/
	13
2437b0d9 SK	14	#define pr_fmt(fmt) "pwm-samsung: " fmt
2437b0d9 SK	15
a69e4c28	16	#include <linux/export.h>
6fc601e3 BD	17	#include <linux/kernel.h>
6fc601e3 BD	18	#include <linux/platform_device.h>
5a0e3ad6	19	#include <linux/slab.h>
6fc601e3 BD	20	#include <linux/err.h>
	21	#include <linux/clk.h>
	22	#include <linux/io.h>
	23	#include <linux/pwm.h>
	24
b5ead1cd	25	#include <mach/map.h>
80b02c17	26
a2b7ba9c	27	#include <plat/regs-timer.h>
6fc601e3	28
215c29d3	29	struct s3c_chip {
6fc601e3 BD	30	struct platform_device *pdev;
	31
	32	struct clk *clk_div;
	33	struct clk *clk;
	34	const char *label;
	35
	36	unsigned int period_ns;
	37	unsigned int duty_ns;
	38
	39	unsigned char tcon_base;
6fc601e3	40	unsigned char pwm_id;
215c29d3	41	struct pwm_chip chip;
6fc601e3 BD	42	};
6fc601e3 BD	43
215c29d3 SH	44	#define to_s3c_chip(chip) container_of(chip, struct s3c_chip, chip)
215c29d3 SH	45
66592eee	46	#define pwm_dbg(_pwm, msg...) dev_dbg(&(_pwm)->pdev->dev, msg)
6fc601e3 BD	47
	48	static struct clk *clk_scaler[2];
	49
215c29d3	50	static inline int pwm_is_tdiv(struct s3c_chip *chip)
6fc601e3	51	{
215c29d3	52	return clk_get_parent(chip->clk) == chip->clk_div;
6fc601e3 BD	53	}
6fc601e3 BD	54
6fc601e3 BD	55	#define pwm_tcon_start(pwm) (1 << (pwm->tcon_base + 0))
	56	#define pwm_tcon_invert(pwm) (1 << (pwm->tcon_base + 2))
	57	#define pwm_tcon_autoreload(pwm) (1 << (pwm->tcon_base + 3))
	58	#define pwm_tcon_manulupdate(pwm) (1 << (pwm->tcon_base + 1))
	59
215c29d3	60	static int s3c_pwm_enable(struct pwm_chip chip, struct pwm_device pwm)
6fc601e3	61	{
215c29d3	62	struct s3c_chip *s3c = to_s3c_chip(chip);
6fc601e3 BD	63	unsigned long flags;
	64	unsigned long tcon;
	65
	66	local_irq_save(flags);
	67
	68	tcon = __raw_readl(S3C2410_TCON);
215c29d3	69	tcon \|= pwm_tcon_start(s3c);
6fc601e3 BD	70	__raw_writel(tcon, S3C2410_TCON);
	71
	72	local_irq_restore(flags);
	73
6fc601e3 BD	74	return 0;
	75	}
	76
215c29d3	77	static void s3c_pwm_disable(struct pwm_chip chip, struct pwm_device pwm)
6fc601e3	78	{
215c29d3	79	struct s3c_chip *s3c = to_s3c_chip(chip);
6fc601e3 BD	80	unsigned long flags;
	81	unsigned long tcon;
	82
	83	local_irq_save(flags);
	84
	85	tcon = __raw_readl(S3C2410_TCON);
215c29d3	86	tcon &= ~pwm_tcon_start(s3c);
6fc601e3 BD	87	__raw_writel(tcon, S3C2410_TCON);
	88
	89	local_irq_restore(flags);
6fc601e3 BD	90	}
6fc601e3 BD	91
215c29d3	92	static unsigned long pwm_calc_tin(struct s3c_chip *s3c, unsigned long freq)
6fc601e3 BD	93	{
	94	unsigned long tin_parent_rate;
	95	unsigned int div;
	96
215c29d3 SH	97	tin_parent_rate = clk_get_rate(clk_get_parent(s3c->clk_div));
215c29d3 SH	98	pwm_dbg(s3c, "tin parent at %lu\n", tin_parent_rate);
6fc601e3 BD	99
	100	for (div = 2; div <= 16; div *= 2) {
	101	if ((tin_parent_rate / (div << 16)) < freq)
	102	return tin_parent_rate / div;
	103	}
	104
	105	return tin_parent_rate / 16;
	106	}
	107
	108	#define NS_IN_HZ (1000000000UL)
	109
215c29d3 SH	110	static int s3c_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
215c29d3 SH	111	int duty_ns, int period_ns)
6fc601e3	112	{
215c29d3	113	struct s3c_chip *s3c = to_s3c_chip(chip);
6fc601e3 BD	114	unsigned long tin_rate;
	115	unsigned long tin_ns;
	116	unsigned long period;
	117	unsigned long flags;
	118	unsigned long tcon;
	119	unsigned long tcnt;
	120	long tcmp;
	121
	122	/* We currently avoid using 64bit arithmetic by using the
	123	* fact that anything faster than 1Hz is easily representable
	124	* by 32bits. */
	125
	126	if (period_ns > NS_IN_HZ \|\| duty_ns > NS_IN_HZ)
	127	return -ERANGE;
	128
	129	if (duty_ns > period_ns)
	130	return -EINVAL;
	131
215c29d3 SH	132	if (period_ns == s3c->period_ns &&
215c29d3 SH	133	duty_ns == s3c->duty_ns)
6fc601e3 BD	134	return 0;
	135
	136	/* The TCMP and TCNT can be read without a lock, they're not
	137	* shared between the timers. */
	138
215c29d3 SH	139	tcmp = __raw_readl(S3C2410_TCMPB(s3c->pwm_id));
215c29d3 SH	140	tcnt = __raw_readl(S3C2410_TCNTB(s3c->pwm_id));
6fc601e3 BD	141
	142	period = NS_IN_HZ / period_ns;
	143
215c29d3	144	pwm_dbg(s3c, "duty_ns=%d, period_ns=%d (%lu)\n",
6fc601e3 BD	145	duty_ns, period_ns, period);
	146
	147	/* Check to see if we are changing the clock rate of the PWM */
	148
215c29d3 SH	149	if (s3c->period_ns != period_ns) {
	150	if (pwm_is_tdiv(s3c)) {
	151	tin_rate = pwm_calc_tin(s3c, period);
	152	clk_set_rate(s3c->clk_div, tin_rate);
6fc601e3	153	} else
215c29d3	154	tin_rate = clk_get_rate(s3c->clk);
6fc601e3	155
215c29d3	156	s3c->period_ns = period_ns;
6fc601e3	157
215c29d3	158	pwm_dbg(s3c, "tin_rate=%lu\n", tin_rate);
6fc601e3 BD	159
	160	tin_ns = NS_IN_HZ / tin_rate;
	161	tcnt = period_ns / tin_ns;
	162	} else
215c29d3	163	tin_ns = NS_IN_HZ / clk_get_rate(s3c->clk);
6fc601e3 BD	164
	165	/* Note, counters count down */
	166
	167	tcmp = duty_ns / tin_ns;
	168	tcmp = tcnt - tcmp;
165f5f64 PK	169	/* the pwm hw only checks the compare register after a decrement,
	170	so the pin never toggles if tcmp = tcnt */
	171	if (tcmp == tcnt)
	172	tcmp--;
6fc601e3	173
215c29d3	174	pwm_dbg(s3c, "tin_ns=%lu, tcmp=%ld/%lu\n", tin_ns, tcmp, tcnt);
6fc601e3 BD	175
	176	if (tcmp < 0)
	177	tcmp = 0;
	178
	179	/* Update the PWM register block. */
	180
	181	local_irq_save(flags);
	182
215c29d3 SH	183	__raw_writel(tcmp, S3C2410_TCMPB(s3c->pwm_id));
215c29d3 SH	184	__raw_writel(tcnt, S3C2410_TCNTB(s3c->pwm_id));
6fc601e3 BD	185
6fc601e3 BD	186	tcon = __raw_readl(S3C2410_TCON);
215c29d3 SH	187	tcon \|= pwm_tcon_manulupdate(s3c);
215c29d3 SH	188	tcon \|= pwm_tcon_autoreload(s3c);
6fc601e3 BD	189	__raw_writel(tcon, S3C2410_TCON);
6fc601e3 BD	190
215c29d3	191	tcon &= ~pwm_tcon_manulupdate(s3c);
6fc601e3 BD	192	__raw_writel(tcon, S3C2410_TCON);
	193
	194	local_irq_restore(flags);
	195
	196	return 0;
	197	}
	198
215c29d3 SH	199	static struct pwm_ops s3c_pwm_ops = {
	200	.enable = s3c_pwm_enable,
	201	.disable = s3c_pwm_disable,
	202	.config = s3c_pwm_config,
	203	.owner = THIS_MODULE,
	204	};
6fc601e3 BD	205
	206	static int s3c_pwm_probe(struct platform_device *pdev)
	207	{
	208	struct device *dev = &pdev->dev;
215c29d3	209	struct s3c_chip *s3c;
6fc601e3 BD	210	unsigned long flags;
	211	unsigned long tcon;
	212	unsigned int id = pdev->id;
	213	int ret;
	214
	215	if (id == 4) {
	216	dev_err(dev, "TIMER4 is currently not supported\n");
	217	return -ENXIO;
	218	}
	219
6192fa87	220	s3c = devm_kzalloc(&pdev->dev, sizeof(*s3c), GFP_KERNEL);
215c29d3	221	if (s3c == NULL) {
6fc601e3 BD	222	dev_err(dev, "failed to allocate pwm_device\n");
	223	return -ENOMEM;
	224	}
	225
6fc601e3	226	/* calculate base of control bits in TCON */
215c29d3 SH	227	s3c->tcon_base = id == 0 ? 0 : (id * 4) + 4;
	228	s3c->chip.ops = &s3c_pwm_ops;
	229	s3c->chip.base = -1;
	230	s3c->chip.npwm = 1;
6fc601e3	231
6192fa87	232	s3c->clk = devm_clk_get(dev, "pwm-tin");
215c29d3	233	if (IS_ERR(s3c->clk)) {
6fc601e3	234	dev_err(dev, "failed to get pwm tin clk\n");
6192fa87	235	return PTR_ERR(s3c->clk);
6fc601e3 BD	236	}
6fc601e3 BD	237
6192fa87	238	s3c->clk_div = devm_clk_get(dev, "pwm-tdiv");
215c29d3	239	if (IS_ERR(s3c->clk_div)) {
6fc601e3	240	dev_err(dev, "failed to get pwm tdiv clk\n");
6192fa87	241	return PTR_ERR(s3c->clk_div);
6fc601e3 BD	242	}
6fc601e3 BD	243
215c29d3 SH	244	clk_enable(s3c->clk);
215c29d3 SH	245	clk_enable(s3c->clk_div);
d8633c1d	246
6fc601e3 BD	247	local_irq_save(flags);
	248
	249	tcon = __raw_readl(S3C2410_TCON);
215c29d3	250	tcon \|= pwm_tcon_invert(s3c);
6fc601e3 BD	251	__raw_writel(tcon, S3C2410_TCON);
	252
	253	local_irq_restore(flags);
	254
215c29d3 SH	255	ret = pwmchip_add(&s3c->chip);
215c29d3 SH	256	if (ret < 0) {
6fc601e3 BD	257	dev_err(dev, "failed to register pwm\n");
	258	goto err_clk_tdiv;
	259	}
	260
215c29d3 SH	261	pwm_dbg(s3c, "config bits %02x\n",
215c29d3 SH	262	(__raw_readl(S3C2410_TCON) >> s3c->tcon_base) & 0x0f);
6fc601e3 BD	263
6fc601e3 BD	264	dev_info(dev, "tin at %lu, tdiv at %lu, tin=%sclk, base %d\n",
215c29d3 SH	265	clk_get_rate(s3c->clk),
	266	clk_get_rate(s3c->clk_div),
	267	pwm_is_tdiv(s3c) ? "div" : "ext", s3c->tcon_base);
6fc601e3	268
215c29d3	269	platform_set_drvdata(pdev, s3c);
6fc601e3 BD	270	return 0;
	271
	272	err_clk_tdiv:
215c29d3 SH	273	clk_disable(s3c->clk_div);
215c29d3 SH	274	clk_disable(s3c->clk);
6fc601e3 BD	275	return ret;
	276	}
	277
93b0d8c6	278	static int __devexit s3c_pwm_remove(struct platform_device *pdev)
6fc601e3	279	{
215c29d3 SH	280	struct s3c_chip *s3c = platform_get_drvdata(pdev);
	281	int err;
	282
	283	err = pwmchip_remove(&s3c->chip);
	284	if (err < 0)
	285	return err;
6fc601e3	286
215c29d3 SH	287	clk_disable(s3c->clk_div);
215c29d3 SH	288	clk_disable(s3c->clk);
6fc601e3 BD	289
	290	return 0;
	291	}
	292
e79032aa VK	293	#ifdef CONFIG_PM
	294	static int s3c_pwm_suspend(struct platform_device *pdev, pm_message_t state)
	295	{
215c29d3	296	struct s3c_chip *s3c = platform_get_drvdata(pdev);
e79032aa VK	297
	298	/* No one preserve these values during suspend so reset them
	299	* Otherwise driver leaves PWM unconfigured if same values
	300	* passed to pwm_config
	301	*/
215c29d3 SH	302	s3c->period_ns = 0;
215c29d3 SH	303	s3c->duty_ns = 0;
e79032aa VK	304
	305	return 0;
	306	}
	307
	308	static int s3c_pwm_resume(struct platform_device *pdev)
	309	{
215c29d3	310	struct s3c_chip *s3c = platform_get_drvdata(pdev);
e79032aa VK	311	unsigned long tcon;
	312
	313	/* Restore invertion */
	314	tcon = __raw_readl(S3C2410_TCON);
215c29d3	315	tcon \|= pwm_tcon_invert(s3c);
e79032aa VK	316	__raw_writel(tcon, S3C2410_TCON);
	317
	318	return 0;
	319	}
	320
	321	#else
	322	#define s3c_pwm_suspend NULL
	323	#define s3c_pwm_resume NULL
	324	#endif
	325
6fc601e3 BD	326	static struct platform_driver s3c_pwm_driver = {
	327	.driver = {
	328	.name = "s3c24xx-pwm",
	329	.owner = THIS_MODULE,
	330	},
	331	.probe = s3c_pwm_probe,
	332	.remove = __devexit_p(s3c_pwm_remove),
e79032aa VK	333	.suspend = s3c_pwm_suspend,
e79032aa VK	334	.resume = s3c_pwm_resume,
6fc601e3 BD	335	};
	336
	337	static int __init pwm_init(void)
	338	{
	339	int ret;
	340
	341	clk_scaler[0] = clk_get(NULL, "pwm-scaler0");
	342	clk_scaler[1] = clk_get(NULL, "pwm-scaler1");
	343
	344	if (IS_ERR(clk_scaler[0]) \|\| IS_ERR(clk_scaler[1])) {
2437b0d9	345	pr_err("failed to get scaler clocks\n");
6fc601e3 BD	346	return -EINVAL;
	347	}
	348
	349	ret = platform_driver_register(&s3c_pwm_driver);
	350	if (ret)
2437b0d9	351	pr_err("failed to add pwm driver\n");
6fc601e3 BD	352
	353	return ret;
	354	}
	355
	356	arch_initcall(pwm_init);