[deliverable/linux.git] / drivers / rapidio / switches / idt_gen2.c

/*
 * IDT CPS Gen.2 Serial RapidIO switch family support
 *
 * Copyright 2010 Integrated Device Technology, Inc.
 * Alexandre Bounine <alexandre.bounine@idt.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/rio.h>
#include <linux/rio_drv.h>
#include <linux/rio_ids.h>
#include <linux/delay.h>
#include "../rio.h"

#define LOCAL_RTE_CONF_DESTID_SEL	0x010070
#define LOCAL_RTE_CONF_DESTID_SEL_PSEL	0x0000001f

#define IDT_LT_ERR_REPORT_EN	0x03100c

#define IDT_PORT_ERR_REPORT_EN(n)	(0x031044 + (n)*0x40)
#define IDT_PORT_ERR_REPORT_EN_BC	0x03ff04

#define IDT_PORT_ISERR_REPORT_EN(n)	(0x03104C + (n)*0x40)
#define IDT_PORT_ISERR_REPORT_EN_BC	0x03ff0c
#define IDT_PORT_INIT_TX_ACQUIRED	0x00000020

#define IDT_LANE_ERR_REPORT_EN(n)	(0x038010 + (n)*0x100)
#define IDT_LANE_ERR_REPORT_EN_BC	0x03ff10

#define IDT_DEV_CTRL_1		0xf2000c
#define IDT_DEV_CTRL_1_GENPW		0x02000000
#define IDT_DEV_CTRL_1_PRSTBEH		0x00000001

#define IDT_CFGBLK_ERR_CAPTURE_EN	0x020008
#define IDT_CFGBLK_ERR_REPORT		0xf20014
#define IDT_CFGBLK_ERR_REPORT_GENPW		0x00000002

#define IDT_AUX_PORT_ERR_CAP_EN	0x020000
#define IDT_AUX_ERR_REPORT_EN	0xf20018
#define IDT_AUX_PORT_ERR_LOG_I2C	0x00000002
#define IDT_AUX_PORT_ERR_LOG_JTAG	0x00000001

#define	IDT_ISLTL_ADDRESS_CAP	0x021014

#define IDT_RIO_DOMAIN		0xf20020
#define IDT_RIO_DOMAIN_MASK		0x000000ff

#define IDT_PW_INFO_CSR		0xf20024

#define IDT_SOFT_RESET		0xf20040
#define IDT_SOFT_RESET_REQ		0x00030097

#define IDT_I2C_MCTRL		0xf20050
#define IDT_I2C_MCTRL_GENPW		0x04000000

#define IDT_JTAG_CTRL		0xf2005c
#define IDT_JTAG_CTRL_GENPW		0x00000002

#define IDT_LANE_CTRL(n)	(0xff8000 + (n)*0x100)
#define IDT_LANE_CTRL_BC	0xffff00
#define IDT_LANE_CTRL_GENPW		0x00200000
#define IDT_LANE_DFE_1_BC	0xffff18
#define IDT_LANE_DFE_2_BC	0xffff1c

#define IDT_PORT_OPS(n)		(0xf40004 + (n)*0x100)
#define IDT_PORT_OPS_GENPW		0x08000000
#define IDT_PORT_OPS_PL_ELOG		0x00000040
#define IDT_PORT_OPS_LL_ELOG		0x00000020
#define IDT_PORT_OPS_LT_ELOG		0x00000010
#define IDT_PORT_OPS_BC		0xf4ff04

#define IDT_PORT_ISERR_DET(n)	(0xf40008 + (n)*0x100)

#define IDT_ERR_CAP		0xfd0000
#define IDT_ERR_CAP_LOG_OVERWR		0x00000004

#define IDT_ERR_RD		0xfd0004

#define IDT_DEFAULT_ROUTE	0xde
#define IDT_NO_ROUTE		0xdf

static int
idtg2_route_add_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
		       u16 table, u16 route_destid, u8 route_port)
{
	/*
	 * Select routing table to update
	 */
	if (table == RIO_GLOBAL_TABLE)
		table = 0;
	else
		table++;

	if (route_port == RIO_INVALID_ROUTE)
		route_port = IDT_DEFAULT_ROUTE;

	rio_mport_write_config_32(mport, destid, hopcount,
				  LOCAL_RTE_CONF_DESTID_SEL, table);

	/*
	 * Program destination port for the specified destID
	 */
	rio_mport_write_config_32(mport, destid, hopcount,
				  RIO_STD_RTE_CONF_DESTID_SEL_CSR,
				  (u32)route_destid);

	rio_mport_write_config_32(mport, destid, hopcount,
				  RIO_STD_RTE_CONF_PORT_SEL_CSR,
				  (u32)route_port);
	udelay(10);

	return 0;
}

static int
idtg2_route_get_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
		       u16 table, u16 route_destid, u8 *route_port)
{
	u32 result;

	/*
	 * Select routing table to read
	 */
	if (table == RIO_GLOBAL_TABLE)
		table = 0;
	else
		table++;

	rio_mport_write_config_32(mport, destid, hopcount,
				  LOCAL_RTE_CONF_DESTID_SEL, table);

	rio_mport_write_config_32(mport, destid, hopcount,
				  RIO_STD_RTE_CONF_DESTID_SEL_CSR,
				  route_destid);

	rio_mport_read_config_32(mport, destid, hopcount,
				 RIO_STD_RTE_CONF_PORT_SEL_CSR, &result);

	if (IDT_DEFAULT_ROUTE == (u8)result || IDT_NO_ROUTE == (u8)result)
		*route_port = RIO_INVALID_ROUTE;
	else
		*route_port = (u8)result;

	return 0;
}

static int
idtg2_route_clr_table(struct rio_mport *mport, u16 destid, u8 hopcount,
		       u16 table)
{
	u32 i;

	/*
	 * Select routing table to read
	 */
	if (table == RIO_GLOBAL_TABLE)
		table = 0;
	else
		table++;

	rio_mport_write_config_32(mport, destid, hopcount,
				  LOCAL_RTE_CONF_DESTID_SEL, table);

	for (i = RIO_STD_RTE_CONF_EXTCFGEN;
	     i <= (RIO_STD_RTE_CONF_EXTCFGEN | 0xff);) {
		rio_mport_write_config_32(mport, destid, hopcount,
			RIO_STD_RTE_CONF_DESTID_SEL_CSR, i);
		rio_mport_write_config_32(mport, destid, hopcount,
			RIO_STD_RTE_CONF_PORT_SEL_CSR,
			(IDT_DEFAULT_ROUTE << 24) | (IDT_DEFAULT_ROUTE << 16) |
			(IDT_DEFAULT_ROUTE << 8) | IDT_DEFAULT_ROUTE);
		i += 4;
	}

	return 0;
}


static int
idtg2_set_domain(struct rio_mport *mport, u16 destid, u8 hopcount,
		       u8 sw_domain)
{
	/*
	 * Switch domain configuration operates only at global level
	 */
	rio_mport_write_config_32(mport, destid, hopcount,
				  IDT_RIO_DOMAIN, (u32)sw_domain);
	return 0;
}

static int
idtg2_get_domain(struct rio_mport *mport, u16 destid, u8 hopcount,
		       u8 *sw_domain)
{
	u32 regval;

	/*
	 * Switch domain configuration operates only at global level
	 */
	rio_mport_read_config_32(mport, destid, hopcount,
				IDT_RIO_DOMAIN, &regval);

	*sw_domain = (u8)(regval & 0xff);

	return 0;
}

static int
idtg2_em_init(struct rio_dev *rdev)
{
	u32 regval;
	int i, tmp;

	/*
	 * This routine performs device-specific initialization only.
	 * All standard EM configuration should be performed at upper level.
	 */

	pr_debug("RIO: %s [%d:%d]\n", __func__, rdev->destid, rdev->hopcount);

	/* Set Port-Write info CSR: PRIO=3 and CRF=1 */
	rio_write_config_32(rdev, IDT_PW_INFO_CSR, 0x0000e000);

	/*
	 * Configure LT LAYER error reporting.
	 */

	/* Enable standard (RIO.p8) error reporting */
	rio_write_config_32(rdev, IDT_LT_ERR_REPORT_EN,
			REM_LTL_ERR_ILLTRAN | REM_LTL_ERR_UNSOLR |
			REM_LTL_ERR_UNSUPTR);

	/* Use Port-Writes for LT layer error reporting.
	 * Enable per-port reset
	 */
	rio_read_config_32(rdev, IDT_DEV_CTRL_1, &regval);
	rio_write_config_32(rdev, IDT_DEV_CTRL_1,
			regval | IDT_DEV_CTRL_1_GENPW | IDT_DEV_CTRL_1_PRSTBEH);

	/*
	 * Configure PORT error reporting.
	 */

	/* Report all RIO.p8 errors supported by device */
	rio_write_config_32(rdev, IDT_PORT_ERR_REPORT_EN_BC, 0x807e8037);

	/* Configure reporting of implementation specific errors/events */
	rio_write_config_32(rdev, IDT_PORT_ISERR_REPORT_EN_BC,
			    IDT_PORT_INIT_TX_ACQUIRED);

	/* Use Port-Writes for port error reporting and enable error logging */
	tmp = RIO_GET_TOTAL_PORTS(rdev->swpinfo);
	for (i = 0; i < tmp; i++) {
		rio_read_config_32(rdev, IDT_PORT_OPS(i), &regval);
		rio_write_config_32(rdev,
				IDT_PORT_OPS(i), regval | IDT_PORT_OPS_GENPW |
				IDT_PORT_OPS_PL_ELOG |
				IDT_PORT_OPS_LL_ELOG |
				IDT_PORT_OPS_LT_ELOG);
	}
	/* Overwrite error log if full */
	rio_write_config_32(rdev, IDT_ERR_CAP, IDT_ERR_CAP_LOG_OVERWR);

	/*
	 * Configure LANE error reporting.
	 */

	/* Disable line error reporting */
	rio_write_config_32(rdev, IDT_LANE_ERR_REPORT_EN_BC, 0);

	/* Use Port-Writes for lane error reporting (when enabled)
	 * (do per-lane update because lanes may have different configuration)
	 */
	tmp = (rdev->did == RIO_DID_IDTCPS1848) ? 48 : 16;
	for (i = 0; i < tmp; i++) {
		rio_read_config_32(rdev, IDT_LANE_CTRL(i), &regval);
		rio_write_config_32(rdev, IDT_LANE_CTRL(i),
				    regval | IDT_LANE_CTRL_GENPW);
	}

	/*
	 * Configure AUX error reporting.
	 */

	/* Disable JTAG and I2C Error capture */
	rio_write_config_32(rdev, IDT_AUX_PORT_ERR_CAP_EN, 0);

	/* Disable JTAG and I2C Error reporting/logging */
	rio_write_config_32(rdev, IDT_AUX_ERR_REPORT_EN, 0);

	/* Disable Port-Write notification from JTAG */
	rio_write_config_32(rdev, IDT_JTAG_CTRL, 0);

	/* Disable Port-Write notification from I2C */
	rio_read_config_32(rdev, IDT_I2C_MCTRL, &regval);
	rio_write_config_32(rdev, IDT_I2C_MCTRL, regval & ~IDT_I2C_MCTRL_GENPW);

	/*
	 * Configure CFG_BLK error reporting.
	 */

	/* Disable Configuration Block error capture */
	rio_write_config_32(rdev, IDT_CFGBLK_ERR_CAPTURE_EN, 0);

	/* Disable Port-Writes for Configuration Block error reporting */
	rio_read_config_32(rdev, IDT_CFGBLK_ERR_REPORT, &regval);
	rio_write_config_32(rdev, IDT_CFGBLK_ERR_REPORT,
			    regval & ~IDT_CFGBLK_ERR_REPORT_GENPW);

	/* set TVAL = ~50us */
	rio_write_config_32(rdev,
		rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x8e << 8);

	return 0;
}

static int
idtg2_em_handler(struct rio_dev *rdev, u8 portnum)
{
	u32 regval, em_perrdet, em_ltlerrdet;

	rio_read_config_32(rdev,
		rdev->em_efptr + RIO_EM_LTL_ERR_DETECT, &em_ltlerrdet);
	if (em_ltlerrdet) {
		/* Service Logical/Transport Layer Error(s) */
		if (em_ltlerrdet & REM_LTL_ERR_IMPSPEC) {
			/* Implementation specific error reported */
			rio_read_config_32(rdev,
					IDT_ISLTL_ADDRESS_CAP, &regval);

			pr_debug("RIO: %s Implementation Specific LTL errors" \
				 " 0x%x @(0x%x)\n",
				 rio_name(rdev), em_ltlerrdet, regval);

			/* Clear implementation specific address capture CSR */
			rio_write_config_32(rdev, IDT_ISLTL_ADDRESS_CAP, 0);

		}
	}

	rio_read_config_32(rdev,
		rdev->em_efptr + RIO_EM_PN_ERR_DETECT(portnum), &em_perrdet);
	if (em_perrdet) {
		/* Service Port-Level Error(s) */
		if (em_perrdet & REM_PED_IMPL_SPEC) {
			/* Implementation Specific port error reported */

			/* Get IS errors reported */
			rio_read_config_32(rdev,
					IDT_PORT_ISERR_DET(portnum), &regval);

			pr_debug("RIO: %s Implementation Specific Port" \
				 " errors 0x%x\n", rio_name(rdev), regval);

			/* Clear all implementation specific events */
			rio_write_config_32(rdev,
					IDT_PORT_ISERR_DET(portnum), 0);
		}
	}

	return 0;
}

static ssize_t
idtg2_show_errlog(struct device *dev, struct device_attribute *attr, char *buf)
{
	struct rio_dev *rdev = to_rio_dev(dev);
	ssize_t len = 0;
	u32 regval;

	while (!rio_read_config_32(rdev, IDT_ERR_RD, &regval)) {
		if (!regval)    /* 0 = end of log */
			break;
		len += snprintf(buf + len, PAGE_SIZE - len,
					"%08x\n", regval);
		if (len >= (PAGE_SIZE - 10))
			break;
	}

	return len;
}

static DEVICE_ATTR(errlog, S_IRUGO, idtg2_show_errlog, NULL);

static int idtg2_sysfs(struct rio_dev *rdev, int create)
{
	struct device *dev = &rdev->dev;
	int err = 0;

	if (create == RIO_SW_SYSFS_CREATE) {
		/* Initialize sysfs entries */
		err = device_create_file(dev, &dev_attr_errlog);
		if (err)
			dev_err(dev, "Unable create sysfs errlog file\n");
	} else
		device_remove_file(dev, &dev_attr_errlog);

	return err;
}

static int idtg2_switch_init(struct rio_dev *rdev, int do_enum)
{
	pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev));
	rdev->rswitch->add_entry = idtg2_route_add_entry;
	rdev->rswitch->get_entry = idtg2_route_get_entry;
	rdev->rswitch->clr_table = idtg2_route_clr_table;
	rdev->rswitch->set_domain = idtg2_set_domain;
	rdev->rswitch->get_domain = idtg2_get_domain;
	rdev->rswitch->em_init = idtg2_em_init;
	rdev->rswitch->em_handle = idtg2_em_handler;
	rdev->rswitch->sw_sysfs = idtg2_sysfs;

	if (do_enum) {
		/* Ensure that default routing is disabled on startup */
		rio_write_config_32(rdev,
				    RIO_STD_RTE_DEFAULT_PORT, IDT_NO_ROUTE);
	}

	return 0;
}

DECLARE_RIO_SWITCH_INIT(RIO_VID_IDT, RIO_DID_IDTCPS1848, idtg2_switch_init);
DECLARE_RIO_SWITCH_INIT(RIO_VID_IDT, RIO_DID_IDTCPS1616, idtg2_switch_init);
DECLARE_RIO_SWITCH_INIT(RIO_VID_IDT, RIO_DID_IDTVPS1616, idtg2_switch_init);
DECLARE_RIO_SWITCH_INIT(RIO_VID_IDT, RIO_DID_IDTSPS1616, idtg2_switch_init);
DECLARE_RIO_SWITCH_INIT(RIO_VID_IDT, RIO_DID_IDTCPS1432, idtg2_switch_init);
Commit	Line	Data
a3725c45 AB	1	/*
	2	* IDT CPS Gen.2 Serial RapidIO switch family support
	3	*
	4	* Copyright 2010 Integrated Device Technology, Inc.
	5	* Alexandre Bounine <alexandre.bounine@idt.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or (at your
	10	* option) any later version.
	11	*/
	12
	13	#include <linux/rio.h>
	14	#include <linux/rio_drv.h>
	15	#include <linux/rio_ids.h>
	16	#include <linux/delay.h>
	17	#include "../rio.h"
	18
	19	#define LOCAL_RTE_CONF_DESTID_SEL 0x010070
	20	#define LOCAL_RTE_CONF_DESTID_SEL_PSEL 0x0000001f
	21
	22	#define IDT_LT_ERR_REPORT_EN 0x03100c
	23
	24	#define IDT_PORT_ERR_REPORT_EN(n) (0x031044 + (n)*0x40)
	25	#define IDT_PORT_ERR_REPORT_EN_BC 0x03ff04
	26
	27	#define IDT_PORT_ISERR_REPORT_EN(n) (0x03104C + (n)*0x40)
	28	#define IDT_PORT_ISERR_REPORT_EN_BC 0x03ff0c
	29	#define IDT_PORT_INIT_TX_ACQUIRED 0x00000020
	30
	31	#define IDT_LANE_ERR_REPORT_EN(n) (0x038010 + (n)*0x100)
	32	#define IDT_LANE_ERR_REPORT_EN_BC 0x03ff10
	33
	34	#define IDT_DEV_CTRL_1 0xf2000c
	35	#define IDT_DEV_CTRL_1_GENPW 0x02000000
	36	#define IDT_DEV_CTRL_1_PRSTBEH 0x00000001
	37
	38	#define IDT_CFGBLK_ERR_CAPTURE_EN 0x020008
	39	#define IDT_CFGBLK_ERR_REPORT 0xf20014
	40	#define IDT_CFGBLK_ERR_REPORT_GENPW 0x00000002
	41
	42	#define IDT_AUX_PORT_ERR_CAP_EN 0x020000
	43	#define IDT_AUX_ERR_REPORT_EN 0xf20018
	44	#define IDT_AUX_PORT_ERR_LOG_I2C 0x00000002
	45	#define IDT_AUX_PORT_ERR_LOG_JTAG 0x00000001
	46
	47	#define IDT_ISLTL_ADDRESS_CAP 0x021014
	48
	49	#define IDT_RIO_DOMAIN 0xf20020
	50	#define IDT_RIO_DOMAIN_MASK 0x000000ff
	51
	52	#define IDT_PW_INFO_CSR 0xf20024
	53
	54	#define IDT_SOFT_RESET 0xf20040
	55	#define IDT_SOFT_RESET_REQ 0x00030097
	56
	57	#define IDT_I2C_MCTRL 0xf20050
	58	#define IDT_I2C_MCTRL_GENPW 0x04000000
	59
	60	#define IDT_JTAG_CTRL 0xf2005c
	61	#define IDT_JTAG_CTRL_GENPW 0x00000002
	62
	63	#define IDT_LANE_CTRL(n) (0xff8000 + (n)*0x100)
	64	#define IDT_LANE_CTRL_BC 0xffff00
65	#define IDT_LANE_CTRL_GENPW 0x00200000
66	#define IDT_LANE_DFE_1_BC 0xffff18
67	#define IDT_LANE_DFE_2_BC 0xffff1c
68
69	#define IDT_PORT_OPS(n) (0xf40004 + (n)*0x100)
70	#define IDT_PORT_OPS_GENPW 0x08000000
71	#define IDT_PORT_OPS_PL_ELOG 0x00000040
72	#define IDT_PORT_OPS_LL_ELOG 0x00000020
73	#define IDT_PORT_OPS_LT_ELOG 0x00000010
74	#define IDT_PORT_OPS_BC 0xf4ff04
75
76	#define IDT_PORT_ISERR_DET(n) (0xf40008 + (n)*0x100)
77
78	#define IDT_ERR_CAP 0xfd0000
79	#define IDT_ERR_CAP_LOG_OVERWR 0x00000004
80
81	#define IDT_ERR_RD 0xfd0004
82
83	#define IDT_DEFAULT_ROUTE 0xde
84	#define IDT_NO_ROUTE 0xdf
85
86	static int
87	idtg2_route_add_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
88	u16 table, u16 route_destid, u8 route_port)
89	{
90	/*
91	* Select routing table to update
92	*/
93	if (table == RIO_GLOBAL_TABLE)
94	table = 0;
95	else
96	table++;
97
0bf2461f AB	98	if (route_port == RIO_INVALID_ROUTE)
	99	route_port = IDT_DEFAULT_ROUTE;
	100
a3725c45 AB	101	rio_mport_write_config_32(mport, destid, hopcount,
	102	LOCAL_RTE_CONF_DESTID_SEL, table);
	103
	104	/*
	105	* Program destination port for the specified destID
	106	*/
	107	rio_mport_write_config_32(mport, destid, hopcount,
	108	RIO_STD_RTE_CONF_DESTID_SEL_CSR,
	109	(u32)route_destid);
	110
	111	rio_mport_write_config_32(mport, destid, hopcount,
	112	RIO_STD_RTE_CONF_PORT_SEL_CSR,
	113	(u32)route_port);
	114	udelay(10);
	115
	116	return 0;
	117	}
	118
	119	static int
	120	idtg2_route_get_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
	121	u16 table, u16 route_destid, u8 *route_port)
	122	{
	123	u32 result;
	124
	125	/*
	126	* Select routing table to read
	127	*/
	128	if (table == RIO_GLOBAL_TABLE)
	129	table = 0;
	130	else
	131	table++;
	132
	133	rio_mport_write_config_32(mport, destid, hopcount,
	134	LOCAL_RTE_CONF_DESTID_SEL, table);
	135
	136	rio_mport_write_config_32(mport, destid, hopcount,
	137	RIO_STD_RTE_CONF_DESTID_SEL_CSR,
	138	route_destid);
	139
	140	rio_mport_read_config_32(mport, destid, hopcount,
	141	RIO_STD_RTE_CONF_PORT_SEL_CSR, &result);
	142
	143	if (IDT_DEFAULT_ROUTE == (u8)result \|\| IDT_NO_ROUTE == (u8)result)
	144	*route_port = RIO_INVALID_ROUTE;
	145	else
	146	*route_port = (u8)result;
	147
	148	return 0;
	149	}
	150
	151	static int
	152	idtg2_route_clr_table(struct rio_mport *mport, u16 destid, u8 hopcount,
	153	u16 table)
	154	{
	155	u32 i;
	156
	157	/*
	158	* Select routing table to read
	159	*/
	160	if (table == RIO_GLOBAL_TABLE)
	161	table = 0;
	162	else
	163	table++;
	164
165	rio_mport_write_config_32(mport, destid, hopcount,
166	LOCAL_RTE_CONF_DESTID_SEL, table);
167
168	for (i = RIO_STD_RTE_CONF_EXTCFGEN;
169	i <= (RIO_STD_RTE_CONF_EXTCFGEN \| 0xff);) {
170	rio_mport_write_config_32(mport, destid, hopcount,
171	RIO_STD_RTE_CONF_DESTID_SEL_CSR, i);
172	rio_mport_write_config_32(mport, destid, hopcount,
173	RIO_STD_RTE_CONF_PORT_SEL_CSR,
174	(IDT_DEFAULT_ROUTE << 24) \| (IDT_DEFAULT_ROUTE << 16) \|
175	(IDT_DEFAULT_ROUTE << 8) \| IDT_DEFAULT_ROUTE);
176	i += 4;
177	}
178
179	return 0;
180	}
181
182
183	static int
184	idtg2_set_domain(struct rio_mport *mport, u16 destid, u8 hopcount,
185	u8 sw_domain)
186	{
187	/*
188	* Switch domain configuration operates only at global level
189	*/
190	rio_mport_write_config_32(mport, destid, hopcount,
191	IDT_RIO_DOMAIN, (u32)sw_domain);
192	return 0;
193	}
194
195	static int
196	idtg2_get_domain(struct rio_mport *mport, u16 destid, u8 hopcount,
197	u8 *sw_domain)
198	{
199	u32 regval;
200
201	/*
202	* Switch domain configuration operates only at global level
203	*/
204	rio_mport_read_config_32(mport, destid, hopcount,
205	IDT_RIO_DOMAIN, &regval);
206
207	*sw_domain = (u8)(regval & 0xff);
208
209	return 0;
210	}
211
212	static int
213	idtg2_em_init(struct rio_dev *rdev)
214	{
a3725c45 AB	215	u32 regval;
	216	int i, tmp;
	217
	218	/*
	219	* This routine performs device-specific initialization only.
	220	* All standard EM configuration should be performed at upper level.
	221	*/
	222
a93192a5	223	pr_debug("RIO: %s [%d:%d]\n", __func__, rdev->destid, rdev->hopcount);
a3725c45 AB	224
a3725c45 AB	225	/* Set Port-Write info CSR: PRIO=3 and CRF=1 */
a93192a5	226	rio_write_config_32(rdev, IDT_PW_INFO_CSR, 0x0000e000);
a3725c45 AB	227
	228	/*
	229	* Configure LT LAYER error reporting.
	230	*/
	231
	232	/* Enable standard (RIO.p8) error reporting */
a93192a5	233	rio_write_config_32(rdev, IDT_LT_ERR_REPORT_EN,
a3725c45 AB	234	REM_LTL_ERR_ILLTRAN \| REM_LTL_ERR_UNSOLR \|
	235	REM_LTL_ERR_UNSUPTR);
	236
	237	/* Use Port-Writes for LT layer error reporting.
	238	* Enable per-port reset
	239	*/
a93192a5 AB	240	rio_read_config_32(rdev, IDT_DEV_CTRL_1, &regval);
a93192a5 AB	241	rio_write_config_32(rdev, IDT_DEV_CTRL_1,
a3725c45 AB	242	regval \| IDT_DEV_CTRL_1_GENPW \| IDT_DEV_CTRL_1_PRSTBEH);
	243
	244	/*
	245	* Configure PORT error reporting.
	246	*/
	247
	248	/* Report all RIO.p8 errors supported by device */
a93192a5	249	rio_write_config_32(rdev, IDT_PORT_ERR_REPORT_EN_BC, 0x807e8037);
a3725c45 AB	250
a3725c45 AB	251	/* Configure reporting of implementation specific errors/events */
a93192a5 AB	252	rio_write_config_32(rdev, IDT_PORT_ISERR_REPORT_EN_BC,
a93192a5 AB	253	IDT_PORT_INIT_TX_ACQUIRED);
a3725c45 AB	254
	255	/* Use Port-Writes for port error reporting and enable error logging */
	256	tmp = RIO_GET_TOTAL_PORTS(rdev->swpinfo);
	257	for (i = 0; i < tmp; i++) {
a93192a5 AB	258	rio_read_config_32(rdev, IDT_PORT_OPS(i), &regval);
a93192a5 AB	259	rio_write_config_32(rdev,
a3725c45 AB	260	IDT_PORT_OPS(i), regval \| IDT_PORT_OPS_GENPW \|
	261	IDT_PORT_OPS_PL_ELOG \|
	262	IDT_PORT_OPS_LL_ELOG \|
	263	IDT_PORT_OPS_LT_ELOG);
	264	}
	265	/* Overwrite error log if full */
a93192a5	266	rio_write_config_32(rdev, IDT_ERR_CAP, IDT_ERR_CAP_LOG_OVERWR);
a3725c45 AB	267
	268	/*
	269	* Configure LANE error reporting.
	270	*/
	271
	272	/* Disable line error reporting */
a93192a5	273	rio_write_config_32(rdev, IDT_LANE_ERR_REPORT_EN_BC, 0);
a3725c45 AB	274
	275	/* Use Port-Writes for lane error reporting (when enabled)
	276	* (do per-lane update because lanes may have different configuration)
	277	*/
	278	tmp = (rdev->did == RIO_DID_IDTCPS1848) ? 48 : 16;
	279	for (i = 0; i < tmp; i++) {
a93192a5 AB	280	rio_read_config_32(rdev, IDT_LANE_CTRL(i), &regval);
	281	rio_write_config_32(rdev, IDT_LANE_CTRL(i),
	282	regval \| IDT_LANE_CTRL_GENPW);
a3725c45 AB	283	}
	284
	285	/*
	286	* Configure AUX error reporting.
	287	*/
	288
	289	/* Disable JTAG and I2C Error capture */
a93192a5	290	rio_write_config_32(rdev, IDT_AUX_PORT_ERR_CAP_EN, 0);
a3725c45 AB	291
a3725c45 AB	292	/* Disable JTAG and I2C Error reporting/logging */
a93192a5	293	rio_write_config_32(rdev, IDT_AUX_ERR_REPORT_EN, 0);
a3725c45 AB	294
a3725c45 AB	295	/* Disable Port-Write notification from JTAG */
a93192a5	296	rio_write_config_32(rdev, IDT_JTAG_CTRL, 0);
a3725c45 AB	297
a3725c45 AB	298	/* Disable Port-Write notification from I2C */
a93192a5 AB	299	rio_read_config_32(rdev, IDT_I2C_MCTRL, &regval);
a93192a5 AB	300	rio_write_config_32(rdev, IDT_I2C_MCTRL, regval & ~IDT_I2C_MCTRL_GENPW);
a3725c45 AB	301
	302	/*
	303	* Configure CFG_BLK error reporting.
	304	*/
	305
	306	/* Disable Configuration Block error capture */
a93192a5	307	rio_write_config_32(rdev, IDT_CFGBLK_ERR_CAPTURE_EN, 0);
a3725c45 AB	308
a3725c45 AB	309	/* Disable Port-Writes for Configuration Block error reporting */
a93192a5 AB	310	rio_read_config_32(rdev, IDT_CFGBLK_ERR_REPORT, &regval);
	311	rio_write_config_32(rdev, IDT_CFGBLK_ERR_REPORT,
	312	regval & ~IDT_CFGBLK_ERR_REPORT_GENPW);
a3725c45 AB	313
a3725c45 AB	314	/* set TVAL = ~50us */
a93192a5	315	rio_write_config_32(rdev,
a3725c45 AB	316	rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x8e << 8);
	317
	318	return 0;
	319	}
	320
	321	static int
	322	idtg2_em_handler(struct rio_dev *rdev, u8 portnum)
	323	{
a3725c45 AB	324	u32 regval, em_perrdet, em_ltlerrdet;
a3725c45 AB	325
a93192a5	326	rio_read_config_32(rdev,
a3725c45 AB	327	rdev->em_efptr + RIO_EM_LTL_ERR_DETECT, &em_ltlerrdet);
	328	if (em_ltlerrdet) {
	329	/* Service Logical/Transport Layer Error(s) */
	330	if (em_ltlerrdet & REM_LTL_ERR_IMPSPEC) {
	331	/* Implementation specific error reported */
a93192a5	332	rio_read_config_32(rdev,
a3725c45 AB	333	IDT_ISLTL_ADDRESS_CAP, &regval);
	334
	335	pr_debug("RIO: %s Implementation Specific LTL errors" \
	336	" 0x%x @(0x%x)\n",
	337	rio_name(rdev), em_ltlerrdet, regval);
	338
	339	/* Clear implementation specific address capture CSR */
a93192a5	340	rio_write_config_32(rdev, IDT_ISLTL_ADDRESS_CAP, 0);
a3725c45 AB	341
	342	}
	343	}
	344
a93192a5	345	rio_read_config_32(rdev,
a3725c45 AB	346	rdev->em_efptr + RIO_EM_PN_ERR_DETECT(portnum), &em_perrdet);
	347	if (em_perrdet) {
	348	/* Service Port-Level Error(s) */
	349	if (em_perrdet & REM_PED_IMPL_SPEC) {
	350	/* Implementation Specific port error reported */
	351
	352	/* Get IS errors reported */
a93192a5	353	rio_read_config_32(rdev,
a3725c45 AB	354	IDT_PORT_ISERR_DET(portnum), &regval);
	355
	356	pr_debug("RIO: %s Implementation Specific Port" \
	357	" errors 0x%x\n", rio_name(rdev), regval);
	358
	359	/* Clear all implementation specific events */
a93192a5	360	rio_write_config_32(rdev,
a3725c45 AB	361	IDT_PORT_ISERR_DET(portnum), 0);
	362	}
	363	}
	364
	365	return 0;
	366	}
	367
	368	static ssize_t
	369	idtg2_show_errlog(struct device dev, struct device_attribute attr, char *buf)
	370	{
	371	struct rio_dev *rdev = to_rio_dev(dev);
a3725c45 AB	372	ssize_t len = 0;
	373	u32 regval;
	374
a93192a5	375	while (!rio_read_config_32(rdev, IDT_ERR_RD, &regval)) {
a3725c45 AB	376	if (!regval) /* 0 = end of log */
	377	break;
	378	len += snprintf(buf + len, PAGE_SIZE - len,
	379	"%08x\n", regval);
	380	if (len >= (PAGE_SIZE - 10))
	381	break;
	382	}
	383
	384	return len;
	385	}
	386
	387	static DEVICE_ATTR(errlog, S_IRUGO, idtg2_show_errlog, NULL);
	388
	389	static int idtg2_sysfs(struct rio_dev *rdev, int create)
	390	{
	391	struct device *dev = &rdev->dev;
	392	int err = 0;
	393
	394	if (create == RIO_SW_SYSFS_CREATE) {
	395	/* Initialize sysfs entries */
	396	err = device_create_file(dev, &dev_attr_errlog);
	397	if (err)
	398	dev_err(dev, "Unable create sysfs errlog file\n");
	399	} else
	400	device_remove_file(dev, &dev_attr_errlog);
	401
	402	return err;
	403	}
	404
	405	static int idtg2_switch_init(struct rio_dev *rdev, int do_enum)
	406	{
	407	pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev));
	408	rdev->rswitch->add_entry = idtg2_route_add_entry;
	409	rdev->rswitch->get_entry = idtg2_route_get_entry;
	410	rdev->rswitch->clr_table = idtg2_route_clr_table;
	411	rdev->rswitch->set_domain = idtg2_set_domain;
	412	rdev->rswitch->get_domain = idtg2_get_domain;
	413	rdev->rswitch->em_init = idtg2_em_init;
	414	rdev->rswitch->em_handle = idtg2_em_handler;
	415	rdev->rswitch->sw_sysfs = idtg2_sysfs;
	416
0bf2461f AB	417	if (do_enum) {
	418	/* Ensure that default routing is disabled on startup */
	419	rio_write_config_32(rdev,
	420	RIO_STD_RTE_DEFAULT_PORT, IDT_NO_ROUTE);
	421	}
	422
a3725c45 AB	423	return 0;
	424	}
	425
	426	DECLARE_RIO_SWITCH_INIT(RIO_VID_IDT, RIO_DID_IDTCPS1848, idtg2_switch_init);
	427	DECLARE_RIO_SWITCH_INIT(RIO_VID_IDT, RIO_DID_IDTCPS1616, idtg2_switch_init);
2e9d4d84 AB	428	DECLARE_RIO_SWITCH_INIT(RIO_VID_IDT, RIO_DID_IDTVPS1616, idtg2_switch_init);
2e9d4d84 AB	429	DECLARE_RIO_SWITCH_INIT(RIO_VID_IDT, RIO_DID_IDTSPS1616, idtg2_switch_init);
13209c2a	430	DECLARE_RIO_SWITCH_INIT(RIO_VID_IDT, RIO_DID_IDTCPS1432, idtg2_switch_init);