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regulator: ab8500: Remove ab8500_regulator_set_voltage_time_sel
[deliverable/linux.git] / drivers / regulator / ab8500.c
CommitLineData
c789ca20
SI		 1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 *
e1159e6d
BJ		 6 * Authors: Sundar Iyer <sundar.iyer@stericsson.com> for ST-Ericsson
7 * Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson
547f384f 8 * Daniel Willerud <daniel.willerud@stericsson.com> for ST-Ericsson
c789ca20
SI		 9 *
10 * AB8500 peripheral regulators
11 *
e1159e6d 12 * AB8500 supports the following regulators:
ea05ef31 13 * VAUX1/2/3, VINTCORE, VTVOUT, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
547f384f
LJ		 14 *
15 * AB8505 supports the following regulators:
16 * VAUX1/2/3/4/5/6, VINTCORE, VADC, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
c789ca20
SI		 17 */
18#include <linux/init.h>
19#include <linux/kernel.h>
65602c32 20#include <linux/module.h>
c789ca20
SI		 21#include <linux/err.h>
22#include <linux/platform_device.h>
47c16975 23#include <linux/mfd/abx500.h>
ee66e653 24#include <linux/mfd/abx500/ab8500.h>
3a8334b9
LJ		 25#include <linux/of.h>
26#include <linux/regulator/of_regulator.h>
c789ca20
SI		 27#include <linux/regulator/driver.h>
28#include <linux/regulator/machine.h>
29#include <linux/regulator/ab8500.h>
3a8334b9 30#include <linux/slab.h>
c789ca20 31
3fe52289
LJ		 32/**
33 * struct ab8500_shared_mode - is used when mode is shared between
34 * two regulators.
35 * @shared_regulator: pointer to the other sharing regulator
36 * @lp_mode_req: low power mode requested by this regulator
37 */
38struct ab8500_shared_mode {
39 struct ab8500_regulator_info *shared_regulator;
40 bool lp_mode_req;
41};
42
c789ca20
SI		 43/**
44 * struct ab8500_regulator_info - ab8500 regulator information
e1159e6d 45 * @dev: device pointer
c789ca20 46 * @desc: regulator description
c789ca20 47 * @regulator_dev: regulator device
3fe52289 48 * @shared_mode: used when mode is shared between two regulators
bd28a157 49 * @is_enabled: status of regulator (on/off)
7ce4669c 50 * @load_lp_uA: maximum load in idle (low power) mode
47c16975 51 * @update_bank: bank to control on/off
c789ca20 52 * @update_reg: register to control on/off
bd28a157
EV		 53 * @update_mask: mask to enable/disable and set mode of regulator
54 * @update_val: bits holding the regulator current mode
55 * @update_val_idle: bits to enable the regulator in idle (low power) mode
56 * @update_val_normal: bits to enable the regulator in normal (high power) mode
3fe52289
LJ		 57 * @mode_bank: bank with location of mode register
58 * @mode_reg: mode register
59 * @mode_mask: mask for setting mode
60 * @mode_val_idle: mode setting for low power
61 * @mode_val_normal: mode setting for normal power
47c16975 62 * @voltage_bank: bank to control regulator voltage
c789ca20
SI		 63 * @voltage_reg: register to control regulator voltage
64 * @voltage_mask: mask to control regulator voltage
a0a7014c 65 * @voltage_shift: shift to control regulator voltage
c789ca20
SI		 66 */
67struct ab8500_regulator_info {
68 struct device *dev;
69 struct regulator_desc desc;
c789ca20 70 struct regulator_dev *regulator;
3fe52289 71 struct ab8500_shared_mode *shared_mode;
bd28a157 72 bool is_enabled;
7ce4669c 73 int load_lp_uA;
47c16975
MW		 74 u8 update_bank;
75 u8 update_reg;
e1159e6d 76 u8 update_mask;
bd28a157
EV		 77 u8 update_val;
78 u8 update_val_idle;
79 u8 update_val_normal;
3fe52289
LJ		 80 u8 mode_bank;
81 u8 mode_reg;
82 u8 mode_mask;
83 u8 mode_val_idle;
84 u8 mode_val_normal;
47c16975
MW		 85 u8 voltage_bank;
86 u8 voltage_reg;
87 u8 voltage_mask;
a0a7014c 88 u8 voltage_shift;
d7607baf
LJ		 89 struct {
90 u8 voltage_limit;
91 u8 voltage_bank;
92 u8 voltage_reg;
93 u8 voltage_mask;
94 u8 voltage_shift;
95 } expand_register;
c789ca20
SI		 96};
97
98/* voltage tables for the vauxn/vintcore supplies */
ec1cc4d9 99static const unsigned int ldo_vauxn_voltages[] = {
c789ca20
SI		 100 1100000,
101 1200000,
102 1300000,
103 1400000,
104 1500000,
105 1800000,
106 1850000,
107 1900000,
108 2500000,
109 2650000,
110 2700000,
111 2750000,
112 2800000,
113 2900000,
114 3000000,
115 3300000,
116};
117
ec1cc4d9 118static const unsigned int ldo_vaux3_voltages[] = {
2b75151a
BJ		 119 1200000,
120 1500000,
121 1800000,
122 2100000,
123 2500000,
124 2750000,
125 2790000,
126 2910000,
127};
128
62ab4111 129static const unsigned int ldo_vaux56_voltages[] = {
547f384f
LJ		 130 1800000,
131 1050000,
132 1100000,
133 1200000,
134 1500000,
135 2200000,
136 2500000,
137 2790000,
138};
139
62ab4111 140static const unsigned int ldo_vaux3_ab8540_voltages[] = {
ae0a9a3e
LJ		 141 1200000,
142 1500000,
143 1800000,
144 2100000,
145 2500000,
146 2750000,
147 2790000,
148 2910000,
149 3050000,
150};
151
684d5ce4
ZH		 152static const unsigned int ldo_vaux56_ab8540_voltages[] = {
153 750000, 760000, 770000, 780000, 790000, 800000,
154 810000, 820000, 830000, 840000, 850000, 860000,
155 870000, 880000, 890000, 900000, 910000, 920000,
156 930000, 940000, 950000, 960000, 970000, 980000,
157 990000, 1000000, 1010000, 1020000, 1030000,
158 1040000, 1050000, 1060000, 1070000, 1080000,
159 1090000, 1100000, 1110000, 1120000, 1130000,
160 1140000, 1150000, 1160000, 1170000, 1180000,
161 1190000, 1200000, 1210000, 1220000, 1230000,
162 1240000, 1250000, 1260000, 1270000, 1280000,
163 1290000, 1300000, 1310000, 1320000, 1330000,
164 1340000, 1350000, 1360000, 1800000, 2790000,
165};
166
ec1cc4d9 167static const unsigned int ldo_vintcore_voltages[] = {
c789ca20
SI		 168 1200000,
169 1225000,
170 1250000,
171 1275000,
172 1300000,
173 1325000,
174 1350000,
175};
176
62ab4111 177static const unsigned int ldo_sdio_voltages[] = {
ae0a9a3e
LJ		 178 1160000,
179 1050000,
180 1100000,
181 1500000,
182 1800000,
183 2200000,
184 2910000,
185 3050000,
186};
187
b080c78a
LJ		 188static const unsigned int fixed_1200000_voltage[] = {
189 1200000,
190};
191
192static const unsigned int fixed_1800000_voltage[] = {
193 1800000,
194};
195
196static const unsigned int fixed_2000000_voltage[] = {
197 2000000,
198};
199
200static const unsigned int fixed_2050000_voltage[] = {
201 2050000,
202};
203
204static const unsigned int fixed_3300000_voltage[] = {
205 3300000,
206};
207
8a3b1b87
LJ		 208static const unsigned int ldo_vana_voltages[] = {
209 1050000,
210 1075000,
211 1100000,
212 1125000,
213 1150000,
214 1175000,
215 1200000,
216 1225000,
217};
218
219static const unsigned int ldo_vaudio_voltages[] = {
220 2000000,
221 2100000,
222 2200000,
223 2300000,
224 2400000,
225 2500000,
226 2600000,
227 2600000, /* Duplicated in Vaudio and IsoUicc Control register. */
228};
229
4c84b4dd
LJ		 230static const unsigned int ldo_vdmic_voltages[] = {
231 1800000,
232 1900000,
233 2000000,
234 2850000,
235};
236
3fe52289
LJ		 237static DEFINE_MUTEX(shared_mode_mutex);
238static struct ab8500_shared_mode ldo_anamic1_shared;
239static struct ab8500_shared_mode ldo_anamic2_shared;
4c84b4dd
LJ		 240static struct ab8500_shared_mode ab8540_ldo_anamic1_shared;
241static struct ab8500_shared_mode ab8540_ldo_anamic2_shared;
3fe52289 242
c789ca20
SI		 243static int ab8500_regulator_enable(struct regulator_dev *rdev)
244{
fc24b426 245 int ret;
c789ca20
SI		 246 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
247
fc24b426
BJ		 248 if (info == NULL) {
249 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 250 return -EINVAL;
fc24b426 251 }
c789ca20 252
47c16975 253 ret = abx500_mask_and_set_register_interruptible(info->dev,
e1159e6d 254 info->update_bank, info->update_reg,
bd28a157 255 info->update_mask, info->update_val);
f71bf528 256 if (ret < 0) {
c789ca20
SI		 257 dev_err(rdev_get_dev(rdev),
258 "couldn't set enable bits for regulator\n");
f71bf528
AL		 259 return ret;
260 }
09aefa12 261
bd28a157
EV		 262 info->is_enabled = true;
263
09aefa12
BJ		 264 dev_vdbg(rdev_get_dev(rdev),
265 "%s-enable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
266 info->desc.name, info->update_bank, info->update_reg,
bd28a157 267 info->update_mask, info->update_val);
09aefa12 268
c789ca20
SI		 269 return ret;
270}
271
272static int ab8500_regulator_disable(struct regulator_dev *rdev)
273{
fc24b426 274 int ret;
c789ca20
SI		 275 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
276
fc24b426
BJ		 277 if (info == NULL) {
278 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 279 return -EINVAL;
fc24b426 280 }
c789ca20 281
47c16975 282 ret = abx500_mask_and_set_register_interruptible(info->dev,
e1159e6d
BJ		 283 info->update_bank, info->update_reg,
284 info->update_mask, 0x0);
f71bf528 285 if (ret < 0) {
c789ca20
SI		 286 dev_err(rdev_get_dev(rdev),
287 "couldn't set disable bits for regulator\n");
f71bf528
AL		 288 return ret;
289 }
09aefa12 290
bd28a157
EV		 291 info->is_enabled = false;
292
09aefa12
BJ		 293 dev_vdbg(rdev_get_dev(rdev),
294 "%s-disable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
295 info->desc.name, info->update_bank, info->update_reg,
296 info->update_mask, 0x0);
297
c789ca20
SI		 298 return ret;
299}
300
7ce4669c
BJ		 301static unsigned int ab8500_regulator_get_optimum_mode(
302 struct regulator_dev *rdev, int input_uV,
303 int output_uV, int load_uA)
304{
305 unsigned int mode;
306
307 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
308
309 if (info == NULL) {
310 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
311 return -EINVAL;
312 }
313
314 if (load_uA <= info->load_lp_uA)
315 mode = REGULATOR_MODE_IDLE;
316 else
317 mode = REGULATOR_MODE_NORMAL;
318
319 return mode;
320}
321
bd28a157
EV		 322static int ab8500_regulator_set_mode(struct regulator_dev *rdev,
323 unsigned int mode)
324{
3fe52289
LJ		 325 int ret = 0;
326 u8 bank;
327 u8 reg;
328 u8 mask;
329 u8 val;
330 bool dmr = false; /* Dedicated mode register */
bd28a157
EV		 331 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
332
333 if (info == NULL) {
334 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
335 return -EINVAL;
336 }
337
3fe52289
LJ		 338 if (info->shared_mode) {
339 /*
340 * Special case where mode is shared between two regulators.
341 */
342 struct ab8500_shared_mode *sm = info->shared_mode;
343 mutex_lock(&shared_mode_mutex);
344
345 if (mode == REGULATOR_MODE_IDLE) {
346 sm->lp_mode_req = true; /* Low power mode requested */
347 if (!((sm->shared_regulator)->
348 shared_mode->lp_mode_req)) {
349 mutex_unlock(&shared_mode_mutex);
350 return 0; /* Other regulator prevent LP mode */
351 }
352 } else {
353 sm->lp_mode_req = false;
354 }
355 }
356
357 if (info->mode_mask) {
358 /* Dedicated register for handling mode */
359
360 dmr = true;
361
362 switch (mode) {
363 case REGULATOR_MODE_NORMAL:
364 val = info->mode_val_normal;
365 break;
366 case REGULATOR_MODE_IDLE:
367 val = info->mode_val_idle;
368 break;
369 default:
370 if (info->shared_mode)
371 mutex_unlock(&shared_mode_mutex);
372 return -EINVAL;
373 }
374
375 bank = info->mode_bank;
376 reg = info->mode_reg;
377 mask = info->mode_mask;
378 } else {
379 /* Mode register same as enable register */
380
381 switch (mode) {
382 case REGULATOR_MODE_NORMAL:
383 info->update_val = info->update_val_normal;
384 val = info->update_val_normal;
385 break;
386 case REGULATOR_MODE_IDLE:
387 info->update_val = info->update_val_idle;
388 val = info->update_val_idle;
389 break;
390 default:
391 if (info->shared_mode)
392 mutex_unlock(&shared_mode_mutex);
393 return -EINVAL;
394 }
395
396 bank = info->update_bank;
397 reg = info->update_reg;
398 mask = info->update_mask;
bd28a157
EV		 399 }
400
3fe52289 401 if (info->is_enabled || dmr) {
bd28a157 402 ret = abx500_mask_and_set_register_interruptible(info->dev,
3fe52289
LJ		 403 bank, reg, mask, val);
404 if (ret < 0)
bd28a157
EV		 405 dev_err(rdev_get_dev(rdev),
406 "couldn't set regulator mode\n");
7ce4669c
BJ		 407
408 dev_vdbg(rdev_get_dev(rdev),
409 "%s-set_mode (bank, reg, mask, value): "
410 "0x%x, 0x%x, 0x%x, 0x%x\n",
3fe52289
LJ		 411 info->desc.name, bank, reg,
412 mask, val);
bd28a157
EV		 413 }
414
3fe52289
LJ		 415 if (info->shared_mode)
416 mutex_unlock(&shared_mode_mutex);
742a7325 417
3fe52289 418 return ret;
bd28a157
EV		 419}
420
421static unsigned int ab8500_regulator_get_mode(struct regulator_dev *rdev)
422{
423 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
424 int ret;
3fe52289
LJ		 425 u8 val;
426 u8 val_normal;
427 u8 val_idle;
bd28a157
EV		 428
429 if (info == NULL) {
430 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
431 return -EINVAL;
432 }
433
3fe52289
LJ		 434 /* Need special handling for shared mode */
435 if (info->shared_mode) {
436 if (info->shared_mode->lp_mode_req)
437 return REGULATOR_MODE_IDLE;
438 else
439 return REGULATOR_MODE_NORMAL;
440 }
441
442 if (info->mode_mask) {
443 /* Dedicated register for handling mode */
444 ret = abx500_get_register_interruptible(info->dev,
445 info->mode_bank, info->mode_reg, &val);
446 val = val & info->mode_mask;
447
448 val_normal = info->mode_val_normal;
449 val_idle = info->mode_val_idle;
450 } else {
451 /* Mode register same as enable register */
452 val = info->update_val;
453 val_normal = info->update_val_normal;
454 val_idle = info->update_val_idle;
455 }
456
457 if (val == val_normal)
bd28a157 458 ret = REGULATOR_MODE_NORMAL;
3fe52289 459 else if (val == val_idle)
bd28a157
EV		 460 ret = REGULATOR_MODE_IDLE;
461 else
462 ret = -EINVAL;
463
464 return ret;
465}
466
c789ca20
SI		 467static int ab8500_regulator_is_enabled(struct regulator_dev *rdev)
468{
fc24b426 469 int ret;
c789ca20 470 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
09aefa12 471 u8 regval;
c789ca20 472
fc24b426
BJ		 473 if (info == NULL) {
474 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 475 return -EINVAL;
fc24b426 476 }
c789ca20 477
47c16975 478 ret = abx500_get_register_interruptible(info->dev,
09aefa12 479 info->update_bank, info->update_reg, &regval);
c789ca20
SI		 480 if (ret < 0) {
481 dev_err(rdev_get_dev(rdev),
482 "couldn't read 0x%x register\n", info->update_reg);
483 return ret;
484 }
485
09aefa12
BJ		 486 dev_vdbg(rdev_get_dev(rdev),
487 "%s-is_enabled (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
488 " 0x%x\n",
489 info->desc.name, info->update_bank, info->update_reg,
490 info->update_mask, regval);
491
492 if (regval & info->update_mask)
bd28a157 493 info->is_enabled = true;
c789ca20 494 else
bd28a157
EV		 495 info->is_enabled = false;
496
497 return info->is_enabled;
c789ca20
SI		 498}
499
3bf6e90e 500static int ab8500_regulator_get_voltage_sel(struct regulator_dev *rdev)
c789ca20 501{
09aefa12 502 int ret, val;
c789ca20 503 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
09aefa12 504 u8 regval;
c789ca20 505
fc24b426
BJ		 506 if (info == NULL) {
507 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 508 return -EINVAL;
fc24b426 509 }
c789ca20 510
09aefa12
BJ		 511 ret = abx500_get_register_interruptible(info->dev,
512 info->voltage_bank, info->voltage_reg, &regval);
c789ca20
SI		 513 if (ret < 0) {
514 dev_err(rdev_get_dev(rdev),
515 "couldn't read voltage reg for regulator\n");
516 return ret;
517 }
518
09aefa12 519 dev_vdbg(rdev_get_dev(rdev),
a0a7014c
LW		 520 "%s-get_voltage (bank, reg, mask, shift, value): "
521 "0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
522 info->desc.name, info->voltage_bank,
523 info->voltage_reg, info->voltage_mask,
524 info->voltage_shift, regval);
09aefa12 525
09aefa12 526 val = regval & info->voltage_mask;
a0a7014c 527 return val >> info->voltage_shift;
c789ca20
SI		 528}
529
d7607baf
LJ		 530static int ab8540_aux3_regulator_get_voltage_sel(struct regulator_dev *rdev)
531{
532 int ret, val;
533 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
534 u8 regval, regval_expand;
535
536 if (info == NULL) {
537 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
538 return -EINVAL;
539 }
540
541 ret = abx500_get_register_interruptible(info->dev,
542 info->voltage_bank, info->voltage_reg, &regval);
543
544 if (ret < 0) {
545 dev_err(rdev_get_dev(rdev),
546 "couldn't read voltage reg for regulator\n");
547 return ret;
548 }
549
550 ret = abx500_get_register_interruptible(info->dev,
551 info->expand_register.voltage_bank,
552 info->expand_register.voltage_reg, &regval_expand);
553
554 if (ret < 0) {
555 dev_err(rdev_get_dev(rdev),
556 "couldn't read voltage reg for regulator\n");
557 return ret;
558 }
559
560 dev_vdbg(rdev_get_dev(rdev),
561 "%s-get_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
562 " 0x%x\n",
563 info->desc.name, info->voltage_bank, info->voltage_reg,
564 info->voltage_mask, regval);
565 dev_vdbg(rdev_get_dev(rdev),
566 "%s-get_voltage expand (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
567 " 0x%x\n",
568 info->desc.name, info->expand_register.voltage_bank,
569 info->expand_register.voltage_reg,
570 info->expand_register.voltage_mask, regval_expand);
571
572 if (regval_expand&(info->expand_register.voltage_mask))
573 /* Vaux3 has a different layout */
574 val = info->expand_register.voltage_limit;
575 else
576 val = (regval & info->voltage_mask) >> info->voltage_shift;
577
578 return val;
579}
580
ae713d39
AL		 581static int ab8500_regulator_set_voltage_sel(struct regulator_dev *rdev,
582 unsigned selector)
c789ca20 583{
fc24b426 584 int ret;
c789ca20 585 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
09aefa12 586 u8 regval;
c789ca20 587
fc24b426
BJ		 588 if (info == NULL) {
589 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 590 return -EINVAL;
fc24b426 591 }
c789ca20 592
c789ca20 593 /* set the registers for the request */
a0a7014c 594 regval = (u8)selector << info->voltage_shift;
47c16975 595 ret = abx500_mask_and_set_register_interruptible(info->dev,
09aefa12
BJ		 596 info->voltage_bank, info->voltage_reg,
597 info->voltage_mask, regval);
c789ca20
SI		 598 if (ret < 0)
599 dev_err(rdev_get_dev(rdev),
600 "couldn't set voltage reg for regulator\n");
601
09aefa12
BJ		 602 dev_vdbg(rdev_get_dev(rdev),
603 "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
604 " 0x%x\n",
605 info->desc.name, info->voltage_bank, info->voltage_reg,
606 info->voltage_mask, regval);
607
c789ca20
SI		 608 return ret;
609}
610
d7607baf
LJ		 611static int ab8540_aux3_regulator_set_voltage_sel(struct regulator_dev *rdev,
612 unsigned selector)
613{
614 int ret;
615 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
616 u8 regval;
617
618 if (info == NULL) {
619 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
620 return -EINVAL;
621 }
622
623 if (selector >= info->expand_register.voltage_limit) {
624 /* Vaux3 bit4 has different layout */
625 regval = (u8)selector << info->expand_register.voltage_shift;
626 ret = abx500_mask_and_set_register_interruptible(info->dev,
627 info->expand_register.voltage_bank,
628 info->expand_register.voltage_reg,
629 info->expand_register.voltage_mask,
630 regval);
631 } else {
632 /* set the registers for the request */
633 regval = (u8)selector << info->voltage_shift;
634 ret = abx500_mask_and_set_register_interruptible(info->dev,
635 info->voltage_bank, info->voltage_reg,
636 info->voltage_mask, regval);
637 }
638 if (ret < 0)
639 dev_err(rdev_get_dev(rdev),
640 "couldn't set voltage reg for regulator\n");
641
642 dev_vdbg(rdev_get_dev(rdev),
643 "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
644 " 0x%x\n",
645 info->desc.name, info->voltage_bank, info->voltage_reg,
646 info->voltage_mask, regval);
647
648 return ret;
649}
650
7ce4669c
BJ		 651static struct regulator_ops ab8500_regulator_volt_mode_ops = {
652 .enable = ab8500_regulator_enable,
653 .disable = ab8500_regulator_disable,
654 .is_enabled = ab8500_regulator_is_enabled,
655 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
656 .set_mode = ab8500_regulator_set_mode,
657 .get_mode = ab8500_regulator_get_mode,
658 .get_voltage_sel = ab8500_regulator_get_voltage_sel,
659 .set_voltage_sel = ab8500_regulator_set_voltage_sel,
660 .list_voltage = regulator_list_voltage_table,
c789ca20
SI		 661};
662
d7607baf
LJ		 663static struct regulator_ops ab8540_aux3_regulator_volt_mode_ops = {
664 .enable = ab8500_regulator_enable,
665 .disable = ab8500_regulator_disable,
666 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
667 .set_mode = ab8500_regulator_set_mode,
668 .get_mode = ab8500_regulator_get_mode,
669 .is_enabled = ab8500_regulator_is_enabled,
670 .get_voltage_sel = ab8540_aux3_regulator_get_voltage_sel,
671 .set_voltage_sel = ab8540_aux3_regulator_set_voltage_sel,
672 .list_voltage = regulator_list_voltage_table,
d7607baf
LJ		 673};
674
8a3b1b87
LJ		 675static struct regulator_ops ab8500_regulator_volt_ops = {
676 .enable = ab8500_regulator_enable,
677 .disable = ab8500_regulator_disable,
678 .is_enabled = ab8500_regulator_is_enabled,
679 .get_voltage_sel = ab8500_regulator_get_voltage_sel,
680 .set_voltage_sel = ab8500_regulator_set_voltage_sel,
681 .list_voltage = regulator_list_voltage_table,
8a3b1b87
LJ		 682};
683
7ce4669c
BJ		 684static struct regulator_ops ab8500_regulator_mode_ops = {
685 .enable = ab8500_regulator_enable,
686 .disable = ab8500_regulator_disable,
687 .is_enabled = ab8500_regulator_is_enabled,
688 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
689 .set_mode = ab8500_regulator_set_mode,
690 .get_mode = ab8500_regulator_get_mode,
d7816ab0 691 .list_voltage = regulator_list_voltage_table,
7ce4669c
BJ		 692};
693
694static struct regulator_ops ab8500_regulator_ops = {
695 .enable = ab8500_regulator_enable,
696 .disable = ab8500_regulator_disable,
697 .is_enabled = ab8500_regulator_is_enabled,
d7816ab0 698 .list_voltage = regulator_list_voltage_table,
c789ca20
SI		 699};
700
3fe52289
LJ		 701static struct regulator_ops ab8500_regulator_anamic_mode_ops = {
702 .enable = ab8500_regulator_enable,
703 .disable = ab8500_regulator_disable,
704 .is_enabled = ab8500_regulator_is_enabled,
705 .set_mode = ab8500_regulator_set_mode,
706 .get_mode = ab8500_regulator_get_mode,
707 .list_voltage = regulator_list_voltage_table,
708};
709
8e6a8d7d 710/* AB8500 regulator information */
6909b452
BJ		 711static struct ab8500_regulator_info
712 ab8500_regulator_info[AB8500_NUM_REGULATORS] = {
c789ca20 713 /*
e1159e6d
BJ		 714 * Variable Voltage Regulators
715 * name, min mV, max mV,
716 * update bank, reg, mask, enable val
ec1cc4d9 717 * volt bank, reg, mask
c789ca20 718 */
6909b452
BJ		 719 [AB8500_LDO_AUX1] = {
720 .desc = {
721 .name = "LDO-AUX1",
7ce4669c 722 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 723 .type = REGULATOR_VOLTAGE,
724 .id = AB8500_LDO_AUX1,
725 .owner = THIS_MODULE,
726 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
ec1cc4d9 727 .volt_table = ldo_vauxn_voltages,
530158b6 728 .enable_time = 200,
6909b452 729 },
7ce4669c 730 .load_lp_uA = 5000,
6909b452
BJ		 731 .update_bank = 0x04,
732 .update_reg = 0x09,
733 .update_mask = 0x03,
bd28a157
EV		 734 .update_val = 0x01,
735 .update_val_idle = 0x03,
736 .update_val_normal = 0x01,
6909b452
BJ		 737 .voltage_bank = 0x04,
738 .voltage_reg = 0x1f,
739 .voltage_mask = 0x0f,
6909b452
BJ		 740 },
741 [AB8500_LDO_AUX2] = {
742 .desc = {
743 .name = "LDO-AUX2",
7ce4669c 744 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 745 .type = REGULATOR_VOLTAGE,
746 .id = AB8500_LDO_AUX2,
747 .owner = THIS_MODULE,
748 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
ec1cc4d9 749 .volt_table = ldo_vauxn_voltages,
530158b6 750 .enable_time = 200,
6909b452 751 },
7ce4669c 752 .load_lp_uA = 5000,
6909b452
BJ		 753 .update_bank = 0x04,
754 .update_reg = 0x09,
755 .update_mask = 0x0c,
bd28a157
EV		 756 .update_val = 0x04,
757 .update_val_idle = 0x0c,
758 .update_val_normal = 0x04,
6909b452
BJ		 759 .voltage_bank = 0x04,
760 .voltage_reg = 0x20,
761 .voltage_mask = 0x0f,
6909b452
BJ		 762 },
763 [AB8500_LDO_AUX3] = {
764 .desc = {
765 .name = "LDO-AUX3",
7ce4669c 766 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 767 .type = REGULATOR_VOLTAGE,
768 .id = AB8500_LDO_AUX3,
769 .owner = THIS_MODULE,
770 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
ec1cc4d9 771 .volt_table = ldo_vaux3_voltages,
530158b6 772 .enable_time = 450,
6909b452 773 },
7ce4669c 774 .load_lp_uA = 5000,
6909b452
BJ		 775 .update_bank = 0x04,
776 .update_reg = 0x0a,
777 .update_mask = 0x03,
bd28a157
EV		 778 .update_val = 0x01,
779 .update_val_idle = 0x03,
780 .update_val_normal = 0x01,
6909b452
BJ		 781 .voltage_bank = 0x04,
782 .voltage_reg = 0x21,
783 .voltage_mask = 0x07,
6909b452
BJ		 784 },
785 [AB8500_LDO_INTCORE] = {
786 .desc = {
787 .name = "LDO-INTCORE",
7ce4669c 788 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 789 .type = REGULATOR_VOLTAGE,
790 .id = AB8500_LDO_INTCORE,
791 .owner = THIS_MODULE,
792 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
ec1cc4d9 793 .volt_table = ldo_vintcore_voltages,
530158b6 794 .enable_time = 750,
6909b452 795 },
7ce4669c 796 .load_lp_uA = 5000,
6909b452
BJ		 797 .update_bank = 0x03,
798 .update_reg = 0x80,
799 .update_mask = 0x44,
cc40dc29 800 .update_val = 0x44,
bd28a157
EV		 801 .update_val_idle = 0x44,
802 .update_val_normal = 0x04,
6909b452
BJ		 803 .voltage_bank = 0x03,
804 .voltage_reg = 0x80,
805 .voltage_mask = 0x38,
a0a7014c 806 .voltage_shift = 3,
6909b452 807 },
c789ca20
SI		 808
809 /*
e1159e6d
BJ		 810 * Fixed Voltage Regulators
811 * name, fixed mV,
812 * update bank, reg, mask, enable val
c789ca20 813 */
6909b452
BJ		 814 [AB8500_LDO_TVOUT] = {
815 .desc = {
816 .name = "LDO-TVOUT",
7ce4669c 817 .ops = &ab8500_regulator_mode_ops,
6909b452
BJ		 818 .type = REGULATOR_VOLTAGE,
819 .id = AB8500_LDO_TVOUT,
820 .owner = THIS_MODULE,
821 .n_voltages = 1,
b080c78a 822 .volt_table = fixed_2000000_voltage,
ed3c138e 823 .enable_time = 500,
6909b452 824 },
7ce4669c 825 .load_lp_uA = 1000,
6909b452
BJ		 826 .update_bank = 0x03,
827 .update_reg = 0x80,
828 .update_mask = 0x82,
bd28a157 829 .update_val = 0x02,
7ce4669c
BJ		 830 .update_val_idle = 0x82,
831 .update_val_normal = 0x02,
6909b452
BJ		 832 },
833 [AB8500_LDO_AUDIO] = {
834 .desc = {
835 .name = "LDO-AUDIO",
7ce4669c 836 .ops = &ab8500_regulator_ops,
6909b452
BJ		 837 .type = REGULATOR_VOLTAGE,
838 .id = AB8500_LDO_AUDIO,
839 .owner = THIS_MODULE,
840 .n_voltages = 1,
530158b6 841 .enable_time = 140,
b080c78a 842 .volt_table = fixed_2000000_voltage,
6909b452 843 },
6909b452
BJ		 844 .update_bank = 0x03,
845 .update_reg = 0x83,
846 .update_mask = 0x02,
bd28a157 847 .update_val = 0x02,
6909b452
BJ		 848 },
849 [AB8500_LDO_ANAMIC1] = {
850 .desc = {
851 .name = "LDO-ANAMIC1",
7ce4669c 852 .ops = &ab8500_regulator_ops,
6909b452
BJ		 853 .type = REGULATOR_VOLTAGE,
854 .id = AB8500_LDO_ANAMIC1,
855 .owner = THIS_MODULE,
856 .n_voltages = 1,
530158b6 857 .enable_time = 500,
b080c78a 858 .volt_table = fixed_2050000_voltage,
6909b452 859 },
6909b452
BJ		 860 .update_bank = 0x03,
861 .update_reg = 0x83,
862 .update_mask = 0x08,
bd28a157 863 .update_val = 0x08,
6909b452
BJ		 864 },
865 [AB8500_LDO_ANAMIC2] = {
866 .desc = {
867 .name = "LDO-ANAMIC2",
7ce4669c 868 .ops = &ab8500_regulator_ops,
6909b452
BJ		 869 .type = REGULATOR_VOLTAGE,
870 .id = AB8500_LDO_ANAMIC2,
871 .owner = THIS_MODULE,
872 .n_voltages = 1,
530158b6 873 .enable_time = 500,
b080c78a 874 .volt_table = fixed_2050000_voltage,
6909b452 875 },
6909b452
BJ		 876 .update_bank = 0x03,
877 .update_reg = 0x83,
878 .update_mask = 0x10,
bd28a157 879 .update_val = 0x10,
6909b452
BJ		 880 },
881 [AB8500_LDO_DMIC] = {
882 .desc = {
883 .name = "LDO-DMIC",
7ce4669c 884 .ops = &ab8500_regulator_ops,
6909b452
BJ		 885 .type = REGULATOR_VOLTAGE,
886 .id = AB8500_LDO_DMIC,
887 .owner = THIS_MODULE,
888 .n_voltages = 1,
530158b6 889 .enable_time = 420,
b080c78a 890 .volt_table = fixed_1800000_voltage,
6909b452 891 },
6909b452
BJ		 892 .update_bank = 0x03,
893 .update_reg = 0x83,
894 .update_mask = 0x04,
bd28a157 895 .update_val = 0x04,
6909b452 896 },
7ce4669c
BJ		 897
898 /*
899 * Regulators with fixed voltage and normal/idle modes
900 */
6909b452
BJ		 901 [AB8500_LDO_ANA] = {
902 .desc = {
903 .name = "LDO-ANA",
7ce4669c 904 .ops = &ab8500_regulator_mode_ops,
6909b452
BJ		 905 .type = REGULATOR_VOLTAGE,
906 .id = AB8500_LDO_ANA,
907 .owner = THIS_MODULE,
908 .n_voltages = 1,
530158b6 909 .enable_time = 140,
b080c78a 910 .volt_table = fixed_1200000_voltage,
6909b452 911 },
7ce4669c 912 .load_lp_uA = 1000,
6909b452
BJ		 913 .update_bank = 0x04,
914 .update_reg = 0x06,
915 .update_mask = 0x0c,
bd28a157 916 .update_val = 0x04,
7ce4669c
BJ		 917 .update_val_idle = 0x0c,
918 .update_val_normal = 0x04,
6909b452 919 },
8e6a8d7d 920};
6909b452 921
547f384f
LJ		 922/* AB8505 regulator information */
923static struct ab8500_regulator_info
924 ab8505_regulator_info[AB8505_NUM_REGULATORS] = {
925 /*
926 * Variable Voltage Regulators
927 * name, min mV, max mV,
928 * update bank, reg, mask, enable val
d3193103 929 * volt bank, reg, mask
547f384f
LJ		 930 */
931 [AB8505_LDO_AUX1] = {
932 .desc = {
933 .name = "LDO-AUX1",
934 .ops = &ab8500_regulator_volt_mode_ops,
935 .type = REGULATOR_VOLTAGE,
0b946411 936 .id = AB8505_LDO_AUX1,
547f384f
LJ		 937 .owner = THIS_MODULE,
938 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 939 .volt_table = ldo_vauxn_voltages,
547f384f 940 },
547f384f
LJ		 941 .load_lp_uA = 5000,
942 .update_bank = 0x04,
943 .update_reg = 0x09,
944 .update_mask = 0x03,
945 .update_val = 0x01,
946 .update_val_idle = 0x03,
947 .update_val_normal = 0x01,
948 .voltage_bank = 0x04,
949 .voltage_reg = 0x1f,
950 .voltage_mask = 0x0f,
547f384f
LJ		 951 },
952 [AB8505_LDO_AUX2] = {
953 .desc = {
954 .name = "LDO-AUX2",
955 .ops = &ab8500_regulator_volt_mode_ops,
956 .type = REGULATOR_VOLTAGE,
0b946411 957 .id = AB8505_LDO_AUX2,
547f384f
LJ		 958 .owner = THIS_MODULE,
959 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 960 .volt_table = ldo_vauxn_voltages,
547f384f 961 },
547f384f
LJ		 962 .load_lp_uA = 5000,
963 .update_bank = 0x04,
964 .update_reg = 0x09,
965 .update_mask = 0x0c,
966 .update_val = 0x04,
967 .update_val_idle = 0x0c,
968 .update_val_normal = 0x04,
969 .voltage_bank = 0x04,
970 .voltage_reg = 0x20,
971 .voltage_mask = 0x0f,
547f384f
LJ		 972 },
973 [AB8505_LDO_AUX3] = {
974 .desc = {
975 .name = "LDO-AUX3",
976 .ops = &ab8500_regulator_volt_mode_ops,
977 .type = REGULATOR_VOLTAGE,
0b946411 978 .id = AB8505_LDO_AUX3,
547f384f
LJ		 979 .owner = THIS_MODULE,
980 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
62ab4111 981 .volt_table = ldo_vaux3_voltages,
547f384f 982 },
547f384f
LJ		 983 .load_lp_uA = 5000,
984 .update_bank = 0x04,
985 .update_reg = 0x0a,
986 .update_mask = 0x03,
987 .update_val = 0x01,
988 .update_val_idle = 0x03,
989 .update_val_normal = 0x01,
990 .voltage_bank = 0x04,
991 .voltage_reg = 0x21,
992 .voltage_mask = 0x07,
547f384f
LJ		 993 },
994 [AB8505_LDO_AUX4] = {
995 .desc = {
996 .name = "LDO-AUX4",
997 .ops = &ab8500_regulator_volt_mode_ops,
998 .type = REGULATOR_VOLTAGE,
0b946411 999 .id = AB8505_LDO_AUX4,
547f384f
LJ		 1000 .owner = THIS_MODULE,
1001 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1002 .volt_table = ldo_vauxn_voltages,
547f384f 1003 },
547f384f
LJ		 1004 .load_lp_uA = 5000,
1005 /* values for Vaux4Regu register */
1006 .update_bank = 0x04,
1007 .update_reg = 0x2e,
1008 .update_mask = 0x03,
1009 .update_val = 0x01,
1010 .update_val_idle = 0x03,
1011 .update_val_normal = 0x01,
1012 /* values for Vaux4SEL register */
1013 .voltage_bank = 0x04,
1014 .voltage_reg = 0x2f,
1015 .voltage_mask = 0x0f,
547f384f
LJ		 1016 },
1017 [AB8505_LDO_AUX5] = {
1018 .desc = {
1019 .name = "LDO-AUX5",
1020 .ops = &ab8500_regulator_volt_mode_ops,
1021 .type = REGULATOR_VOLTAGE,
1022 .id = AB8505_LDO_AUX5,
1023 .owner = THIS_MODULE,
1024 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages),
62ab4111 1025 .volt_table = ldo_vaux56_voltages,
547f384f 1026 },
547f384f
LJ		 1027 .load_lp_uA = 2000,
1028 /* values for CtrlVaux5 register */
1029 .update_bank = 0x01,
1030 .update_reg = 0x55,
ae0a9a3e
LJ		 1031 .update_mask = 0x18,
1032 .update_val = 0x10,
1033 .update_val_idle = 0x18,
1034 .update_val_normal = 0x10,
547f384f
LJ		 1035 .voltage_bank = 0x01,
1036 .voltage_reg = 0x55,
1037 .voltage_mask = 0x07,
547f384f
LJ		 1038 },
1039 [AB8505_LDO_AUX6] = {
1040 .desc = {
1041 .name = "LDO-AUX6",
1042 .ops = &ab8500_regulator_volt_mode_ops,
1043 .type = REGULATOR_VOLTAGE,
1044 .id = AB8505_LDO_AUX6,
1045 .owner = THIS_MODULE,
1046 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages),
62ab4111 1047 .volt_table = ldo_vaux56_voltages,
547f384f 1048 },
547f384f
LJ		 1049 .load_lp_uA = 2000,
1050 /* values for CtrlVaux6 register */
1051 .update_bank = 0x01,
1052 .update_reg = 0x56,
ae0a9a3e
LJ		 1053 .update_mask = 0x18,
1054 .update_val = 0x10,
1055 .update_val_idle = 0x18,
1056 .update_val_normal = 0x10,
547f384f
LJ		 1057 .voltage_bank = 0x01,
1058 .voltage_reg = 0x56,
1059 .voltage_mask = 0x07,
547f384f
LJ		 1060 },
1061 [AB8505_LDO_INTCORE] = {
1062 .desc = {
1063 .name = "LDO-INTCORE",
1064 .ops = &ab8500_regulator_volt_mode_ops,
1065 .type = REGULATOR_VOLTAGE,
0b946411 1066 .id = AB8505_LDO_INTCORE,
547f384f
LJ		 1067 .owner = THIS_MODULE,
1068 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
62ab4111 1069 .volt_table = ldo_vintcore_voltages,
547f384f 1070 },
547f384f
LJ		 1071 .load_lp_uA = 5000,
1072 .update_bank = 0x03,
1073 .update_reg = 0x80,
1074 .update_mask = 0x44,
1075 .update_val = 0x04,
1076 .update_val_idle = 0x44,
1077 .update_val_normal = 0x04,
1078 .voltage_bank = 0x03,
1079 .voltage_reg = 0x80,
1080 .voltage_mask = 0x38,
547f384f
LJ		 1081 .voltage_shift = 3,
1082 },
1083
1084 /*
1085 * Fixed Voltage Regulators
1086 * name, fixed mV,
1087 * update bank, reg, mask, enable val
1088 */
1089 [AB8505_LDO_ADC] = {
1090 .desc = {
1091 .name = "LDO-ADC",
1092 .ops = &ab8500_regulator_mode_ops,
1093 .type = REGULATOR_VOLTAGE,
1094 .id = AB8505_LDO_ADC,
1095 .owner = THIS_MODULE,
1096 .n_voltages = 1,
b080c78a 1097 .volt_table = fixed_2000000_voltage,
a4d68468 1098 .enable_time = 10000,
547f384f 1099 },
547f384f
LJ		 1100 .load_lp_uA = 1000,
1101 .update_bank = 0x03,
1102 .update_reg = 0x80,
1103 .update_mask = 0x82,
1104 .update_val = 0x02,
1105 .update_val_idle = 0x82,
1106 .update_val_normal = 0x02,
1107 },
1108 [AB8505_LDO_USB] = {
1109 .desc = {
1110 .name = "LDO-USB",
1111 .ops = &ab8500_regulator_mode_ops,
1112 .type = REGULATOR_VOLTAGE,
0b946411 1113 .id = AB8505_LDO_USB,
547f384f
LJ		 1114 .owner = THIS_MODULE,
1115 .n_voltages = 1,
b080c78a 1116 .volt_table = fixed_3300000_voltage,
547f384f 1117 },
547f384f
LJ		 1118 .update_bank = 0x03,
1119 .update_reg = 0x82,
1120 .update_mask = 0x03,
1121 .update_val = 0x01,
1122 .update_val_idle = 0x03,
1123 .update_val_normal = 0x01,
1124 },
1125 [AB8505_LDO_AUDIO] = {
1126 .desc = {
1127 .name = "LDO-AUDIO",
8a3b1b87 1128 .ops = &ab8500_regulator_volt_ops,
547f384f 1129 .type = REGULATOR_VOLTAGE,
0b946411 1130 .id = AB8505_LDO_AUDIO,
547f384f 1131 .owner = THIS_MODULE,
8a3b1b87
LJ		 1132 .n_voltages = ARRAY_SIZE(ldo_vaudio_voltages),
1133 .volt_table = ldo_vaudio_voltages,
547f384f 1134 },
547f384f
LJ		 1135 .update_bank = 0x03,
1136 .update_reg = 0x83,
1137 .update_mask = 0x02,
1138 .update_val = 0x02,
8a3b1b87
LJ		 1139 .voltage_bank = 0x01,
1140 .voltage_reg = 0x57,
1141 .voltage_mask = 0x7,
1142 .voltage_shift = 4,
547f384f
LJ		 1143 },
1144 [AB8505_LDO_ANAMIC1] = {
1145 .desc = {
1146 .name = "LDO-ANAMIC1",
3fe52289 1147 .ops = &ab8500_regulator_anamic_mode_ops,
547f384f 1148 .type = REGULATOR_VOLTAGE,
0b946411 1149 .id = AB8505_LDO_ANAMIC1,
547f384f
LJ		 1150 .owner = THIS_MODULE,
1151 .n_voltages = 1,
b080c78a 1152 .volt_table = fixed_2050000_voltage,
547f384f 1153 },
4c84b4dd 1154 .shared_mode = &ldo_anamic1_shared,
547f384f
LJ		 1155 .update_bank = 0x03,
1156 .update_reg = 0x83,
1157 .update_mask = 0x08,
1158 .update_val = 0x08,
3fe52289
LJ		 1159 .mode_bank = 0x01,
1160 .mode_reg = 0x54,
1161 .mode_mask = 0x04,
1162 .mode_val_idle = 0x04,
1163 .mode_val_normal = 0x00,
547f384f
LJ		 1164 },
1165 [AB8505_LDO_ANAMIC2] = {
1166 .desc = {
1167 .name = "LDO-ANAMIC2",
3fe52289 1168 .ops = &ab8500_regulator_anamic_mode_ops,
547f384f 1169 .type = REGULATOR_VOLTAGE,
0b946411 1170 .id = AB8505_LDO_ANAMIC2,
547f384f
LJ		 1171 .owner = THIS_MODULE,
1172 .n_voltages = 1,
b080c78a 1173 .volt_table = fixed_2050000_voltage,
547f384f 1174 },
3fe52289 1175 .shared_mode = &ldo_anamic2_shared,
547f384f
LJ		 1176 .update_bank = 0x03,
1177 .update_reg = 0x83,
1178 .update_mask = 0x10,
1179 .update_val = 0x10,
3fe52289
LJ		 1180 .mode_bank = 0x01,
1181 .mode_reg = 0x54,
1182 .mode_mask = 0x04,
1183 .mode_val_idle = 0x04,
1184 .mode_val_normal = 0x00,
547f384f
LJ		 1185 },
1186 [AB8505_LDO_AUX8] = {
1187 .desc = {
1188 .name = "LDO-AUX8",
1189 .ops = &ab8500_regulator_ops,
1190 .type = REGULATOR_VOLTAGE,
1191 .id = AB8505_LDO_AUX8,
1192 .owner = THIS_MODULE,
1193 .n_voltages = 1,
b080c78a 1194 .volt_table = fixed_1800000_voltage,
547f384f 1195 },
547f384f
LJ		 1196 .update_bank = 0x03,
1197 .update_reg = 0x83,
1198 .update_mask = 0x04,
1199 .update_val = 0x04,
1200 },
1201 /*
1202 * Regulators with fixed voltage and normal/idle modes
1203 */
1204 [AB8505_LDO_ANA] = {
1205 .desc = {
1206 .name = "LDO-ANA",
8a3b1b87 1207 .ops = &ab8500_regulator_volt_mode_ops,
547f384f 1208 .type = REGULATOR_VOLTAGE,
0b946411 1209 .id = AB8505_LDO_ANA,
547f384f 1210 .owner = THIS_MODULE,
8a3b1b87
LJ		 1211 .n_voltages = ARRAY_SIZE(ldo_vana_voltages),
1212 .volt_table = ldo_vana_voltages,
547f384f 1213 },
547f384f
LJ		 1214 .load_lp_uA = 1000,
1215 .update_bank = 0x04,
1216 .update_reg = 0x06,
1217 .update_mask = 0x0c,
1218 .update_val = 0x04,
1219 .update_val_idle = 0x0c,
1220 .update_val_normal = 0x04,
8a3b1b87
LJ		 1221 .voltage_bank = 0x04,
1222 .voltage_reg = 0x29,
1223 .voltage_mask = 0x7,
547f384f
LJ		 1224 },
1225};
1226
8e6a8d7d
LJ		 1227/* AB9540 regulator information */
1228static struct ab8500_regulator_info
1229 ab9540_regulator_info[AB9540_NUM_REGULATORS] = {
1230 /*
1231 * Variable Voltage Regulators
1232 * name, min mV, max mV,
1233 * update bank, reg, mask, enable val
d3193103 1234 * volt bank, reg, mask
8e6a8d7d
LJ		 1235 */
1236 [AB9540_LDO_AUX1] = {
1237 .desc = {
1238 .name = "LDO-AUX1",
1239 .ops = &ab8500_regulator_volt_mode_ops,
1240 .type = REGULATOR_VOLTAGE,
0b946411 1241 .id = AB9540_LDO_AUX1,
8e6a8d7d
LJ		 1242 .owner = THIS_MODULE,
1243 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1244 .volt_table = ldo_vauxn_voltages,
8e6a8d7d 1245 },
8e6a8d7d
LJ		 1246 .load_lp_uA = 5000,
1247 .update_bank = 0x04,
1248 .update_reg = 0x09,
1249 .update_mask = 0x03,
1250 .update_val = 0x01,
1251 .update_val_idle = 0x03,
1252 .update_val_normal = 0x01,
1253 .voltage_bank = 0x04,
1254 .voltage_reg = 0x1f,
1255 .voltage_mask = 0x0f,
8e6a8d7d
LJ		 1256 },
1257 [AB9540_LDO_AUX2] = {
1258 .desc = {
1259 .name = "LDO-AUX2",
1260 .ops = &ab8500_regulator_volt_mode_ops,
1261 .type = REGULATOR_VOLTAGE,
0b946411 1262 .id = AB9540_LDO_AUX2,
8e6a8d7d
LJ		 1263 .owner = THIS_MODULE,
1264 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1265 .volt_table = ldo_vauxn_voltages,
8e6a8d7d 1266 },
8e6a8d7d
LJ		 1267 .load_lp_uA = 5000,
1268 .update_bank = 0x04,
1269 .update_reg = 0x09,
1270 .update_mask = 0x0c,
1271 .update_val = 0x04,
1272 .update_val_idle = 0x0c,
1273 .update_val_normal = 0x04,
1274 .voltage_bank = 0x04,
1275 .voltage_reg = 0x20,
1276 .voltage_mask = 0x0f,
8e6a8d7d
LJ		 1277 },
1278 [AB9540_LDO_AUX3] = {
1279 .desc = {
1280 .name = "LDO-AUX3",
1281 .ops = &ab8500_regulator_volt_mode_ops,
1282 .type = REGULATOR_VOLTAGE,
0b946411 1283 .id = AB9540_LDO_AUX3,
8e6a8d7d
LJ		 1284 .owner = THIS_MODULE,
1285 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
62ab4111 1286 .volt_table = ldo_vaux3_voltages,
8e6a8d7d 1287 },
8e6a8d7d
LJ		 1288 .load_lp_uA = 5000,
1289 .update_bank = 0x04,
1290 .update_reg = 0x0a,
1291 .update_mask = 0x03,
1292 .update_val = 0x01,
1293 .update_val_idle = 0x03,
1294 .update_val_normal = 0x01,
1295 .voltage_bank = 0x04,
1296 .voltage_reg = 0x21,
1297 .voltage_mask = 0x07,
8e6a8d7d
LJ		 1298 },
1299 [AB9540_LDO_AUX4] = {
1300 .desc = {
1301 .name = "LDO-AUX4",
1302 .ops = &ab8500_regulator_volt_mode_ops,
1303 .type = REGULATOR_VOLTAGE,
1304 .id = AB9540_LDO_AUX4,
1305 .owner = THIS_MODULE,
1306 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1307 .volt_table = ldo_vauxn_voltages,
8e6a8d7d 1308 },
8e6a8d7d
LJ		 1309 .load_lp_uA = 5000,
1310 /* values for Vaux4Regu register */
1311 .update_bank = 0x04,
1312 .update_reg = 0x2e,
1313 .update_mask = 0x03,
1314 .update_val = 0x01,
1315 .update_val_idle = 0x03,
1316 .update_val_normal = 0x01,
1317 /* values for Vaux4SEL register */
1318 .voltage_bank = 0x04,
1319 .voltage_reg = 0x2f,
1320 .voltage_mask = 0x0f,
8e6a8d7d
LJ		 1321 },
1322 [AB9540_LDO_INTCORE] = {
1323 .desc = {
1324 .name = "LDO-INTCORE",
1325 .ops = &ab8500_regulator_volt_mode_ops,
1326 .type = REGULATOR_VOLTAGE,
0b946411 1327 .id = AB9540_LDO_INTCORE,
8e6a8d7d
LJ		 1328 .owner = THIS_MODULE,
1329 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
62ab4111 1330 .volt_table = ldo_vintcore_voltages,
8e6a8d7d 1331 },
8e6a8d7d
LJ		 1332 .load_lp_uA = 5000,
1333 .update_bank = 0x03,
1334 .update_reg = 0x80,
1335 .update_mask = 0x44,
1336 .update_val = 0x44,
1337 .update_val_idle = 0x44,
1338 .update_val_normal = 0x04,
1339 .voltage_bank = 0x03,
1340 .voltage_reg = 0x80,
1341 .voltage_mask = 0x38,
8e6a8d7d
LJ		 1342 .voltage_shift = 3,
1343 },
6909b452 1344
8e6a8d7d
LJ		 1345 /*
1346 * Fixed Voltage Regulators
1347 * name, fixed mV,
1348 * update bank, reg, mask, enable val
1349 */
1350 [AB9540_LDO_TVOUT] = {
1351 .desc = {
1352 .name = "LDO-TVOUT",
1353 .ops = &ab8500_regulator_mode_ops,
1354 .type = REGULATOR_VOLTAGE,
0b946411 1355 .id = AB9540_LDO_TVOUT,
8e6a8d7d
LJ		 1356 .owner = THIS_MODULE,
1357 .n_voltages = 1,
b080c78a 1358 .volt_table = fixed_2000000_voltage,
a4d68468 1359 .enable_time = 10000,
8e6a8d7d 1360 },
8e6a8d7d
LJ		 1361 .load_lp_uA = 1000,
1362 .update_bank = 0x03,
1363 .update_reg = 0x80,
1364 .update_mask = 0x82,
1365 .update_val = 0x02,
1366 .update_val_idle = 0x82,
1367 .update_val_normal = 0x02,
1368 },
1369 [AB9540_LDO_USB] = {
1370 .desc = {
1371 .name = "LDO-USB",
1372 .ops = &ab8500_regulator_ops,
1373 .type = REGULATOR_VOLTAGE,
1374 .id = AB9540_LDO_USB,
1375 .owner = THIS_MODULE,
1376 .n_voltages = 1,
b080c78a 1377 .volt_table = fixed_3300000_voltage,
8e6a8d7d 1378 },
8e6a8d7d
LJ		 1379 .update_bank = 0x03,
1380 .update_reg = 0x82,
1381 .update_mask = 0x03,
1382 .update_val = 0x01,
1383 .update_val_idle = 0x03,
1384 .update_val_normal = 0x01,
1385 },
1386 [AB9540_LDO_AUDIO] = {
1387 .desc = {
1388 .name = "LDO-AUDIO",
1389 .ops = &ab8500_regulator_ops,
1390 .type = REGULATOR_VOLTAGE,
0b946411 1391 .id = AB9540_LDO_AUDIO,
8e6a8d7d
LJ		 1392 .owner = THIS_MODULE,
1393 .n_voltages = 1,
b080c78a 1394 .volt_table = fixed_2000000_voltage,
8e6a8d7d 1395 },
8e6a8d7d
LJ		 1396 .update_bank = 0x03,
1397 .update_reg = 0x83,
1398 .update_mask = 0x02,
1399 .update_val = 0x02,
1400 },
1401 [AB9540_LDO_ANAMIC1] = {
1402 .desc = {
1403 .name = "LDO-ANAMIC1",
1404 .ops = &ab8500_regulator_ops,
1405 .type = REGULATOR_VOLTAGE,
0b946411 1406 .id = AB9540_LDO_ANAMIC1,
8e6a8d7d
LJ		 1407 .owner = THIS_MODULE,
1408 .n_voltages = 1,
b080c78a 1409 .volt_table = fixed_2050000_voltage,
8e6a8d7d 1410 },
8e6a8d7d
LJ		 1411 .update_bank = 0x03,
1412 .update_reg = 0x83,
1413 .update_mask = 0x08,
1414 .update_val = 0x08,
1415 },
1416 [AB9540_LDO_ANAMIC2] = {
1417 .desc = {
1418 .name = "LDO-ANAMIC2",
1419 .ops = &ab8500_regulator_ops,
1420 .type = REGULATOR_VOLTAGE,
0b946411 1421 .id = AB9540_LDO_ANAMIC2,
8e6a8d7d
LJ		 1422 .owner = THIS_MODULE,
1423 .n_voltages = 1,
b080c78a 1424 .volt_table = fixed_2050000_voltage,
8e6a8d7d 1425 },
8e6a8d7d
LJ		 1426 .update_bank = 0x03,
1427 .update_reg = 0x83,
1428 .update_mask = 0x10,
1429 .update_val = 0x10,
1430 },
1431 [AB9540_LDO_DMIC] = {
1432 .desc = {
1433 .name = "LDO-DMIC",
1434 .ops = &ab8500_regulator_ops,
1435 .type = REGULATOR_VOLTAGE,
0b946411 1436 .id = AB9540_LDO_DMIC,
8e6a8d7d
LJ		 1437 .owner = THIS_MODULE,
1438 .n_voltages = 1,
b080c78a 1439 .volt_table = fixed_1800000_voltage,
8e6a8d7d 1440 },
8e6a8d7d
LJ		 1441 .update_bank = 0x03,
1442 .update_reg = 0x83,
1443 .update_mask = 0x04,
1444 .update_val = 0x04,
1445 },
1446
1447 /*
1448 * Regulators with fixed voltage and normal/idle modes
1449 */
1450 [AB9540_LDO_ANA] = {
1451 .desc = {
1452 .name = "LDO-ANA",
1453 .ops = &ab8500_regulator_mode_ops,
1454 .type = REGULATOR_VOLTAGE,
0b946411 1455 .id = AB9540_LDO_ANA,
8e6a8d7d
LJ		 1456 .owner = THIS_MODULE,
1457 .n_voltages = 1,
b080c78a 1458 .volt_table = fixed_1200000_voltage,
8e6a8d7d 1459 },
8e6a8d7d
LJ		 1460 .load_lp_uA = 1000,
1461 .update_bank = 0x04,
1462 .update_reg = 0x06,
1463 .update_mask = 0x0c,
1464 .update_val = 0x08,
1465 .update_val_idle = 0x0c,
1466 .update_val_normal = 0x08,
1467 },
c789ca20
SI		 1468};
1469
ae0a9a3e
LJ		 1470/* AB8540 regulator information */
1471static struct ab8500_regulator_info
1472 ab8540_regulator_info[AB8540_NUM_REGULATORS] = {
1473 /*
1474 * Variable Voltage Regulators
1475 * name, min mV, max mV,
1476 * update bank, reg, mask, enable val
d3193103 1477 * volt bank, reg, mask
ae0a9a3e
LJ		 1478 */
1479 [AB8540_LDO_AUX1] = {
1480 .desc = {
1481 .name = "LDO-AUX1",
1482 .ops = &ab8500_regulator_volt_mode_ops,
1483 .type = REGULATOR_VOLTAGE,
0b946411 1484 .id = AB8540_LDO_AUX1,
ae0a9a3e
LJ		 1485 .owner = THIS_MODULE,
1486 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1487 .volt_table = ldo_vauxn_voltages,
ae0a9a3e
LJ		 1488 },
1489 .load_lp_uA = 5000,
1490 .update_bank = 0x04,
1491 .update_reg = 0x09,
1492 .update_mask = 0x03,
1493 .update_val = 0x01,
1494 .update_val_idle = 0x03,
1495 .update_val_normal = 0x01,
1496 .voltage_bank = 0x04,
1497 .voltage_reg = 0x1f,
1498 .voltage_mask = 0x0f,
ae0a9a3e
LJ		 1499 },
1500 [AB8540_LDO_AUX2] = {
1501 .desc = {
1502 .name = "LDO-AUX2",
1503 .ops = &ab8500_regulator_volt_mode_ops,
1504 .type = REGULATOR_VOLTAGE,
0b946411 1505 .id = AB8540_LDO_AUX2,
ae0a9a3e
LJ		 1506 .owner = THIS_MODULE,
1507 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1508 .volt_table = ldo_vauxn_voltages,
ae0a9a3e
LJ		 1509 },
1510 .load_lp_uA = 5000,
1511 .update_bank = 0x04,
1512 .update_reg = 0x09,
1513 .update_mask = 0x0c,
1514 .update_val = 0x04,
1515 .update_val_idle = 0x0c,
1516 .update_val_normal = 0x04,
1517 .voltage_bank = 0x04,
1518 .voltage_reg = 0x20,
1519 .voltage_mask = 0x0f,
ae0a9a3e
LJ		 1520 },
1521 [AB8540_LDO_AUX3] = {
1522 .desc = {
1523 .name = "LDO-AUX3",
d7607baf 1524 .ops = &ab8540_aux3_regulator_volt_mode_ops,
ae0a9a3e 1525 .type = REGULATOR_VOLTAGE,
0b946411 1526 .id = AB8540_LDO_AUX3,
ae0a9a3e
LJ		 1527 .owner = THIS_MODULE,
1528 .n_voltages = ARRAY_SIZE(ldo_vaux3_ab8540_voltages),
62ab4111 1529 .volt_table = ldo_vaux3_ab8540_voltages,
ae0a9a3e
LJ		 1530 },
1531 .load_lp_uA = 5000,
1532 .update_bank = 0x04,
1533 .update_reg = 0x0a,
1534 .update_mask = 0x03,
1535 .update_val = 0x01,
1536 .update_val_idle = 0x03,
1537 .update_val_normal = 0x01,
1538 .voltage_bank = 0x04,
1539 .voltage_reg = 0x21,
1540 .voltage_mask = 0x07,
d7607baf
LJ		 1541 .expand_register = {
1542 .voltage_limit = 8,
1543 .voltage_bank = 0x04,
1544 .voltage_reg = 0x01,
1545 .voltage_mask = 0x10,
1546 .voltage_shift = 1,
1547 }
ae0a9a3e
LJ		 1548 },
1549 [AB8540_LDO_AUX4] = {
1550 .desc = {
1551 .name = "LDO-AUX4",
1552 .ops = &ab8500_regulator_volt_mode_ops,
1553 .type = REGULATOR_VOLTAGE,
0b946411 1554 .id = AB8540_LDO_AUX4,
ae0a9a3e
LJ		 1555 .owner = THIS_MODULE,
1556 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1557 .volt_table = ldo_vauxn_voltages,
ae0a9a3e
LJ		 1558 },
1559 .load_lp_uA = 5000,
1560 /* values for Vaux4Regu register */
1561 .update_bank = 0x04,
1562 .update_reg = 0x2e,
1563 .update_mask = 0x03,
1564 .update_val = 0x01,
1565 .update_val_idle = 0x03,
1566 .update_val_normal = 0x01,
1567 /* values for Vaux4SEL register */
1568 .voltage_bank = 0x04,
1569 .voltage_reg = 0x2f,
1570 .voltage_mask = 0x0f,
ae0a9a3e 1571 },
684d5ce4
ZH		 1572 [AB8540_LDO_AUX5] = {
1573 .desc = {
1574 .name = "LDO-AUX5",
1575 .ops = &ab8500_regulator_volt_mode_ops,
1576 .type = REGULATOR_VOLTAGE,
1577 .id = AB8540_LDO_AUX5,
1578 .owner = THIS_MODULE,
1579 .n_voltages = ARRAY_SIZE(ldo_vaux56_ab8540_voltages),
d3193103 1580 .volt_table = ldo_vaux56_ab8540_voltages,
684d5ce4
ZH		 1581 },
1582 .load_lp_uA = 20000,
1583 /* values for Vaux5Regu register */
1584 .update_bank = 0x04,
1585 .update_reg = 0x32,
1586 .update_mask = 0x03,
1587 .update_val = 0x01,
1588 .update_val_idle = 0x03,
1589 .update_val_normal = 0x01,
1590 /* values for Vaux5SEL register */
1591 .voltage_bank = 0x04,
1592 .voltage_reg = 0x33,
1593 .voltage_mask = 0x3f,
684d5ce4
ZH		 1594 },
1595 [AB8540_LDO_AUX6] = {
1596 .desc = {
1597 .name = "LDO-AUX6",
1598 .ops = &ab8500_regulator_volt_mode_ops,
1599 .type = REGULATOR_VOLTAGE,
1600 .id = AB8540_LDO_AUX6,
1601 .owner = THIS_MODULE,
1602 .n_voltages = ARRAY_SIZE(ldo_vaux56_ab8540_voltages),
d3193103 1603 .volt_table = ldo_vaux56_ab8540_voltages,
684d5ce4
ZH		 1604 },
1605 .load_lp_uA = 20000,
1606 /* values for Vaux6Regu register */
1607 .update_bank = 0x04,
1608 .update_reg = 0x35,
1609 .update_mask = 0x03,
1610 .update_val = 0x01,
1611 .update_val_idle = 0x03,
1612 .update_val_normal = 0x01,
1613 /* values for Vaux6SEL register */
1614 .voltage_bank = 0x04,
1615 .voltage_reg = 0x36,
1616 .voltage_mask = 0x3f,
684d5ce4 1617 },
ae0a9a3e
LJ		 1618 [AB8540_LDO_INTCORE] = {
1619 .desc = {
1620 .name = "LDO-INTCORE",
1621 .ops = &ab8500_regulator_volt_mode_ops,
1622 .type = REGULATOR_VOLTAGE,
0b946411 1623 .id = AB8540_LDO_INTCORE,
ae0a9a3e
LJ		 1624 .owner = THIS_MODULE,
1625 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
62ab4111 1626 .volt_table = ldo_vintcore_voltages,
ae0a9a3e
LJ		 1627 },
1628 .load_lp_uA = 5000,
1629 .update_bank = 0x03,
1630 .update_reg = 0x80,
1631 .update_mask = 0x44,
1632 .update_val = 0x44,
1633 .update_val_idle = 0x44,
1634 .update_val_normal = 0x04,
1635 .voltage_bank = 0x03,
1636 .voltage_reg = 0x80,
1637 .voltage_mask = 0x38,
ae0a9a3e
LJ		 1638 .voltage_shift = 3,
1639 },
1640
1641 /*
1642 * Fixed Voltage Regulators
1643 * name, fixed mV,
1644 * update bank, reg, mask, enable val
1645 */
1646 [AB8540_LDO_TVOUT] = {
1647 .desc = {
1648 .name = "LDO-TVOUT",
1649 .ops = &ab8500_regulator_mode_ops,
1650 .type = REGULATOR_VOLTAGE,
0b946411 1651 .id = AB8540_LDO_TVOUT,
ae0a9a3e
LJ		 1652 .owner = THIS_MODULE,
1653 .n_voltages = 1,
aca45e9e 1654 .volt_table = fixed_2000000_voltage,
a4d68468 1655 .enable_time = 10000,
ae0a9a3e 1656 },
ae0a9a3e
LJ		 1657 .load_lp_uA = 1000,
1658 .update_bank = 0x03,
1659 .update_reg = 0x80,
1660 .update_mask = 0x82,
1661 .update_val = 0x02,
1662 .update_val_idle = 0x82,
1663 .update_val_normal = 0x02,
1664 },
1665 [AB8540_LDO_AUDIO] = {
1666 .desc = {
1667 .name = "LDO-AUDIO",
1668 .ops = &ab8500_regulator_ops,
1669 .type = REGULATOR_VOLTAGE,
0b946411 1670 .id = AB8540_LDO_AUDIO,
ae0a9a3e
LJ		 1671 .owner = THIS_MODULE,
1672 .n_voltages = 1,
b080c78a 1673 .volt_table = fixed_2000000_voltage,
ae0a9a3e
LJ		 1674 },
1675 .update_bank = 0x03,
1676 .update_reg = 0x83,
1677 .update_mask = 0x02,
1678 .update_val = 0x02,
1679 },
1680 [AB8540_LDO_ANAMIC1] = {
1681 .desc = {
1682 .name = "LDO-ANAMIC1",
4c84b4dd 1683 .ops = &ab8500_regulator_anamic_mode_ops,
ae0a9a3e 1684 .type = REGULATOR_VOLTAGE,
0b946411 1685 .id = AB8540_LDO_ANAMIC1,
ae0a9a3e
LJ		 1686 .owner = THIS_MODULE,
1687 .n_voltages = 1,
b080c78a 1688 .volt_table = fixed_2050000_voltage,
ae0a9a3e 1689 },
4c84b4dd 1690 .shared_mode = &ab8540_ldo_anamic1_shared,
ae0a9a3e
LJ		 1691 .update_bank = 0x03,
1692 .update_reg = 0x83,
1693 .update_mask = 0x08,
1694 .update_val = 0x08,
4c84b4dd
LJ		 1695 .mode_bank = 0x03,
1696 .mode_reg = 0x83,
1697 .mode_mask = 0x20,
1698 .mode_val_idle = 0x20,
1699 .mode_val_normal = 0x00,
ae0a9a3e
LJ		 1700 },
1701 [AB8540_LDO_ANAMIC2] = {
1702 .desc = {
1703 .name = "LDO-ANAMIC2",
4c84b4dd 1704 .ops = &ab8500_regulator_anamic_mode_ops,
ae0a9a3e 1705 .type = REGULATOR_VOLTAGE,
0b946411 1706 .id = AB8540_LDO_ANAMIC2,
ae0a9a3e
LJ		 1707 .owner = THIS_MODULE,
1708 .n_voltages = 1,
b080c78a 1709 .volt_table = fixed_2050000_voltage,
ae0a9a3e 1710 },
4c84b4dd 1711 .shared_mode = &ab8540_ldo_anamic2_shared,
ae0a9a3e
LJ		 1712 .update_bank = 0x03,
1713 .update_reg = 0x83,
1714 .update_mask = 0x10,
1715 .update_val = 0x10,
4c84b4dd
LJ		 1716 .mode_bank = 0x03,
1717 .mode_reg = 0x83,
1718 .mode_mask = 0x20,
1719 .mode_val_idle = 0x20,
1720 .mode_val_normal = 0x00,
ae0a9a3e
LJ		 1721 },
1722 [AB8540_LDO_DMIC] = {
1723 .desc = {
1724 .name = "LDO-DMIC",
4c84b4dd 1725 .ops = &ab8500_regulator_volt_mode_ops,
ae0a9a3e 1726 .type = REGULATOR_VOLTAGE,
0b946411 1727 .id = AB8540_LDO_DMIC,
ae0a9a3e 1728 .owner = THIS_MODULE,
4c84b4dd 1729 .n_voltages = ARRAY_SIZE(ldo_vdmic_voltages),
d3193103 1730 .volt_table = ldo_vdmic_voltages,
ae0a9a3e 1731 },
4c84b4dd 1732 .load_lp_uA = 1000,
ae0a9a3e
LJ		 1733 .update_bank = 0x03,
1734 .update_reg = 0x83,
1735 .update_mask = 0x04,
1736 .update_val = 0x04,
4c84b4dd
LJ		 1737 .voltage_bank = 0x03,
1738 .voltage_reg = 0x83,
1739 .voltage_mask = 0xc0,
ae0a9a3e
LJ		 1740 },
1741
1742 /*
1743 * Regulators with fixed voltage and normal/idle modes
1744 */
1745 [AB8540_LDO_ANA] = {
1746 .desc = {
1747 .name = "LDO-ANA",
1748 .ops = &ab8500_regulator_mode_ops,
1749 .type = REGULATOR_VOLTAGE,
0b946411 1750 .id = AB8540_LDO_ANA,
ae0a9a3e
LJ		 1751 .owner = THIS_MODULE,
1752 .n_voltages = 1,
b080c78a 1753 .volt_table = fixed_1200000_voltage,
ae0a9a3e
LJ		 1754 },
1755 .load_lp_uA = 1000,
1756 .update_bank = 0x04,
1757 .update_reg = 0x06,
1758 .update_mask = 0x0c,
1759 .update_val = 0x04,
1760 .update_val_idle = 0x0c,
1761 .update_val_normal = 0x04,
1762 },
1763 [AB8540_LDO_SDIO] = {
1764 .desc = {
1765 .name = "LDO-SDIO",
1766 .ops = &ab8500_regulator_volt_mode_ops,
1767 .type = REGULATOR_VOLTAGE,
1768 .id = AB8540_LDO_SDIO,
1769 .owner = THIS_MODULE,
62ab4111
LJ		 1770 .n_voltages = ARRAY_SIZE(ldo_sdio_voltages),
1771 .volt_table = ldo_sdio_voltages,
ae0a9a3e 1772 },
ae0a9a3e
LJ		 1773 .load_lp_uA = 5000,
1774 .update_bank = 0x03,
1775 .update_reg = 0x88,
1776 .update_mask = 0x30,
1777 .update_val = 0x10,
1778 .update_val_idle = 0x30,
1779 .update_val_normal = 0x10,
1780 .voltage_bank = 0x03,
1781 .voltage_reg = 0x88,
1782 .voltage_mask = 0x07,
ae0a9a3e
LJ		 1783 },
1784};
1785
3fe52289
LJ		 1786static struct ab8500_shared_mode ldo_anamic1_shared = {
1787 .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC2],
1788};
1789
1790static struct ab8500_shared_mode ldo_anamic2_shared = {
1791 .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC1],
1792};
1793
4c84b4dd
LJ		 1794static struct ab8500_shared_mode ab8540_ldo_anamic1_shared = {
1795 .shared_regulator = &ab8540_regulator_info[AB8540_LDO_ANAMIC2],
1796};
1797
1798static struct ab8500_shared_mode ab8540_ldo_anamic2_shared = {
1799 .shared_regulator = &ab8540_regulator_info[AB8540_LDO_ANAMIC1],
1800};
1801
79568b94
BJ		 1802struct ab8500_reg_init {
1803 u8 bank;
1804 u8 addr;
1805 u8 mask;
1806};
1807
1808#define REG_INIT(_id, _bank, _addr, _mask) \
1809 [_id] = { \
1810 .bank = _bank, \
1811 .addr = _addr, \
1812 .mask = _mask, \
1813 }
1814
8e6a8d7d 1815/* AB8500 register init */
79568b94
BJ		 1816static struct ab8500_reg_init ab8500_reg_init[] = {
1817 /*
33bc8f46 1818 * 0x30, VanaRequestCtrl
79568b94
BJ		 1819 * 0xc0, VextSupply1RequestCtrl
1820 */
43a5911b 1821 REG_INIT(AB8500_REGUREQUESTCTRL2, 0x03, 0x04, 0xf0),
79568b94
BJ		 1822 /*
1823 * 0x03, VextSupply2RequestCtrl
1824 * 0x0c, VextSupply3RequestCtrl
1825 * 0x30, Vaux1RequestCtrl
1826 * 0xc0, Vaux2RequestCtrl
1827 */
1828 REG_INIT(AB8500_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
1829 /*
1830 * 0x03, Vaux3RequestCtrl
1831 * 0x04, SwHPReq
1832 */
1833 REG_INIT(AB8500_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
1834 /*
1835 * 0x08, VanaSysClkReq1HPValid
1836 * 0x20, Vaux1SysClkReq1HPValid
1837 * 0x40, Vaux2SysClkReq1HPValid
1838 * 0x80, Vaux3SysClkReq1HPValid
1839 */
43a5911b 1840 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xe8),
79568b94
BJ		 1841 /*
1842 * 0x10, VextSupply1SysClkReq1HPValid
1843 * 0x20, VextSupply2SysClkReq1HPValid
1844 * 0x40, VextSupply3SysClkReq1HPValid
1845 */
43a5911b 1846 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x70),
79568b94
BJ		 1847 /*
1848 * 0x08, VanaHwHPReq1Valid
1849 * 0x20, Vaux1HwHPReq1Valid
1850 * 0x40, Vaux2HwHPReq1Valid
1851 * 0x80, Vaux3HwHPReq1Valid
1852 */
43a5911b 1853 REG_INIT(AB8500_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xe8),
79568b94
BJ		 1854 /*
1855 * 0x01, VextSupply1HwHPReq1Valid
1856 * 0x02, VextSupply2HwHPReq1Valid
1857 * 0x04, VextSupply3HwHPReq1Valid
1858 */
43a5911b 1859 REG_INIT(AB8500_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07),
79568b94
BJ		 1860 /*
1861 * 0x08, VanaHwHPReq2Valid
1862 * 0x20, Vaux1HwHPReq2Valid
1863 * 0x40, Vaux2HwHPReq2Valid
1864 * 0x80, Vaux3HwHPReq2Valid
1865 */
43a5911b 1866 REG_INIT(AB8500_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xe8),
79568b94
BJ		 1867 /*
1868 * 0x01, VextSupply1HwHPReq2Valid
1869 * 0x02, VextSupply2HwHPReq2Valid
1870 * 0x04, VextSupply3HwHPReq2Valid
1871 */
43a5911b 1872 REG_INIT(AB8500_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07),
79568b94
BJ		 1873 /*
1874 * 0x20, VanaSwHPReqValid
1875 * 0x80, Vaux1SwHPReqValid
1876 */
43a5911b 1877 REG_INIT(AB8500_REGUSWHPREQVALID1, 0x03, 0x0d, 0xa0),
79568b94
BJ		 1878 /*
1879 * 0x01, Vaux2SwHPReqValid
1880 * 0x02, Vaux3SwHPReqValid
1881 * 0x04, VextSupply1SwHPReqValid
1882 * 0x08, VextSupply2SwHPReqValid
1883 * 0x10, VextSupply3SwHPReqValid
1884 */
43a5911b 1885 REG_INIT(AB8500_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f),
79568b94
BJ		 1886 /*
1887 * 0x02, SysClkReq2Valid1
43a5911b
LJ		 1888 * 0x04, SysClkReq3Valid1
1889 * 0x08, SysClkReq4Valid1
1890 * 0x10, SysClkReq5Valid1
1891 * 0x20, SysClkReq6Valid1
1892 * 0x40, SysClkReq7Valid1
79568b94
BJ		 1893 * 0x80, SysClkReq8Valid1
1894 */
1895 REG_INIT(AB8500_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
1896 /*
1897 * 0x02, SysClkReq2Valid2
43a5911b
LJ		 1898 * 0x04, SysClkReq3Valid2
1899 * 0x08, SysClkReq4Valid2
1900 * 0x10, SysClkReq5Valid2
1901 * 0x20, SysClkReq6Valid2
1902 * 0x40, SysClkReq7Valid2
79568b94
BJ		 1903 * 0x80, SysClkReq8Valid2
1904 */
1905 REG_INIT(AB8500_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
1906 /*
1907 * 0x02, VTVoutEna
1908 * 0x04, Vintcore12Ena
1909 * 0x38, Vintcore12Sel
1910 * 0x40, Vintcore12LP
1911 * 0x80, VTVoutLP
1912 */
1913 REG_INIT(AB8500_REGUMISC1, 0x03, 0x80, 0xfe),
1914 /*
1915 * 0x02, VaudioEna
1916 * 0x04, VdmicEna
1917 * 0x08, Vamic1Ena
1918 * 0x10, Vamic2Ena
1919 */
1920 REG_INIT(AB8500_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
1921 /*
1922 * 0x01, Vamic1_dzout
1923 * 0x02, Vamic2_dzout
1924 */
1925 REG_INIT(AB8500_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
d79df329 1926 /*
43a5911b 1927 * 0x03, VpllRegu (NOTE! PRCMU register bits)
33bc8f46 1928 * 0x0c, VanaRegu
79568b94
BJ		 1929 */
1930 REG_INIT(AB8500_VPLLVANAREGU, 0x04, 0x06, 0x0f),
1931 /*
1932 * 0x01, VrefDDREna
1933 * 0x02, VrefDDRSleepMode
1934 */
1935 REG_INIT(AB8500_VREFDDR, 0x04, 0x07, 0x03),
1936 /*
1937 * 0x03, VextSupply1Regu
1938 * 0x0c, VextSupply2Regu
1939 * 0x30, VextSupply3Regu
1940 * 0x40, ExtSupply2Bypass
1941 * 0x80, ExtSupply3Bypass
1942 */
1943 REG_INIT(AB8500_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
1944 /*
1945 * 0x03, Vaux1Regu
1946 * 0x0c, Vaux2Regu
1947 */
1948 REG_INIT(AB8500_VAUX12REGU, 0x04, 0x09, 0x0f),
1949 /*
1950 * 0x03, Vaux3Regu
1951 */
43a5911b 1952 REG_INIT(AB8500_VRF1VAUX3REGU, 0x04, 0x0a, 0x03),
79568b94
BJ		 1953 /*
1954 * 0x0f, Vaux1Sel
1955 */
1956 REG_INIT(AB8500_VAUX1SEL, 0x04, 0x1f, 0x0f),
1957 /*
1958 * 0x0f, Vaux2Sel
1959 */
1960 REG_INIT(AB8500_VAUX2SEL, 0x04, 0x20, 0x0f),
1961 /*
1962 * 0x07, Vaux3Sel
1963 */
43a5911b 1964 REG_INIT(AB8500_VRF1VAUX3SEL, 0x04, 0x21, 0x07),
79568b94
BJ		 1965 /*
1966 * 0x01, VextSupply12LP
1967 */
1968 REG_INIT(AB8500_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
1969 /*
1970 * 0x04, Vaux1Disch
1971 * 0x08, Vaux2Disch
1972 * 0x10, Vaux3Disch
1973 * 0x20, Vintcore12Disch
1974 * 0x40, VTVoutDisch
1975 * 0x80, VaudioDisch
1976 */
43a5911b 1977 REG_INIT(AB8500_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
79568b94
BJ		 1978 /*
1979 * 0x02, VanaDisch
1980 * 0x04, VdmicPullDownEna
1981 * 0x10, VdmicDisch
1982 */
43a5911b 1983 REG_INIT(AB8500_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
79568b94
BJ		 1984};
1985
547f384f
LJ		 1986/* AB8505 register init */
1987static struct ab8500_reg_init ab8505_reg_init[] = {
1988 /*
1989 * 0x03, VarmRequestCtrl
1990 * 0x0c, VsmpsCRequestCtrl
1991 * 0x30, VsmpsARequestCtrl
1992 * 0xc0, VsmpsBRequestCtrl
1993 */
1994 REG_INIT(AB8505_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
1995 /*
1996 * 0x03, VsafeRequestCtrl
1997 * 0x0c, VpllRequestCtrl
1998 * 0x30, VanaRequestCtrl
1999 */
2000 REG_INIT(AB8505_REGUREQUESTCTRL2, 0x03, 0x04, 0x3f),
2001 /*
2002 * 0x30, Vaux1RequestCtrl
2003 * 0xc0, Vaux2RequestCtrl
2004 */
2005 REG_INIT(AB8505_REGUREQUESTCTRL3, 0x03, 0x05, 0xf0),
2006 /*
2007 * 0x03, Vaux3RequestCtrl
2008 * 0x04, SwHPReq
2009 */
2010 REG_INIT(AB8505_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
2011 /*
2012 * 0x01, VsmpsASysClkReq1HPValid
2013 * 0x02, VsmpsBSysClkReq1HPValid
2014 * 0x04, VsafeSysClkReq1HPValid
2015 * 0x08, VanaSysClkReq1HPValid
2016 * 0x10, VpllSysClkReq1HPValid
2017 * 0x20, Vaux1SysClkReq1HPValid
2018 * 0x40, Vaux2SysClkReq1HPValid
2019 * 0x80, Vaux3SysClkReq1HPValid
2020 */
2021 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
2022 /*
2023 * 0x01, VsmpsCSysClkReq1HPValid
2024 * 0x02, VarmSysClkReq1HPValid
2025 * 0x04, VbbSysClkReq1HPValid
2026 * 0x08, VsmpsMSysClkReq1HPValid
2027 */
2028 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x0f),
2029 /*
2030 * 0x01, VsmpsAHwHPReq1Valid
2031 * 0x02, VsmpsBHwHPReq1Valid
2032 * 0x04, VsafeHwHPReq1Valid
2033 * 0x08, VanaHwHPReq1Valid
2034 * 0x10, VpllHwHPReq1Valid
2035 * 0x20, Vaux1HwHPReq1Valid
2036 * 0x40, Vaux2HwHPReq1Valid
2037 * 0x80, Vaux3HwHPReq1Valid
2038 */
2039 REG_INIT(AB8505_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
2040 /*
2041 * 0x08, VsmpsMHwHPReq1Valid
2042 */
2043 REG_INIT(AB8505_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x08),
2044 /*
2045 * 0x01, VsmpsAHwHPReq2Valid
2046 * 0x02, VsmpsBHwHPReq2Valid
2047 * 0x04, VsafeHwHPReq2Valid
2048 * 0x08, VanaHwHPReq2Valid
2049 * 0x10, VpllHwHPReq2Valid
2050 * 0x20, Vaux1HwHPReq2Valid
2051 * 0x40, Vaux2HwHPReq2Valid
2052 * 0x80, Vaux3HwHPReq2Valid
2053 */
2054 REG_INIT(AB8505_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
2055 /*
2056 * 0x08, VsmpsMHwHPReq2Valid
2057 */
2058 REG_INIT(AB8505_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x08),
2059 /*
2060 * 0x01, VsmpsCSwHPReqValid
2061 * 0x02, VarmSwHPReqValid
2062 * 0x04, VsmpsASwHPReqValid
2063 * 0x08, VsmpsBSwHPReqValid
2064 * 0x10, VsafeSwHPReqValid
2065 * 0x20, VanaSwHPReqValid
2066 * 0x40, VpllSwHPReqValid
2067 * 0x80, Vaux1SwHPReqValid
2068 */
2069 REG_INIT(AB8505_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2070 /*
2071 * 0x01, Vaux2SwHPReqValid
2072 * 0x02, Vaux3SwHPReqValid
2073 * 0x20, VsmpsMSwHPReqValid
2074 */
2075 REG_INIT(AB8505_REGUSWHPREQVALID2, 0x03, 0x0e, 0x23),
2076 /*
2077 * 0x02, SysClkReq2Valid1
2078 * 0x04, SysClkReq3Valid1
2079 * 0x08, SysClkReq4Valid1
2080 */
2081 REG_INIT(AB8505_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0x0e),
2082 /*
2083 * 0x02, SysClkReq2Valid2
2084 * 0x04, SysClkReq3Valid2
2085 * 0x08, SysClkReq4Valid2
2086 */
2087 REG_INIT(AB8505_REGUSYSCLKREQVALID2, 0x03, 0x10, 0x0e),
2088 /*
2089 * 0x01, Vaux4SwHPReqValid
2090 * 0x02, Vaux4HwHPReq2Valid
2091 * 0x04, Vaux4HwHPReq1Valid
2092 * 0x08, Vaux4SysClkReq1HPValid
2093 */
2094 REG_INIT(AB8505_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2095 /*
2096 * 0x02, VadcEna
2097 * 0x04, VintCore12Ena
2098 * 0x38, VintCore12Sel
2099 * 0x40, VintCore12LP
2100 * 0x80, VadcLP
2101 */
2102 REG_INIT(AB8505_REGUMISC1, 0x03, 0x80, 0xfe),
2103 /*
2104 * 0x02, VaudioEna
2105 * 0x04, VdmicEna
2106 * 0x08, Vamic1Ena
2107 * 0x10, Vamic2Ena
2108 */
2109 REG_INIT(AB8505_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
2110 /*
2111 * 0x01, Vamic1_dzout
2112 * 0x02, Vamic2_dzout
2113 */
2114 REG_INIT(AB8505_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2115 /*
2116 * 0x03, VsmpsARegu
2117 * 0x0c, VsmpsASelCtrl
2118 * 0x10, VsmpsAAutoMode
2119 * 0x20, VsmpsAPWMMode
2120 */
2121 REG_INIT(AB8505_VSMPSAREGU, 0x04, 0x03, 0x3f),
2122 /*
2123 * 0x03, VsmpsBRegu
2124 * 0x0c, VsmpsBSelCtrl
2125 * 0x10, VsmpsBAutoMode
2126 * 0x20, VsmpsBPWMMode
2127 */
2128 REG_INIT(AB8505_VSMPSBREGU, 0x04, 0x04, 0x3f),
2129 /*
2130 * 0x03, VsafeRegu
2131 * 0x0c, VsafeSelCtrl
2132 * 0x10, VsafeAutoMode
2133 * 0x20, VsafePWMMode
2134 */
2135 REG_INIT(AB8505_VSAFEREGU, 0x04, 0x05, 0x3f),
2136 /*
2137 * 0x03, VpllRegu (NOTE! PRCMU register bits)
2138 * 0x0c, VanaRegu
2139 */
2140 REG_INIT(AB8505_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2141 /*
2142 * 0x03, VextSupply1Regu
2143 * 0x0c, VextSupply2Regu
2144 * 0x30, VextSupply3Regu
2145 * 0x40, ExtSupply2Bypass
2146 * 0x80, ExtSupply3Bypass
2147 */
2148 REG_INIT(AB8505_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2149 /*
2150 * 0x03, Vaux1Regu
2151 * 0x0c, Vaux2Regu
2152 */
2153 REG_INIT(AB8505_VAUX12REGU, 0x04, 0x09, 0x0f),
2154 /*
2155 * 0x0f, Vaux3Regu
2156 */
2157 REG_INIT(AB8505_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2158 /*
2159 * 0x3f, VsmpsASel1
2160 */
2161 REG_INIT(AB8505_VSMPSASEL1, 0x04, 0x13, 0x3f),
2162 /*
2163 * 0x3f, VsmpsASel2
2164 */
2165 REG_INIT(AB8505_VSMPSASEL2, 0x04, 0x14, 0x3f),
2166 /*
2167 * 0x3f, VsmpsASel3
2168 */
2169 REG_INIT(AB8505_VSMPSASEL3, 0x04, 0x15, 0x3f),
2170 /*
2171 * 0x3f, VsmpsBSel1
2172 */
2173 REG_INIT(AB8505_VSMPSBSEL1, 0x04, 0x17, 0x3f),
2174 /*
2175 * 0x3f, VsmpsBSel2
2176 */
2177 REG_INIT(AB8505_VSMPSBSEL2, 0x04, 0x18, 0x3f),
2178 /*
2179 * 0x3f, VsmpsBSel3
2180 */
2181 REG_INIT(AB8505_VSMPSBSEL3, 0x04, 0x19, 0x3f),
2182 /*
2183 * 0x7f, VsafeSel1
2184 */
2185 REG_INIT(AB8505_VSAFESEL1, 0x04, 0x1b, 0x7f),
2186 /*
2187 * 0x3f, VsafeSel2
2188 */
2189 REG_INIT(AB8505_VSAFESEL2, 0x04, 0x1c, 0x7f),
2190 /*
2191 * 0x3f, VsafeSel3
2192 */
2193 REG_INIT(AB8505_VSAFESEL3, 0x04, 0x1d, 0x7f),
2194 /*
2195 * 0x0f, Vaux1Sel
2196 */
2197 REG_INIT(AB8505_VAUX1SEL, 0x04, 0x1f, 0x0f),
2198 /*
2199 * 0x0f, Vaux2Sel
2200 */
2201 REG_INIT(AB8505_VAUX2SEL, 0x04, 0x20, 0x0f),
2202 /*
2203 * 0x07, Vaux3Sel
2204 * 0x30, VRF1Sel
2205 */
2206 REG_INIT(AB8505_VRF1VAUX3SEL, 0x04, 0x21, 0x37),
2207 /*
2208 * 0x03, Vaux4RequestCtrl
2209 */
2210 REG_INIT(AB8505_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2211 /*
2212 * 0x03, Vaux4Regu
2213 */
2214 REG_INIT(AB8505_VAUX4REGU, 0x04, 0x2e, 0x03),
2215 /*
2216 * 0x0f, Vaux4Sel
2217 */
2218 REG_INIT(AB8505_VAUX4SEL, 0x04, 0x2f, 0x0f),
2219 /*
2220 * 0x04, Vaux1Disch
2221 * 0x08, Vaux2Disch
2222 * 0x10, Vaux3Disch
2223 * 0x20, Vintcore12Disch
2224 * 0x40, VTVoutDisch
2225 * 0x80, VaudioDisch
2226 */
2227 REG_INIT(AB8505_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
2228 /*
2229 * 0x02, VanaDisch
2230 * 0x04, VdmicPullDownEna
2231 * 0x10, VdmicDisch
2232 */
2233 REG_INIT(AB8505_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
2234 /*
2235 * 0x01, Vaux4Disch
2236 */
2237 REG_INIT(AB8505_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2238 /*
2239 * 0x07, Vaux5Sel
2240 * 0x08, Vaux5LP
2241 * 0x10, Vaux5Ena
2242 * 0x20, Vaux5Disch
2243 * 0x40, Vaux5DisSfst
2244 * 0x80, Vaux5DisPulld
2245 */
2246 REG_INIT(AB8505_CTRLVAUX5, 0x01, 0x55, 0xff),
2247 /*
2248 * 0x07, Vaux6Sel
2249 * 0x08, Vaux6LP
2250 * 0x10, Vaux6Ena
2251 * 0x80, Vaux6DisPulld
2252 */
2253 REG_INIT(AB8505_CTRLVAUX6, 0x01, 0x56, 0x9f),
2254};
2255
8e6a8d7d
LJ		 2256/* AB9540 register init */
2257static struct ab8500_reg_init ab9540_reg_init[] = {
2258 /*
2259 * 0x03, VarmRequestCtrl
2260 * 0x0c, VapeRequestCtrl
2261 * 0x30, Vsmps1RequestCtrl
2262 * 0xc0, Vsmps2RequestCtrl
2263 */
2264 REG_INIT(AB9540_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
2265 /*
2266 * 0x03, Vsmps3RequestCtrl
2267 * 0x0c, VpllRequestCtrl
2268 * 0x30, VanaRequestCtrl
2269 * 0xc0, VextSupply1RequestCtrl
2270 */
2271 REG_INIT(AB9540_REGUREQUESTCTRL2, 0x03, 0x04, 0xff),
2272 /*
2273 * 0x03, VextSupply2RequestCtrl
2274 * 0x0c, VextSupply3RequestCtrl
2275 * 0x30, Vaux1RequestCtrl
2276 * 0xc0, Vaux2RequestCtrl
2277 */
2278 REG_INIT(AB9540_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
2279 /*
2280 * 0x03, Vaux3RequestCtrl
2281 * 0x04, SwHPReq
2282 */
2283 REG_INIT(AB9540_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
2284 /*
2285 * 0x01, Vsmps1SysClkReq1HPValid
2286 * 0x02, Vsmps2SysClkReq1HPValid
2287 * 0x04, Vsmps3SysClkReq1HPValid
2288 * 0x08, VanaSysClkReq1HPValid
2289 * 0x10, VpllSysClkReq1HPValid
2290 * 0x20, Vaux1SysClkReq1HPValid
2291 * 0x40, Vaux2SysClkReq1HPValid
2292 * 0x80, Vaux3SysClkReq1HPValid
2293 */
2294 REG_INIT(AB9540_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
2295 /*
2296 * 0x01, VapeSysClkReq1HPValid
2297 * 0x02, VarmSysClkReq1HPValid
2298 * 0x04, VbbSysClkReq1HPValid
2299 * 0x08, VmodSysClkReq1HPValid
2300 * 0x10, VextSupply1SysClkReq1HPValid
2301 * 0x20, VextSupply2SysClkReq1HPValid
2302 * 0x40, VextSupply3SysClkReq1HPValid
2303 */
2304 REG_INIT(AB9540_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x7f),
2305 /*
2306 * 0x01, Vsmps1HwHPReq1Valid
2307 * 0x02, Vsmps2HwHPReq1Valid
2308 * 0x04, Vsmps3HwHPReq1Valid
2309 * 0x08, VanaHwHPReq1Valid
2310 * 0x10, VpllHwHPReq1Valid
2311 * 0x20, Vaux1HwHPReq1Valid
2312 * 0x40, Vaux2HwHPReq1Valid
2313 * 0x80, Vaux3HwHPReq1Valid
2314 */
2315 REG_INIT(AB9540_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
2316 /*
2317 * 0x01, VextSupply1HwHPReq1Valid
2318 * 0x02, VextSupply2HwHPReq1Valid
2319 * 0x04, VextSupply3HwHPReq1Valid
2320 * 0x08, VmodHwHPReq1Valid
2321 */
2322 REG_INIT(AB9540_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x0f),
2323 /*
2324 * 0x01, Vsmps1HwHPReq2Valid
2325 * 0x02, Vsmps2HwHPReq2Valid
2326 * 0x03, Vsmps3HwHPReq2Valid
2327 * 0x08, VanaHwHPReq2Valid
2328 * 0x10, VpllHwHPReq2Valid
2329 * 0x20, Vaux1HwHPReq2Valid
2330 * 0x40, Vaux2HwHPReq2Valid
2331 * 0x80, Vaux3HwHPReq2Valid
2332 */
2333 REG_INIT(AB9540_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
2334 /*
2335 * 0x01, VextSupply1HwHPReq2Valid
2336 * 0x02, VextSupply2HwHPReq2Valid
2337 * 0x04, VextSupply3HwHPReq2Valid
2338 * 0x08, VmodHwHPReq2Valid
2339 */
2340 REG_INIT(AB9540_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x0f),
2341 /*
2342 * 0x01, VapeSwHPReqValid
2343 * 0x02, VarmSwHPReqValid
2344 * 0x04, Vsmps1SwHPReqValid
2345 * 0x08, Vsmps2SwHPReqValid
2346 * 0x10, Vsmps3SwHPReqValid
2347 * 0x20, VanaSwHPReqValid
2348 * 0x40, VpllSwHPReqValid
2349 * 0x80, Vaux1SwHPReqValid
2350 */
2351 REG_INIT(AB9540_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2352 /*
2353 * 0x01, Vaux2SwHPReqValid
2354 * 0x02, Vaux3SwHPReqValid
2355 * 0x04, VextSupply1SwHPReqValid
2356 * 0x08, VextSupply2SwHPReqValid
2357 * 0x10, VextSupply3SwHPReqValid
2358 * 0x20, VmodSwHPReqValid
2359 */
2360 REG_INIT(AB9540_REGUSWHPREQVALID2, 0x03, 0x0e, 0x3f),
2361 /*
2362 * 0x02, SysClkReq2Valid1
2363 * ...
2364 * 0x80, SysClkReq8Valid1
2365 */
2366 REG_INIT(AB9540_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
2367 /*
2368 * 0x02, SysClkReq2Valid2
2369 * ...
2370 * 0x80, SysClkReq8Valid2
2371 */
2372 REG_INIT(AB9540_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
2373 /*
2374 * 0x01, Vaux4SwHPReqValid
2375 * 0x02, Vaux4HwHPReq2Valid
2376 * 0x04, Vaux4HwHPReq1Valid
2377 * 0x08, Vaux4SysClkReq1HPValid
2378 */
2379 REG_INIT(AB9540_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2380 /*
2381 * 0x02, VTVoutEna
2382 * 0x04, Vintcore12Ena
2383 * 0x38, Vintcore12Sel
2384 * 0x40, Vintcore12LP
2385 * 0x80, VTVoutLP
2386 */
2387 REG_INIT(AB9540_REGUMISC1, 0x03, 0x80, 0xfe),
2388 /*
2389 * 0x02, VaudioEna
2390 * 0x04, VdmicEna
2391 * 0x08, Vamic1Ena
2392 * 0x10, Vamic2Ena
2393 */
2394 REG_INIT(AB9540_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
2395 /*
2396 * 0x01, Vamic1_dzout
2397 * 0x02, Vamic2_dzout
2398 */
2399 REG_INIT(AB9540_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2400 /*
2401 * 0x03, Vsmps1Regu
2402 * 0x0c, Vsmps1SelCtrl
2403 * 0x10, Vsmps1AutoMode
2404 * 0x20, Vsmps1PWMMode
2405 */
2406 REG_INIT(AB9540_VSMPS1REGU, 0x04, 0x03, 0x3f),
2407 /*
2408 * 0x03, Vsmps2Regu
2409 * 0x0c, Vsmps2SelCtrl
2410 * 0x10, Vsmps2AutoMode
2411 * 0x20, Vsmps2PWMMode
2412 */
2413 REG_INIT(AB9540_VSMPS2REGU, 0x04, 0x04, 0x3f),
2414 /*
2415 * 0x03, Vsmps3Regu
2416 * 0x0c, Vsmps3SelCtrl
2417 * NOTE! PRCMU register
2418 */
2419 REG_INIT(AB9540_VSMPS3REGU, 0x04, 0x05, 0x0f),
2420 /*
2421 * 0x03, VpllRegu
2422 * 0x0c, VanaRegu
2423 */
2424 REG_INIT(AB9540_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2425 /*
2426 * 0x03, VextSupply1Regu
2427 * 0x0c, VextSupply2Regu
2428 * 0x30, VextSupply3Regu
2429 * 0x40, ExtSupply2Bypass
2430 * 0x80, ExtSupply3Bypass
2431 */
2432 REG_INIT(AB9540_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2433 /*
2434 * 0x03, Vaux1Regu
2435 * 0x0c, Vaux2Regu
2436 */
2437 REG_INIT(AB9540_VAUX12REGU, 0x04, 0x09, 0x0f),
2438 /*
2439 * 0x0c, Vrf1Regu
2440 * 0x03, Vaux3Regu
2441 */
2442 REG_INIT(AB9540_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2443 /*
2444 * 0x3f, Vsmps1Sel1
2445 */
2446 REG_INIT(AB9540_VSMPS1SEL1, 0x04, 0x13, 0x3f),
2447 /*
2448 * 0x3f, Vsmps1Sel2
2449 */
2450 REG_INIT(AB9540_VSMPS1SEL2, 0x04, 0x14, 0x3f),
2451 /*
2452 * 0x3f, Vsmps1Sel3
2453 */
2454 REG_INIT(AB9540_VSMPS1SEL3, 0x04, 0x15, 0x3f),
2455 /*
2456 * 0x3f, Vsmps2Sel1
2457 */
2458 REG_INIT(AB9540_VSMPS2SEL1, 0x04, 0x17, 0x3f),
2459 /*
2460 * 0x3f, Vsmps2Sel2
2461 */
2462 REG_INIT(AB9540_VSMPS2SEL2, 0x04, 0x18, 0x3f),
2463 /*
2464 * 0x3f, Vsmps2Sel3
2465 */
2466 REG_INIT(AB9540_VSMPS2SEL3, 0x04, 0x19, 0x3f),
2467 /*
2468 * 0x7f, Vsmps3Sel1
2469 * NOTE! PRCMU register
2470 */
2471 REG_INIT(AB9540_VSMPS3SEL1, 0x04, 0x1b, 0x7f),
2472 /*
2473 * 0x7f, Vsmps3Sel2
2474 * NOTE! PRCMU register
2475 */
2476 REG_INIT(AB9540_VSMPS3SEL2, 0x04, 0x1c, 0x7f),
2477 /*
2478 * 0x0f, Vaux1Sel
2479 */
2480 REG_INIT(AB9540_VAUX1SEL, 0x04, 0x1f, 0x0f),
2481 /*
2482 * 0x0f, Vaux2Sel
2483 */
2484 REG_INIT(AB9540_VAUX2SEL, 0x04, 0x20, 0x0f),
2485 /*
2486 * 0x07, Vaux3Sel
2487 * 0x30, Vrf1Sel
2488 */
2489 REG_INIT(AB9540_VRF1VAUX3SEL, 0x04, 0x21, 0x37),
2490 /*
2491 * 0x01, VextSupply12LP
2492 */
2493 REG_INIT(AB9540_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
2494 /*
2495 * 0x03, Vaux4RequestCtrl
2496 */
2497 REG_INIT(AB9540_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2498 /*
2499 * 0x03, Vaux4Regu
2500 */
2501 REG_INIT(AB9540_VAUX4REGU, 0x04, 0x2e, 0x03),
2502 /*
2503 * 0x08, Vaux4Sel
2504 */
2505 REG_INIT(AB9540_VAUX4SEL, 0x04, 0x2f, 0x0f),
2506 /*
2507 * 0x01, VpllDisch
2508 * 0x02, Vrf1Disch
2509 * 0x04, Vaux1Disch
2510 * 0x08, Vaux2Disch
2511 * 0x10, Vaux3Disch
2512 * 0x20, Vintcore12Disch
2513 * 0x40, VTVoutDisch
2514 * 0x80, VaudioDisch
2515 */
2516 REG_INIT(AB9540_REGUCTRLDISCH, 0x04, 0x43, 0xff),
2517 /*
2518 * 0x01, VsimDisch
2519 * 0x02, VanaDisch
2520 * 0x04, VdmicPullDownEna
2521 * 0x08, VpllPullDownEna
2522 * 0x10, VdmicDisch
2523 */
2524 REG_INIT(AB9540_REGUCTRLDISCH2, 0x04, 0x44, 0x1f),
2525 /*
2526 * 0x01, Vaux4Disch
2527 */
2528 REG_INIT(AB9540_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2529};
2530
ae0a9a3e
LJ		 2531/* AB8540 register init */
2532static struct ab8500_reg_init ab8540_reg_init[] = {
2533 /*
2534 * 0x01, VSimSycClkReq1Valid
2535 * 0x02, VSimSycClkReq2Valid
2536 * 0x04, VSimSycClkReq3Valid
2537 * 0x08, VSimSycClkReq4Valid
2538 * 0x10, VSimSycClkReq5Valid
2539 * 0x20, VSimSycClkReq6Valid
2540 * 0x40, VSimSycClkReq7Valid
2541 * 0x80, VSimSycClkReq8Valid
2542 */
2543 REG_INIT(AB8540_VSIMSYSCLKCTRL, 0x02, 0x33, 0xff),
2544 /*
2545 * 0x03, VarmRequestCtrl
2546 * 0x0c, VapeRequestCtrl
2547 * 0x30, Vsmps1RequestCtrl
2548 * 0xc0, Vsmps2RequestCtrl
2549 */
2550 REG_INIT(AB8540_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
2551 /*
2552 * 0x03, Vsmps3RequestCtrl
2553 * 0x0c, VpllRequestCtrl
2554 * 0x30, VanaRequestCtrl
2555 * 0xc0, VextSupply1RequestCtrl
2556 */
2557 REG_INIT(AB8540_REGUREQUESTCTRL2, 0x03, 0x04, 0xff),
2558 /*
2559 * 0x03, VextSupply2RequestCtrl
2560 * 0x0c, VextSupply3RequestCtrl
2561 * 0x30, Vaux1RequestCtrl
2562 * 0xc0, Vaux2RequestCtrl
2563 */
2564 REG_INIT(AB8540_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
2565 /*
2566 * 0x03, Vaux3RequestCtrl
2567 * 0x04, SwHPReq
2568 */
2569 REG_INIT(AB8540_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
2570 /*
2571 * 0x01, Vsmps1SysClkReq1HPValid
2572 * 0x02, Vsmps2SysClkReq1HPValid
2573 * 0x04, Vsmps3SysClkReq1HPValid
2574 * 0x08, VanaSysClkReq1HPValid
2575 * 0x10, VpllSysClkReq1HPValid
2576 * 0x20, Vaux1SysClkReq1HPValid
2577 * 0x40, Vaux2SysClkReq1HPValid
2578 * 0x80, Vaux3SysClkReq1HPValid
2579 */
2580 REG_INIT(AB8540_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
2581 /*
2582 * 0x01, VapeSysClkReq1HPValid
2583 * 0x02, VarmSysClkReq1HPValid
2584 * 0x04, VbbSysClkReq1HPValid
2585 * 0x10, VextSupply1SysClkReq1HPValid
2586 * 0x20, VextSupply2SysClkReq1HPValid
2587 * 0x40, VextSupply3SysClkReq1HPValid
2588 */
2589 REG_INIT(AB8540_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x77),
2590 /*
2591 * 0x01, Vsmps1HwHPReq1Valid
2592 * 0x02, Vsmps2HwHPReq1Valid
2593 * 0x04, Vsmps3HwHPReq1Valid
2594 * 0x08, VanaHwHPReq1Valid
2595 * 0x10, VpllHwHPReq1Valid
2596 * 0x20, Vaux1HwHPReq1Valid
2597 * 0x40, Vaux2HwHPReq1Valid
2598 * 0x80, Vaux3HwHPReq1Valid
2599 */
2600 REG_INIT(AB8540_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
2601 /*
2602 * 0x01, VextSupply1HwHPReq1Valid
2603 * 0x02, VextSupply2HwHPReq1Valid
2604 * 0x04, VextSupply3HwHPReq1Valid
2605 */
2606 REG_INIT(AB8540_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07),
2607 /*
2608 * 0x01, Vsmps1HwHPReq2Valid
2609 * 0x02, Vsmps2HwHPReq2Valid
2610 * 0x03, Vsmps3HwHPReq2Valid
2611 * 0x08, VanaHwHPReq2Valid
2612 * 0x10, VpllHwHPReq2Valid
2613 * 0x20, Vaux1HwHPReq2Valid
2614 * 0x40, Vaux2HwHPReq2Valid
2615 * 0x80, Vaux3HwHPReq2Valid
2616 */
2617 REG_INIT(AB8540_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
2618 /*
2619 * 0x01, VextSupply1HwHPReq2Valid
2620 * 0x02, VextSupply2HwHPReq2Valid
2621 * 0x04, VextSupply3HwHPReq2Valid
2622 */
2623 REG_INIT(AB8540_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07),
2624 /*
2625 * 0x01, VapeSwHPReqValid
2626 * 0x02, VarmSwHPReqValid
2627 * 0x04, Vsmps1SwHPReqValid
2628 * 0x08, Vsmps2SwHPReqValid
2629 * 0x10, Vsmps3SwHPReqValid
2630 * 0x20, VanaSwHPReqValid
2631 * 0x40, VpllSwHPReqValid
2632 * 0x80, Vaux1SwHPReqValid
2633 */
2634 REG_INIT(AB8540_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2635 /*
2636 * 0x01, Vaux2SwHPReqValid
2637 * 0x02, Vaux3SwHPReqValid
2638 * 0x04, VextSupply1SwHPReqValid
2639 * 0x08, VextSupply2SwHPReqValid
2640 * 0x10, VextSupply3SwHPReqValid
2641 */
2642 REG_INIT(AB8540_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f),
2643 /*
2644 * 0x02, SysClkReq2Valid1
2645 * ...
2646 * 0x80, SysClkReq8Valid1
2647 */
2648 REG_INIT(AB8540_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xff),
2649 /*
2650 * 0x02, SysClkReq2Valid2
2651 * ...
2652 * 0x80, SysClkReq8Valid2
2653 */
2654 REG_INIT(AB8540_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xff),
2655 /*
2656 * 0x01, Vaux4SwHPReqValid
2657 * 0x02, Vaux4HwHPReq2Valid
2658 * 0x04, Vaux4HwHPReq1Valid
2659 * 0x08, Vaux4SysClkReq1HPValid
2660 */
2661 REG_INIT(AB8540_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2662 /*
2663 * 0x01, Vaux5SwHPReqValid
2664 * 0x02, Vaux5HwHPReq2Valid
2665 * 0x04, Vaux5HwHPReq1Valid
2666 * 0x08, Vaux5SysClkReq1HPValid
2667 */
2668 REG_INIT(AB8540_REGUVAUX5REQVALID, 0x03, 0x12, 0x0f),
2669 /*
2670 * 0x01, Vaux6SwHPReqValid
2671 * 0x02, Vaux6HwHPReq2Valid
2672 * 0x04, Vaux6HwHPReq1Valid
2673 * 0x08, Vaux6SysClkReq1HPValid
2674 */
2675 REG_INIT(AB8540_REGUVAUX6REQVALID, 0x03, 0x13, 0x0f),
2676 /*
2677 * 0x01, VclkbSwHPReqValid
2678 * 0x02, VclkbHwHPReq2Valid
2679 * 0x04, VclkbHwHPReq1Valid
2680 * 0x08, VclkbSysClkReq1HPValid
2681 */
2682 REG_INIT(AB8540_REGUVCLKBREQVALID, 0x03, 0x14, 0x0f),
2683 /*
2684 * 0x01, Vrf1SwHPReqValid
2685 * 0x02, Vrf1HwHPReq2Valid
2686 * 0x04, Vrf1HwHPReq1Valid
2687 * 0x08, Vrf1SysClkReq1HPValid
2688 */
2689 REG_INIT(AB8540_REGUVRF1REQVALID, 0x03, 0x15, 0x0f),
2690 /*
2691 * 0x02, VTVoutEna
2692 * 0x04, Vintcore12Ena
2693 * 0x38, Vintcore12Sel
2694 * 0x40, Vintcore12LP
2695 * 0x80, VTVoutLP
2696 */
2697 REG_INIT(AB8540_REGUMISC1, 0x03, 0x80, 0xfe),
2698 /*
2699 * 0x02, VaudioEna
2700 * 0x04, VdmicEna
2701 * 0x08, Vamic1Ena
2702 * 0x10, Vamic2Ena
2703 * 0x20, Vamic12LP
2704 * 0xC0, VdmicSel
2705 */
2706 REG_INIT(AB8540_VAUDIOSUPPLY, 0x03, 0x83, 0xfe),
2707 /*
2708 * 0x01, Vamic1_dzout
2709 * 0x02, Vamic2_dzout
2710 */
2711 REG_INIT(AB8540_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2712 /*
2713 * 0x07, VHSICSel
2714 * 0x08, VHSICOffState
2715 * 0x10, VHSIEna
2716 * 0x20, VHSICLP
2717 */
2718 REG_INIT(AB8540_VHSIC, 0x03, 0x87, 0x3f),
2719 /*
2720 * 0x07, VSDIOSel
2721 * 0x08, VSDIOOffState
2722 * 0x10, VSDIOEna
2723 * 0x20, VSDIOLP
2724 */
2725 REG_INIT(AB8540_VSDIO, 0x03, 0x88, 0x3f),
2726 /*
2727 * 0x03, Vsmps1Regu
2728 * 0x0c, Vsmps1SelCtrl
2729 * 0x10, Vsmps1AutoMode
2730 * 0x20, Vsmps1PWMMode
2731 */
2732 REG_INIT(AB8540_VSMPS1REGU, 0x04, 0x03, 0x3f),
2733 /*
2734 * 0x03, Vsmps2Regu
2735 * 0x0c, Vsmps2SelCtrl
2736 * 0x10, Vsmps2AutoMode
2737 * 0x20, Vsmps2PWMMode
2738 */
2739 REG_INIT(AB8540_VSMPS2REGU, 0x04, 0x04, 0x3f),
2740 /*
2741 * 0x03, Vsmps3Regu
2742 * 0x0c, Vsmps3SelCtrl
2743 * 0x10, Vsmps3AutoMode
2744 * 0x20, Vsmps3PWMMode
2745 * NOTE! PRCMU register
2746 */
2747 REG_INIT(AB8540_VSMPS3REGU, 0x04, 0x05, 0x0f),
2748 /*
2749 * 0x03, VpllRegu
2750 * 0x0c, VanaRegu
2751 */
2752 REG_INIT(AB8540_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2753 /*
2754 * 0x03, VextSupply1Regu
2755 * 0x0c, VextSupply2Regu
2756 * 0x30, VextSupply3Regu
2757 * 0x40, ExtSupply2Bypass
2758 * 0x80, ExtSupply3Bypass
2759 */
2760 REG_INIT(AB8540_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2761 /*
2762 * 0x03, Vaux1Regu
2763 * 0x0c, Vaux2Regu
2764 */
2765 REG_INIT(AB8540_VAUX12REGU, 0x04, 0x09, 0x0f),
2766 /*
2767 * 0x0c, VRF1Regu
2768 * 0x03, Vaux3Regu
2769 */
2770 REG_INIT(AB8540_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2771 /*
2772 * 0x3f, Vsmps1Sel1
2773 */
2774 REG_INIT(AB8540_VSMPS1SEL1, 0x04, 0x13, 0x3f),
2775 /*
2776 * 0x3f, Vsmps1Sel2
2777 */
2778 REG_INIT(AB8540_VSMPS1SEL2, 0x04, 0x14, 0x3f),
2779 /*
2780 * 0x3f, Vsmps1Sel3
2781 */
2782 REG_INIT(AB8540_VSMPS1SEL3, 0x04, 0x15, 0x3f),
2783 /*
2784 * 0x3f, Vsmps2Sel1
2785 */
2786 REG_INIT(AB8540_VSMPS2SEL1, 0x04, 0x17, 0x3f),
2787 /*
2788 * 0x3f, Vsmps2Sel2
2789 */
2790 REG_INIT(AB8540_VSMPS2SEL2, 0x04, 0x18, 0x3f),
2791 /*
2792 * 0x3f, Vsmps2Sel3
2793 */
2794 REG_INIT(AB8540_VSMPS2SEL3, 0x04, 0x19, 0x3f),
2795 /*
2796 * 0x7f, Vsmps3Sel1
2797 * NOTE! PRCMU register
2798 */
2799 REG_INIT(AB8540_VSMPS3SEL1, 0x04, 0x1b, 0x7f),
2800 /*
2801 * 0x7f, Vsmps3Sel2
2802 * NOTE! PRCMU register
2803 */
2804 REG_INIT(AB8540_VSMPS3SEL2, 0x04, 0x1c, 0x7f),
2805 /*
2806 * 0x0f, Vaux1Sel
2807 */
2808 REG_INIT(AB8540_VAUX1SEL, 0x04, 0x1f, 0x0f),
2809 /*
2810 * 0x0f, Vaux2Sel
2811 */
2812 REG_INIT(AB8540_VAUX2SEL, 0x04, 0x20, 0x0f),
2813 /*
2814 * 0x07, Vaux3Sel
2815 * 0x70, Vrf1Sel
2816 */
2817 REG_INIT(AB8540_VRF1VAUX3SEL, 0x04, 0x21, 0x77),
2818 /*
2819 * 0x01, VextSupply12LP
2820 */
2821 REG_INIT(AB8540_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
2822 /*
2823 * 0x07, Vanasel
2824 * 0x30, Vpllsel
2825 */
2826 REG_INIT(AB8540_VANAVPLLSEL, 0x04, 0x29, 0x37),
2827 /*
2828 * 0x03, Vaux4RequestCtrl
2829 */
2830 REG_INIT(AB8540_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2831 /*
2832 * 0x03, Vaux4Regu
2833 */
2834 REG_INIT(AB8540_VAUX4REGU, 0x04, 0x2e, 0x03),
2835 /*
2836 * 0x0f, Vaux4Sel
2837 */
2838 REG_INIT(AB8540_VAUX4SEL, 0x04, 0x2f, 0x0f),
2839 /*
2840 * 0x03, Vaux5RequestCtrl
2841 */
2842 REG_INIT(AB8540_VAUX5REQCTRL, 0x04, 0x31, 0x03),
2843 /*
2844 * 0x03, Vaux5Regu
2845 */
2846 REG_INIT(AB8540_VAUX5REGU, 0x04, 0x32, 0x03),
2847 /*
2848 * 0x3f, Vaux5Sel
2849 */
2850 REG_INIT(AB8540_VAUX5SEL, 0x04, 0x33, 0x3f),
2851 /*
2852 * 0x03, Vaux6RequestCtrl
2853 */
2854 REG_INIT(AB8540_VAUX6REQCTRL, 0x04, 0x34, 0x03),
2855 /*
2856 * 0x03, Vaux6Regu
2857 */
2858 REG_INIT(AB8540_VAUX6REGU, 0x04, 0x35, 0x03),
2859 /*
2860 * 0x3f, Vaux6Sel
2861 */
2862 REG_INIT(AB8540_VAUX6SEL, 0x04, 0x36, 0x3f),
2863 /*
2864 * 0x03, VCLKBRequestCtrl
2865 */
2866 REG_INIT(AB8540_VCLKBREQCTRL, 0x04, 0x37, 0x03),
2867 /*
2868 * 0x03, VCLKBRegu
2869 */
2870 REG_INIT(AB8540_VCLKBREGU, 0x04, 0x38, 0x03),
2871 /*
2872 * 0x07, VCLKBSel
2873 */
2874 REG_INIT(AB8540_VCLKBSEL, 0x04, 0x39, 0x07),
2875 /*
2876 * 0x03, Vrf1RequestCtrl
2877 */
2878 REG_INIT(AB8540_VRF1REQCTRL, 0x04, 0x3a, 0x03),
2879 /*
2880 * 0x01, VpllDisch
2881 * 0x02, Vrf1Disch
2882 * 0x04, Vaux1Disch
2883 * 0x08, Vaux2Disch
2884 * 0x10, Vaux3Disch
2885 * 0x20, Vintcore12Disch
2886 * 0x40, VTVoutDisch
2887 * 0x80, VaudioDisch
2888 */
2889 REG_INIT(AB8540_REGUCTRLDISCH, 0x04, 0x43, 0xff),
2890 /*
2891 * 0x02, VanaDisch
2892 * 0x04, VdmicPullDownEna
2893 * 0x08, VpllPullDownEna
2894 * 0x10, VdmicDisch
2895 */
2896 REG_INIT(AB8540_REGUCTRLDISCH2, 0x04, 0x44, 0x1e),
2897 /*
2898 * 0x01, Vaux4Disch
2899 */
2900 REG_INIT(AB8540_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2901 /*
2902 * 0x01, Vaux5Disch
2903 * 0x02, Vaux6Disch
2904 * 0x04, VCLKBDisch
2905 */
2906 REG_INIT(AB8540_REGUCTRLDISCH4, 0x04, 0x49, 0x07),
2907};
2908
b54969ac 2909static struct of_regulator_match ab8500_regulator_match[] = {
7e715b95
LJ		 2910 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8500_LDO_AUX1, },
2911 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8500_LDO_AUX2, },
2912 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8500_LDO_AUX3, },
2913 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8500_LDO_INTCORE, },
2914 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8500_LDO_TVOUT, },
7e715b95
LJ		 2915 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8500_LDO_AUDIO, },
2916 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8500_LDO_ANAMIC1, },
2917 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8500_LDO_ANAMIC2, },
2918 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8500_LDO_DMIC, },
2919 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8500_LDO_ANA, },
3a8334b9
LJ		 2920};
2921
547f384f
LJ		 2922static struct of_regulator_match ab8505_regulator_match[] = {
2923 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8505_LDO_AUX1, },
2924 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8505_LDO_AUX2, },
2925 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8505_LDO_AUX3, },
2926 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8505_LDO_AUX4, },
2927 { .name = "ab8500_ldo_aux5", .driver_data = (void *) AB8505_LDO_AUX5, },
2928 { .name = "ab8500_ldo_aux6", .driver_data = (void *) AB8505_LDO_AUX6, },
2929 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8505_LDO_INTCORE, },
2930 { .name = "ab8500_ldo_adc", .driver_data = (void *) AB8505_LDO_ADC, },
2931 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8505_LDO_AUDIO, },
2932 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8505_LDO_ANAMIC1, },
2933 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8505_LDO_ANAMIC2, },
2934 { .name = "ab8500_ldo_aux8", .driver_data = (void *) AB8505_LDO_AUX8, },
2935 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8505_LDO_ANA, },
2936};
2937
ae0a9a3e
LJ		 2938static struct of_regulator_match ab8540_regulator_match[] = {
2939 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8540_LDO_AUX1, },
2940 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8540_LDO_AUX2, },
2941 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8540_LDO_AUX3, },
2942 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8540_LDO_AUX4, },
684d5ce4
ZH		 2943 { .name = "ab8500_ldo_aux5", .driver_data = (void *) AB8540_LDO_AUX5, },
2944 { .name = "ab8500_ldo_aux6", .driver_data = (void *) AB8540_LDO_AUX6, },
ae0a9a3e
LJ		 2945 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8540_LDO_INTCORE, },
2946 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8540_LDO_TVOUT, },
2947 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8540_LDO_AUDIO, },
2948 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8540_LDO_ANAMIC1, },
2949 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8540_LDO_ANAMIC2, },
2950 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8540_LDO_DMIC, },
2951 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8540_LDO_ANA, },
2952 { .name = "ab8500_ldo_sdio", .driver_data = (void *) AB8540_LDO_SDIO, },
2953};
2954
8e6a8d7d
LJ		 2955static struct of_regulator_match ab9540_regulator_match[] = {
2956 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB9540_LDO_AUX1, },
2957 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB9540_LDO_AUX2, },
2958 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB9540_LDO_AUX3, },
2959 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB9540_LDO_AUX4, },
2960 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB9540_LDO_INTCORE, },
2961 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB9540_LDO_TVOUT, },
2962 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB9540_LDO_AUDIO, },
2963 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB9540_LDO_ANAMIC1, },
2964 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB9540_LDO_ANAMIC2, },
2965 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB9540_LDO_DMIC, },
2966 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB9540_LDO_ANA, },
2967};
2968
da45edc7
LJ		 2969static struct {
2970 struct ab8500_regulator_info *info;
2971 int info_size;
2972 struct ab8500_reg_init *init;
2973 int init_size;
2974 struct of_regulator_match *match;
2975 int match_size;
2976} abx500_regulator;
2977
33aeb49e
LJ		 2978static void abx500_get_regulator_info(struct ab8500 *ab8500)
2979{
2980 if (is_ab9540(ab8500)) {
2981 abx500_regulator.info = ab9540_regulator_info;
2982 abx500_regulator.info_size = ARRAY_SIZE(ab9540_regulator_info);
2983 abx500_regulator.init = ab9540_reg_init;
2984 abx500_regulator.init_size = AB9540_NUM_REGULATOR_REGISTERS;
2985 abx500_regulator.match = ab9540_regulator_match;
2986 abx500_regulator.match_size = ARRAY_SIZE(ab9540_regulator_match);
2987 } else if (is_ab8505(ab8500)) {
2988 abx500_regulator.info = ab8505_regulator_info;
2989 abx500_regulator.info_size = ARRAY_SIZE(ab8505_regulator_info);
2990 abx500_regulator.init = ab8505_reg_init;
2991 abx500_regulator.init_size = AB8505_NUM_REGULATOR_REGISTERS;
2992 abx500_regulator.match = ab8505_regulator_match;
2993 abx500_regulator.match_size = ARRAY_SIZE(ab8505_regulator_match);
2994 } else if (is_ab8540(ab8500)) {
2995 abx500_regulator.info = ab8540_regulator_info;
2996 abx500_regulator.info_size = ARRAY_SIZE(ab8540_regulator_info);
2997 abx500_regulator.init = ab8540_reg_init;
2998 abx500_regulator.init_size = AB8540_NUM_REGULATOR_REGISTERS;
2999 abx500_regulator.match = ab8540_regulator_match;
3000 abx500_regulator.match_size = ARRAY_SIZE(ab8540_regulator_match);
3001 } else {
3002 abx500_regulator.info = ab8500_regulator_info;
3003 abx500_regulator.info_size = ARRAY_SIZE(ab8500_regulator_info);
3004 abx500_regulator.init = ab8500_reg_init;
3005 abx500_regulator.init_size = AB8500_NUM_REGULATOR_REGISTERS;
3006 abx500_regulator.match = ab8500_regulator_match;
3007 abx500_regulator.match_size = ARRAY_SIZE(ab8500_regulator_match);
3008 }
3009}
3010
da45edc7
LJ		 3011static int ab8500_regulator_init_registers(struct platform_device *pdev,
3012 int id, int mask, int value)
3013{
3014 struct ab8500_reg_init *reg_init = abx500_regulator.init;
3015 int err;
3016
3017 BUG_ON(value & ~mask);
3018 BUG_ON(mask & ~reg_init[id].mask);
3019
3020 /* initialize register */
3021 err = abx500_mask_and_set_register_interruptible(
3022 &pdev->dev,
3023 reg_init[id].bank,
3024 reg_init[id].addr,
3025 mask, value);
3026 if (err < 0) {
3027 dev_err(&pdev->dev,
3028 "Failed to initialize 0x%02x, 0x%02x.\n",
3029 reg_init[id].bank,
3030 reg_init[id].addr);
3031 return err;
3032 }
3033 dev_vdbg(&pdev->dev,
3034 " init: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",
3035 reg_init[id].bank,
3036 reg_init[id].addr,
3037 mask, value);
3038
3039 return 0;
3040}
3041
3042static int ab8500_regulator_register(struct platform_device *pdev,
3043 struct regulator_init_data *init_data,
3044 int id, struct device_node *np)
3045{
3046 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
3047 struct ab8500_regulator_info *info = NULL;
3048 struct regulator_config config = { };
3049 int err;
3050
3051 /* assign per-regulator data */
3052 info = &abx500_regulator.info[id];
3053 info->dev = &pdev->dev;
3054
3055 config.dev = &pdev->dev;
3056 config.init_data = init_data;
3057 config.driver_data = info;
3058 config.of_node = np;
3059
3060 /* fix for hardware before ab8500v2.0 */
3061 if (is_ab8500_1p1_or_earlier(ab8500)) {
3062 if (info->desc.id == AB8500_LDO_AUX3) {
3063 info->desc.n_voltages =
3064 ARRAY_SIZE(ldo_vauxn_voltages);
3065 info->desc.volt_table = ldo_vauxn_voltages;
3066 info->voltage_mask = 0xf;
3067 }
3068 }
3069
3070 /* register regulator with framework */
3071 info->regulator = regulator_register(&info->desc, &config);
3072 if (IS_ERR(info->regulator)) {
3073 err = PTR_ERR(info->regulator);
3074 dev_err(&pdev->dev, "failed to register regulator %s\n",
3075 info->desc.name);
3076 /* when we fail, un-register all earlier regulators */
3077 while (--id >= 0) {
3078 info = &abx500_regulator.info[id];
3079 regulator_unregister(info->regulator);
3080 }
3081 return err;
3082 }
3083
3084 return 0;
3085}
3086
a5023574 3087static int
b54969ac 3088ab8500_regulator_of_probe(struct platform_device *pdev,
b54969ac 3089 struct device_node *np)
3a8334b9 3090{
33aeb49e 3091 struct of_regulator_match *match = abx500_regulator.match;
3a8334b9
LJ		 3092 int err, i;
3093
33aeb49e 3094 for (i = 0; i < abx500_regulator.info_size; i++) {
3a8334b9 3095 err = ab8500_regulator_register(
33aeb49e 3096 pdev, match[i].init_data, i, match[i].of_node);
3a8334b9
LJ		 3097 if (err)
3098 return err;
3099 }
3100
3101 return 0;
3102}
3103
a5023574 3104static int ab8500_regulator_probe(struct platform_device *pdev)
c789ca20
SI		 3105{
3106 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
3a8334b9 3107 struct device_node *np = pdev->dev.of_node;
732805a5
BJ		 3108 struct ab8500_platform_data *ppdata;
3109 struct ab8500_regulator_platform_data *pdata;
c789ca20 3110 int i, err;
b54969ac 3111
33aeb49e
LJ		 3112 if (!ab8500) {
3113 dev_err(&pdev->dev, "null mfd parent\n");
3114 return -EINVAL;
8e6a8d7d 3115 }
c789ca20 3116
33aeb49e
LJ		 3117 abx500_get_regulator_info(ab8500);
3118
3a8334b9 3119 if (np) {
33aeb49e
LJ		 3120 err = of_regulator_match(&pdev->dev, np,
3121 abx500_regulator.match,
3122 abx500_regulator.match_size);
3a8334b9
LJ		 3123 if (err < 0) {
3124 dev_err(&pdev->dev,
3125 "Error parsing regulator init data: %d\n", err);
3126 return err;
3127 }
3128
33aeb49e 3129 err = ab8500_regulator_of_probe(pdev, np);
3a8334b9
LJ		 3130 return err;
3131 }
3132
732805a5
BJ		 3133 ppdata = dev_get_platdata(ab8500->dev);
3134 if (!ppdata) {
3135 dev_err(&pdev->dev, "null parent pdata\n");
3136 return -EINVAL;
3137 }
3138
3139 pdata = ppdata->regulator;
fc24b426
BJ		 3140 if (!pdata) {
3141 dev_err(&pdev->dev, "null pdata\n");
3142 return -EINVAL;
3143 }
c789ca20 3144
cb189b07 3145 /* make sure the platform data has the correct size */
33aeb49e 3146 if (pdata->num_regulator != abx500_regulator.info_size) {
79568b94 3147 dev_err(&pdev->dev, "Configuration error: size mismatch.\n");
cb189b07
BJ		 3148 return -EINVAL;
3149 }
3150
da0b0c47
LJ		 3151 /* initialize debug (initial state is recorded with this call) */
3152 err = ab8500_regulator_debug_init(pdev);
3153 if (err)
3154 return err;
3155
79568b94 3156 /* initialize registers */
732805a5 3157 for (i = 0; i < pdata->num_reg_init; i++) {
3c1b8438 3158 int id, mask, value;
79568b94 3159
732805a5
BJ		 3160 id = pdata->reg_init[i].id;
3161 mask = pdata->reg_init[i].mask;
3162 value = pdata->reg_init[i].value;
79568b94
BJ		 3163
3164 /* check for configuration errors */
33aeb49e 3165 BUG_ON(id >= abx500_regulator.init_size);
79568b94 3166
33aeb49e 3167 err = ab8500_regulator_init_registers(pdev, id, mask, value);
a7ac1d9e 3168 if (err < 0)
79568b94 3169 return err;
79568b94
BJ		 3170 }
3171
f7eae37f
RV		 3172 if (!is_ab8505(ab8500)) {
3173 /* register external regulators (before Vaux1, 2 and 3) */
3174 err = ab8500_ext_regulator_init(pdev);
3175 if (err)
3176 return err;
3177 }
d1a82001 3178
c789ca20 3179 /* register all regulators */
33aeb49e 3180 for (i = 0; i < abx500_regulator.info_size; i++) {
b54969ac 3181 err = ab8500_regulator_register(pdev, &pdata->regulator[i],
33aeb49e 3182 i, NULL);
a7ac1d9e 3183 if (err < 0)
c789ca20 3184 return err;
c789ca20
SI		 3185 }
3186
3187 return 0;
3188}
3189
8dc995f5 3190static int ab8500_regulator_remove(struct platform_device *pdev)
c789ca20 3191{
d1a82001 3192 int i, err;
8e6a8d7d 3193 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
b54969ac 3194
33aeb49e 3195 for (i = 0; i < abx500_regulator.info_size; i++) {
c789ca20 3196 struct ab8500_regulator_info *info = NULL;
33aeb49e 3197 info = &abx500_regulator.info[i];
09aefa12
BJ		 3198
3199 dev_vdbg(rdev_get_dev(info->regulator),
3200 "%s-remove\n", info->desc.name);
3201
c789ca20
SI		 3202 regulator_unregister(info->regulator);
3203 }
3204
f7eae37f
RV		 3205 if (!is_ab8505(ab8500)) {
3206 /* remove external regulators (after Vaux1, 2 and 3) */
3207 err = ab8500_ext_regulator_exit(pdev);
3208 if (err)
3209 return err;
3210 }
d1a82001 3211
da0b0c47
LJ		 3212 /* remove regulator debug */
3213 err = ab8500_regulator_debug_exit(pdev);
3214 if (err)
3215 return err;
3216
c789ca20
SI		 3217 return 0;
3218}
3219
3220static struct platform_driver ab8500_regulator_driver = {
3221 .probe = ab8500_regulator_probe,
5eb9f2b9 3222 .remove = ab8500_regulator_remove,
c789ca20
SI		 3223 .driver = {
3224 .name = "ab8500-regulator",
3225 .owner = THIS_MODULE,
3226 },
3227};
3228
3229static int __init ab8500_regulator_init(void)
3230{
3231 int ret;
3232
3233 ret = platform_driver_register(&ab8500_regulator_driver);
3234 if (ret != 0)
3235 pr_err("Failed to register ab8500 regulator: %d\n", ret);
3236
3237 return ret;
3238}
3239subsys_initcall(ab8500_regulator_init);
3240
3241static void __exit ab8500_regulator_exit(void)
3242{
3243 platform_driver_unregister(&ab8500_regulator_driver);
3244}
3245module_exit(ab8500_regulator_exit);
3246
3247MODULE_LICENSE("GPL v2");
3248MODULE_AUTHOR("Sundar Iyer <sundar.iyer@stericsson.com>");
732805a5 3249MODULE_AUTHOR("Bengt Jonsson <bengt.g.jonsson@stericsson.com>");
547f384f 3250MODULE_AUTHOR("Daniel Willerud <daniel.willerud@stericsson.com>");
c789ca20
SI		 3251MODULE_DESCRIPTION("Regulator Driver for ST-Ericsson AB8500 Mixed-Sig PMIC");
3252MODULE_ALIAS("platform:ab8500-regulator");
Linux kernel - Deliverables
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