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dfe7a1b0 CC |
1 | /* |
2 | * AXP20x regulators driver. | |
3 | * | |
4 | * Copyright (C) 2013 Carlo Caione <carlo@caione.org> | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General | |
7 | * Public License. See the file "COPYING" in the main directory of this | |
8 | * archive for more details. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #include <linux/err.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/of_device.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/regmap.h> | |
23 | #include <linux/mfd/axp20x.h> | |
24 | #include <linux/regulator/driver.h> | |
25 | #include <linux/regulator/of_regulator.h> | |
26 | ||
27 | #define AXP20X_IO_ENABLED 0x03 | |
28 | #define AXP20X_IO_DISABLED 0x07 | |
29 | ||
3cb99e2e CYT |
30 | #define AXP22X_IO_ENABLED 0x03 |
31 | #define AXP22X_IO_DISABLED 0x04 | |
1b82b4e4 | 32 | |
dfe7a1b0 CC |
33 | #define AXP20X_WORKMODE_DCDC2_MASK BIT(2) |
34 | #define AXP20X_WORKMODE_DCDC3_MASK BIT(1) | |
1b82b4e4 | 35 | #define AXP22X_WORKMODE_DCDCX_MASK(x) BIT(x) |
dfe7a1b0 CC |
36 | |
37 | #define AXP20X_FREQ_DCDC_MASK 0x0f | |
38 | ||
636e2a39 HG |
39 | #define AXP22X_MISC_N_VBUSEN_FUNC BIT(4) |
40 | ||
866bd951 BB |
41 | #define AXP_DESC_IO(_family, _id, _match, _supply, _min, _max, _step, _vreg, \ |
42 | _vmask, _ereg, _emask, _enable_val, _disable_val) \ | |
43 | [_family##_##_id] = { \ | |
e0bbb38c | 44 | .name = (_match), \ |
dfe7a1b0 | 45 | .supply_name = (_supply), \ |
880fe82d CYT |
46 | .of_match = of_match_ptr(_match), \ |
47 | .regulators_node = of_match_ptr("regulators"), \ | |
dfe7a1b0 | 48 | .type = REGULATOR_VOLTAGE, \ |
866bd951 | 49 | .id = _family##_##_id, \ |
dfe7a1b0 CC |
50 | .n_voltages = (((_max) - (_min)) / (_step) + 1), \ |
51 | .owner = THIS_MODULE, \ | |
52 | .min_uV = (_min) * 1000, \ | |
53 | .uV_step = (_step) * 1000, \ | |
54 | .vsel_reg = (_vreg), \ | |
55 | .vsel_mask = (_vmask), \ | |
56 | .enable_reg = (_ereg), \ | |
57 | .enable_mask = (_emask), \ | |
58 | .enable_val = (_enable_val), \ | |
59 | .disable_val = (_disable_val), \ | |
60 | .ops = &axp20x_ops, \ | |
61 | } | |
62 | ||
866bd951 BB |
63 | #define AXP_DESC(_family, _id, _match, _supply, _min, _max, _step, _vreg, \ |
64 | _vmask, _ereg, _emask) \ | |
65 | [_family##_##_id] = { \ | |
e0bbb38c | 66 | .name = (_match), \ |
dfe7a1b0 | 67 | .supply_name = (_supply), \ |
880fe82d CYT |
68 | .of_match = of_match_ptr(_match), \ |
69 | .regulators_node = of_match_ptr("regulators"), \ | |
dfe7a1b0 | 70 | .type = REGULATOR_VOLTAGE, \ |
866bd951 | 71 | .id = _family##_##_id, \ |
dfe7a1b0 CC |
72 | .n_voltages = (((_max) - (_min)) / (_step) + 1), \ |
73 | .owner = THIS_MODULE, \ | |
74 | .min_uV = (_min) * 1000, \ | |
75 | .uV_step = (_step) * 1000, \ | |
76 | .vsel_reg = (_vreg), \ | |
77 | .vsel_mask = (_vmask), \ | |
78 | .enable_reg = (_ereg), \ | |
79 | .enable_mask = (_emask), \ | |
80 | .ops = &axp20x_ops, \ | |
81 | } | |
82 | ||
94c39041 | 83 | #define AXP_DESC_SW(_family, _id, _match, _supply, _ereg, _emask) \ |
1b82b4e4 | 84 | [_family##_##_id] = { \ |
e0bbb38c | 85 | .name = (_match), \ |
1b82b4e4 BB |
86 | .supply_name = (_supply), \ |
87 | .of_match = of_match_ptr(_match), \ | |
88 | .regulators_node = of_match_ptr("regulators"), \ | |
89 | .type = REGULATOR_VOLTAGE, \ | |
90 | .id = _family##_##_id, \ | |
1b82b4e4 | 91 | .owner = THIS_MODULE, \ |
1b82b4e4 BB |
92 | .enable_reg = (_ereg), \ |
93 | .enable_mask = (_emask), \ | |
94 | .ops = &axp20x_ops_sw, \ | |
95 | } | |
96 | ||
866bd951 BB |
97 | #define AXP_DESC_FIXED(_family, _id, _match, _supply, _volt) \ |
98 | [_family##_##_id] = { \ | |
e0bbb38c | 99 | .name = (_match), \ |
dfe7a1b0 | 100 | .supply_name = (_supply), \ |
880fe82d CYT |
101 | .of_match = of_match_ptr(_match), \ |
102 | .regulators_node = of_match_ptr("regulators"), \ | |
dfe7a1b0 | 103 | .type = REGULATOR_VOLTAGE, \ |
866bd951 | 104 | .id = _family##_##_id, \ |
dfe7a1b0 CC |
105 | .n_voltages = 1, \ |
106 | .owner = THIS_MODULE, \ | |
107 | .min_uV = (_volt) * 1000, \ | |
108 | .ops = &axp20x_ops_fixed \ | |
109 | } | |
110 | ||
13d57e64 CYT |
111 | #define AXP_DESC_RANGES(_family, _id, _match, _supply, _ranges, _n_voltages, \ |
112 | _vreg, _vmask, _ereg, _emask) \ | |
866bd951 | 113 | [_family##_##_id] = { \ |
e0bbb38c | 114 | .name = (_match), \ |
dfe7a1b0 | 115 | .supply_name = (_supply), \ |
880fe82d CYT |
116 | .of_match = of_match_ptr(_match), \ |
117 | .regulators_node = of_match_ptr("regulators"), \ | |
dfe7a1b0 | 118 | .type = REGULATOR_VOLTAGE, \ |
866bd951 | 119 | .id = _family##_##_id, \ |
13d57e64 | 120 | .n_voltages = (_n_voltages), \ |
dfe7a1b0 CC |
121 | .owner = THIS_MODULE, \ |
122 | .vsel_reg = (_vreg), \ | |
123 | .vsel_mask = (_vmask), \ | |
124 | .enable_reg = (_ereg), \ | |
125 | .enable_mask = (_emask), \ | |
13d57e64 CYT |
126 | .linear_ranges = (_ranges), \ |
127 | .n_linear_ranges = ARRAY_SIZE(_ranges), \ | |
128 | .ops = &axp20x_ops_range, \ | |
dfe7a1b0 CC |
129 | } |
130 | ||
dfe7a1b0 CC |
131 | static struct regulator_ops axp20x_ops_fixed = { |
132 | .list_voltage = regulator_list_voltage_linear, | |
133 | }; | |
134 | ||
13d57e64 | 135 | static struct regulator_ops axp20x_ops_range = { |
dfe7a1b0 CC |
136 | .set_voltage_sel = regulator_set_voltage_sel_regmap, |
137 | .get_voltage_sel = regulator_get_voltage_sel_regmap, | |
13d57e64 | 138 | .list_voltage = regulator_list_voltage_linear_range, |
dfe7a1b0 CC |
139 | .enable = regulator_enable_regmap, |
140 | .disable = regulator_disable_regmap, | |
141 | .is_enabled = regulator_is_enabled_regmap, | |
142 | }; | |
143 | ||
144 | static struct regulator_ops axp20x_ops = { | |
145 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
146 | .get_voltage_sel = regulator_get_voltage_sel_regmap, | |
147 | .list_voltage = regulator_list_voltage_linear, | |
148 | .enable = regulator_enable_regmap, | |
149 | .disable = regulator_disable_regmap, | |
150 | .is_enabled = regulator_is_enabled_regmap, | |
151 | }; | |
152 | ||
1b82b4e4 | 153 | static struct regulator_ops axp20x_ops_sw = { |
1b82b4e4 BB |
154 | .enable = regulator_enable_regmap, |
155 | .disable = regulator_disable_regmap, | |
156 | .is_enabled = regulator_is_enabled_regmap, | |
157 | }; | |
158 | ||
13d57e64 CYT |
159 | static const struct regulator_linear_range axp20x_ldo4_ranges[] = { |
160 | REGULATOR_LINEAR_RANGE(1250000, 0x0, 0x0, 0), | |
161 | REGULATOR_LINEAR_RANGE(1300000, 0x1, 0x8, 100000), | |
8d4d5c3a MR |
162 | REGULATOR_LINEAR_RANGE(2500000, 0x9, 0x9, 0), |
163 | REGULATOR_LINEAR_RANGE(2700000, 0xa, 0xb, 100000), | |
164 | REGULATOR_LINEAR_RANGE(3000000, 0xc, 0xf, 100000), | |
13d57e64 CYT |
165 | }; |
166 | ||
dfe7a1b0 | 167 | static const struct regulator_desc axp20x_regulators[] = { |
866bd951 BB |
168 | AXP_DESC(AXP20X, DCDC2, "dcdc2", "vin2", 700, 2275, 25, |
169 | AXP20X_DCDC2_V_OUT, 0x3f, AXP20X_PWR_OUT_CTRL, 0x10), | |
170 | AXP_DESC(AXP20X, DCDC3, "dcdc3", "vin3", 700, 3500, 25, | |
171 | AXP20X_DCDC3_V_OUT, 0x7f, AXP20X_PWR_OUT_CTRL, 0x02), | |
172 | AXP_DESC_FIXED(AXP20X, LDO1, "ldo1", "acin", 1300), | |
173 | AXP_DESC(AXP20X, LDO2, "ldo2", "ldo24in", 1800, 3300, 100, | |
174 | AXP20X_LDO24_V_OUT, 0xf0, AXP20X_PWR_OUT_CTRL, 0x04), | |
175 | AXP_DESC(AXP20X, LDO3, "ldo3", "ldo3in", 700, 3500, 25, | |
176 | AXP20X_LDO3_V_OUT, 0x7f, AXP20X_PWR_OUT_CTRL, 0x40), | |
13d57e64 CYT |
177 | AXP_DESC_RANGES(AXP20X, LDO4, "ldo4", "ldo24in", axp20x_ldo4_ranges, |
178 | 16, AXP20X_LDO24_V_OUT, 0x0f, AXP20X_PWR_OUT_CTRL, | |
179 | 0x08), | |
866bd951 BB |
180 | AXP_DESC_IO(AXP20X, LDO5, "ldo5", "ldo5in", 1800, 3300, 100, |
181 | AXP20X_LDO5_V_OUT, 0xf0, AXP20X_GPIO0_CTRL, 0x07, | |
182 | AXP20X_IO_ENABLED, AXP20X_IO_DISABLED), | |
dfe7a1b0 CC |
183 | }; |
184 | ||
1b82b4e4 BB |
185 | static const struct regulator_desc axp22x_regulators[] = { |
186 | AXP_DESC(AXP22X, DCDC1, "dcdc1", "vin1", 1600, 3400, 100, | |
187 | AXP22X_DCDC1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(1)), | |
188 | AXP_DESC(AXP22X, DCDC2, "dcdc2", "vin2", 600, 1540, 20, | |
189 | AXP22X_DCDC2_V_OUT, 0x3f, AXP22X_PWR_OUT_CTRL1, BIT(2)), | |
190 | AXP_DESC(AXP22X, DCDC3, "dcdc3", "vin3", 600, 1860, 20, | |
191 | AXP22X_DCDC3_V_OUT, 0x3f, AXP22X_PWR_OUT_CTRL1, BIT(3)), | |
192 | AXP_DESC(AXP22X, DCDC4, "dcdc4", "vin4", 600, 1540, 20, | |
6b3600b4 | 193 | AXP22X_DCDC4_V_OUT, 0x3f, AXP22X_PWR_OUT_CTRL1, BIT(4)), |
1b82b4e4 | 194 | AXP_DESC(AXP22X, DCDC5, "dcdc5", "vin5", 1000, 2550, 50, |
6b3600b4 | 195 | AXP22X_DCDC5_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(5)), |
1b82b4e4 | 196 | /* secondary switchable output of DCDC1 */ |
94c39041 CYT |
197 | AXP_DESC_SW(AXP22X, DC1SW, "dc1sw", NULL, AXP22X_PWR_OUT_CTRL2, |
198 | BIT(7)), | |
1b82b4e4 | 199 | /* LDO regulator internally chained to DCDC5 */ |
7118f19c | 200 | AXP_DESC(AXP22X, DC5LDO, "dc5ldo", NULL, 700, 1400, 100, |
1b82b4e4 BB |
201 | AXP22X_DC5LDO_V_OUT, 0x7, AXP22X_PWR_OUT_CTRL1, BIT(0)), |
202 | AXP_DESC(AXP22X, ALDO1, "aldo1", "aldoin", 700, 3300, 100, | |
203 | AXP22X_ALDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(6)), | |
204 | AXP_DESC(AXP22X, ALDO2, "aldo2", "aldoin", 700, 3300, 100, | |
205 | AXP22X_ALDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(7)), | |
206 | AXP_DESC(AXP22X, ALDO3, "aldo3", "aldoin", 700, 3300, 100, | |
207 | AXP22X_ALDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL3, BIT(7)), | |
208 | AXP_DESC(AXP22X, DLDO1, "dldo1", "dldoin", 700, 3300, 100, | |
209 | AXP22X_DLDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(3)), | |
210 | AXP_DESC(AXP22X, DLDO2, "dldo2", "dldoin", 700, 3300, 100, | |
211 | AXP22X_DLDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(4)), | |
212 | AXP_DESC(AXP22X, DLDO3, "dldo3", "dldoin", 700, 3300, 100, | |
213 | AXP22X_DLDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(5)), | |
214 | AXP_DESC(AXP22X, DLDO4, "dldo4", "dldoin", 700, 3300, 100, | |
215 | AXP22X_DLDO4_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(6)), | |
216 | AXP_DESC(AXP22X, ELDO1, "eldo1", "eldoin", 700, 3300, 100, | |
217 | AXP22X_ELDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(0)), | |
218 | AXP_DESC(AXP22X, ELDO2, "eldo2", "eldoin", 700, 3300, 100, | |
219 | AXP22X_ELDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(1)), | |
220 | AXP_DESC(AXP22X, ELDO3, "eldo3", "eldoin", 700, 3300, 100, | |
221 | AXP22X_ELDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(2)), | |
f40d4896 HG |
222 | /* Note the datasheet only guarantees reliable operation up to |
223 | * 3.3V, this needs to be enforced via dts provided constraints */ | |
224 | AXP_DESC_IO(AXP22X, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100, | |
1b82b4e4 BB |
225 | AXP22X_LDO_IO0_V_OUT, 0x1f, AXP20X_GPIO0_CTRL, 0x07, |
226 | AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), | |
f40d4896 HG |
227 | /* Note the datasheet only guarantees reliable operation up to |
228 | * 3.3V, this needs to be enforced via dts provided constraints */ | |
229 | AXP_DESC_IO(AXP22X, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100, | |
1b82b4e4 BB |
230 | AXP22X_LDO_IO1_V_OUT, 0x1f, AXP20X_GPIO1_CTRL, 0x07, |
231 | AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), | |
232 | AXP_DESC_FIXED(AXP22X, RTC_LDO, "rtc_ldo", "ips", 3000), | |
233 | }; | |
234 | ||
636e2a39 HG |
235 | static const struct regulator_desc axp22x_drivevbus_regulator = { |
236 | .name = "drivevbus", | |
237 | .supply_name = "drivevbus", | |
238 | .of_match = of_match_ptr("drivevbus"), | |
239 | .regulators_node = of_match_ptr("regulators"), | |
240 | .type = REGULATOR_VOLTAGE, | |
241 | .owner = THIS_MODULE, | |
242 | .enable_reg = AXP20X_VBUS_IPSOUT_MGMT, | |
243 | .enable_mask = BIT(2), | |
244 | .ops = &axp20x_ops_sw, | |
245 | }; | |
246 | ||
a51f9f46 CYT |
247 | static const struct regulator_linear_range axp809_dcdc4_ranges[] = { |
248 | REGULATOR_LINEAR_RANGE(600000, 0x0, 0x2f, 20000), | |
249 | REGULATOR_LINEAR_RANGE(1800000, 0x30, 0x38, 100000), | |
250 | }; | |
251 | ||
252 | static const struct regulator_linear_range axp809_dldo1_ranges[] = { | |
253 | REGULATOR_LINEAR_RANGE(700000, 0x0, 0x1a, 100000), | |
254 | REGULATOR_LINEAR_RANGE(3400000, 0x1b, 0x1f, 200000), | |
255 | }; | |
256 | ||
257 | static const struct regulator_desc axp809_regulators[] = { | |
258 | AXP_DESC(AXP809, DCDC1, "dcdc1", "vin1", 1600, 3400, 100, | |
259 | AXP22X_DCDC1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(1)), | |
260 | AXP_DESC(AXP809, DCDC2, "dcdc2", "vin2", 600, 1540, 20, | |
261 | AXP22X_DCDC2_V_OUT, 0x3f, AXP22X_PWR_OUT_CTRL1, BIT(2)), | |
262 | AXP_DESC(AXP809, DCDC3, "dcdc3", "vin3", 600, 1860, 20, | |
263 | AXP22X_DCDC3_V_OUT, 0x3f, AXP22X_PWR_OUT_CTRL1, BIT(3)), | |
264 | AXP_DESC_RANGES(AXP809, DCDC4, "dcdc4", "vin4", axp809_dcdc4_ranges, | |
265 | 57, AXP22X_DCDC4_V_OUT, 0x3f, AXP22X_PWR_OUT_CTRL1, | |
266 | BIT(4)), | |
267 | AXP_DESC(AXP809, DCDC5, "dcdc5", "vin5", 1000, 2550, 50, | |
268 | AXP22X_DCDC5_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(5)), | |
269 | /* secondary switchable output of DCDC1 */ | |
270 | AXP_DESC_SW(AXP809, DC1SW, "dc1sw", NULL, AXP22X_PWR_OUT_CTRL2, | |
271 | BIT(7)), | |
272 | /* LDO regulator internally chained to DCDC5 */ | |
273 | AXP_DESC(AXP809, DC5LDO, "dc5ldo", NULL, 700, 1400, 100, | |
274 | AXP22X_DC5LDO_V_OUT, 0x7, AXP22X_PWR_OUT_CTRL1, BIT(0)), | |
275 | AXP_DESC(AXP809, ALDO1, "aldo1", "aldoin", 700, 3300, 100, | |
276 | AXP22X_ALDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(6)), | |
277 | AXP_DESC(AXP809, ALDO2, "aldo2", "aldoin", 700, 3300, 100, | |
278 | AXP22X_ALDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(7)), | |
279 | AXP_DESC(AXP809, ALDO3, "aldo3", "aldoin", 700, 3300, 100, | |
280 | AXP22X_ALDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(5)), | |
281 | AXP_DESC_RANGES(AXP809, DLDO1, "dldo1", "dldoin", axp809_dldo1_ranges, | |
282 | 32, AXP22X_DLDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, | |
283 | BIT(3)), | |
284 | AXP_DESC(AXP809, DLDO2, "dldo2", "dldoin", 700, 3300, 100, | |
285 | AXP22X_DLDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(4)), | |
286 | AXP_DESC(AXP809, ELDO1, "eldo1", "eldoin", 700, 3300, 100, | |
287 | AXP22X_ELDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(0)), | |
288 | AXP_DESC(AXP809, ELDO2, "eldo2", "eldoin", 700, 3300, 100, | |
289 | AXP22X_ELDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(1)), | |
290 | AXP_DESC(AXP809, ELDO3, "eldo3", "eldoin", 700, 3300, 100, | |
291 | AXP22X_ELDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(2)), | |
292 | AXP_DESC_IO(AXP809, LDO_IO0, "ldo_io0", "ips", 700, 3300, 100, | |
293 | AXP22X_LDO_IO0_V_OUT, 0x1f, AXP20X_GPIO0_CTRL, 0x07, | |
294 | AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), | |
295 | AXP_DESC_IO(AXP809, LDO_IO1, "ldo_io1", "ips", 700, 3300, 100, | |
296 | AXP22X_LDO_IO1_V_OUT, 0x1f, AXP20X_GPIO1_CTRL, 0x07, | |
297 | AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), | |
298 | AXP_DESC_FIXED(AXP809, RTC_LDO, "rtc_ldo", "ips", 1800), | |
299 | AXP_DESC_SW(AXP809, SW, "sw", "swin", AXP22X_PWR_OUT_CTRL2, BIT(6)), | |
300 | }; | |
301 | ||
dfe7a1b0 CC |
302 | static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq) |
303 | { | |
304 | struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent); | |
866bd951 BB |
305 | u32 min, max, def, step; |
306 | ||
307 | switch (axp20x->variant) { | |
308 | case AXP202_ID: | |
309 | case AXP209_ID: | |
310 | min = 750; | |
311 | max = 1875; | |
312 | def = 1500; | |
313 | step = 75; | |
314 | break; | |
1b82b4e4 | 315 | case AXP221_ID: |
04e0981c | 316 | case AXP223_ID: |
a51f9f46 | 317 | case AXP809_ID: |
1b82b4e4 BB |
318 | min = 1800; |
319 | max = 4050; | |
320 | def = 3000; | |
321 | step = 150; | |
322 | break; | |
866bd951 BB |
323 | default: |
324 | dev_err(&pdev->dev, | |
325 | "Setting DCDC frequency for unsupported AXP variant\n"); | |
326 | return -EINVAL; | |
327 | } | |
328 | ||
329 | if (dcdcfreq == 0) | |
330 | dcdcfreq = def; | |
dfe7a1b0 | 331 | |
866bd951 BB |
332 | if (dcdcfreq < min) { |
333 | dcdcfreq = min; | |
334 | dev_warn(&pdev->dev, "DCDC frequency too low. Set to %ukHz\n", | |
335 | min); | |
dfe7a1b0 CC |
336 | } |
337 | ||
866bd951 BB |
338 | if (dcdcfreq > max) { |
339 | dcdcfreq = max; | |
340 | dev_warn(&pdev->dev, "DCDC frequency too high. Set to %ukHz\n", | |
341 | max); | |
dfe7a1b0 CC |
342 | } |
343 | ||
866bd951 | 344 | dcdcfreq = (dcdcfreq - min) / step; |
dfe7a1b0 CC |
345 | |
346 | return regmap_update_bits(axp20x->regmap, AXP20X_DCDC_FREQ, | |
347 | AXP20X_FREQ_DCDC_MASK, dcdcfreq); | |
348 | } | |
349 | ||
350 | static int axp20x_regulator_parse_dt(struct platform_device *pdev) | |
351 | { | |
352 | struct device_node *np, *regulators; | |
353 | int ret; | |
866bd951 | 354 | u32 dcdcfreq = 0; |
dfe7a1b0 CC |
355 | |
356 | np = of_node_get(pdev->dev.parent->of_node); | |
357 | if (!np) | |
358 | return 0; | |
359 | ||
a6016c52 | 360 | regulators = of_get_child_by_name(np, "regulators"); |
dfe7a1b0 CC |
361 | if (!regulators) { |
362 | dev_warn(&pdev->dev, "regulators node not found\n"); | |
363 | } else { | |
dfe7a1b0 CC |
364 | of_property_read_u32(regulators, "x-powers,dcdc-freq", &dcdcfreq); |
365 | ret = axp20x_set_dcdc_freq(pdev, dcdcfreq); | |
366 | if (ret < 0) { | |
367 | dev_err(&pdev->dev, "Error setting dcdc frequency: %d\n", ret); | |
368 | return ret; | |
369 | } | |
370 | ||
371 | of_node_put(regulators); | |
372 | } | |
373 | ||
374 | return 0; | |
375 | } | |
376 | ||
377 | static int axp20x_set_dcdc_workmode(struct regulator_dev *rdev, int id, u32 workmode) | |
378 | { | |
866bd951 BB |
379 | struct axp20x_dev *axp20x = rdev_get_drvdata(rdev); |
380 | unsigned int mask; | |
dfe7a1b0 | 381 | |
866bd951 BB |
382 | switch (axp20x->variant) { |
383 | case AXP202_ID: | |
384 | case AXP209_ID: | |
385 | if ((id != AXP20X_DCDC2) && (id != AXP20X_DCDC3)) | |
386 | return -EINVAL; | |
387 | ||
388 | mask = AXP20X_WORKMODE_DCDC2_MASK; | |
389 | if (id == AXP20X_DCDC3) | |
390 | mask = AXP20X_WORKMODE_DCDC3_MASK; | |
dfe7a1b0 | 391 | |
866bd951 BB |
392 | workmode <<= ffs(mask) - 1; |
393 | break; | |
dfe7a1b0 | 394 | |
1b82b4e4 | 395 | case AXP221_ID: |
04e0981c | 396 | case AXP223_ID: |
a51f9f46 | 397 | case AXP809_ID: |
1b82b4e4 BB |
398 | if (id < AXP22X_DCDC1 || id > AXP22X_DCDC5) |
399 | return -EINVAL; | |
400 | ||
401 | mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP22X_DCDC1); | |
402 | workmode <<= id - AXP22X_DCDC1; | |
403 | break; | |
404 | ||
866bd951 BB |
405 | default: |
406 | /* should not happen */ | |
407 | WARN_ON(1); | |
408 | return -EINVAL; | |
409 | } | |
dfe7a1b0 CC |
410 | |
411 | return regmap_update_bits(rdev->regmap, AXP20X_DCDC_MODE, mask, workmode); | |
412 | } | |
413 | ||
414 | static int axp20x_regulator_probe(struct platform_device *pdev) | |
415 | { | |
416 | struct regulator_dev *rdev; | |
417 | struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent); | |
866bd951 | 418 | const struct regulator_desc *regulators; |
765e8023 CYT |
419 | struct regulator_config config = { |
420 | .dev = pdev->dev.parent, | |
421 | .regmap = axp20x->regmap, | |
866bd951 | 422 | .driver_data = axp20x, |
765e8023 | 423 | }; |
866bd951 | 424 | int ret, i, nregulators; |
dfe7a1b0 | 425 | u32 workmode; |
a51f9f46 CYT |
426 | const char *dcdc1_name = axp22x_regulators[AXP22X_DCDC1].name; |
427 | const char *dcdc5_name = axp22x_regulators[AXP22X_DCDC5].name; | |
636e2a39 | 428 | bool drivevbus = false; |
dfe7a1b0 | 429 | |
866bd951 BB |
430 | switch (axp20x->variant) { |
431 | case AXP202_ID: | |
432 | case AXP209_ID: | |
433 | regulators = axp20x_regulators; | |
434 | nregulators = AXP20X_REG_ID_MAX; | |
435 | break; | |
1b82b4e4 | 436 | case AXP221_ID: |
04e0981c | 437 | case AXP223_ID: |
1b82b4e4 BB |
438 | regulators = axp22x_regulators; |
439 | nregulators = AXP22X_REG_ID_MAX; | |
636e2a39 HG |
440 | drivevbus = of_property_read_bool(pdev->dev.parent->of_node, |
441 | "x-powers,drive-vbus-en"); | |
1b82b4e4 | 442 | break; |
a51f9f46 CYT |
443 | case AXP809_ID: |
444 | regulators = axp809_regulators; | |
445 | nregulators = AXP809_REG_ID_MAX; | |
446 | break; | |
866bd951 BB |
447 | default: |
448 | dev_err(&pdev->dev, "Unsupported AXP variant: %ld\n", | |
449 | axp20x->variant); | |
450 | return -EINVAL; | |
451 | } | |
452 | ||
765e8023 CYT |
453 | /* This only sets the dcdc freq. Ignore any errors */ |
454 | axp20x_regulator_parse_dt(pdev); | |
dfe7a1b0 | 455 | |
866bd951 | 456 | for (i = 0; i < nregulators; i++) { |
7118f19c CYT |
457 | const struct regulator_desc *desc = ®ulators[i]; |
458 | struct regulator_desc *new_desc; | |
459 | ||
460 | /* | |
461 | * Regulators DC1SW and DC5LDO are connected internally, | |
462 | * so we have to handle their supply names separately. | |
463 | * | |
464 | * We always register the regulators in proper sequence, | |
465 | * so the supply names are correctly read. See the last | |
466 | * part of this loop to see where we save the DT defined | |
467 | * name. | |
468 | */ | |
a51f9f46 CYT |
469 | if ((regulators == axp22x_regulators && i == AXP22X_DC1SW) || |
470 | (regulators == axp809_regulators && i == AXP809_DC1SW)) { | |
471 | new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc), | |
472 | GFP_KERNEL); | |
473 | *new_desc = regulators[i]; | |
474 | new_desc->supply_name = dcdc1_name; | |
475 | desc = new_desc; | |
476 | } | |
477 | ||
478 | if ((regulators == axp22x_regulators && i == AXP22X_DC5LDO) || | |
479 | (regulators == axp809_regulators && i == AXP809_DC5LDO)) { | |
480 | new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc), | |
481 | GFP_KERNEL); | |
482 | *new_desc = regulators[i]; | |
483 | new_desc->supply_name = dcdc5_name; | |
484 | desc = new_desc; | |
7118f19c CYT |
485 | } |
486 | ||
487 | rdev = devm_regulator_register(&pdev->dev, desc, &config); | |
dfe7a1b0 CC |
488 | if (IS_ERR(rdev)) { |
489 | dev_err(&pdev->dev, "Failed to register %s\n", | |
866bd951 | 490 | regulators[i].name); |
dfe7a1b0 CC |
491 | |
492 | return PTR_ERR(rdev); | |
493 | } | |
494 | ||
765e8023 CYT |
495 | ret = of_property_read_u32(rdev->dev.of_node, |
496 | "x-powers,dcdc-workmode", | |
dfe7a1b0 CC |
497 | &workmode); |
498 | if (!ret) { | |
499 | if (axp20x_set_dcdc_workmode(rdev, i, workmode)) | |
500 | dev_err(&pdev->dev, "Failed to set workmode on %s\n", | |
866bd951 | 501 | rdev->desc->name); |
dfe7a1b0 | 502 | } |
7118f19c CYT |
503 | |
504 | /* | |
505 | * Save AXP22X DCDC1 / DCDC5 regulator names for later. | |
506 | */ | |
a51f9f46 CYT |
507 | if ((regulators == axp22x_regulators && i == AXP22X_DCDC1) || |
508 | (regulators == axp809_regulators && i == AXP809_DCDC1)) | |
509 | of_property_read_string(rdev->dev.of_node, | |
510 | "regulator-name", | |
511 | &dcdc1_name); | |
512 | ||
513 | if ((regulators == axp22x_regulators && i == AXP22X_DCDC5) || | |
514 | (regulators == axp809_regulators && i == AXP809_DCDC5)) | |
515 | of_property_read_string(rdev->dev.of_node, | |
516 | "regulator-name", | |
517 | &dcdc5_name); | |
dfe7a1b0 CC |
518 | } |
519 | ||
636e2a39 HG |
520 | if (drivevbus) { |
521 | /* Change N_VBUSEN sense pin to DRIVEVBUS output pin */ | |
522 | regmap_update_bits(axp20x->regmap, AXP20X_OVER_TMP, | |
523 | AXP22X_MISC_N_VBUSEN_FUNC, 0); | |
524 | rdev = devm_regulator_register(&pdev->dev, | |
525 | &axp22x_drivevbus_regulator, | |
526 | &config); | |
527 | if (IS_ERR(rdev)) { | |
528 | dev_err(&pdev->dev, "Failed to register drivevbus\n"); | |
529 | return PTR_ERR(rdev); | |
530 | } | |
531 | } | |
532 | ||
dfe7a1b0 CC |
533 | return 0; |
534 | } | |
535 | ||
536 | static struct platform_driver axp20x_regulator_driver = { | |
537 | .probe = axp20x_regulator_probe, | |
538 | .driver = { | |
539 | .name = "axp20x-regulator", | |
dfe7a1b0 CC |
540 | }, |
541 | }; | |
542 | ||
543 | module_platform_driver(axp20x_regulator_driver); | |
544 | ||
545 | MODULE_LICENSE("GPL v2"); | |
546 | MODULE_AUTHOR("Carlo Caione <carlo@caione.org>"); | |
547 | MODULE_DESCRIPTION("Regulator Driver for AXP20X PMIC"); | |
d4ea7d86 | 548 | MODULE_ALIAS("platform:axp20x-regulator"); |