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1028a37d | 1 | /* |
7bd39354 JB |
2 | * da9211-regulator.h - Regulator definitions for DA9211/DA9213/DA9215 |
3 | * Copyright (C) 2015 Dialog Semiconductor Ltd. | |
1028a37d | 4 | * |
7bd39354 JB |
5 | * This program is free software; you can redistribute it and/or |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
1028a37d | 9 | * |
7bd39354 | 10 | * This program is distributed in the hope that it will be useful, |
1028a37d | 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
7bd39354 JB |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
13 | * GNU General Public License for more details. | |
1028a37d JB |
14 | */ |
15 | ||
16 | #ifndef __DA9211_REGISTERS_H__ | |
17 | #define __DA9211_REGISTERS_H__ | |
18 | ||
19 | /* Page selection */ | |
20 | #define DA9211_REG_PAGE_CON 0x00 | |
21 | ||
22 | /* System Control and Event Registers */ | |
23 | #define DA9211_REG_STATUS_A 0x50 | |
24 | #define DA9211_REG_STATUS_B 0x51 | |
25 | #define DA9211_REG_EVENT_A 0x52 | |
26 | #define DA9211_REG_EVENT_B 0x53 | |
27 | #define DA9211_REG_MASK_A 0x54 | |
28 | #define DA9211_REG_MASK_B 0x55 | |
29 | #define DA9211_REG_CONTROL_A 0x56 | |
30 | ||
31 | /* GPIO Control Registers */ | |
32 | #define DA9211_REG_GPIO_0_1 0x58 | |
33 | #define DA9211_REG_GPIO_2_3 0x59 | |
34 | #define DA9211_REG_GPIO_4 0x5A | |
35 | ||
36 | /* Regulator Registers */ | |
37 | #define DA9211_REG_BUCKA_CONT 0x5D | |
38 | #define DA9211_REG_BUCKB_CONT 0x5E | |
39 | #define DA9211_REG_BUCK_ILIM 0xD0 | |
40 | #define DA9211_REG_BUCKA_CONF 0xD1 | |
41 | #define DA9211_REG_BUCKB_CONF 0xD2 | |
42 | #define DA9211_REG_BUCK_CONF 0xD3 | |
43 | #define DA9211_REG_VBACKA_MAX 0xD5 | |
44 | #define DA9211_REG_VBACKB_MAX 0xD6 | |
45 | #define DA9211_REG_VBUCKA_A 0xD7 | |
46 | #define DA9211_REG_VBUCKA_B 0xD8 | |
47 | #define DA9211_REG_VBUCKB_A 0xD9 | |
48 | #define DA9211_REG_VBUCKB_B 0xDA | |
49 | ||
50 | /* I2C Interface Settings */ | |
51 | #define DA9211_REG_INTERFACE 0x105 | |
52 | ||
53 | /* BUCK Phase Selection*/ | |
54 | #define DA9211_REG_CONFIG_E 0x147 | |
55 | ||
005547e0 JB |
56 | /* Device ID */ |
57 | #define DA9211_REG_DEVICE_ID 0x201 | |
58 | ||
1028a37d JB |
59 | /* |
60 | * Registers bits | |
61 | */ | |
62 | /* DA9211_REG_PAGE_CON (addr=0x00) */ | |
63 | #define DA9211_REG_PAGE_SHIFT 1 | |
005547e0 | 64 | #define DA9211_REG_PAGE_MASK 0x06 |
1028a37d JB |
65 | /* On I2C registers 0x00 - 0xFF */ |
66 | #define DA9211_REG_PAGE0 0 | |
67 | /* On I2C registers 0x100 - 0x1FF */ | |
68 | #define DA9211_REG_PAGE2 2 | |
69 | #define DA9211_PAGE_WRITE_MODE 0x00 | |
70 | #define DA9211_REPEAT_WRITE_MODE 0x40 | |
71 | #define DA9211_PAGE_REVERT 0x80 | |
72 | ||
73 | /* DA9211_REG_STATUS_A (addr=0x50) */ | |
74 | #define DA9211_GPI0 0x01 | |
75 | #define DA9211_GPI1 0x02 | |
76 | #define DA9211_GPI2 0x04 | |
77 | #define DA9211_GPI3 0x08 | |
78 | #define DA9211_GPI4 0x10 | |
79 | ||
80 | /* DA9211_REG_EVENT_A (addr=0x52) */ | |
81 | #define DA9211_E_GPI0 0x01 | |
82 | #define DA9211_E_GPI1 0x02 | |
83 | #define DA9211_E_GPI2 0x04 | |
84 | #define DA9211_E_GPI3 0x08 | |
85 | #define DA9211_E_GPI4 0x10 | |
86 | #define DA9211_E_UVLO_IO 0x40 | |
87 | ||
88 | /* DA9211_REG_EVENT_B (addr=0x53) */ | |
89 | #define DA9211_E_PWRGOOD_A 0x01 | |
90 | #define DA9211_E_PWRGOOD_B 0x02 | |
91 | #define DA9211_E_TEMP_WARN 0x04 | |
92 | #define DA9211_E_TEMP_CRIT 0x08 | |
93 | #define DA9211_E_OV_CURR_A 0x10 | |
94 | #define DA9211_E_OV_CURR_B 0x20 | |
95 | ||
96 | /* DA9211_REG_MASK_A (addr=0x54) */ | |
97 | #define DA9211_M_GPI0 0x01 | |
98 | #define DA9211_M_GPI1 0x02 | |
99 | #define DA9211_M_GPI2 0x04 | |
100 | #define DA9211_M_GPI3 0x08 | |
101 | #define DA9211_M_GPI4 0x10 | |
102 | #define DA9211_M_UVLO_IO 0x40 | |
103 | ||
104 | /* DA9211_REG_MASK_B (addr=0x55) */ | |
105 | #define DA9211_M_PWRGOOD_A 0x01 | |
106 | #define DA9211_M_PWRGOOD_B 0x02 | |
107 | #define DA9211_M_TEMP_WARN 0x04 | |
108 | #define DA9211_M_TEMP_CRIT 0x08 | |
109 | #define DA9211_M_OV_CURR_A 0x10 | |
110 | #define DA9211_M_OV_CURR_B 0x20 | |
111 | ||
112 | /* DA9211_REG_CONTROL_A (addr=0x56) */ | |
113 | #define DA9211_DEBOUNCING_SHIFT 0 | |
114 | #define DA9211_DEBOUNCING_MASK 0x07 | |
115 | #define DA9211_SLEW_RATE_SHIFT 3 | |
116 | #define DA9211_SLEW_RATE_A_MASK 0x18 | |
117 | #define DA9211_SLEW_RATE_B_SHIFT 5 | |
118 | #define DA9211_SLEW_RATE_B_MASK 0x60 | |
119 | #define DA9211_V_LOCK 0x80 | |
120 | ||
121 | /* DA9211_REG_GPIO_0_1 (addr=0x58) */ | |
122 | #define DA9211_GPIO0_PIN_SHIFT 0 | |
123 | #define DA9211_GPIO0_PIN_MASK 0x03 | |
124 | #define DA9211_GPIO0_PIN_GPI 0x00 | |
125 | #define DA9211_GPIO0_PIN_GPO_OD 0x02 | |
126 | #define DA9211_GPIO0_PIN_GPO 0x03 | |
127 | #define DA9211_GPIO0_TYPE 0x04 | |
128 | #define DA9211_GPIO0_TYPE_GPI 0x00 | |
129 | #define DA9211_GPIO0_TYPE_GPO 0x04 | |
130 | #define DA9211_GPIO0_MODE 0x08 | |
131 | #define DA9211_GPIO1_PIN_SHIFT 4 | |
132 | #define DA9211_GPIO1_PIN_MASK 0x30 | |
133 | #define DA9211_GPIO1_PIN_GPI 0x00 | |
134 | #define DA9211_GPIO1_PIN_VERROR 0x10 | |
135 | #define DA9211_GPIO1_PIN_GPO_OD 0x20 | |
136 | #define DA9211_GPIO1_PIN_GPO 0x30 | |
137 | #define DA9211_GPIO1_TYPE_SHIFT 0x40 | |
138 | #define DA9211_GPIO1_TYPE_GPI 0x00 | |
139 | #define DA9211_GPIO1_TYPE_GPO 0x40 | |
140 | #define DA9211_GPIO1_MODE 0x80 | |
141 | ||
142 | /* DA9211_REG_GPIO_2_3 (addr=0x59) */ | |
143 | #define DA9211_GPIO2_PIN_SHIFT 0 | |
144 | #define DA9211_GPIO2_PIN_MASK 0x03 | |
145 | #define DA9211_GPIO2_PIN_GPI 0x00 | |
146 | #define DA9211_GPIO5_PIN_BUCK_CLK 0x10 | |
147 | #define DA9211_GPIO2_PIN_GPO_OD 0x02 | |
148 | #define DA9211_GPIO2_PIN_GPO 0x03 | |
149 | #define DA9211_GPIO2_TYPE 0x04 | |
150 | #define DA9211_GPIO2_TYPE_GPI 0x00 | |
151 | #define DA9211_GPIO2_TYPE_GPO 0x04 | |
152 | #define DA9211_GPIO2_MODE 0x08 | |
153 | #define DA9211_GPIO3_PIN_SHIFT 4 | |
154 | #define DA9211_GPIO3_PIN_MASK 0x30 | |
155 | #define DA9211_GPIO3_PIN_GPI 0x00 | |
156 | #define DA9211_GPIO3_PIN_IERROR 0x10 | |
157 | #define DA9211_GPIO3_PIN_GPO_OD 0x20 | |
158 | #define DA9211_GPIO3_PIN_GPO 0x30 | |
159 | #define DA9211_GPIO3_TYPE_SHIFT 0x40 | |
160 | #define DA9211_GPIO3_TYPE_GPI 0x00 | |
161 | #define DA9211_GPIO3_TYPE_GPO 0x40 | |
162 | #define DA9211_GPIO3_MODE 0x80 | |
163 | ||
164 | /* DA9211_REG_GPIO_4 (addr=0x5A) */ | |
165 | #define DA9211_GPIO4_PIN_SHIFT 0 | |
166 | #define DA9211_GPIO4_PIN_MASK 0x03 | |
167 | #define DA9211_GPIO4_PIN_GPI 0x00 | |
168 | #define DA9211_GPIO4_PIN_GPO_OD 0x02 | |
169 | #define DA9211_GPIO4_PIN_GPO 0x03 | |
170 | #define DA9211_GPIO4_TYPE 0x04 | |
171 | #define DA9211_GPIO4_TYPE_GPI 0x00 | |
172 | #define DA9211_GPIO4_TYPE_GPO 0x04 | |
173 | #define DA9211_GPIO4_MODE 0x08 | |
174 | ||
175 | /* DA9211_REG_BUCKA_CONT (addr=0x5D) */ | |
176 | #define DA9211_BUCKA_EN 0x01 | |
177 | #define DA9211_BUCKA_GPI_SHIFT 1 | |
178 | #define DA9211_BUCKA_GPI_MASK 0x06 | |
179 | #define DA9211_BUCKA_GPI_OFF 0x00 | |
180 | #define DA9211_BUCKA_GPI_GPIO0 0x02 | |
181 | #define DA9211_BUCKA_GPI_GPIO1 0x04 | |
182 | #define DA9211_BUCKA_GPI_GPIO3 0x06 | |
183 | #define DA9211_BUCKA_PD_DIS 0x08 | |
184 | #define DA9211_VBUCKA_SEL 0x10 | |
185 | #define DA9211_VBUCKA_SEL_A 0x00 | |
186 | #define DA9211_VBUCKA_SEL_B 0x10 | |
187 | #define DA9211_VBUCKA_GPI_SHIFT 5 | |
188 | #define DA9211_VBUCKA_GPI_MASK 0x60 | |
189 | #define DA9211_VBUCKA_GPI_OFF 0x00 | |
190 | #define DA9211_VBUCKA_GPI_GPIO1 0x20 | |
191 | #define DA9211_VBUCKA_GPI_GPIO2 0x40 | |
192 | #define DA9211_VBUCKA_GPI_GPIO4 0x60 | |
193 | ||
194 | /* DA9211_REG_BUCKB_CONT (addr=0x5E) */ | |
195 | #define DA9211_BUCKB_EN 0x01 | |
196 | #define DA9211_BUCKB_GPI_SHIFT 1 | |
197 | #define DA9211_BUCKB_GPI_MASK 0x06 | |
198 | #define DA9211_BUCKB_GPI_OFF 0x00 | |
199 | #define DA9211_BUCKB_GPI_GPIO0 0x02 | |
200 | #define DA9211_BUCKB_GPI_GPIO1 0x04 | |
201 | #define DA9211_BUCKB_GPI_GPIO3 0x06 | |
202 | #define DA9211_BUCKB_PD_DIS 0x08 | |
203 | #define DA9211_VBUCKB_SEL 0x10 | |
204 | #define DA9211_VBUCKB_SEL_A 0x00 | |
205 | #define DA9211_VBUCKB_SEL_B 0x10 | |
206 | #define DA9211_VBUCKB_GPI_SHIFT 5 | |
207 | #define DA9211_VBUCKB_GPI_MASK 0x60 | |
208 | #define DA9211_VBUCKB_GPI_OFF 0x00 | |
209 | #define DA9211_VBUCKB_GPI_GPIO1 0x20 | |
210 | #define DA9211_VBUCKB_GPI_GPIO2 0x40 | |
211 | #define DA9211_VBUCKB_GPI_GPIO4 0x60 | |
212 | ||
213 | /* DA9211_REG_BUCK_ILIM (addr=0xD0) */ | |
214 | #define DA9211_BUCKA_ILIM_SHIFT 0 | |
215 | #define DA9211_BUCKA_ILIM_MASK 0x0F | |
216 | #define DA9211_BUCKB_ILIM_SHIFT 4 | |
217 | #define DA9211_BUCKB_ILIM_MASK 0xF0 | |
218 | ||
219 | /* DA9211_REG_BUCKA_CONF (addr=0xD1) */ | |
220 | #define DA9211_BUCKA_MODE_SHIFT 0 | |
221 | #define DA9211_BUCKA_MODE_MASK 0x03 | |
222 | #define DA9211_BUCKA_MODE_MANUAL 0x00 | |
223 | #define DA9211_BUCKA_MODE_SLEEP 0x01 | |
224 | #define DA9211_BUCKA_MODE_SYNC 0x02 | |
225 | #define DA9211_BUCKA_MODE_AUTO 0x03 | |
226 | #define DA9211_BUCKA_UP_CTRL_SHIFT 2 | |
227 | #define DA9211_BUCKA_UP_CTRL_MASK 0x1C | |
228 | #define DA9211_BUCKA_DOWN_CTRL_SHIFT 5 | |
229 | #define DA9211_BUCKA_DOWN_CTRL_MASK 0xE0 | |
230 | ||
231 | /* DA9211_REG_BUCKB_CONF (addr=0xD2) */ | |
232 | #define DA9211_BUCKB_MODE_SHIFT 0 | |
233 | #define DA9211_BUCKB_MODE_MASK 0x03 | |
234 | #define DA9211_BUCKB_MODE_MANUAL 0x00 | |
235 | #define DA9211_BUCKB_MODE_SLEEP 0x01 | |
236 | #define DA9211_BUCKB_MODE_SYNC 0x02 | |
237 | #define DA9211_BUCKB_MODE_AUTO 0x03 | |
238 | #define DA9211_BUCKB_UP_CTRL_SHIFT 2 | |
239 | #define DA9211_BUCKB_UP_CTRL_MASK 0x1C | |
240 | #define DA9211_BUCKB_DOWN_CTRL_SHIFT 5 | |
241 | #define DA9211_BUCKB_DOWN_CTRL_MASK 0xE0 | |
242 | ||
243 | /* DA9211_REG_BUCK_CONF (addr=0xD3) */ | |
244 | #define DA9211_PHASE_SEL_A_SHIFT 0 | |
245 | #define DA9211_PHASE_SEL_A_MASK 0x03 | |
246 | #define DA9211_PHASE_SEL_B_SHIFT 2 | |
247 | #define DA9211_PHASE_SEL_B_MASK 0x04 | |
248 | #define DA9211_PH_SH_EN_A_SHIFT 3 | |
249 | #define DA9211_PH_SH_EN_A_MASK 0x08 | |
250 | #define DA9211_PH_SH_EN_B_SHIFT 4 | |
251 | #define DA9211_PH_SH_EN_B_MASK 0x10 | |
252 | ||
253 | /* DA9211_REG_VBUCKA_MAX (addr=0xD5) */ | |
254 | #define DA9211_VBUCKA_BASE_SHIFT 0 | |
255 | #define DA9211_VBUCKA_BASE_MASK 0x7F | |
256 | ||
257 | /* DA9211_REG_VBUCKB_MAX (addr=0xD6) */ | |
258 | #define DA9211_VBUCKB_BASE_SHIFT 0 | |
259 | #define DA9211_VBUCKB_BASE_MASK 0x7F | |
260 | ||
261 | /* DA9211_REG_VBUCKA/B_A/B (addr=0xD7/0xD8/0xD9/0xDA) */ | |
262 | #define DA9211_VBUCK_SHIFT 0 | |
263 | #define DA9211_VBUCK_MASK 0x7F | |
264 | #define DA9211_VBUCK_BIAS 0 | |
265 | #define DA9211_BUCK_SL 0x80 | |
266 | ||
267 | /* DA9211_REG_INTERFACE (addr=0x105) */ | |
268 | #define DA9211_IF_BASE_ADDR_SHIFT 4 | |
269 | #define DA9211_IF_BASE_ADDR_MASK 0xF0 | |
270 | ||
271 | /* DA9211_REG_CONFIG_E (addr=0x147) */ | |
272 | #define DA9211_SLAVE_SEL 0x40 | |
273 | ||
274 | #endif /* __DA9211_REGISTERS_H__ */ |