Commit | Line | Data |
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5b1c2028 LD |
1 | /* |
2 | * Maxim MAX77620 Regulator driver | |
3 | * | |
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | |
5 | * | |
6 | * Author: Mallikarjun Kasoju <mkasoju@nvidia.com> | |
7 | * Laxman Dewangan <ldewangan@nvidia.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms and conditions of the GNU General Public License, | |
11 | * version 2, as published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/init.h> | |
15 | #include <linux/mfd/max77620.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/of.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/regmap.h> | |
20 | #include <linux/regulator/driver.h> | |
21 | #include <linux/regulator/machine.h> | |
22 | #include <linux/regulator/of_regulator.h> | |
23 | ||
24 | #define max77620_rails(_name) "max77620-"#_name | |
25 | ||
26 | /* Power Mode */ | |
27 | #define MAX77620_POWER_MODE_NORMAL 3 | |
28 | #define MAX77620_POWER_MODE_LPM 2 | |
29 | #define MAX77620_POWER_MODE_GLPM 1 | |
30 | #define MAX77620_POWER_MODE_DISABLE 0 | |
31 | ||
32 | /* SD Slew Rate */ | |
33 | #define MAX77620_SD_SR_13_75 0 | |
34 | #define MAX77620_SD_SR_27_5 1 | |
35 | #define MAX77620_SD_SR_55 2 | |
36 | #define MAX77620_SD_SR_100 3 | |
37 | ||
38 | enum max77620_regulators { | |
39 | MAX77620_REGULATOR_ID_SD0, | |
40 | MAX77620_REGULATOR_ID_SD1, | |
41 | MAX77620_REGULATOR_ID_SD2, | |
42 | MAX77620_REGULATOR_ID_SD3, | |
43 | MAX77620_REGULATOR_ID_SD4, | |
44 | MAX77620_REGULATOR_ID_LDO0, | |
45 | MAX77620_REGULATOR_ID_LDO1, | |
46 | MAX77620_REGULATOR_ID_LDO2, | |
47 | MAX77620_REGULATOR_ID_LDO3, | |
48 | MAX77620_REGULATOR_ID_LDO4, | |
49 | MAX77620_REGULATOR_ID_LDO5, | |
50 | MAX77620_REGULATOR_ID_LDO6, | |
51 | MAX77620_REGULATOR_ID_LDO7, | |
52 | MAX77620_REGULATOR_ID_LDO8, | |
53 | MAX77620_NUM_REGS, | |
54 | }; | |
55 | ||
56 | /* Regulator types */ | |
57 | enum max77620_regulator_type { | |
58 | MAX77620_REGULATOR_TYPE_SD, | |
59 | MAX77620_REGULATOR_TYPE_LDO_N, | |
60 | MAX77620_REGULATOR_TYPE_LDO_P, | |
61 | }; | |
62 | ||
63 | struct max77620_regulator_info { | |
64 | u8 type; | |
5b1c2028 LD |
65 | u8 fps_addr; |
66 | u8 volt_addr; | |
67 | u8 cfg_addr; | |
5b1c2028 LD |
68 | u8 power_mode_mask; |
69 | u8 power_mode_shift; | |
70 | u8 remote_sense_addr; | |
71 | u8 remote_sense_mask; | |
72 | struct regulator_desc desc; | |
73 | }; | |
74 | ||
75 | struct max77620_regulator_pdata { | |
76 | struct regulator_init_data *reg_idata; | |
77 | int active_fps_src; | |
78 | int active_fps_pd_slot; | |
79 | int active_fps_pu_slot; | |
80 | int suspend_fps_src; | |
81 | int suspend_fps_pd_slot; | |
82 | int suspend_fps_pu_slot; | |
83 | int current_mode; | |
5aa43599 | 84 | int ramp_rate_setting; |
5b1c2028 LD |
85 | }; |
86 | ||
87 | struct max77620_regulator { | |
88 | struct device *dev; | |
89 | struct regmap *rmap; | |
90 | struct max77620_regulator_info *rinfo[MAX77620_NUM_REGS]; | |
91 | struct max77620_regulator_pdata reg_pdata[MAX77620_NUM_REGS]; | |
5b1c2028 LD |
92 | int enable_power_mode[MAX77620_NUM_REGS]; |
93 | int current_power_mode[MAX77620_NUM_REGS]; | |
94 | int active_fps_src[MAX77620_NUM_REGS]; | |
95 | }; | |
96 | ||
97 | #define fps_src_name(fps_src) \ | |
98 | (fps_src == MAX77620_FPS_SRC_0 ? "FPS_SRC_0" : \ | |
99 | fps_src == MAX77620_FPS_SRC_1 ? "FPS_SRC_1" : \ | |
100 | fps_src == MAX77620_FPS_SRC_2 ? "FPS_SRC_2" : "FPS_SRC_NONE") | |
101 | ||
102 | static int max77620_regulator_get_fps_src(struct max77620_regulator *pmic, | |
103 | int id) | |
104 | { | |
105 | struct max77620_regulator_info *rinfo = pmic->rinfo[id]; | |
106 | unsigned int val; | |
107 | int ret; | |
108 | ||
109 | ret = regmap_read(pmic->rmap, rinfo->fps_addr, &val); | |
110 | if (ret < 0) { | |
111 | dev_err(pmic->dev, "Reg 0x%02x read failed %d\n", | |
112 | rinfo->fps_addr, ret); | |
113 | return ret; | |
114 | } | |
115 | ||
116 | return (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT; | |
117 | } | |
118 | ||
119 | static int max77620_regulator_set_fps_src(struct max77620_regulator *pmic, | |
120 | int fps_src, int id) | |
121 | { | |
122 | struct max77620_regulator_info *rinfo = pmic->rinfo[id]; | |
123 | unsigned int val; | |
124 | int ret; | |
125 | ||
91ff811f VRT |
126 | if (!rinfo) |
127 | return 0; | |
128 | ||
5b1c2028 LD |
129 | switch (fps_src) { |
130 | case MAX77620_FPS_SRC_0: | |
131 | case MAX77620_FPS_SRC_1: | |
132 | case MAX77620_FPS_SRC_2: | |
133 | case MAX77620_FPS_SRC_NONE: | |
134 | break; | |
135 | ||
136 | case MAX77620_FPS_SRC_DEF: | |
137 | ret = regmap_read(pmic->rmap, rinfo->fps_addr, &val); | |
138 | if (ret < 0) { | |
139 | dev_err(pmic->dev, "Reg 0x%02x read failed %d\n", | |
140 | rinfo->fps_addr, ret); | |
141 | return ret; | |
142 | } | |
143 | ret = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT; | |
144 | pmic->active_fps_src[id] = ret; | |
145 | return 0; | |
146 | ||
147 | default: | |
148 | dev_err(pmic->dev, "Invalid FPS %d for regulator %d\n", | |
149 | fps_src, id); | |
150 | return -EINVAL; | |
151 | } | |
152 | ||
153 | ret = regmap_update_bits(pmic->rmap, rinfo->fps_addr, | |
154 | MAX77620_FPS_SRC_MASK, | |
155 | fps_src << MAX77620_FPS_SRC_SHIFT); | |
156 | if (ret < 0) { | |
157 | dev_err(pmic->dev, "Reg 0x%02x update failed %d\n", | |
158 | rinfo->fps_addr, ret); | |
159 | return ret; | |
160 | } | |
161 | pmic->active_fps_src[id] = fps_src; | |
162 | ||
163 | return 0; | |
164 | } | |
165 | ||
166 | static int max77620_regulator_set_fps_slots(struct max77620_regulator *pmic, | |
167 | int id, bool is_suspend) | |
168 | { | |
169 | struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id]; | |
170 | struct max77620_regulator_info *rinfo = pmic->rinfo[id]; | |
171 | unsigned int val = 0; | |
172 | unsigned int mask = 0; | |
173 | int pu = rpdata->active_fps_pu_slot; | |
174 | int pd = rpdata->active_fps_pd_slot; | |
175 | int ret = 0; | |
176 | ||
91ff811f VRT |
177 | if (!rinfo) |
178 | return 0; | |
179 | ||
5b1c2028 LD |
180 | if (is_suspend) { |
181 | pu = rpdata->suspend_fps_pu_slot; | |
182 | pd = rpdata->suspend_fps_pd_slot; | |
183 | } | |
184 | ||
185 | /* FPS power up period setting */ | |
186 | if (pu >= 0) { | |
187 | val |= (pu << MAX77620_FPS_PU_PERIOD_SHIFT); | |
188 | mask |= MAX77620_FPS_PU_PERIOD_MASK; | |
189 | } | |
190 | ||
191 | /* FPS power down period setting */ | |
192 | if (pd >= 0) { | |
193 | val |= (pd << MAX77620_FPS_PD_PERIOD_SHIFT); | |
194 | mask |= MAX77620_FPS_PD_PERIOD_MASK; | |
195 | } | |
196 | ||
197 | if (mask) { | |
198 | ret = regmap_update_bits(pmic->rmap, rinfo->fps_addr, | |
199 | mask, val); | |
200 | if (ret < 0) { | |
201 | dev_err(pmic->dev, "Reg 0x%02x update failed: %d\n", | |
202 | rinfo->fps_addr, ret); | |
203 | return ret; | |
204 | } | |
205 | } | |
206 | ||
207 | return ret; | |
208 | } | |
209 | ||
210 | static int max77620_regulator_set_power_mode(struct max77620_regulator *pmic, | |
211 | int power_mode, int id) | |
212 | { | |
213 | struct max77620_regulator_info *rinfo = pmic->rinfo[id]; | |
214 | u8 mask = rinfo->power_mode_mask; | |
215 | u8 shift = rinfo->power_mode_shift; | |
216 | u8 addr; | |
217 | int ret; | |
218 | ||
219 | switch (rinfo->type) { | |
220 | case MAX77620_REGULATOR_TYPE_SD: | |
221 | addr = rinfo->cfg_addr; | |
222 | break; | |
223 | default: | |
224 | addr = rinfo->volt_addr; | |
225 | break; | |
226 | } | |
227 | ||
228 | ret = regmap_update_bits(pmic->rmap, addr, mask, power_mode << shift); | |
229 | if (ret < 0) { | |
230 | dev_err(pmic->dev, "Regulator %d mode set failed: %d\n", | |
231 | id, ret); | |
232 | return ret; | |
233 | } | |
234 | pmic->current_power_mode[id] = power_mode; | |
235 | ||
236 | return ret; | |
237 | } | |
238 | ||
239 | static int max77620_regulator_get_power_mode(struct max77620_regulator *pmic, | |
240 | int id) | |
241 | { | |
242 | struct max77620_regulator_info *rinfo = pmic->rinfo[id]; | |
243 | unsigned int val, addr; | |
244 | u8 mask = rinfo->power_mode_mask; | |
245 | u8 shift = rinfo->power_mode_shift; | |
246 | int ret; | |
247 | ||
248 | switch (rinfo->type) { | |
249 | case MAX77620_REGULATOR_TYPE_SD: | |
250 | addr = rinfo->cfg_addr; | |
251 | break; | |
252 | default: | |
253 | addr = rinfo->volt_addr; | |
254 | break; | |
255 | } | |
256 | ||
257 | ret = regmap_read(pmic->rmap, addr, &val); | |
258 | if (ret < 0) { | |
259 | dev_err(pmic->dev, "Regulator %d: Reg 0x%02x read failed: %d\n", | |
260 | id, addr, ret); | |
261 | return ret; | |
262 | } | |
263 | ||
264 | return (val & mask) >> shift; | |
265 | } | |
266 | ||
267 | static int max77620_read_slew_rate(struct max77620_regulator *pmic, int id) | |
268 | { | |
269 | struct max77620_regulator_info *rinfo = pmic->rinfo[id]; | |
270 | unsigned int rval; | |
271 | int slew_rate; | |
272 | int ret; | |
273 | ||
aad76f74 AL |
274 | ret = regmap_read(pmic->rmap, rinfo->cfg_addr, &rval); |
275 | if (ret < 0) { | |
276 | dev_err(pmic->dev, "Register 0x%02x read failed: %d\n", | |
277 | rinfo->cfg_addr, ret); | |
278 | return ret; | |
279 | } | |
280 | ||
5b1c2028 LD |
281 | switch (rinfo->type) { |
282 | case MAX77620_REGULATOR_TYPE_SD: | |
5b1c2028 LD |
283 | slew_rate = (rval >> MAX77620_SD_SR_SHIFT) & 0x3; |
284 | switch (slew_rate) { | |
285 | case 0: | |
286 | slew_rate = 13750; | |
287 | break; | |
288 | case 1: | |
289 | slew_rate = 27500; | |
290 | break; | |
291 | case 2: | |
292 | slew_rate = 55000; | |
293 | break; | |
294 | case 3: | |
295 | slew_rate = 100000; | |
296 | break; | |
297 | } | |
298 | rinfo->desc.ramp_delay = slew_rate; | |
299 | break; | |
300 | default: | |
5b1c2028 LD |
301 | slew_rate = rval & 0x1; |
302 | switch (slew_rate) { | |
303 | case 0: | |
304 | slew_rate = 100000; | |
305 | break; | |
306 | case 1: | |
307 | slew_rate = 5000; | |
308 | break; | |
309 | } | |
310 | rinfo->desc.ramp_delay = slew_rate; | |
311 | break; | |
312 | } | |
313 | ||
314 | return 0; | |
315 | } | |
316 | ||
5aa43599 LD |
317 | static int max77620_set_slew_rate(struct max77620_regulator *pmic, int id, |
318 | int slew_rate) | |
319 | { | |
320 | struct max77620_regulator_info *rinfo = pmic->rinfo[id]; | |
321 | unsigned int val; | |
322 | int ret; | |
323 | u8 mask; | |
324 | ||
325 | if (rinfo->type == MAX77620_REGULATOR_TYPE_SD) { | |
326 | if (slew_rate <= 13750) | |
327 | val = 0; | |
328 | else if (slew_rate <= 27500) | |
329 | val = 1; | |
330 | else if (slew_rate <= 55000) | |
331 | val = 2; | |
332 | else | |
333 | val = 3; | |
334 | val <<= MAX77620_SD_SR_SHIFT; | |
335 | mask = MAX77620_SD_SR_MASK; | |
336 | } else { | |
337 | if (slew_rate <= 5000) | |
338 | val = 1; | |
339 | else | |
340 | val = 0; | |
341 | mask = MAX77620_LDO_SLEW_RATE_MASK; | |
342 | } | |
343 | ||
344 | ret = regmap_update_bits(pmic->rmap, rinfo->cfg_addr, mask, val); | |
345 | if (ret < 0) { | |
346 | dev_err(pmic->dev, "Regulator %d slew rate set failed: %d\n", | |
347 | id, ret); | |
348 | return ret; | |
349 | } | |
350 | ||
351 | return 0; | |
352 | } | |
353 | ||
5b1c2028 LD |
354 | static int max77620_init_pmic(struct max77620_regulator *pmic, int id) |
355 | { | |
356 | struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id]; | |
357 | int ret; | |
358 | ||
359 | /* Update power mode */ | |
360 | ret = max77620_regulator_get_power_mode(pmic, id); | |
361 | if (ret < 0) | |
362 | return ret; | |
363 | ||
364 | pmic->current_power_mode[id] = ret; | |
365 | pmic->enable_power_mode[id] = MAX77620_POWER_MODE_NORMAL; | |
366 | ||
367 | if (rpdata->active_fps_src == MAX77620_FPS_SRC_DEF) { | |
368 | ret = max77620_regulator_get_fps_src(pmic, id); | |
369 | if (ret < 0) | |
370 | return ret; | |
371 | rpdata->active_fps_src = ret; | |
372 | } | |
373 | ||
374 | /* If rails are externally control of FPS then enable it always. */ | |
375 | if (rpdata->active_fps_src == MAX77620_FPS_SRC_NONE) { | |
376 | ret = max77620_regulator_set_power_mode(pmic, | |
377 | pmic->enable_power_mode[id], id); | |
378 | if (ret < 0) | |
379 | return ret; | |
380 | } else { | |
381 | if (pmic->current_power_mode[id] != | |
382 | pmic->enable_power_mode[id]) { | |
383 | ret = max77620_regulator_set_power_mode(pmic, | |
384 | pmic->enable_power_mode[id], id); | |
385 | if (ret < 0) | |
386 | return ret; | |
387 | } | |
388 | } | |
389 | ||
390 | ret = max77620_regulator_set_fps_src(pmic, rpdata->active_fps_src, id); | |
391 | if (ret < 0) | |
392 | return ret; | |
393 | ||
394 | ret = max77620_regulator_set_fps_slots(pmic, id, false); | |
395 | if (ret < 0) | |
396 | return ret; | |
397 | ||
5aa43599 LD |
398 | if (rpdata->ramp_rate_setting) { |
399 | ret = max77620_set_slew_rate(pmic, id, | |
400 | rpdata->ramp_rate_setting); | |
401 | if (ret < 0) | |
402 | return ret; | |
403 | } | |
404 | ||
5b1c2028 LD |
405 | return 0; |
406 | } | |
407 | ||
408 | static int max77620_regulator_enable(struct regulator_dev *rdev) | |
409 | { | |
410 | struct max77620_regulator *pmic = rdev_get_drvdata(rdev); | |
411 | int id = rdev_get_id(rdev); | |
412 | ||
413 | if (pmic->active_fps_src[id] != MAX77620_FPS_SRC_NONE) | |
414 | return 0; | |
415 | ||
416 | return max77620_regulator_set_power_mode(pmic, | |
417 | pmic->enable_power_mode[id], id); | |
418 | } | |
419 | ||
420 | static int max77620_regulator_disable(struct regulator_dev *rdev) | |
421 | { | |
422 | struct max77620_regulator *pmic = rdev_get_drvdata(rdev); | |
423 | int id = rdev_get_id(rdev); | |
424 | ||
425 | if (pmic->active_fps_src[id] != MAX77620_FPS_SRC_NONE) | |
426 | return 0; | |
427 | ||
428 | return max77620_regulator_set_power_mode(pmic, | |
429 | MAX77620_POWER_MODE_DISABLE, id); | |
430 | } | |
431 | ||
432 | static int max77620_regulator_is_enabled(struct regulator_dev *rdev) | |
433 | { | |
434 | struct max77620_regulator *pmic = rdev_get_drvdata(rdev); | |
435 | int id = rdev_get_id(rdev); | |
436 | int ret = 1; | |
437 | ||
438 | if (pmic->active_fps_src[id] != MAX77620_FPS_SRC_NONE) | |
439 | return 1; | |
440 | ||
441 | ret = max77620_regulator_get_power_mode(pmic, id); | |
442 | if (ret < 0) | |
443 | return ret; | |
444 | ||
445 | if (ret != MAX77620_POWER_MODE_DISABLE) | |
446 | return 1; | |
447 | ||
448 | return 0; | |
449 | } | |
450 | ||
451 | static int max77620_regulator_set_mode(struct regulator_dev *rdev, | |
452 | unsigned int mode) | |
453 | { | |
454 | struct max77620_regulator *pmic = rdev_get_drvdata(rdev); | |
455 | int id = rdev_get_id(rdev); | |
456 | struct max77620_regulator_info *rinfo = pmic->rinfo[id]; | |
457 | struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id]; | |
458 | bool fpwm = false; | |
459 | int power_mode; | |
460 | int ret; | |
461 | u8 val; | |
462 | ||
463 | switch (mode) { | |
464 | case REGULATOR_MODE_FAST: | |
465 | fpwm = true; | |
466 | power_mode = MAX77620_POWER_MODE_NORMAL; | |
467 | break; | |
468 | ||
469 | case REGULATOR_MODE_NORMAL: | |
470 | power_mode = MAX77620_POWER_MODE_NORMAL; | |
471 | break; | |
472 | ||
473 | case REGULATOR_MODE_IDLE: | |
474 | power_mode = MAX77620_POWER_MODE_LPM; | |
475 | break; | |
476 | ||
477 | default: | |
478 | dev_err(pmic->dev, "Regulator %d mode %d is invalid\n", | |
479 | id, mode); | |
480 | return -EINVAL; | |
481 | } | |
482 | ||
483 | if (rinfo->type != MAX77620_REGULATOR_TYPE_SD) | |
484 | goto skip_fpwm; | |
485 | ||
486 | val = (fpwm) ? MAX77620_SD_FPWM_MASK : 0; | |
487 | ret = regmap_update_bits(pmic->rmap, rinfo->cfg_addr, | |
488 | MAX77620_SD_FPWM_MASK, val); | |
489 | if (ret < 0) { | |
490 | dev_err(pmic->dev, "Reg 0x%02x update failed: %d\n", | |
491 | rinfo->cfg_addr, ret); | |
492 | return ret; | |
493 | } | |
494 | rpdata->current_mode = mode; | |
495 | ||
496 | skip_fpwm: | |
497 | ret = max77620_regulator_set_power_mode(pmic, power_mode, id); | |
498 | if (ret < 0) | |
499 | return ret; | |
500 | ||
501 | pmic->enable_power_mode[id] = power_mode; | |
502 | ||
503 | return 0; | |
504 | } | |
505 | ||
506 | static unsigned int max77620_regulator_get_mode(struct regulator_dev *rdev) | |
507 | { | |
508 | struct max77620_regulator *pmic = rdev_get_drvdata(rdev); | |
509 | int id = rdev_get_id(rdev); | |
510 | struct max77620_regulator_info *rinfo = pmic->rinfo[id]; | |
511 | int fpwm = 0; | |
512 | int ret; | |
513 | int pm_mode, reg_mode; | |
514 | unsigned int val; | |
515 | ||
516 | ret = max77620_regulator_get_power_mode(pmic, id); | |
517 | if (ret < 0) | |
518 | return 0; | |
519 | ||
520 | pm_mode = ret; | |
521 | ||
522 | if (rinfo->type == MAX77620_REGULATOR_TYPE_SD) { | |
523 | ret = regmap_read(pmic->rmap, rinfo->cfg_addr, &val); | |
524 | if (ret < 0) { | |
525 | dev_err(pmic->dev, "Reg 0x%02x read failed: %d\n", | |
526 | rinfo->cfg_addr, ret); | |
527 | return ret; | |
528 | } | |
529 | fpwm = !!(val & MAX77620_SD_FPWM_MASK); | |
530 | } | |
531 | ||
532 | switch (pm_mode) { | |
533 | case MAX77620_POWER_MODE_NORMAL: | |
534 | case MAX77620_POWER_MODE_DISABLE: | |
535 | if (fpwm) | |
536 | reg_mode = REGULATOR_MODE_FAST; | |
537 | else | |
538 | reg_mode = REGULATOR_MODE_NORMAL; | |
539 | break; | |
540 | case MAX77620_POWER_MODE_LPM: | |
541 | case MAX77620_POWER_MODE_GLPM: | |
542 | reg_mode = REGULATOR_MODE_IDLE; | |
543 | break; | |
544 | default: | |
545 | return 0; | |
546 | } | |
547 | ||
548 | return reg_mode; | |
549 | } | |
550 | ||
551 | static int max77620_regulator_set_ramp_delay(struct regulator_dev *rdev, | |
552 | int ramp_delay) | |
553 | { | |
554 | struct max77620_regulator *pmic = rdev_get_drvdata(rdev); | |
555 | int id = rdev_get_id(rdev); | |
5aa43599 | 556 | struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id]; |
5b1c2028 | 557 | |
5aa43599 LD |
558 | /* Device specific ramp rate setting tells that platform has |
559 | * different ramp rate from advertised value. In this case, | |
560 | * do not configure anything and just return success. | |
561 | */ | |
562 | if (rpdata->ramp_rate_setting) | |
563 | return 0; | |
5b1c2028 | 564 | |
5aa43599 | 565 | return max77620_set_slew_rate(pmic, id, ramp_delay); |
5b1c2028 LD |
566 | } |
567 | ||
568 | static int max77620_of_parse_cb(struct device_node *np, | |
569 | const struct regulator_desc *desc, | |
570 | struct regulator_config *config) | |
571 | { | |
572 | struct max77620_regulator *pmic = config->driver_data; | |
573 | struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[desc->id]; | |
574 | u32 pval; | |
575 | int ret; | |
576 | ||
577 | ret = of_property_read_u32(np, "maxim,active-fps-source", &pval); | |
578 | rpdata->active_fps_src = (!ret) ? pval : MAX77620_FPS_SRC_DEF; | |
579 | ||
580 | ret = of_property_read_u32(np, "maxim,active-fps-power-up-slot", &pval); | |
581 | rpdata->active_fps_pu_slot = (!ret) ? pval : -1; | |
582 | ||
583 | ret = of_property_read_u32( | |
584 | np, "maxim,active-fps-power-down-slot", &pval); | |
585 | rpdata->active_fps_pd_slot = (!ret) ? pval : -1; | |
586 | ||
587 | ret = of_property_read_u32(np, "maxim,suspend-fps-source", &pval); | |
588 | rpdata->suspend_fps_src = (!ret) ? pval : -1; | |
589 | ||
590 | ret = of_property_read_u32( | |
591 | np, "maxim,suspend-fps-power-up-slot", &pval); | |
592 | rpdata->suspend_fps_pu_slot = (!ret) ? pval : -1; | |
593 | ||
594 | ret = of_property_read_u32( | |
595 | np, "maxim,suspend-fps-power-down-slot", &pval); | |
596 | rpdata->suspend_fps_pd_slot = (!ret) ? pval : -1; | |
597 | ||
5aa43599 LD |
598 | ret = of_property_read_u32(np, "maxim,ramp-rate-setting", &pval); |
599 | rpdata->ramp_rate_setting = (!ret) ? pval : 0; | |
600 | ||
5b1c2028 LD |
601 | return max77620_init_pmic(pmic, desc->id); |
602 | } | |
603 | ||
604 | static struct regulator_ops max77620_regulator_ops = { | |
605 | .is_enabled = max77620_regulator_is_enabled, | |
606 | .enable = max77620_regulator_enable, | |
607 | .disable = max77620_regulator_disable, | |
608 | .list_voltage = regulator_list_voltage_linear, | |
609 | .map_voltage = regulator_map_voltage_linear, | |
610 | .get_voltage_sel = regulator_get_voltage_sel_regmap, | |
611 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
612 | .set_mode = max77620_regulator_set_mode, | |
613 | .get_mode = max77620_regulator_get_mode, | |
614 | .set_ramp_delay = max77620_regulator_set_ramp_delay, | |
615 | .set_voltage_time_sel = regulator_set_voltage_time_sel, | |
51817f46 | 616 | .set_active_discharge = regulator_set_active_discharge_regmap, |
5b1c2028 LD |
617 | }; |
618 | ||
619 | #define MAX77620_SD_CNF2_ROVS_EN_NONE 0 | |
620 | #define RAIL_SD(_id, _name, _sname, _volt_mask, _min_uV, _max_uV, \ | |
621 | _step_uV, _rs_add, _rs_mask) \ | |
622 | [MAX77620_REGULATOR_ID_##_id] = { \ | |
623 | .type = MAX77620_REGULATOR_TYPE_SD, \ | |
5b1c2028 LD |
624 | .volt_addr = MAX77620_REG_##_id, \ |
625 | .cfg_addr = MAX77620_REG_##_id##_CFG, \ | |
626 | .fps_addr = MAX77620_REG_FPS_##_id, \ | |
627 | .remote_sense_addr = _rs_add, \ | |
628 | .remote_sense_mask = MAX77620_SD_CNF2_ROVS_EN_##_rs_mask, \ | |
5b1c2028 LD |
629 | .power_mode_mask = MAX77620_SD_POWER_MODE_MASK, \ |
630 | .power_mode_shift = MAX77620_SD_POWER_MODE_SHIFT, \ | |
631 | .desc = { \ | |
632 | .name = max77620_rails(_name), \ | |
633 | .of_match = of_match_ptr(#_name), \ | |
634 | .regulators_node = of_match_ptr("regulators"), \ | |
635 | .of_parse_cb = max77620_of_parse_cb, \ | |
636 | .supply_name = _sname, \ | |
637 | .id = MAX77620_REGULATOR_ID_##_id, \ | |
638 | .ops = &max77620_regulator_ops, \ | |
639 | .n_voltages = ((_max_uV - _min_uV) / _step_uV) + 1, \ | |
640 | .min_uV = _min_uV, \ | |
641 | .uV_step = _step_uV, \ | |
642 | .enable_time = 500, \ | |
643 | .vsel_mask = MAX77620_##_volt_mask##_VOLT_MASK, \ | |
644 | .vsel_reg = MAX77620_REG_##_id, \ | |
51817f46 LD |
645 | .active_discharge_off = 0, \ |
646 | .active_discharge_on = MAX77620_SD_CFG1_ADE_ENABLE, \ | |
647 | .active_discharge_mask = MAX77620_SD_CFG1_ADE_MASK, \ | |
648 | .active_discharge_reg = MAX77620_REG_##_id##_CFG, \ | |
5b1c2028 LD |
649 | .type = REGULATOR_VOLTAGE, \ |
650 | }, \ | |
651 | } | |
652 | ||
653 | #define RAIL_LDO(_id, _name, _sname, _type, _min_uV, _max_uV, _step_uV) \ | |
654 | [MAX77620_REGULATOR_ID_##_id] = { \ | |
655 | .type = MAX77620_REGULATOR_TYPE_LDO_##_type, \ | |
5b1c2028 LD |
656 | .volt_addr = MAX77620_REG_##_id##_CFG, \ |
657 | .cfg_addr = MAX77620_REG_##_id##_CFG2, \ | |
658 | .fps_addr = MAX77620_REG_FPS_##_id, \ | |
659 | .remote_sense_addr = 0xFF, \ | |
5b1c2028 LD |
660 | .power_mode_mask = MAX77620_LDO_POWER_MODE_MASK, \ |
661 | .power_mode_shift = MAX77620_LDO_POWER_MODE_SHIFT, \ | |
662 | .desc = { \ | |
663 | .name = max77620_rails(_name), \ | |
664 | .of_match = of_match_ptr(#_name), \ | |
665 | .regulators_node = of_match_ptr("regulators"), \ | |
666 | .of_parse_cb = max77620_of_parse_cb, \ | |
667 | .supply_name = _sname, \ | |
668 | .id = MAX77620_REGULATOR_ID_##_id, \ | |
669 | .ops = &max77620_regulator_ops, \ | |
670 | .n_voltages = ((_max_uV - _min_uV) / _step_uV) + 1, \ | |
671 | .min_uV = _min_uV, \ | |
672 | .uV_step = _step_uV, \ | |
673 | .enable_time = 500, \ | |
674 | .vsel_mask = MAX77620_LDO_VOLT_MASK, \ | |
675 | .vsel_reg = MAX77620_REG_##_id##_CFG, \ | |
51817f46 LD |
676 | .active_discharge_off = 0, \ |
677 | .active_discharge_on = MAX77620_LDO_CFG2_ADE_ENABLE, \ | |
678 | .active_discharge_mask = MAX77620_LDO_CFG2_ADE_MASK, \ | |
679 | .active_discharge_reg = MAX77620_REG_##_id##_CFG2, \ | |
5b1c2028 LD |
680 | .type = REGULATOR_VOLTAGE, \ |
681 | }, \ | |
682 | } | |
683 | ||
684 | static struct max77620_regulator_info max77620_regs_info[MAX77620_NUM_REGS] = { | |
685 | RAIL_SD(SD0, sd0, "in-sd0", SD0, 600000, 1400000, 12500, 0x22, SD0), | |
686 | RAIL_SD(SD1, sd1, "in-sd1", SD1, 600000, 1550000, 12500, 0x22, SD1), | |
687 | RAIL_SD(SD2, sd2, "in-sd2", SDX, 600000, 3787500, 12500, 0xFF, NONE), | |
688 | RAIL_SD(SD3, sd3, "in-sd3", SDX, 600000, 3787500, 12500, 0xFF, NONE), | |
5b1c2028 LD |
689 | |
690 | RAIL_LDO(LDO0, ldo0, "in-ldo0-1", N, 800000, 2375000, 25000), | |
691 | RAIL_LDO(LDO1, ldo1, "in-ldo0-1", N, 800000, 2375000, 25000), | |
692 | RAIL_LDO(LDO2, ldo2, "in-ldo2", P, 800000, 3950000, 50000), | |
693 | RAIL_LDO(LDO3, ldo3, "in-ldo3-5", P, 800000, 3950000, 50000), | |
694 | RAIL_LDO(LDO4, ldo4, "in-ldo4-6", P, 800000, 1587500, 12500), | |
695 | RAIL_LDO(LDO5, ldo5, "in-ldo3-5", P, 800000, 3950000, 50000), | |
696 | RAIL_LDO(LDO6, ldo6, "in-ldo4-6", P, 800000, 3950000, 50000), | |
697 | RAIL_LDO(LDO7, ldo7, "in-ldo7-8", N, 800000, 3950000, 50000), | |
698 | RAIL_LDO(LDO8, ldo8, "in-ldo7-8", N, 800000, 3950000, 50000), | |
699 | }; | |
700 | ||
701 | static struct max77620_regulator_info max20024_regs_info[MAX77620_NUM_REGS] = { | |
702 | RAIL_SD(SD0, sd0, "in-sd0", SD0, 800000, 1587500, 12500, 0x22, SD0), | |
703 | RAIL_SD(SD1, sd1, "in-sd1", SD1, 600000, 3387500, 12500, 0x22, SD1), | |
704 | RAIL_SD(SD2, sd2, "in-sd2", SDX, 600000, 3787500, 12500, 0xFF, NONE), | |
705 | RAIL_SD(SD3, sd3, "in-sd3", SDX, 600000, 3787500, 12500, 0xFF, NONE), | |
706 | RAIL_SD(SD4, sd4, "in-sd4", SDX, 600000, 3787500, 12500, 0xFF, NONE), | |
707 | ||
708 | RAIL_LDO(LDO0, ldo0, "in-ldo0-1", N, 800000, 2375000, 25000), | |
709 | RAIL_LDO(LDO1, ldo1, "in-ldo0-1", N, 800000, 2375000, 25000), | |
710 | RAIL_LDO(LDO2, ldo2, "in-ldo2", P, 800000, 3950000, 50000), | |
711 | RAIL_LDO(LDO3, ldo3, "in-ldo3-5", P, 800000, 3950000, 50000), | |
712 | RAIL_LDO(LDO4, ldo4, "in-ldo4-6", P, 800000, 1587500, 12500), | |
713 | RAIL_LDO(LDO5, ldo5, "in-ldo3-5", P, 800000, 3950000, 50000), | |
714 | RAIL_LDO(LDO6, ldo6, "in-ldo4-6", P, 800000, 3950000, 50000), | |
715 | RAIL_LDO(LDO7, ldo7, "in-ldo7-8", N, 800000, 3950000, 50000), | |
716 | RAIL_LDO(LDO8, ldo8, "in-ldo7-8", N, 800000, 3950000, 50000), | |
717 | }; | |
718 | ||
719 | static int max77620_regulator_probe(struct platform_device *pdev) | |
720 | { | |
721 | struct max77620_chip *max77620_chip = dev_get_drvdata(pdev->dev.parent); | |
722 | struct max77620_regulator_info *rinfo; | |
723 | struct device *dev = &pdev->dev; | |
724 | struct regulator_config config = { }; | |
725 | struct max77620_regulator *pmic; | |
726 | int ret = 0; | |
727 | int id; | |
728 | ||
729 | pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL); | |
730 | if (!pmic) | |
731 | return -ENOMEM; | |
732 | ||
733 | platform_set_drvdata(pdev, pmic); | |
734 | pmic->dev = dev; | |
735 | pmic->rmap = max77620_chip->rmap; | |
736 | if (!dev->of_node) | |
737 | dev->of_node = pdev->dev.parent->of_node; | |
738 | ||
739 | switch (max77620_chip->chip_id) { | |
740 | case MAX77620: | |
741 | rinfo = max77620_regs_info; | |
742 | break; | |
743 | default: | |
744 | rinfo = max20024_regs_info; | |
745 | break; | |
746 | } | |
747 | ||
748 | config.regmap = pmic->rmap; | |
749 | config.dev = dev; | |
750 | config.driver_data = pmic; | |
751 | ||
752 | for (id = 0; id < MAX77620_NUM_REGS; id++) { | |
753 | struct regulator_dev *rdev; | |
754 | struct regulator_desc *rdesc; | |
755 | ||
756 | if ((max77620_chip->chip_id == MAX77620) && | |
757 | (id == MAX77620_REGULATOR_ID_SD4)) | |
758 | continue; | |
759 | ||
760 | rdesc = &rinfo[id].desc; | |
761 | pmic->rinfo[id] = &max77620_regs_info[id]; | |
762 | pmic->enable_power_mode[id] = MAX77620_POWER_MODE_NORMAL; | |
5b1c2028 LD |
763 | |
764 | ret = max77620_read_slew_rate(pmic, id); | |
765 | if (ret < 0) | |
766 | return ret; | |
767 | ||
768 | rdev = devm_regulator_register(dev, rdesc, &config); | |
769 | if (IS_ERR(rdev)) { | |
770 | ret = PTR_ERR(rdev); | |
771 | dev_err(dev, "Regulator registration %s failed: %d\n", | |
772 | rdesc->name, ret); | |
773 | return ret; | |
774 | } | |
775 | } | |
776 | ||
777 | return 0; | |
778 | } | |
779 | ||
780 | #ifdef CONFIG_PM_SLEEP | |
781 | static int max77620_regulator_suspend(struct device *dev) | |
782 | { | |
783 | struct max77620_regulator *pmic = dev_get_drvdata(dev); | |
784 | struct max77620_regulator_pdata *reg_pdata; | |
785 | int id; | |
786 | ||
787 | for (id = 0; id < MAX77620_NUM_REGS; id++) { | |
788 | reg_pdata = &pmic->reg_pdata[id]; | |
789 | ||
790 | max77620_regulator_set_fps_slots(pmic, id, true); | |
791 | if (reg_pdata->suspend_fps_src < 0) | |
792 | continue; | |
793 | ||
794 | max77620_regulator_set_fps_src(pmic, reg_pdata->suspend_fps_src, | |
795 | id); | |
796 | } | |
797 | ||
798 | return 0; | |
799 | } | |
800 | ||
801 | static int max77620_regulator_resume(struct device *dev) | |
802 | { | |
803 | struct max77620_regulator *pmic = dev_get_drvdata(dev); | |
804 | struct max77620_regulator_pdata *reg_pdata; | |
805 | int id; | |
806 | ||
807 | for (id = 0; id < MAX77620_NUM_REGS; id++) { | |
808 | reg_pdata = &pmic->reg_pdata[id]; | |
809 | ||
810 | max77620_regulator_set_fps_slots(pmic, id, false); | |
811 | if (reg_pdata->active_fps_src < 0) | |
812 | continue; | |
813 | max77620_regulator_set_fps_src(pmic, reg_pdata->active_fps_src, | |
814 | id); | |
815 | } | |
816 | ||
817 | return 0; | |
818 | } | |
819 | #endif | |
820 | ||
821 | static const struct dev_pm_ops max77620_regulator_pm_ops = { | |
822 | SET_SYSTEM_SLEEP_PM_OPS(max77620_regulator_suspend, | |
823 | max77620_regulator_resume) | |
824 | }; | |
825 | ||
826 | static const struct platform_device_id max77620_regulator_devtype[] = { | |
827 | { .name = "max77620-pmic", }, | |
828 | { .name = "max20024-pmic", }, | |
829 | {}, | |
830 | }; | |
831 | MODULE_DEVICE_TABLE(platform, max77620_regulator_devtype); | |
832 | ||
833 | static struct platform_driver max77620_regulator_driver = { | |
834 | .probe = max77620_regulator_probe, | |
835 | .id_table = max77620_regulator_devtype, | |
836 | .driver = { | |
837 | .name = "max77620-pmic", | |
838 | .pm = &max77620_regulator_pm_ops, | |
839 | }, | |
840 | }; | |
841 | ||
842 | module_platform_driver(max77620_regulator_driver); | |
843 | ||
844 | MODULE_DESCRIPTION("MAX77620/MAX20024 regulator driver"); | |
845 | MODULE_AUTHOR("Mallikarjun Kasoju <mkasoju@nvidia.com>"); | |
846 | MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>"); | |
5b1c2028 | 847 | MODULE_LICENSE("GPL v2"); |