[deliverable/linux.git] / drivers / regulator / mc13783-regulator.c

/*
 * Regulator Driver for Freescale MC13783 PMIC
 *
 * Copyright 2010 Yong Shen <yong.shen@linaro.org>
 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
 * Copyright 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/mfd/mc13783.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/driver.h>
#include <linux/platform_device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/err.h>
#include "mc13xxx.h"

#define MC13783_REG_SWITCHERS5			29
#define MC13783_REG_SWITCHERS5_SW3EN			(1 << 20)
#define MC13783_REG_SWITCHERS5_SW3VSEL			18
#define MC13783_REG_SWITCHERS5_SW3VSEL_M		(3 << 18)

#define MC13783_REG_REGULATORSETTING0		30
#define MC13783_REG_REGULATORSETTING0_VIOLOVSEL		2
#define MC13783_REG_REGULATORSETTING0_VDIGVSEL		4
#define MC13783_REG_REGULATORSETTING0_VGENVSEL		6
#define MC13783_REG_REGULATORSETTING0_VRFDIGVSEL	9
#define MC13783_REG_REGULATORSETTING0_VRFREFVSEL	11
#define MC13783_REG_REGULATORSETTING0_VRFCPVSEL		13
#define MC13783_REG_REGULATORSETTING0_VSIMVSEL		14
#define MC13783_REG_REGULATORSETTING0_VESIMVSEL		15
#define MC13783_REG_REGULATORSETTING0_VCAMVSEL		16

#define MC13783_REG_REGULATORSETTING0_VIOLOVSEL_M	(3 << 2)
#define MC13783_REG_REGULATORSETTING0_VDIGVSEL_M	(3 << 4)
#define MC13783_REG_REGULATORSETTING0_VGENVSEL_M	(7 << 6)
#define MC13783_REG_REGULATORSETTING0_VRFDIGVSEL_M	(3 << 9)
#define MC13783_REG_REGULATORSETTING0_VRFREFVSEL_M	(3 << 11)
#define MC13783_REG_REGULATORSETTING0_VRFCPVSEL_M	(1 << 13)
#define MC13783_REG_REGULATORSETTING0_VSIMVSEL_M	(1 << 14)
#define MC13783_REG_REGULATORSETTING0_VESIMVSEL_M	(1 << 15)
#define MC13783_REG_REGULATORSETTING0_VCAMVSEL_M	(7 << 16)

#define MC13783_REG_REGULATORSETTING1		31
#define MC13783_REG_REGULATORSETTING1_VVIBVSEL		0
#define MC13783_REG_REGULATORSETTING1_VRF1VSEL		2
#define MC13783_REG_REGULATORSETTING1_VRF2VSEL		4
#define MC13783_REG_REGULATORSETTING1_VMMC1VSEL		6
#define MC13783_REG_REGULATORSETTING1_VMMC2VSEL		9

#define MC13783_REG_REGULATORSETTING1_VVIBVSEL_M	(3 << 0)
#define MC13783_REG_REGULATORSETTING1_VRF1VSEL_M	(3 << 2)
#define MC13783_REG_REGULATORSETTING1_VRF2VSEL_M	(3 << 4)
#define MC13783_REG_REGULATORSETTING1_VMMC1VSEL_M	(7 << 6)
#define MC13783_REG_REGULATORSETTING1_VMMC2VSEL_M	(7 << 9)

#define MC13783_REG_REGULATORMODE0		32
#define MC13783_REG_REGULATORMODE0_VAUDIOEN		(1 << 0)
#define MC13783_REG_REGULATORMODE0_VIOHIEN		(1 << 3)
#define MC13783_REG_REGULATORMODE0_VIOLOEN		(1 << 6)
#define MC13783_REG_REGULATORMODE0_VDIGEN		(1 << 9)
#define MC13783_REG_REGULATORMODE0_VGENEN		(1 << 12)
#define MC13783_REG_REGULATORMODE0_VRFDIGEN		(1 << 15)
#define MC13783_REG_REGULATORMODE0_VRFREFEN		(1 << 18)
#define MC13783_REG_REGULATORMODE0_VRFCPEN		(1 << 21)

#define MC13783_REG_REGULATORMODE1		33
#define MC13783_REG_REGULATORMODE1_VSIMEN		(1 << 0)
#define MC13783_REG_REGULATORMODE1_VESIMEN		(1 << 3)
#define MC13783_REG_REGULATORMODE1_VCAMEN		(1 << 6)
#define MC13783_REG_REGULATORMODE1_VRFBGEN		(1 << 9)
#define MC13783_REG_REGULATORMODE1_VVIBEN		(1 << 11)
#define MC13783_REG_REGULATORMODE1_VRF1EN		(1 << 12)
#define MC13783_REG_REGULATORMODE1_VRF2EN		(1 << 15)
#define MC13783_REG_REGULATORMODE1_VMMC1EN		(1 << 18)
#define MC13783_REG_REGULATORMODE1_VMMC2EN		(1 << 21)

#define MC13783_REG_POWERMISC			34
#define MC13783_REG_POWERMISC_GPO1EN			(1 << 6)
#define MC13783_REG_POWERMISC_GPO2EN			(1 << 8)
#define MC13783_REG_POWERMISC_GPO3EN			(1 << 10)
#define MC13783_REG_POWERMISC_GPO4EN			(1 << 12)
#define MC13783_REG_POWERMISC_PWGT1SPIEN		(1 << 15)
#define MC13783_REG_POWERMISC_PWGT2SPIEN		(1 << 16)

#define MC13783_REG_POWERMISC_PWGTSPI_M			(3 << 15)


/* Voltage Values */
static const int mc13783_sw3_val[] = {
	5000000, 5000000, 5000000, 5500000,
};

static const int mc13783_vaudio_val[] = {
	2775000,
};

static const int mc13783_viohi_val[] = {
	2775000,
};

static const int mc13783_violo_val[] = {
	1200000, 1300000, 1500000, 1800000,
};

static const int mc13783_vdig_val[] = {
	1200000, 1300000, 1500000, 1800000,
};

static const int mc13783_vgen_val[] = {
	1200000, 1300000, 1500000, 1800000,
	1100000, 2000000, 2775000, 2400000,
};

static const int mc13783_vrfdig_val[] = {
	1200000, 1500000, 1800000, 1875000,
};

static const int mc13783_vrfref_val[] = {
	2475000, 2600000, 2700000, 2775000,
};

static const int mc13783_vrfcp_val[] = {
	2700000, 2775000,
};

static const int mc13783_vsim_val[] = {
	1800000, 2900000, 3000000,
};

static const int mc13783_vesim_val[] = {
	1800000, 2900000,
};

static const int mc13783_vcam_val[] = {
	1500000, 1800000, 2500000, 2550000,
	2600000, 2750000, 2800000, 3000000,
};

static const int mc13783_vrfbg_val[] = {
	1250000,
};

static const int mc13783_vvib_val[] = {
	1300000, 1800000, 2000000, 3000000,
};

static const int mc13783_vmmc_val[] = {
	1600000, 1800000, 2000000, 2600000,
	2700000, 2800000, 2900000, 3000000,
};

static const int mc13783_vrf_val[] = {
	1500000, 1875000, 2700000, 2775000,
};

static const int mc13783_gpo_val[] = {
	3100000,
};

static const int mc13783_pwgtdrv_val[] = {
	5500000,
};

static struct regulator_ops mc13783_gpo_regulator_ops;

#define MC13783_DEFINE(prefix, name, reg, vsel_reg, voltages)	\
	MC13xxx_DEFINE(MC13783_REG_, name, reg, vsel_reg, voltages, \
			mc13xxx_regulator_ops)

#define MC13783_FIXED_DEFINE(prefix, name, reg, voltages)		\
	MC13xxx_FIXED_DEFINE(MC13783_REG_, name, reg, voltages, \
			mc13xxx_fixed_regulator_ops)

#define MC13783_GPO_DEFINE(prefix, name, reg, voltages)		\
	MC13xxx_GPO_DEFINE(MC13783_REG_, name, reg, voltages, \
			mc13783_gpo_regulator_ops)

#define MC13783_DEFINE_SW(_name, _reg, _vsel_reg, _voltages)		\
	MC13783_DEFINE(REG, _name, _reg, _vsel_reg, _voltages)
#define MC13783_DEFINE_REGU(_name, _reg, _vsel_reg, _voltages)		\
	MC13783_DEFINE(REG, _name, _reg, _vsel_reg, _voltages)

static struct mc13xxx_regulator mc13783_regulators[] = {
	MC13783_DEFINE_SW(SW3, SWITCHERS5, SWITCHERS5, mc13783_sw3_val),

	MC13783_FIXED_DEFINE(REG, VAUDIO, REGULATORMODE0, mc13783_vaudio_val),
	MC13783_FIXED_DEFINE(REG, VIOHI, REGULATORMODE0, mc13783_viohi_val),
	MC13783_DEFINE_REGU(VIOLO, REGULATORMODE0, REGULATORSETTING0,	\
			    mc13783_violo_val),
	MC13783_DEFINE_REGU(VDIG, REGULATORMODE0, REGULATORSETTING0,	\
			    mc13783_vdig_val),
	MC13783_DEFINE_REGU(VGEN, REGULATORMODE0, REGULATORSETTING0,	\
			    mc13783_vgen_val),
	MC13783_DEFINE_REGU(VRFDIG, REGULATORMODE0, REGULATORSETTING0,	\
			    mc13783_vrfdig_val),
	MC13783_DEFINE_REGU(VRFREF, REGULATORMODE0, REGULATORSETTING0,	\
			    mc13783_vrfref_val),
	MC13783_DEFINE_REGU(VRFCP, REGULATORMODE0, REGULATORSETTING0,	\
			    mc13783_vrfcp_val),
	MC13783_DEFINE_REGU(VSIM, REGULATORMODE1, REGULATORSETTING0,	\
			    mc13783_vsim_val),
	MC13783_DEFINE_REGU(VESIM, REGULATORMODE1, REGULATORSETTING0,	\
			    mc13783_vesim_val),
	MC13783_DEFINE_REGU(VCAM, REGULATORMODE1, REGULATORSETTING0,	\
			    mc13783_vcam_val),
	MC13783_FIXED_DEFINE(REG, VRFBG, REGULATORMODE1, mc13783_vrfbg_val),
	MC13783_DEFINE_REGU(VVIB, REGULATORMODE1, REGULATORSETTING1,	\
			    mc13783_vvib_val),
	MC13783_DEFINE_REGU(VRF1, REGULATORMODE1, REGULATORSETTING1,	\
			    mc13783_vrf_val),
	MC13783_DEFINE_REGU(VRF2, REGULATORMODE1, REGULATORSETTING1,	\
			    mc13783_vrf_val),
	MC13783_DEFINE_REGU(VMMC1, REGULATORMODE1, REGULATORSETTING1,	\
			    mc13783_vmmc_val),
	MC13783_DEFINE_REGU(VMMC2, REGULATORMODE1, REGULATORSETTING1,	\
			    mc13783_vmmc_val),
	MC13783_GPO_DEFINE(REG, GPO1, POWERMISC, mc13783_gpo_val),
	MC13783_GPO_DEFINE(REG, GPO2, POWERMISC, mc13783_gpo_val),
	MC13783_GPO_DEFINE(REG, GPO3, POWERMISC, mc13783_gpo_val),
	MC13783_GPO_DEFINE(REG, GPO4, POWERMISC, mc13783_gpo_val),
	MC13783_GPO_DEFINE(REG, PWGT1SPI, POWERMISC, mc13783_pwgtdrv_val),
	MC13783_GPO_DEFINE(REG, PWGT2SPI, POWERMISC, mc13783_pwgtdrv_val),
};

static int mc13783_powermisc_rmw(struct mc13xxx_regulator_priv *priv, u32 mask,
		u32 val)
{
	struct mc13xxx *mc13783 = priv->mc13xxx;
	int ret;
	u32 valread;

	BUG_ON(val & ~mask);

	ret = mc13xxx_reg_read(mc13783, MC13783_REG_POWERMISC, &valread);
	if (ret)
		return ret;

	/* Update the stored state for Power Gates. */
	priv->powermisc_pwgt_state =
				(priv->powermisc_pwgt_state & ~mask) | val;
	priv->powermisc_pwgt_state &= MC13783_REG_POWERMISC_PWGTSPI_M;

	/* Construct the new register value */
	valread = (valread & ~mask) | val;
	/* Overwrite the PWGTxEN with the stored version */
	valread = (valread & ~MC13783_REG_POWERMISC_PWGTSPI_M) |
						priv->powermisc_pwgt_state;

	return mc13xxx_reg_write(mc13783, MC13783_REG_POWERMISC, valread);
}

static int mc13783_gpo_regulator_enable(struct regulator_dev *rdev)
{
	struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
	struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
	int id = rdev_get_id(rdev);
	int ret;
	u32 en_val = mc13xxx_regulators[id].enable_bit;

	dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);

	/* Power Gate enable value is 0 */
	if (id == MC13783_REG_PWGT1SPI ||
	    id == MC13783_REG_PWGT2SPI)
		en_val = 0;

	mc13xxx_lock(priv->mc13xxx);
	ret = mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit,
					en_val);
	mc13xxx_unlock(priv->mc13xxx);

	return ret;
}

static int mc13783_gpo_regulator_disable(struct regulator_dev *rdev)
{
	struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
	struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
	int id = rdev_get_id(rdev);
	int ret;
	u32 dis_val = 0;

	dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);

	/* Power Gate disable value is 1 */
	if (id == MC13783_REG_PWGT1SPI ||
	    id == MC13783_REG_PWGT2SPI)
		dis_val = mc13xxx_regulators[id].enable_bit;

	mc13xxx_lock(priv->mc13xxx);
	ret = mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit,
					dis_val);
	mc13xxx_unlock(priv->mc13xxx);

	return ret;
}

static int mc13783_gpo_regulator_is_enabled(struct regulator_dev *rdev)
{
	struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
	struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
	int ret, id = rdev_get_id(rdev);
	unsigned int val;

	mc13xxx_lock(priv->mc13xxx);
	ret = mc13xxx_reg_read(priv->mc13xxx, mc13xxx_regulators[id].reg, &val);
	mc13xxx_unlock(priv->mc13xxx);

	if (ret)
		return ret;

	/* Power Gates state is stored in powermisc_pwgt_state
	 * where the meaning of bits is negated */
	val = (val & ~MC13783_REG_POWERMISC_PWGTSPI_M) |
	      (priv->powermisc_pwgt_state ^ MC13783_REG_POWERMISC_PWGTSPI_M);

	return (val & mc13xxx_regulators[id].enable_bit) != 0;
}

static struct regulator_ops mc13783_gpo_regulator_ops = {
	.enable = mc13783_gpo_regulator_enable,
	.disable = mc13783_gpo_regulator_disable,
	.is_enabled = mc13783_gpo_regulator_is_enabled,
	.list_voltage = mc13xxx_regulator_list_voltage,
	.set_voltage = mc13xxx_fixed_regulator_set_voltage,
	.get_voltage = mc13xxx_fixed_regulator_get_voltage,
};

static int __devinit mc13783_regulator_probe(struct platform_device *pdev)
{
	struct mc13xxx_regulator_priv *priv;
	struct mc13xxx *mc13783 = dev_get_drvdata(pdev->dev.parent);
	struct mc13783_regulator_platform_data *pdata =
		dev_get_platdata(&pdev->dev);
	struct mc13783_regulator_init_data *init_data;
	int i, ret;

	dev_dbg(&pdev->dev, "%s id %d\n", __func__, pdev->id);

	priv = kzalloc(sizeof(*priv) +
			pdata->num_regulators * sizeof(priv->regulators[0]),
			GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->mc13xxx_regulators = mc13783_regulators;
	priv->mc13xxx = mc13783;

	for (i = 0; i < pdata->num_regulators; i++) {
		init_data = &pdata->regulators[i];
		priv->regulators[i] = regulator_register(
				&mc13783_regulators[init_data->id].desc,
				&pdev->dev, init_data->init_data, priv);

		if (IS_ERR(priv->regulators[i])) {
			dev_err(&pdev->dev, "failed to register regulator %s\n",
				mc13783_regulators[i].desc.name);
			ret = PTR_ERR(priv->regulators[i]);
			goto err;
		}
	}

	platform_set_drvdata(pdev, priv);

	return 0;
err:
	while (--i >= 0)
		regulator_unregister(priv->regulators[i]);

	kfree(priv);

	return ret;
}

static int __devexit mc13783_regulator_remove(struct platform_device *pdev)
{
	struct mc13xxx_regulator_priv *priv = platform_get_drvdata(pdev);
	struct mc13783_regulator_platform_data *pdata =
		dev_get_platdata(&pdev->dev);
	int i;

	platform_set_drvdata(pdev, NULL);

	for (i = 0; i < pdata->num_regulators; i++)
		regulator_unregister(priv->regulators[i]);

	kfree(priv);
	return 0;
}

static struct platform_driver mc13783_regulator_driver = {
	.driver	= {
		.name	= "mc13783-regulator",
		.owner	= THIS_MODULE,
	},
	.remove		= __devexit_p(mc13783_regulator_remove),
	.probe		= mc13783_regulator_probe,
};

static int __init mc13783_regulator_init(void)
{
	return platform_driver_register(&mc13783_regulator_driver);
}
subsys_initcall(mc13783_regulator_init);

static void __exit mc13783_regulator_exit(void)
{
	platform_driver_unregister(&mc13783_regulator_driver);
}
module_exit(mc13783_regulator_exit);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
MODULE_DESCRIPTION("Regulator Driver for Freescale MC13783 PMIC");
MODULE_ALIAS("platform:mc13783-regulator");
Commit	Line	Data
295c08bc SH	1	/*
	2	* Regulator Driver for Freescale MC13783 PMIC
	3	*
167e3d8a	4	* Copyright 2010 Yong Shen <yong.shen@linaro.org>
295c08bc	5	* Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
1bd588fd	6	* Copyright 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
295c08bc SH	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
a10099bc	13	#include <linux/mfd/mc13783.h>
295c08bc SH	14	#include <linux/regulator/machine.h>
	15	#include <linux/regulator/driver.h>
	16	#include <linux/platform_device.h>
295c08bc	17	#include <linux/kernel.h>
5a0e3ad6	18	#include <linux/slab.h>
295c08bc SH	19	#include <linux/init.h>
295c08bc SH	20	#include <linux/err.h>
167e3d8a	21	#include "mc13xxx.h"
295c08bc	22
a10099bc UKK	23	#define MC13783_REG_SWITCHERS5 29
a10099bc UKK	24	#define MC13783_REG_SWITCHERS5_SW3EN (1 << 20)
1bd588fd AP	25	#define MC13783_REG_SWITCHERS5_SW3VSEL 18
	26	#define MC13783_REG_SWITCHERS5_SW3VSEL_M (3 << 18)
	27
	28	#define MC13783_REG_REGULATORSETTING0 30
	29	#define MC13783_REG_REGULATORSETTING0_VIOLOVSEL 2
	30	#define MC13783_REG_REGULATORSETTING0_VDIGVSEL 4
	31	#define MC13783_REG_REGULATORSETTING0_VGENVSEL 6
	32	#define MC13783_REG_REGULATORSETTING0_VRFDIGVSEL 9
	33	#define MC13783_REG_REGULATORSETTING0_VRFREFVSEL 11
	34	#define MC13783_REG_REGULATORSETTING0_VRFCPVSEL 13
	35	#define MC13783_REG_REGULATORSETTING0_VSIMVSEL 14
	36	#define MC13783_REG_REGULATORSETTING0_VESIMVSEL 15
	37	#define MC13783_REG_REGULATORSETTING0_VCAMVSEL 16
	38
	39	#define MC13783_REG_REGULATORSETTING0_VIOLOVSEL_M (3 << 2)
	40	#define MC13783_REG_REGULATORSETTING0_VDIGVSEL_M (3 << 4)
	41	#define MC13783_REG_REGULATORSETTING0_VGENVSEL_M (7 << 6)
	42	#define MC13783_REG_REGULATORSETTING0_VRFDIGVSEL_M (3 << 9)
	43	#define MC13783_REG_REGULATORSETTING0_VRFREFVSEL_M (3 << 11)
	44	#define MC13783_REG_REGULATORSETTING0_VRFCPVSEL_M (1 << 13)
	45	#define MC13783_REG_REGULATORSETTING0_VSIMVSEL_M (1 << 14)
	46	#define MC13783_REG_REGULATORSETTING0_VESIMVSEL_M (1 << 15)
	47	#define MC13783_REG_REGULATORSETTING0_VCAMVSEL_M (7 << 16)
	48
	49	#define MC13783_REG_REGULATORSETTING1 31
	50	#define MC13783_REG_REGULATORSETTING1_VVIBVSEL 0
	51	#define MC13783_REG_REGULATORSETTING1_VRF1VSEL 2
	52	#define MC13783_REG_REGULATORSETTING1_VRF2VSEL 4
	53	#define MC13783_REG_REGULATORSETTING1_VMMC1VSEL 6
	54	#define MC13783_REG_REGULATORSETTING1_VMMC2VSEL 9
	55
	56	#define MC13783_REG_REGULATORSETTING1_VVIBVSEL_M (3 << 0)
	57	#define MC13783_REG_REGULATORSETTING1_VRF1VSEL_M (3 << 2)
	58	#define MC13783_REG_REGULATORSETTING1_VRF2VSEL_M (3 << 4)
	59	#define MC13783_REG_REGULATORSETTING1_VMMC1VSEL_M (7 << 6)
	60	#define MC13783_REG_REGULATORSETTING1_VMMC2VSEL_M (7 << 9)
a10099bc UKK	61
	62	#define MC13783_REG_REGULATORMODE0 32
	63	#define MC13783_REG_REGULATORMODE0_VAUDIOEN (1 << 0)
	64	#define MC13783_REG_REGULATORMODE0_VIOHIEN (1 << 3)
	65	#define MC13783_REG_REGULATORMODE0_VIOLOEN (1 << 6)
	66	#define MC13783_REG_REGULATORMODE0_VDIGEN (1 << 9)
	67	#define MC13783_REG_REGULATORMODE0_VGENEN (1 << 12)
	68	#define MC13783_REG_REGULATORMODE0_VRFDIGEN (1 << 15)
	69	#define MC13783_REG_REGULATORMODE0_VRFREFEN (1 << 18)
	70	#define MC13783_REG_REGULATORMODE0_VRFCPEN (1 << 21)
	71
	72	#define MC13783_REG_REGULATORMODE1 33
	73	#define MC13783_REG_REGULATORMODE1_VSIMEN (1 << 0)
	74	#define MC13783_REG_REGULATORMODE1_VESIMEN (1 << 3)
	75	#define MC13783_REG_REGULATORMODE1_VCAMEN (1 << 6)
	76	#define MC13783_REG_REGULATORMODE1_VRFBGEN (1 << 9)
	77	#define MC13783_REG_REGULATORMODE1_VVIBEN (1 << 11)
	78	#define MC13783_REG_REGULATORMODE1_VRF1EN (1 << 12)
	79	#define MC13783_REG_REGULATORMODE1_VRF2EN (1 << 15)
	80	#define MC13783_REG_REGULATORMODE1_VMMC1EN (1 << 18)
	81	#define MC13783_REG_REGULATORMODE1_VMMC2EN (1 << 21)
	82
	83	#define MC13783_REG_POWERMISC 34
	84	#define MC13783_REG_POWERMISC_GPO1EN (1 << 6)
	85	#define MC13783_REG_POWERMISC_GPO2EN (1 << 8)
	86	#define MC13783_REG_POWERMISC_GPO3EN (1 << 10)
	87	#define MC13783_REG_POWERMISC_GPO4EN (1 << 12)
f4b97b36 AP	88	#define MC13783_REG_POWERMISC_PWGT1SPIEN (1 << 15)
	89	#define MC13783_REG_POWERMISC_PWGT2SPIEN (1 << 16)
	90
	91	#define MC13783_REG_POWERMISC_PWGTSPI_M (3 << 15)
	92
a10099bc	93
1bd588fd	94	/* Voltage Values */
6220b87b	95	static const int mc13783_sw3_val[] = {
1bd588fd AP	96	5000000, 5000000, 5000000, 5500000,
	97	};
	98
6220b87b	99	static const int mc13783_vaudio_val[] = {
1bd588fd AP	100	2775000,
	101	};
	102
6220b87b	103	static const int mc13783_viohi_val[] = {
1bd588fd AP	104	2775000,
	105	};
	106
6220b87b	107	static const int mc13783_violo_val[] = {
1bd588fd AP	108	1200000, 1300000, 1500000, 1800000,
	109	};
	110
6220b87b	111	static const int mc13783_vdig_val[] = {
1bd588fd AP	112	1200000, 1300000, 1500000, 1800000,
	113	};
	114
6220b87b	115	static const int mc13783_vgen_val[] = {
1bd588fd AP	116	1200000, 1300000, 1500000, 1800000,
	117	1100000, 2000000, 2775000, 2400000,
	118	};
	119
6220b87b	120	static const int mc13783_vrfdig_val[] = {
1bd588fd AP	121	1200000, 1500000, 1800000, 1875000,
	122	};
	123
6220b87b	124	static const int mc13783_vrfref_val[] = {
1bd588fd AP	125	2475000, 2600000, 2700000, 2775000,
	126	};
	127
6220b87b	128	static const int mc13783_vrfcp_val[] = {
1bd588fd AP	129	2700000, 2775000,
	130	};
	131
6220b87b	132	static const int mc13783_vsim_val[] = {
1bd588fd AP	133	1800000, 2900000, 3000000,
	134	};
	135
6220b87b	136	static const int mc13783_vesim_val[] = {
1bd588fd AP	137	1800000, 2900000,
	138	};
	139
6220b87b	140	static const int mc13783_vcam_val[] = {
1bd588fd AP	141	1500000, 1800000, 2500000, 2550000,
	142	2600000, 2750000, 2800000, 3000000,
	143	};
	144
6220b87b	145	static const int mc13783_vrfbg_val[] = {
1bd588fd AP	146	1250000,
	147	};
	148
6220b87b	149	static const int mc13783_vvib_val[] = {
1bd588fd AP	150	1300000, 1800000, 2000000, 3000000,
	151	};
	152
6220b87b	153	static const int mc13783_vmmc_val[] = {
1bd588fd AP	154	1600000, 1800000, 2000000, 2600000,
	155	2700000, 2800000, 2900000, 3000000,
	156	};
	157
6220b87b	158	static const int mc13783_vrf_val[] = {
1bd588fd	159	1500000, 1875000, 2700000, 2775000,
295c08bc SH	160	};
295c08bc SH	161
6220b87b	162	static const int mc13783_gpo_val[] = {
f4b97b36 AP	163	3100000,
	164	};
	165
6220b87b	166	static const int mc13783_pwgtdrv_val[] = {
f4b97b36 AP	167	5500000,
	168	};
	169
f4b97b36	170	static struct regulator_ops mc13783_gpo_regulator_ops;
1bd588fd	171
167e3d8a YS	172	#define MC13783_DEFINE(prefix, name, reg, vsel_reg, voltages) \
	173	MC13xxx_DEFINE(MC13783_REG_, name, reg, vsel_reg, voltages, \
	174	mc13xxx_regulator_ops)
295c08bc	175
167e3d8a YS	176	#define MC13783_FIXED_DEFINE(prefix, name, reg, voltages) \
	177	MC13xxx_FIXED_DEFINE(MC13783_REG_, name, reg, voltages, \
	178	mc13xxx_fixed_regulator_ops)
1bd588fd	179
167e3d8a YS	180	#define MC13783_GPO_DEFINE(prefix, name, reg, voltages) \
	181	MC13xxx_GPO_DEFINE(MC13783_REG_, name, reg, voltages, \
	182	mc13783_gpo_regulator_ops)
a10099bc	183
1bd588fd	184	#define MC13783_DEFINE_SW(_name, _reg, _vsel_reg, _voltages) \
57c78e35	185	MC13783_DEFINE(REG, _name, _reg, _vsel_reg, _voltages)
1bd588fd	186	#define MC13783_DEFINE_REGU(_name, _reg, _vsel_reg, _voltages) \
57c78e35	187	MC13783_DEFINE(REG, _name, _reg, _vsel_reg, _voltages)
a10099bc	188
167e3d8a	189	static struct mc13xxx_regulator mc13783_regulators[] = {
1bd588fd AP	190	MC13783_DEFINE_SW(SW3, SWITCHERS5, SWITCHERS5, mc13783_sw3_val),
1bd588fd AP	191
57c78e35 YS	192	MC13783_FIXED_DEFINE(REG, VAUDIO, REGULATORMODE0, mc13783_vaudio_val),
57c78e35 YS	193	MC13783_FIXED_DEFINE(REG, VIOHI, REGULATORMODE0, mc13783_viohi_val),
1bd588fd AP	194	MC13783_DEFINE_REGU(VIOLO, REGULATORMODE0, REGULATORSETTING0, \
	195	mc13783_violo_val),
	196	MC13783_DEFINE_REGU(VDIG, REGULATORMODE0, REGULATORSETTING0, \
	197	mc13783_vdig_val),
	198	MC13783_DEFINE_REGU(VGEN, REGULATORMODE0, REGULATORSETTING0, \
	199	mc13783_vgen_val),
	200	MC13783_DEFINE_REGU(VRFDIG, REGULATORMODE0, REGULATORSETTING0, \
	201	mc13783_vrfdig_val),
	202	MC13783_DEFINE_REGU(VRFREF, REGULATORMODE0, REGULATORSETTING0, \
	203	mc13783_vrfref_val),
	204	MC13783_DEFINE_REGU(VRFCP, REGULATORMODE0, REGULATORSETTING0, \
	205	mc13783_vrfcp_val),
	206	MC13783_DEFINE_REGU(VSIM, REGULATORMODE1, REGULATORSETTING0, \
	207	mc13783_vsim_val),
	208	MC13783_DEFINE_REGU(VESIM, REGULATORMODE1, REGULATORSETTING0, \
	209	mc13783_vesim_val),
	210	MC13783_DEFINE_REGU(VCAM, REGULATORMODE1, REGULATORSETTING0, \
	211	mc13783_vcam_val),
57c78e35	212	MC13783_FIXED_DEFINE(REG, VRFBG, REGULATORMODE1, mc13783_vrfbg_val),
1bd588fd AP	213	MC13783_DEFINE_REGU(VVIB, REGULATORMODE1, REGULATORSETTING1, \
	214	mc13783_vvib_val),
	215	MC13783_DEFINE_REGU(VRF1, REGULATORMODE1, REGULATORSETTING1, \
	216	mc13783_vrf_val),
	217	MC13783_DEFINE_REGU(VRF2, REGULATORMODE1, REGULATORSETTING1, \
	218	mc13783_vrf_val),
	219	MC13783_DEFINE_REGU(VMMC1, REGULATORMODE1, REGULATORSETTING1, \
	220	mc13783_vmmc_val),
	221	MC13783_DEFINE_REGU(VMMC2, REGULATORMODE1, REGULATORSETTING1, \
	222	mc13783_vmmc_val),
57c78e35 YS	223	MC13783_GPO_DEFINE(REG, GPO1, POWERMISC, mc13783_gpo_val),
	224	MC13783_GPO_DEFINE(REG, GPO2, POWERMISC, mc13783_gpo_val),
	225	MC13783_GPO_DEFINE(REG, GPO3, POWERMISC, mc13783_gpo_val),
	226	MC13783_GPO_DEFINE(REG, GPO4, POWERMISC, mc13783_gpo_val),
	227	MC13783_GPO_DEFINE(REG, PWGT1SPI, POWERMISC, mc13783_pwgtdrv_val),
	228	MC13783_GPO_DEFINE(REG, PWGT2SPI, POWERMISC, mc13783_pwgtdrv_val),
295c08bc SH	229	};
295c08bc SH	230
167e3d8a YS	231	static int mc13783_powermisc_rmw(struct mc13xxx_regulator_priv *priv, u32 mask,
167e3d8a YS	232	u32 val)
f4b97b36	233	{
167e3d8a	234	struct mc13xxx *mc13783 = priv->mc13xxx;
f4b97b36 AP	235	int ret;
	236	u32 valread;
	237
	238	BUG_ON(val & ~mask);
	239
167e3d8a	240	ret = mc13xxx_reg_read(mc13783, MC13783_REG_POWERMISC, &valread);
f4b97b36 AP	241	if (ret)
	242	return ret;
	243
	244	/* Update the stored state for Power Gates. */
	245	priv->powermisc_pwgt_state =
	246	(priv->powermisc_pwgt_state & ~mask) \| val;
	247	priv->powermisc_pwgt_state &= MC13783_REG_POWERMISC_PWGTSPI_M;
	248
	249	/* Construct the new register value */
	250	valread = (valread & ~mask) \| val;
	251	/* Overwrite the PWGTxEN with the stored version */
	252	valread = (valread & ~MC13783_REG_POWERMISC_PWGTSPI_M) \|
	253	priv->powermisc_pwgt_state;
	254
167e3d8a	255	return mc13xxx_reg_write(mc13783, MC13783_REG_POWERMISC, valread);
f4b97b36 AP	256	}
	257
	258	static int mc13783_gpo_regulator_enable(struct regulator_dev *rdev)
	259	{
167e3d8a YS	260	struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
167e3d8a YS	261	struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
f4b97b36 AP	262	int id = rdev_get_id(rdev);
f4b97b36 AP	263	int ret;
167e3d8a	264	u32 en_val = mc13xxx_regulators[id].enable_bit;
f4b97b36 AP	265
	266	dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
	267
	268	/* Power Gate enable value is 0 */
57c78e35 YS	269	if (id == MC13783_REG_PWGT1SPI \|\|
57c78e35 YS	270	id == MC13783_REG_PWGT2SPI)
f4b97b36 AP	271	en_val = 0;
f4b97b36 AP	272
167e3d8a YS	273	mc13xxx_lock(priv->mc13xxx);
167e3d8a YS	274	ret = mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit,
f4b97b36	275	en_val);
167e3d8a	276	mc13xxx_unlock(priv->mc13xxx);
f4b97b36 AP	277
	278	return ret;
	279	}
	280
	281	static int mc13783_gpo_regulator_disable(struct regulator_dev *rdev)
	282	{
167e3d8a YS	283	struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
167e3d8a YS	284	struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
f4b97b36 AP	285	int id = rdev_get_id(rdev);
	286	int ret;
	287	u32 dis_val = 0;
	288
	289	dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
	290
	291	/* Power Gate disable value is 1 */
57c78e35 YS	292	if (id == MC13783_REG_PWGT1SPI \|\|
57c78e35 YS	293	id == MC13783_REG_PWGT2SPI)
167e3d8a	294	dis_val = mc13xxx_regulators[id].enable_bit;
f4b97b36	295
167e3d8a YS	296	mc13xxx_lock(priv->mc13xxx);
167e3d8a YS	297	ret = mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit,
f4b97b36	298	dis_val);
167e3d8a	299	mc13xxx_unlock(priv->mc13xxx);
f4b97b36 AP	300
	301	return ret;
	302	}
	303
	304	static int mc13783_gpo_regulator_is_enabled(struct regulator_dev *rdev)
	305	{
167e3d8a YS	306	struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
167e3d8a YS	307	struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
f4b97b36 AP	308	int ret, id = rdev_get_id(rdev);
	309	unsigned int val;
	310
167e3d8a YS	311	mc13xxx_lock(priv->mc13xxx);
	312	ret = mc13xxx_reg_read(priv->mc13xxx, mc13xxx_regulators[id].reg, &val);
	313	mc13xxx_unlock(priv->mc13xxx);
f4b97b36 AP	314
	315	if (ret)
	316	return ret;
	317
	318	/* Power Gates state is stored in powermisc_pwgt_state
	319	* where the meaning of bits is negated */
	320	val = (val & ~MC13783_REG_POWERMISC_PWGTSPI_M) \|
	321	(priv->powermisc_pwgt_state ^ MC13783_REG_POWERMISC_PWGTSPI_M);
	322
167e3d8a	323	return (val & mc13xxx_regulators[id].enable_bit) != 0;
f4b97b36 AP	324	}
	325
	326	static struct regulator_ops mc13783_gpo_regulator_ops = {
	327	.enable = mc13783_gpo_regulator_enable,
	328	.disable = mc13783_gpo_regulator_disable,
	329	.is_enabled = mc13783_gpo_regulator_is_enabled,
167e3d8a YS	330	.list_voltage = mc13xxx_regulator_list_voltage,
	331	.set_voltage = mc13xxx_fixed_regulator_set_voltage,
	332	.get_voltage = mc13xxx_fixed_regulator_get_voltage,
f4b97b36 AP	333	};
f4b97b36 AP	334
295c08bc SH	335	static int __devinit mc13783_regulator_probe(struct platform_device *pdev)
295c08bc SH	336	{
167e3d8a YS	337	struct mc13xxx_regulator_priv *priv;
167e3d8a YS	338	struct mc13xxx *mc13783 = dev_get_drvdata(pdev->dev.parent);
c8a03c96 SO	339	struct mc13783_regulator_platform_data *pdata =
c8a03c96 SO	340	dev_get_platdata(&pdev->dev);
295c08bc SH	341	struct mc13783_regulator_init_data *init_data;
	342	int i, ret;
	343
c719864f	344	dev_dbg(&pdev->dev, "%s id %d\n", __func__, pdev->id);
295c08bc	345
a10099bc UKK	346	priv = kzalloc(sizeof(*priv) +
a10099bc UKK	347	pdata->num_regulators * sizeof(priv->regulators[0]),
295c08bc SH	348	GFP_KERNEL);
	349	if (!priv)
	350	return -ENOMEM;
	351
167e3d8a YS	352	priv->mc13xxx_regulators = mc13783_regulators;
167e3d8a YS	353	priv->mc13xxx = mc13783;
295c08bc	354
a10099bc UKK	355	for (i = 0; i < pdata->num_regulators; i++) {
a10099bc UKK	356	init_data = &pdata->regulators[i];
295c08bc SH	357	priv->regulators[i] = regulator_register(
	358	&mc13783_regulators[init_data->id].desc,
	359	&pdev->dev, init_data->init_data, priv);
	360
	361	if (IS_ERR(priv->regulators[i])) {
	362	dev_err(&pdev->dev, "failed to register regulator %s\n",
	363	mc13783_regulators[i].desc.name);
	364	ret = PTR_ERR(priv->regulators[i]);
	365	goto err;
	366	}
	367	}
	368
	369	platform_set_drvdata(pdev, priv);
	370
	371	return 0;
	372	err:
	373	while (--i >= 0)
	374	regulator_unregister(priv->regulators[i]);
	375
	376	kfree(priv);
	377
	378	return ret;
	379	}
	380
	381	static int __devexit mc13783_regulator_remove(struct platform_device *pdev)
	382	{
167e3d8a	383	struct mc13xxx_regulator_priv *priv = platform_get_drvdata(pdev);
c8a03c96 SO	384	struct mc13783_regulator_platform_data *pdata =
c8a03c96 SO	385	dev_get_platdata(&pdev->dev);
295c08bc SH	386	int i;
295c08bc SH	387
58d57658 AL	388	platform_set_drvdata(pdev, NULL);
58d57658 AL	389
a10099bc	390	for (i = 0; i < pdata->num_regulators; i++)
295c08bc SH	391	regulator_unregister(priv->regulators[i]);
295c08bc SH	392
58d57658	393	kfree(priv);
295c08bc SH	394	return 0;
	395	}
	396
	397	static struct platform_driver mc13783_regulator_driver = {
	398	.driver = {
	399	.name = "mc13783-regulator",
	400	.owner = THIS_MODULE,
	401	},
	402	.remove = __devexit_p(mc13783_regulator_remove),
735eb93a	403	.probe = mc13783_regulator_probe,
295c08bc SH	404	};
	405
	406	static int __init mc13783_regulator_init(void)
	407	{
735eb93a	408	return platform_driver_register(&mc13783_regulator_driver);
295c08bc SH	409	}
	410	subsys_initcall(mc13783_regulator_init);
	411
	412	static void __exit mc13783_regulator_exit(void)
	413	{
	414	platform_driver_unregister(&mc13783_regulator_driver);
	415	}
	416	module_exit(mc13783_regulator_exit);
	417
a10099bc	418	MODULE_LICENSE("GPL v2");
1dcc434b	419	MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
295c08bc SH	420	MODULE_DESCRIPTION("Regulator Driver for Freescale MC13783 PMIC");
295c08bc SH	421	MODULE_ALIAS("platform:mc13783-regulator");