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regulator: palmas: Fix SMPS enable/disable/is_enabled
[deliverable/linux.git] / drivers / regulator / palmas-regulator.c
CommitLineData
e5ce4208
GG		 1/*
2 * Driver for Regulator part of Palmas PMIC Chips
3 *
7be859f7 4 * Copyright 2011-2013 Texas Instruments Inc.
e5ce4208
GG		 5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
a7dddf27 7 * Author: Ian Lartey <ian@slimlogic.co.uk>
e5ce4208
GG		 8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/err.h>
20#include <linux/platform_device.h>
21#include <linux/regulator/driver.h>
22#include <linux/regulator/machine.h>
23#include <linux/slab.h>
24#include <linux/regmap.h>
25#include <linux/mfd/palmas.h>
a361cd9f
GG		 26#include <linux/of.h>
27#include <linux/of_platform.h>
28#include <linux/regulator/of_regulator.h>
e5ce4208
GG		 29
30struct regs_info {
31 char *name;
504382c9 32 char *sname;
e5ce4208
GG		 33 u8 vsel_addr;
34 u8 ctrl_addr;
35 u8 tstep_addr;
32b6d3f6 36 int sleep_id;
e5ce4208
GG		 37};
38
dbabd624
K		 39static const struct regulator_linear_range smps_low_ranges[] = {
40 REGULATOR_LINEAR_RANGE(500000, 0x1, 0x6, 0),
41 REGULATOR_LINEAR_RANGE(510000, 0x7, 0x79, 10000),
42 REGULATOR_LINEAR_RANGE(1650000, 0x7A, 0x7f, 0),
43};
44
45static const struct regulator_linear_range smps_high_ranges[] = {
46 REGULATOR_LINEAR_RANGE(1000000, 0x1, 0x6, 0),
47 REGULATOR_LINEAR_RANGE(1020000, 0x7, 0x79, 20000),
48 REGULATOR_LINEAR_RANGE(3300000, 0x7A, 0x7f, 0),
49};
50
e5ce4208
GG		 51static const struct regs_info palmas_regs_info[] = {
52 {
53 .name = "SMPS12",
504382c9 54 .sname = "smps1-in",
e5ce4208
GG		 55 .vsel_addr = PALMAS_SMPS12_VOLTAGE,
56 .ctrl_addr = PALMAS_SMPS12_CTRL,
57 .tstep_addr = PALMAS_SMPS12_TSTEP,
32b6d3f6 58 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
e5ce4208
GG		 59 },
60 {
61 .name = "SMPS123",
504382c9 62 .sname = "smps1-in",
e5ce4208
GG		 63 .vsel_addr = PALMAS_SMPS12_VOLTAGE,
64 .ctrl_addr = PALMAS_SMPS12_CTRL,
65 .tstep_addr = PALMAS_SMPS12_TSTEP,
32b6d3f6 66 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
e5ce4208
GG		 67 },
68 {
69 .name = "SMPS3",
504382c9 70 .sname = "smps3-in",
e5ce4208
GG		 71 .vsel_addr = PALMAS_SMPS3_VOLTAGE,
72 .ctrl_addr = PALMAS_SMPS3_CTRL,
32b6d3f6 73 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS3,
e5ce4208
GG		 74 },
75 {
76 .name = "SMPS45",
504382c9 77 .sname = "smps4-in",
e5ce4208
GG		 78 .vsel_addr = PALMAS_SMPS45_VOLTAGE,
79 .ctrl_addr = PALMAS_SMPS45_CTRL,
80 .tstep_addr = PALMAS_SMPS45_TSTEP,
32b6d3f6 81 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
e5ce4208
GG		 82 },
83 {
84 .name = "SMPS457",
504382c9 85 .sname = "smps4-in",
e5ce4208
GG		 86 .vsel_addr = PALMAS_SMPS45_VOLTAGE,
87 .ctrl_addr = PALMAS_SMPS45_CTRL,
88 .tstep_addr = PALMAS_SMPS45_TSTEP,
32b6d3f6 89 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
e5ce4208
GG		 90 },
91 {
92 .name = "SMPS6",
504382c9 93 .sname = "smps6-in",
e5ce4208
GG		 94 .vsel_addr = PALMAS_SMPS6_VOLTAGE,
95 .ctrl_addr = PALMAS_SMPS6_CTRL,
96 .tstep_addr = PALMAS_SMPS6_TSTEP,
32b6d3f6 97 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS6,
e5ce4208
GG		 98 },
99 {
100 .name = "SMPS7",
504382c9 101 .sname = "smps7-in",
e5ce4208
GG		 102 .vsel_addr = PALMAS_SMPS7_VOLTAGE,
103 .ctrl_addr = PALMAS_SMPS7_CTRL,
32b6d3f6 104 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS7,
e5ce4208
GG		 105 },
106 {
107 .name = "SMPS8",
504382c9 108 .sname = "smps8-in",
e5ce4208
GG		 109 .vsel_addr = PALMAS_SMPS8_VOLTAGE,
110 .ctrl_addr = PALMAS_SMPS8_CTRL,
111 .tstep_addr = PALMAS_SMPS8_TSTEP,
32b6d3f6 112 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS8,
e5ce4208
GG		 113 },
114 {
115 .name = "SMPS9",
504382c9 116 .sname = "smps9-in",
e5ce4208
GG		 117 .vsel_addr = PALMAS_SMPS9_VOLTAGE,
118 .ctrl_addr = PALMAS_SMPS9_CTRL,
32b6d3f6 119 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS9,
e5ce4208
GG		 120 },
121 {
77409d9b 122 .name = "SMPS10_OUT2",
504382c9 123 .sname = "smps10-in",
e31089c6 124 .ctrl_addr = PALMAS_SMPS10_CTRL,
32b6d3f6 125 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
e5ce4208 126 },
77409d9b
KVA		 127 {
128 .name = "SMPS10_OUT1",
129 .sname = "smps10-out2",
130 .ctrl_addr = PALMAS_SMPS10_CTRL,
32b6d3f6 131 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
77409d9b 132 },
e5ce4208
GG		 133 {
134 .name = "LDO1",
504382c9 135 .sname = "ldo1-in",
e5ce4208
GG		 136 .vsel_addr = PALMAS_LDO1_VOLTAGE,
137 .ctrl_addr = PALMAS_LDO1_CTRL,
32b6d3f6 138 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO1,
e5ce4208
GG		 139 },
140 {
141 .name = "LDO2",
504382c9 142 .sname = "ldo2-in",
e5ce4208
GG		 143 .vsel_addr = PALMAS_LDO2_VOLTAGE,
144 .ctrl_addr = PALMAS_LDO2_CTRL,
32b6d3f6 145 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO2,
e5ce4208
GG		 146 },
147 {
148 .name = "LDO3",
504382c9 149 .sname = "ldo3-in",
e5ce4208
GG		 150 .vsel_addr = PALMAS_LDO3_VOLTAGE,
151 .ctrl_addr = PALMAS_LDO3_CTRL,
32b6d3f6 152 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO3,
e5ce4208
GG		 153 },
154 {
155 .name = "LDO4",
504382c9 156 .sname = "ldo4-in",
e5ce4208
GG		 157 .vsel_addr = PALMAS_LDO4_VOLTAGE,
158 .ctrl_addr = PALMAS_LDO4_CTRL,
32b6d3f6 159 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO4,
e5ce4208
GG		 160 },
161 {
162 .name = "LDO5",
504382c9 163 .sname = "ldo5-in",
e5ce4208
GG		 164 .vsel_addr = PALMAS_LDO5_VOLTAGE,
165 .ctrl_addr = PALMAS_LDO5_CTRL,
32b6d3f6 166 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO5,
e5ce4208
GG		 167 },
168 {
169 .name = "LDO6",
504382c9 170 .sname = "ldo6-in",
e5ce4208
GG		 171 .vsel_addr = PALMAS_LDO6_VOLTAGE,
172 .ctrl_addr = PALMAS_LDO6_CTRL,
32b6d3f6 173 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO6,
e5ce4208
GG		 174 },
175 {
176 .name = "LDO7",
504382c9 177 .sname = "ldo7-in",
e5ce4208
GG		 178 .vsel_addr = PALMAS_LDO7_VOLTAGE,
179 .ctrl_addr = PALMAS_LDO7_CTRL,
32b6d3f6 180 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO7,
e5ce4208
GG		 181 },
182 {
183 .name = "LDO8",
504382c9 184 .sname = "ldo8-in",
e5ce4208
GG		 185 .vsel_addr = PALMAS_LDO8_VOLTAGE,
186 .ctrl_addr = PALMAS_LDO8_CTRL,
32b6d3f6 187 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO8,
e5ce4208
GG		 188 },
189 {
190 .name = "LDO9",
504382c9 191 .sname = "ldo9-in",
e5ce4208
GG		 192 .vsel_addr = PALMAS_LDO9_VOLTAGE,
193 .ctrl_addr = PALMAS_LDO9_CTRL,
32b6d3f6 194 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO9,
e5ce4208
GG		 195 },
196 {
197 .name = "LDOLN",
504382c9 198 .sname = "ldoln-in",
e5ce4208
GG		 199 .vsel_addr = PALMAS_LDOLN_VOLTAGE,
200 .ctrl_addr = PALMAS_LDOLN_CTRL,
32b6d3f6 201 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDOLN,
e5ce4208
GG		 202 },
203 {
204 .name = "LDOUSB",
504382c9 205 .sname = "ldousb-in",
e5ce4208
GG		 206 .vsel_addr = PALMAS_LDOUSB_VOLTAGE,
207 .ctrl_addr = PALMAS_LDOUSB_CTRL,
32b6d3f6 208 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDOUSB,
e5ce4208 209 },
aa07f027
LD		 210 {
211 .name = "REGEN1",
212 .ctrl_addr = PALMAS_REGEN1_CTRL,
32b6d3f6 213 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN1,
aa07f027
LD		 214 },
215 {
216 .name = "REGEN2",
217 .ctrl_addr = PALMAS_REGEN2_CTRL,
32b6d3f6 218 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN2,
aa07f027
LD		 219 },
220 {
221 .name = "REGEN3",
222 .ctrl_addr = PALMAS_REGEN3_CTRL,
32b6d3f6 223 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN3,
aa07f027
LD		 224 },
225 {
226 .name = "SYSEN1",
227 .ctrl_addr = PALMAS_SYSEN1_CTRL,
32b6d3f6 228 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SYSEN1,
aa07f027
LD		 229 },
230 {
231 .name = "SYSEN2",
232 .ctrl_addr = PALMAS_SYSEN2_CTRL,
32b6d3f6 233 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SYSEN2,
aa07f027 234 },
e5ce4208
GG		 235};
236
28d1e8cd
LD		 237static unsigned int palmas_smps_ramp_delay[4] = {0, 10000, 5000, 2500};
238
e5ce4208
GG		 239#define SMPS_CTRL_MODE_OFF 0x00
240#define SMPS_CTRL_MODE_ON 0x01
241#define SMPS_CTRL_MODE_ECO 0x02
242#define SMPS_CTRL_MODE_PWM 0x03
243
0f45aa84 244#define PALMAS_SMPS_NUM_VOLTAGES 122
e5ce4208
GG		 245#define PALMAS_SMPS10_NUM_VOLTAGES 2
246#define PALMAS_LDO_NUM_VOLTAGES 50
247
248#define SMPS10_VSEL (1<<3)
249#define SMPS10_BOOST_EN (1<<2)
250#define SMPS10_BYPASS_EN (1<<1)
251#define SMPS10_SWITCH_EN (1<<0)
252
253#define REGULATOR_SLAVE 0
254
255static int palmas_smps_read(struct palmas *palmas, unsigned int reg,
256 unsigned int *dest)
257{
258 unsigned int addr;
259
260 addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg);
261
262 return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest);
263}
264
265static int palmas_smps_write(struct palmas *palmas, unsigned int reg,
266 unsigned int value)
267{
268 unsigned int addr;
269
270 addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg);
271
272 return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value);
273}
274
275static int palmas_ldo_read(struct palmas *palmas, unsigned int reg,
276 unsigned int *dest)
277{
278 unsigned int addr;
279
280 addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg);
281
282 return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest);
283}
284
285static int palmas_ldo_write(struct palmas *palmas, unsigned int reg,
286 unsigned int value)
287{
288 unsigned int addr;
289
290 addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg);
291
292 return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value);
293}
294
e5ce4208
GG		 295static int palmas_set_mode_smps(struct regulator_dev *dev, unsigned int mode)
296{
297 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
298 int id = rdev_get_id(dev);
299 unsigned int reg;
51d3a0c9 300 bool rail_enable = true;
e5ce4208
GG		 301
302 palmas_smps_read(pmic->palmas, palmas_regs_info[id].ctrl_addr, &reg);
999f0c7c 303 reg &= ~PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
e5ce4208 304
51d3a0c9
LD		 305 if (reg == SMPS_CTRL_MODE_OFF)
306 rail_enable = false;
307
e5ce4208
GG		 308 switch (mode) {
309 case REGULATOR_MODE_NORMAL:
310 reg |= SMPS_CTRL_MODE_ON;
311 break;
312 case REGULATOR_MODE_IDLE:
313 reg |= SMPS_CTRL_MODE_ECO;
314 break;
315 case REGULATOR_MODE_FAST:
316 reg |= SMPS_CTRL_MODE_PWM;
317 break;
318 default:
319 return -EINVAL;
320 }
e5ce4208 321
51d3a0c9
LD		 322 pmic->current_reg_mode[id] = reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
323 if (rail_enable)
324 palmas_smps_write(pmic->palmas,
325 palmas_regs_info[id].ctrl_addr, reg);
318dbb02
NM		 326
327 /* Switch the enable value to ensure this is used for enable */
328 pmic->desc[id].enable_val = pmic->current_reg_mode[id];
329
e5ce4208
GG		 330 return 0;
331}
332
333static unsigned int palmas_get_mode_smps(struct regulator_dev *dev)
334{
335 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
336 int id = rdev_get_id(dev);
337 unsigned int reg;
338
51d3a0c9 339 reg = pmic->current_reg_mode[id] & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
e5ce4208
GG		 340
341 switch (reg) {
342 case SMPS_CTRL_MODE_ON:
343 return REGULATOR_MODE_NORMAL;
344 case SMPS_CTRL_MODE_ECO:
345 return REGULATOR_MODE_IDLE;
346 case SMPS_CTRL_MODE_PWM:
347 return REGULATOR_MODE_FAST;
348 }
349
350 return 0;
351}
352
28d1e8cd
LD		 353static int palmas_smps_set_ramp_delay(struct regulator_dev *rdev,
354 int ramp_delay)
355{
356 struct palmas_pmic *pmic = rdev_get_drvdata(rdev);
357 int id = rdev_get_id(rdev);
358 unsigned int reg = 0;
359 unsigned int addr = palmas_regs_info[id].tstep_addr;
360 int ret;
361
f22c2bae
AL		 362 /* SMPS3 and SMPS7 do not have tstep_addr setting */
363 switch (id) {
364 case PALMAS_REG_SMPS3:
365 case PALMAS_REG_SMPS7:
366 return 0;
367 }
368
28d1e8cd
LD		 369 if (ramp_delay <= 0)
370 reg = 0;
0ea34b57 371 else if (ramp_delay <= 2500)
28d1e8cd 372 reg = 3;
0ea34b57 373 else if (ramp_delay <= 5000)
28d1e8cd
LD		 374 reg = 2;
375 else
376 reg = 1;
377
378 ret = palmas_smps_write(pmic->palmas, addr, reg);
379 if (ret < 0) {
380 dev_err(pmic->palmas->dev, "TSTEP write failed: %d\n", ret);
381 return ret;
382 }
383
384 pmic->ramp_delay[id] = palmas_smps_ramp_delay[reg];
385 return ret;
386}
387
e5ce4208 388static struct regulator_ops palmas_ops_smps = {
dbabd624
K		 389 .is_enabled = regulator_is_enabled_regmap,
390 .enable = regulator_enable_regmap,
391 .disable = regulator_disable_regmap,
e5ce4208
GG		 392 .set_mode = palmas_set_mode_smps,
393 .get_mode = palmas_get_mode_smps,
bdc4baac
AL		 394 .get_voltage_sel = regulator_get_voltage_sel_regmap,
395 .set_voltage_sel = regulator_set_voltage_sel_regmap,
dbabd624
K		 396 .list_voltage = regulator_list_voltage_linear_range,
397 .map_voltage = regulator_map_voltage_linear_range,
398 .set_voltage_time_sel = regulator_set_voltage_time_sel,
28d1e8cd 399 .set_ramp_delay = palmas_smps_set_ramp_delay,
e5ce4208
GG		 400};
401
32b6d3f6
LD		 402static struct regulator_ops palmas_ops_ext_control_smps = {
403 .set_mode = palmas_set_mode_smps,
404 .get_mode = palmas_get_mode_smps,
405 .get_voltage_sel = regulator_get_voltage_sel_regmap,
406 .set_voltage_sel = regulator_set_voltage_sel_regmap,
dbabd624
K		 407 .list_voltage = regulator_list_voltage_linear_range,
408 .map_voltage = regulator_map_voltage_linear_range,
409 .set_voltage_time_sel = regulator_set_voltage_time_sel,
32b6d3f6
LD		 410 .set_ramp_delay = palmas_smps_set_ramp_delay,
411};
412
e5ce4208
GG		 413static struct regulator_ops palmas_ops_smps10 = {
414 .is_enabled = regulator_is_enabled_regmap,
415 .enable = regulator_enable_regmap,
416 .disable = regulator_disable_regmap,
417 .get_voltage_sel = regulator_get_voltage_sel_regmap,
418 .set_voltage_sel = regulator_set_voltage_sel_regmap,
8029a006
AL		 419 .list_voltage = regulator_list_voltage_linear,
420 .map_voltage = regulator_map_voltage_linear,
77409d9b
KVA		 421 .set_bypass = regulator_set_bypass_regmap,
422 .get_bypass = regulator_get_bypass_regmap,
e5ce4208
GG		 423};
424
425static int palmas_is_enabled_ldo(struct regulator_dev *dev)
426{
427 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
428 int id = rdev_get_id(dev);
429 unsigned int reg;
430
431 palmas_ldo_read(pmic->palmas, palmas_regs_info[id].ctrl_addr, &reg);
432
433 reg &= PALMAS_LDO1_CTRL_STATUS;
434
435 return !!(reg);
436}
437
e5ce4208
GG		 438static struct regulator_ops palmas_ops_ldo = {
439 .is_enabled = palmas_is_enabled_ldo,
440 .enable = regulator_enable_regmap,
441 .disable = regulator_disable_regmap,
4a247a96
AL		 442 .get_voltage_sel = regulator_get_voltage_sel_regmap,
443 .set_voltage_sel = regulator_set_voltage_sel_regmap,
9119ff6a
AL		 444 .list_voltage = regulator_list_voltage_linear,
445 .map_voltage = regulator_map_voltage_linear,
e5ce4208
GG		 446};
447
32b6d3f6
LD		 448static struct regulator_ops palmas_ops_ext_control_ldo = {
449 .get_voltage_sel = regulator_get_voltage_sel_regmap,
450 .set_voltage_sel = regulator_set_voltage_sel_regmap,
451 .list_voltage = regulator_list_voltage_linear,
452 .map_voltage = regulator_map_voltage_linear,
453};
454
aa07f027
LD		 455static struct regulator_ops palmas_ops_extreg = {
456 .is_enabled = regulator_is_enabled_regmap,
457 .enable = regulator_enable_regmap,
458 .disable = regulator_disable_regmap,
459};
460
32b6d3f6
LD		 461static struct regulator_ops palmas_ops_ext_control_extreg = {
462};
463
464static int palmas_regulator_config_external(struct palmas *palmas, int id,
465 struct palmas_reg_init *reg_init)
466{
467 int sleep_id = palmas_regs_info[id].sleep_id;
468 int ret;
469
470 ret = palmas_ext_control_req_config(palmas, sleep_id,
471 reg_init->roof_floor, true);
472 if (ret < 0)
473 dev_err(palmas->dev,
474 "Ext control config for regulator %d failed %d\n",
475 id, ret);
476 return ret;
477}
478
e5ce4208
GG		 479/*
480 * setup the hardware based sleep configuration of the SMPS/LDO regulators
481 * from the platform data. This is different to the software based control
482 * supported by the regulator framework as it is controlled by toggling
483 * pins on the PMIC such as PREQ, SYSEN, ...
484 */
485static int palmas_smps_init(struct palmas *palmas, int id,
486 struct palmas_reg_init *reg_init)
487{
488 unsigned int reg;
489 unsigned int addr;
490 int ret;
491
492 addr = palmas_regs_info[id].ctrl_addr;
493
494 ret = palmas_smps_read(palmas, addr, &reg);
495 if (ret)
496 return ret;
497
fedd89b1 498 switch (id) {
77409d9b
KVA		 499 case PALMAS_REG_SMPS10_OUT1:
500 case PALMAS_REG_SMPS10_OUT2:
30590d04
LD		 501 reg &= ~PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK;
502 if (reg_init->mode_sleep)
fedd89b1
AL		 503 reg |= reg_init->mode_sleep <<
504 PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT;
fedd89b1
AL		 505 break;
506 default:
e5ce4208
GG		 507 if (reg_init->warm_reset)
508 reg |= PALMAS_SMPS12_CTRL_WR_S;
30590d04
LD		 509 else
510 reg &= ~PALMAS_SMPS12_CTRL_WR_S;
e5ce4208
GG		 511
512 if (reg_init->roof_floor)
513 reg |= PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN;
30590d04
LD		 514 else
515 reg &= ~PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN;
e5ce4208 516
30590d04
LD		 517 reg &= ~PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK;
518 if (reg_init->mode_sleep)
e5ce4208
GG		 519 reg |= reg_init->mode_sleep <<
520 PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT;
e5ce4208 521 }
fedd89b1 522
e5ce4208
GG		 523 ret = palmas_smps_write(palmas, addr, reg);
524 if (ret)
525 return ret;
526
e5ce4208
GG		 527 if (palmas_regs_info[id].vsel_addr && reg_init->vsel) {
528 addr = palmas_regs_info[id].vsel_addr;
529
530 reg = reg_init->vsel;
531
532 ret = palmas_smps_write(palmas, addr, reg);
533 if (ret)
534 return ret;
535 }
536
32b6d3f6
LD		 537 if (reg_init->roof_floor && (id != PALMAS_REG_SMPS10_OUT1) &&
538 (id != PALMAS_REG_SMPS10_OUT2)) {
539 /* Enable externally controlled regulator */
540 addr = palmas_regs_info[id].ctrl_addr;
541 ret = palmas_smps_read(palmas, addr, &reg);
542 if (ret < 0)
543 return ret;
e5ce4208 544
32b6d3f6
LD		 545 if (!(reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK)) {
546 reg |= SMPS_CTRL_MODE_ON;
547 ret = palmas_smps_write(palmas, addr, reg);
548 if (ret < 0)
549 return ret;
550 }
551 return palmas_regulator_config_external(palmas, id, reg_init);
552 }
e5ce4208
GG		 553 return 0;
554}
555
556static int palmas_ldo_init(struct palmas *palmas, int id,
557 struct palmas_reg_init *reg_init)
558{
559 unsigned int reg;
560 unsigned int addr;
561 int ret;
562
563 addr = palmas_regs_info[id].ctrl_addr;
564
2735daeb 565 ret = palmas_ldo_read(palmas, addr, &reg);
e5ce4208
GG		 566 if (ret)
567 return ret;
568
569 if (reg_init->warm_reset)
570 reg |= PALMAS_LDO1_CTRL_WR_S;
30590d04
LD		 571 else
572 reg &= ~PALMAS_LDO1_CTRL_WR_S;
e5ce4208
GG		 573
574 if (reg_init->mode_sleep)
575 reg |= PALMAS_LDO1_CTRL_MODE_SLEEP;
30590d04
LD		 576 else
577 reg &= ~PALMAS_LDO1_CTRL_MODE_SLEEP;
e5ce4208 578
2735daeb 579 ret = palmas_ldo_write(palmas, addr, reg);
e5ce4208
GG		 580 if (ret)
581 return ret;
582
32b6d3f6
LD		 583 if (reg_init->roof_floor) {
584 /* Enable externally controlled regulator */
585 addr = palmas_regs_info[id].ctrl_addr;
586 ret = palmas_update_bits(palmas, PALMAS_LDO_BASE,
587 addr, PALMAS_LDO1_CTRL_MODE_ACTIVE,
588 PALMAS_LDO1_CTRL_MODE_ACTIVE);
589 if (ret < 0) {
590 dev_err(palmas->dev,
591 "LDO Register 0x%02x update failed %d\n",
592 addr, ret);
593 return ret;
594 }
595 return palmas_regulator_config_external(palmas, id, reg_init);
596 }
e5ce4208
GG		 597 return 0;
598}
599
aa07f027
LD		 600static int palmas_extreg_init(struct palmas *palmas, int id,
601 struct palmas_reg_init *reg_init)
602{
603 unsigned int addr;
604 int ret;
605 unsigned int val = 0;
606
607 addr = palmas_regs_info[id].ctrl_addr;
608
609 if (reg_init->mode_sleep)
610 val = PALMAS_REGEN1_CTRL_MODE_SLEEP;
611
612 ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
613 addr, PALMAS_REGEN1_CTRL_MODE_SLEEP, val);
614 if (ret < 0) {
615 dev_err(palmas->dev, "Resource reg 0x%02x update failed %d\n",
616 addr, ret);
617 return ret;
618 }
32b6d3f6
LD		 619
620 if (reg_init->roof_floor) {
621 /* Enable externally controlled regulator */
622 addr = palmas_regs_info[id].ctrl_addr;
623 ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
624 addr, PALMAS_REGEN1_CTRL_MODE_ACTIVE,
625 PALMAS_REGEN1_CTRL_MODE_ACTIVE);
626 if (ret < 0) {
627 dev_err(palmas->dev,
628 "Resource Register 0x%02x update failed %d\n",
629 addr, ret);
630 return ret;
631 }
632 return palmas_regulator_config_external(palmas, id, reg_init);
633 }
aa07f027
LD		 634 return 0;
635}
636
17c11a76
LD		 637static void palmas_enable_ldo8_track(struct palmas *palmas)
638{
639 unsigned int reg;
640 unsigned int addr;
641 int ret;
642
643 addr = palmas_regs_info[PALMAS_REG_LDO8].ctrl_addr;
644
645 ret = palmas_ldo_read(palmas, addr, &reg);
646 if (ret) {
647 dev_err(palmas->dev, "Error in reading ldo8 control reg\n");
648 return;
649 }
650
651 reg |= PALMAS_LDO8_CTRL_LDO_TRACKING_EN;
652 ret = palmas_ldo_write(palmas, addr, reg);
653 if (ret < 0) {
654 dev_err(palmas->dev, "Error in enabling tracking mode\n");
655 return;
656 }
657 /*
658 * When SMPS45 is set to off and LDO8 tracking is enabled, the LDO8
659 * output is defined by the LDO8_VOLTAGE.VSEL register divided by two,
660 * and can be set from 0.45 to 1.65 V.
661 */
662 addr = palmas_regs_info[PALMAS_REG_LDO8].vsel_addr;
663 ret = palmas_ldo_read(palmas, addr, &reg);
664 if (ret) {
665 dev_err(palmas->dev, "Error in reading ldo8 voltage reg\n");
666 return;
667 }
668
669 reg = (reg << 1) & PALMAS_LDO8_VOLTAGE_VSEL_MASK;
670 ret = palmas_ldo_write(palmas, addr, reg);
671 if (ret < 0)
672 dev_err(palmas->dev, "Error in setting ldo8 voltage reg\n");
673
674 return;
675}
676
a361cd9f
GG		 677static struct of_regulator_match palmas_matches[] = {
678 { .name = "smps12", },
679 { .name = "smps123", },
680 { .name = "smps3", },
681 { .name = "smps45", },
682 { .name = "smps457", },
683 { .name = "smps6", },
684 { .name = "smps7", },
685 { .name = "smps8", },
686 { .name = "smps9", },
77409d9b
KVA		 687 { .name = "smps10_out2", },
688 { .name = "smps10_out1", },
a361cd9f
GG		 689 { .name = "ldo1", },
690 { .name = "ldo2", },
691 { .name = "ldo3", },
692 { .name = "ldo4", },
693 { .name = "ldo5", },
694 { .name = "ldo6", },
695 { .name = "ldo7", },
696 { .name = "ldo8", },
697 { .name = "ldo9", },
698 { .name = "ldoln", },
699 { .name = "ldousb", },
aa07f027
LD		 700 { .name = "regen1", },
701 { .name = "regen2", },
702 { .name = "regen3", },
703 { .name = "sysen1", },
704 { .name = "sysen2", },
a361cd9f
GG		 705};
706
a5023574 707static void palmas_dt_to_pdata(struct device *dev,
a361cd9f
GG		 708 struct device_node *node,
709 struct palmas_pmic_platform_data *pdata)
710{
711 struct device_node *regulators;
712 u32 prop;
713 int idx, ret;
714
c92f5dd2 715 node = of_node_get(node);
acc1ccad 716 regulators = of_get_child_by_name(node, "regulators");
a361cd9f
GG		 717 if (!regulators) {
718 dev_info(dev, "regulator node not found\n");
719 return;
720 }
721
722 ret = of_regulator_match(dev, regulators, palmas_matches,
723 PALMAS_NUM_REGS);
c92f5dd2 724 of_node_put(regulators);
a361cd9f
GG		 725 if (ret < 0) {
726 dev_err(dev, "Error parsing regulator init data: %d\n", ret);
727 return;
728 }
729
730 for (idx = 0; idx < PALMAS_NUM_REGS; idx++) {
731 if (!palmas_matches[idx].init_data ||
732 !palmas_matches[idx].of_node)
733 continue;
734
735 pdata->reg_data[idx] = palmas_matches[idx].init_data;
736
737 pdata->reg_init[idx] = devm_kzalloc(dev,
738 sizeof(struct palmas_reg_init), GFP_KERNEL);
739
7be859f7 740 pdata->reg_init[idx]->warm_reset =
71f2146f
AL		 741 of_property_read_bool(palmas_matches[idx].of_node,
742 "ti,warm-reset");
a361cd9f 743
32b6d3f6
LD		 744 ret = of_property_read_u32(palmas_matches[idx].of_node,
745 "ti,roof-floor", &prop);
746 /* EINVAL: Property not found */
747 if (ret != -EINVAL) {
748 int econtrol;
749
750 /* use default value, when no value is specified */
751 econtrol = PALMAS_EXT_CONTROL_NSLEEP;
752 if (!ret) {
753 switch (prop) {
754 case 1:
755 econtrol = PALMAS_EXT_CONTROL_ENABLE1;
756 break;
757 case 2:
758 econtrol = PALMAS_EXT_CONTROL_ENABLE2;
759 break;
760 case 3:
761 econtrol = PALMAS_EXT_CONTROL_NSLEEP;
762 break;
763 default:
764 WARN_ON(1);
765 dev_warn(dev,
766 "%s: Invalid roof-floor option: %u\n",
767 palmas_matches[idx].name, prop);
768 break;
769 }
770 }
771 pdata->reg_init[idx]->roof_floor = econtrol;
772 }
a361cd9f
GG		 773
774 ret = of_property_read_u32(palmas_matches[idx].of_node,
3c870e3f 775 "ti,mode-sleep", &prop);
a361cd9f
GG		 776 if (!ret)
777 pdata->reg_init[idx]->mode_sleep = prop;
778
7be859f7
GG		 779 ret = of_property_read_bool(palmas_matches[idx].of_node,
780 "ti,smps-range");
781 if (ret)
782 pdata->reg_init[idx]->vsel =
783 PALMAS_SMPS12_VOLTAGE_RANGE;
a361cd9f 784
17c11a76
LD		 785 if (idx == PALMAS_REG_LDO8)
786 pdata->enable_ldo8_tracking = of_property_read_bool(
787 palmas_matches[idx].of_node,
788 "ti,enable-ldo8-tracking");
a361cd9f
GG		 789 }
790
7be859f7 791 pdata->ldo6_vibrator = of_property_read_bool(node, "ti,ldo6-vibrator");
a361cd9f
GG		 792}
793
794
bbcf50b1 795static int palmas_regulators_probe(struct platform_device *pdev)
e5ce4208
GG		 796{
797 struct palmas *palmas = dev_get_drvdata(pdev->dev.parent);
dff91d0b 798 struct palmas_pmic_platform_data *pdata = dev_get_platdata(&pdev->dev);
a361cd9f 799 struct device_node *node = pdev->dev.of_node;
e5ce4208
GG		 800 struct regulator_dev *rdev;
801 struct regulator_config config = { };
802 struct palmas_pmic *pmic;
803 struct palmas_reg_init *reg_init;
804 int id = 0, ret;
805 unsigned int addr, reg;
806
a361cd9f
GG		 807 if (node && !pdata) {
808 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
809
810 if (!pdata)
811 return -ENOMEM;
812
813 palmas_dt_to_pdata(&pdev->dev, node, pdata);
814 }
e5ce4208
GG		 815
816 pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
817 if (!pmic)
818 return -ENOMEM;
819
820 pmic->dev = &pdev->dev;
821 pmic->palmas = palmas;
822 palmas->pmic = pmic;
823 platform_set_drvdata(pdev, pmic);
824
825 ret = palmas_smps_read(palmas, PALMAS_SMPS_CTRL, &reg);
826 if (ret)
1c9d2d71 827 return ret;
e5ce4208
GG		 828
829 if (reg & PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN)
830 pmic->smps123 = 1;
831
832 if (reg & PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN)
833 pmic->smps457 = 1;
834
835 config.regmap = palmas->regmap[REGULATOR_SLAVE];
836 config.dev = &pdev->dev;
837 config.driver_data = pmic;
838
839 for (id = 0; id < PALMAS_REG_LDO1; id++) {
28d1e8cd 840 bool ramp_delay_support = false;
e5ce4208
GG		 841
842 /*
843 * Miss out regulators which are not available due
844 * to slaving configurations.
845 */
846 switch (id) {
847 case PALMAS_REG_SMPS12:
848 case PALMAS_REG_SMPS3:
849 if (pmic->smps123)
850 continue;
28d1e8cd
LD		 851 if (id == PALMAS_REG_SMPS12)
852 ramp_delay_support = true;
e5ce4208
GG		 853 break;
854 case PALMAS_REG_SMPS123:
855 if (!pmic->smps123)
856 continue;
28d1e8cd 857 ramp_delay_support = true;
e5ce4208
GG		 858 break;
859 case PALMAS_REG_SMPS45:
860 case PALMAS_REG_SMPS7:
861 if (pmic->smps457)
862 continue;
28d1e8cd
LD		 863 if (id == PALMAS_REG_SMPS45)
864 ramp_delay_support = true;
e5ce4208
GG		 865 break;
866 case PALMAS_REG_SMPS457:
867 if (!pmic->smps457)
868 continue;
28d1e8cd
LD		 869 ramp_delay_support = true;
870 break;
77409d9b
KVA		 871 case PALMAS_REG_SMPS10_OUT1:
872 case PALMAS_REG_SMPS10_OUT2:
1ffb0be3
K		 873 if (!PALMAS_PMIC_HAS(palmas, SMPS10_BOOST))
874 continue;
28d1e8cd
LD		 875 }
876
3f4d6364 877 if ((id == PALMAS_REG_SMPS6) || (id == PALMAS_REG_SMPS8))
28d1e8cd
LD		 878 ramp_delay_support = true;
879
880 if (ramp_delay_support) {
881 addr = palmas_regs_info[id].tstep_addr;
882 ret = palmas_smps_read(pmic->palmas, addr, &reg);
883 if (ret < 0) {
884 dev_err(&pdev->dev,
885 "reading TSTEP reg failed: %d\n", ret);
51c86b3e 886 return ret;
28d1e8cd
LD		 887 }
888 pmic->desc[id].ramp_delay =
889 palmas_smps_ramp_delay[reg & 0x3];
890 pmic->ramp_delay[id] = pmic->desc[id].ramp_delay;
e5ce4208
GG		 891 }
892
bdc4baac
AL		 893 /* Initialise sleep/init values from platform data */
894 if (pdata && pdata->reg_init[id]) {
895 reg_init = pdata->reg_init[id];
896 ret = palmas_smps_init(palmas, id, reg_init);
897 if (ret)
51c86b3e 898 return ret;
32b6d3f6
LD		 899 } else {
900 reg_init = NULL;
bdc4baac
AL		 901 }
902
e5ce4208
GG		 903 /* Register the regulators */
904 pmic->desc[id].name = palmas_regs_info[id].name;
905 pmic->desc[id].id = id;
906
fedd89b1 907 switch (id) {
77409d9b
KVA		 908 case PALMAS_REG_SMPS10_OUT1:
909 case PALMAS_REG_SMPS10_OUT2:
e5ce4208
GG		 910 pmic->desc[id].n_voltages = PALMAS_SMPS10_NUM_VOLTAGES;
911 pmic->desc[id].ops = &palmas_ops_smps10;
12565b16
AL		 912 pmic->desc[id].vsel_reg =
913 PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
914 PALMAS_SMPS10_CTRL);
e5ce4208 915 pmic->desc[id].vsel_mask = SMPS10_VSEL;
a68de074
GG		 916 pmic->desc[id].enable_reg =
917 PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
f232168d 918 PALMAS_SMPS10_CTRL);
77409d9b
KVA		 919 if (id == PALMAS_REG_SMPS10_OUT1)
920 pmic->desc[id].enable_mask = SMPS10_SWITCH_EN;
921 else
922 pmic->desc[id].enable_mask = SMPS10_BOOST_EN;
923 pmic->desc[id].bypass_reg =
924 PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
925 PALMAS_SMPS10_CTRL);
926 pmic->desc[id].bypass_mask = SMPS10_BYPASS_EN;
8029a006
AL		 927 pmic->desc[id].min_uV = 3750000;
928 pmic->desc[id].uV_step = 1250000;
fedd89b1
AL		 929 break;
930 default:
bdc4baac
AL		 931 /*
932 * Read and store the RANGE bit for later use
933 * This must be done before regulator is probed,
51d3a0c9
LD		 934 * otherwise we error in probe with unsupportable
935 * ranges. Read the current smps mode for later use.
bdc4baac 936 */
e5ce4208 937 addr = palmas_regs_info[id].vsel_addr;
dbabd624 938 pmic->desc[id].n_linear_ranges = 3;
e5ce4208
GG		 939
940 ret = palmas_smps_read(pmic->palmas, addr, &reg);
941 if (ret)
51c86b3e 942 return ret;
e5ce4208
GG		 943 if (reg & PALMAS_SMPS12_VOLTAGE_RANGE)
944 pmic->range[id] = 1;
dbabd624
K		 945 if (pmic->range[id])
946 pmic->desc[id].linear_ranges = smps_high_ranges;
947 else
948 pmic->desc[id].linear_ranges = smps_low_ranges;
bdc4baac 949
32b6d3f6
LD		 950 if (reg_init && reg_init->roof_floor)
951 pmic->desc[id].ops =
952 &palmas_ops_ext_control_smps;
953 else
954 pmic->desc[id].ops = &palmas_ops_smps;
bdc4baac
AL		 955 pmic->desc[id].n_voltages = PALMAS_SMPS_NUM_VOLTAGES;
956 pmic->desc[id].vsel_reg =
957 PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
958 palmas_regs_info[id].vsel_addr);
959 pmic->desc[id].vsel_mask =
960 PALMAS_SMPS12_VOLTAGE_VSEL_MASK;
51d3a0c9
LD		 961
962 /* Read the smps mode for later use. */
963 addr = palmas_regs_info[id].ctrl_addr;
964 ret = palmas_smps_read(pmic->palmas, addr, &reg);
965 if (ret)
51c86b3e 966 return ret;
51d3a0c9
LD		 967 pmic->current_reg_mode[id] = reg &
968 PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
318dbb02
NM		 969
970 pmic->desc[id].enable_reg =
971 PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
972 palmas_regs_info[id].ctrl_addr);
973 pmic->desc[id].enable_mask =
974 PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
975 /* set_mode overrides this value */
976 pmic->desc[id].enable_val = SMPS_CTRL_MODE_ON;
e5ce4208
GG		 977 }
978
bdc4baac
AL		 979 pmic->desc[id].type = REGULATOR_VOLTAGE;
980 pmic->desc[id].owner = THIS_MODULE;
981
a361cd9f 982 if (pdata)
e5ce4208
GG		 983 config.init_data = pdata->reg_data[id];
984 else
985 config.init_data = NULL;
986
504382c9 987 pmic->desc[id].supply_name = palmas_regs_info[id].sname;
a361cd9f
GG		 988 config.of_node = palmas_matches[id].of_node;
989
51c86b3e
SK		 990 rdev = devm_regulator_register(&pdev->dev, &pmic->desc[id],
991 &config);
e5ce4208
GG		 992 if (IS_ERR(rdev)) {
993 dev_err(&pdev->dev,
994 "failed to register %s regulator\n",
995 pdev->name);
51c86b3e 996 return PTR_ERR(rdev);
e5ce4208
GG		 997 }
998
999 /* Save regulator for cleanup */
1000 pmic->rdev[id] = rdev;
1001 }
1002
1003 /* Start this loop from the id left from previous loop */
1004 for (; id < PALMAS_NUM_REGS; id++) {
32b6d3f6
LD		 1005 if (pdata && pdata->reg_init[id])
1006 reg_init = pdata->reg_init[id];
1007 else
1008 reg_init = NULL;
e5ce4208
GG		 1009
1010 /* Miss out regulators which are not available due
1011 * to alternate functions.
1012 */
1013
1014 /* Register the regulators */
1015 pmic->desc[id].name = palmas_regs_info[id].name;
1016 pmic->desc[id].id = id;
e5ce4208
GG		 1017 pmic->desc[id].type = REGULATOR_VOLTAGE;
1018 pmic->desc[id].owner = THIS_MODULE;
aa07f027
LD		 1019
1020 if (id < PALMAS_REG_REGEN1) {
1021 pmic->desc[id].n_voltages = PALMAS_LDO_NUM_VOLTAGES;
32b6d3f6
LD		 1022 if (reg_init && reg_init->roof_floor)
1023 pmic->desc[id].ops =
1024 &palmas_ops_ext_control_ldo;
1025 else
1026 pmic->desc[id].ops = &palmas_ops_ldo;
aa07f027
LD		 1027 pmic->desc[id].min_uV = 900000;
1028 pmic->desc[id].uV_step = 50000;
1029 pmic->desc[id].linear_min_sel = 1;
087d30e3 1030 pmic->desc[id].enable_time = 500;
aa07f027
LD		 1031 pmic->desc[id].vsel_reg =
1032 PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
4a247a96 1033 palmas_regs_info[id].vsel_addr);
aa07f027
LD		 1034 pmic->desc[id].vsel_mask =
1035 PALMAS_LDO1_VOLTAGE_VSEL_MASK;
1036 pmic->desc[id].enable_reg =
1037 PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
1038 palmas_regs_info[id].ctrl_addr);
1039 pmic->desc[id].enable_mask =
1040 PALMAS_LDO1_CTRL_MODE_ACTIVE;
17c11a76
LD		 1041
1042 /* Check if LDO8 is in tracking mode or not */
1043 if (pdata && (id == PALMAS_REG_LDO8) &&
1044 pdata->enable_ldo8_tracking) {
1045 palmas_enable_ldo8_track(palmas);
3df4a81c 1046 pmic->desc[id].min_uV = 450000;
17c11a76
LD		 1047 pmic->desc[id].uV_step = 25000;
1048 }
087d30e3
LD		 1049
1050 /* LOD6 in vibrator mode will have enable time 2000us */
1051 if (pdata && pdata->ldo6_vibrator &&
1052 (id == PALMAS_REG_LDO6))
1053 pmic->desc[id].enable_time = 2000;
aa07f027
LD		 1054 } else {
1055 pmic->desc[id].n_voltages = 1;
32b6d3f6
LD		 1056 if (reg_init && reg_init->roof_floor)
1057 pmic->desc[id].ops =
1058 &palmas_ops_ext_control_extreg;
1059 else
1060 pmic->desc[id].ops = &palmas_ops_extreg;
aa07f027
LD		 1061 pmic->desc[id].enable_reg =
1062 PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE,
a68de074 1063 palmas_regs_info[id].ctrl_addr);
aa07f027
LD		 1064 pmic->desc[id].enable_mask =
1065 PALMAS_REGEN1_CTRL_MODE_ACTIVE;
1066 }
e5ce4208 1067
a361cd9f 1068 if (pdata)
e5ce4208
GG		 1069 config.init_data = pdata->reg_data[id];
1070 else
1071 config.init_data = NULL;
1072
504382c9 1073 pmic->desc[id].supply_name = palmas_regs_info[id].sname;
a361cd9f
GG		 1074 config.of_node = palmas_matches[id].of_node;
1075
51c86b3e
SK		 1076 rdev = devm_regulator_register(&pdev->dev, &pmic->desc[id],
1077 &config);
e5ce4208
GG		 1078 if (IS_ERR(rdev)) {
1079 dev_err(&pdev->dev,
1080 "failed to register %s regulator\n",
1081 pdev->name);
51c86b3e 1082 return PTR_ERR(rdev);
e5ce4208
GG		 1083 }
1084
1085 /* Save regulator for cleanup */
1086 pmic->rdev[id] = rdev;
1087
1088 /* Initialise sleep/init values from platform data */
a361cd9f 1089 if (pdata) {
e5ce4208
GG		 1090 reg_init = pdata->reg_init[id];
1091 if (reg_init) {
aa07f027
LD		 1092 if (id < PALMAS_REG_REGEN1)
1093 ret = palmas_ldo_init(palmas,
1094 id, reg_init);
1095 else
1096 ret = palmas_extreg_init(palmas,
1097 id, reg_init);
cb2e45e3 1098 if (ret)
51c86b3e 1099 return ret;
e5ce4208
GG		 1100 }
1101 }
1102 }
1103
17c11a76 1104
e5ce4208 1105 return 0;
e5ce4208
GG		 1106}
1107
2449df9f 1108static const struct of_device_id of_palmas_match_tbl[] = {
a361cd9f 1109 { .compatible = "ti,palmas-pmic", },
7be859f7
GG		 1110 { .compatible = "ti,twl6035-pmic", },
1111 { .compatible = "ti,twl6036-pmic", },
1112 { .compatible = "ti,twl6037-pmic", },
1113 { .compatible = "ti,tps65913-pmic", },
1114 { .compatible = "ti,tps65914-pmic", },
1115 { .compatible = "ti,tps80036-pmic", },
b5c46787 1116 { .compatible = "ti,tps659038-pmic", },
a361cd9f
GG		 1117 { /* end */ }
1118};
1119
e5ce4208
GG		 1120static struct platform_driver palmas_driver = {
1121 .driver = {
1122 .name = "palmas-pmic",
a361cd9f 1123 .of_match_table = of_palmas_match_tbl,
e5ce4208
GG		 1124 .owner = THIS_MODULE,
1125 },
bbcf50b1 1126 .probe = palmas_regulators_probe,
e5ce4208
GG		 1127};
1128
1129static int __init palmas_init(void)
1130{
1131 return platform_driver_register(&palmas_driver);
1132}
1133subsys_initcall(palmas_init);
1134
1135static void __exit palmas_exit(void)
1136{
1137 platform_driver_unregister(&palmas_driver);
1138}
1139module_exit(palmas_exit);
1140
1141MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
1142MODULE_DESCRIPTION("Palmas voltage regulator driver");
1143MODULE_LICENSE("GPL");
1144MODULE_ALIAS("platform:palmas-pmic");
a361cd9f 1145MODULE_DEVICE_TABLE(of, of_palmas_match_tbl);
Linux kernel - Deliverables
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