projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
regulator: palmas: preserve modes of rails during enable/disable
[deliverable/linux.git] / drivers / regulator / palmas-regulator.c
CommitLineData
e5ce4208
GG		 1/*
2 * Driver for Regulator part of Palmas PMIC Chips
3 *
7be859f7 4 * Copyright 2011-2013 Texas Instruments Inc.
e5ce4208
GG		 5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/err.h>
19#include <linux/platform_device.h>
20#include <linux/regulator/driver.h>
21#include <linux/regulator/machine.h>
22#include <linux/slab.h>
23#include <linux/regmap.h>
24#include <linux/mfd/palmas.h>
a361cd9f
GG		 25#include <linux/of.h>
26#include <linux/of_platform.h>
27#include <linux/regulator/of_regulator.h>
e5ce4208
GG		 28
29struct regs_info {
30 char *name;
504382c9 31 char *sname;
e5ce4208
GG		 32 u8 vsel_addr;
33 u8 ctrl_addr;
34 u8 tstep_addr;
35};
36
37static const struct regs_info palmas_regs_info[] = {
38 {
39 .name = "SMPS12",
504382c9 40 .sname = "smps1-in",
e5ce4208
GG		 41 .vsel_addr = PALMAS_SMPS12_VOLTAGE,
42 .ctrl_addr = PALMAS_SMPS12_CTRL,
43 .tstep_addr = PALMAS_SMPS12_TSTEP,
44 },
45 {
46 .name = "SMPS123",
504382c9 47 .sname = "smps1-in",
e5ce4208
GG		 48 .vsel_addr = PALMAS_SMPS12_VOLTAGE,
49 .ctrl_addr = PALMAS_SMPS12_CTRL,
50 .tstep_addr = PALMAS_SMPS12_TSTEP,
51 },
52 {
53 .name = "SMPS3",
504382c9 54 .sname = "smps3-in",
e5ce4208
GG		 55 .vsel_addr = PALMAS_SMPS3_VOLTAGE,
56 .ctrl_addr = PALMAS_SMPS3_CTRL,
57 },
58 {
59 .name = "SMPS45",
504382c9 60 .sname = "smps4-in",
e5ce4208
GG		 61 .vsel_addr = PALMAS_SMPS45_VOLTAGE,
62 .ctrl_addr = PALMAS_SMPS45_CTRL,
63 .tstep_addr = PALMAS_SMPS45_TSTEP,
64 },
65 {
66 .name = "SMPS457",
504382c9 67 .sname = "smps4-in",
e5ce4208
GG		 68 .vsel_addr = PALMAS_SMPS45_VOLTAGE,
69 .ctrl_addr = PALMAS_SMPS45_CTRL,
70 .tstep_addr = PALMAS_SMPS45_TSTEP,
71 },
72 {
73 .name = "SMPS6",
504382c9 74 .sname = "smps6-in",
e5ce4208
GG		 75 .vsel_addr = PALMAS_SMPS6_VOLTAGE,
76 .ctrl_addr = PALMAS_SMPS6_CTRL,
77 .tstep_addr = PALMAS_SMPS6_TSTEP,
78 },
79 {
80 .name = "SMPS7",
504382c9 81 .sname = "smps7-in",
e5ce4208
GG		 82 .vsel_addr = PALMAS_SMPS7_VOLTAGE,
83 .ctrl_addr = PALMAS_SMPS7_CTRL,
84 },
85 {
86 .name = "SMPS8",
504382c9 87 .sname = "smps8-in",
e5ce4208
GG		 88 .vsel_addr = PALMAS_SMPS8_VOLTAGE,
89 .ctrl_addr = PALMAS_SMPS8_CTRL,
90 .tstep_addr = PALMAS_SMPS8_TSTEP,
91 },
92 {
93 .name = "SMPS9",
504382c9 94 .sname = "smps9-in",
e5ce4208
GG		 95 .vsel_addr = PALMAS_SMPS9_VOLTAGE,
96 .ctrl_addr = PALMAS_SMPS9_CTRL,
97 },
98 {
99 .name = "SMPS10",
504382c9 100 .sname = "smps10-in",
e5ce4208
GG		 101 },
102 {
103 .name = "LDO1",
504382c9 104 .sname = "ldo1-in",
e5ce4208
GG		 105 .vsel_addr = PALMAS_LDO1_VOLTAGE,
106 .ctrl_addr = PALMAS_LDO1_CTRL,
107 },
108 {
109 .name = "LDO2",
504382c9 110 .sname = "ldo2-in",
e5ce4208
GG		 111 .vsel_addr = PALMAS_LDO2_VOLTAGE,
112 .ctrl_addr = PALMAS_LDO2_CTRL,
113 },
114 {
115 .name = "LDO3",
504382c9 116 .sname = "ldo3-in",
e5ce4208
GG		 117 .vsel_addr = PALMAS_LDO3_VOLTAGE,
118 .ctrl_addr = PALMAS_LDO3_CTRL,
119 },
120 {
121 .name = "LDO4",
504382c9 122 .sname = "ldo4-in",
e5ce4208
GG		 123 .vsel_addr = PALMAS_LDO4_VOLTAGE,
124 .ctrl_addr = PALMAS_LDO4_CTRL,
125 },
126 {
127 .name = "LDO5",
504382c9 128 .sname = "ldo5-in",
e5ce4208
GG		 129 .vsel_addr = PALMAS_LDO5_VOLTAGE,
130 .ctrl_addr = PALMAS_LDO5_CTRL,
131 },
132 {
133 .name = "LDO6",
504382c9 134 .sname = "ldo6-in",
e5ce4208
GG		 135 .vsel_addr = PALMAS_LDO6_VOLTAGE,
136 .ctrl_addr = PALMAS_LDO6_CTRL,
137 },
138 {
139 .name = "LDO7",
504382c9 140 .sname = "ldo7-in",
e5ce4208
GG		 141 .vsel_addr = PALMAS_LDO7_VOLTAGE,
142 .ctrl_addr = PALMAS_LDO7_CTRL,
143 },
144 {
145 .name = "LDO8",
504382c9 146 .sname = "ldo8-in",
e5ce4208
GG		 147 .vsel_addr = PALMAS_LDO8_VOLTAGE,
148 .ctrl_addr = PALMAS_LDO8_CTRL,
149 },
150 {
151 .name = "LDO9",
504382c9 152 .sname = "ldo9-in",
e5ce4208
GG		 153 .vsel_addr = PALMAS_LDO9_VOLTAGE,
154 .ctrl_addr = PALMAS_LDO9_CTRL,
155 },
156 {
157 .name = "LDOLN",
504382c9 158 .sname = "ldoln-in",
e5ce4208
GG		 159 .vsel_addr = PALMAS_LDOLN_VOLTAGE,
160 .ctrl_addr = PALMAS_LDOLN_CTRL,
161 },
162 {
163 .name = "LDOUSB",
504382c9 164 .sname = "ldousb-in",
e5ce4208
GG		 165 .vsel_addr = PALMAS_LDOUSB_VOLTAGE,
166 .ctrl_addr = PALMAS_LDOUSB_CTRL,
167 },
aa07f027
LD		 168 {
169 .name = "REGEN1",
170 .ctrl_addr = PALMAS_REGEN1_CTRL,
171 },
172 {
173 .name = "REGEN2",
174 .ctrl_addr = PALMAS_REGEN2_CTRL,
175 },
176 {
177 .name = "REGEN3",
178 .ctrl_addr = PALMAS_REGEN3_CTRL,
179 },
180 {
181 .name = "SYSEN1",
182 .ctrl_addr = PALMAS_SYSEN1_CTRL,
183 },
184 {
185 .name = "SYSEN2",
186 .ctrl_addr = PALMAS_SYSEN2_CTRL,
187 },
e5ce4208
GG		 188};
189
28d1e8cd
LD		 190static unsigned int palmas_smps_ramp_delay[4] = {0, 10000, 5000, 2500};
191
e5ce4208
GG		 192#define SMPS_CTRL_MODE_OFF 0x00
193#define SMPS_CTRL_MODE_ON 0x01
194#define SMPS_CTRL_MODE_ECO 0x02
195#define SMPS_CTRL_MODE_PWM 0x03
196
197/* These values are derived from the data sheet. And are the number of steps
198 * where there is a voltage change, the ranges at beginning and end of register
199 * max/min values where there are no change are ommitted.
200 *
201 * So they are basically (maxV-minV)/stepV
202 */
203#define PALMAS_SMPS_NUM_VOLTAGES 116
204#define PALMAS_SMPS10_NUM_VOLTAGES 2
205#define PALMAS_LDO_NUM_VOLTAGES 50
206
207#define SMPS10_VSEL (1<<3)
208#define SMPS10_BOOST_EN (1<<2)
209#define SMPS10_BYPASS_EN (1<<1)
210#define SMPS10_SWITCH_EN (1<<0)
211
212#define REGULATOR_SLAVE 0
213
214static int palmas_smps_read(struct palmas *palmas, unsigned int reg,
215 unsigned int *dest)
216{
217 unsigned int addr;
218
219 addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg);
220
221 return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest);
222}
223
224static int palmas_smps_write(struct palmas *palmas, unsigned int reg,
225 unsigned int value)
226{
227 unsigned int addr;
228
229 addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg);
230
231 return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value);
232}
233
234static int palmas_ldo_read(struct palmas *palmas, unsigned int reg,
235 unsigned int *dest)
236{
237 unsigned int addr;
238
239 addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg);
240
241 return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest);
242}
243
244static int palmas_ldo_write(struct palmas *palmas, unsigned int reg,
245 unsigned int value)
246{
247 unsigned int addr;
248
249 addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg);
250
251 return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value);
252}
253
254static int palmas_is_enabled_smps(struct regulator_dev *dev)
255{
256 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
257 int id = rdev_get_id(dev);
258 unsigned int reg;
259
260 palmas_smps_read(pmic->palmas, palmas_regs_info[id].ctrl_addr, &reg);
261
262 reg &= PALMAS_SMPS12_CTRL_STATUS_MASK;
263 reg >>= PALMAS_SMPS12_CTRL_STATUS_SHIFT;
264
265 return !!(reg);
266}
267
268static int palmas_enable_smps(struct regulator_dev *dev)
269{
270 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
271 int id = rdev_get_id(dev);
272 unsigned int reg;
273
274 palmas_smps_read(pmic->palmas, palmas_regs_info[id].ctrl_addr, &reg);
275
276 reg &= ~PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
51d3a0c9
LD		 277 if (pmic->current_reg_mode[id])
278 reg |= pmic->current_reg_mode[id];
279 else
280 reg |= SMPS_CTRL_MODE_ON;
e5ce4208
GG		 281
282 palmas_smps_write(pmic->palmas, palmas_regs_info[id].ctrl_addr, reg);
283
284 return 0;
285}
286
287static int palmas_disable_smps(struct regulator_dev *dev)
288{
289 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
290 int id = rdev_get_id(dev);
291 unsigned int reg;
292
293 palmas_smps_read(pmic->palmas, palmas_regs_info[id].ctrl_addr, &reg);
294
295 reg &= ~PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
296
297 palmas_smps_write(pmic->palmas, palmas_regs_info[id].ctrl_addr, reg);
298
299 return 0;
300}
301
e5ce4208
GG		 302static int palmas_set_mode_smps(struct regulator_dev *dev, unsigned int mode)
303{
304 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
305 int id = rdev_get_id(dev);
306 unsigned int reg;
51d3a0c9 307 bool rail_enable = true;
e5ce4208
GG		 308
309 palmas_smps_read(pmic->palmas, palmas_regs_info[id].ctrl_addr, &reg);
999f0c7c 310 reg &= ~PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
e5ce4208 311
51d3a0c9
LD		 312 if (reg == SMPS_CTRL_MODE_OFF)
313 rail_enable = false;
314
e5ce4208
GG		 315 switch (mode) {
316 case REGULATOR_MODE_NORMAL:
317 reg |= SMPS_CTRL_MODE_ON;
318 break;
319 case REGULATOR_MODE_IDLE:
320 reg |= SMPS_CTRL_MODE_ECO;
321 break;
322 case REGULATOR_MODE_FAST:
323 reg |= SMPS_CTRL_MODE_PWM;
324 break;
325 default:
326 return -EINVAL;
327 }
e5ce4208 328
51d3a0c9
LD		 329 pmic->current_reg_mode[id] = reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
330 if (rail_enable)
331 palmas_smps_write(pmic->palmas,
332 palmas_regs_info[id].ctrl_addr, reg);
e5ce4208
GG		 333 return 0;
334}
335
336static unsigned int palmas_get_mode_smps(struct regulator_dev *dev)
337{
338 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
339 int id = rdev_get_id(dev);
340 unsigned int reg;
341
51d3a0c9 342 reg = pmic->current_reg_mode[id] & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
e5ce4208
GG		 343
344 switch (reg) {
345 case SMPS_CTRL_MODE_ON:
346 return REGULATOR_MODE_NORMAL;
347 case SMPS_CTRL_MODE_ECO:
348 return REGULATOR_MODE_IDLE;
349 case SMPS_CTRL_MODE_PWM:
350 return REGULATOR_MODE_FAST;
351 }
352
353 return 0;
354}
355
356static int palmas_list_voltage_smps(struct regulator_dev *dev,
357 unsigned selector)
358{
359 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
360 int id = rdev_get_id(dev);
361 int mult = 1;
362
e5ce4208
GG		 363 /* Read the multiplier set in VSEL register to return
364 * the correct voltage.
365 */
366 if (pmic->range[id])
367 mult = 2;
368
ad02e846
AL		 369 if (selector == 0)
370 return 0;
371 else if (selector < 6)
372 return 500000 * mult;
373 else
374 /* Voltage is linear mapping starting from selector 6,
375 * volt = (0.49V + ((selector - 5) * 0.01V)) * RANGE
376 * RANGE is either x1 or x2
377 */
378 return (490000 + ((selector - 5) * 10000)) * mult;
e5ce4208
GG		 379}
380
381static int palmas_map_voltage_smps(struct regulator_dev *rdev,
382 int min_uV, int max_uV)
383{
8a165df7
AL		 384 struct palmas_pmic *pmic = rdev_get_drvdata(rdev);
385 int id = rdev_get_id(rdev);
e5ce4208
GG		 386 int ret, voltage;
387
8a165df7
AL		 388 if (min_uV == 0)
389 return 0;
390
391 if (pmic->range[id]) { /* RANGE is x2 */
392 if (min_uV < 1000000)
393 min_uV = 1000000;
ad02e846 394 ret = DIV_ROUND_UP(min_uV - 1000000, 20000) + 6;
8a165df7
AL		 395 } else { /* RANGE is x1 */
396 if (min_uV < 500000)
397 min_uV = 500000;
ad02e846 398 ret = DIV_ROUND_UP(min_uV - 500000, 10000) + 6;
8a165df7 399 }
e5ce4208
GG		 400
401 /* Map back into a voltage to verify we're still in bounds */
402 voltage = palmas_list_voltage_smps(rdev, ret);
403 if (voltage < min_uV || voltage > max_uV)
404 return -EINVAL;
405
406 return ret;
407}
408
28d1e8cd
LD		 409static int palma_smps_set_voltage_smps_time_sel(struct regulator_dev *rdev,
410 unsigned int old_selector, unsigned int new_selector)
411{
412 struct palmas_pmic *pmic = rdev_get_drvdata(rdev);
413 int id = rdev_get_id(rdev);
414 int old_uv, new_uv;
415 unsigned int ramp_delay = pmic->ramp_delay[id];
416
417 if (!ramp_delay)
418 return 0;
419
420 old_uv = palmas_list_voltage_smps(rdev, old_selector);
421 if (old_uv < 0)
422 return old_uv;
423
424 new_uv = palmas_list_voltage_smps(rdev, new_selector);
425 if (new_uv < 0)
426 return new_uv;
427
428 return DIV_ROUND_UP(abs(old_uv - new_uv), ramp_delay);
429}
430
431static int palmas_smps_set_ramp_delay(struct regulator_dev *rdev,
432 int ramp_delay)
433{
434 struct palmas_pmic *pmic = rdev_get_drvdata(rdev);
435 int id = rdev_get_id(rdev);
436 unsigned int reg = 0;
437 unsigned int addr = palmas_regs_info[id].tstep_addr;
438 int ret;
439
440 if (ramp_delay <= 0)
441 reg = 0;
442 else if (ramp_delay < 2500)
443 reg = 3;
444 else if (ramp_delay < 5000)
445 reg = 2;
446 else
447 reg = 1;
448
449 ret = palmas_smps_write(pmic->palmas, addr, reg);
450 if (ret < 0) {
451 dev_err(pmic->palmas->dev, "TSTEP write failed: %d\n", ret);
452 return ret;
453 }
454
455 pmic->ramp_delay[id] = palmas_smps_ramp_delay[reg];
456 return ret;
457}
458
e5ce4208
GG		 459static struct regulator_ops palmas_ops_smps = {
460 .is_enabled = palmas_is_enabled_smps,
461 .enable = palmas_enable_smps,
462 .disable = palmas_disable_smps,
463 .set_mode = palmas_set_mode_smps,
464 .get_mode = palmas_get_mode_smps,
bdc4baac
AL		 465 .get_voltage_sel = regulator_get_voltage_sel_regmap,
466 .set_voltage_sel = regulator_set_voltage_sel_regmap,
e5ce4208
GG		 467 .list_voltage = palmas_list_voltage_smps,
468 .map_voltage = palmas_map_voltage_smps,
28d1e8cd
LD		 469 .set_voltage_time_sel = palma_smps_set_voltage_smps_time_sel,
470 .set_ramp_delay = palmas_smps_set_ramp_delay,
e5ce4208
GG		 471};
472
e5ce4208
GG		 473static struct regulator_ops palmas_ops_smps10 = {
474 .is_enabled = regulator_is_enabled_regmap,
475 .enable = regulator_enable_regmap,
476 .disable = regulator_disable_regmap,
477 .get_voltage_sel = regulator_get_voltage_sel_regmap,
478 .set_voltage_sel = regulator_set_voltage_sel_regmap,
8029a006
AL		 479 .list_voltage = regulator_list_voltage_linear,
480 .map_voltage = regulator_map_voltage_linear,
e5ce4208
GG		 481};
482
483static int palmas_is_enabled_ldo(struct regulator_dev *dev)
484{
485 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
486 int id = rdev_get_id(dev);
487 unsigned int reg;
488
489 palmas_ldo_read(pmic->palmas, palmas_regs_info[id].ctrl_addr, &reg);
490
491 reg &= PALMAS_LDO1_CTRL_STATUS;
492
493 return !!(reg);
494}
495
e5ce4208
GG		 496static struct regulator_ops palmas_ops_ldo = {
497 .is_enabled = palmas_is_enabled_ldo,
498 .enable = regulator_enable_regmap,
499 .disable = regulator_disable_regmap,
4a247a96
AL		 500 .get_voltage_sel = regulator_get_voltage_sel_regmap,
501 .set_voltage_sel = regulator_set_voltage_sel_regmap,
9119ff6a
AL		 502 .list_voltage = regulator_list_voltage_linear,
503 .map_voltage = regulator_map_voltage_linear,
e5ce4208
GG		 504};
505
aa07f027
LD		 506static struct regulator_ops palmas_ops_extreg = {
507 .is_enabled = regulator_is_enabled_regmap,
508 .enable = regulator_enable_regmap,
509 .disable = regulator_disable_regmap,
510};
511
e5ce4208
GG		 512/*
513 * setup the hardware based sleep configuration of the SMPS/LDO regulators
514 * from the platform data. This is different to the software based control
515 * supported by the regulator framework as it is controlled by toggling
516 * pins on the PMIC such as PREQ, SYSEN, ...
517 */
518static int palmas_smps_init(struct palmas *palmas, int id,
519 struct palmas_reg_init *reg_init)
520{
521 unsigned int reg;
522 unsigned int addr;
523 int ret;
524
525 addr = palmas_regs_info[id].ctrl_addr;
526
527 ret = palmas_smps_read(palmas, addr, &reg);
528 if (ret)
529 return ret;
530
fedd89b1
AL		 531 switch (id) {
532 case PALMAS_REG_SMPS10:
30590d04
LD		 533 reg &= ~PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK;
534 if (reg_init->mode_sleep)
fedd89b1
AL		 535 reg |= reg_init->mode_sleep <<
536 PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT;
fedd89b1
AL		 537 break;
538 default:
e5ce4208
GG		 539 if (reg_init->warm_reset)
540 reg |= PALMAS_SMPS12_CTRL_WR_S;
30590d04
LD		 541 else
542 reg &= ~PALMAS_SMPS12_CTRL_WR_S;
e5ce4208
GG		 543
544 if (reg_init->roof_floor)
545 reg |= PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN;
30590d04
LD		 546 else
547 reg &= ~PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN;
e5ce4208 548
30590d04
LD		 549 reg &= ~PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK;
550 if (reg_init->mode_sleep)
e5ce4208
GG		 551 reg |= reg_init->mode_sleep <<
552 PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT;
e5ce4208 553 }
fedd89b1 554
e5ce4208
GG		 555 ret = palmas_smps_write(palmas, addr, reg);
556 if (ret)
557 return ret;
558
e5ce4208
GG		 559 if (palmas_regs_info[id].vsel_addr && reg_init->vsel) {
560 addr = palmas_regs_info[id].vsel_addr;
561
562 reg = reg_init->vsel;
563
564 ret = palmas_smps_write(palmas, addr, reg);
565 if (ret)
566 return ret;
567 }
568
569
570 return 0;
571}
572
573static int palmas_ldo_init(struct palmas *palmas, int id,
574 struct palmas_reg_init *reg_init)
575{
576 unsigned int reg;
577 unsigned int addr;
578 int ret;
579
580 addr = palmas_regs_info[id].ctrl_addr;
581
2735daeb 582 ret = palmas_ldo_read(palmas, addr, &reg);
e5ce4208
GG		 583 if (ret)
584 return ret;
585
586 if (reg_init->warm_reset)
587 reg |= PALMAS_LDO1_CTRL_WR_S;
30590d04
LD		 588 else
589 reg &= ~PALMAS_LDO1_CTRL_WR_S;
e5ce4208
GG		 590
591 if (reg_init->mode_sleep)
592 reg |= PALMAS_LDO1_CTRL_MODE_SLEEP;
30590d04
LD		 593 else
594 reg &= ~PALMAS_LDO1_CTRL_MODE_SLEEP;
e5ce4208 595
2735daeb 596 ret = palmas_ldo_write(palmas, addr, reg);
e5ce4208
GG		 597 if (ret)
598 return ret;
599
600 return 0;
601}
602
aa07f027
LD		 603static int palmas_extreg_init(struct palmas *palmas, int id,
604 struct palmas_reg_init *reg_init)
605{
606 unsigned int addr;
607 int ret;
608 unsigned int val = 0;
609
610 addr = palmas_regs_info[id].ctrl_addr;
611
612 if (reg_init->mode_sleep)
613 val = PALMAS_REGEN1_CTRL_MODE_SLEEP;
614
615 ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
616 addr, PALMAS_REGEN1_CTRL_MODE_SLEEP, val);
617 if (ret < 0) {
618 dev_err(palmas->dev, "Resource reg 0x%02x update failed %d\n",
619 addr, ret);
620 return ret;
621 }
622 return 0;
623}
624
17c11a76
LD		 625static void palmas_enable_ldo8_track(struct palmas *palmas)
626{
627 unsigned int reg;
628 unsigned int addr;
629 int ret;
630
631 addr = palmas_regs_info[PALMAS_REG_LDO8].ctrl_addr;
632
633 ret = palmas_ldo_read(palmas, addr, &reg);
634 if (ret) {
635 dev_err(palmas->dev, "Error in reading ldo8 control reg\n");
636 return;
637 }
638
639 reg |= PALMAS_LDO8_CTRL_LDO_TRACKING_EN;
640 ret = palmas_ldo_write(palmas, addr, reg);
641 if (ret < 0) {
642 dev_err(palmas->dev, "Error in enabling tracking mode\n");
643 return;
644 }
645 /*
646 * When SMPS45 is set to off and LDO8 tracking is enabled, the LDO8
647 * output is defined by the LDO8_VOLTAGE.VSEL register divided by two,
648 * and can be set from 0.45 to 1.65 V.
649 */
650 addr = palmas_regs_info[PALMAS_REG_LDO8].vsel_addr;
651 ret = palmas_ldo_read(palmas, addr, &reg);
652 if (ret) {
653 dev_err(palmas->dev, "Error in reading ldo8 voltage reg\n");
654 return;
655 }
656
657 reg = (reg << 1) & PALMAS_LDO8_VOLTAGE_VSEL_MASK;
658 ret = palmas_ldo_write(palmas, addr, reg);
659 if (ret < 0)
660 dev_err(palmas->dev, "Error in setting ldo8 voltage reg\n");
661
662 return;
663}
664
a361cd9f
GG		 665static struct of_regulator_match palmas_matches[] = {
666 { .name = "smps12", },
667 { .name = "smps123", },
668 { .name = "smps3", },
669 { .name = "smps45", },
670 { .name = "smps457", },
671 { .name = "smps6", },
672 { .name = "smps7", },
673 { .name = "smps8", },
674 { .name = "smps9", },
675 { .name = "smps10", },
676 { .name = "ldo1", },
677 { .name = "ldo2", },
678 { .name = "ldo3", },
679 { .name = "ldo4", },
680 { .name = "ldo5", },
681 { .name = "ldo6", },
682 { .name = "ldo7", },
683 { .name = "ldo8", },
684 { .name = "ldo9", },
685 { .name = "ldoln", },
686 { .name = "ldousb", },
aa07f027
LD		 687 { .name = "regen1", },
688 { .name = "regen2", },
689 { .name = "regen3", },
690 { .name = "sysen1", },
691 { .name = "sysen2", },
a361cd9f
GG		 692};
693
a5023574 694static void palmas_dt_to_pdata(struct device *dev,
a361cd9f
GG		 695 struct device_node *node,
696 struct palmas_pmic_platform_data *pdata)
697{
698 struct device_node *regulators;
699 u32 prop;
700 int idx, ret;
701
c92f5dd2 702 node = of_node_get(node);
a361cd9f
GG		 703 regulators = of_find_node_by_name(node, "regulators");
704 if (!regulators) {
705 dev_info(dev, "regulator node not found\n");
706 return;
707 }
708
709 ret = of_regulator_match(dev, regulators, palmas_matches,
710 PALMAS_NUM_REGS);
c92f5dd2 711 of_node_put(regulators);
a361cd9f
GG		 712 if (ret < 0) {
713 dev_err(dev, "Error parsing regulator init data: %d\n", ret);
714 return;
715 }
716
717 for (idx = 0; idx < PALMAS_NUM_REGS; idx++) {
718 if (!palmas_matches[idx].init_data ||
719 !palmas_matches[idx].of_node)
720 continue;
721
722 pdata->reg_data[idx] = palmas_matches[idx].init_data;
723
724 pdata->reg_init[idx] = devm_kzalloc(dev,
725 sizeof(struct palmas_reg_init), GFP_KERNEL);
726
7be859f7 727 pdata->reg_init[idx]->warm_reset =
71f2146f
AL		 728 of_property_read_bool(palmas_matches[idx].of_node,
729 "ti,warm-reset");
a361cd9f 730
7be859f7
GG		 731 pdata->reg_init[idx]->roof_floor =
732 of_property_read_bool(palmas_matches[idx].of_node,
733 "ti,roof-floor");
a361cd9f
GG		 734
735 ret = of_property_read_u32(palmas_matches[idx].of_node,
3c870e3f 736 "ti,mode-sleep", &prop);
a361cd9f
GG		 737 if (!ret)
738 pdata->reg_init[idx]->mode_sleep = prop;
739
7be859f7
GG		 740 ret = of_property_read_bool(palmas_matches[idx].of_node,
741 "ti,smps-range");
742 if (ret)
743 pdata->reg_init[idx]->vsel =
744 PALMAS_SMPS12_VOLTAGE_RANGE;
17c11a76
LD		 745
746 if (idx == PALMAS_REG_LDO8)
747 pdata->enable_ldo8_tracking = of_property_read_bool(
748 palmas_matches[idx].of_node,
749 "ti,enable-ldo8-tracking");
a361cd9f
GG		 750 }
751
7be859f7 752 pdata->ldo6_vibrator = of_property_read_bool(node, "ti,ldo6-vibrator");
a361cd9f
GG		 753}
754
755
bbcf50b1 756static int palmas_regulators_probe(struct platform_device *pdev)
e5ce4208
GG		 757{
758 struct palmas *palmas = dev_get_drvdata(pdev->dev.parent);
759 struct palmas_pmic_platform_data *pdata = pdev->dev.platform_data;
a361cd9f 760 struct device_node *node = pdev->dev.of_node;
e5ce4208
GG		 761 struct regulator_dev *rdev;
762 struct regulator_config config = { };
763 struct palmas_pmic *pmic;
764 struct palmas_reg_init *reg_init;
765 int id = 0, ret;
766 unsigned int addr, reg;
767
a361cd9f
GG		 768 if (node && !pdata) {
769 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
770
771 if (!pdata)
772 return -ENOMEM;
773
774 palmas_dt_to_pdata(&pdev->dev, node, pdata);
775 }
e5ce4208
GG		 776
777 pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
778 if (!pmic)
779 return -ENOMEM;
780
781 pmic->dev = &pdev->dev;
782 pmic->palmas = palmas;
783 palmas->pmic = pmic;
784 platform_set_drvdata(pdev, pmic);
785
786 ret = palmas_smps_read(palmas, PALMAS_SMPS_CTRL, &reg);
787 if (ret)
1c9d2d71 788 return ret;
e5ce4208
GG		 789
790 if (reg & PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN)
791 pmic->smps123 = 1;
792
793 if (reg & PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN)
794 pmic->smps457 = 1;
795
796 config.regmap = palmas->regmap[REGULATOR_SLAVE];
797 config.dev = &pdev->dev;
798 config.driver_data = pmic;
799
800 for (id = 0; id < PALMAS_REG_LDO1; id++) {
28d1e8cd 801 bool ramp_delay_support = false;
e5ce4208
GG		 802
803 /*
804 * Miss out regulators which are not available due
805 * to slaving configurations.
806 */
807 switch (id) {
808 case PALMAS_REG_SMPS12:
809 case PALMAS_REG_SMPS3:
810 if (pmic->smps123)
811 continue;
28d1e8cd
LD		 812 if (id == PALMAS_REG_SMPS12)
813 ramp_delay_support = true;
e5ce4208
GG		 814 break;
815 case PALMAS_REG_SMPS123:
816 if (!pmic->smps123)
817 continue;
28d1e8cd 818 ramp_delay_support = true;
e5ce4208
GG		 819 break;
820 case PALMAS_REG_SMPS45:
821 case PALMAS_REG_SMPS7:
822 if (pmic->smps457)
823 continue;
28d1e8cd
LD		 824 if (id == PALMAS_REG_SMPS45)
825 ramp_delay_support = true;
e5ce4208
GG		 826 break;
827 case PALMAS_REG_SMPS457:
828 if (!pmic->smps457)
829 continue;
28d1e8cd
LD		 830 ramp_delay_support = true;
831 break;
832 }
833
834 if ((id == PALMAS_REG_SMPS6) && (id == PALMAS_REG_SMPS8))
835 ramp_delay_support = true;
836
837 if (ramp_delay_support) {
838 addr = palmas_regs_info[id].tstep_addr;
839 ret = palmas_smps_read(pmic->palmas, addr, &reg);
840 if (ret < 0) {
841 dev_err(&pdev->dev,
842 "reading TSTEP reg failed: %d\n", ret);
843 goto err_unregister_regulator;
844 }
845 pmic->desc[id].ramp_delay =
846 palmas_smps_ramp_delay[reg & 0x3];
847 pmic->ramp_delay[id] = pmic->desc[id].ramp_delay;
e5ce4208
GG		 848 }
849
bdc4baac
AL		 850 /* Initialise sleep/init values from platform data */
851 if (pdata && pdata->reg_init[id]) {
852 reg_init = pdata->reg_init[id];
853 ret = palmas_smps_init(palmas, id, reg_init);
854 if (ret)
855 goto err_unregister_regulator;
856 }
857
e5ce4208
GG		 858 /* Register the regulators */
859 pmic->desc[id].name = palmas_regs_info[id].name;
860 pmic->desc[id].id = id;
861
fedd89b1
AL		 862 switch (id) {
863 case PALMAS_REG_SMPS10:
e5ce4208
GG		 864 pmic->desc[id].n_voltages = PALMAS_SMPS10_NUM_VOLTAGES;
865 pmic->desc[id].ops = &palmas_ops_smps10;
12565b16
AL		 866 pmic->desc[id].vsel_reg =
867 PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
868 PALMAS_SMPS10_CTRL);
e5ce4208 869 pmic->desc[id].vsel_mask = SMPS10_VSEL;
a68de074
GG		 870 pmic->desc[id].enable_reg =
871 PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
872 PALMAS_SMPS10_STATUS);
e5ce4208 873 pmic->desc[id].enable_mask = SMPS10_BOOST_EN;
8029a006
AL		 874 pmic->desc[id].min_uV = 3750000;
875 pmic->desc[id].uV_step = 1250000;
fedd89b1
AL		 876 break;
877 default:
bdc4baac
AL		 878 /*
879 * Read and store the RANGE bit for later use
880 * This must be done before regulator is probed,
51d3a0c9
LD		 881 * otherwise we error in probe with unsupportable
882 * ranges. Read the current smps mode for later use.
bdc4baac 883 */
e5ce4208
GG		 884 addr = palmas_regs_info[id].vsel_addr;
885
886 ret = palmas_smps_read(pmic->palmas, addr, &reg);
887 if (ret)
888 goto err_unregister_regulator;
889 if (reg & PALMAS_SMPS12_VOLTAGE_RANGE)
890 pmic->range[id] = 1;
bdc4baac
AL		 891
892 pmic->desc[id].ops = &palmas_ops_smps;
893 pmic->desc[id].n_voltages = PALMAS_SMPS_NUM_VOLTAGES;
894 pmic->desc[id].vsel_reg =
895 PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
896 palmas_regs_info[id].vsel_addr);
897 pmic->desc[id].vsel_mask =
898 PALMAS_SMPS12_VOLTAGE_VSEL_MASK;
51d3a0c9
LD		 899
900 /* Read the smps mode for later use. */
901 addr = palmas_regs_info[id].ctrl_addr;
902 ret = palmas_smps_read(pmic->palmas, addr, &reg);
903 if (ret)
904 goto err_unregister_regulator;
905 pmic->current_reg_mode[id] = reg &
906 PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
e5ce4208
GG		 907 }
908
bdc4baac
AL		 909 pmic->desc[id].type = REGULATOR_VOLTAGE;
910 pmic->desc[id].owner = THIS_MODULE;
911
a361cd9f 912 if (pdata)
e5ce4208
GG		 913 config.init_data = pdata->reg_data[id];
914 else
915 config.init_data = NULL;
916
504382c9 917 pmic->desc[id].supply_name = palmas_regs_info[id].sname;
a361cd9f
GG		 918 config.of_node = palmas_matches[id].of_node;
919
e5ce4208
GG		 920 rdev = regulator_register(&pmic->desc[id], &config);
921 if (IS_ERR(rdev)) {
922 dev_err(&pdev->dev,
923 "failed to register %s regulator\n",
924 pdev->name);
925 ret = PTR_ERR(rdev);
926 goto err_unregister_regulator;
927 }
928
929 /* Save regulator for cleanup */
930 pmic->rdev[id] = rdev;
931 }
932
933 /* Start this loop from the id left from previous loop */
934 for (; id < PALMAS_NUM_REGS; id++) {
935
936 /* Miss out regulators which are not available due
937 * to alternate functions.
938 */
939
940 /* Register the regulators */
941 pmic->desc[id].name = palmas_regs_info[id].name;
942 pmic->desc[id].id = id;
e5ce4208
GG		 943 pmic->desc[id].type = REGULATOR_VOLTAGE;
944 pmic->desc[id].owner = THIS_MODULE;
aa07f027
LD		 945
946 if (id < PALMAS_REG_REGEN1) {
947 pmic->desc[id].n_voltages = PALMAS_LDO_NUM_VOLTAGES;
948 pmic->desc[id].ops = &palmas_ops_ldo;
949 pmic->desc[id].min_uV = 900000;
950 pmic->desc[id].uV_step = 50000;
951 pmic->desc[id].linear_min_sel = 1;
952 pmic->desc[id].vsel_reg =
953 PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
4a247a96 954 palmas_regs_info[id].vsel_addr);
aa07f027
LD		 955 pmic->desc[id].vsel_mask =
956 PALMAS_LDO1_VOLTAGE_VSEL_MASK;
957 pmic->desc[id].enable_reg =
958 PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
959 palmas_regs_info[id].ctrl_addr);
960 pmic->desc[id].enable_mask =
961 PALMAS_LDO1_CTRL_MODE_ACTIVE;
17c11a76
LD		 962
963 /* Check if LDO8 is in tracking mode or not */
964 if (pdata && (id == PALMAS_REG_LDO8) &&
965 pdata->enable_ldo8_tracking) {
966 palmas_enable_ldo8_track(palmas);
967 pmic->desc[id].uV_step = 25000;
968 }
aa07f027
LD		 969 } else {
970 pmic->desc[id].n_voltages = 1;
971 pmic->desc[id].ops = &palmas_ops_extreg;
972 pmic->desc[id].enable_reg =
973 PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE,
a68de074 974 palmas_regs_info[id].ctrl_addr);
aa07f027
LD		 975 pmic->desc[id].enable_mask =
976 PALMAS_REGEN1_CTRL_MODE_ACTIVE;
977 }
e5ce4208 978
a361cd9f 979 if (pdata)
e5ce4208
GG		 980 config.init_data = pdata->reg_data[id];
981 else
982 config.init_data = NULL;
983
504382c9 984 pmic->desc[id].supply_name = palmas_regs_info[id].sname;
a361cd9f
GG		 985 config.of_node = palmas_matches[id].of_node;
986
e5ce4208
GG		 987 rdev = regulator_register(&pmic->desc[id], &config);
988 if (IS_ERR(rdev)) {
989 dev_err(&pdev->dev,
990 "failed to register %s regulator\n",
991 pdev->name);
992 ret = PTR_ERR(rdev);
993 goto err_unregister_regulator;
994 }
995
996 /* Save regulator for cleanup */
997 pmic->rdev[id] = rdev;
998
999 /* Initialise sleep/init values from platform data */
a361cd9f 1000 if (pdata) {
e5ce4208
GG		 1001 reg_init = pdata->reg_init[id];
1002 if (reg_init) {
aa07f027
LD		 1003 if (id < PALMAS_REG_REGEN1)
1004 ret = palmas_ldo_init(palmas,
1005 id, reg_init);
1006 else
1007 ret = palmas_extreg_init(palmas,
1008 id, reg_init);
1c9d2d71
AL		 1009 if (ret) {
1010 regulator_unregister(pmic->rdev[id]);
e5ce4208 1011 goto err_unregister_regulator;
1c9d2d71 1012 }
e5ce4208
GG		 1013 }
1014 }
1015 }
1016
17c11a76 1017
e5ce4208
GG		 1018 return 0;
1019
1020err_unregister_regulator:
1021 while (--id >= 0)
1022 regulator_unregister(pmic->rdev[id]);
e5ce4208
GG		 1023 return ret;
1024}
1025
bbcf50b1 1026static int palmas_regulators_remove(struct platform_device *pdev)
e5ce4208
GG		 1027{
1028 struct palmas_pmic *pmic = platform_get_drvdata(pdev);
1029 int id;
1030
1031 for (id = 0; id < PALMAS_NUM_REGS; id++)
1032 regulator_unregister(pmic->rdev[id]);
e5ce4208
GG		 1033 return 0;
1034}
1035
3d68dfe3 1036static struct of_device_id of_palmas_match_tbl[] = {
a361cd9f 1037 { .compatible = "ti,palmas-pmic", },
7be859f7
GG		 1038 { .compatible = "ti,twl6035-pmic", },
1039 { .compatible = "ti,twl6036-pmic", },
1040 { .compatible = "ti,twl6037-pmic", },
1041 { .compatible = "ti,tps65913-pmic", },
1042 { .compatible = "ti,tps65914-pmic", },
1043 { .compatible = "ti,tps80036-pmic", },
a361cd9f
GG		 1044 { /* end */ }
1045};
1046
e5ce4208
GG		 1047static struct platform_driver palmas_driver = {
1048 .driver = {
1049 .name = "palmas-pmic",
a361cd9f 1050 .of_match_table = of_palmas_match_tbl,
e5ce4208
GG		 1051 .owner = THIS_MODULE,
1052 },
bbcf50b1
LD		 1053 .probe = palmas_regulators_probe,
1054 .remove = palmas_regulators_remove,
e5ce4208
GG		 1055};
1056
1057static int __init palmas_init(void)
1058{
1059 return platform_driver_register(&palmas_driver);
1060}
1061subsys_initcall(palmas_init);
1062
1063static void __exit palmas_exit(void)
1064{
1065 platform_driver_unregister(&palmas_driver);
1066}
1067module_exit(palmas_exit);
1068
1069MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
1070MODULE_DESCRIPTION("Palmas voltage regulator driver");
1071MODULE_LICENSE("GPL");
1072MODULE_ALIAS("platform:palmas-pmic");
a361cd9f 1073MODULE_DEVICE_TABLE(of, of_palmas_match_tbl);
Linux kernel - Deliverables
This page took 0.115638 seconds and 5 git commands to generate.