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regulator: palmas: Rename reg_info to palmas_reg_info
[deliverable/linux.git] / drivers / regulator / palmas-regulator.c
CommitLineData
e5ce4208
GG		 1/*
2 * Driver for Regulator part of Palmas PMIC Chips
3 *
7be859f7 4 * Copyright 2011-2013 Texas Instruments Inc.
e5ce4208
GG		 5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
a7dddf27 7 * Author: Ian Lartey <ian@slimlogic.co.uk>
e5ce4208
GG		 8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/err.h>
20#include <linux/platform_device.h>
21#include <linux/regulator/driver.h>
22#include <linux/regulator/machine.h>
23#include <linux/slab.h>
24#include <linux/regmap.h>
25#include <linux/mfd/palmas.h>
a361cd9f
GG		 26#include <linux/of.h>
27#include <linux/of_platform.h>
28#include <linux/regulator/of_regulator.h>
e5ce4208 29
dbabd624 30static const struct regulator_linear_range smps_low_ranges[] = {
6b7f2d82 31 REGULATOR_LINEAR_RANGE(0, 0x0, 0x0, 0),
dbabd624
K		 32 REGULATOR_LINEAR_RANGE(500000, 0x1, 0x6, 0),
33 REGULATOR_LINEAR_RANGE(510000, 0x7, 0x79, 10000),
34 REGULATOR_LINEAR_RANGE(1650000, 0x7A, 0x7f, 0),
35};
36
37static const struct regulator_linear_range smps_high_ranges[] = {
6b7f2d82 38 REGULATOR_LINEAR_RANGE(0, 0x0, 0x0, 0),
dbabd624
K		 39 REGULATOR_LINEAR_RANGE(1000000, 0x1, 0x6, 0),
40 REGULATOR_LINEAR_RANGE(1020000, 0x7, 0x79, 20000),
41 REGULATOR_LINEAR_RANGE(3300000, 0x7A, 0x7f, 0),
42};
43
e7cf34ef 44static struct palmas_regs_info palmas_regs_info[] = {
e5ce4208
GG		 45 {
46 .name = "SMPS12",
504382c9 47 .sname = "smps1-in",
e5ce4208
GG		 48 .vsel_addr = PALMAS_SMPS12_VOLTAGE,
49 .ctrl_addr = PALMAS_SMPS12_CTRL,
50 .tstep_addr = PALMAS_SMPS12_TSTEP,
32b6d3f6 51 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
e5ce4208
GG		 52 },
53 {
54 .name = "SMPS123",
504382c9 55 .sname = "smps1-in",
e5ce4208
GG		 56 .vsel_addr = PALMAS_SMPS12_VOLTAGE,
57 .ctrl_addr = PALMAS_SMPS12_CTRL,
58 .tstep_addr = PALMAS_SMPS12_TSTEP,
32b6d3f6 59 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
e5ce4208
GG		 60 },
61 {
62 .name = "SMPS3",
504382c9 63 .sname = "smps3-in",
e5ce4208
GG		 64 .vsel_addr = PALMAS_SMPS3_VOLTAGE,
65 .ctrl_addr = PALMAS_SMPS3_CTRL,
32b6d3f6 66 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS3,
e5ce4208
GG		 67 },
68 {
69 .name = "SMPS45",
504382c9 70 .sname = "smps4-in",
e5ce4208
GG		 71 .vsel_addr = PALMAS_SMPS45_VOLTAGE,
72 .ctrl_addr = PALMAS_SMPS45_CTRL,
73 .tstep_addr = PALMAS_SMPS45_TSTEP,
32b6d3f6 74 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
e5ce4208
GG		 75 },
76 {
77 .name = "SMPS457",
504382c9 78 .sname = "smps4-in",
e5ce4208
GG		 79 .vsel_addr = PALMAS_SMPS45_VOLTAGE,
80 .ctrl_addr = PALMAS_SMPS45_CTRL,
81 .tstep_addr = PALMAS_SMPS45_TSTEP,
32b6d3f6 82 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
e5ce4208
GG		 83 },
84 {
85 .name = "SMPS6",
504382c9 86 .sname = "smps6-in",
e5ce4208
GG		 87 .vsel_addr = PALMAS_SMPS6_VOLTAGE,
88 .ctrl_addr = PALMAS_SMPS6_CTRL,
89 .tstep_addr = PALMAS_SMPS6_TSTEP,
32b6d3f6 90 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS6,
e5ce4208
GG		 91 },
92 {
93 .name = "SMPS7",
504382c9 94 .sname = "smps7-in",
e5ce4208
GG		 95 .vsel_addr = PALMAS_SMPS7_VOLTAGE,
96 .ctrl_addr = PALMAS_SMPS7_CTRL,
32b6d3f6 97 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS7,
e5ce4208
GG		 98 },
99 {
100 .name = "SMPS8",
504382c9 101 .sname = "smps8-in",
e5ce4208
GG		 102 .vsel_addr = PALMAS_SMPS8_VOLTAGE,
103 .ctrl_addr = PALMAS_SMPS8_CTRL,
104 .tstep_addr = PALMAS_SMPS8_TSTEP,
32b6d3f6 105 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS8,
e5ce4208
GG		 106 },
107 {
108 .name = "SMPS9",
504382c9 109 .sname = "smps9-in",
e5ce4208
GG		 110 .vsel_addr = PALMAS_SMPS9_VOLTAGE,
111 .ctrl_addr = PALMAS_SMPS9_CTRL,
32b6d3f6 112 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS9,
e5ce4208
GG		 113 },
114 {
77409d9b 115 .name = "SMPS10_OUT2",
504382c9 116 .sname = "smps10-in",
e31089c6 117 .ctrl_addr = PALMAS_SMPS10_CTRL,
32b6d3f6 118 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
e5ce4208 119 },
77409d9b
KVA		 120 {
121 .name = "SMPS10_OUT1",
122 .sname = "smps10-out2",
123 .ctrl_addr = PALMAS_SMPS10_CTRL,
32b6d3f6 124 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
77409d9b 125 },
e5ce4208
GG		 126 {
127 .name = "LDO1",
504382c9 128 .sname = "ldo1-in",
e5ce4208
GG		 129 .vsel_addr = PALMAS_LDO1_VOLTAGE,
130 .ctrl_addr = PALMAS_LDO1_CTRL,
32b6d3f6 131 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO1,
e5ce4208
GG		 132 },
133 {
134 .name = "LDO2",
504382c9 135 .sname = "ldo2-in",
e5ce4208
GG		 136 .vsel_addr = PALMAS_LDO2_VOLTAGE,
137 .ctrl_addr = PALMAS_LDO2_CTRL,
32b6d3f6 138 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO2,
e5ce4208
GG		 139 },
140 {
141 .name = "LDO3",
504382c9 142 .sname = "ldo3-in",
e5ce4208
GG		 143 .vsel_addr = PALMAS_LDO3_VOLTAGE,
144 .ctrl_addr = PALMAS_LDO3_CTRL,
32b6d3f6 145 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO3,
e5ce4208
GG		 146 },
147 {
148 .name = "LDO4",
504382c9 149 .sname = "ldo4-in",
e5ce4208
GG		 150 .vsel_addr = PALMAS_LDO4_VOLTAGE,
151 .ctrl_addr = PALMAS_LDO4_CTRL,
32b6d3f6 152 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO4,
e5ce4208
GG		 153 },
154 {
155 .name = "LDO5",
504382c9 156 .sname = "ldo5-in",
e5ce4208
GG		 157 .vsel_addr = PALMAS_LDO5_VOLTAGE,
158 .ctrl_addr = PALMAS_LDO5_CTRL,
32b6d3f6 159 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO5,
e5ce4208
GG		 160 },
161 {
162 .name = "LDO6",
504382c9 163 .sname = "ldo6-in",
e5ce4208
GG		 164 .vsel_addr = PALMAS_LDO6_VOLTAGE,
165 .ctrl_addr = PALMAS_LDO6_CTRL,
32b6d3f6 166 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO6,
e5ce4208
GG		 167 },
168 {
169 .name = "LDO7",
504382c9 170 .sname = "ldo7-in",
e5ce4208
GG		 171 .vsel_addr = PALMAS_LDO7_VOLTAGE,
172 .ctrl_addr = PALMAS_LDO7_CTRL,
32b6d3f6 173 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO7,
e5ce4208
GG		 174 },
175 {
176 .name = "LDO8",
504382c9 177 .sname = "ldo8-in",
e5ce4208
GG		 178 .vsel_addr = PALMAS_LDO8_VOLTAGE,
179 .ctrl_addr = PALMAS_LDO8_CTRL,
32b6d3f6 180 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO8,
e5ce4208
GG		 181 },
182 {
183 .name = "LDO9",
504382c9 184 .sname = "ldo9-in",
e5ce4208
GG		 185 .vsel_addr = PALMAS_LDO9_VOLTAGE,
186 .ctrl_addr = PALMAS_LDO9_CTRL,
32b6d3f6 187 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO9,
e5ce4208
GG		 188 },
189 {
190 .name = "LDOLN",
504382c9 191 .sname = "ldoln-in",
e5ce4208
GG		 192 .vsel_addr = PALMAS_LDOLN_VOLTAGE,
193 .ctrl_addr = PALMAS_LDOLN_CTRL,
32b6d3f6 194 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDOLN,
e5ce4208
GG		 195 },
196 {
197 .name = "LDOUSB",
504382c9 198 .sname = "ldousb-in",
e5ce4208
GG		 199 .vsel_addr = PALMAS_LDOUSB_VOLTAGE,
200 .ctrl_addr = PALMAS_LDOUSB_CTRL,
32b6d3f6 201 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDOUSB,
e5ce4208 202 },
aa07f027
LD		 203 {
204 .name = "REGEN1",
205 .ctrl_addr = PALMAS_REGEN1_CTRL,
32b6d3f6 206 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN1,
aa07f027
LD		 207 },
208 {
209 .name = "REGEN2",
210 .ctrl_addr = PALMAS_REGEN2_CTRL,
32b6d3f6 211 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN2,
aa07f027
LD		 212 },
213 {
214 .name = "REGEN3",
215 .ctrl_addr = PALMAS_REGEN3_CTRL,
32b6d3f6 216 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN3,
aa07f027
LD		 217 },
218 {
219 .name = "SYSEN1",
220 .ctrl_addr = PALMAS_SYSEN1_CTRL,
32b6d3f6 221 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SYSEN1,
aa07f027
LD		 222 },
223 {
224 .name = "SYSEN2",
225 .ctrl_addr = PALMAS_SYSEN2_CTRL,
32b6d3f6 226 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SYSEN2,
aa07f027 227 },
e5ce4208
GG		 228};
229
e7cf34ef 230static struct palmas_regs_info tps65917_regs_info[] = {
d6f83370
K		 231 {
232 .name = "SMPS1",
233 .sname = "smps1-in",
234 .vsel_addr = TPS65917_SMPS1_VOLTAGE,
235 .ctrl_addr = TPS65917_SMPS1_CTRL,
236 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS1,
237 },
238 {
239 .name = "SMPS2",
240 .sname = "smps2-in",
241 .vsel_addr = TPS65917_SMPS2_VOLTAGE,
242 .ctrl_addr = TPS65917_SMPS2_CTRL,
243 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS2,
244 },
245 {
246 .name = "SMPS3",
247 .sname = "smps3-in",
248 .vsel_addr = TPS65917_SMPS3_VOLTAGE,
249 .ctrl_addr = TPS65917_SMPS3_CTRL,
250 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS3,
251 },
252 {
253 .name = "SMPS4",
254 .sname = "smps4-in",
255 .vsel_addr = TPS65917_SMPS4_VOLTAGE,
256 .ctrl_addr = TPS65917_SMPS4_CTRL,
257 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS4,
258 },
259 {
260 .name = "SMPS5",
261 .sname = "smps5-in",
262 .vsel_addr = TPS65917_SMPS5_VOLTAGE,
263 .ctrl_addr = TPS65917_SMPS5_CTRL,
264 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS5,
265 },
266 {
267 .name = "LDO1",
268 .sname = "ldo1-in",
269 .vsel_addr = TPS65917_LDO1_VOLTAGE,
270 .ctrl_addr = TPS65917_LDO1_CTRL,
271 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO1,
272 },
273 {
274 .name = "LDO2",
275 .sname = "ldo2-in",
276 .vsel_addr = TPS65917_LDO2_VOLTAGE,
277 .ctrl_addr = TPS65917_LDO2_CTRL,
278 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO2,
279 },
280 {
281 .name = "LDO3",
282 .sname = "ldo3-in",
283 .vsel_addr = TPS65917_LDO3_VOLTAGE,
284 .ctrl_addr = TPS65917_LDO3_CTRL,
285 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO3,
286 },
287 {
288 .name = "LDO4",
289 .sname = "ldo4-in",
290 .vsel_addr = TPS65917_LDO4_VOLTAGE,
291 .ctrl_addr = TPS65917_LDO4_CTRL,
292 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO4,
293 },
294 {
295 .name = "LDO5",
296 .sname = "ldo5-in",
297 .vsel_addr = TPS65917_LDO5_VOLTAGE,
298 .ctrl_addr = TPS65917_LDO5_CTRL,
299 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO5,
300 },
301 {
302 .name = "REGEN1",
303 .ctrl_addr = TPS65917_REGEN1_CTRL,
304 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN1,
305 },
306 {
307 .name = "REGEN2",
308 .ctrl_addr = TPS65917_REGEN2_CTRL,
309 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN2,
310 },
311 {
312 .name = "REGEN3",
313 .ctrl_addr = TPS65917_REGEN3_CTRL,
314 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN3,
315 },
316};
317
cac9e916
K		 318#define EXTERNAL_REQUESTOR(_id, _offset, _pos) \
319 [PALMAS_EXTERNAL_REQSTR_ID_##_id] = { \
320 .id = PALMAS_EXTERNAL_REQSTR_ID_##_id, \
321 .reg_offset = _offset, \
322 .bit_pos = _pos, \
323 }
324
4b09e17b 325static struct palmas_sleep_requestor_info palma_sleep_req_info[] = {
cac9e916
K		 326 EXTERNAL_REQUESTOR(REGEN1, 0, 0),
327 EXTERNAL_REQUESTOR(REGEN2, 0, 1),
328 EXTERNAL_REQUESTOR(SYSEN1, 0, 2),
329 EXTERNAL_REQUESTOR(SYSEN2, 0, 3),
330 EXTERNAL_REQUESTOR(CLK32KG, 0, 4),
331 EXTERNAL_REQUESTOR(CLK32KGAUDIO, 0, 5),
332 EXTERNAL_REQUESTOR(REGEN3, 0, 6),
333 EXTERNAL_REQUESTOR(SMPS12, 1, 0),
334 EXTERNAL_REQUESTOR(SMPS3, 1, 1),
335 EXTERNAL_REQUESTOR(SMPS45, 1, 2),
336 EXTERNAL_REQUESTOR(SMPS6, 1, 3),
337 EXTERNAL_REQUESTOR(SMPS7, 1, 4),
338 EXTERNAL_REQUESTOR(SMPS8, 1, 5),
339 EXTERNAL_REQUESTOR(SMPS9, 1, 6),
340 EXTERNAL_REQUESTOR(SMPS10, 1, 7),
341 EXTERNAL_REQUESTOR(LDO1, 2, 0),
342 EXTERNAL_REQUESTOR(LDO2, 2, 1),
343 EXTERNAL_REQUESTOR(LDO3, 2, 2),
344 EXTERNAL_REQUESTOR(LDO4, 2, 3),
345 EXTERNAL_REQUESTOR(LDO5, 2, 4),
346 EXTERNAL_REQUESTOR(LDO6, 2, 5),
347 EXTERNAL_REQUESTOR(LDO7, 2, 6),
348 EXTERNAL_REQUESTOR(LDO8, 2, 7),
349 EXTERNAL_REQUESTOR(LDO9, 3, 0),
350 EXTERNAL_REQUESTOR(LDOLN, 3, 1),
351 EXTERNAL_REQUESTOR(LDOUSB, 3, 2),
352};
353
d6f83370
K		 354#define EXTERNAL_REQUESTOR_TPS65917(_id, _offset, _pos) \
355 [TPS65917_EXTERNAL_REQSTR_ID_##_id] = { \
356 .id = TPS65917_EXTERNAL_REQSTR_ID_##_id, \
357 .reg_offset = _offset, \
358 .bit_pos = _pos, \
359 }
360
361static struct palmas_sleep_requestor_info tps65917_sleep_req_info[] = {
362 EXTERNAL_REQUESTOR_TPS65917(REGEN1, 0, 0),
363 EXTERNAL_REQUESTOR_TPS65917(REGEN2, 0, 1),
364 EXTERNAL_REQUESTOR_TPS65917(REGEN3, 0, 6),
365 EXTERNAL_REQUESTOR_TPS65917(SMPS1, 1, 0),
366 EXTERNAL_REQUESTOR_TPS65917(SMPS2, 1, 1),
367 EXTERNAL_REQUESTOR_TPS65917(SMPS3, 1, 2),
368 EXTERNAL_REQUESTOR_TPS65917(SMPS4, 1, 3),
369 EXTERNAL_REQUESTOR_TPS65917(SMPS5, 1, 4),
370 EXTERNAL_REQUESTOR_TPS65917(LDO1, 2, 0),
371 EXTERNAL_REQUESTOR_TPS65917(LDO2, 2, 1),
372 EXTERNAL_REQUESTOR_TPS65917(LDO3, 2, 2),
373 EXTERNAL_REQUESTOR_TPS65917(LDO4, 2, 3),
374 EXTERNAL_REQUESTOR_TPS65917(LDO5, 2, 4),
375};
376
28d1e8cd
LD		 377static unsigned int palmas_smps_ramp_delay[4] = {0, 10000, 5000, 2500};
378
e5ce4208
GG		 379#define SMPS_CTRL_MODE_OFF 0x00
380#define SMPS_CTRL_MODE_ON 0x01
381#define SMPS_CTRL_MODE_ECO 0x02
382#define SMPS_CTRL_MODE_PWM 0x03
383
0f45aa84 384#define PALMAS_SMPS_NUM_VOLTAGES 122
e5ce4208
GG		 385#define PALMAS_SMPS10_NUM_VOLTAGES 2
386#define PALMAS_LDO_NUM_VOLTAGES 50
387
388#define SMPS10_VSEL (1<<3)
389#define SMPS10_BOOST_EN (1<<2)
390#define SMPS10_BYPASS_EN (1<<1)
391#define SMPS10_SWITCH_EN (1<<0)
392
393#define REGULATOR_SLAVE 0
394
395static int palmas_smps_read(struct palmas *palmas, unsigned int reg,
396 unsigned int *dest)
397{
398 unsigned int addr;
399
400 addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg);
401
402 return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest);
403}
404
405static int palmas_smps_write(struct palmas *palmas, unsigned int reg,
406 unsigned int value)
407{
408 unsigned int addr;
409
410 addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg);
411
412 return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value);
413}
414
415static int palmas_ldo_read(struct palmas *palmas, unsigned int reg,
416 unsigned int *dest)
417{
418 unsigned int addr;
419
420 addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg);
421
422 return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest);
423}
424
425static int palmas_ldo_write(struct palmas *palmas, unsigned int reg,
426 unsigned int value)
427{
428 unsigned int addr;
429
430 addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg);
431
432 return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value);
433}
434
e5ce4208
GG		 435static int palmas_set_mode_smps(struct regulator_dev *dev, unsigned int mode)
436{
437 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
cac9e916 438 struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata;
e5ce4208
GG		 439 int id = rdev_get_id(dev);
440 unsigned int reg;
51d3a0c9 441 bool rail_enable = true;
e5ce4208 442
cac9e916
K		 443 palmas_smps_read(pmic->palmas, ddata->palmas_regs_info[id].ctrl_addr,
444 &reg);
445
999f0c7c 446 reg &= ~PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
e5ce4208 447
51d3a0c9
LD		 448 if (reg == SMPS_CTRL_MODE_OFF)
449 rail_enable = false;
450
e5ce4208
GG		 451 switch (mode) {
452 case REGULATOR_MODE_NORMAL:
453 reg |= SMPS_CTRL_MODE_ON;
454 break;
455 case REGULATOR_MODE_IDLE:
456 reg |= SMPS_CTRL_MODE_ECO;
457 break;
458 case REGULATOR_MODE_FAST:
459 reg |= SMPS_CTRL_MODE_PWM;
460 break;
461 default:
462 return -EINVAL;
463 }
e5ce4208 464
51d3a0c9
LD		 465 pmic->current_reg_mode[id] = reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
466 if (rail_enable)
467 palmas_smps_write(pmic->palmas,
cac9e916 468 ddata->palmas_regs_info[id].ctrl_addr, reg);
318dbb02
NM		 469
470 /* Switch the enable value to ensure this is used for enable */
471 pmic->desc[id].enable_val = pmic->current_reg_mode[id];
472
e5ce4208
GG		 473 return 0;
474}
475
476static unsigned int palmas_get_mode_smps(struct regulator_dev *dev)
477{
478 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
479 int id = rdev_get_id(dev);
480 unsigned int reg;
481
51d3a0c9 482 reg = pmic->current_reg_mode[id] & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
e5ce4208
GG		 483
484 switch (reg) {
485 case SMPS_CTRL_MODE_ON:
486 return REGULATOR_MODE_NORMAL;
487 case SMPS_CTRL_MODE_ECO:
488 return REGULATOR_MODE_IDLE;
489 case SMPS_CTRL_MODE_PWM:
490 return REGULATOR_MODE_FAST;
491 }
492
493 return 0;
494}
495
28d1e8cd
LD		 496static int palmas_smps_set_ramp_delay(struct regulator_dev *rdev,
497 int ramp_delay)
498{
499 struct palmas_pmic *pmic = rdev_get_drvdata(rdev);
cac9e916 500 struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata;
28d1e8cd
LD		 501 int id = rdev_get_id(rdev);
502 unsigned int reg = 0;
cac9e916 503 unsigned int addr = ddata->palmas_regs_info[id].tstep_addr;
28d1e8cd
LD		 504 int ret;
505
f22c2bae
AL		 506 /* SMPS3 and SMPS7 do not have tstep_addr setting */
507 switch (id) {
508 case PALMAS_REG_SMPS3:
509 case PALMAS_REG_SMPS7:
510 return 0;
511 }
512
28d1e8cd
LD		 513 if (ramp_delay <= 0)
514 reg = 0;
0ea34b57 515 else if (ramp_delay <= 2500)
28d1e8cd 516 reg = 3;
0ea34b57 517 else if (ramp_delay <= 5000)
28d1e8cd
LD		 518 reg = 2;
519 else
520 reg = 1;
521
522 ret = palmas_smps_write(pmic->palmas, addr, reg);
523 if (ret < 0) {
524 dev_err(pmic->palmas->dev, "TSTEP write failed: %d\n", ret);
525 return ret;
526 }
527
528 pmic->ramp_delay[id] = palmas_smps_ramp_delay[reg];
529 return ret;
530}
531
e5ce4208 532static struct regulator_ops palmas_ops_smps = {
dbabd624
K		 533 .is_enabled = regulator_is_enabled_regmap,
534 .enable = regulator_enable_regmap,
535 .disable = regulator_disable_regmap,
e5ce4208
GG		 536 .set_mode = palmas_set_mode_smps,
537 .get_mode = palmas_get_mode_smps,
bdc4baac
AL		 538 .get_voltage_sel = regulator_get_voltage_sel_regmap,
539 .set_voltage_sel = regulator_set_voltage_sel_regmap,
dbabd624
K		 540 .list_voltage = regulator_list_voltage_linear_range,
541 .map_voltage = regulator_map_voltage_linear_range,
542 .set_voltage_time_sel = regulator_set_voltage_time_sel,
28d1e8cd 543 .set_ramp_delay = palmas_smps_set_ramp_delay,
e5ce4208
GG		 544};
545
32b6d3f6
LD		 546static struct regulator_ops palmas_ops_ext_control_smps = {
547 .set_mode = palmas_set_mode_smps,
548 .get_mode = palmas_get_mode_smps,
549 .get_voltage_sel = regulator_get_voltage_sel_regmap,
550 .set_voltage_sel = regulator_set_voltage_sel_regmap,
dbabd624
K		 551 .list_voltage = regulator_list_voltage_linear_range,
552 .map_voltage = regulator_map_voltage_linear_range,
553 .set_voltage_time_sel = regulator_set_voltage_time_sel,
32b6d3f6
LD		 554 .set_ramp_delay = palmas_smps_set_ramp_delay,
555};
556
e5ce4208
GG		 557static struct regulator_ops palmas_ops_smps10 = {
558 .is_enabled = regulator_is_enabled_regmap,
559 .enable = regulator_enable_regmap,
560 .disable = regulator_disable_regmap,
561 .get_voltage_sel = regulator_get_voltage_sel_regmap,
562 .set_voltage_sel = regulator_set_voltage_sel_regmap,
8029a006
AL		 563 .list_voltage = regulator_list_voltage_linear,
564 .map_voltage = regulator_map_voltage_linear,
77409d9b
KVA		 565 .set_bypass = regulator_set_bypass_regmap,
566 .get_bypass = regulator_get_bypass_regmap,
e5ce4208
GG		 567};
568
d6f83370
K		 569static struct regulator_ops tps65917_ops_smps = {
570 .is_enabled = regulator_is_enabled_regmap,
571 .enable = regulator_enable_regmap,
572 .disable = regulator_disable_regmap,
573 .set_mode = palmas_set_mode_smps,
574 .get_mode = palmas_get_mode_smps,
575 .get_voltage_sel = regulator_get_voltage_sel_regmap,
576 .set_voltage_sel = regulator_set_voltage_sel_regmap,
577 .list_voltage = regulator_list_voltage_linear_range,
578 .map_voltage = regulator_map_voltage_linear_range,
579 .set_voltage_time_sel = regulator_set_voltage_time_sel,
580};
581
582static struct regulator_ops tps65917_ops_ext_control_smps = {
583 .set_mode = palmas_set_mode_smps,
584 .get_mode = palmas_get_mode_smps,
585 .get_voltage_sel = regulator_get_voltage_sel_regmap,
586 .set_voltage_sel = regulator_set_voltage_sel_regmap,
587 .list_voltage = regulator_list_voltage_linear_range,
588 .map_voltage = regulator_map_voltage_linear_range,
589};
590
e5ce4208
GG		 591static int palmas_is_enabled_ldo(struct regulator_dev *dev)
592{
593 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
cac9e916 594 struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata;
e5ce4208
GG		 595 int id = rdev_get_id(dev);
596 unsigned int reg;
597
cac9e916
K		 598 palmas_ldo_read(pmic->palmas,
599 ddata->palmas_regs_info[id].ctrl_addr, &reg);
e5ce4208
GG		 600
601 reg &= PALMAS_LDO1_CTRL_STATUS;
602
603 return !!(reg);
604}
605
e5ce4208
GG		 606static struct regulator_ops palmas_ops_ldo = {
607 .is_enabled = palmas_is_enabled_ldo,
608 .enable = regulator_enable_regmap,
609 .disable = regulator_disable_regmap,
4a247a96
AL		 610 .get_voltage_sel = regulator_get_voltage_sel_regmap,
611 .set_voltage_sel = regulator_set_voltage_sel_regmap,
9119ff6a
AL		 612 .list_voltage = regulator_list_voltage_linear,
613 .map_voltage = regulator_map_voltage_linear,
e5ce4208
GG		 614};
615
32b6d3f6
LD		 616static struct regulator_ops palmas_ops_ext_control_ldo = {
617 .get_voltage_sel = regulator_get_voltage_sel_regmap,
618 .set_voltage_sel = regulator_set_voltage_sel_regmap,
619 .list_voltage = regulator_list_voltage_linear,
620 .map_voltage = regulator_map_voltage_linear,
621};
622
aa07f027
LD		 623static struct regulator_ops palmas_ops_extreg = {
624 .is_enabled = regulator_is_enabled_regmap,
625 .enable = regulator_enable_regmap,
626 .disable = regulator_disable_regmap,
627};
628
32b6d3f6
LD		 629static struct regulator_ops palmas_ops_ext_control_extreg = {
630};
631
d6f83370
K		 632static struct regulator_ops tps65917_ops_ldo = {
633 .is_enabled = palmas_is_enabled_ldo,
634 .enable = regulator_enable_regmap,
635 .disable = regulator_disable_regmap,
636 .get_voltage_sel = regulator_get_voltage_sel_regmap,
637 .set_voltage_sel = regulator_set_voltage_sel_regmap,
638 .list_voltage = regulator_list_voltage_linear,
639 .map_voltage = regulator_map_voltage_linear,
640 .set_voltage_time_sel = regulator_set_voltage_time_sel,
641};
642
32b6d3f6
LD		 643static int palmas_regulator_config_external(struct palmas *palmas, int id,
644 struct palmas_reg_init *reg_init)
645{
646 int sleep_id = palmas_regs_info[id].sleep_id;
647 int ret;
648
649 ret = palmas_ext_control_req_config(palmas, sleep_id,
650 reg_init->roof_floor, true);
651 if (ret < 0)
652 dev_err(palmas->dev,
653 "Ext control config for regulator %d failed %d\n",
654 id, ret);
655 return ret;
656}
657
e5ce4208
GG		 658/*
659 * setup the hardware based sleep configuration of the SMPS/LDO regulators
660 * from the platform data. This is different to the software based control
661 * supported by the regulator framework as it is controlled by toggling
662 * pins on the PMIC such as PREQ, SYSEN, ...
663 */
664static int palmas_smps_init(struct palmas *palmas, int id,
665 struct palmas_reg_init *reg_init)
666{
667 unsigned int reg;
668 unsigned int addr;
669 int ret;
670
cac9e916
K		 671 struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
672
673 addr = ddata->palmas_regs_info[id].ctrl_addr;
e5ce4208
GG		 674
675 ret = palmas_smps_read(palmas, addr, &reg);
676 if (ret)
677 return ret;
678
fedd89b1 679 switch (id) {
77409d9b
KVA		 680 case PALMAS_REG_SMPS10_OUT1:
681 case PALMAS_REG_SMPS10_OUT2:
30590d04
LD		 682 reg &= ~PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK;
683 if (reg_init->mode_sleep)
fedd89b1
AL		 684 reg |= reg_init->mode_sleep <<
685 PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT;
fedd89b1
AL		 686 break;
687 default:
e5ce4208
GG		 688 if (reg_init->warm_reset)
689 reg |= PALMAS_SMPS12_CTRL_WR_S;
30590d04
LD		 690 else
691 reg &= ~PALMAS_SMPS12_CTRL_WR_S;
e5ce4208
GG		 692
693 if (reg_init->roof_floor)
694 reg |= PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN;
30590d04
LD		 695 else
696 reg &= ~PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN;
e5ce4208 697
30590d04
LD		 698 reg &= ~PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK;
699 if (reg_init->mode_sleep)
e5ce4208
GG		 700 reg |= reg_init->mode_sleep <<
701 PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT;
e5ce4208 702 }
fedd89b1 703
e5ce4208
GG		 704 ret = palmas_smps_write(palmas, addr, reg);
705 if (ret)
706 return ret;
707
cac9e916
K		 708 if (ddata->palmas_regs_info[id].vsel_addr && reg_init->vsel) {
709 addr = ddata->palmas_regs_info[id].vsel_addr;
e5ce4208
GG		 710
711 reg = reg_init->vsel;
712
713 ret = palmas_smps_write(palmas, addr, reg);
714 if (ret)
715 return ret;
716 }
717
32b6d3f6
LD		 718 if (reg_init->roof_floor && (id != PALMAS_REG_SMPS10_OUT1) &&
719 (id != PALMAS_REG_SMPS10_OUT2)) {
720 /* Enable externally controlled regulator */
cac9e916 721 addr = ddata->palmas_regs_info[id].ctrl_addr;
32b6d3f6
LD		 722 ret = palmas_smps_read(palmas, addr, &reg);
723 if (ret < 0)
724 return ret;
e5ce4208 725
32b6d3f6
LD		 726 if (!(reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK)) {
727 reg |= SMPS_CTRL_MODE_ON;
728 ret = palmas_smps_write(palmas, addr, reg);
729 if (ret < 0)
730 return ret;
731 }
732 return palmas_regulator_config_external(palmas, id, reg_init);
733 }
e5ce4208
GG		 734 return 0;
735}
736
737static int palmas_ldo_init(struct palmas *palmas, int id,
738 struct palmas_reg_init *reg_init)
739{
740 unsigned int reg;
741 unsigned int addr;
742 int ret;
743
cac9e916
K		 744 struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
745
746 addr = ddata->palmas_regs_info[id].ctrl_addr;
e5ce4208 747
2735daeb 748 ret = palmas_ldo_read(palmas, addr, &reg);
e5ce4208
GG		 749 if (ret)
750 return ret;
751
752 if (reg_init->warm_reset)
753 reg |= PALMAS_LDO1_CTRL_WR_S;
30590d04
LD		 754 else
755 reg &= ~PALMAS_LDO1_CTRL_WR_S;
e5ce4208
GG		 756
757 if (reg_init->mode_sleep)
758 reg |= PALMAS_LDO1_CTRL_MODE_SLEEP;
30590d04
LD		 759 else
760 reg &= ~PALMAS_LDO1_CTRL_MODE_SLEEP;
e5ce4208 761
2735daeb 762 ret = palmas_ldo_write(palmas, addr, reg);
e5ce4208
GG		 763 if (ret)
764 return ret;
765
32b6d3f6
LD		 766 if (reg_init->roof_floor) {
767 /* Enable externally controlled regulator */
cac9e916 768 addr = ddata->palmas_regs_info[id].ctrl_addr;
32b6d3f6
LD		 769 ret = palmas_update_bits(palmas, PALMAS_LDO_BASE,
770 addr, PALMAS_LDO1_CTRL_MODE_ACTIVE,
771 PALMAS_LDO1_CTRL_MODE_ACTIVE);
772 if (ret < 0) {
773 dev_err(palmas->dev,
774 "LDO Register 0x%02x update failed %d\n",
775 addr, ret);
776 return ret;
777 }
778 return palmas_regulator_config_external(palmas, id, reg_init);
779 }
e5ce4208
GG		 780 return 0;
781}
782
aa07f027
LD		 783static int palmas_extreg_init(struct palmas *palmas, int id,
784 struct palmas_reg_init *reg_init)
785{
786 unsigned int addr;
787 int ret;
788 unsigned int val = 0;
789
cac9e916
K		 790 struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
791
792 addr = ddata->palmas_regs_info[id].ctrl_addr;
aa07f027
LD		 793
794 if (reg_init->mode_sleep)
795 val = PALMAS_REGEN1_CTRL_MODE_SLEEP;
796
797 ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
798 addr, PALMAS_REGEN1_CTRL_MODE_SLEEP, val);
799 if (ret < 0) {
800 dev_err(palmas->dev, "Resource reg 0x%02x update failed %d\n",
801 addr, ret);
802 return ret;
803 }
32b6d3f6
LD		 804
805 if (reg_init->roof_floor) {
806 /* Enable externally controlled regulator */
cac9e916 807 addr = ddata->palmas_regs_info[id].ctrl_addr;
32b6d3f6
LD		 808 ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
809 addr, PALMAS_REGEN1_CTRL_MODE_ACTIVE,
810 PALMAS_REGEN1_CTRL_MODE_ACTIVE);
811 if (ret < 0) {
812 dev_err(palmas->dev,
813 "Resource Register 0x%02x update failed %d\n",
814 addr, ret);
815 return ret;
816 }
817 return palmas_regulator_config_external(palmas, id, reg_init);
818 }
aa07f027
LD		 819 return 0;
820}
821
17c11a76
LD		 822static void palmas_enable_ldo8_track(struct palmas *palmas)
823{
824 unsigned int reg;
825 unsigned int addr;
826 int ret;
827
cac9e916
K		 828 struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
829
830 addr = ddata->palmas_regs_info[PALMAS_REG_LDO8].ctrl_addr;
17c11a76
LD		 831
832 ret = palmas_ldo_read(palmas, addr, &reg);
833 if (ret) {
834 dev_err(palmas->dev, "Error in reading ldo8 control reg\n");
835 return;
836 }
837
838 reg |= PALMAS_LDO8_CTRL_LDO_TRACKING_EN;
839 ret = palmas_ldo_write(palmas, addr, reg);
840 if (ret < 0) {
841 dev_err(palmas->dev, "Error in enabling tracking mode\n");
842 return;
843 }
844 /*
845 * When SMPS45 is set to off and LDO8 tracking is enabled, the LDO8
846 * output is defined by the LDO8_VOLTAGE.VSEL register divided by two,
847 * and can be set from 0.45 to 1.65 V.
848 */
cac9e916 849 addr = ddata->palmas_regs_info[PALMAS_REG_LDO8].vsel_addr;
17c11a76
LD		 850 ret = palmas_ldo_read(palmas, addr, &reg);
851 if (ret) {
852 dev_err(palmas->dev, "Error in reading ldo8 voltage reg\n");
853 return;
854 }
855
856 reg = (reg << 1) & PALMAS_LDO8_VOLTAGE_VSEL_MASK;
857 ret = palmas_ldo_write(palmas, addr, reg);
858 if (ret < 0)
859 dev_err(palmas->dev, "Error in setting ldo8 voltage reg\n");
860
861 return;
862}
863
cac9e916
K		 864static int palmas_ldo_registration(struct palmas_pmic *pmic,
865 struct palmas_pmic_driver_data *ddata,
866 struct palmas_pmic_platform_data *pdata,
867 const char *pdev_name,
868 struct regulator_config config)
a361cd9f 869{
cac9e916
K		 870 int id, ret;
871 struct regulator_dev *rdev;
872 struct palmas_reg_init *reg_init;
a361cd9f 873
cac9e916
K		 874 for (id = ddata->ldo_begin; id < ddata->max_reg; id++) {
875 if (pdata && pdata->reg_init[id])
876 reg_init = pdata->reg_init[id];
877 else
878 reg_init = NULL;
a361cd9f 879
cac9e916
K		 880 /* Miss out regulators which are not available due
881 * to alternate functions.
882 */
a361cd9f 883
cac9e916
K		 884 /* Register the regulators */
885 pmic->desc[id].name = ddata->palmas_regs_info[id].name;
886 pmic->desc[id].id = id;
887 pmic->desc[id].type = REGULATOR_VOLTAGE;
888 pmic->desc[id].owner = THIS_MODULE;
a361cd9f 889
cac9e916
K		 890 if (id < PALMAS_REG_REGEN1) {
891 pmic->desc[id].n_voltages = PALMAS_LDO_NUM_VOLTAGES;
892 if (reg_init && reg_init->roof_floor)
893 pmic->desc[id].ops =
894 &palmas_ops_ext_control_ldo;
895 else
896 pmic->desc[id].ops = &palmas_ops_ldo;
897 pmic->desc[id].min_uV = 900000;
898 pmic->desc[id].uV_step = 50000;
899 pmic->desc[id].linear_min_sel = 1;
900 pmic->desc[id].enable_time = 500;
901 pmic->desc[id].vsel_reg =
902 PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
903 ddata->palmas_regs_info[id].vsel_addr);
904 pmic->desc[id].vsel_mask =
905 PALMAS_LDO1_VOLTAGE_VSEL_MASK;
906 pmic->desc[id].enable_reg =
907 PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
908 ddata->palmas_regs_info[id].ctrl_addr);
909 pmic->desc[id].enable_mask =
910 PALMAS_LDO1_CTRL_MODE_ACTIVE;
a361cd9f 911
cac9e916
K		 912 /* Check if LDO8 is in tracking mode or not */
913 if (pdata && (id == PALMAS_REG_LDO8) &&
914 pdata->enable_ldo8_tracking) {
915 palmas_enable_ldo8_track(pmic->palmas);
916 pmic->desc[id].min_uV = 450000;
917 pmic->desc[id].uV_step = 25000;
918 }
a361cd9f 919
cac9e916
K		 920 /* LOD6 in vibrator mode will have enable time 2000us */
921 if (pdata && pdata->ldo6_vibrator &&
922 (id == PALMAS_REG_LDO6))
923 pmic->desc[id].enable_time = 2000;
924 } else {
925 pmic->desc[id].n_voltages = 1;
926 if (reg_init && reg_init->roof_floor)
927 pmic->desc[id].ops =
928 &palmas_ops_ext_control_extreg;
929 else
930 pmic->desc[id].ops = &palmas_ops_extreg;
931 pmic->desc[id].enable_reg =
932 PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE,
933 ddata->palmas_regs_info[id].ctrl_addr);
934 pmic->desc[id].enable_mask =
935 PALMAS_REGEN1_CTRL_MODE_ACTIVE;
936 }
a361cd9f 937
cac9e916
K		 938 if (pdata)
939 config.init_data = pdata->reg_data[id];
940 else
941 config.init_data = NULL;
32b6d3f6 942
cac9e916
K		 943 pmic->desc[id].supply_name = ddata->palmas_regs_info[id].sname;
944 config.of_node = ddata->palmas_matches[id].of_node;
a361cd9f 945
cac9e916
K		 946 rdev = devm_regulator_register(pmic->dev, &pmic->desc[id],
947 &config);
948 if (IS_ERR(rdev)) {
949 dev_err(pmic->dev,
950 "failed to register %s regulator\n",
951 pdev_name);
952 return PTR_ERR(rdev);
953 }
a361cd9f 954
cac9e916
K		 955 /* Save regulator for cleanup */
956 pmic->rdev[id] = rdev;
a361cd9f 957
cac9e916
K		 958 /* Initialise sleep/init values from platform data */
959 if (pdata) {
960 reg_init = pdata->reg_init[id];
961 if (reg_init) {
962 if (id <= ddata->ldo_end)
963 ret = palmas_ldo_init(pmic->palmas, id,
964 reg_init);
965 else
966 ret = palmas_extreg_init(pmic->palmas,
967 id, reg_init);
968 if (ret)
969 return ret;
970 }
971 }
a361cd9f
GG		 972 }
973
cac9e916 974 return 0;
a361cd9f
GG		 975}
976
d6f83370
K		 977static int tps65917_ldo_registration(struct palmas_pmic *pmic,
978 struct palmas_pmic_driver_data *ddata,
979 struct palmas_pmic_platform_data *pdata,
980 const char *pdev_name,
981 struct regulator_config config)
982{
983 int id, ret;
984 struct regulator_dev *rdev;
985 struct palmas_reg_init *reg_init;
986
987 for (id = ddata->ldo_begin; id < ddata->max_reg; id++) {
988 if (pdata && pdata->reg_init[id])
989 reg_init = pdata->reg_init[id];
990 else
991 reg_init = NULL;
992
993 /* Miss out regulators which are not available due
994 * to alternate functions.
995 */
996
997 /* Register the regulators */
998 pmic->desc[id].name = ddata->palmas_regs_info[id].name;
999 pmic->desc[id].id = id;
1000 pmic->desc[id].type = REGULATOR_VOLTAGE;
1001 pmic->desc[id].owner = THIS_MODULE;
1002
1003 if (id < TPS65917_REG_REGEN1) {
1004 pmic->desc[id].n_voltages = PALMAS_LDO_NUM_VOLTAGES;
1005 if (reg_init && reg_init->roof_floor)
1006 pmic->desc[id].ops =
1007 &palmas_ops_ext_control_ldo;
1008 else
1009 pmic->desc[id].ops = &tps65917_ops_ldo;
1010 pmic->desc[id].min_uV = 900000;
1011 pmic->desc[id].uV_step = 50000;
1012 pmic->desc[id].linear_min_sel = 1;
1013 pmic->desc[id].enable_time = 500;
1014 pmic->desc[id].vsel_reg =
1015 PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
1016 ddata->palmas_regs_info[id].vsel_addr);
1017 pmic->desc[id].vsel_mask =
1018 PALMAS_LDO1_VOLTAGE_VSEL_MASK;
1019 pmic->desc[id].enable_reg =
1020 PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
1021 ddata->palmas_regs_info[id].ctrl_addr);
1022 pmic->desc[id].enable_mask =
1023 PALMAS_LDO1_CTRL_MODE_ACTIVE;
1024 /*
1025 * To be confirmed. Discussion on going with PMIC Team.
1026 * It is of the order of ~60mV/uS.
1027 */
1028 pmic->desc[id].ramp_delay = 2500;
1029 } else {
1030 pmic->desc[id].n_voltages = 1;
1031 if (reg_init && reg_init->roof_floor)
1032 pmic->desc[id].ops =
1033 &palmas_ops_ext_control_extreg;
1034 else
1035 pmic->desc[id].ops = &palmas_ops_extreg;
1036 pmic->desc[id].enable_reg =
1037 PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE,
1038 ddata->palmas_regs_info[id].ctrl_addr);
1039 pmic->desc[id].enable_mask =
1040 PALMAS_REGEN1_CTRL_MODE_ACTIVE;
1041 }
1042
1043 if (pdata)
1044 config.init_data = pdata->reg_data[id];
1045 else
1046 config.init_data = NULL;
1047
1048 pmic->desc[id].supply_name = ddata->palmas_regs_info[id].sname;
1049 config.of_node = ddata->palmas_matches[id].of_node;
1050
1051 rdev = devm_regulator_register(pmic->dev, &pmic->desc[id],
1052 &config);
1053 if (IS_ERR(rdev)) {
1054 dev_err(pmic->dev,
1055 "failed to register %s regulator\n",
1056 pdev_name);
1057 return PTR_ERR(rdev);
1058 }
1059
1060 /* Save regulator for cleanup */
1061 pmic->rdev[id] = rdev;
1062
1063 /* Initialise sleep/init values from platform data */
1064 if (pdata) {
1065 reg_init = pdata->reg_init[id];
1066 if (reg_init) {
1067 if (id < TPS65917_REG_REGEN1)
1068 ret = palmas_ldo_init(pmic->palmas,
1069 id, reg_init);
1070 else
1071 ret = palmas_extreg_init(pmic->palmas,
1072 id, reg_init);
1073 if (ret)
1074 return ret;
1075 }
1076 }
1077 }
1078
1079 return 0;
1080}
1081
cac9e916
K		 1082static int palmas_smps_registration(struct palmas_pmic *pmic,
1083 struct palmas_pmic_driver_data *ddata,
1084 struct palmas_pmic_platform_data *pdata,
1085 const char *pdev_name,
1086 struct regulator_config config)
e5ce4208 1087{
cac9e916
K		 1088 int id, ret;
1089 unsigned int addr, reg;
e5ce4208 1090 struct regulator_dev *rdev;
e5ce4208 1091 struct palmas_reg_init *reg_init;
e5ce4208 1092
cac9e916 1093 for (id = ddata->smps_start; id <= ddata->smps_end; id++) {
28d1e8cd 1094 bool ramp_delay_support = false;
e5ce4208
GG		 1095
1096 /*
1097 * Miss out regulators which are not available due
1098 * to slaving configurations.
1099 */
1100 switch (id) {
1101 case PALMAS_REG_SMPS12:
1102 case PALMAS_REG_SMPS3:
1103 if (pmic->smps123)
1104 continue;
28d1e8cd
LD		 1105 if (id == PALMAS_REG_SMPS12)
1106 ramp_delay_support = true;
e5ce4208
GG		 1107 break;
1108 case PALMAS_REG_SMPS123:
1109 if (!pmic->smps123)
1110 continue;
28d1e8cd 1111 ramp_delay_support = true;
e5ce4208
GG		 1112 break;
1113 case PALMAS_REG_SMPS45:
1114 case PALMAS_REG_SMPS7:
1115 if (pmic->smps457)
1116 continue;
28d1e8cd
LD		 1117 if (id == PALMAS_REG_SMPS45)
1118 ramp_delay_support = true;
e5ce4208
GG		 1119 break;
1120 case PALMAS_REG_SMPS457:
1121 if (!pmic->smps457)
1122 continue;
28d1e8cd
LD		 1123 ramp_delay_support = true;
1124 break;
77409d9b
KVA		 1125 case PALMAS_REG_SMPS10_OUT1:
1126 case PALMAS_REG_SMPS10_OUT2:
cac9e916 1127 if (!PALMAS_PMIC_HAS(pmic->palmas, SMPS10_BOOST))
1ffb0be3 1128 continue;
28d1e8cd
LD		 1129 }
1130
3f4d6364 1131 if ((id == PALMAS_REG_SMPS6) || (id == PALMAS_REG_SMPS8))
28d1e8cd
LD		 1132 ramp_delay_support = true;
1133
1134 if (ramp_delay_support) {
cac9e916 1135 addr = ddata->palmas_regs_info[id].tstep_addr;
28d1e8cd
LD		 1136 ret = palmas_smps_read(pmic->palmas, addr, &reg);
1137 if (ret < 0) {
cac9e916 1138 dev_err(pmic->dev,
28d1e8cd 1139 "reading TSTEP reg failed: %d\n", ret);
51c86b3e 1140 return ret;
28d1e8cd
LD		 1141 }
1142 pmic->desc[id].ramp_delay =
1143 palmas_smps_ramp_delay[reg & 0x3];
1144 pmic->ramp_delay[id] = pmic->desc[id].ramp_delay;
e5ce4208
GG		 1145 }
1146
bdc4baac
AL		 1147 /* Initialise sleep/init values from platform data */
1148 if (pdata && pdata->reg_init[id]) {
1149 reg_init = pdata->reg_init[id];
cac9e916 1150 ret = palmas_smps_init(pmic->palmas, id, reg_init);
bdc4baac 1151 if (ret)
51c86b3e 1152 return ret;
32b6d3f6
LD		 1153 } else {
1154 reg_init = NULL;
bdc4baac
AL		 1155 }
1156
e5ce4208 1157 /* Register the regulators */
cac9e916 1158 pmic->desc[id].name = ddata->palmas_regs_info[id].name;
e5ce4208
GG		 1159 pmic->desc[id].id = id;
1160
fedd89b1 1161 switch (id) {
77409d9b
KVA		 1162 case PALMAS_REG_SMPS10_OUT1:
1163 case PALMAS_REG_SMPS10_OUT2:
e5ce4208
GG		 1164 pmic->desc[id].n_voltages = PALMAS_SMPS10_NUM_VOLTAGES;
1165 pmic->desc[id].ops = &palmas_ops_smps10;
12565b16
AL		 1166 pmic->desc[id].vsel_reg =
1167 PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1168 PALMAS_SMPS10_CTRL);
e5ce4208 1169 pmic->desc[id].vsel_mask = SMPS10_VSEL;
a68de074
GG		 1170 pmic->desc[id].enable_reg =
1171 PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
f232168d 1172 PALMAS_SMPS10_CTRL);
77409d9b
KVA		 1173 if (id == PALMAS_REG_SMPS10_OUT1)
1174 pmic->desc[id].enable_mask = SMPS10_SWITCH_EN;
1175 else
1176 pmic->desc[id].enable_mask = SMPS10_BOOST_EN;
1177 pmic->desc[id].bypass_reg =
1178 PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1179 PALMAS_SMPS10_CTRL);
1180 pmic->desc[id].bypass_mask = SMPS10_BYPASS_EN;
8029a006
AL		 1181 pmic->desc[id].min_uV = 3750000;
1182 pmic->desc[id].uV_step = 1250000;
fedd89b1
AL		 1183 break;
1184 default:
bdc4baac
AL		 1185 /*
1186 * Read and store the RANGE bit for later use
1187 * This must be done before regulator is probed,
51d3a0c9
LD		 1188 * otherwise we error in probe with unsupportable
1189 * ranges. Read the current smps mode for later use.
bdc4baac 1190 */
e5ce4208 1191 addr = palmas_regs_info[id].vsel_addr;
dbabd624 1192 pmic->desc[id].n_linear_ranges = 3;
e5ce4208
GG		 1193
1194 ret = palmas_smps_read(pmic->palmas, addr, &reg);
1195 if (ret)
51c86b3e 1196 return ret;
e5ce4208
GG		 1197 if (reg & PALMAS_SMPS12_VOLTAGE_RANGE)
1198 pmic->range[id] = 1;
dbabd624
K		 1199 if (pmic->range[id])
1200 pmic->desc[id].linear_ranges = smps_high_ranges;
1201 else
1202 pmic->desc[id].linear_ranges = smps_low_ranges;
bdc4baac 1203
32b6d3f6
LD		 1204 if (reg_init && reg_init->roof_floor)
1205 pmic->desc[id].ops =
1206 &palmas_ops_ext_control_smps;
1207 else
1208 pmic->desc[id].ops = &palmas_ops_smps;
bdc4baac
AL		 1209 pmic->desc[id].n_voltages = PALMAS_SMPS_NUM_VOLTAGES;
1210 pmic->desc[id].vsel_reg =
1211 PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1212 palmas_regs_info[id].vsel_addr);
1213 pmic->desc[id].vsel_mask =
1214 PALMAS_SMPS12_VOLTAGE_VSEL_MASK;
51d3a0c9
LD		 1215
1216 /* Read the smps mode for later use. */
1217 addr = palmas_regs_info[id].ctrl_addr;
1218 ret = palmas_smps_read(pmic->palmas, addr, &reg);
1219 if (ret)
51c86b3e 1220 return ret;
51d3a0c9
LD		 1221 pmic->current_reg_mode[id] = reg &
1222 PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
318dbb02
NM		 1223
1224 pmic->desc[id].enable_reg =
5b01bd11 1225 PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
318dbb02
NM		 1226 palmas_regs_info[id].ctrl_addr);
1227 pmic->desc[id].enable_mask =
1228 PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
1229 /* set_mode overrides this value */
1230 pmic->desc[id].enable_val = SMPS_CTRL_MODE_ON;
e5ce4208
GG		 1231 }
1232
bdc4baac
AL		 1233 pmic->desc[id].type = REGULATOR_VOLTAGE;
1234 pmic->desc[id].owner = THIS_MODULE;
1235
a361cd9f 1236 if (pdata)
e5ce4208
GG		 1237 config.init_data = pdata->reg_data[id];
1238 else
1239 config.init_data = NULL;
1240
cac9e916
K		 1241 pmic->desc[id].supply_name = ddata->palmas_regs_info[id].sname;
1242 config.of_node = ddata->palmas_matches[id].of_node;
a361cd9f 1243
cac9e916 1244 rdev = devm_regulator_register(pmic->dev, &pmic->desc[id],
51c86b3e 1245 &config);
e5ce4208 1246 if (IS_ERR(rdev)) {
cac9e916 1247 dev_err(pmic->dev,
e5ce4208 1248 "failed to register %s regulator\n",
cac9e916 1249 pdev_name);
51c86b3e 1250 return PTR_ERR(rdev);
e5ce4208
GG		 1251 }
1252
1253 /* Save regulator for cleanup */
1254 pmic->rdev[id] = rdev;
1255 }
1256
cac9e916
K		 1257 return 0;
1258}
e5ce4208 1259
d6f83370
K		 1260static int tps65917_smps_registration(struct palmas_pmic *pmic,
1261 struct palmas_pmic_driver_data *ddata,
1262 struct palmas_pmic_platform_data *pdata,
1263 const char *pdev_name,
1264 struct regulator_config config)
1265{
1266 int id, ret;
1267 unsigned int addr, reg;
1268 struct regulator_dev *rdev;
1269 struct palmas_reg_init *reg_init;
1270
1271 for (id = ddata->smps_start; id <= ddata->smps_end; id++) {
1272 /*
1273 * Miss out regulators which are not available due
1274 * to slaving configurations.
1275 */
1276 pmic->desc[id].n_linear_ranges = 3;
1277 if ((id == TPS65917_REG_SMPS2) && pmic->smps12)
1278 continue;
1279
1280 /* Initialise sleep/init values from platform data */
1281 if (pdata && pdata->reg_init[id]) {
1282 reg_init = pdata->reg_init[id];
1283 ret = palmas_smps_init(pmic->palmas, id, reg_init);
1284 if (ret)
1285 return ret;
1286 } else {
1287 reg_init = NULL;
1288 }
1289
1290 /* Register the regulators */
1291 pmic->desc[id].name = ddata->palmas_regs_info[id].name;
1292 pmic->desc[id].id = id;
1293
1294 /*
1295 * Read and store the RANGE bit for later use
1296 * This must be done before regulator is probed,
1297 * otherwise we error in probe with unsupportable
1298 * ranges. Read the current smps mode for later use.
1299 */
1300 addr = ddata->palmas_regs_info[id].vsel_addr;
1301
1302 ret = palmas_smps_read(pmic->palmas, addr, &reg);
1303 if (ret)
1304 return ret;
1305 if (reg & TPS65917_SMPS1_VOLTAGE_RANGE)
1306 pmic->range[id] = 1;
1307
1308 if (pmic->range[id])
1309 pmic->desc[id].linear_ranges = smps_high_ranges;
1310 else
1311 pmic->desc[id].linear_ranges = smps_low_ranges;
1312
1313
1314 if (reg_init && reg_init->roof_floor)
1315 pmic->desc[id].ops =
1316 &tps65917_ops_ext_control_smps;
1317 else
1318 pmic->desc[id].ops = &tps65917_ops_smps;
1319 pmic->desc[id].n_voltages = PALMAS_SMPS_NUM_VOLTAGES;
1320 pmic->desc[id].vsel_reg =
1321 PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1322 tps65917_regs_info[id].vsel_addr);
1323 pmic->desc[id].vsel_mask =
1324 PALMAS_SMPS12_VOLTAGE_VSEL_MASK;
1325
1326 pmic->desc[id].ramp_delay = 2500;
1327
1328 /* Read the smps mode for later use. */
1329 addr = ddata->palmas_regs_info[id].ctrl_addr;
1330 ret = palmas_smps_read(pmic->palmas, addr, &reg);
1331 if (ret)
1332 return ret;
1333 pmic->current_reg_mode[id] = reg &
1334 PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
1335
1336 pmic->desc[id].type = REGULATOR_VOLTAGE;
1337 pmic->desc[id].owner = THIS_MODULE;
1338
1339 if (pdata)
1340 config.init_data = pdata->reg_data[id];
1341 else
1342 config.init_data = NULL;
1343
1344 pmic->desc[id].supply_name = ddata->palmas_regs_info[id].sname;
1345 config.of_node = ddata->palmas_matches[id].of_node;
1346
1347 rdev = devm_regulator_register(pmic->dev, &pmic->desc[id],
1348 &config);
1349 if (IS_ERR(rdev)) {
1350 dev_err(pmic->dev,
1351 "failed to register %s regulator\n",
1352 pdev_name);
1353 return PTR_ERR(rdev);
1354 }
1355
1356 /* Save regulator for cleanup */
1357 pmic->rdev[id] = rdev;
1358 }
1359
1360 return 0;
1361}
1362
cac9e916
K		 1363static struct of_regulator_match palmas_matches[] = {
1364 { .name = "smps12", },
1365 { .name = "smps123", },
1366 { .name = "smps3", },
1367 { .name = "smps45", },
1368 { .name = "smps457", },
1369 { .name = "smps6", },
1370 { .name = "smps7", },
1371 { .name = "smps8", },
1372 { .name = "smps9", },
1373 { .name = "smps10_out2", },
1374 { .name = "smps10_out1", },
1375 { .name = "ldo1", },
1376 { .name = "ldo2", },
1377 { .name = "ldo3", },
1378 { .name = "ldo4", },
1379 { .name = "ldo5", },
1380 { .name = "ldo6", },
1381 { .name = "ldo7", },
1382 { .name = "ldo8", },
1383 { .name = "ldo9", },
1384 { .name = "ldoln", },
1385 { .name = "ldousb", },
1386 { .name = "regen1", },
1387 { .name = "regen2", },
1388 { .name = "regen3", },
1389 { .name = "sysen1", },
1390 { .name = "sysen2", },
1391};
e5ce4208 1392
d6f83370
K		 1393static struct of_regulator_match tps65917_matches[] = {
1394 { .name = "smps1", },
1395 { .name = "smps2", },
1396 { .name = "smps3", },
1397 { .name = "smps4", },
1398 { .name = "smps5", },
1399 { .name = "ldo1", },
1400 { .name = "ldo2", },
1401 { .name = "ldo3", },
1402 { .name = "ldo4", },
1403 { .name = "ldo5", },
1404 { .name = "regen1", },
1405 { .name = "regen2", },
1406 { .name = "regen3", },
1407 { .name = "sysen1", },
1408 { .name = "sysen2", },
1409};
1410
4b09e17b 1411static struct palmas_pmic_driver_data palmas_ddata = {
cac9e916
K		 1412 .smps_start = PALMAS_REG_SMPS12,
1413 .smps_end = PALMAS_REG_SMPS10_OUT1,
1414 .ldo_begin = PALMAS_REG_LDO1,
1415 .ldo_end = PALMAS_REG_LDOUSB,
1416 .max_reg = PALMAS_NUM_REGS,
1417 .palmas_regs_info = palmas_regs_info,
1418 .palmas_matches = palmas_matches,
1419 .sleep_req_info = palma_sleep_req_info,
1420 .smps_register = palmas_smps_registration,
1421 .ldo_register = palmas_ldo_registration,
1422};
aa07f027 1423
4b09e17b 1424static struct palmas_pmic_driver_data tps65917_ddata = {
d6f83370
K		 1425 .smps_start = TPS65917_REG_SMPS1,
1426 .smps_end = TPS65917_REG_SMPS5,
1427 .ldo_begin = TPS65917_REG_LDO1,
1428 .ldo_end = TPS65917_REG_LDO5,
1429 .max_reg = TPS65917_NUM_REGS,
1430 .palmas_regs_info = tps65917_regs_info,
1431 .palmas_matches = tps65917_matches,
1432 .sleep_req_info = tps65917_sleep_req_info,
1433 .smps_register = tps65917_smps_registration,
1434 .ldo_register = tps65917_ldo_registration,
1435};
1436
cac9e916
K		 1437static void palmas_dt_to_pdata(struct device *dev,
1438 struct device_node *node,
1439 struct palmas_pmic_platform_data *pdata,
1440 struct palmas_pmic_driver_data *ddata)
1441{
1442 struct device_node *regulators;
1443 u32 prop;
1444 int idx, ret;
17c11a76 1445
cac9e916
K		 1446 node = of_node_get(node);
1447 regulators = of_get_child_by_name(node, "regulators");
1448 if (!regulators) {
1449 dev_info(dev, "regulator node not found\n");
1450 return;
1451 }
087d30e3 1452
cac9e916
K		 1453 ret = of_regulator_match(dev, regulators, ddata->palmas_matches,
1454 ddata->max_reg);
1455 of_node_put(regulators);
1456 if (ret < 0) {
1457 dev_err(dev, "Error parsing regulator init data: %d\n", ret);
1458 return;
1459 }
e5ce4208 1460
cac9e916
K		 1461 for (idx = 0; idx < ddata->max_reg; idx++) {
1462 if (!ddata->palmas_matches[idx].init_data ||
1463 !ddata->palmas_matches[idx].of_node)
1464 continue;
e5ce4208 1465
cac9e916 1466 pdata->reg_data[idx] = ddata->palmas_matches[idx].init_data;
a361cd9f 1467
cac9e916
K		 1468 pdata->reg_init[idx] = devm_kzalloc(dev,
1469 sizeof(struct palmas_reg_init), GFP_KERNEL);
e5ce4208 1470
cac9e916
K		 1471 pdata->reg_init[idx]->warm_reset =
1472 of_property_read_bool(ddata->palmas_matches[idx].of_node,
1473 "ti,warm-reset");
e5ce4208 1474
cac9e916
K		 1475 ret = of_property_read_u32(ddata->palmas_matches[idx].of_node,
1476 "ti,roof-floor", &prop);
1477 /* EINVAL: Property not found */
1478 if (ret != -EINVAL) {
1479 int econtrol;
1480
1481 /* use default value, when no value is specified */
1482 econtrol = PALMAS_EXT_CONTROL_NSLEEP;
1483 if (!ret) {
1484 switch (prop) {
1485 case 1:
1486 econtrol = PALMAS_EXT_CONTROL_ENABLE1;
1487 break;
1488 case 2:
1489 econtrol = PALMAS_EXT_CONTROL_ENABLE2;
1490 break;
1491 case 3:
1492 econtrol = PALMAS_EXT_CONTROL_NSLEEP;
1493 break;
1494 default:
1495 WARN_ON(1);
1496 dev_warn(dev,
1497 "%s: Invalid roof-floor option: %u\n",
1498 palmas_matches[idx].name, prop);
1499 break;
1500 }
e5ce4208 1501 }
cac9e916 1502 pdata->reg_init[idx]->roof_floor = econtrol;
e5ce4208 1503 }
e5ce4208 1504
cac9e916
K		 1505 ret = of_property_read_u32(ddata->palmas_matches[idx].of_node,
1506 "ti,mode-sleep", &prop);
1507 if (!ret)
1508 pdata->reg_init[idx]->mode_sleep = prop;
17c11a76 1509
cac9e916
K		 1510 ret = of_property_read_bool(ddata->palmas_matches[idx].of_node,
1511 "ti,smps-range");
1512 if (ret)
1513 pdata->reg_init[idx]->vsel =
1514 PALMAS_SMPS12_VOLTAGE_RANGE;
1515
1516 if (idx == PALMAS_REG_LDO8)
1517 pdata->enable_ldo8_tracking = of_property_read_bool(
1518 ddata->palmas_matches[idx].of_node,
1519 "ti,enable-ldo8-tracking");
1520 }
1521
1522 pdata->ldo6_vibrator = of_property_read_bool(node, "ti,ldo6-vibrator");
e5ce4208
GG		 1523}
1524
cac9e916
K		 1525static struct of_device_id of_palmas_match_tbl[] = {
1526 {
1527 .compatible = "ti,palmas-pmic",
1528 .data = &palmas_ddata,
1529 },
1530 {
1531 .compatible = "ti,twl6035-pmic",
1532 .data = &palmas_ddata,
1533 },
1534 {
1535 .compatible = "ti,twl6036-pmic",
1536 .data = &palmas_ddata,
1537 },
1538 {
1539 .compatible = "ti,twl6037-pmic",
1540 .data = &palmas_ddata,
1541 },
1542 {
1543 .compatible = "ti,tps65913-pmic",
1544 .data = &palmas_ddata,
1545 },
1546 {
1547 .compatible = "ti,tps65914-pmic",
1548 .data = &palmas_ddata,
1549 },
1550 {
1551 .compatible = "ti,tps80036-pmic",
1552 .data = &palmas_ddata,
1553 },
1554 {
1555 .compatible = "ti,tps659038-pmic",
1556 .data = &palmas_ddata,
d6f83370
K		 1557 },
1558 {
1559 .compatible = "ti,tps65917-pmic",
1560 .data = &tps65917_ddata,
cac9e916 1561 },
a361cd9f
GG		 1562 { /* end */ }
1563};
1564
cac9e916
K		 1565static int palmas_regulators_probe(struct platform_device *pdev)
1566{
1567 struct palmas *palmas = dev_get_drvdata(pdev->dev.parent);
1568 struct palmas_pmic_platform_data *pdata = dev_get_platdata(&pdev->dev);
1569 struct device_node *node = pdev->dev.of_node;
1570 struct palmas_pmic_driver_data *driver_data;
1571 struct regulator_config config = { };
1572 struct palmas_pmic *pmic;
1573 const char *pdev_name;
1574 const struct of_device_id *match;
1575 int ret = 0;
1576 unsigned int reg;
1577
1578 match = of_match_device(of_match_ptr(of_palmas_match_tbl), &pdev->dev);
1579
1580 if (!match)
1581 return -ENODATA;
1582
1583 driver_data = (struct palmas_pmic_driver_data *)match->data;
1584 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1585 if (!pdata)
1586 return -ENOMEM;
1587
1588 pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
1589 if (!pmic)
1590 return -ENOMEM;
1591
1592 pmic->dev = &pdev->dev;
1593 pmic->palmas = palmas;
1594 palmas->pmic = pmic;
1595 platform_set_drvdata(pdev, pmic);
1596 pmic->palmas->pmic_ddata = driver_data;
1597
1598 palmas_dt_to_pdata(&pdev->dev, node, pdata, driver_data);
1599
1600 ret = palmas_smps_read(palmas, PALMAS_SMPS_CTRL, &reg);
1601 if (ret)
1602 return ret;
1603
1604 if (reg & PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN)
1605 pmic->smps123 = 1;
1606
1607 if (reg & PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN)
1608 pmic->smps457 = 1;
1609
1610 config.regmap = palmas->regmap[REGULATOR_SLAVE];
1611 config.dev = &pdev->dev;
1612 config.driver_data = pmic;
1613 pdev_name = pdev->name;
1614
1615 ret = driver_data->smps_register(pmic, driver_data, pdata, pdev_name,
1616 config);
1617 if (ret)
1618 return ret;
1619
1620 ret = driver_data->ldo_register(pmic, driver_data, pdata, pdev_name,
1621 config);
1622
1623 return ret;
1624}
1625
e5ce4208
GG		 1626static struct platform_driver palmas_driver = {
1627 .driver = {
1628 .name = "palmas-pmic",
a361cd9f 1629 .of_match_table = of_palmas_match_tbl,
e5ce4208
GG		 1630 .owner = THIS_MODULE,
1631 },
bbcf50b1 1632 .probe = palmas_regulators_probe,
e5ce4208
GG		 1633};
1634
1635static int __init palmas_init(void)
1636{
1637 return platform_driver_register(&palmas_driver);
1638}
1639subsys_initcall(palmas_init);
1640
1641static void __exit palmas_exit(void)
1642{
1643 platform_driver_unregister(&palmas_driver);
1644}
1645module_exit(palmas_exit);
1646
1647MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
1648MODULE_DESCRIPTION("Palmas voltage regulator driver");
1649MODULE_LICENSE("GPL");
1650MODULE_ALIAS("platform:palmas-pmic");
a361cd9f 1651MODULE_DEVICE_TABLE(of, of_palmas_match_tbl);
Linux kernel - Deliverables
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