Commit | Line | Data |
---|---|---|
fa16a5c1 | 1 | /* |
c4aa6f31 | 2 | * twl-regulator.c -- support regulators in twl4030/twl6030 family chips |
fa16a5c1 DB |
3 | * |
4 | * Copyright (C) 2008 David Brownell | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/err.h> | |
53b8a9d9 | 15 | #include <linux/delay.h> |
fa16a5c1 DB |
16 | #include <linux/platform_device.h> |
17 | #include <linux/regulator/driver.h> | |
18 | #include <linux/regulator/machine.h> | |
b07682b6 | 19 | #include <linux/i2c/twl.h> |
fa16a5c1 DB |
20 | |
21 | ||
22 | /* | |
c4aa6f31 | 23 | * The TWL4030/TW5030/TPS659x0/TWL6030 family chips include power management, a |
fa16a5c1 DB |
24 | * USB OTG transceiver, an RTC, ADC, PWM, and lots more. Some versions |
25 | * include an audio codec, battery charger, and more voltage regulators. | |
26 | * These chips are often used in OMAP-based systems. | |
27 | * | |
28 | * This driver implements software-based resource control for various | |
29 | * voltage regulators. This is usually augmented with state machine | |
30 | * based control. | |
31 | */ | |
32 | ||
33 | struct twlreg_info { | |
34 | /* start of regulator's PM_RECEIVER control register bank */ | |
35 | u8 base; | |
36 | ||
c4aa6f31 | 37 | /* twl resource ID, for resource control state machine */ |
fa16a5c1 DB |
38 | u8 id; |
39 | ||
40 | /* voltage in mV = table[VSEL]; table_len must be a power-of-two */ | |
41 | u8 table_len; | |
42 | const u16 *table; | |
43 | ||
045f972f JKS |
44 | /* regulator specific turn-on delay */ |
45 | u16 delay; | |
46 | ||
47 | /* State REMAP default configuration */ | |
48 | u8 remap; | |
49 | ||
fa16a5c1 DB |
50 | /* chip constraints on regulator behavior */ |
51 | u16 min_mV; | |
3e3d3be7 | 52 | u16 max_mV; |
fa16a5c1 DB |
53 | |
54 | /* used by regulator core */ | |
55 | struct regulator_desc desc; | |
56 | }; | |
57 | ||
58 | ||
59 | /* LDO control registers ... offset is from the base of its register bank. | |
60 | * The first three registers of all power resource banks help hardware to | |
61 | * manage the various resource groups. | |
62 | */ | |
441a4505 | 63 | /* Common offset in TWL4030/6030 */ |
fa16a5c1 | 64 | #define VREG_GRP 0 |
441a4505 | 65 | /* TWL4030 register offsets */ |
fa16a5c1 DB |
66 | #define VREG_TYPE 1 |
67 | #define VREG_REMAP 2 | |
68 | #define VREG_DEDICATED 3 /* LDO control */ | |
441a4505 RN |
69 | /* TWL6030 register offsets */ |
70 | #define VREG_TRANS 1 | |
71 | #define VREG_STATE 2 | |
72 | #define VREG_VOLTAGE 3 | |
73 | /* TWL6030 Misc register offsets */ | |
74 | #define VREG_BC_ALL 1 | |
75 | #define VREG_BC_REF 2 | |
76 | #define VREG_BC_PROC 3 | |
77 | #define VREG_BC_CLK_RST 4 | |
fa16a5c1 DB |
78 | |
79 | static inline int | |
441a4505 | 80 | twlreg_read(struct twlreg_info *info, unsigned slave_subgp, unsigned offset) |
fa16a5c1 DB |
81 | { |
82 | u8 value; | |
83 | int status; | |
84 | ||
441a4505 | 85 | status = twl_i2c_read_u8(slave_subgp, |
fa16a5c1 DB |
86 | &value, info->base + offset); |
87 | return (status < 0) ? status : value; | |
88 | } | |
89 | ||
90 | static inline int | |
441a4505 RN |
91 | twlreg_write(struct twlreg_info *info, unsigned slave_subgp, unsigned offset, |
92 | u8 value) | |
fa16a5c1 | 93 | { |
441a4505 | 94 | return twl_i2c_write_u8(slave_subgp, |
fa16a5c1 DB |
95 | value, info->base + offset); |
96 | } | |
97 | ||
98 | /*----------------------------------------------------------------------*/ | |
99 | ||
100 | /* generic power resource operations, which work on all regulators */ | |
101 | ||
c4aa6f31 | 102 | static int twlreg_grp(struct regulator_dev *rdev) |
fa16a5c1 | 103 | { |
441a4505 RN |
104 | return twlreg_read(rdev_get_drvdata(rdev), TWL_MODULE_PM_RECEIVER, |
105 | VREG_GRP); | |
fa16a5c1 DB |
106 | } |
107 | ||
108 | /* | |
109 | * Enable/disable regulators by joining/leaving the P1 (processor) group. | |
110 | * We assume nobody else is updating the DEV_GRP registers. | |
111 | */ | |
441a4505 RN |
112 | /* definition for 4030 family */ |
113 | #define P3_GRP_4030 BIT(7) /* "peripherals" */ | |
114 | #define P2_GRP_4030 BIT(6) /* secondary processor, modem, etc */ | |
115 | #define P1_GRP_4030 BIT(5) /* CPU/Linux */ | |
116 | /* definition for 6030 family */ | |
117 | #define P3_GRP_6030 BIT(2) /* secondary processor, modem, etc */ | |
118 | #define P2_GRP_6030 BIT(1) /* "peripherals" */ | |
119 | #define P1_GRP_6030 BIT(0) /* CPU/Linux */ | |
fa16a5c1 | 120 | |
c4aa6f31 | 121 | static int twlreg_is_enabled(struct regulator_dev *rdev) |
fa16a5c1 | 122 | { |
c4aa6f31 | 123 | int state = twlreg_grp(rdev); |
fa16a5c1 DB |
124 | |
125 | if (state < 0) | |
126 | return state; | |
127 | ||
441a4505 RN |
128 | if (twl_class_is_4030()) |
129 | state &= P1_GRP_4030; | |
130 | else | |
131 | state &= P1_GRP_6030; | |
132 | return state; | |
fa16a5c1 DB |
133 | } |
134 | ||
c4aa6f31 | 135 | static int twlreg_enable(struct regulator_dev *rdev) |
fa16a5c1 DB |
136 | { |
137 | struct twlreg_info *info = rdev_get_drvdata(rdev); | |
138 | int grp; | |
53b8a9d9 | 139 | int ret; |
fa16a5c1 | 140 | |
441a4505 | 141 | grp = twlreg_read(info, TWL_MODULE_PM_RECEIVER, VREG_GRP); |
fa16a5c1 DB |
142 | if (grp < 0) |
143 | return grp; | |
144 | ||
441a4505 RN |
145 | if (twl_class_is_4030()) |
146 | grp |= P1_GRP_4030; | |
147 | else | |
148 | grp |= P1_GRP_6030; | |
149 | ||
53b8a9d9 JKS |
150 | ret = twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_GRP, grp); |
151 | ||
152 | udelay(info->delay); | |
153 | ||
154 | return ret; | |
fa16a5c1 DB |
155 | } |
156 | ||
c4aa6f31 | 157 | static int twlreg_disable(struct regulator_dev *rdev) |
fa16a5c1 DB |
158 | { |
159 | struct twlreg_info *info = rdev_get_drvdata(rdev); | |
160 | int grp; | |
161 | ||
441a4505 | 162 | grp = twlreg_read(info, TWL_MODULE_PM_RECEIVER, VREG_GRP); |
fa16a5c1 DB |
163 | if (grp < 0) |
164 | return grp; | |
165 | ||
441a4505 | 166 | if (twl_class_is_4030()) |
cf9836f4 | 167 | grp &= ~(P1_GRP_4030 | P2_GRP_4030 | P3_GRP_4030); |
441a4505 | 168 | else |
cf9836f4 | 169 | grp &= ~(P1_GRP_6030 | P2_GRP_6030 | P3_GRP_6030); |
441a4505 RN |
170 | |
171 | return twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_GRP, grp); | |
fa16a5c1 DB |
172 | } |
173 | ||
c4aa6f31 | 174 | static int twlreg_get_status(struct regulator_dev *rdev) |
fa16a5c1 | 175 | { |
c4aa6f31 | 176 | int state = twlreg_grp(rdev); |
fa16a5c1 | 177 | |
441a4505 RN |
178 | if (twl_class_is_6030()) |
179 | return 0; /* FIXME return for 6030 regulator */ | |
180 | ||
fa16a5c1 DB |
181 | if (state < 0) |
182 | return state; | |
183 | state &= 0x0f; | |
184 | ||
185 | /* assume state != WARM_RESET; we'd not be running... */ | |
186 | if (!state) | |
187 | return REGULATOR_STATUS_OFF; | |
188 | return (state & BIT(3)) | |
189 | ? REGULATOR_STATUS_NORMAL | |
190 | : REGULATOR_STATUS_STANDBY; | |
191 | } | |
192 | ||
c4aa6f31 | 193 | static int twlreg_set_mode(struct regulator_dev *rdev, unsigned mode) |
fa16a5c1 DB |
194 | { |
195 | struct twlreg_info *info = rdev_get_drvdata(rdev); | |
196 | unsigned message; | |
197 | int status; | |
198 | ||
441a4505 RN |
199 | if (twl_class_is_6030()) |
200 | return 0; /* FIXME return for 6030 regulator */ | |
201 | ||
fa16a5c1 DB |
202 | /* We can only set the mode through state machine commands... */ |
203 | switch (mode) { | |
204 | case REGULATOR_MODE_NORMAL: | |
205 | message = MSG_SINGULAR(DEV_GRP_P1, info->id, RES_STATE_ACTIVE); | |
206 | break; | |
207 | case REGULATOR_MODE_STANDBY: | |
208 | message = MSG_SINGULAR(DEV_GRP_P1, info->id, RES_STATE_SLEEP); | |
209 | break; | |
210 | default: | |
211 | return -EINVAL; | |
212 | } | |
213 | ||
214 | /* Ensure the resource is associated with some group */ | |
c4aa6f31 | 215 | status = twlreg_grp(rdev); |
fa16a5c1 DB |
216 | if (status < 0) |
217 | return status; | |
441a4505 | 218 | if (!(status & (P3_GRP_4030 | P2_GRP_4030 | P1_GRP_4030))) |
fa16a5c1 DB |
219 | return -EACCES; |
220 | ||
c4aa6f31 | 221 | status = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, |
b9e26bc8 AL |
222 | message >> 8, TWL4030_PM_MASTER_PB_WORD_MSB); |
223 | if (status < 0) | |
fa16a5c1 DB |
224 | return status; |
225 | ||
c4aa6f31 | 226 | return twl_i2c_write_u8(TWL_MODULE_PM_MASTER, |
b9e26bc8 | 227 | message & 0xff, TWL4030_PM_MASTER_PB_WORD_LSB); |
fa16a5c1 DB |
228 | } |
229 | ||
230 | /*----------------------------------------------------------------------*/ | |
231 | ||
232 | /* | |
233 | * Support for adjustable-voltage LDOs uses a four bit (or less) voltage | |
234 | * select field in its control register. We use tables indexed by VSEL | |
235 | * to record voltages in milliVolts. (Accuracy is about three percent.) | |
236 | * | |
237 | * Note that VSEL values for VAUX2 changed in twl5030 and newer silicon; | |
238 | * currently handled by listing two slightly different VAUX2 regulators, | |
239 | * only one of which will be configured. | |
240 | * | |
241 | * VSEL values documented as "TI cannot support these values" are flagged | |
242 | * in these tables as UNSUP() values; we normally won't assign them. | |
d6bb69cf AH |
243 | * |
244 | * VAUX3 at 3V is incorrectly listed in some TI manuals as unsupported. | |
245 | * TI are revising the twl5030/tps659x0 specs to support that 3.0V setting. | |
fa16a5c1 DB |
246 | */ |
247 | #ifdef CONFIG_TWL4030_ALLOW_UNSUPPORTED | |
248 | #define UNSUP_MASK 0x0000 | |
249 | #else | |
250 | #define UNSUP_MASK 0x8000 | |
251 | #endif | |
252 | ||
253 | #define UNSUP(x) (UNSUP_MASK | (x)) | |
254 | #define IS_UNSUP(x) (UNSUP_MASK & (x)) | |
255 | #define LDO_MV(x) (~UNSUP_MASK & (x)) | |
256 | ||
257 | ||
258 | static const u16 VAUX1_VSEL_table[] = { | |
259 | UNSUP(1500), UNSUP(1800), 2500, 2800, | |
260 | 3000, 3000, 3000, 3000, | |
261 | }; | |
262 | static const u16 VAUX2_4030_VSEL_table[] = { | |
263 | UNSUP(1000), UNSUP(1000), UNSUP(1200), 1300, | |
264 | 1500, 1800, UNSUP(1850), 2500, | |
265 | UNSUP(2600), 2800, UNSUP(2850), UNSUP(3000), | |
266 | UNSUP(3150), UNSUP(3150), UNSUP(3150), UNSUP(3150), | |
267 | }; | |
268 | static const u16 VAUX2_VSEL_table[] = { | |
269 | 1700, 1700, 1900, 1300, | |
270 | 1500, 1800, 2000, 2500, | |
271 | 2100, 2800, 2200, 2300, | |
272 | 2400, 2400, 2400, 2400, | |
273 | }; | |
274 | static const u16 VAUX3_VSEL_table[] = { | |
275 | 1500, 1800, 2500, 2800, | |
d6bb69cf | 276 | 3000, 3000, 3000, 3000, |
fa16a5c1 DB |
277 | }; |
278 | static const u16 VAUX4_VSEL_table[] = { | |
279 | 700, 1000, 1200, UNSUP(1300), | |
280 | 1500, 1800, UNSUP(1850), 2500, | |
1897e742 DB |
281 | UNSUP(2600), 2800, UNSUP(2850), UNSUP(3000), |
282 | UNSUP(3150), UNSUP(3150), UNSUP(3150), UNSUP(3150), | |
fa16a5c1 DB |
283 | }; |
284 | static const u16 VMMC1_VSEL_table[] = { | |
285 | 1850, 2850, 3000, 3150, | |
286 | }; | |
287 | static const u16 VMMC2_VSEL_table[] = { | |
288 | UNSUP(1000), UNSUP(1000), UNSUP(1200), UNSUP(1300), | |
289 | UNSUP(1500), UNSUP(1800), 1850, UNSUP(2500), | |
290 | 2600, 2800, 2850, 3000, | |
291 | 3150, 3150, 3150, 3150, | |
292 | }; | |
293 | static const u16 VPLL1_VSEL_table[] = { | |
294 | 1000, 1200, 1300, 1800, | |
295 | UNSUP(2800), UNSUP(3000), UNSUP(3000), UNSUP(3000), | |
296 | }; | |
297 | static const u16 VPLL2_VSEL_table[] = { | |
298 | 700, 1000, 1200, 1300, | |
299 | UNSUP(1500), 1800, UNSUP(1850), UNSUP(2500), | |
300 | UNSUP(2600), UNSUP(2800), UNSUP(2850), UNSUP(3000), | |
301 | UNSUP(3150), UNSUP(3150), UNSUP(3150), UNSUP(3150), | |
302 | }; | |
303 | static const u16 VSIM_VSEL_table[] = { | |
304 | UNSUP(1000), UNSUP(1200), UNSUP(1300), 1800, | |
305 | 2800, 3000, 3000, 3000, | |
306 | }; | |
307 | static const u16 VDAC_VSEL_table[] = { | |
308 | 1200, 1300, 1800, 1800, | |
309 | }; | |
07fc493f JKS |
310 | static const u16 VDD1_VSEL_table[] = { |
311 | 800, 1450, | |
312 | }; | |
313 | static const u16 VDD2_VSEL_table[] = { | |
314 | 800, 1450, 1500, | |
315 | }; | |
316 | static const u16 VIO_VSEL_table[] = { | |
317 | 1800, 1850, | |
318 | }; | |
319 | static const u16 VINTANA2_VSEL_table[] = { | |
320 | 2500, 2750, | |
321 | }; | |
fa16a5c1 | 322 | |
3e3d3be7 | 323 | static int twl4030ldo_list_voltage(struct regulator_dev *rdev, unsigned index) |
66b659e6 DB |
324 | { |
325 | struct twlreg_info *info = rdev_get_drvdata(rdev); | |
326 | int mV = info->table[index]; | |
327 | ||
328 | return IS_UNSUP(mV) ? 0 : (LDO_MV(mV) * 1000); | |
329 | } | |
330 | ||
fa16a5c1 | 331 | static int |
3a93f2a9 MB |
332 | twl4030ldo_set_voltage(struct regulator_dev *rdev, int min_uV, int max_uV, |
333 | unsigned *selector) | |
fa16a5c1 DB |
334 | { |
335 | struct twlreg_info *info = rdev_get_drvdata(rdev); | |
336 | int vsel; | |
337 | ||
338 | for (vsel = 0; vsel < info->table_len; vsel++) { | |
339 | int mV = info->table[vsel]; | |
340 | int uV; | |
341 | ||
342 | if (IS_UNSUP(mV)) | |
343 | continue; | |
344 | uV = LDO_MV(mV) * 1000; | |
345 | ||
66b659e6 DB |
346 | /* REVISIT for VAUX2, first match may not be best/lowest */ |
347 | ||
fa16a5c1 | 348 | /* use the first in-range value */ |
3a93f2a9 MB |
349 | if (min_uV <= uV && uV <= max_uV) { |
350 | *selector = vsel; | |
441a4505 RN |
351 | return twlreg_write(info, TWL_MODULE_PM_RECEIVER, |
352 | VREG_VOLTAGE, vsel); | |
3a93f2a9 | 353 | } |
fa16a5c1 DB |
354 | } |
355 | ||
356 | return -EDOM; | |
357 | } | |
358 | ||
3e3d3be7 | 359 | static int twl4030ldo_get_voltage(struct regulator_dev *rdev) |
fa16a5c1 DB |
360 | { |
361 | struct twlreg_info *info = rdev_get_drvdata(rdev); | |
441a4505 RN |
362 | int vsel = twlreg_read(info, TWL_MODULE_PM_RECEIVER, |
363 | VREG_VOLTAGE); | |
fa16a5c1 DB |
364 | |
365 | if (vsel < 0) | |
366 | return vsel; | |
367 | ||
368 | vsel &= info->table_len - 1; | |
369 | return LDO_MV(info->table[vsel]) * 1000; | |
370 | } | |
371 | ||
3e3d3be7 RN |
372 | static struct regulator_ops twl4030ldo_ops = { |
373 | .list_voltage = twl4030ldo_list_voltage, | |
66b659e6 | 374 | |
3e3d3be7 RN |
375 | .set_voltage = twl4030ldo_set_voltage, |
376 | .get_voltage = twl4030ldo_get_voltage, | |
377 | ||
378 | .enable = twlreg_enable, | |
379 | .disable = twlreg_disable, | |
380 | .is_enabled = twlreg_is_enabled, | |
381 | ||
382 | .set_mode = twlreg_set_mode, | |
383 | ||
384 | .get_status = twlreg_get_status, | |
385 | }; | |
386 | ||
387 | static int twl6030ldo_list_voltage(struct regulator_dev *rdev, unsigned index) | |
388 | { | |
389 | struct twlreg_info *info = rdev_get_drvdata(rdev); | |
390 | ||
391 | return ((info->min_mV + (index * 100)) * 1000); | |
392 | } | |
393 | ||
394 | static int | |
3a93f2a9 MB |
395 | twl6030ldo_set_voltage(struct regulator_dev *rdev, int min_uV, int max_uV, |
396 | unsigned *selector) | |
3e3d3be7 RN |
397 | { |
398 | struct twlreg_info *info = rdev_get_drvdata(rdev); | |
399 | int vsel; | |
400 | ||
401 | if ((min_uV/1000 < info->min_mV) || (max_uV/1000 > info->max_mV)) | |
402 | return -EDOM; | |
403 | ||
404 | /* | |
405 | * Use the below formula to calculate vsel | |
406 | * mV = 1000mv + 100mv * (vsel - 1) | |
407 | */ | |
408 | vsel = (min_uV/1000 - 1000)/100 + 1; | |
3a93f2a9 | 409 | *selector = vsel; |
3e3d3be7 RN |
410 | return twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_VOLTAGE, vsel); |
411 | ||
412 | } | |
413 | ||
414 | static int twl6030ldo_get_voltage(struct regulator_dev *rdev) | |
415 | { | |
416 | struct twlreg_info *info = rdev_get_drvdata(rdev); | |
417 | int vsel = twlreg_read(info, TWL_MODULE_PM_RECEIVER, | |
418 | VREG_VOLTAGE); | |
419 | ||
420 | if (vsel < 0) | |
421 | return vsel; | |
422 | ||
423 | /* | |
424 | * Use the below formula to calculate vsel | |
425 | * mV = 1000mv + 100mv * (vsel - 1) | |
426 | */ | |
427 | return (1000 + (100 * (vsel - 1))) * 1000; | |
428 | } | |
429 | ||
430 | static struct regulator_ops twl6030ldo_ops = { | |
431 | .list_voltage = twl6030ldo_list_voltage, | |
432 | ||
433 | .set_voltage = twl6030ldo_set_voltage, | |
434 | .get_voltage = twl6030ldo_get_voltage, | |
fa16a5c1 | 435 | |
c4aa6f31 RN |
436 | .enable = twlreg_enable, |
437 | .disable = twlreg_disable, | |
438 | .is_enabled = twlreg_is_enabled, | |
fa16a5c1 | 439 | |
c4aa6f31 | 440 | .set_mode = twlreg_set_mode, |
fa16a5c1 | 441 | |
c4aa6f31 | 442 | .get_status = twlreg_get_status, |
fa16a5c1 DB |
443 | }; |
444 | ||
445 | /*----------------------------------------------------------------------*/ | |
446 | ||
447 | /* | |
448 | * Fixed voltage LDOs don't have a VSEL field to update. | |
449 | */ | |
c4aa6f31 | 450 | static int twlfixed_list_voltage(struct regulator_dev *rdev, unsigned index) |
66b659e6 DB |
451 | { |
452 | struct twlreg_info *info = rdev_get_drvdata(rdev); | |
453 | ||
454 | return info->min_mV * 1000; | |
455 | } | |
456 | ||
c4aa6f31 | 457 | static int twlfixed_get_voltage(struct regulator_dev *rdev) |
fa16a5c1 DB |
458 | { |
459 | struct twlreg_info *info = rdev_get_drvdata(rdev); | |
460 | ||
461 | return info->min_mV * 1000; | |
462 | } | |
463 | ||
c4aa6f31 RN |
464 | static struct regulator_ops twlfixed_ops = { |
465 | .list_voltage = twlfixed_list_voltage, | |
66b659e6 | 466 | |
c4aa6f31 | 467 | .get_voltage = twlfixed_get_voltage, |
fa16a5c1 | 468 | |
c4aa6f31 RN |
469 | .enable = twlreg_enable, |
470 | .disable = twlreg_disable, | |
471 | .is_enabled = twlreg_is_enabled, | |
fa16a5c1 | 472 | |
c4aa6f31 | 473 | .set_mode = twlreg_set_mode, |
fa16a5c1 | 474 | |
c4aa6f31 | 475 | .get_status = twlreg_get_status, |
fa16a5c1 DB |
476 | }; |
477 | ||
478 | /*----------------------------------------------------------------------*/ | |
479 | ||
045f972f JKS |
480 | #define TWL4030_FIXED_LDO(label, offset, mVolts, num, turnon_delay, \ |
481 | remap_conf) \ | |
482 | TWL_FIXED_LDO(label, offset, mVolts, num, turnon_delay, \ | |
483 | remap_conf, TWL4030) | |
045f972f JKS |
484 | #define TWL6030_FIXED_LDO(label, offset, mVolts, num, turnon_delay, \ |
485 | remap_conf) \ | |
486 | TWL_FIXED_LDO(label, offset, mVolts, num, turnon_delay, \ | |
487 | remap_conf, TWL6030) | |
488 | ||
3e3d3be7 | 489 | #define TWL4030_ADJUSTABLE_LDO(label, offset, num, turnon_delay, remap_conf) { \ |
fa16a5c1 DB |
490 | .base = offset, \ |
491 | .id = num, \ | |
492 | .table_len = ARRAY_SIZE(label##_VSEL_table), \ | |
493 | .table = label##_VSEL_table, \ | |
045f972f JKS |
494 | .delay = turnon_delay, \ |
495 | .remap = remap_conf, \ | |
fa16a5c1 DB |
496 | .desc = { \ |
497 | .name = #label, \ | |
3e3d3be7 | 498 | .id = TWL4030_REG_##label, \ |
66b659e6 | 499 | .n_voltages = ARRAY_SIZE(label##_VSEL_table), \ |
3e3d3be7 RN |
500 | .ops = &twl4030ldo_ops, \ |
501 | .type = REGULATOR_VOLTAGE, \ | |
502 | .owner = THIS_MODULE, \ | |
503 | }, \ | |
504 | } | |
505 | ||
506 | #define TWL6030_ADJUSTABLE_LDO(label, offset, min_mVolts, max_mVolts, num, \ | |
507 | remap_conf) { \ | |
508 | .base = offset, \ | |
509 | .id = num, \ | |
510 | .min_mV = min_mVolts, \ | |
511 | .max_mV = max_mVolts, \ | |
512 | .remap = remap_conf, \ | |
513 | .desc = { \ | |
514 | .name = #label, \ | |
515 | .id = TWL6030_REG_##label, \ | |
516 | .n_voltages = (max_mVolts - min_mVolts)/100, \ | |
517 | .ops = &twl6030ldo_ops, \ | |
fa16a5c1 DB |
518 | .type = REGULATOR_VOLTAGE, \ |
519 | .owner = THIS_MODULE, \ | |
520 | }, \ | |
521 | } | |
522 | ||
3e3d3be7 | 523 | |
045f972f JKS |
524 | #define TWL_FIXED_LDO(label, offset, mVolts, num, turnon_delay, remap_conf, \ |
525 | family) { \ | |
fa16a5c1 DB |
526 | .base = offset, \ |
527 | .id = num, \ | |
528 | .min_mV = mVolts, \ | |
045f972f JKS |
529 | .delay = turnon_delay, \ |
530 | .remap = remap_conf, \ | |
fa16a5c1 DB |
531 | .desc = { \ |
532 | .name = #label, \ | |
c4aa6f31 | 533 | .id = family##_REG_##label, \ |
66b659e6 | 534 | .n_voltages = 1, \ |
c4aa6f31 | 535 | .ops = &twlfixed_ops, \ |
fa16a5c1 DB |
536 | .type = REGULATOR_VOLTAGE, \ |
537 | .owner = THIS_MODULE, \ | |
538 | }, \ | |
539 | } | |
540 | ||
541 | /* | |
542 | * We list regulators here if systems need some level of | |
543 | * software control over them after boot. | |
544 | */ | |
c4aa6f31 | 545 | static struct twlreg_info twl_regs[] = { |
045f972f JKS |
546 | TWL4030_ADJUSTABLE_LDO(VAUX1, 0x17, 1, 100, 0x08), |
547 | TWL4030_ADJUSTABLE_LDO(VAUX2_4030, 0x1b, 2, 100, 0x08), | |
548 | TWL4030_ADJUSTABLE_LDO(VAUX2, 0x1b, 2, 100, 0x08), | |
549 | TWL4030_ADJUSTABLE_LDO(VAUX3, 0x1f, 3, 100, 0x08), | |
550 | TWL4030_ADJUSTABLE_LDO(VAUX4, 0x23, 4, 100, 0x08), | |
551 | TWL4030_ADJUSTABLE_LDO(VMMC1, 0x27, 5, 100, 0x08), | |
552 | TWL4030_ADJUSTABLE_LDO(VMMC2, 0x2b, 6, 100, 0x08), | |
553 | TWL4030_ADJUSTABLE_LDO(VPLL1, 0x2f, 7, 100, 0x00), | |
554 | TWL4030_ADJUSTABLE_LDO(VPLL2, 0x33, 8, 100, 0x08), | |
555 | TWL4030_ADJUSTABLE_LDO(VSIM, 0x37, 9, 100, 0x00), | |
556 | TWL4030_ADJUSTABLE_LDO(VDAC, 0x3b, 10, 100, 0x08), | |
557 | TWL4030_FIXED_LDO(VINTANA1, 0x3f, 1500, 11, 100, 0x08), | |
558 | TWL4030_ADJUSTABLE_LDO(VINTANA2, 0x43, 12, 100, 0x08), | |
559 | TWL4030_FIXED_LDO(VINTDIG, 0x47, 1500, 13, 100, 0x08), | |
560 | TWL4030_ADJUSTABLE_LDO(VIO, 0x4b, 14, 1000, 0x08), | |
561 | TWL4030_ADJUSTABLE_LDO(VDD1, 0x55, 15, 1000, 0x08), | |
562 | TWL4030_ADJUSTABLE_LDO(VDD2, 0x63, 16, 1000, 0x08), | |
563 | TWL4030_FIXED_LDO(VUSB1V5, 0x71, 1500, 17, 100, 0x08), | |
564 | TWL4030_FIXED_LDO(VUSB1V8, 0x74, 1800, 18, 100, 0x08), | |
565 | TWL4030_FIXED_LDO(VUSB3V1, 0x77, 3100, 19, 150, 0x08), | |
fa16a5c1 | 566 | /* VUSBCP is managed *only* by the USB subchip */ |
441a4505 RN |
567 | |
568 | /* 6030 REG with base as PMC Slave Misc : 0x0030 */ | |
045f972f JKS |
569 | /* Turnon-delay and remap configuration values for 6030 are not |
570 | verified since the specification is not public */ | |
3e3d3be7 RN |
571 | TWL6030_ADJUSTABLE_LDO(VAUX1_6030, 0x54, 1000, 3300, 1, 0x21), |
572 | TWL6030_ADJUSTABLE_LDO(VAUX2_6030, 0x58, 1000, 3300, 2, 0x21), | |
573 | TWL6030_ADJUSTABLE_LDO(VAUX3_6030, 0x5c, 1000, 3300, 3, 0x21), | |
574 | TWL6030_ADJUSTABLE_LDO(VMMC, 0x68, 1000, 3300, 4, 0x21), | |
575 | TWL6030_ADJUSTABLE_LDO(VPP, 0x6c, 1000, 3300, 5, 0x21), | |
576 | TWL6030_ADJUSTABLE_LDO(VUSIM, 0x74, 1000, 3300, 7, 0x21), | |
2ebcf632 RN |
577 | TWL6030_FIXED_LDO(VANA, 0x50, 2100, 15, 0, 0x21), |
578 | TWL6030_FIXED_LDO(VCXIO, 0x60, 1800, 16, 0, 0x21), | |
579 | TWL6030_FIXED_LDO(VDAC, 0x64, 1800, 17, 0, 0x21), | |
580 | TWL6030_FIXED_LDO(VUSB, 0x70, 3300, 18, 0, 0x21) | |
fa16a5c1 DB |
581 | }; |
582 | ||
24c29020 | 583 | static int __devinit twlreg_probe(struct platform_device *pdev) |
fa16a5c1 DB |
584 | { |
585 | int i; | |
586 | struct twlreg_info *info; | |
587 | struct regulator_init_data *initdata; | |
588 | struct regulation_constraints *c; | |
589 | struct regulator_dev *rdev; | |
fa16a5c1 | 590 | |
c4aa6f31 RN |
591 | for (i = 0, info = NULL; i < ARRAY_SIZE(twl_regs); i++) { |
592 | if (twl_regs[i].desc.id != pdev->id) | |
fa16a5c1 | 593 | continue; |
c4aa6f31 | 594 | info = twl_regs + i; |
fa16a5c1 DB |
595 | break; |
596 | } | |
597 | if (!info) | |
598 | return -ENODEV; | |
599 | ||
600 | initdata = pdev->dev.platform_data; | |
601 | if (!initdata) | |
602 | return -EINVAL; | |
603 | ||
604 | /* Constrain board-specific capabilities according to what | |
605 | * this driver and the chip itself can actually do. | |
606 | */ | |
607 | c = &initdata->constraints; | |
fa16a5c1 DB |
608 | c->valid_modes_mask &= REGULATOR_MODE_NORMAL | REGULATOR_MODE_STANDBY; |
609 | c->valid_ops_mask &= REGULATOR_CHANGE_VOLTAGE | |
610 | | REGULATOR_CHANGE_MODE | |
611 | | REGULATOR_CHANGE_STATUS; | |
205e5cd3 JKS |
612 | switch (pdev->id) { |
613 | case TWL4030_REG_VIO: | |
614 | case TWL4030_REG_VDD1: | |
615 | case TWL4030_REG_VDD2: | |
616 | case TWL4030_REG_VPLL1: | |
617 | case TWL4030_REG_VINTANA1: | |
618 | case TWL4030_REG_VINTANA2: | |
619 | case TWL4030_REG_VINTDIG: | |
620 | c->always_on = true; | |
621 | break; | |
622 | default: | |
623 | break; | |
624 | } | |
fa16a5c1 DB |
625 | |
626 | rdev = regulator_register(&info->desc, &pdev->dev, initdata, info); | |
627 | if (IS_ERR(rdev)) { | |
628 | dev_err(&pdev->dev, "can't register %s, %ld\n", | |
629 | info->desc.name, PTR_ERR(rdev)); | |
630 | return PTR_ERR(rdev); | |
631 | } | |
632 | platform_set_drvdata(pdev, rdev); | |
633 | ||
30010fa5 JKS |
634 | twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_REMAP, |
635 | info->remap); | |
636 | ||
fa16a5c1 DB |
637 | /* NOTE: many regulators support short-circuit IRQs (presentable |
638 | * as REGULATOR_OVER_CURRENT notifications?) configured via: | |
639 | * - SC_CONFIG | |
640 | * - SC_DETECT1 (vintana2, vmmc1/2, vaux1/2/3/4) | |
641 | * - SC_DETECT2 (vusb, vdac, vio, vdd1/2, vpll2) | |
642 | * - IT_CONFIG | |
643 | */ | |
644 | ||
645 | return 0; | |
646 | } | |
647 | ||
c4aa6f31 | 648 | static int __devexit twlreg_remove(struct platform_device *pdev) |
fa16a5c1 DB |
649 | { |
650 | regulator_unregister(platform_get_drvdata(pdev)); | |
651 | return 0; | |
652 | } | |
653 | ||
c4aa6f31 | 654 | MODULE_ALIAS("platform:twl_reg"); |
fa16a5c1 | 655 | |
c4aa6f31 RN |
656 | static struct platform_driver twlreg_driver = { |
657 | .probe = twlreg_probe, | |
658 | .remove = __devexit_p(twlreg_remove), | |
fa16a5c1 | 659 | /* NOTE: short name, to work around driver model truncation of |
c4aa6f31 | 660 | * "twl_regulator.12" (and friends) to "twl_regulator.1". |
fa16a5c1 | 661 | */ |
c4aa6f31 | 662 | .driver.name = "twl_reg", |
fa16a5c1 DB |
663 | .driver.owner = THIS_MODULE, |
664 | }; | |
665 | ||
c4aa6f31 | 666 | static int __init twlreg_init(void) |
fa16a5c1 | 667 | { |
c4aa6f31 | 668 | return platform_driver_register(&twlreg_driver); |
fa16a5c1 | 669 | } |
c4aa6f31 | 670 | subsys_initcall(twlreg_init); |
fa16a5c1 | 671 | |
c4aa6f31 | 672 | static void __exit twlreg_exit(void) |
fa16a5c1 | 673 | { |
c4aa6f31 | 674 | platform_driver_unregister(&twlreg_driver); |
fa16a5c1 | 675 | } |
c4aa6f31 | 676 | module_exit(twlreg_exit) |
fa16a5c1 | 677 | |
c4aa6f31 | 678 | MODULE_DESCRIPTION("TWL regulator driver"); |
fa16a5c1 | 679 | MODULE_LICENSE("GPL"); |