Commit | Line | Data |
---|---|---|
4cdf854f DB |
1 | /* |
2 | * "RTT as Real Time Clock" driver for AT91SAM9 SoC family | |
3 | * | |
4 | * (C) 2007 Michel Benoit | |
5 | * | |
6 | * Based on rtc-at91rm9200.c by Rick Bronson | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * as published by the Free Software Foundation; either version | |
11 | * 2 of the License, or (at your option) any later version. | |
12 | */ | |
13 | ||
6932ff53 | 14 | #include <linux/clk.h> |
4cdf854f DB |
15 | #include <linux/interrupt.h> |
16 | #include <linux/ioctl.h> | |
9d42e465 | 17 | #include <linux/io.h> |
6932ff53 | 18 | #include <linux/kernel.h> |
43e112bb | 19 | #include <linux/mfd/syscon.h> |
6932ff53 | 20 | #include <linux/module.h> |
1955f213 | 21 | #include <linux/of.h> |
6932ff53 | 22 | #include <linux/platform_device.h> |
43e112bb | 23 | #include <linux/regmap.h> |
6932ff53 AB |
24 | #include <linux/rtc.h> |
25 | #include <linux/slab.h> | |
603b1a23 | 26 | #include <linux/suspend.h> |
6932ff53 | 27 | #include <linux/time.h> |
4cdf854f | 28 | |
4cdf854f DB |
29 | /* |
30 | * This driver uses two configurable hardware resources that live in the | |
31 | * AT91SAM9 backup power domain (intended to be powered at all times) | |
32 | * to implement the Real Time Clock interfaces | |
33 | * | |
34 | * - A "Real-time Timer" (RTT) counts up in seconds from a base time. | |
35 | * We can't assign the counter value (CRTV) ... but we can reset it. | |
36 | * | |
37 | * - One of the "General Purpose Backup Registers" (GPBRs) holds the | |
38 | * base time, normally an offset from the beginning of the POSIX | |
39 | * epoch (1970-Jan-1 00:00:00 UTC). Some systems also include the | |
40 | * local timezone's offset. | |
41 | * | |
42 | * The RTC's value is the RTT counter plus that offset. The RTC's alarm | |
43 | * is likewise a base (ALMV) plus that offset. | |
44 | * | |
45 | * Not all RTTs will be used as RTCs; some systems have multiple RTTs to | |
46 | * choose from, or a "real" RTC module. All systems have multiple GPBR | |
47 | * registers available, likewise usable for more than "RTC" support. | |
48 | */ | |
49 | ||
6575bd7c BB |
50 | #define AT91_RTT_MR 0x00 /* Real-time Mode Register */ |
51 | #define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */ | |
52 | #define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */ | |
53 | #define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */ | |
54 | #define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */ | |
55 | ||
56 | #define AT91_RTT_AR 0x04 /* Real-time Alarm Register */ | |
57 | #define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */ | |
58 | ||
59 | #define AT91_RTT_VR 0x08 /* Real-time Value Register */ | |
60 | #define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */ | |
61 | ||
62 | #define AT91_RTT_SR 0x0c /* Real-time Status Register */ | |
63 | #define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */ | |
64 | #define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */ | |
65 | ||
4cdf854f DB |
66 | /* |
67 | * We store ALARM_DISABLED in ALMV to record that no alarm is set. | |
68 | * It's also the reset value for that field. | |
69 | */ | |
70 | #define ALARM_DISABLED ((u32)~0) | |
71 | ||
72 | ||
73 | struct sam9_rtc { | |
74 | void __iomem *rtt; | |
75 | struct rtc_device *rtcdev; | |
76 | u32 imr; | |
43e112bb BB |
77 | struct regmap *gpbr; |
78 | unsigned int gpbr_offset; | |
e402af6c | 79 | int irq; |
a975f47f | 80 | struct clk *sclk; |
603b1a23 BB |
81 | bool suspended; |
82 | unsigned long events; | |
83 | spinlock_t lock; | |
4cdf854f DB |
84 | }; |
85 | ||
86 | #define rtt_readl(rtc, field) \ | |
272f1dfa | 87 | readl((rtc)->rtt + AT91_RTT_ ## field) |
4cdf854f | 88 | #define rtt_writel(rtc, field, val) \ |
272f1dfa | 89 | writel((val), (rtc)->rtt + AT91_RTT_ ## field) |
4cdf854f | 90 | |
43e112bb BB |
91 | static inline unsigned int gpbr_readl(struct sam9_rtc *rtc) |
92 | { | |
93 | unsigned int val; | |
94 | ||
95 | regmap_read(rtc->gpbr, rtc->gpbr_offset, &val); | |
96 | ||
97 | return val; | |
98 | } | |
99 | ||
100 | static inline void gpbr_writel(struct sam9_rtc *rtc, unsigned int val) | |
101 | { | |
102 | regmap_write(rtc->gpbr, rtc->gpbr_offset, val); | |
103 | } | |
4cdf854f DB |
104 | |
105 | /* | |
106 | * Read current time and date in RTC | |
107 | */ | |
108 | static int at91_rtc_readtime(struct device *dev, struct rtc_time *tm) | |
109 | { | |
110 | struct sam9_rtc *rtc = dev_get_drvdata(dev); | |
111 | u32 secs, secs2; | |
112 | u32 offset; | |
113 | ||
114 | /* read current time offset */ | |
115 | offset = gpbr_readl(rtc); | |
116 | if (offset == 0) | |
117 | return -EILSEQ; | |
118 | ||
119 | /* reread the counter to help sync the two clock domains */ | |
120 | secs = rtt_readl(rtc, VR); | |
121 | secs2 = rtt_readl(rtc, VR); | |
122 | if (secs != secs2) | |
123 | secs = rtt_readl(rtc, VR); | |
124 | ||
125 | rtc_time_to_tm(offset + secs, tm); | |
126 | ||
127 | dev_dbg(dev, "%s: %4d-%02d-%02d %02d:%02d:%02d\n", "readtime", | |
128 | 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday, | |
129 | tm->tm_hour, tm->tm_min, tm->tm_sec); | |
130 | ||
131 | return 0; | |
132 | } | |
133 | ||
134 | /* | |
135 | * Set current time and date in RTC | |
136 | */ | |
137 | static int at91_rtc_settime(struct device *dev, struct rtc_time *tm) | |
138 | { | |
139 | struct sam9_rtc *rtc = dev_get_drvdata(dev); | |
140 | int err; | |
141 | u32 offset, alarm, mr; | |
142 | unsigned long secs; | |
143 | ||
144 | dev_dbg(dev, "%s: %4d-%02d-%02d %02d:%02d:%02d\n", "settime", | |
145 | 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday, | |
146 | tm->tm_hour, tm->tm_min, tm->tm_sec); | |
147 | ||
148 | err = rtc_tm_to_time(tm, &secs); | |
149 | if (err != 0) | |
150 | return err; | |
151 | ||
152 | mr = rtt_readl(rtc, MR); | |
153 | ||
154 | /* disable interrupts */ | |
155 | rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN)); | |
156 | ||
157 | /* read current time offset */ | |
158 | offset = gpbr_readl(rtc); | |
159 | ||
160 | /* store the new base time in a battery backup register */ | |
161 | secs += 1; | |
162 | gpbr_writel(rtc, secs); | |
163 | ||
164 | /* adjust the alarm time for the new base */ | |
165 | alarm = rtt_readl(rtc, AR); | |
166 | if (alarm != ALARM_DISABLED) { | |
167 | if (offset > secs) { | |
168 | /* time jumped backwards, increase time until alarm */ | |
169 | alarm += (offset - secs); | |
170 | } else if ((alarm + offset) > secs) { | |
171 | /* time jumped forwards, decrease time until alarm */ | |
172 | alarm -= (secs - offset); | |
173 | } else { | |
174 | /* time jumped past the alarm, disable alarm */ | |
175 | alarm = ALARM_DISABLED; | |
176 | mr &= ~AT91_RTT_ALMIEN; | |
177 | } | |
178 | rtt_writel(rtc, AR, alarm); | |
179 | } | |
180 | ||
181 | /* reset the timer, and re-enable interrupts */ | |
182 | rtt_writel(rtc, MR, mr | AT91_RTT_RTTRST); | |
183 | ||
184 | return 0; | |
185 | } | |
186 | ||
187 | static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm) | |
188 | { | |
189 | struct sam9_rtc *rtc = dev_get_drvdata(dev); | |
190 | struct rtc_time *tm = &alrm->time; | |
191 | u32 alarm = rtt_readl(rtc, AR); | |
192 | u32 offset; | |
193 | ||
194 | offset = gpbr_readl(rtc); | |
195 | if (offset == 0) | |
196 | return -EILSEQ; | |
197 | ||
870a2761 | 198 | memset(alrm, 0, sizeof(*alrm)); |
4cdf854f DB |
199 | if (alarm != ALARM_DISABLED && offset != 0) { |
200 | rtc_time_to_tm(offset + alarm, tm); | |
201 | ||
202 | dev_dbg(dev, "%s: %4d-%02d-%02d %02d:%02d:%02d\n", "readalarm", | |
203 | 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday, | |
204 | tm->tm_hour, tm->tm_min, tm->tm_sec); | |
205 | ||
206 | if (rtt_readl(rtc, MR) & AT91_RTT_ALMIEN) | |
207 | alrm->enabled = 1; | |
208 | } | |
209 | ||
210 | return 0; | |
211 | } | |
212 | ||
213 | static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) | |
214 | { | |
215 | struct sam9_rtc *rtc = dev_get_drvdata(dev); | |
216 | struct rtc_time *tm = &alrm->time; | |
217 | unsigned long secs; | |
218 | u32 offset; | |
219 | u32 mr; | |
220 | int err; | |
221 | ||
222 | err = rtc_tm_to_time(tm, &secs); | |
223 | if (err != 0) | |
224 | return err; | |
225 | ||
226 | offset = gpbr_readl(rtc); | |
227 | if (offset == 0) { | |
228 | /* time is not set */ | |
229 | return -EILSEQ; | |
230 | } | |
231 | mr = rtt_readl(rtc, MR); | |
232 | rtt_writel(rtc, MR, mr & ~AT91_RTT_ALMIEN); | |
233 | ||
234 | /* alarm in the past? finish and leave disabled */ | |
235 | if (secs <= offset) { | |
236 | rtt_writel(rtc, AR, ALARM_DISABLED); | |
237 | return 0; | |
238 | } | |
239 | ||
240 | /* else set alarm and maybe enable it */ | |
241 | rtt_writel(rtc, AR, secs - offset); | |
242 | if (alrm->enabled) | |
243 | rtt_writel(rtc, MR, mr | AT91_RTT_ALMIEN); | |
244 | ||
245 | dev_dbg(dev, "%s: %4d-%02d-%02d %02d:%02d:%02d\n", "setalarm", | |
246 | tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_hour, | |
247 | tm->tm_min, tm->tm_sec); | |
248 | ||
249 | return 0; | |
250 | } | |
251 | ||
16380c15 JS |
252 | static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
253 | { | |
254 | struct sam9_rtc *rtc = dev_get_drvdata(dev); | |
255 | u32 mr = rtt_readl(rtc, MR); | |
256 | ||
257 | dev_dbg(dev, "alarm_irq_enable: enabled=%08x, mr %08x\n", enabled, mr); | |
258 | if (enabled) | |
259 | rtt_writel(rtc, MR, mr | AT91_RTT_ALMIEN); | |
260 | else | |
261 | rtt_writel(rtc, MR, mr & ~AT91_RTT_ALMIEN); | |
262 | return 0; | |
263 | } | |
264 | ||
4cdf854f DB |
265 | /* |
266 | * Provide additional RTC information in /proc/driver/rtc | |
267 | */ | |
268 | static int at91_rtc_proc(struct device *dev, struct seq_file *seq) | |
269 | { | |
270 | struct sam9_rtc *rtc = dev_get_drvdata(dev); | |
271 | u32 mr = mr = rtt_readl(rtc, MR); | |
272 | ||
273 | seq_printf(seq, "update_IRQ\t: %s\n", | |
274 | (mr & AT91_RTT_RTTINCIEN) ? "yes" : "no"); | |
275 | return 0; | |
276 | } | |
277 | ||
603b1a23 | 278 | static irqreturn_t at91_rtc_cache_events(struct sam9_rtc *rtc) |
4cdf854f | 279 | { |
4cdf854f | 280 | u32 sr, mr; |
4cdf854f DB |
281 | |
282 | /* Shared interrupt may be for another device. Note: reading | |
283 | * SR clears it, so we must only read it in this irq handler! | |
284 | */ | |
285 | mr = rtt_readl(rtc, MR) & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN); | |
9fedc9f1 | 286 | sr = rtt_readl(rtc, SR) & (mr >> 16); |
4cdf854f DB |
287 | if (!sr) |
288 | return IRQ_NONE; | |
289 | ||
290 | /* alarm status */ | |
291 | if (sr & AT91_RTT_ALMS) | |
603b1a23 | 292 | rtc->events |= (RTC_AF | RTC_IRQF); |
4cdf854f DB |
293 | |
294 | /* timer update/increment */ | |
295 | if (sr & AT91_RTT_RTTINC) | |
603b1a23 BB |
296 | rtc->events |= (RTC_UF | RTC_IRQF); |
297 | ||
298 | return IRQ_HANDLED; | |
299 | } | |
300 | ||
301 | static void at91_rtc_flush_events(struct sam9_rtc *rtc) | |
302 | { | |
303 | if (!rtc->events) | |
304 | return; | |
4cdf854f | 305 | |
603b1a23 BB |
306 | rtc_update_irq(rtc->rtcdev, 1, rtc->events); |
307 | rtc->events = 0; | |
4cdf854f | 308 | |
2a4e2b87 | 309 | pr_debug("%s: num=%ld, events=0x%02lx\n", __func__, |
603b1a23 BB |
310 | rtc->events >> 8, rtc->events & 0x000000FF); |
311 | } | |
4cdf854f | 312 | |
603b1a23 BB |
313 | /* |
314 | * IRQ handler for the RTC | |
315 | */ | |
316 | static irqreturn_t at91_rtc_interrupt(int irq, void *_rtc) | |
317 | { | |
318 | struct sam9_rtc *rtc = _rtc; | |
319 | int ret; | |
320 | ||
321 | spin_lock(&rtc->lock); | |
322 | ||
323 | ret = at91_rtc_cache_events(rtc); | |
324 | ||
325 | /* We're called in suspended state */ | |
326 | if (rtc->suspended) { | |
327 | /* Mask irqs coming from this peripheral */ | |
328 | rtt_writel(rtc, MR, | |
329 | rtt_readl(rtc, MR) & | |
330 | ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN)); | |
331 | /* Trigger a system wakeup */ | |
332 | pm_system_wakeup(); | |
333 | } else { | |
334 | at91_rtc_flush_events(rtc); | |
335 | } | |
336 | ||
337 | spin_unlock(&rtc->lock); | |
338 | ||
339 | return ret; | |
4cdf854f DB |
340 | } |
341 | ||
342 | static const struct rtc_class_ops at91_rtc_ops = { | |
4cdf854f DB |
343 | .read_time = at91_rtc_readtime, |
344 | .set_time = at91_rtc_settime, | |
345 | .read_alarm = at91_rtc_readalarm, | |
346 | .set_alarm = at91_rtc_setalarm, | |
347 | .proc = at91_rtc_proc, | |
d4035850 | 348 | .alarm_irq_enable = at91_rtc_alarm_irq_enable, |
4cdf854f DB |
349 | }; |
350 | ||
bddd8ddd | 351 | static const struct regmap_config gpbr_regmap_config = { |
43e112bb BB |
352 | .reg_bits = 32, |
353 | .val_bits = 32, | |
354 | .reg_stride = 4, | |
355 | }; | |
356 | ||
4cdf854f DB |
357 | /* |
358 | * Initialize and install RTC driver | |
359 | */ | |
5a167f45 | 360 | static int at91_rtc_probe(struct platform_device *pdev) |
4cdf854f | 361 | { |
d41da3ee | 362 | struct resource *r; |
4cdf854f | 363 | struct sam9_rtc *rtc; |
e402af6c | 364 | int ret, irq; |
4cdf854f | 365 | u32 mr; |
a975f47f | 366 | unsigned int sclk_rate; |
4cdf854f | 367 | |
e402af6c LD |
368 | irq = platform_get_irq(pdev, 0); |
369 | if (irq < 0) { | |
370 | dev_err(&pdev->dev, "failed to get interrupt resource\n"); | |
371 | return irq; | |
372 | } | |
373 | ||
9d42e465 | 374 | rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); |
4cdf854f DB |
375 | if (!rtc) |
376 | return -ENOMEM; | |
377 | ||
e402af6c LD |
378 | rtc->irq = irq; |
379 | ||
9fedc9f1 DB |
380 | /* platform setup code should have handled this; sigh */ |
381 | if (!device_can_wakeup(&pdev->dev)) | |
382 | device_init_wakeup(&pdev->dev, 1); | |
383 | ||
4cdf854f | 384 | platform_set_drvdata(pdev, rtc); |
4cdf854f | 385 | |
d41da3ee BB |
386 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
387 | rtc->rtt = devm_ioremap_resource(&pdev->dev, r); | |
388 | if (IS_ERR(rtc->rtt)) | |
389 | return PTR_ERR(rtc->rtt); | |
390 | ||
43e112bb BB |
391 | if (!pdev->dev.of_node) { |
392 | /* | |
393 | * TODO: Remove this code chunk when removing non DT board | |
394 | * support. Remember to remove the gpbr_regmap_config | |
395 | * variable too. | |
396 | */ | |
397 | void __iomem *gpbr; | |
398 | ||
399 | r = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
400 | gpbr = devm_ioremap_resource(&pdev->dev, r); | |
401 | if (IS_ERR(gpbr)) | |
402 | return PTR_ERR(gpbr); | |
403 | ||
404 | rtc->gpbr = regmap_init_mmio(NULL, gpbr, | |
405 | &gpbr_regmap_config); | |
406 | } else { | |
407 | struct of_phandle_args args; | |
408 | ||
409 | ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, | |
410 | "atmel,rtt-rtc-time-reg", 1, 0, | |
411 | &args); | |
412 | if (ret) | |
413 | return ret; | |
414 | ||
415 | rtc->gpbr = syscon_node_to_regmap(args.np); | |
416 | rtc->gpbr_offset = args.args[0]; | |
417 | } | |
418 | ||
419 | if (IS_ERR(rtc->gpbr)) { | |
420 | dev_err(&pdev->dev, "failed to retrieve gpbr regmap, aborting.\n"); | |
421 | return -ENOMEM; | |
422 | } | |
b3af8b49 | 423 | |
a975f47f BB |
424 | rtc->sclk = devm_clk_get(&pdev->dev, NULL); |
425 | if (IS_ERR(rtc->sclk)) | |
426 | return PTR_ERR(rtc->sclk); | |
427 | ||
a975f47f BB |
428 | ret = clk_prepare_enable(rtc->sclk); |
429 | if (ret) { | |
430 | dev_err(&pdev->dev, "Could not enable slow clock\n"); | |
431 | return ret; | |
432 | } | |
433 | ||
8918bd8a AB |
434 | sclk_rate = clk_get_rate(rtc->sclk); |
435 | if (!sclk_rate || sclk_rate > AT91_RTT_RTPRES) { | |
436 | dev_err(&pdev->dev, "Invalid slow clock rate\n"); | |
437 | ret = -EINVAL; | |
438 | goto err_clk; | |
439 | } | |
440 | ||
4cdf854f DB |
441 | mr = rtt_readl(rtc, MR); |
442 | ||
443 | /* unless RTT is counting at 1 Hz, re-initialize it */ | |
a975f47f BB |
444 | if ((mr & AT91_RTT_RTPRES) != sclk_rate) { |
445 | mr = AT91_RTT_RTTRST | (sclk_rate & AT91_RTT_RTPRES); | |
4cdf854f DB |
446 | gpbr_writel(rtc, 0); |
447 | } | |
448 | ||
449 | /* disable all interrupts (same as on shutdown path) */ | |
450 | mr &= ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN); | |
451 | rtt_writel(rtc, MR, mr); | |
452 | ||
9d42e465 JH |
453 | rtc->rtcdev = devm_rtc_device_register(&pdev->dev, pdev->name, |
454 | &at91_rtc_ops, THIS_MODULE); | |
ffe60fcf AB |
455 | if (IS_ERR(rtc->rtcdev)) { |
456 | ret = PTR_ERR(rtc->rtcdev); | |
457 | goto err_clk; | |
458 | } | |
4cdf854f DB |
459 | |
460 | /* register irq handler after we know what name we'll use */ | |
9d42e465 | 461 | ret = devm_request_irq(&pdev->dev, rtc->irq, at91_rtc_interrupt, |
603b1a23 BB |
462 | IRQF_SHARED | IRQF_COND_SUSPEND, |
463 | dev_name(&rtc->rtcdev->dev), rtc); | |
4cdf854f | 464 | if (ret) { |
e402af6c | 465 | dev_dbg(&pdev->dev, "can't share IRQ %d?\n", rtc->irq); |
ffe60fcf | 466 | goto err_clk; |
4cdf854f DB |
467 | } |
468 | ||
469 | /* NOTE: sam9260 rev A silicon has a ROM bug which resets the | |
470 | * RTT on at least some reboots. If you have that chip, you must | |
471 | * initialize the time from some external source like a GPS, wall | |
472 | * clock, discrete RTC, etc | |
473 | */ | |
474 | ||
475 | if (gpbr_readl(rtc) == 0) | |
476 | dev_warn(&pdev->dev, "%s: SET TIME!\n", | |
744bcb13 | 477 | dev_name(&rtc->rtcdev->dev)); |
4cdf854f DB |
478 | |
479 | return 0; | |
ffe60fcf AB |
480 | |
481 | err_clk: | |
482 | clk_disable_unprepare(rtc->sclk); | |
483 | ||
484 | return ret; | |
4cdf854f DB |
485 | } |
486 | ||
487 | /* | |
488 | * Disable and remove the RTC driver | |
489 | */ | |
5a167f45 | 490 | static int at91_rtc_remove(struct platform_device *pdev) |
4cdf854f DB |
491 | { |
492 | struct sam9_rtc *rtc = platform_get_drvdata(pdev); | |
493 | u32 mr = rtt_readl(rtc, MR); | |
494 | ||
495 | /* disable all interrupts */ | |
496 | rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN)); | |
4cdf854f | 497 | |
73ab31ce | 498 | clk_disable_unprepare(rtc->sclk); |
a975f47f | 499 | |
4cdf854f DB |
500 | return 0; |
501 | } | |
502 | ||
503 | static void at91_rtc_shutdown(struct platform_device *pdev) | |
504 | { | |
505 | struct sam9_rtc *rtc = platform_get_drvdata(pdev); | |
506 | u32 mr = rtt_readl(rtc, MR); | |
507 | ||
508 | rtc->imr = mr & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN); | |
509 | rtt_writel(rtc, MR, mr & ~rtc->imr); | |
510 | } | |
511 | ||
4dc8eb13 | 512 | #ifdef CONFIG_PM_SLEEP |
4cdf854f DB |
513 | |
514 | /* AT91SAM9 RTC Power management control */ | |
515 | ||
4dc8eb13 | 516 | static int at91_rtc_suspend(struct device *dev) |
4cdf854f | 517 | { |
4dc8eb13 | 518 | struct sam9_rtc *rtc = dev_get_drvdata(dev); |
4cdf854f DB |
519 | u32 mr = rtt_readl(rtc, MR); |
520 | ||
521 | /* | |
522 | * This IRQ is shared with DBGU and other hardware which isn't | |
523 | * necessarily a wakeup event source. | |
524 | */ | |
525 | rtc->imr = mr & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN); | |
526 | if (rtc->imr) { | |
4dc8eb13 | 527 | if (device_may_wakeup(dev) && (mr & AT91_RTT_ALMIEN)) { |
603b1a23 BB |
528 | unsigned long flags; |
529 | ||
e402af6c | 530 | enable_irq_wake(rtc->irq); |
603b1a23 BB |
531 | spin_lock_irqsave(&rtc->lock, flags); |
532 | rtc->suspended = true; | |
533 | spin_unlock_irqrestore(&rtc->lock, flags); | |
4cdf854f DB |
534 | /* don't let RTTINC cause wakeups */ |
535 | if (mr & AT91_RTT_RTTINCIEN) | |
536 | rtt_writel(rtc, MR, mr & ~AT91_RTT_RTTINCIEN); | |
537 | } else | |
538 | rtt_writel(rtc, MR, mr & ~rtc->imr); | |
539 | } | |
540 | ||
541 | return 0; | |
542 | } | |
543 | ||
4dc8eb13 | 544 | static int at91_rtc_resume(struct device *dev) |
4cdf854f | 545 | { |
4dc8eb13 | 546 | struct sam9_rtc *rtc = dev_get_drvdata(dev); |
4cdf854f DB |
547 | u32 mr; |
548 | ||
549 | if (rtc->imr) { | |
603b1a23 BB |
550 | unsigned long flags; |
551 | ||
4dc8eb13 | 552 | if (device_may_wakeup(dev)) |
e402af6c | 553 | disable_irq_wake(rtc->irq); |
4cdf854f DB |
554 | mr = rtt_readl(rtc, MR); |
555 | rtt_writel(rtc, MR, mr | rtc->imr); | |
603b1a23 BB |
556 | |
557 | spin_lock_irqsave(&rtc->lock, flags); | |
558 | rtc->suspended = false; | |
559 | at91_rtc_cache_events(rtc); | |
560 | at91_rtc_flush_events(rtc); | |
561 | spin_unlock_irqrestore(&rtc->lock, flags); | |
4cdf854f DB |
562 | } |
563 | ||
564 | return 0; | |
565 | } | |
4cdf854f DB |
566 | #endif |
567 | ||
4dc8eb13 JH |
568 | static SIMPLE_DEV_PM_OPS(at91_rtc_pm_ops, at91_rtc_suspend, at91_rtc_resume); |
569 | ||
07d4d724 BB |
570 | #ifdef CONFIG_OF |
571 | static const struct of_device_id at91_rtc_dt_ids[] = { | |
572 | { .compatible = "atmel,at91sam9260-rtt" }, | |
573 | { /* sentinel */ } | |
574 | }; | |
575 | MODULE_DEVICE_TABLE(of, at91_rtc_dt_ids); | |
576 | #endif | |
577 | ||
4cdf854f | 578 | static struct platform_driver at91_rtc_driver = { |
205056a3 | 579 | .probe = at91_rtc_probe, |
5a167f45 | 580 | .remove = at91_rtc_remove, |
4cdf854f | 581 | .shutdown = at91_rtc_shutdown, |
205056a3 JCPV |
582 | .driver = { |
583 | .name = "rtc-at91sam9", | |
4dc8eb13 | 584 | .pm = &at91_rtc_pm_ops, |
07d4d724 | 585 | .of_match_table = of_match_ptr(at91_rtc_dt_ids), |
205056a3 | 586 | }, |
4cdf854f DB |
587 | }; |
588 | ||
477d30d7 | 589 | module_platform_driver(at91_rtc_driver); |
4cdf854f DB |
590 | |
591 | MODULE_AUTHOR("Michel Benoit"); | |
592 | MODULE_DESCRIPTION("RTC driver for Atmel AT91SAM9x"); | |
593 | MODULE_LICENSE("GPL"); |