Commit | Line | Data |
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7be2c7c9 DB |
1 | /* |
2 | * RTC class driver for "CMOS RTC": PCs, ACPI, etc | |
3 | * | |
4 | * Copyright (C) 1996 Paul Gortmaker (drivers/char/rtc.c) | |
5 | * Copyright (C) 2006 David Brownell (convert to new framework) | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
12 | ||
13 | /* | |
14 | * The original "cmos clock" chip was an MC146818 chip, now obsolete. | |
15 | * That defined the register interface now provided by all PCs, some | |
16 | * non-PC systems, and incorporated into ACPI. Modern PC chipsets | |
17 | * integrate an MC146818 clone in their southbridge, and boards use | |
18 | * that instead of discrete clones like the DS12887 or M48T86. There | |
19 | * are also clones that connect using the LPC bus. | |
20 | * | |
21 | * That register API is also used directly by various other drivers | |
22 | * (notably for integrated NVRAM), infrastructure (x86 has code to | |
23 | * bypass the RTC framework, directly reading the RTC during boot | |
24 | * and updating minutes/seconds for systems using NTP synch) and | |
25 | * utilities (like userspace 'hwclock', if no /dev node exists). | |
26 | * | |
27 | * So **ALL** calls to CMOS_READ and CMOS_WRITE must be done with | |
28 | * interrupts disabled, holding the global rtc_lock, to exclude those | |
29 | * other drivers and utilities on correctly configured systems. | |
30 | */ | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/spinlock.h> | |
36 | #include <linux/platform_device.h> | |
37 | #include <linux/mod_devicetable.h> | |
38 | ||
39 | /* this is for "generic access to PC-style RTC" using CMOS_READ/CMOS_WRITE */ | |
40 | #include <asm-generic/rtc.h> | |
41 | ||
7be2c7c9 DB |
42 | struct cmos_rtc { |
43 | struct rtc_device *rtc; | |
44 | struct device *dev; | |
45 | int irq; | |
46 | struct resource *iomem; | |
47 | ||
87ac84f4 DB |
48 | void (*wake_on)(struct device *); |
49 | void (*wake_off)(struct device *); | |
50 | ||
51 | u8 enabled_wake; | |
7be2c7c9 DB |
52 | u8 suspend_ctrl; |
53 | ||
54 | /* newer hardware extends the original register set */ | |
55 | u8 day_alrm; | |
56 | u8 mon_alrm; | |
57 | u8 century; | |
58 | }; | |
59 | ||
60 | /* both platform and pnp busses use negative numbers for invalid irqs */ | |
61 | #define is_valid_irq(n) ((n) >= 0) | |
62 | ||
63 | static const char driver_name[] = "rtc_cmos"; | |
64 | ||
bcd9b89c DB |
65 | /* The RTC_INTR register may have e.g. RTC_PF set even if RTC_PIE is clear; |
66 | * always mask it against the irq enable bits in RTC_CONTROL. Bit values | |
67 | * are the same: PF==PIE, AF=AIE, UF=UIE; so RTC_IRQMASK works with both. | |
68 | */ | |
69 | #define RTC_IRQMASK (RTC_PF | RTC_AF | RTC_UF) | |
70 | ||
71 | static inline int is_intr(u8 rtc_intr) | |
72 | { | |
73 | if (!(rtc_intr & RTC_IRQF)) | |
74 | return 0; | |
75 | return rtc_intr & RTC_IRQMASK; | |
76 | } | |
77 | ||
7be2c7c9 DB |
78 | /*----------------------------------------------------------------*/ |
79 | ||
35d3fdd5 DB |
80 | /* Much modern x86 hardware has HPETs (10+ MHz timers) which, because |
81 | * many BIOS programmers don't set up "sane mode" IRQ routing, are mostly | |
82 | * used in a broken "legacy replacement" mode. The breakage includes | |
83 | * HPET #1 hijacking the IRQ for this RTC, and being unavailable for | |
84 | * other (better) use. | |
85 | * | |
86 | * When that broken mode is in use, platform glue provides a partial | |
87 | * emulation of hardware RTC IRQ facilities using HPET #1. We don't | |
88 | * want to use HPET for anything except those IRQs though... | |
89 | */ | |
90 | #ifdef CONFIG_HPET_EMULATE_RTC | |
91 | #include <asm/hpet.h> | |
92 | #else | |
93 | ||
94 | static inline int is_hpet_enabled(void) | |
95 | { | |
96 | return 0; | |
97 | } | |
98 | ||
99 | static inline int hpet_mask_rtc_irq_bit(unsigned long mask) | |
100 | { | |
101 | return 0; | |
102 | } | |
103 | ||
104 | static inline int hpet_set_rtc_irq_bit(unsigned long mask) | |
105 | { | |
106 | return 0; | |
107 | } | |
108 | ||
109 | static inline int | |
110 | hpet_set_alarm_time(unsigned char hrs, unsigned char min, unsigned char sec) | |
111 | { | |
112 | return 0; | |
113 | } | |
114 | ||
115 | static inline int hpet_set_periodic_freq(unsigned long freq) | |
116 | { | |
117 | return 0; | |
118 | } | |
119 | ||
120 | static inline int hpet_rtc_dropped_irq(void) | |
121 | { | |
122 | return 0; | |
123 | } | |
124 | ||
125 | static inline int hpet_rtc_timer_init(void) | |
126 | { | |
127 | return 0; | |
128 | } | |
129 | ||
130 | extern irq_handler_t hpet_rtc_interrupt; | |
131 | ||
132 | static inline int hpet_register_irq_handler(irq_handler_t handler) | |
133 | { | |
134 | return 0; | |
135 | } | |
136 | ||
137 | static inline int hpet_unregister_irq_handler(irq_handler_t handler) | |
138 | { | |
139 | return 0; | |
140 | } | |
141 | ||
142 | #endif | |
143 | ||
144 | /*----------------------------------------------------------------*/ | |
145 | ||
c8fc40cd DB |
146 | #ifdef RTC_PORT |
147 | ||
148 | /* Most newer x86 systems have two register banks, the first used | |
149 | * for RTC and NVRAM and the second only for NVRAM. Caller must | |
150 | * own rtc_lock ... and we won't worry about access during NMI. | |
151 | */ | |
152 | #define can_bank2 true | |
153 | ||
154 | static inline unsigned char cmos_read_bank2(unsigned char addr) | |
155 | { | |
156 | outb(addr, RTC_PORT(2)); | |
157 | return inb(RTC_PORT(3)); | |
158 | } | |
159 | ||
160 | static inline void cmos_write_bank2(unsigned char val, unsigned char addr) | |
161 | { | |
162 | outb(addr, RTC_PORT(2)); | |
163 | outb(val, RTC_PORT(2)); | |
164 | } | |
165 | ||
166 | #else | |
167 | ||
168 | #define can_bank2 false | |
169 | ||
170 | static inline unsigned char cmos_read_bank2(unsigned char addr) | |
171 | { | |
172 | return 0; | |
173 | } | |
174 | ||
175 | static inline void cmos_write_bank2(unsigned char val, unsigned char addr) | |
176 | { | |
177 | } | |
178 | ||
179 | #endif | |
180 | ||
181 | /*----------------------------------------------------------------*/ | |
182 | ||
7be2c7c9 DB |
183 | static int cmos_read_time(struct device *dev, struct rtc_time *t) |
184 | { | |
185 | /* REVISIT: if the clock has a "century" register, use | |
186 | * that instead of the heuristic in get_rtc_time(). | |
187 | * That'll make Y3K compatility (year > 2070) easy! | |
188 | */ | |
189 | get_rtc_time(t); | |
190 | return 0; | |
191 | } | |
192 | ||
193 | static int cmos_set_time(struct device *dev, struct rtc_time *t) | |
194 | { | |
195 | /* REVISIT: set the "century" register if available | |
196 | * | |
197 | * NOTE: this ignores the issue whereby updating the seconds | |
198 | * takes effect exactly 500ms after we write the register. | |
199 | * (Also queueing and other delays before we get this far.) | |
200 | */ | |
201 | return set_rtc_time(t); | |
202 | } | |
203 | ||
204 | static int cmos_read_alarm(struct device *dev, struct rtc_wkalrm *t) | |
205 | { | |
206 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
207 | unsigned char rtc_control; | |
208 | ||
209 | if (!is_valid_irq(cmos->irq)) | |
210 | return -EIO; | |
211 | ||
212 | /* Basic alarms only support hour, minute, and seconds fields. | |
213 | * Some also support day and month, for alarms up to a year in | |
214 | * the future. | |
215 | */ | |
216 | t->time.tm_mday = -1; | |
217 | t->time.tm_mon = -1; | |
218 | ||
219 | spin_lock_irq(&rtc_lock); | |
220 | t->time.tm_sec = CMOS_READ(RTC_SECONDS_ALARM); | |
221 | t->time.tm_min = CMOS_READ(RTC_MINUTES_ALARM); | |
222 | t->time.tm_hour = CMOS_READ(RTC_HOURS_ALARM); | |
223 | ||
224 | if (cmos->day_alrm) { | |
615bb29c ML |
225 | /* ignore upper bits on readback per ACPI spec */ |
226 | t->time.tm_mday = CMOS_READ(cmos->day_alrm) & 0x3f; | |
7be2c7c9 DB |
227 | if (!t->time.tm_mday) |
228 | t->time.tm_mday = -1; | |
229 | ||
230 | if (cmos->mon_alrm) { | |
231 | t->time.tm_mon = CMOS_READ(cmos->mon_alrm); | |
232 | if (!t->time.tm_mon) | |
233 | t->time.tm_mon = -1; | |
234 | } | |
235 | } | |
236 | ||
237 | rtc_control = CMOS_READ(RTC_CONTROL); | |
238 | spin_unlock_irq(&rtc_lock); | |
239 | ||
240 | /* REVISIT this assumes PC style usage: always BCD */ | |
241 | ||
242 | if (((unsigned)t->time.tm_sec) < 0x60) | |
fe20ba70 | 243 | t->time.tm_sec = bcd2bin(t->time.tm_sec); |
7be2c7c9 DB |
244 | else |
245 | t->time.tm_sec = -1; | |
246 | if (((unsigned)t->time.tm_min) < 0x60) | |
fe20ba70 | 247 | t->time.tm_min = bcd2bin(t->time.tm_min); |
7be2c7c9 DB |
248 | else |
249 | t->time.tm_min = -1; | |
250 | if (((unsigned)t->time.tm_hour) < 0x24) | |
fe20ba70 | 251 | t->time.tm_hour = bcd2bin(t->time.tm_hour); |
7be2c7c9 DB |
252 | else |
253 | t->time.tm_hour = -1; | |
254 | ||
255 | if (cmos->day_alrm) { | |
256 | if (((unsigned)t->time.tm_mday) <= 0x31) | |
fe20ba70 | 257 | t->time.tm_mday = bcd2bin(t->time.tm_mday); |
7be2c7c9 DB |
258 | else |
259 | t->time.tm_mday = -1; | |
260 | if (cmos->mon_alrm) { | |
261 | if (((unsigned)t->time.tm_mon) <= 0x12) | |
fe20ba70 | 262 | t->time.tm_mon = bcd2bin(t->time.tm_mon) - 1; |
7be2c7c9 DB |
263 | else |
264 | t->time.tm_mon = -1; | |
265 | } | |
266 | } | |
267 | t->time.tm_year = -1; | |
268 | ||
269 | t->enabled = !!(rtc_control & RTC_AIE); | |
270 | t->pending = 0; | |
271 | ||
272 | return 0; | |
273 | } | |
274 | ||
7e2a31da DB |
275 | static void cmos_checkintr(struct cmos_rtc *cmos, unsigned char rtc_control) |
276 | { | |
277 | unsigned char rtc_intr; | |
278 | ||
279 | /* NOTE after changing RTC_xIE bits we always read INTR_FLAGS; | |
280 | * allegedly some older rtcs need that to handle irqs properly | |
281 | */ | |
282 | rtc_intr = CMOS_READ(RTC_INTR_FLAGS); | |
283 | ||
284 | if (is_hpet_enabled()) | |
285 | return; | |
286 | ||
287 | rtc_intr &= (rtc_control & RTC_IRQMASK) | RTC_IRQF; | |
288 | if (is_intr(rtc_intr)) | |
289 | rtc_update_irq(cmos->rtc, 1, rtc_intr); | |
290 | } | |
291 | ||
292 | static void cmos_irq_enable(struct cmos_rtc *cmos, unsigned char mask) | |
293 | { | |
294 | unsigned char rtc_control; | |
295 | ||
296 | /* flush any pending IRQ status, notably for update irqs, | |
297 | * before we enable new IRQs | |
298 | */ | |
299 | rtc_control = CMOS_READ(RTC_CONTROL); | |
300 | cmos_checkintr(cmos, rtc_control); | |
301 | ||
302 | rtc_control |= mask; | |
303 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
304 | hpet_set_rtc_irq_bit(mask); | |
305 | ||
306 | cmos_checkintr(cmos, rtc_control); | |
307 | } | |
308 | ||
309 | static void cmos_irq_disable(struct cmos_rtc *cmos, unsigned char mask) | |
310 | { | |
311 | unsigned char rtc_control; | |
312 | ||
313 | rtc_control = CMOS_READ(RTC_CONTROL); | |
314 | rtc_control &= ~mask; | |
315 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
316 | hpet_mask_rtc_irq_bit(mask); | |
317 | ||
318 | cmos_checkintr(cmos, rtc_control); | |
319 | } | |
320 | ||
7be2c7c9 DB |
321 | static int cmos_set_alarm(struct device *dev, struct rtc_wkalrm *t) |
322 | { | |
323 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
324 | unsigned char mon, mday, hrs, min, sec; | |
7be2c7c9 DB |
325 | |
326 | if (!is_valid_irq(cmos->irq)) | |
327 | return -EIO; | |
328 | ||
329 | /* REVISIT this assumes PC style usage: always BCD */ | |
330 | ||
331 | /* Writing 0xff means "don't care" or "match all". */ | |
332 | ||
2b653e06 | 333 | mon = t->time.tm_mon + 1; |
fe20ba70 | 334 | mon = (mon <= 12) ? bin2bcd(mon) : 0xff; |
7be2c7c9 DB |
335 | |
336 | mday = t->time.tm_mday; | |
fe20ba70 | 337 | mday = (mday >= 1 && mday <= 31) ? bin2bcd(mday) : 0xff; |
7be2c7c9 DB |
338 | |
339 | hrs = t->time.tm_hour; | |
fe20ba70 | 340 | hrs = (hrs < 24) ? bin2bcd(hrs) : 0xff; |
7be2c7c9 DB |
341 | |
342 | min = t->time.tm_min; | |
fe20ba70 | 343 | min = (min < 60) ? bin2bcd(min) : 0xff; |
7be2c7c9 DB |
344 | |
345 | sec = t->time.tm_sec; | |
fe20ba70 | 346 | sec = (sec < 60) ? bin2bcd(sec) : 0xff; |
7be2c7c9 DB |
347 | |
348 | spin_lock_irq(&rtc_lock); | |
349 | ||
350 | /* next rtc irq must not be from previous alarm setting */ | |
7e2a31da | 351 | cmos_irq_disable(cmos, RTC_AIE); |
7be2c7c9 DB |
352 | |
353 | /* update alarm */ | |
354 | CMOS_WRITE(hrs, RTC_HOURS_ALARM); | |
355 | CMOS_WRITE(min, RTC_MINUTES_ALARM); | |
356 | CMOS_WRITE(sec, RTC_SECONDS_ALARM); | |
357 | ||
358 | /* the system may support an "enhanced" alarm */ | |
359 | if (cmos->day_alrm) { | |
360 | CMOS_WRITE(mday, cmos->day_alrm); | |
361 | if (cmos->mon_alrm) | |
362 | CMOS_WRITE(mon, cmos->mon_alrm); | |
363 | } | |
364 | ||
35d3fdd5 DB |
365 | /* FIXME the HPET alarm glue currently ignores day_alrm |
366 | * and mon_alrm ... | |
367 | */ | |
368 | hpet_set_alarm_time(t->time.tm_hour, t->time.tm_min, t->time.tm_sec); | |
369 | ||
7e2a31da DB |
370 | if (t->enabled) |
371 | cmos_irq_enable(cmos, RTC_AIE); | |
7be2c7c9 DB |
372 | |
373 | spin_unlock_irq(&rtc_lock); | |
374 | ||
375 | return 0; | |
376 | } | |
377 | ||
57deb526 | 378 | static int cmos_irq_set_freq(struct device *dev, int freq) |
7be2c7c9 DB |
379 | { |
380 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
381 | int f; | |
382 | unsigned long flags; | |
383 | ||
384 | if (!is_valid_irq(cmos->irq)) | |
385 | return -ENXIO; | |
386 | ||
387 | /* 0 = no irqs; 1 = 2^15 Hz ... 15 = 2^0 Hz */ | |
388 | f = ffs(freq); | |
97144c67 DB |
389 | if (f-- > 16) |
390 | return -EINVAL; | |
391 | f = 16 - f; | |
7be2c7c9 DB |
392 | |
393 | spin_lock_irqsave(&rtc_lock, flags); | |
35d3fdd5 DB |
394 | hpet_set_periodic_freq(freq); |
395 | CMOS_WRITE(RTC_REF_CLCK_32KHZ | f, RTC_FREQ_SELECT); | |
7be2c7c9 DB |
396 | spin_unlock_irqrestore(&rtc_lock, flags); |
397 | ||
398 | return 0; | |
399 | } | |
400 | ||
57deb526 AZ |
401 | static int cmos_irq_set_state(struct device *dev, int enabled) |
402 | { | |
403 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
57deb526 AZ |
404 | unsigned long flags; |
405 | ||
406 | if (!is_valid_irq(cmos->irq)) | |
407 | return -ENXIO; | |
408 | ||
409 | spin_lock_irqsave(&rtc_lock, flags); | |
57deb526 | 410 | |
7e2a31da DB |
411 | if (enabled) |
412 | cmos_irq_enable(cmos, RTC_PIE); | |
413 | else | |
414 | cmos_irq_disable(cmos, RTC_PIE); | |
57deb526 AZ |
415 | |
416 | spin_unlock_irqrestore(&rtc_lock, flags); | |
417 | return 0; | |
418 | } | |
419 | ||
7be2c7c9 DB |
420 | #if defined(CONFIG_RTC_INTF_DEV) || defined(CONFIG_RTC_INTF_DEV_MODULE) |
421 | ||
422 | static int | |
423 | cmos_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) | |
424 | { | |
425 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
7be2c7c9 DB |
426 | unsigned long flags; |
427 | ||
428 | switch (cmd) { | |
429 | case RTC_AIE_OFF: | |
430 | case RTC_AIE_ON: | |
431 | case RTC_UIE_OFF: | |
432 | case RTC_UIE_ON: | |
7be2c7c9 DB |
433 | if (!is_valid_irq(cmos->irq)) |
434 | return -EINVAL; | |
435 | break; | |
35d3fdd5 | 436 | /* PIE ON/OFF is handled by cmos_irq_set_state() */ |
7be2c7c9 DB |
437 | default: |
438 | return -ENOIOCTLCMD; | |
439 | } | |
440 | ||
441 | spin_lock_irqsave(&rtc_lock, flags); | |
7be2c7c9 DB |
442 | switch (cmd) { |
443 | case RTC_AIE_OFF: /* alarm off */ | |
7e2a31da | 444 | cmos_irq_disable(cmos, RTC_AIE); |
7be2c7c9 DB |
445 | break; |
446 | case RTC_AIE_ON: /* alarm on */ | |
7e2a31da | 447 | cmos_irq_enable(cmos, RTC_AIE); |
7be2c7c9 DB |
448 | break; |
449 | case RTC_UIE_OFF: /* update off */ | |
7e2a31da | 450 | cmos_irq_disable(cmos, RTC_UIE); |
7be2c7c9 DB |
451 | break; |
452 | case RTC_UIE_ON: /* update on */ | |
7e2a31da | 453 | cmos_irq_enable(cmos, RTC_UIE); |
7be2c7c9 | 454 | break; |
7be2c7c9 | 455 | } |
7be2c7c9 DB |
456 | spin_unlock_irqrestore(&rtc_lock, flags); |
457 | return 0; | |
458 | } | |
459 | ||
460 | #else | |
461 | #define cmos_rtc_ioctl NULL | |
462 | #endif | |
463 | ||
464 | #if defined(CONFIG_RTC_INTF_PROC) || defined(CONFIG_RTC_INTF_PROC_MODULE) | |
465 | ||
466 | static int cmos_procfs(struct device *dev, struct seq_file *seq) | |
467 | { | |
468 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
469 | unsigned char rtc_control, valid; | |
470 | ||
471 | spin_lock_irq(&rtc_lock); | |
472 | rtc_control = CMOS_READ(RTC_CONTROL); | |
473 | valid = CMOS_READ(RTC_VALID); | |
474 | spin_unlock_irq(&rtc_lock); | |
475 | ||
476 | /* NOTE: at least ICH6 reports battery status using a different | |
477 | * (non-RTC) bit; and SQWE is ignored on many current systems. | |
478 | */ | |
479 | return seq_printf(seq, | |
480 | "periodic_IRQ\t: %s\n" | |
481 | "update_IRQ\t: %s\n" | |
c8626a1d | 482 | "HPET_emulated\t: %s\n" |
7be2c7c9 DB |
483 | // "square_wave\t: %s\n" |
484 | // "BCD\t\t: %s\n" | |
485 | "DST_enable\t: %s\n" | |
486 | "periodic_freq\t: %d\n" | |
487 | "batt_status\t: %s\n", | |
488 | (rtc_control & RTC_PIE) ? "yes" : "no", | |
489 | (rtc_control & RTC_UIE) ? "yes" : "no", | |
c8626a1d | 490 | is_hpet_enabled() ? "yes" : "no", |
7be2c7c9 DB |
491 | // (rtc_control & RTC_SQWE) ? "yes" : "no", |
492 | // (rtc_control & RTC_DM_BINARY) ? "no" : "yes", | |
493 | (rtc_control & RTC_DST_EN) ? "yes" : "no", | |
494 | cmos->rtc->irq_freq, | |
495 | (valid & RTC_VRT) ? "okay" : "dead"); | |
496 | } | |
497 | ||
498 | #else | |
499 | #define cmos_procfs NULL | |
500 | #endif | |
501 | ||
502 | static const struct rtc_class_ops cmos_rtc_ops = { | |
503 | .ioctl = cmos_rtc_ioctl, | |
504 | .read_time = cmos_read_time, | |
505 | .set_time = cmos_set_time, | |
506 | .read_alarm = cmos_read_alarm, | |
507 | .set_alarm = cmos_set_alarm, | |
508 | .proc = cmos_procfs, | |
57deb526 AZ |
509 | .irq_set_freq = cmos_irq_set_freq, |
510 | .irq_set_state = cmos_irq_set_state, | |
7be2c7c9 DB |
511 | }; |
512 | ||
513 | /*----------------------------------------------------------------*/ | |
514 | ||
e07e232c DB |
515 | /* |
516 | * All these chips have at least 64 bytes of address space, shared by | |
517 | * RTC registers and NVRAM. Most of those bytes of NVRAM are used | |
518 | * by boot firmware. Modern chips have 128 or 256 bytes. | |
519 | */ | |
520 | ||
521 | #define NVRAM_OFFSET (RTC_REG_D + 1) | |
522 | ||
523 | static ssize_t | |
524 | cmos_nvram_read(struct kobject *kobj, struct bin_attribute *attr, | |
525 | char *buf, loff_t off, size_t count) | |
526 | { | |
527 | int retval; | |
528 | ||
529 | if (unlikely(off >= attr->size)) | |
530 | return 0; | |
c8fc40cd DB |
531 | if (unlikely(off < 0)) |
532 | return -EINVAL; | |
e07e232c DB |
533 | if ((off + count) > attr->size) |
534 | count = attr->size - off; | |
535 | ||
c8fc40cd | 536 | off += NVRAM_OFFSET; |
e07e232c | 537 | spin_lock_irq(&rtc_lock); |
c8fc40cd DB |
538 | for (retval = 0; count; count--, off++, retval++) { |
539 | if (off < 128) | |
540 | *buf++ = CMOS_READ(off); | |
541 | else if (can_bank2) | |
542 | *buf++ = cmos_read_bank2(off); | |
543 | else | |
544 | break; | |
545 | } | |
e07e232c DB |
546 | spin_unlock_irq(&rtc_lock); |
547 | ||
548 | return retval; | |
549 | } | |
550 | ||
551 | static ssize_t | |
552 | cmos_nvram_write(struct kobject *kobj, struct bin_attribute *attr, | |
553 | char *buf, loff_t off, size_t count) | |
554 | { | |
555 | struct cmos_rtc *cmos; | |
556 | int retval; | |
557 | ||
558 | cmos = dev_get_drvdata(container_of(kobj, struct device, kobj)); | |
559 | if (unlikely(off >= attr->size)) | |
560 | return -EFBIG; | |
c8fc40cd DB |
561 | if (unlikely(off < 0)) |
562 | return -EINVAL; | |
e07e232c DB |
563 | if ((off + count) > attr->size) |
564 | count = attr->size - off; | |
565 | ||
566 | /* NOTE: on at least PCs and Ataris, the boot firmware uses a | |
567 | * checksum on part of the NVRAM data. That's currently ignored | |
568 | * here. If userspace is smart enough to know what fields of | |
569 | * NVRAM to update, updating checksums is also part of its job. | |
570 | */ | |
c8fc40cd | 571 | off += NVRAM_OFFSET; |
e07e232c | 572 | spin_lock_irq(&rtc_lock); |
c8fc40cd | 573 | for (retval = 0; count; count--, off++, retval++) { |
e07e232c DB |
574 | /* don't trash RTC registers */ |
575 | if (off == cmos->day_alrm | |
576 | || off == cmos->mon_alrm | |
577 | || off == cmos->century) | |
578 | buf++; | |
c8fc40cd | 579 | else if (off < 128) |
e07e232c | 580 | CMOS_WRITE(*buf++, off); |
c8fc40cd DB |
581 | else if (can_bank2) |
582 | cmos_write_bank2(*buf++, off); | |
583 | else | |
584 | break; | |
e07e232c DB |
585 | } |
586 | spin_unlock_irq(&rtc_lock); | |
587 | ||
588 | return retval; | |
589 | } | |
590 | ||
591 | static struct bin_attribute nvram = { | |
592 | .attr = { | |
593 | .name = "nvram", | |
594 | .mode = S_IRUGO | S_IWUSR, | |
e07e232c DB |
595 | }, |
596 | ||
597 | .read = cmos_nvram_read, | |
598 | .write = cmos_nvram_write, | |
599 | /* size gets set up later */ | |
600 | }; | |
601 | ||
602 | /*----------------------------------------------------------------*/ | |
603 | ||
7be2c7c9 DB |
604 | static struct cmos_rtc cmos_rtc; |
605 | ||
606 | static irqreturn_t cmos_interrupt(int irq, void *p) | |
607 | { | |
608 | u8 irqstat; | |
8a0bdfd7 | 609 | u8 rtc_control; |
7be2c7c9 DB |
610 | |
611 | spin_lock(&rtc_lock); | |
35d3fdd5 DB |
612 | |
613 | /* When the HPET interrupt handler calls us, the interrupt | |
614 | * status is passed as arg1 instead of the irq number. But | |
615 | * always clear irq status, even when HPET is in the way. | |
616 | * | |
617 | * Note that HPET and RTC are almost certainly out of phase, | |
618 | * giving different IRQ status ... | |
9d8af78b | 619 | */ |
35d3fdd5 DB |
620 | irqstat = CMOS_READ(RTC_INTR_FLAGS); |
621 | rtc_control = CMOS_READ(RTC_CONTROL); | |
9d8af78b BW |
622 | if (is_hpet_enabled()) |
623 | irqstat = (unsigned long)irq & 0xF0; | |
35d3fdd5 | 624 | irqstat &= (rtc_control & RTC_IRQMASK) | RTC_IRQF; |
8a0bdfd7 DB |
625 | |
626 | /* All Linux RTC alarms should be treated as if they were oneshot. | |
627 | * Similar code may be needed in system wakeup paths, in case the | |
628 | * alarm woke the system. | |
629 | */ | |
630 | if (irqstat & RTC_AIE) { | |
631 | rtc_control &= ~RTC_AIE; | |
632 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
35d3fdd5 DB |
633 | hpet_mask_rtc_irq_bit(RTC_AIE); |
634 | ||
8a0bdfd7 DB |
635 | CMOS_READ(RTC_INTR_FLAGS); |
636 | } | |
7be2c7c9 DB |
637 | spin_unlock(&rtc_lock); |
638 | ||
bcd9b89c | 639 | if (is_intr(irqstat)) { |
7be2c7c9 DB |
640 | rtc_update_irq(p, 1, irqstat); |
641 | return IRQ_HANDLED; | |
642 | } else | |
643 | return IRQ_NONE; | |
644 | } | |
645 | ||
41ac8df9 | 646 | #ifdef CONFIG_PNP |
7be2c7c9 DB |
647 | #define INITSECTION |
648 | ||
649 | #else | |
7be2c7c9 DB |
650 | #define INITSECTION __init |
651 | #endif | |
652 | ||
653 | static int INITSECTION | |
654 | cmos_do_probe(struct device *dev, struct resource *ports, int rtc_irq) | |
655 | { | |
656 | struct cmos_rtc_board_info *info = dev->platform_data; | |
657 | int retval = 0; | |
658 | unsigned char rtc_control; | |
e07e232c | 659 | unsigned address_space; |
7be2c7c9 DB |
660 | |
661 | /* there can be only one ... */ | |
662 | if (cmos_rtc.dev) | |
663 | return -EBUSY; | |
664 | ||
665 | if (!ports) | |
666 | return -ENODEV; | |
667 | ||
05440dfc DB |
668 | /* Claim I/O ports ASAP, minimizing conflict with legacy driver. |
669 | * | |
670 | * REVISIT non-x86 systems may instead use memory space resources | |
671 | * (needing ioremap etc), not i/o space resources like this ... | |
672 | */ | |
673 | ports = request_region(ports->start, | |
674 | ports->end + 1 - ports->start, | |
675 | driver_name); | |
676 | if (!ports) { | |
677 | dev_dbg(dev, "i/o registers already in use\n"); | |
678 | return -EBUSY; | |
679 | } | |
680 | ||
7be2c7c9 DB |
681 | cmos_rtc.irq = rtc_irq; |
682 | cmos_rtc.iomem = ports; | |
683 | ||
e07e232c DB |
684 | /* Heuristic to deduce NVRAM size ... do what the legacy NVRAM |
685 | * driver did, but don't reject unknown configs. Old hardware | |
c8fc40cd DB |
686 | * won't address 128 bytes. Newer chips have multiple banks, |
687 | * though they may not be listed in one I/O resource. | |
e07e232c DB |
688 | */ |
689 | #if defined(CONFIG_ATARI) | |
690 | address_space = 64; | |
582defd8 | 691 | #elif defined(__i386__) || defined(__x86_64__) || defined(__arm__) || defined(__sparc__) |
e07e232c DB |
692 | address_space = 128; |
693 | #else | |
694 | #warning Assuming 128 bytes of RTC+NVRAM address space, not 64 bytes. | |
695 | address_space = 128; | |
696 | #endif | |
c8fc40cd DB |
697 | if (can_bank2 && ports->end > (ports->start + 1)) |
698 | address_space = 256; | |
e07e232c | 699 | |
87ac84f4 DB |
700 | /* For ACPI systems extension info comes from the FADT. On others, |
701 | * board specific setup provides it as appropriate. Systems where | |
702 | * the alarm IRQ isn't automatically a wakeup IRQ (like ACPI, and | |
703 | * some almost-clones) can provide hooks to make that behave. | |
e07e232c DB |
704 | * |
705 | * Note that ACPI doesn't preclude putting these registers into | |
706 | * "extended" areas of the chip, including some that we won't yet | |
707 | * expect CMOS_READ and friends to handle. | |
7be2c7c9 DB |
708 | */ |
709 | if (info) { | |
e07e232c DB |
710 | if (info->rtc_day_alarm && info->rtc_day_alarm < 128) |
711 | cmos_rtc.day_alrm = info->rtc_day_alarm; | |
712 | if (info->rtc_mon_alarm && info->rtc_mon_alarm < 128) | |
713 | cmos_rtc.mon_alrm = info->rtc_mon_alarm; | |
714 | if (info->rtc_century && info->rtc_century < 128) | |
715 | cmos_rtc.century = info->rtc_century; | |
87ac84f4 DB |
716 | |
717 | if (info->wake_on && info->wake_off) { | |
718 | cmos_rtc.wake_on = info->wake_on; | |
719 | cmos_rtc.wake_off = info->wake_off; | |
720 | } | |
7be2c7c9 DB |
721 | } |
722 | ||
723 | cmos_rtc.rtc = rtc_device_register(driver_name, dev, | |
724 | &cmos_rtc_ops, THIS_MODULE); | |
05440dfc DB |
725 | if (IS_ERR(cmos_rtc.rtc)) { |
726 | retval = PTR_ERR(cmos_rtc.rtc); | |
727 | goto cleanup0; | |
728 | } | |
7be2c7c9 DB |
729 | |
730 | cmos_rtc.dev = dev; | |
731 | dev_set_drvdata(dev, &cmos_rtc); | |
cd966209 | 732 | rename_region(ports, cmos_rtc.rtc->dev.bus_id); |
7be2c7c9 DB |
733 | |
734 | spin_lock_irq(&rtc_lock); | |
735 | ||
736 | /* force periodic irq to CMOS reset default of 1024Hz; | |
737 | * | |
738 | * REVISIT it's been reported that at least one x86_64 ALI mobo | |
739 | * doesn't use 32KHz here ... for portability we might need to | |
740 | * do something about other clock frequencies. | |
741 | */ | |
7be2c7c9 | 742 | cmos_rtc.rtc->irq_freq = 1024; |
35d3fdd5 DB |
743 | hpet_set_periodic_freq(cmos_rtc.rtc->irq_freq); |
744 | CMOS_WRITE(RTC_REF_CLCK_32KHZ | 0x06, RTC_FREQ_SELECT); | |
7be2c7c9 | 745 | |
7e2a31da DB |
746 | /* disable irqs */ |
747 | cmos_irq_disable(&cmos_rtc, RTC_PIE | RTC_AIE | RTC_UIE); | |
35d3fdd5 | 748 | |
7e2a31da | 749 | rtc_control = CMOS_READ(RTC_CONTROL); |
7be2c7c9 DB |
750 | |
751 | spin_unlock_irq(&rtc_lock); | |
752 | ||
753 | /* FIXME teach the alarm code how to handle binary mode; | |
754 | * <asm-generic/rtc.h> doesn't know 12-hour mode either. | |
755 | */ | |
582defd8 DM |
756 | if (is_valid_irq(rtc_irq) && |
757 | (!(rtc_control & RTC_24H) || (rtc_control & (RTC_DM_BINARY)))) { | |
7be2c7c9 DB |
758 | dev_dbg(dev, "only 24-hr BCD mode supported\n"); |
759 | retval = -ENXIO; | |
760 | goto cleanup1; | |
761 | } | |
762 | ||
9d8af78b BW |
763 | if (is_valid_irq(rtc_irq)) { |
764 | irq_handler_t rtc_cmos_int_handler; | |
765 | ||
766 | if (is_hpet_enabled()) { | |
767 | int err; | |
768 | ||
769 | rtc_cmos_int_handler = hpet_rtc_interrupt; | |
770 | err = hpet_register_irq_handler(cmos_interrupt); | |
771 | if (err != 0) { | |
772 | printk(KERN_WARNING "hpet_register_irq_handler " | |
773 | " failed in rtc_init()."); | |
774 | goto cleanup1; | |
775 | } | |
776 | } else | |
777 | rtc_cmos_int_handler = cmos_interrupt; | |
778 | ||
779 | retval = request_irq(rtc_irq, rtc_cmos_int_handler, | |
780 | IRQF_DISABLED, cmos_rtc.rtc->dev.bus_id, | |
ab6a2d70 | 781 | cmos_rtc.rtc); |
9d8af78b BW |
782 | if (retval < 0) { |
783 | dev_dbg(dev, "IRQ %d is already in use\n", rtc_irq); | |
784 | goto cleanup1; | |
785 | } | |
7be2c7c9 | 786 | } |
9d8af78b | 787 | hpet_rtc_timer_init(); |
7be2c7c9 | 788 | |
e07e232c DB |
789 | /* export at least the first block of NVRAM */ |
790 | nvram.size = address_space - NVRAM_OFFSET; | |
791 | retval = sysfs_create_bin_file(&dev->kobj, &nvram); | |
792 | if (retval < 0) { | |
793 | dev_dbg(dev, "can't create nvram file? %d\n", retval); | |
794 | goto cleanup2; | |
795 | } | |
7be2c7c9 | 796 | |
80bb26d4 | 797 | pr_info("%s: alarms up to one %s%s, %zd bytes nvram%s\n", |
cd966209 | 798 | cmos_rtc.rtc->dev.bus_id, |
7be2c7c9 DB |
799 | is_valid_irq(rtc_irq) |
800 | ? (cmos_rtc.mon_alrm | |
801 | ? "year" | |
802 | : (cmos_rtc.day_alrm | |
803 | ? "month" : "day")) | |
804 | : "no", | |
35d3fdd5 | 805 | cmos_rtc.century ? ", y3k" : "", |
c8fc40cd | 806 | nvram.size, |
35d3fdd5 | 807 | is_hpet_enabled() ? ", hpet irqs" : ""); |
7be2c7c9 DB |
808 | |
809 | return 0; | |
810 | ||
e07e232c DB |
811 | cleanup2: |
812 | if (is_valid_irq(rtc_irq)) | |
813 | free_irq(rtc_irq, cmos_rtc.rtc); | |
7be2c7c9 | 814 | cleanup1: |
05440dfc | 815 | cmos_rtc.dev = NULL; |
7be2c7c9 | 816 | rtc_device_unregister(cmos_rtc.rtc); |
05440dfc DB |
817 | cleanup0: |
818 | release_region(ports->start, ports->end + 1 - ports->start); | |
7be2c7c9 DB |
819 | return retval; |
820 | } | |
821 | ||
822 | static void cmos_do_shutdown(void) | |
823 | { | |
7be2c7c9 | 824 | spin_lock_irq(&rtc_lock); |
7e2a31da | 825 | cmos_irq_disable(&cmos_rtc, RTC_IRQMASK); |
7be2c7c9 DB |
826 | spin_unlock_irq(&rtc_lock); |
827 | } | |
828 | ||
829 | static void __exit cmos_do_remove(struct device *dev) | |
830 | { | |
831 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
05440dfc | 832 | struct resource *ports; |
7be2c7c9 DB |
833 | |
834 | cmos_do_shutdown(); | |
835 | ||
e07e232c DB |
836 | sysfs_remove_bin_file(&dev->kobj, &nvram); |
837 | ||
9d8af78b | 838 | if (is_valid_irq(cmos->irq)) { |
05440dfc | 839 | free_irq(cmos->irq, cmos->rtc); |
9d8af78b BW |
840 | hpet_unregister_irq_handler(cmos_interrupt); |
841 | } | |
7be2c7c9 | 842 | |
05440dfc DB |
843 | rtc_device_unregister(cmos->rtc); |
844 | cmos->rtc = NULL; | |
7be2c7c9 | 845 | |
05440dfc DB |
846 | ports = cmos->iomem; |
847 | release_region(ports->start, ports->end + 1 - ports->start); | |
848 | cmos->iomem = NULL; | |
849 | ||
850 | cmos->dev = NULL; | |
7be2c7c9 DB |
851 | dev_set_drvdata(dev, NULL); |
852 | } | |
853 | ||
854 | #ifdef CONFIG_PM | |
855 | ||
856 | static int cmos_suspend(struct device *dev, pm_message_t mesg) | |
857 | { | |
858 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
bcd9b89c | 859 | unsigned char tmp; |
7be2c7c9 DB |
860 | |
861 | /* only the alarm might be a wakeup event source */ | |
862 | spin_lock_irq(&rtc_lock); | |
863 | cmos->suspend_ctrl = tmp = CMOS_READ(RTC_CONTROL); | |
864 | if (tmp & (RTC_PIE|RTC_AIE|RTC_UIE)) { | |
35d3fdd5 | 865 | unsigned char mask; |
bcd9b89c | 866 | |
74c4633d | 867 | if (device_may_wakeup(dev)) |
35d3fdd5 | 868 | mask = RTC_IRQMASK & ~RTC_AIE; |
7be2c7c9 | 869 | else |
35d3fdd5 DB |
870 | mask = RTC_IRQMASK; |
871 | tmp &= ~mask; | |
7be2c7c9 | 872 | CMOS_WRITE(tmp, RTC_CONTROL); |
35d3fdd5 DB |
873 | hpet_mask_rtc_irq_bit(mask); |
874 | ||
7e2a31da | 875 | cmos_checkintr(cmos, tmp); |
bcd9b89c | 876 | } |
7be2c7c9 DB |
877 | spin_unlock_irq(&rtc_lock); |
878 | ||
87ac84f4 DB |
879 | if (tmp & RTC_AIE) { |
880 | cmos->enabled_wake = 1; | |
881 | if (cmos->wake_on) | |
882 | cmos->wake_on(dev); | |
883 | else | |
884 | enable_irq_wake(cmos->irq); | |
885 | } | |
7be2c7c9 DB |
886 | |
887 | pr_debug("%s: suspend%s, ctrl %02x\n", | |
cd966209 | 888 | cmos_rtc.rtc->dev.bus_id, |
7be2c7c9 DB |
889 | (tmp & RTC_AIE) ? ", alarm may wake" : "", |
890 | tmp); | |
891 | ||
892 | return 0; | |
893 | } | |
894 | ||
74c4633d RW |
895 | /* We want RTC alarms to wake us from e.g. ACPI G2/S5 "soft off", even |
896 | * after a detour through G3 "mechanical off", although the ACPI spec | |
897 | * says wakeup should only work from G1/S4 "hibernate". To most users, | |
898 | * distinctions between S4 and S5 are pointless. So when the hardware | |
899 | * allows, don't draw that distinction. | |
900 | */ | |
901 | static inline int cmos_poweroff(struct device *dev) | |
902 | { | |
903 | return cmos_suspend(dev, PMSG_HIBERNATE); | |
904 | } | |
905 | ||
7be2c7c9 DB |
906 | static int cmos_resume(struct device *dev) |
907 | { | |
908 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
909 | unsigned char tmp = cmos->suspend_ctrl; | |
910 | ||
7be2c7c9 | 911 | /* re-enable any irqs previously active */ |
35d3fdd5 DB |
912 | if (tmp & RTC_IRQMASK) { |
913 | unsigned char mask; | |
7be2c7c9 | 914 | |
87ac84f4 DB |
915 | if (cmos->enabled_wake) { |
916 | if (cmos->wake_off) | |
917 | cmos->wake_off(dev); | |
918 | else | |
919 | disable_irq_wake(cmos->irq); | |
920 | cmos->enabled_wake = 0; | |
921 | } | |
7be2c7c9 DB |
922 | |
923 | spin_lock_irq(&rtc_lock); | |
35d3fdd5 DB |
924 | do { |
925 | CMOS_WRITE(tmp, RTC_CONTROL); | |
926 | hpet_set_rtc_irq_bit(tmp & RTC_IRQMASK); | |
927 | ||
928 | mask = CMOS_READ(RTC_INTR_FLAGS); | |
929 | mask &= (tmp & RTC_IRQMASK) | RTC_IRQF; | |
7e2a31da | 930 | if (!is_hpet_enabled() || !is_intr(mask)) |
35d3fdd5 DB |
931 | break; |
932 | ||
933 | /* force one-shot behavior if HPET blocked | |
934 | * the wake alarm's irq | |
935 | */ | |
936 | rtc_update_irq(cmos->rtc, 1, mask); | |
937 | tmp &= ~RTC_AIE; | |
938 | hpet_mask_rtc_irq_bit(RTC_AIE); | |
939 | } while (mask & RTC_AIE); | |
bcd9b89c | 940 | spin_unlock_irq(&rtc_lock); |
7be2c7c9 DB |
941 | } |
942 | ||
943 | pr_debug("%s: resume, ctrl %02x\n", | |
cd966209 | 944 | cmos_rtc.rtc->dev.bus_id, |
35d3fdd5 | 945 | tmp); |
7be2c7c9 DB |
946 | |
947 | return 0; | |
948 | } | |
949 | ||
950 | #else | |
951 | #define cmos_suspend NULL | |
952 | #define cmos_resume NULL | |
74c4633d RW |
953 | |
954 | static inline int cmos_poweroff(struct device *dev) | |
955 | { | |
956 | return -ENOSYS; | |
957 | } | |
958 | ||
7be2c7c9 DB |
959 | #endif |
960 | ||
961 | /*----------------------------------------------------------------*/ | |
962 | ||
e07e232c DB |
963 | /* On non-x86 systems, a "CMOS" RTC lives most naturally on platform_bus. |
964 | * ACPI systems always list these as PNPACPI devices, and pre-ACPI PCs | |
965 | * probably list them in similar PNPBIOS tables; so PNP is more common. | |
966 | * | |
967 | * We don't use legacy "poke at the hardware" probing. Ancient PCs that | |
968 | * predate even PNPBIOS should set up platform_bus devices. | |
7be2c7c9 DB |
969 | */ |
970 | ||
a474aaed BH |
971 | #ifdef CONFIG_ACPI |
972 | ||
973 | #include <linux/acpi.h> | |
974 | ||
975 | #ifdef CONFIG_PM | |
976 | static u32 rtc_handler(void *context) | |
977 | { | |
978 | acpi_clear_event(ACPI_EVENT_RTC); | |
979 | acpi_disable_event(ACPI_EVENT_RTC, 0); | |
980 | return ACPI_INTERRUPT_HANDLED; | |
981 | } | |
982 | ||
983 | static inline void rtc_wake_setup(void) | |
984 | { | |
985 | acpi_install_fixed_event_handler(ACPI_EVENT_RTC, rtc_handler, NULL); | |
986 | /* | |
987 | * After the RTC handler is installed, the Fixed_RTC event should | |
988 | * be disabled. Only when the RTC alarm is set will it be enabled. | |
989 | */ | |
990 | acpi_clear_event(ACPI_EVENT_RTC); | |
991 | acpi_disable_event(ACPI_EVENT_RTC, 0); | |
992 | } | |
993 | ||
994 | static void rtc_wake_on(struct device *dev) | |
995 | { | |
996 | acpi_clear_event(ACPI_EVENT_RTC); | |
997 | acpi_enable_event(ACPI_EVENT_RTC, 0); | |
998 | } | |
999 | ||
1000 | static void rtc_wake_off(struct device *dev) | |
1001 | { | |
1002 | acpi_disable_event(ACPI_EVENT_RTC, 0); | |
1003 | } | |
1004 | #else | |
1005 | #define rtc_wake_setup() do{}while(0) | |
1006 | #define rtc_wake_on NULL | |
1007 | #define rtc_wake_off NULL | |
1008 | #endif | |
1009 | ||
1010 | /* Every ACPI platform has a mc146818 compatible "cmos rtc". Here we find | |
1011 | * its device node and pass extra config data. This helps its driver use | |
1012 | * capabilities that the now-obsolete mc146818 didn't have, and informs it | |
1013 | * that this board's RTC is wakeup-capable (per ACPI spec). | |
1014 | */ | |
1015 | static struct cmos_rtc_board_info acpi_rtc_info; | |
1016 | ||
1017 | static void __devinit | |
1018 | cmos_wake_setup(struct device *dev) | |
1019 | { | |
1020 | if (acpi_disabled) | |
1021 | return; | |
1022 | ||
1023 | rtc_wake_setup(); | |
1024 | acpi_rtc_info.wake_on = rtc_wake_on; | |
1025 | acpi_rtc_info.wake_off = rtc_wake_off; | |
1026 | ||
1027 | /* workaround bug in some ACPI tables */ | |
1028 | if (acpi_gbl_FADT.month_alarm && !acpi_gbl_FADT.day_alarm) { | |
1029 | dev_dbg(dev, "bogus FADT month_alarm (%d)\n", | |
1030 | acpi_gbl_FADT.month_alarm); | |
1031 | acpi_gbl_FADT.month_alarm = 0; | |
1032 | } | |
1033 | ||
1034 | acpi_rtc_info.rtc_day_alarm = acpi_gbl_FADT.day_alarm; | |
1035 | acpi_rtc_info.rtc_mon_alarm = acpi_gbl_FADT.month_alarm; | |
1036 | acpi_rtc_info.rtc_century = acpi_gbl_FADT.century; | |
1037 | ||
1038 | /* NOTE: S4_RTC_WAKE is NOT currently useful to Linux */ | |
1039 | if (acpi_gbl_FADT.flags & ACPI_FADT_S4_RTC_WAKE) | |
1040 | dev_info(dev, "RTC can wake from S4\n"); | |
1041 | ||
1042 | dev->platform_data = &acpi_rtc_info; | |
1043 | ||
1044 | /* RTC always wakes from S1/S2/S3, and often S4/STD */ | |
1045 | device_init_wakeup(dev, 1); | |
1046 | } | |
1047 | ||
1048 | #else | |
1049 | ||
1050 | static void __devinit | |
1051 | cmos_wake_setup(struct device *dev) | |
1052 | { | |
1053 | } | |
1054 | ||
1055 | #endif | |
1056 | ||
41ac8df9 | 1057 | #ifdef CONFIG_PNP |
7be2c7c9 DB |
1058 | |
1059 | #include <linux/pnp.h> | |
1060 | ||
1061 | static int __devinit | |
1062 | cmos_pnp_probe(struct pnp_dev *pnp, const struct pnp_device_id *id) | |
1063 | { | |
a474aaed BH |
1064 | cmos_wake_setup(&pnp->dev); |
1065 | ||
6cd8fa87 MG |
1066 | if (pnp_port_start(pnp,0) == 0x70 && !pnp_irq_valid(pnp,0)) |
1067 | /* Some machines contain a PNP entry for the RTC, but | |
1068 | * don't define the IRQ. It should always be safe to | |
1069 | * hardcode it in these cases | |
1070 | */ | |
8766ad0c BH |
1071 | return cmos_do_probe(&pnp->dev, |
1072 | pnp_get_resource(pnp, IORESOURCE_IO, 0), 8); | |
6cd8fa87 MG |
1073 | else |
1074 | return cmos_do_probe(&pnp->dev, | |
8766ad0c BH |
1075 | pnp_get_resource(pnp, IORESOURCE_IO, 0), |
1076 | pnp_irq(pnp, 0)); | |
7be2c7c9 DB |
1077 | } |
1078 | ||
1079 | static void __exit cmos_pnp_remove(struct pnp_dev *pnp) | |
1080 | { | |
1081 | cmos_do_remove(&pnp->dev); | |
1082 | } | |
1083 | ||
1084 | #ifdef CONFIG_PM | |
1085 | ||
1086 | static int cmos_pnp_suspend(struct pnp_dev *pnp, pm_message_t mesg) | |
1087 | { | |
1088 | return cmos_suspend(&pnp->dev, mesg); | |
1089 | } | |
1090 | ||
1091 | static int cmos_pnp_resume(struct pnp_dev *pnp) | |
1092 | { | |
1093 | return cmos_resume(&pnp->dev); | |
1094 | } | |
1095 | ||
1096 | #else | |
1097 | #define cmos_pnp_suspend NULL | |
1098 | #define cmos_pnp_resume NULL | |
1099 | #endif | |
1100 | ||
74c4633d RW |
1101 | static void cmos_pnp_shutdown(struct device *pdev) |
1102 | { | |
1103 | if (system_state == SYSTEM_POWER_OFF && !cmos_poweroff(pdev)) | |
1104 | return; | |
1105 | ||
1106 | cmos_do_shutdown(); | |
1107 | } | |
7be2c7c9 DB |
1108 | |
1109 | static const struct pnp_device_id rtc_ids[] = { | |
1110 | { .id = "PNP0b00", }, | |
1111 | { .id = "PNP0b01", }, | |
1112 | { .id = "PNP0b02", }, | |
1113 | { }, | |
1114 | }; | |
1115 | MODULE_DEVICE_TABLE(pnp, rtc_ids); | |
1116 | ||
1117 | static struct pnp_driver cmos_pnp_driver = { | |
1118 | .name = (char *) driver_name, | |
1119 | .id_table = rtc_ids, | |
1120 | .probe = cmos_pnp_probe, | |
1121 | .remove = __exit_p(cmos_pnp_remove), | |
1122 | ||
1123 | /* flag ensures resume() gets called, and stops syslog spam */ | |
1124 | .flags = PNP_DRIVER_RES_DO_NOT_CHANGE, | |
1125 | .suspend = cmos_pnp_suspend, | |
1126 | .resume = cmos_pnp_resume, | |
74c4633d RW |
1127 | .driver = { |
1128 | .name = (char *)driver_name, | |
1129 | .shutdown = cmos_pnp_shutdown, | |
1130 | } | |
7be2c7c9 DB |
1131 | }; |
1132 | ||
1da2e3d6 | 1133 | #endif /* CONFIG_PNP */ |
7be2c7c9 DB |
1134 | |
1135 | /*----------------------------------------------------------------*/ | |
1136 | ||
41ac8df9 | 1137 | /* Platform setup should have set up an RTC device, when PNP is |
bcd9b89c | 1138 | * unavailable ... this could happen even on (older) PCs. |
7be2c7c9 DB |
1139 | */ |
1140 | ||
1141 | static int __init cmos_platform_probe(struct platform_device *pdev) | |
1142 | { | |
a474aaed | 1143 | cmos_wake_setup(&pdev->dev); |
7be2c7c9 DB |
1144 | return cmos_do_probe(&pdev->dev, |
1145 | platform_get_resource(pdev, IORESOURCE_IO, 0), | |
1146 | platform_get_irq(pdev, 0)); | |
1147 | } | |
1148 | ||
1149 | static int __exit cmos_platform_remove(struct platform_device *pdev) | |
1150 | { | |
1151 | cmos_do_remove(&pdev->dev); | |
1152 | return 0; | |
1153 | } | |
1154 | ||
1155 | static void cmos_platform_shutdown(struct platform_device *pdev) | |
1156 | { | |
74c4633d RW |
1157 | if (system_state == SYSTEM_POWER_OFF && !cmos_poweroff(&pdev->dev)) |
1158 | return; | |
1159 | ||
7be2c7c9 DB |
1160 | cmos_do_shutdown(); |
1161 | } | |
1162 | ||
ad28a07b KS |
1163 | /* work with hotplug and coldplug */ |
1164 | MODULE_ALIAS("platform:rtc_cmos"); | |
1165 | ||
7be2c7c9 DB |
1166 | static struct platform_driver cmos_platform_driver = { |
1167 | .remove = __exit_p(cmos_platform_remove), | |
1168 | .shutdown = cmos_platform_shutdown, | |
1169 | .driver = { | |
1170 | .name = (char *) driver_name, | |
1171 | .suspend = cmos_suspend, | |
1172 | .resume = cmos_resume, | |
1173 | } | |
1174 | }; | |
1175 | ||
1176 | static int __init cmos_init(void) | |
1177 | { | |
72f22b1e BH |
1178 | int retval = 0; |
1179 | ||
1da2e3d6 | 1180 | #ifdef CONFIG_PNP |
72f22b1e BH |
1181 | pnp_register_driver(&cmos_pnp_driver); |
1182 | #endif | |
1183 | ||
1184 | if (!cmos_rtc.dev) | |
1185 | retval = platform_driver_probe(&cmos_platform_driver, | |
1186 | cmos_platform_probe); | |
1187 | ||
1188 | if (retval == 0) | |
1189 | return 0; | |
1190 | ||
1191 | #ifdef CONFIG_PNP | |
1192 | pnp_unregister_driver(&cmos_pnp_driver); | |
1193 | #endif | |
1194 | return retval; | |
7be2c7c9 DB |
1195 | } |
1196 | module_init(cmos_init); | |
1197 | ||
1198 | static void __exit cmos_exit(void) | |
1199 | { | |
1da2e3d6 | 1200 | #ifdef CONFIG_PNP |
72f22b1e BH |
1201 | pnp_unregister_driver(&cmos_pnp_driver); |
1202 | #endif | |
7be2c7c9 DB |
1203 | platform_driver_unregister(&cmos_platform_driver); |
1204 | } | |
1205 | module_exit(cmos_exit); | |
1206 | ||
1207 | ||
7be2c7c9 DB |
1208 | MODULE_AUTHOR("David Brownell"); |
1209 | MODULE_DESCRIPTION("Driver for PC-style 'CMOS' RTCs"); | |
1210 | MODULE_LICENSE("GPL"); |