Commit | Line | Data |
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7be2c7c9 DB |
1 | /* |
2 | * RTC class driver for "CMOS RTC": PCs, ACPI, etc | |
3 | * | |
4 | * Copyright (C) 1996 Paul Gortmaker (drivers/char/rtc.c) | |
5 | * Copyright (C) 2006 David Brownell (convert to new framework) | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
12 | ||
13 | /* | |
14 | * The original "cmos clock" chip was an MC146818 chip, now obsolete. | |
15 | * That defined the register interface now provided by all PCs, some | |
16 | * non-PC systems, and incorporated into ACPI. Modern PC chipsets | |
17 | * integrate an MC146818 clone in their southbridge, and boards use | |
18 | * that instead of discrete clones like the DS12887 or M48T86. There | |
19 | * are also clones that connect using the LPC bus. | |
20 | * | |
21 | * That register API is also used directly by various other drivers | |
22 | * (notably for integrated NVRAM), infrastructure (x86 has code to | |
23 | * bypass the RTC framework, directly reading the RTC during boot | |
24 | * and updating minutes/seconds for systems using NTP synch) and | |
25 | * utilities (like userspace 'hwclock', if no /dev node exists). | |
26 | * | |
27 | * So **ALL** calls to CMOS_READ and CMOS_WRITE must be done with | |
28 | * interrupts disabled, holding the global rtc_lock, to exclude those | |
29 | * other drivers and utilities on correctly configured systems. | |
30 | */ | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/spinlock.h> | |
36 | #include <linux/platform_device.h> | |
37 | #include <linux/mod_devicetable.h> | |
38 | ||
9d8af78b BW |
39 | #ifdef CONFIG_HPET_EMULATE_RTC |
40 | #include <asm/hpet.h> | |
41 | #endif | |
42 | ||
7be2c7c9 DB |
43 | /* this is for "generic access to PC-style RTC" using CMOS_READ/CMOS_WRITE */ |
44 | #include <asm-generic/rtc.h> | |
45 | ||
9d8af78b BW |
46 | #ifndef CONFIG_HPET_EMULATE_RTC |
47 | #define is_hpet_enabled() 0 | |
48 | #define hpet_set_alarm_time(hrs, min, sec) do { } while (0) | |
49 | #define hpet_set_periodic_freq(arg) 0 | |
50 | #define hpet_mask_rtc_irq_bit(arg) do { } while (0) | |
51 | #define hpet_set_rtc_irq_bit(arg) do { } while (0) | |
52 | #define hpet_rtc_timer_init() do { } while (0) | |
53 | #define hpet_register_irq_handler(h) 0 | |
54 | #define hpet_unregister_irq_handler(h) do { } while (0) | |
55 | extern irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id); | |
56 | #endif | |
7be2c7c9 DB |
57 | |
58 | struct cmos_rtc { | |
59 | struct rtc_device *rtc; | |
60 | struct device *dev; | |
61 | int irq; | |
62 | struct resource *iomem; | |
63 | ||
87ac84f4 DB |
64 | void (*wake_on)(struct device *); |
65 | void (*wake_off)(struct device *); | |
66 | ||
67 | u8 enabled_wake; | |
7be2c7c9 DB |
68 | u8 suspend_ctrl; |
69 | ||
70 | /* newer hardware extends the original register set */ | |
71 | u8 day_alrm; | |
72 | u8 mon_alrm; | |
73 | u8 century; | |
74 | }; | |
75 | ||
76 | /* both platform and pnp busses use negative numbers for invalid irqs */ | |
77 | #define is_valid_irq(n) ((n) >= 0) | |
78 | ||
79 | static const char driver_name[] = "rtc_cmos"; | |
80 | ||
bcd9b89c DB |
81 | /* The RTC_INTR register may have e.g. RTC_PF set even if RTC_PIE is clear; |
82 | * always mask it against the irq enable bits in RTC_CONTROL. Bit values | |
83 | * are the same: PF==PIE, AF=AIE, UF=UIE; so RTC_IRQMASK works with both. | |
84 | */ | |
85 | #define RTC_IRQMASK (RTC_PF | RTC_AF | RTC_UF) | |
86 | ||
87 | static inline int is_intr(u8 rtc_intr) | |
88 | { | |
89 | if (!(rtc_intr & RTC_IRQF)) | |
90 | return 0; | |
91 | return rtc_intr & RTC_IRQMASK; | |
92 | } | |
93 | ||
7be2c7c9 DB |
94 | /*----------------------------------------------------------------*/ |
95 | ||
96 | static int cmos_read_time(struct device *dev, struct rtc_time *t) | |
97 | { | |
98 | /* REVISIT: if the clock has a "century" register, use | |
99 | * that instead of the heuristic in get_rtc_time(). | |
100 | * That'll make Y3K compatility (year > 2070) easy! | |
101 | */ | |
102 | get_rtc_time(t); | |
103 | return 0; | |
104 | } | |
105 | ||
106 | static int cmos_set_time(struct device *dev, struct rtc_time *t) | |
107 | { | |
108 | /* REVISIT: set the "century" register if available | |
109 | * | |
110 | * NOTE: this ignores the issue whereby updating the seconds | |
111 | * takes effect exactly 500ms after we write the register. | |
112 | * (Also queueing and other delays before we get this far.) | |
113 | */ | |
114 | return set_rtc_time(t); | |
115 | } | |
116 | ||
117 | static int cmos_read_alarm(struct device *dev, struct rtc_wkalrm *t) | |
118 | { | |
119 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
120 | unsigned char rtc_control; | |
121 | ||
122 | if (!is_valid_irq(cmos->irq)) | |
123 | return -EIO; | |
124 | ||
125 | /* Basic alarms only support hour, minute, and seconds fields. | |
126 | * Some also support day and month, for alarms up to a year in | |
127 | * the future. | |
128 | */ | |
129 | t->time.tm_mday = -1; | |
130 | t->time.tm_mon = -1; | |
131 | ||
132 | spin_lock_irq(&rtc_lock); | |
133 | t->time.tm_sec = CMOS_READ(RTC_SECONDS_ALARM); | |
134 | t->time.tm_min = CMOS_READ(RTC_MINUTES_ALARM); | |
135 | t->time.tm_hour = CMOS_READ(RTC_HOURS_ALARM); | |
136 | ||
137 | if (cmos->day_alrm) { | |
615bb29c ML |
138 | /* ignore upper bits on readback per ACPI spec */ |
139 | t->time.tm_mday = CMOS_READ(cmos->day_alrm) & 0x3f; | |
7be2c7c9 DB |
140 | if (!t->time.tm_mday) |
141 | t->time.tm_mday = -1; | |
142 | ||
143 | if (cmos->mon_alrm) { | |
144 | t->time.tm_mon = CMOS_READ(cmos->mon_alrm); | |
145 | if (!t->time.tm_mon) | |
146 | t->time.tm_mon = -1; | |
147 | } | |
148 | } | |
149 | ||
150 | rtc_control = CMOS_READ(RTC_CONTROL); | |
151 | spin_unlock_irq(&rtc_lock); | |
152 | ||
153 | /* REVISIT this assumes PC style usage: always BCD */ | |
154 | ||
155 | if (((unsigned)t->time.tm_sec) < 0x60) | |
156 | t->time.tm_sec = BCD2BIN(t->time.tm_sec); | |
157 | else | |
158 | t->time.tm_sec = -1; | |
159 | if (((unsigned)t->time.tm_min) < 0x60) | |
160 | t->time.tm_min = BCD2BIN(t->time.tm_min); | |
161 | else | |
162 | t->time.tm_min = -1; | |
163 | if (((unsigned)t->time.tm_hour) < 0x24) | |
164 | t->time.tm_hour = BCD2BIN(t->time.tm_hour); | |
165 | else | |
166 | t->time.tm_hour = -1; | |
167 | ||
168 | if (cmos->day_alrm) { | |
169 | if (((unsigned)t->time.tm_mday) <= 0x31) | |
170 | t->time.tm_mday = BCD2BIN(t->time.tm_mday); | |
171 | else | |
172 | t->time.tm_mday = -1; | |
173 | if (cmos->mon_alrm) { | |
174 | if (((unsigned)t->time.tm_mon) <= 0x12) | |
175 | t->time.tm_mon = BCD2BIN(t->time.tm_mon) - 1; | |
176 | else | |
177 | t->time.tm_mon = -1; | |
178 | } | |
179 | } | |
180 | t->time.tm_year = -1; | |
181 | ||
182 | t->enabled = !!(rtc_control & RTC_AIE); | |
183 | t->pending = 0; | |
184 | ||
185 | return 0; | |
186 | } | |
187 | ||
188 | static int cmos_set_alarm(struct device *dev, struct rtc_wkalrm *t) | |
189 | { | |
190 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
191 | unsigned char mon, mday, hrs, min, sec; | |
192 | unsigned char rtc_control, rtc_intr; | |
193 | ||
194 | if (!is_valid_irq(cmos->irq)) | |
195 | return -EIO; | |
196 | ||
197 | /* REVISIT this assumes PC style usage: always BCD */ | |
198 | ||
199 | /* Writing 0xff means "don't care" or "match all". */ | |
200 | ||
2b653e06 ZY |
201 | mon = t->time.tm_mon + 1; |
202 | mon = (mon <= 12) ? BIN2BCD(mon) : 0xff; | |
7be2c7c9 DB |
203 | |
204 | mday = t->time.tm_mday; | |
205 | mday = (mday >= 1 && mday <= 31) ? BIN2BCD(mday) : 0xff; | |
206 | ||
207 | hrs = t->time.tm_hour; | |
208 | hrs = (hrs < 24) ? BIN2BCD(hrs) : 0xff; | |
209 | ||
210 | min = t->time.tm_min; | |
211 | min = (min < 60) ? BIN2BCD(min) : 0xff; | |
212 | ||
213 | sec = t->time.tm_sec; | |
214 | sec = (sec < 60) ? BIN2BCD(sec) : 0xff; | |
215 | ||
9d8af78b | 216 | hpet_set_alarm_time(t->time.tm_hour, t->time.tm_min, t->time.tm_sec); |
7be2c7c9 DB |
217 | spin_lock_irq(&rtc_lock); |
218 | ||
219 | /* next rtc irq must not be from previous alarm setting */ | |
220 | rtc_control = CMOS_READ(RTC_CONTROL); | |
221 | rtc_control &= ~RTC_AIE; | |
222 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
223 | rtc_intr = CMOS_READ(RTC_INTR_FLAGS); | |
bcd9b89c DB |
224 | rtc_intr &= (rtc_control & RTC_IRQMASK) | RTC_IRQF; |
225 | if (is_intr(rtc_intr)) | |
ab6a2d70 | 226 | rtc_update_irq(cmos->rtc, 1, rtc_intr); |
7be2c7c9 DB |
227 | |
228 | /* update alarm */ | |
229 | CMOS_WRITE(hrs, RTC_HOURS_ALARM); | |
230 | CMOS_WRITE(min, RTC_MINUTES_ALARM); | |
231 | CMOS_WRITE(sec, RTC_SECONDS_ALARM); | |
232 | ||
233 | /* the system may support an "enhanced" alarm */ | |
234 | if (cmos->day_alrm) { | |
235 | CMOS_WRITE(mday, cmos->day_alrm); | |
236 | if (cmos->mon_alrm) | |
237 | CMOS_WRITE(mon, cmos->mon_alrm); | |
238 | } | |
239 | ||
240 | if (t->enabled) { | |
241 | rtc_control |= RTC_AIE; | |
242 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
243 | rtc_intr = CMOS_READ(RTC_INTR_FLAGS); | |
bcd9b89c DB |
244 | rtc_intr &= (rtc_control & RTC_IRQMASK) | RTC_IRQF; |
245 | if (is_intr(rtc_intr)) | |
ab6a2d70 | 246 | rtc_update_irq(cmos->rtc, 1, rtc_intr); |
7be2c7c9 DB |
247 | } |
248 | ||
249 | spin_unlock_irq(&rtc_lock); | |
250 | ||
251 | return 0; | |
252 | } | |
253 | ||
57deb526 | 254 | static int cmos_irq_set_freq(struct device *dev, int freq) |
7be2c7c9 DB |
255 | { |
256 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
257 | int f; | |
258 | unsigned long flags; | |
259 | ||
260 | if (!is_valid_irq(cmos->irq)) | |
261 | return -ENXIO; | |
262 | ||
263 | /* 0 = no irqs; 1 = 2^15 Hz ... 15 = 2^0 Hz */ | |
264 | f = ffs(freq); | |
97144c67 DB |
265 | if (f-- > 16) |
266 | return -EINVAL; | |
267 | f = 16 - f; | |
7be2c7c9 DB |
268 | |
269 | spin_lock_irqsave(&rtc_lock, flags); | |
9d8af78b BW |
270 | if (!hpet_set_periodic_freq(freq)) |
271 | CMOS_WRITE(RTC_REF_CLCK_32KHZ | f, RTC_FREQ_SELECT); | |
7be2c7c9 DB |
272 | spin_unlock_irqrestore(&rtc_lock, flags); |
273 | ||
274 | return 0; | |
275 | } | |
276 | ||
57deb526 AZ |
277 | static int cmos_irq_set_state(struct device *dev, int enabled) |
278 | { | |
279 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
280 | unsigned char rtc_control, rtc_intr; | |
281 | unsigned long flags; | |
282 | ||
283 | if (!is_valid_irq(cmos->irq)) | |
284 | return -ENXIO; | |
285 | ||
286 | spin_lock_irqsave(&rtc_lock, flags); | |
287 | rtc_control = CMOS_READ(RTC_CONTROL); | |
288 | ||
289 | if (enabled) | |
290 | rtc_control |= RTC_PIE; | |
291 | else | |
292 | rtc_control &= ~RTC_PIE; | |
293 | ||
294 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
295 | ||
296 | rtc_intr = CMOS_READ(RTC_INTR_FLAGS); | |
297 | rtc_intr &= (rtc_control & RTC_IRQMASK) | RTC_IRQF; | |
298 | if (is_intr(rtc_intr)) | |
299 | rtc_update_irq(cmos->rtc, 1, rtc_intr); | |
300 | ||
301 | spin_unlock_irqrestore(&rtc_lock, flags); | |
302 | return 0; | |
303 | } | |
304 | ||
7be2c7c9 DB |
305 | #if defined(CONFIG_RTC_INTF_DEV) || defined(CONFIG_RTC_INTF_DEV_MODULE) |
306 | ||
307 | static int | |
308 | cmos_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) | |
309 | { | |
310 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
311 | unsigned char rtc_control, rtc_intr; | |
312 | unsigned long flags; | |
313 | ||
314 | switch (cmd) { | |
315 | case RTC_AIE_OFF: | |
316 | case RTC_AIE_ON: | |
317 | case RTC_UIE_OFF: | |
318 | case RTC_UIE_ON: | |
319 | case RTC_PIE_OFF: | |
320 | case RTC_PIE_ON: | |
321 | if (!is_valid_irq(cmos->irq)) | |
322 | return -EINVAL; | |
323 | break; | |
324 | default: | |
325 | return -ENOIOCTLCMD; | |
326 | } | |
327 | ||
328 | spin_lock_irqsave(&rtc_lock, flags); | |
329 | rtc_control = CMOS_READ(RTC_CONTROL); | |
330 | switch (cmd) { | |
331 | case RTC_AIE_OFF: /* alarm off */ | |
332 | rtc_control &= ~RTC_AIE; | |
9d8af78b | 333 | hpet_mask_rtc_irq_bit(RTC_AIE); |
7be2c7c9 DB |
334 | break; |
335 | case RTC_AIE_ON: /* alarm on */ | |
336 | rtc_control |= RTC_AIE; | |
9d8af78b | 337 | hpet_set_rtc_irq_bit(RTC_AIE); |
7be2c7c9 DB |
338 | break; |
339 | case RTC_UIE_OFF: /* update off */ | |
340 | rtc_control &= ~RTC_UIE; | |
9d8af78b | 341 | hpet_mask_rtc_irq_bit(RTC_UIE); |
7be2c7c9 DB |
342 | break; |
343 | case RTC_UIE_ON: /* update on */ | |
344 | rtc_control |= RTC_UIE; | |
9d8af78b | 345 | hpet_set_rtc_irq_bit(RTC_UIE); |
7be2c7c9 DB |
346 | break; |
347 | case RTC_PIE_OFF: /* periodic off */ | |
348 | rtc_control &= ~RTC_PIE; | |
9d8af78b | 349 | hpet_mask_rtc_irq_bit(RTC_PIE); |
7be2c7c9 DB |
350 | break; |
351 | case RTC_PIE_ON: /* periodic on */ | |
352 | rtc_control |= RTC_PIE; | |
9d8af78b | 353 | hpet_set_rtc_irq_bit(RTC_PIE); |
7be2c7c9 DB |
354 | break; |
355 | } | |
9d8af78b BW |
356 | if (!is_hpet_enabled()) |
357 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
358 | ||
7be2c7c9 | 359 | rtc_intr = CMOS_READ(RTC_INTR_FLAGS); |
bcd9b89c DB |
360 | rtc_intr &= (rtc_control & RTC_IRQMASK) | RTC_IRQF; |
361 | if (is_intr(rtc_intr)) | |
ab6a2d70 | 362 | rtc_update_irq(cmos->rtc, 1, rtc_intr); |
9d8af78b | 363 | |
7be2c7c9 DB |
364 | spin_unlock_irqrestore(&rtc_lock, flags); |
365 | return 0; | |
366 | } | |
367 | ||
368 | #else | |
369 | #define cmos_rtc_ioctl NULL | |
370 | #endif | |
371 | ||
372 | #if defined(CONFIG_RTC_INTF_PROC) || defined(CONFIG_RTC_INTF_PROC_MODULE) | |
373 | ||
374 | static int cmos_procfs(struct device *dev, struct seq_file *seq) | |
375 | { | |
376 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
377 | unsigned char rtc_control, valid; | |
378 | ||
379 | spin_lock_irq(&rtc_lock); | |
380 | rtc_control = CMOS_READ(RTC_CONTROL); | |
381 | valid = CMOS_READ(RTC_VALID); | |
382 | spin_unlock_irq(&rtc_lock); | |
383 | ||
384 | /* NOTE: at least ICH6 reports battery status using a different | |
385 | * (non-RTC) bit; and SQWE is ignored on many current systems. | |
386 | */ | |
387 | return seq_printf(seq, | |
388 | "periodic_IRQ\t: %s\n" | |
389 | "update_IRQ\t: %s\n" | |
c8626a1d | 390 | "HPET_emulated\t: %s\n" |
7be2c7c9 DB |
391 | // "square_wave\t: %s\n" |
392 | // "BCD\t\t: %s\n" | |
393 | "DST_enable\t: %s\n" | |
394 | "periodic_freq\t: %d\n" | |
395 | "batt_status\t: %s\n", | |
396 | (rtc_control & RTC_PIE) ? "yes" : "no", | |
397 | (rtc_control & RTC_UIE) ? "yes" : "no", | |
c8626a1d | 398 | is_hpet_enabled() ? "yes" : "no", |
7be2c7c9 DB |
399 | // (rtc_control & RTC_SQWE) ? "yes" : "no", |
400 | // (rtc_control & RTC_DM_BINARY) ? "no" : "yes", | |
401 | (rtc_control & RTC_DST_EN) ? "yes" : "no", | |
402 | cmos->rtc->irq_freq, | |
403 | (valid & RTC_VRT) ? "okay" : "dead"); | |
404 | } | |
405 | ||
406 | #else | |
407 | #define cmos_procfs NULL | |
408 | #endif | |
409 | ||
410 | static const struct rtc_class_ops cmos_rtc_ops = { | |
411 | .ioctl = cmos_rtc_ioctl, | |
412 | .read_time = cmos_read_time, | |
413 | .set_time = cmos_set_time, | |
414 | .read_alarm = cmos_read_alarm, | |
415 | .set_alarm = cmos_set_alarm, | |
416 | .proc = cmos_procfs, | |
57deb526 AZ |
417 | .irq_set_freq = cmos_irq_set_freq, |
418 | .irq_set_state = cmos_irq_set_state, | |
7be2c7c9 DB |
419 | }; |
420 | ||
421 | /*----------------------------------------------------------------*/ | |
422 | ||
e07e232c DB |
423 | /* |
424 | * All these chips have at least 64 bytes of address space, shared by | |
425 | * RTC registers and NVRAM. Most of those bytes of NVRAM are used | |
426 | * by boot firmware. Modern chips have 128 or 256 bytes. | |
427 | */ | |
428 | ||
429 | #define NVRAM_OFFSET (RTC_REG_D + 1) | |
430 | ||
431 | static ssize_t | |
432 | cmos_nvram_read(struct kobject *kobj, struct bin_attribute *attr, | |
433 | char *buf, loff_t off, size_t count) | |
434 | { | |
435 | int retval; | |
436 | ||
437 | if (unlikely(off >= attr->size)) | |
438 | return 0; | |
439 | if ((off + count) > attr->size) | |
440 | count = attr->size - off; | |
441 | ||
442 | spin_lock_irq(&rtc_lock); | |
443 | for (retval = 0, off += NVRAM_OFFSET; count--; retval++, off++) | |
444 | *buf++ = CMOS_READ(off); | |
445 | spin_unlock_irq(&rtc_lock); | |
446 | ||
447 | return retval; | |
448 | } | |
449 | ||
450 | static ssize_t | |
451 | cmos_nvram_write(struct kobject *kobj, struct bin_attribute *attr, | |
452 | char *buf, loff_t off, size_t count) | |
453 | { | |
454 | struct cmos_rtc *cmos; | |
455 | int retval; | |
456 | ||
457 | cmos = dev_get_drvdata(container_of(kobj, struct device, kobj)); | |
458 | if (unlikely(off >= attr->size)) | |
459 | return -EFBIG; | |
460 | if ((off + count) > attr->size) | |
461 | count = attr->size - off; | |
462 | ||
463 | /* NOTE: on at least PCs and Ataris, the boot firmware uses a | |
464 | * checksum on part of the NVRAM data. That's currently ignored | |
465 | * here. If userspace is smart enough to know what fields of | |
466 | * NVRAM to update, updating checksums is also part of its job. | |
467 | */ | |
468 | spin_lock_irq(&rtc_lock); | |
469 | for (retval = 0, off += NVRAM_OFFSET; count--; retval++, off++) { | |
470 | /* don't trash RTC registers */ | |
471 | if (off == cmos->day_alrm | |
472 | || off == cmos->mon_alrm | |
473 | || off == cmos->century) | |
474 | buf++; | |
475 | else | |
476 | CMOS_WRITE(*buf++, off); | |
477 | } | |
478 | spin_unlock_irq(&rtc_lock); | |
479 | ||
480 | return retval; | |
481 | } | |
482 | ||
483 | static struct bin_attribute nvram = { | |
484 | .attr = { | |
485 | .name = "nvram", | |
486 | .mode = S_IRUGO | S_IWUSR, | |
487 | .owner = THIS_MODULE, | |
488 | }, | |
489 | ||
490 | .read = cmos_nvram_read, | |
491 | .write = cmos_nvram_write, | |
492 | /* size gets set up later */ | |
493 | }; | |
494 | ||
495 | /*----------------------------------------------------------------*/ | |
496 | ||
7be2c7c9 DB |
497 | static struct cmos_rtc cmos_rtc; |
498 | ||
499 | static irqreturn_t cmos_interrupt(int irq, void *p) | |
500 | { | |
501 | u8 irqstat; | |
8a0bdfd7 | 502 | u8 rtc_control; |
7be2c7c9 DB |
503 | |
504 | spin_lock(&rtc_lock); | |
9d8af78b BW |
505 | /* |
506 | * In this case it is HPET RTC interrupt handler | |
507 | * calling us, with the interrupt information | |
508 | * passed as arg1, instead of irq. | |
509 | */ | |
510 | if (is_hpet_enabled()) | |
511 | irqstat = (unsigned long)irq & 0xF0; | |
512 | else { | |
513 | irqstat = CMOS_READ(RTC_INTR_FLAGS); | |
514 | rtc_control = CMOS_READ(RTC_CONTROL); | |
515 | irqstat &= (rtc_control & RTC_IRQMASK) | RTC_IRQF; | |
516 | } | |
8a0bdfd7 DB |
517 | |
518 | /* All Linux RTC alarms should be treated as if they were oneshot. | |
519 | * Similar code may be needed in system wakeup paths, in case the | |
520 | * alarm woke the system. | |
521 | */ | |
522 | if (irqstat & RTC_AIE) { | |
9d8af78b | 523 | rtc_control = CMOS_READ(RTC_CONTROL); |
8a0bdfd7 DB |
524 | rtc_control &= ~RTC_AIE; |
525 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
526 | CMOS_READ(RTC_INTR_FLAGS); | |
527 | } | |
7be2c7c9 DB |
528 | spin_unlock(&rtc_lock); |
529 | ||
bcd9b89c | 530 | if (is_intr(irqstat)) { |
7be2c7c9 DB |
531 | rtc_update_irq(p, 1, irqstat); |
532 | return IRQ_HANDLED; | |
533 | } else | |
534 | return IRQ_NONE; | |
535 | } | |
536 | ||
41ac8df9 | 537 | #ifdef CONFIG_PNP |
7be2c7c9 DB |
538 | #define INITSECTION |
539 | ||
540 | #else | |
7be2c7c9 DB |
541 | #define INITSECTION __init |
542 | #endif | |
543 | ||
544 | static int INITSECTION | |
545 | cmos_do_probe(struct device *dev, struct resource *ports, int rtc_irq) | |
546 | { | |
547 | struct cmos_rtc_board_info *info = dev->platform_data; | |
548 | int retval = 0; | |
549 | unsigned char rtc_control; | |
e07e232c | 550 | unsigned address_space; |
7be2c7c9 DB |
551 | |
552 | /* there can be only one ... */ | |
553 | if (cmos_rtc.dev) | |
554 | return -EBUSY; | |
555 | ||
556 | if (!ports) | |
557 | return -ENODEV; | |
558 | ||
05440dfc DB |
559 | /* Claim I/O ports ASAP, minimizing conflict with legacy driver. |
560 | * | |
561 | * REVISIT non-x86 systems may instead use memory space resources | |
562 | * (needing ioremap etc), not i/o space resources like this ... | |
563 | */ | |
564 | ports = request_region(ports->start, | |
565 | ports->end + 1 - ports->start, | |
566 | driver_name); | |
567 | if (!ports) { | |
568 | dev_dbg(dev, "i/o registers already in use\n"); | |
569 | return -EBUSY; | |
570 | } | |
571 | ||
7be2c7c9 DB |
572 | cmos_rtc.irq = rtc_irq; |
573 | cmos_rtc.iomem = ports; | |
574 | ||
e07e232c DB |
575 | /* Heuristic to deduce NVRAM size ... do what the legacy NVRAM |
576 | * driver did, but don't reject unknown configs. Old hardware | |
577 | * won't address 128 bytes, and for now we ignore the way newer | |
578 | * chips can address 256 bytes (using two more i/o ports). | |
579 | */ | |
580 | #if defined(CONFIG_ATARI) | |
581 | address_space = 64; | |
582 | #elif defined(__i386__) || defined(__x86_64__) || defined(__arm__) | |
583 | address_space = 128; | |
584 | #else | |
585 | #warning Assuming 128 bytes of RTC+NVRAM address space, not 64 bytes. | |
586 | address_space = 128; | |
587 | #endif | |
588 | ||
87ac84f4 DB |
589 | /* For ACPI systems extension info comes from the FADT. On others, |
590 | * board specific setup provides it as appropriate. Systems where | |
591 | * the alarm IRQ isn't automatically a wakeup IRQ (like ACPI, and | |
592 | * some almost-clones) can provide hooks to make that behave. | |
e07e232c DB |
593 | * |
594 | * Note that ACPI doesn't preclude putting these registers into | |
595 | * "extended" areas of the chip, including some that we won't yet | |
596 | * expect CMOS_READ and friends to handle. | |
7be2c7c9 DB |
597 | */ |
598 | if (info) { | |
e07e232c DB |
599 | if (info->rtc_day_alarm && info->rtc_day_alarm < 128) |
600 | cmos_rtc.day_alrm = info->rtc_day_alarm; | |
601 | if (info->rtc_mon_alarm && info->rtc_mon_alarm < 128) | |
602 | cmos_rtc.mon_alrm = info->rtc_mon_alarm; | |
603 | if (info->rtc_century && info->rtc_century < 128) | |
604 | cmos_rtc.century = info->rtc_century; | |
87ac84f4 DB |
605 | |
606 | if (info->wake_on && info->wake_off) { | |
607 | cmos_rtc.wake_on = info->wake_on; | |
608 | cmos_rtc.wake_off = info->wake_off; | |
609 | } | |
7be2c7c9 DB |
610 | } |
611 | ||
612 | cmos_rtc.rtc = rtc_device_register(driver_name, dev, | |
613 | &cmos_rtc_ops, THIS_MODULE); | |
05440dfc DB |
614 | if (IS_ERR(cmos_rtc.rtc)) { |
615 | retval = PTR_ERR(cmos_rtc.rtc); | |
616 | goto cleanup0; | |
617 | } | |
7be2c7c9 DB |
618 | |
619 | cmos_rtc.dev = dev; | |
620 | dev_set_drvdata(dev, &cmos_rtc); | |
cd966209 | 621 | rename_region(ports, cmos_rtc.rtc->dev.bus_id); |
7be2c7c9 DB |
622 | |
623 | spin_lock_irq(&rtc_lock); | |
624 | ||
625 | /* force periodic irq to CMOS reset default of 1024Hz; | |
626 | * | |
627 | * REVISIT it's been reported that at least one x86_64 ALI mobo | |
628 | * doesn't use 32KHz here ... for portability we might need to | |
629 | * do something about other clock frequencies. | |
630 | */ | |
7be2c7c9 | 631 | cmos_rtc.rtc->irq_freq = 1024; |
9d8af78b BW |
632 | if (!hpet_set_periodic_freq(cmos_rtc.rtc->irq_freq)) |
633 | CMOS_WRITE(RTC_REF_CLCK_32KHZ | 0x06, RTC_FREQ_SELECT); | |
7be2c7c9 DB |
634 | |
635 | /* disable irqs. | |
636 | * | |
637 | * NOTE after changing RTC_xIE bits we always read INTR_FLAGS; | |
638 | * allegedly some older rtcs need that to handle irqs properly | |
639 | */ | |
640 | rtc_control = CMOS_READ(RTC_CONTROL); | |
641 | rtc_control &= ~(RTC_PIE | RTC_AIE | RTC_UIE); | |
642 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
643 | CMOS_READ(RTC_INTR_FLAGS); | |
644 | ||
645 | spin_unlock_irq(&rtc_lock); | |
646 | ||
647 | /* FIXME teach the alarm code how to handle binary mode; | |
648 | * <asm-generic/rtc.h> doesn't know 12-hour mode either. | |
649 | */ | |
650 | if (!(rtc_control & RTC_24H) || (rtc_control & (RTC_DM_BINARY))) { | |
651 | dev_dbg(dev, "only 24-hr BCD mode supported\n"); | |
652 | retval = -ENXIO; | |
653 | goto cleanup1; | |
654 | } | |
655 | ||
9d8af78b BW |
656 | if (is_valid_irq(rtc_irq)) { |
657 | irq_handler_t rtc_cmos_int_handler; | |
658 | ||
659 | if (is_hpet_enabled()) { | |
660 | int err; | |
661 | ||
662 | rtc_cmos_int_handler = hpet_rtc_interrupt; | |
663 | err = hpet_register_irq_handler(cmos_interrupt); | |
664 | if (err != 0) { | |
665 | printk(KERN_WARNING "hpet_register_irq_handler " | |
666 | " failed in rtc_init()."); | |
667 | goto cleanup1; | |
668 | } | |
669 | } else | |
670 | rtc_cmos_int_handler = cmos_interrupt; | |
671 | ||
672 | retval = request_irq(rtc_irq, rtc_cmos_int_handler, | |
673 | IRQF_DISABLED, cmos_rtc.rtc->dev.bus_id, | |
ab6a2d70 | 674 | cmos_rtc.rtc); |
9d8af78b BW |
675 | if (retval < 0) { |
676 | dev_dbg(dev, "IRQ %d is already in use\n", rtc_irq); | |
677 | goto cleanup1; | |
678 | } | |
7be2c7c9 | 679 | } |
9d8af78b | 680 | hpet_rtc_timer_init(); |
7be2c7c9 | 681 | |
e07e232c DB |
682 | /* export at least the first block of NVRAM */ |
683 | nvram.size = address_space - NVRAM_OFFSET; | |
684 | retval = sysfs_create_bin_file(&dev->kobj, &nvram); | |
685 | if (retval < 0) { | |
686 | dev_dbg(dev, "can't create nvram file? %d\n", retval); | |
687 | goto cleanup2; | |
688 | } | |
7be2c7c9 DB |
689 | |
690 | pr_info("%s: alarms up to one %s%s\n", | |
cd966209 | 691 | cmos_rtc.rtc->dev.bus_id, |
7be2c7c9 DB |
692 | is_valid_irq(rtc_irq) |
693 | ? (cmos_rtc.mon_alrm | |
694 | ? "year" | |
695 | : (cmos_rtc.day_alrm | |
696 | ? "month" : "day")) | |
697 | : "no", | |
698 | cmos_rtc.century ? ", y3k" : "" | |
699 | ); | |
700 | ||
701 | return 0; | |
702 | ||
e07e232c DB |
703 | cleanup2: |
704 | if (is_valid_irq(rtc_irq)) | |
705 | free_irq(rtc_irq, cmos_rtc.rtc); | |
7be2c7c9 | 706 | cleanup1: |
05440dfc | 707 | cmos_rtc.dev = NULL; |
7be2c7c9 | 708 | rtc_device_unregister(cmos_rtc.rtc); |
05440dfc DB |
709 | cleanup0: |
710 | release_region(ports->start, ports->end + 1 - ports->start); | |
7be2c7c9 DB |
711 | return retval; |
712 | } | |
713 | ||
714 | static void cmos_do_shutdown(void) | |
715 | { | |
716 | unsigned char rtc_control; | |
717 | ||
718 | spin_lock_irq(&rtc_lock); | |
719 | rtc_control = CMOS_READ(RTC_CONTROL); | |
720 | rtc_control &= ~(RTC_PIE|RTC_AIE|RTC_UIE); | |
721 | CMOS_WRITE(rtc_control, RTC_CONTROL); | |
722 | CMOS_READ(RTC_INTR_FLAGS); | |
723 | spin_unlock_irq(&rtc_lock); | |
724 | } | |
725 | ||
726 | static void __exit cmos_do_remove(struct device *dev) | |
727 | { | |
728 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
05440dfc | 729 | struct resource *ports; |
7be2c7c9 DB |
730 | |
731 | cmos_do_shutdown(); | |
732 | ||
e07e232c DB |
733 | sysfs_remove_bin_file(&dev->kobj, &nvram); |
734 | ||
9d8af78b | 735 | if (is_valid_irq(cmos->irq)) { |
05440dfc | 736 | free_irq(cmos->irq, cmos->rtc); |
9d8af78b BW |
737 | hpet_unregister_irq_handler(cmos_interrupt); |
738 | } | |
7be2c7c9 | 739 | |
05440dfc DB |
740 | rtc_device_unregister(cmos->rtc); |
741 | cmos->rtc = NULL; | |
7be2c7c9 | 742 | |
05440dfc DB |
743 | ports = cmos->iomem; |
744 | release_region(ports->start, ports->end + 1 - ports->start); | |
745 | cmos->iomem = NULL; | |
746 | ||
747 | cmos->dev = NULL; | |
7be2c7c9 DB |
748 | dev_set_drvdata(dev, NULL); |
749 | } | |
750 | ||
751 | #ifdef CONFIG_PM | |
752 | ||
753 | static int cmos_suspend(struct device *dev, pm_message_t mesg) | |
754 | { | |
755 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
756 | int do_wake = device_may_wakeup(dev); | |
bcd9b89c | 757 | unsigned char tmp; |
7be2c7c9 DB |
758 | |
759 | /* only the alarm might be a wakeup event source */ | |
760 | spin_lock_irq(&rtc_lock); | |
761 | cmos->suspend_ctrl = tmp = CMOS_READ(RTC_CONTROL); | |
762 | if (tmp & (RTC_PIE|RTC_AIE|RTC_UIE)) { | |
bcd9b89c DB |
763 | unsigned char irqstat; |
764 | ||
7be2c7c9 DB |
765 | if (do_wake) |
766 | tmp &= ~(RTC_PIE|RTC_UIE); | |
767 | else | |
768 | tmp &= ~(RTC_PIE|RTC_AIE|RTC_UIE); | |
769 | CMOS_WRITE(tmp, RTC_CONTROL); | |
770 | irqstat = CMOS_READ(RTC_INTR_FLAGS); | |
bcd9b89c DB |
771 | irqstat &= (tmp & RTC_IRQMASK) | RTC_IRQF; |
772 | if (is_intr(irqstat)) | |
ab6a2d70 | 773 | rtc_update_irq(cmos->rtc, 1, irqstat); |
bcd9b89c | 774 | } |
7be2c7c9 DB |
775 | spin_unlock_irq(&rtc_lock); |
776 | ||
87ac84f4 DB |
777 | if (tmp & RTC_AIE) { |
778 | cmos->enabled_wake = 1; | |
779 | if (cmos->wake_on) | |
780 | cmos->wake_on(dev); | |
781 | else | |
782 | enable_irq_wake(cmos->irq); | |
783 | } | |
7be2c7c9 DB |
784 | |
785 | pr_debug("%s: suspend%s, ctrl %02x\n", | |
cd966209 | 786 | cmos_rtc.rtc->dev.bus_id, |
7be2c7c9 DB |
787 | (tmp & RTC_AIE) ? ", alarm may wake" : "", |
788 | tmp); | |
789 | ||
790 | return 0; | |
791 | } | |
792 | ||
793 | static int cmos_resume(struct device *dev) | |
794 | { | |
795 | struct cmos_rtc *cmos = dev_get_drvdata(dev); | |
796 | unsigned char tmp = cmos->suspend_ctrl; | |
797 | ||
7be2c7c9 DB |
798 | /* re-enable any irqs previously active */ |
799 | if (tmp & (RTC_PIE|RTC_AIE|RTC_UIE)) { | |
800 | ||
87ac84f4 DB |
801 | if (cmos->enabled_wake) { |
802 | if (cmos->wake_off) | |
803 | cmos->wake_off(dev); | |
804 | else | |
805 | disable_irq_wake(cmos->irq); | |
806 | cmos->enabled_wake = 0; | |
807 | } | |
7be2c7c9 DB |
808 | |
809 | spin_lock_irq(&rtc_lock); | |
810 | CMOS_WRITE(tmp, RTC_CONTROL); | |
811 | tmp = CMOS_READ(RTC_INTR_FLAGS); | |
bcd9b89c DB |
812 | tmp &= (cmos->suspend_ctrl & RTC_IRQMASK) | RTC_IRQF; |
813 | if (is_intr(tmp)) | |
ab6a2d70 | 814 | rtc_update_irq(cmos->rtc, 1, tmp); |
bcd9b89c | 815 | spin_unlock_irq(&rtc_lock); |
7be2c7c9 DB |
816 | } |
817 | ||
818 | pr_debug("%s: resume, ctrl %02x\n", | |
cd966209 | 819 | cmos_rtc.rtc->dev.bus_id, |
7be2c7c9 DB |
820 | cmos->suspend_ctrl); |
821 | ||
822 | ||
823 | return 0; | |
824 | } | |
825 | ||
826 | #else | |
827 | #define cmos_suspend NULL | |
828 | #define cmos_resume NULL | |
829 | #endif | |
830 | ||
831 | /*----------------------------------------------------------------*/ | |
832 | ||
e07e232c DB |
833 | /* On non-x86 systems, a "CMOS" RTC lives most naturally on platform_bus. |
834 | * ACPI systems always list these as PNPACPI devices, and pre-ACPI PCs | |
835 | * probably list them in similar PNPBIOS tables; so PNP is more common. | |
836 | * | |
837 | * We don't use legacy "poke at the hardware" probing. Ancient PCs that | |
838 | * predate even PNPBIOS should set up platform_bus devices. | |
7be2c7c9 DB |
839 | */ |
840 | ||
41ac8df9 | 841 | #ifdef CONFIG_PNP |
7be2c7c9 DB |
842 | |
843 | #include <linux/pnp.h> | |
844 | ||
845 | static int __devinit | |
846 | cmos_pnp_probe(struct pnp_dev *pnp, const struct pnp_device_id *id) | |
847 | { | |
848 | /* REVISIT paranoia argues for a shutdown notifier, since PNP | |
849 | * drivers can't provide shutdown() methods to disable IRQs. | |
850 | * Or better yet, fix PNP to allow those methods... | |
851 | */ | |
6cd8fa87 MG |
852 | if (pnp_port_start(pnp,0) == 0x70 && !pnp_irq_valid(pnp,0)) |
853 | /* Some machines contain a PNP entry for the RTC, but | |
854 | * don't define the IRQ. It should always be safe to | |
855 | * hardcode it in these cases | |
856 | */ | |
857 | return cmos_do_probe(&pnp->dev, &pnp->res.port_resource[0], 8); | |
858 | else | |
859 | return cmos_do_probe(&pnp->dev, | |
860 | &pnp->res.port_resource[0], | |
861 | pnp->res.irq_resource[0].start); | |
7be2c7c9 DB |
862 | } |
863 | ||
864 | static void __exit cmos_pnp_remove(struct pnp_dev *pnp) | |
865 | { | |
866 | cmos_do_remove(&pnp->dev); | |
867 | } | |
868 | ||
869 | #ifdef CONFIG_PM | |
870 | ||
871 | static int cmos_pnp_suspend(struct pnp_dev *pnp, pm_message_t mesg) | |
872 | { | |
873 | return cmos_suspend(&pnp->dev, mesg); | |
874 | } | |
875 | ||
876 | static int cmos_pnp_resume(struct pnp_dev *pnp) | |
877 | { | |
878 | return cmos_resume(&pnp->dev); | |
879 | } | |
880 | ||
881 | #else | |
882 | #define cmos_pnp_suspend NULL | |
883 | #define cmos_pnp_resume NULL | |
884 | #endif | |
885 | ||
886 | ||
887 | static const struct pnp_device_id rtc_ids[] = { | |
888 | { .id = "PNP0b00", }, | |
889 | { .id = "PNP0b01", }, | |
890 | { .id = "PNP0b02", }, | |
891 | { }, | |
892 | }; | |
893 | MODULE_DEVICE_TABLE(pnp, rtc_ids); | |
894 | ||
895 | static struct pnp_driver cmos_pnp_driver = { | |
896 | .name = (char *) driver_name, | |
897 | .id_table = rtc_ids, | |
898 | .probe = cmos_pnp_probe, | |
899 | .remove = __exit_p(cmos_pnp_remove), | |
900 | ||
901 | /* flag ensures resume() gets called, and stops syslog spam */ | |
902 | .flags = PNP_DRIVER_RES_DO_NOT_CHANGE, | |
903 | .suspend = cmos_pnp_suspend, | |
904 | .resume = cmos_pnp_resume, | |
905 | }; | |
906 | ||
907 | static int __init cmos_init(void) | |
908 | { | |
909 | return pnp_register_driver(&cmos_pnp_driver); | |
910 | } | |
911 | module_init(cmos_init); | |
912 | ||
913 | static void __exit cmos_exit(void) | |
914 | { | |
915 | pnp_unregister_driver(&cmos_pnp_driver); | |
916 | } | |
917 | module_exit(cmos_exit); | |
918 | ||
41ac8df9 | 919 | #else /* no PNP */ |
7be2c7c9 DB |
920 | |
921 | /*----------------------------------------------------------------*/ | |
922 | ||
41ac8df9 | 923 | /* Platform setup should have set up an RTC device, when PNP is |
bcd9b89c | 924 | * unavailable ... this could happen even on (older) PCs. |
7be2c7c9 DB |
925 | */ |
926 | ||
927 | static int __init cmos_platform_probe(struct platform_device *pdev) | |
928 | { | |
929 | return cmos_do_probe(&pdev->dev, | |
930 | platform_get_resource(pdev, IORESOURCE_IO, 0), | |
931 | platform_get_irq(pdev, 0)); | |
932 | } | |
933 | ||
934 | static int __exit cmos_platform_remove(struct platform_device *pdev) | |
935 | { | |
936 | cmos_do_remove(&pdev->dev); | |
937 | return 0; | |
938 | } | |
939 | ||
940 | static void cmos_platform_shutdown(struct platform_device *pdev) | |
941 | { | |
942 | cmos_do_shutdown(); | |
943 | } | |
944 | ||
ad28a07b KS |
945 | /* work with hotplug and coldplug */ |
946 | MODULE_ALIAS("platform:rtc_cmos"); | |
947 | ||
7be2c7c9 DB |
948 | static struct platform_driver cmos_platform_driver = { |
949 | .remove = __exit_p(cmos_platform_remove), | |
950 | .shutdown = cmos_platform_shutdown, | |
951 | .driver = { | |
952 | .name = (char *) driver_name, | |
953 | .suspend = cmos_suspend, | |
954 | .resume = cmos_resume, | |
955 | } | |
956 | }; | |
957 | ||
958 | static int __init cmos_init(void) | |
959 | { | |
960 | return platform_driver_probe(&cmos_platform_driver, | |
961 | cmos_platform_probe); | |
962 | } | |
963 | module_init(cmos_init); | |
964 | ||
965 | static void __exit cmos_exit(void) | |
966 | { | |
967 | platform_driver_unregister(&cmos_platform_driver); | |
968 | } | |
969 | module_exit(cmos_exit); | |
970 | ||
971 | ||
41ac8df9 | 972 | #endif /* !PNP */ |
7be2c7c9 DB |
973 | |
974 | MODULE_AUTHOR("David Brownell"); | |
975 | MODULE_DESCRIPTION("Driver for PC-style 'CMOS' RTCs"); | |
976 | MODULE_LICENSE("GPL"); |