powerpc: Don't do generic calibrate_delay()
[deliverable/linux.git] / drivers / rtc / rtc-ds1307.c
CommitLineData
1abb0dc9
DB
1/*
2 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
3 *
4 * Copyright (C) 2005 James Chapman (ds1337 core)
5 * Copyright (C) 2006 David Brownell
a2166858 6 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
1abb0dc9
DB
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/slab.h>
16#include <linux/i2c.h>
17#include <linux/string.h>
18#include <linux/rtc.h>
19#include <linux/bcd.h>
20
21
22
23/* We can't determine type by probing, but if we expect pre-Linux code
24 * to have set the chip up as a clock (turning on the oscillator and
25 * setting the date and time), Linux can ignore the non-clock features.
26 * That's a natural job for a factory or repair bench.
1abb0dc9
DB
27 */
28enum ds_type {
045e0e85
DB
29 ds_1307,
30 ds_1337,
31 ds_1338,
32 ds_1339,
33 ds_1340,
34 m41t00,
a2166858 35 rx_8025,
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DB
36 // rs5c372 too? different address...
37};
38
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DB
39
40/* RTC registers don't differ much, except for the century flag */
41#define DS1307_REG_SECS 0x00 /* 00-59 */
42# define DS1307_BIT_CH 0x80
be5f59f4 43# define DS1340_BIT_nEOSC 0x80
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DB
44#define DS1307_REG_MIN 0x01 /* 00-59 */
45#define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
c065f35c
DB
46# define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
47# define DS1307_BIT_PM 0x20 /* in REG_HOUR */
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DB
48# define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
49# define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
50#define DS1307_REG_WDAY 0x03 /* 01-07 */
51#define DS1307_REG_MDAY 0x04 /* 01-31 */
52#define DS1307_REG_MONTH 0x05 /* 01-12 */
53# define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
54#define DS1307_REG_YEAR 0x06 /* 00-99 */
55
56/* Other registers (control, status, alarms, trickle charge, NVRAM, etc)
045e0e85
DB
57 * start at 7, and they differ a LOT. Only control and status matter for
58 * basic RTC date and time functionality; be careful using them.
1abb0dc9 59 */
045e0e85 60#define DS1307_REG_CONTROL 0x07 /* or ds1338 */
1abb0dc9 61# define DS1307_BIT_OUT 0x80
be5f59f4 62# define DS1338_BIT_OSF 0x20
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DB
63# define DS1307_BIT_SQWE 0x10
64# define DS1307_BIT_RS1 0x02
65# define DS1307_BIT_RS0 0x01
66#define DS1337_REG_CONTROL 0x0e
67# define DS1337_BIT_nEOSC 0x80
cb49a5e9 68# define DS1339_BIT_BBSQI 0x20
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DB
69# define DS1337_BIT_RS2 0x10
70# define DS1337_BIT_RS1 0x08
71# define DS1337_BIT_INTCN 0x04
72# define DS1337_BIT_A2IE 0x02
73# define DS1337_BIT_A1IE 0x01
045e0e85
DB
74#define DS1340_REG_CONTROL 0x07
75# define DS1340_BIT_OUT 0x80
76# define DS1340_BIT_FT 0x40
77# define DS1340_BIT_CALIB_SIGN 0x20
78# define DS1340_M_CALIBRATION 0x1f
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RG
79#define DS1340_REG_FLAG 0x09
80# define DS1340_BIT_OSF 0x80
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DB
81#define DS1337_REG_STATUS 0x0f
82# define DS1337_BIT_OSF 0x80
83# define DS1337_BIT_A2I 0x02
84# define DS1337_BIT_A1I 0x01
cb49a5e9 85#define DS1339_REG_ALARM1_SECS 0x07
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DB
86#define DS1339_REG_TRICKLE 0x10
87
a2166858
MF
88#define RX8025_REG_CTRL1 0x0e
89# define RX8025_BIT_2412 0x20
90#define RX8025_REG_CTRL2 0x0f
91# define RX8025_BIT_PON 0x10
92# define RX8025_BIT_VDET 0x40
93# define RX8025_BIT_XST 0x20
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DB
94
95
96struct ds1307 {
cb49a5e9 97 u8 regs[11];
1abb0dc9 98 enum ds_type type;
cb49a5e9
RG
99 unsigned long flags;
100#define HAS_NVRAM 0 /* bit 0 == sysfs file active */
101#define HAS_ALARM 1 /* bit 1 == irq claimed */
045e0e85 102 struct i2c_client *client;
1abb0dc9 103 struct rtc_device *rtc;
cb49a5e9 104 struct work_struct work;
30e7b039
ES
105 s32 (*read_block_data)(struct i2c_client *client, u8 command,
106 u8 length, u8 *values);
107 s32 (*write_block_data)(struct i2c_client *client, u8 command,
108 u8 length, const u8 *values);
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DB
109};
110
045e0e85 111struct chip_desc {
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DB
112 unsigned nvram56:1;
113 unsigned alarm:1;
045e0e85
DB
114};
115
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JD
116static const struct chip_desc chips[] = {
117[ds_1307] = {
045e0e85 118 .nvram56 = 1,
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JD
119},
120[ds_1337] = {
045e0e85 121 .alarm = 1,
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JD
122},
123[ds_1338] = {
045e0e85 124 .nvram56 = 1,
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JD
125},
126[ds_1339] = {
045e0e85 127 .alarm = 1,
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JD
128},
129[ds_1340] = {
130},
131[m41t00] = {
a2166858
MF
132},
133[rx_8025] = {
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DB
134}, };
135
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JD
136static const struct i2c_device_id ds1307_id[] = {
137 { "ds1307", ds_1307 },
138 { "ds1337", ds_1337 },
139 { "ds1338", ds_1338 },
140 { "ds1339", ds_1339 },
141 { "ds1340", ds_1340 },
142 { "m41t00", m41t00 },
a2166858 143 { "rx8025", rx_8025 },
3760f736
JD
144 { }
145};
146MODULE_DEVICE_TABLE(i2c, ds1307_id);
1abb0dc9 147
cb49a5e9
RG
148/*----------------------------------------------------------------------*/
149
30e7b039
ES
150#define BLOCK_DATA_MAX_TRIES 10
151
152static s32 ds1307_read_block_data_once(struct i2c_client *client, u8 command,
153 u8 length, u8 *values)
154{
155 s32 i, data;
156
157 for (i = 0; i < length; i++) {
158 data = i2c_smbus_read_byte_data(client, command + i);
159 if (data < 0)
160 return data;
161 values[i] = data;
162 }
163 return i;
164}
165
166static s32 ds1307_read_block_data(struct i2c_client *client, u8 command,
167 u8 length, u8 *values)
168{
169 u8 oldvalues[I2C_SMBUS_BLOCK_MAX];
170 s32 ret;
171 int tries = 0;
172
173 dev_dbg(&client->dev, "ds1307_read_block_data (length=%d)\n", length);
174 ret = ds1307_read_block_data_once(client, command, length, values);
175 if (ret < 0)
176 return ret;
177 do {
178 if (++tries > BLOCK_DATA_MAX_TRIES) {
179 dev_err(&client->dev,
180 "ds1307_read_block_data failed\n");
181 return -EIO;
182 }
183 memcpy(oldvalues, values, length);
184 ret = ds1307_read_block_data_once(client, command, length,
185 values);
186 if (ret < 0)
187 return ret;
188 } while (memcmp(oldvalues, values, length));
189 return length;
190}
191
192static s32 ds1307_write_block_data(struct i2c_client *client, u8 command,
193 u8 length, const u8 *values)
194{
195 u8 currvalues[I2C_SMBUS_BLOCK_MAX];
196 int tries = 0;
197
198 dev_dbg(&client->dev, "ds1307_write_block_data (length=%d)\n", length);
199 do {
200 s32 i, ret;
201
202 if (++tries > BLOCK_DATA_MAX_TRIES) {
203 dev_err(&client->dev,
204 "ds1307_write_block_data failed\n");
205 return -EIO;
206 }
207 for (i = 0; i < length; i++) {
208 ret = i2c_smbus_write_byte_data(client, command + i,
209 values[i]);
210 if (ret < 0)
211 return ret;
212 }
213 ret = ds1307_read_block_data_once(client, command, length,
214 currvalues);
215 if (ret < 0)
216 return ret;
217 } while (memcmp(currvalues, values, length));
218 return length;
219}
220
221/*----------------------------------------------------------------------*/
222
cb49a5e9
RG
223/*
224 * The IRQ logic includes a "real" handler running in IRQ context just
225 * long enough to schedule this workqueue entry. We need a task context
226 * to talk to the RTC, since I2C I/O calls require that; and disable the
227 * IRQ until we clear its status on the chip, so that this handler can
228 * work with any type of triggering (not just falling edge).
229 *
230 * The ds1337 and ds1339 both have two alarms, but we only use the first
231 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
232 * signal; ds1339 chips have only one alarm signal.
233 */
234static void ds1307_work(struct work_struct *work)
235{
236 struct ds1307 *ds1307;
237 struct i2c_client *client;
238 struct mutex *lock;
239 int stat, control;
240
241 ds1307 = container_of(work, struct ds1307, work);
242 client = ds1307->client;
243 lock = &ds1307->rtc->ops_lock;
244
245 mutex_lock(lock);
246 stat = i2c_smbus_read_byte_data(client, DS1337_REG_STATUS);
247 if (stat < 0)
248 goto out;
249
250 if (stat & DS1337_BIT_A1I) {
251 stat &= ~DS1337_BIT_A1I;
252 i2c_smbus_write_byte_data(client, DS1337_REG_STATUS, stat);
253
254 control = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
255 if (control < 0)
256 goto out;
257
258 control &= ~DS1337_BIT_A1IE;
259 i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, control);
260
261 /* rtc_update_irq() assumes that it is called
262 * from IRQ-disabled context.
263 */
264 local_irq_disable();
265 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
266 local_irq_enable();
267 }
268
269out:
270 if (test_bit(HAS_ALARM, &ds1307->flags))
271 enable_irq(client->irq);
272 mutex_unlock(lock);
273}
274
275static irqreturn_t ds1307_irq(int irq, void *dev_id)
276{
277 struct i2c_client *client = dev_id;
278 struct ds1307 *ds1307 = i2c_get_clientdata(client);
279
280 disable_irq_nosync(irq);
281 schedule_work(&ds1307->work);
282 return IRQ_HANDLED;
283}
284
285/*----------------------------------------------------------------------*/
286
1abb0dc9
DB
287static int ds1307_get_time(struct device *dev, struct rtc_time *t)
288{
289 struct ds1307 *ds1307 = dev_get_drvdata(dev);
290 int tmp;
291
045e0e85 292 /* read the RTC date and time registers all at once */
30e7b039 293 tmp = ds1307->read_block_data(ds1307->client,
fed40b73
BS
294 DS1307_REG_SECS, 7, ds1307->regs);
295 if (tmp != 7) {
1abb0dc9
DB
296 dev_err(dev, "%s error %d\n", "read", tmp);
297 return -EIO;
298 }
299
300 dev_dbg(dev, "%s: %02x %02x %02x %02x %02x %02x %02x\n",
301 "read",
302 ds1307->regs[0], ds1307->regs[1],
303 ds1307->regs[2], ds1307->regs[3],
304 ds1307->regs[4], ds1307->regs[5],
305 ds1307->regs[6]);
306
fe20ba70
AB
307 t->tm_sec = bcd2bin(ds1307->regs[DS1307_REG_SECS] & 0x7f);
308 t->tm_min = bcd2bin(ds1307->regs[DS1307_REG_MIN] & 0x7f);
1abb0dc9 309 tmp = ds1307->regs[DS1307_REG_HOUR] & 0x3f;
fe20ba70
AB
310 t->tm_hour = bcd2bin(tmp);
311 t->tm_wday = bcd2bin(ds1307->regs[DS1307_REG_WDAY] & 0x07) - 1;
312 t->tm_mday = bcd2bin(ds1307->regs[DS1307_REG_MDAY] & 0x3f);
1abb0dc9 313 tmp = ds1307->regs[DS1307_REG_MONTH] & 0x1f;
fe20ba70 314 t->tm_mon = bcd2bin(tmp) - 1;
1abb0dc9
DB
315
316 /* assume 20YY not 19YY, and ignore DS1337_BIT_CENTURY */
fe20ba70 317 t->tm_year = bcd2bin(ds1307->regs[DS1307_REG_YEAR]) + 100;
1abb0dc9
DB
318
319 dev_dbg(dev, "%s secs=%d, mins=%d, "
320 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
321 "read", t->tm_sec, t->tm_min,
322 t->tm_hour, t->tm_mday,
323 t->tm_mon, t->tm_year, t->tm_wday);
324
045e0e85
DB
325 /* initial clock setting can be undefined */
326 return rtc_valid_tm(t);
1abb0dc9
DB
327}
328
329static int ds1307_set_time(struct device *dev, struct rtc_time *t)
330{
331 struct ds1307 *ds1307 = dev_get_drvdata(dev);
332 int result;
333 int tmp;
334 u8 *buf = ds1307->regs;
335
336 dev_dbg(dev, "%s secs=%d, mins=%d, "
337 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
11966adc
JG
338 "write", t->tm_sec, t->tm_min,
339 t->tm_hour, t->tm_mday,
340 t->tm_mon, t->tm_year, t->tm_wday);
1abb0dc9 341
fe20ba70
AB
342 buf[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
343 buf[DS1307_REG_MIN] = bin2bcd(t->tm_min);
344 buf[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
345 buf[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
346 buf[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
347 buf[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
1abb0dc9
DB
348
349 /* assume 20YY not 19YY */
350 tmp = t->tm_year - 100;
fe20ba70 351 buf[DS1307_REG_YEAR] = bin2bcd(tmp);
1abb0dc9 352
be5f59f4
RG
353 switch (ds1307->type) {
354 case ds_1337:
355 case ds_1339:
1abb0dc9 356 buf[DS1307_REG_MONTH] |= DS1337_BIT_CENTURY;
be5f59f4
RG
357 break;
358 case ds_1340:
1abb0dc9
DB
359 buf[DS1307_REG_HOUR] |= DS1340_BIT_CENTURY_EN
360 | DS1340_BIT_CENTURY;
be5f59f4
RG
361 break;
362 default:
363 break;
364 }
1abb0dc9 365
1abb0dc9
DB
366 dev_dbg(dev, "%s: %02x %02x %02x %02x %02x %02x %02x\n",
367 "write", buf[0], buf[1], buf[2], buf[3],
368 buf[4], buf[5], buf[6]);
369
30e7b039 370 result = ds1307->write_block_data(ds1307->client, 0, 7, buf);
fed40b73
BS
371 if (result < 0) {
372 dev_err(dev, "%s error %d\n", "write", result);
373 return result;
1abb0dc9
DB
374 }
375 return 0;
376}
377
74d88eb2 378static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
cb49a5e9
RG
379{
380 struct i2c_client *client = to_i2c_client(dev);
381 struct ds1307 *ds1307 = i2c_get_clientdata(client);
382 int ret;
383
384 if (!test_bit(HAS_ALARM, &ds1307->flags))
385 return -EINVAL;
386
387 /* read all ALARM1, ALARM2, and status registers at once */
30e7b039 388 ret = ds1307->read_block_data(client,
fed40b73
BS
389 DS1339_REG_ALARM1_SECS, 9, ds1307->regs);
390 if (ret != 9) {
cb49a5e9
RG
391 dev_err(dev, "%s error %d\n", "alarm read", ret);
392 return -EIO;
393 }
394
395 dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
396 "alarm read",
397 ds1307->regs[0], ds1307->regs[1],
398 ds1307->regs[2], ds1307->regs[3],
399 ds1307->regs[4], ds1307->regs[5],
400 ds1307->regs[6], ds1307->regs[7],
401 ds1307->regs[8]);
402
403 /* report alarm time (ALARM1); assume 24 hour and day-of-month modes,
404 * and that all four fields are checked matches
405 */
406 t->time.tm_sec = bcd2bin(ds1307->regs[0] & 0x7f);
407 t->time.tm_min = bcd2bin(ds1307->regs[1] & 0x7f);
408 t->time.tm_hour = bcd2bin(ds1307->regs[2] & 0x3f);
409 t->time.tm_mday = bcd2bin(ds1307->regs[3] & 0x3f);
410 t->time.tm_mon = -1;
411 t->time.tm_year = -1;
412 t->time.tm_wday = -1;
413 t->time.tm_yday = -1;
414 t->time.tm_isdst = -1;
415
416 /* ... and status */
417 t->enabled = !!(ds1307->regs[7] & DS1337_BIT_A1IE);
418 t->pending = !!(ds1307->regs[8] & DS1337_BIT_A1I);
419
420 dev_dbg(dev, "%s secs=%d, mins=%d, "
421 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
422 "alarm read", t->time.tm_sec, t->time.tm_min,
423 t->time.tm_hour, t->time.tm_mday,
424 t->enabled, t->pending);
425
426 return 0;
427}
428
74d88eb2 429static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
cb49a5e9
RG
430{
431 struct i2c_client *client = to_i2c_client(dev);
432 struct ds1307 *ds1307 = i2c_get_clientdata(client);
433 unsigned char *buf = ds1307->regs;
434 u8 control, status;
435 int ret;
436
437 if (!test_bit(HAS_ALARM, &ds1307->flags))
438 return -EINVAL;
439
440 dev_dbg(dev, "%s secs=%d, mins=%d, "
441 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
442 "alarm set", t->time.tm_sec, t->time.tm_min,
443 t->time.tm_hour, t->time.tm_mday,
444 t->enabled, t->pending);
445
446 /* read current status of both alarms and the chip */
30e7b039 447 ret = ds1307->read_block_data(client,
fed40b73
BS
448 DS1339_REG_ALARM1_SECS, 9, buf);
449 if (ret != 9) {
cb49a5e9
RG
450 dev_err(dev, "%s error %d\n", "alarm write", ret);
451 return -EIO;
452 }
453 control = ds1307->regs[7];
454 status = ds1307->regs[8];
455
456 dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
457 "alarm set (old status)",
458 ds1307->regs[0], ds1307->regs[1],
459 ds1307->regs[2], ds1307->regs[3],
460 ds1307->regs[4], ds1307->regs[5],
461 ds1307->regs[6], control, status);
462
463 /* set ALARM1, using 24 hour and day-of-month modes */
cb49a5e9
RG
464 buf[0] = bin2bcd(t->time.tm_sec);
465 buf[1] = bin2bcd(t->time.tm_min);
466 buf[2] = bin2bcd(t->time.tm_hour);
467 buf[3] = bin2bcd(t->time.tm_mday);
468
469 /* set ALARM2 to non-garbage */
470 buf[4] = 0;
471 buf[5] = 0;
472 buf[6] = 0;
473
474 /* optionally enable ALARM1 */
475 buf[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
476 if (t->enabled) {
477 dev_dbg(dev, "alarm IRQ armed\n");
478 buf[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
479 }
480 buf[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
481
30e7b039 482 ret = ds1307->write_block_data(client,
fed40b73
BS
483 DS1339_REG_ALARM1_SECS, 9, buf);
484 if (ret < 0) {
cb49a5e9 485 dev_err(dev, "can't set alarm time\n");
fed40b73 486 return ret;
cb49a5e9
RG
487 }
488
489 return 0;
490}
491
492static int ds1307_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
493{
494 struct i2c_client *client = to_i2c_client(dev);
495 struct ds1307 *ds1307 = i2c_get_clientdata(client);
496 int ret;
497
498 switch (cmd) {
499 case RTC_AIE_OFF:
500 if (!test_bit(HAS_ALARM, &ds1307->flags))
501 return -ENOTTY;
502
503 ret = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
504 if (ret < 0)
505 return ret;
506
507 ret &= ~DS1337_BIT_A1IE;
508
509 ret = i2c_smbus_write_byte_data(client,
510 DS1337_REG_CONTROL, ret);
511 if (ret < 0)
512 return ret;
513
514 break;
515
516 case RTC_AIE_ON:
517 if (!test_bit(HAS_ALARM, &ds1307->flags))
518 return -ENOTTY;
519
520 ret = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
521 if (ret < 0)
522 return ret;
523
524 ret |= DS1337_BIT_A1IE;
525
526 ret = i2c_smbus_write_byte_data(client,
527 DS1337_REG_CONTROL, ret);
528 if (ret < 0)
529 return ret;
530
531 break;
532
533 default:
534 return -ENOIOCTLCMD;
535 }
536
537 return 0;
538}
539
ff8371ac 540static const struct rtc_class_ops ds13xx_rtc_ops = {
1abb0dc9
DB
541 .read_time = ds1307_get_time,
542 .set_time = ds1307_set_time,
74d88eb2
JR
543 .read_alarm = ds1337_read_alarm,
544 .set_alarm = ds1337_set_alarm,
cb49a5e9 545 .ioctl = ds1307_ioctl,
1abb0dc9
DB
546};
547
682d73f6
DB
548/*----------------------------------------------------------------------*/
549
550#define NVRAM_SIZE 56
551
552static ssize_t
553ds1307_nvram_read(struct kobject *kobj, struct bin_attribute *attr,
554 char *buf, loff_t off, size_t count)
555{
556 struct i2c_client *client;
557 struct ds1307 *ds1307;
682d73f6
DB
558 int result;
559
fcd8db00 560 client = kobj_to_i2c_client(kobj);
682d73f6
DB
561 ds1307 = i2c_get_clientdata(client);
562
563 if (unlikely(off >= NVRAM_SIZE))
564 return 0;
565 if ((off + count) > NVRAM_SIZE)
566 count = NVRAM_SIZE - off;
567 if (unlikely(!count))
568 return count;
569
30e7b039 570 result = ds1307->read_block_data(client, 8 + off, count, buf);
fed40b73 571 if (result < 0)
682d73f6 572 dev_err(&client->dev, "%s error %d\n", "nvram read", result);
fed40b73 573 return result;
682d73f6
DB
574}
575
576static ssize_t
577ds1307_nvram_write(struct kobject *kobj, struct bin_attribute *attr,
578 char *buf, loff_t off, size_t count)
579{
580 struct i2c_client *client;
30e7b039 581 struct ds1307 *ds1307;
fed40b73 582 int result;
682d73f6 583
fcd8db00 584 client = kobj_to_i2c_client(kobj);
30e7b039 585 ds1307 = i2c_get_clientdata(client);
682d73f6
DB
586
587 if (unlikely(off >= NVRAM_SIZE))
588 return -EFBIG;
589 if ((off + count) > NVRAM_SIZE)
590 count = NVRAM_SIZE - off;
591 if (unlikely(!count))
592 return count;
593
30e7b039 594 result = ds1307->write_block_data(client, 8 + off, count, buf);
fed40b73
BS
595 if (result < 0) {
596 dev_err(&client->dev, "%s error %d\n", "nvram write", result);
597 return result;
598 }
599 return count;
682d73f6
DB
600}
601
602static struct bin_attribute nvram = {
603 .attr = {
604 .name = "nvram",
605 .mode = S_IRUGO | S_IWUSR,
682d73f6
DB
606 },
607
608 .read = ds1307_nvram_read,
609 .write = ds1307_nvram_write,
610 .size = NVRAM_SIZE,
611};
612
613/*----------------------------------------------------------------------*/
614
1abb0dc9
DB
615static struct i2c_driver ds1307_driver;
616
d2653e92
JD
617static int __devinit ds1307_probe(struct i2c_client *client,
618 const struct i2c_device_id *id)
1abb0dc9
DB
619{
620 struct ds1307 *ds1307;
621 int err = -ENODEV;
1abb0dc9 622 int tmp;
3760f736 623 const struct chip_desc *chip = &chips[id->driver_data];
c065f35c 624 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
cb49a5e9 625 int want_irq = false;
fed40b73 626 unsigned char *buf;
1abb0dc9 627
30e7b039
ES
628 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)
629 && !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK))
c065f35c
DB
630 return -EIO;
631
632 if (!(ds1307 = kzalloc(sizeof(struct ds1307), GFP_KERNEL)))
633 return -ENOMEM;
045e0e85
DB
634
635 ds1307->client = client;
1abb0dc9 636 i2c_set_clientdata(client, ds1307);
3760f736 637 ds1307->type = id->driver_data;
fed40b73 638 buf = ds1307->regs;
30e7b039
ES
639 if (i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) {
640 ds1307->read_block_data = i2c_smbus_read_i2c_block_data;
641 ds1307->write_block_data = i2c_smbus_write_i2c_block_data;
642 } else {
643 ds1307->read_block_data = ds1307_read_block_data;
644 ds1307->write_block_data = ds1307_write_block_data;
645 }
045e0e85
DB
646
647 switch (ds1307->type) {
648 case ds_1337:
649 case ds_1339:
cb49a5e9
RG
650 /* has IRQ? */
651 if (ds1307->client->irq > 0 && chip->alarm) {
652 INIT_WORK(&ds1307->work, ds1307_work);
653 want_irq = true;
654 }
be5f59f4 655 /* get registers that the "rtc" read below won't read... */
30e7b039 656 tmp = ds1307->read_block_data(ds1307->client,
fed40b73 657 DS1337_REG_CONTROL, 2, buf);
1abb0dc9
DB
658 if (tmp != 2) {
659 pr_debug("read error %d\n", tmp);
660 err = -EIO;
661 goto exit_free;
662 }
663
be5f59f4
RG
664 /* oscillator off? turn it on, so clock can tick. */
665 if (ds1307->regs[0] & DS1337_BIT_nEOSC)
cb49a5e9
RG
666 ds1307->regs[0] &= ~DS1337_BIT_nEOSC;
667
668 /* Using IRQ? Disable the square wave and both alarms.
669 * For ds1339, be sure alarms can trigger when we're
670 * running on Vbackup (BBSQI); we assume ds1337 will
671 * ignore that bit
672 */
673 if (want_irq) {
674 ds1307->regs[0] |= DS1337_BIT_INTCN | DS1339_BIT_BBSQI;
675 ds1307->regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
676 }
677
678 i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL,
679 ds1307->regs[0]);
be5f59f4
RG
680
681 /* oscillator fault? clear flag, and warn */
682 if (ds1307->regs[1] & DS1337_BIT_OSF) {
683 i2c_smbus_write_byte_data(client, DS1337_REG_STATUS,
684 ds1307->regs[1] & ~DS1337_BIT_OSF);
685 dev_warn(&client->dev, "SET TIME!\n");
1abb0dc9 686 }
045e0e85 687 break;
a2166858
MF
688
689 case rx_8025:
690 tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
691 RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
692 if (tmp != 2) {
693 pr_debug("read error %d\n", tmp);
694 err = -EIO;
695 goto exit_free;
696 }
697
698 /* oscillator off? turn it on, so clock can tick. */
699 if (!(ds1307->regs[1] & RX8025_BIT_XST)) {
700 ds1307->regs[1] |= RX8025_BIT_XST;
701 i2c_smbus_write_byte_data(client,
702 RX8025_REG_CTRL2 << 4 | 0x08,
703 ds1307->regs[1]);
704 dev_warn(&client->dev,
705 "oscillator stop detected - SET TIME!\n");
706 }
707
708 if (ds1307->regs[1] & RX8025_BIT_PON) {
709 ds1307->regs[1] &= ~RX8025_BIT_PON;
710 i2c_smbus_write_byte_data(client,
711 RX8025_REG_CTRL2 << 4 | 0x08,
712 ds1307->regs[1]);
713 dev_warn(&client->dev, "power-on detected\n");
714 }
715
716 if (ds1307->regs[1] & RX8025_BIT_VDET) {
717 ds1307->regs[1] &= ~RX8025_BIT_VDET;
718 i2c_smbus_write_byte_data(client,
719 RX8025_REG_CTRL2 << 4 | 0x08,
720 ds1307->regs[1]);
721 dev_warn(&client->dev, "voltage drop detected\n");
722 }
723
724 /* make sure we are running in 24hour mode */
725 if (!(ds1307->regs[0] & RX8025_BIT_2412)) {
726 u8 hour;
727
728 /* switch to 24 hour mode */
729 i2c_smbus_write_byte_data(client,
730 RX8025_REG_CTRL1 << 4 | 0x08,
731 ds1307->regs[0] |
732 RX8025_BIT_2412);
733
734 tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
735 RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
736 if (tmp != 2) {
737 pr_debug("read error %d\n", tmp);
738 err = -EIO;
739 goto exit_free;
740 }
741
742 /* correct hour */
743 hour = bcd2bin(ds1307->regs[DS1307_REG_HOUR]);
744 if (hour == 12)
745 hour = 0;
746 if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
747 hour += 12;
748
749 i2c_smbus_write_byte_data(client,
750 DS1307_REG_HOUR << 4 | 0x08,
751 hour);
752 }
753 break;
045e0e85
DB
754 default:
755 break;
756 }
1abb0dc9
DB
757
758read_rtc:
759 /* read RTC registers */
30e7b039 760 tmp = ds1307->read_block_data(ds1307->client, 0, 8, buf);
fed40b73 761 if (tmp != 8) {
1abb0dc9
DB
762 pr_debug("read error %d\n", tmp);
763 err = -EIO;
764 goto exit_free;
765 }
766
767 /* minimal sanity checking; some chips (like DS1340) don't
768 * specify the extra bits as must-be-zero, but there are
769 * still a few values that are clearly out-of-range.
770 */
771 tmp = ds1307->regs[DS1307_REG_SECS];
045e0e85
DB
772 switch (ds1307->type) {
773 case ds_1307:
045e0e85 774 case m41t00:
be5f59f4 775 /* clock halted? turn it on, so clock can tick. */
045e0e85 776 if (tmp & DS1307_BIT_CH) {
be5f59f4
RG
777 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
778 dev_warn(&client->dev, "SET TIME!\n");
045e0e85 779 goto read_rtc;
1abb0dc9 780 }
045e0e85 781 break;
be5f59f4
RG
782 case ds_1338:
783 /* clock halted? turn it on, so clock can tick. */
045e0e85 784 if (tmp & DS1307_BIT_CH)
be5f59f4
RG
785 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
786
787 /* oscillator fault? clear flag, and warn */
788 if (ds1307->regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
789 i2c_smbus_write_byte_data(client, DS1307_REG_CONTROL,
bd16f9eb 790 ds1307->regs[DS1307_REG_CONTROL]
be5f59f4
RG
791 & ~DS1338_BIT_OSF);
792 dev_warn(&client->dev, "SET TIME!\n");
793 goto read_rtc;
794 }
045e0e85 795 break;
fcd8db00
R
796 case ds_1340:
797 /* clock halted? turn it on, so clock can tick. */
798 if (tmp & DS1340_BIT_nEOSC)
799 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
800
801 tmp = i2c_smbus_read_byte_data(client, DS1340_REG_FLAG);
802 if (tmp < 0) {
803 pr_debug("read error %d\n", tmp);
804 err = -EIO;
805 goto exit_free;
806 }
807
808 /* oscillator fault? clear flag, and warn */
809 if (tmp & DS1340_BIT_OSF) {
810 i2c_smbus_write_byte_data(client, DS1340_REG_FLAG, 0);
811 dev_warn(&client->dev, "SET TIME!\n");
812 }
813 break;
a2166858 814 case rx_8025:
c065f35c
DB
815 case ds_1337:
816 case ds_1339:
045e0e85 817 break;
1abb0dc9 818 }
045e0e85 819
1abb0dc9 820 tmp = ds1307->regs[DS1307_REG_HOUR];
c065f35c
DB
821 switch (ds1307->type) {
822 case ds_1340:
823 case m41t00:
824 /* NOTE: ignores century bits; fix before deploying
825 * systems that will run through year 2100.
826 */
827 break;
a2166858
MF
828 case rx_8025:
829 break;
c065f35c
DB
830 default:
831 if (!(tmp & DS1307_BIT_12HR))
832 break;
833
834 /* Be sure we're in 24 hour mode. Multi-master systems
835 * take note...
836 */
fe20ba70 837 tmp = bcd2bin(tmp & 0x1f);
c065f35c
DB
838 if (tmp == 12)
839 tmp = 0;
840 if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
841 tmp += 12;
1abb0dc9
DB
842 i2c_smbus_write_byte_data(client,
843 DS1307_REG_HOUR,
fe20ba70 844 bin2bcd(tmp));
1abb0dc9
DB
845 }
846
1abb0dc9
DB
847 ds1307->rtc = rtc_device_register(client->name, &client->dev,
848 &ds13xx_rtc_ops, THIS_MODULE);
849 if (IS_ERR(ds1307->rtc)) {
850 err = PTR_ERR(ds1307->rtc);
851 dev_err(&client->dev,
852 "unable to register the class device\n");
c065f35c 853 goto exit_free;
1abb0dc9
DB
854 }
855
cb49a5e9
RG
856 if (want_irq) {
857 err = request_irq(client->irq, ds1307_irq, 0,
858 ds1307->rtc->name, client);
859 if (err) {
860 dev_err(&client->dev,
861 "unable to request IRQ!\n");
862 goto exit_irq;
863 }
864 set_bit(HAS_ALARM, &ds1307->flags);
865 dev_dbg(&client->dev, "got IRQ %d\n", client->irq);
866 }
867
682d73f6
DB
868 if (chip->nvram56) {
869 err = sysfs_create_bin_file(&client->dev.kobj, &nvram);
870 if (err == 0) {
cb49a5e9 871 set_bit(HAS_NVRAM, &ds1307->flags);
682d73f6
DB
872 dev_info(&client->dev, "56 bytes nvram\n");
873 }
874 }
875
1abb0dc9
DB
876 return 0;
877
cb49a5e9
RG
878exit_irq:
879 if (ds1307->rtc)
880 rtc_device_unregister(ds1307->rtc);
1abb0dc9
DB
881exit_free:
882 kfree(ds1307);
1abb0dc9
DB
883 return err;
884}
885
c065f35c 886static int __devexit ds1307_remove(struct i2c_client *client)
1abb0dc9 887{
cb49a5e9
RG
888 struct ds1307 *ds1307 = i2c_get_clientdata(client);
889
890 if (test_and_clear_bit(HAS_ALARM, &ds1307->flags)) {
891 free_irq(client->irq, client);
892 cancel_work_sync(&ds1307->work);
893 }
1abb0dc9 894
cb49a5e9 895 if (test_and_clear_bit(HAS_NVRAM, &ds1307->flags))
682d73f6
DB
896 sysfs_remove_bin_file(&client->dev.kobj, &nvram);
897
1abb0dc9 898 rtc_device_unregister(ds1307->rtc);
1abb0dc9
DB
899 kfree(ds1307);
900 return 0;
901}
902
903static struct i2c_driver ds1307_driver = {
904 .driver = {
c065f35c 905 .name = "rtc-ds1307",
1abb0dc9
DB
906 .owner = THIS_MODULE,
907 },
c065f35c
DB
908 .probe = ds1307_probe,
909 .remove = __devexit_p(ds1307_remove),
3760f736 910 .id_table = ds1307_id,
1abb0dc9
DB
911};
912
913static int __init ds1307_init(void)
914{
915 return i2c_add_driver(&ds1307_driver);
916}
917module_init(ds1307_init);
918
919static void __exit ds1307_exit(void)
920{
921 i2c_del_driver(&ds1307_driver);
922}
923module_exit(ds1307_exit);
924
925MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
926MODULE_LICENSE("GPL");
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