Commit | Line | Data |
---|---|---|
1abb0dc9 DB |
1 | /* |
2 | * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips. | |
3 | * | |
4 | * Copyright (C) 2005 James Chapman (ds1337 core) | |
5 | * Copyright (C) 2006 David Brownell | |
a2166858 | 6 | * Copyright (C) 2009 Matthias Fuchs (rx8025 support) |
bc48b902 | 7 | * Copyright (C) 2012 Bertrand Achard (nvram access fixes) |
1abb0dc9 DB |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/string.h> | |
19 | #include <linux/rtc.h> | |
20 | #include <linux/bcd.h> | |
eb86c306 | 21 | #include <linux/rtc/ds1307.h> |
1abb0dc9 | 22 | |
40ce972d DA |
23 | /* |
24 | * We can't determine type by probing, but if we expect pre-Linux code | |
1abb0dc9 DB |
25 | * to have set the chip up as a clock (turning on the oscillator and |
26 | * setting the date and time), Linux can ignore the non-clock features. | |
27 | * That's a natural job for a factory or repair bench. | |
1abb0dc9 DB |
28 | */ |
29 | enum ds_type { | |
045e0e85 DB |
30 | ds_1307, |
31 | ds_1337, | |
32 | ds_1338, | |
33 | ds_1339, | |
34 | ds_1340, | |
33df2ee1 | 35 | ds_1388, |
97f902b7 | 36 | ds_3231, |
045e0e85 | 37 | m41t00, |
f4199f85 | 38 | mcp794xx, |
a2166858 | 39 | rx_8025, |
32d322bc | 40 | last_ds_type /* always last */ |
40ce972d | 41 | /* rs5c372 too? different address... */ |
1abb0dc9 DB |
42 | }; |
43 | ||
1abb0dc9 DB |
44 | |
45 | /* RTC registers don't differ much, except for the century flag */ | |
46 | #define DS1307_REG_SECS 0x00 /* 00-59 */ | |
47 | # define DS1307_BIT_CH 0x80 | |
be5f59f4 | 48 | # define DS1340_BIT_nEOSC 0x80 |
f4199f85 | 49 | # define MCP794XX_BIT_ST 0x80 |
1abb0dc9 DB |
50 | #define DS1307_REG_MIN 0x01 /* 00-59 */ |
51 | #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */ | |
c065f35c DB |
52 | # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */ |
53 | # define DS1307_BIT_PM 0x20 /* in REG_HOUR */ | |
1abb0dc9 DB |
54 | # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */ |
55 | # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */ | |
56 | #define DS1307_REG_WDAY 0x03 /* 01-07 */ | |
f4199f85 | 57 | # define MCP794XX_BIT_VBATEN 0x08 |
1abb0dc9 DB |
58 | #define DS1307_REG_MDAY 0x04 /* 01-31 */ |
59 | #define DS1307_REG_MONTH 0x05 /* 01-12 */ | |
60 | # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */ | |
61 | #define DS1307_REG_YEAR 0x06 /* 00-99 */ | |
62 | ||
40ce972d DA |
63 | /* |
64 | * Other registers (control, status, alarms, trickle charge, NVRAM, etc) | |
045e0e85 DB |
65 | * start at 7, and they differ a LOT. Only control and status matter for |
66 | * basic RTC date and time functionality; be careful using them. | |
1abb0dc9 | 67 | */ |
045e0e85 | 68 | #define DS1307_REG_CONTROL 0x07 /* or ds1338 */ |
1abb0dc9 | 69 | # define DS1307_BIT_OUT 0x80 |
be5f59f4 | 70 | # define DS1338_BIT_OSF 0x20 |
1abb0dc9 DB |
71 | # define DS1307_BIT_SQWE 0x10 |
72 | # define DS1307_BIT_RS1 0x02 | |
73 | # define DS1307_BIT_RS0 0x01 | |
74 | #define DS1337_REG_CONTROL 0x0e | |
75 | # define DS1337_BIT_nEOSC 0x80 | |
cb49a5e9 | 76 | # define DS1339_BIT_BBSQI 0x20 |
97f902b7 | 77 | # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */ |
1abb0dc9 DB |
78 | # define DS1337_BIT_RS2 0x10 |
79 | # define DS1337_BIT_RS1 0x08 | |
80 | # define DS1337_BIT_INTCN 0x04 | |
81 | # define DS1337_BIT_A2IE 0x02 | |
82 | # define DS1337_BIT_A1IE 0x01 | |
045e0e85 DB |
83 | #define DS1340_REG_CONTROL 0x07 |
84 | # define DS1340_BIT_OUT 0x80 | |
85 | # define DS1340_BIT_FT 0x40 | |
86 | # define DS1340_BIT_CALIB_SIGN 0x20 | |
87 | # define DS1340_M_CALIBRATION 0x1f | |
be5f59f4 RG |
88 | #define DS1340_REG_FLAG 0x09 |
89 | # define DS1340_BIT_OSF 0x80 | |
1abb0dc9 DB |
90 | #define DS1337_REG_STATUS 0x0f |
91 | # define DS1337_BIT_OSF 0x80 | |
92 | # define DS1337_BIT_A2I 0x02 | |
93 | # define DS1337_BIT_A1I 0x01 | |
cb49a5e9 | 94 | #define DS1339_REG_ALARM1_SECS 0x07 |
eb86c306 WS |
95 | |
96 | #define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0 | |
1abb0dc9 | 97 | |
a2166858 MF |
98 | #define RX8025_REG_CTRL1 0x0e |
99 | # define RX8025_BIT_2412 0x20 | |
100 | #define RX8025_REG_CTRL2 0x0f | |
101 | # define RX8025_BIT_PON 0x10 | |
102 | # define RX8025_BIT_VDET 0x40 | |
103 | # define RX8025_BIT_XST 0x20 | |
1abb0dc9 DB |
104 | |
105 | ||
106 | struct ds1307 { | |
33df2ee1 | 107 | u8 offset; /* register's offset */ |
cb49a5e9 | 108 | u8 regs[11]; |
9eab0a78 AB |
109 | u16 nvram_offset; |
110 | struct bin_attribute *nvram; | |
1abb0dc9 | 111 | enum ds_type type; |
cb49a5e9 RG |
112 | unsigned long flags; |
113 | #define HAS_NVRAM 0 /* bit 0 == sysfs file active */ | |
114 | #define HAS_ALARM 1 /* bit 1 == irq claimed */ | |
045e0e85 | 115 | struct i2c_client *client; |
1abb0dc9 | 116 | struct rtc_device *rtc; |
cb49a5e9 | 117 | struct work_struct work; |
0cc43a18 | 118 | s32 (*read_block_data)(const struct i2c_client *client, u8 command, |
30e7b039 | 119 | u8 length, u8 *values); |
0cc43a18 | 120 | s32 (*write_block_data)(const struct i2c_client *client, u8 command, |
30e7b039 | 121 | u8 length, const u8 *values); |
1abb0dc9 DB |
122 | }; |
123 | ||
045e0e85 | 124 | struct chip_desc { |
045e0e85 | 125 | unsigned alarm:1; |
9eab0a78 AB |
126 | u16 nvram_offset; |
127 | u16 nvram_size; | |
eb86c306 | 128 | u16 trickle_charger_reg; |
33b04b7b MV |
129 | u8 trickle_charger_setup; |
130 | u8 (*do_trickle_setup)(struct i2c_client *, uint32_t, bool); | |
045e0e85 DB |
131 | }; |
132 | ||
33b04b7b MV |
133 | static u8 do_trickle_setup_ds1339(struct i2c_client *, |
134 | uint32_t ohms, bool diode); | |
135 | ||
136 | static struct chip_desc chips[last_ds_type] = { | |
32d322bc | 137 | [ds_1307] = { |
9eab0a78 AB |
138 | .nvram_offset = 8, |
139 | .nvram_size = 56, | |
32d322bc WS |
140 | }, |
141 | [ds_1337] = { | |
142 | .alarm = 1, | |
143 | }, | |
144 | [ds_1338] = { | |
9eab0a78 AB |
145 | .nvram_offset = 8, |
146 | .nvram_size = 56, | |
32d322bc WS |
147 | }, |
148 | [ds_1339] = { | |
149 | .alarm = 1, | |
eb86c306 | 150 | .trickle_charger_reg = 0x10, |
33b04b7b | 151 | .do_trickle_setup = &do_trickle_setup_ds1339, |
eb86c306 WS |
152 | }, |
153 | [ds_1340] = { | |
154 | .trickle_charger_reg = 0x08, | |
155 | }, | |
156 | [ds_1388] = { | |
157 | .trickle_charger_reg = 0x0a, | |
32d322bc WS |
158 | }, |
159 | [ds_3231] = { | |
160 | .alarm = 1, | |
161 | }, | |
f4199f85 | 162 | [mcp794xx] = { |
1d1945d2 | 163 | .alarm = 1, |
9eab0a78 AB |
164 | /* this is battery backed SRAM */ |
165 | .nvram_offset = 0x20, | |
166 | .nvram_size = 0x40, | |
167 | }, | |
32d322bc | 168 | }; |
045e0e85 | 169 | |
3760f736 JD |
170 | static const struct i2c_device_id ds1307_id[] = { |
171 | { "ds1307", ds_1307 }, | |
172 | { "ds1337", ds_1337 }, | |
173 | { "ds1338", ds_1338 }, | |
174 | { "ds1339", ds_1339 }, | |
33df2ee1 | 175 | { "ds1388", ds_1388 }, |
3760f736 | 176 | { "ds1340", ds_1340 }, |
97f902b7 | 177 | { "ds3231", ds_3231 }, |
3760f736 | 178 | { "m41t00", m41t00 }, |
f4199f85 TN |
179 | { "mcp7940x", mcp794xx }, |
180 | { "mcp7941x", mcp794xx }, | |
31c1771c | 181 | { "pt7c4338", ds_1307 }, |
a2166858 | 182 | { "rx8025", rx_8025 }, |
3760f736 JD |
183 | { } |
184 | }; | |
185 | MODULE_DEVICE_TABLE(i2c, ds1307_id); | |
1abb0dc9 | 186 | |
cb49a5e9 RG |
187 | /*----------------------------------------------------------------------*/ |
188 | ||
30e7b039 ES |
189 | #define BLOCK_DATA_MAX_TRIES 10 |
190 | ||
0cc43a18 JD |
191 | static s32 ds1307_read_block_data_once(const struct i2c_client *client, |
192 | u8 command, u8 length, u8 *values) | |
30e7b039 ES |
193 | { |
194 | s32 i, data; | |
195 | ||
196 | for (i = 0; i < length; i++) { | |
197 | data = i2c_smbus_read_byte_data(client, command + i); | |
198 | if (data < 0) | |
199 | return data; | |
200 | values[i] = data; | |
201 | } | |
202 | return i; | |
203 | } | |
204 | ||
0cc43a18 | 205 | static s32 ds1307_read_block_data(const struct i2c_client *client, u8 command, |
30e7b039 ES |
206 | u8 length, u8 *values) |
207 | { | |
bc48b902 | 208 | u8 oldvalues[255]; |
30e7b039 ES |
209 | s32 ret; |
210 | int tries = 0; | |
211 | ||
212 | dev_dbg(&client->dev, "ds1307_read_block_data (length=%d)\n", length); | |
213 | ret = ds1307_read_block_data_once(client, command, length, values); | |
214 | if (ret < 0) | |
215 | return ret; | |
216 | do { | |
217 | if (++tries > BLOCK_DATA_MAX_TRIES) { | |
218 | dev_err(&client->dev, | |
219 | "ds1307_read_block_data failed\n"); | |
220 | return -EIO; | |
221 | } | |
222 | memcpy(oldvalues, values, length); | |
223 | ret = ds1307_read_block_data_once(client, command, length, | |
224 | values); | |
225 | if (ret < 0) | |
226 | return ret; | |
227 | } while (memcmp(oldvalues, values, length)); | |
228 | return length; | |
229 | } | |
230 | ||
0cc43a18 | 231 | static s32 ds1307_write_block_data(const struct i2c_client *client, u8 command, |
30e7b039 ES |
232 | u8 length, const u8 *values) |
233 | { | |
bc48b902 | 234 | u8 currvalues[255]; |
30e7b039 ES |
235 | int tries = 0; |
236 | ||
237 | dev_dbg(&client->dev, "ds1307_write_block_data (length=%d)\n", length); | |
238 | do { | |
239 | s32 i, ret; | |
240 | ||
241 | if (++tries > BLOCK_DATA_MAX_TRIES) { | |
242 | dev_err(&client->dev, | |
243 | "ds1307_write_block_data failed\n"); | |
244 | return -EIO; | |
245 | } | |
246 | for (i = 0; i < length; i++) { | |
247 | ret = i2c_smbus_write_byte_data(client, command + i, | |
248 | values[i]); | |
249 | if (ret < 0) | |
250 | return ret; | |
251 | } | |
252 | ret = ds1307_read_block_data_once(client, command, length, | |
253 | currvalues); | |
254 | if (ret < 0) | |
255 | return ret; | |
256 | } while (memcmp(currvalues, values, length)); | |
257 | return length; | |
258 | } | |
259 | ||
260 | /*----------------------------------------------------------------------*/ | |
261 | ||
bc48b902 BA |
262 | /* These RTC devices are not designed to be connected to a SMbus adapter. |
263 | SMbus limits block operations length to 32 bytes, whereas it's not | |
264 | limited on I2C buses. As a result, accesses may exceed 32 bytes; | |
265 | in that case, split them into smaller blocks */ | |
266 | ||
267 | static s32 ds1307_native_smbus_write_block_data(const struct i2c_client *client, | |
268 | u8 command, u8 length, const u8 *values) | |
269 | { | |
270 | u8 suboffset = 0; | |
271 | ||
272 | if (length <= I2C_SMBUS_BLOCK_MAX) | |
273 | return i2c_smbus_write_i2c_block_data(client, | |
274 | command, length, values); | |
275 | ||
276 | while (suboffset < length) { | |
277 | s32 retval = i2c_smbus_write_i2c_block_data(client, | |
278 | command + suboffset, | |
279 | min(I2C_SMBUS_BLOCK_MAX, length - suboffset), | |
280 | values + suboffset); | |
281 | if (retval < 0) | |
282 | return retval; | |
283 | ||
284 | suboffset += I2C_SMBUS_BLOCK_MAX; | |
285 | } | |
286 | return length; | |
287 | } | |
288 | ||
289 | static s32 ds1307_native_smbus_read_block_data(const struct i2c_client *client, | |
290 | u8 command, u8 length, u8 *values) | |
291 | { | |
292 | u8 suboffset = 0; | |
293 | ||
294 | if (length <= I2C_SMBUS_BLOCK_MAX) | |
295 | return i2c_smbus_read_i2c_block_data(client, | |
296 | command, length, values); | |
297 | ||
298 | while (suboffset < length) { | |
299 | s32 retval = i2c_smbus_read_i2c_block_data(client, | |
300 | command + suboffset, | |
301 | min(I2C_SMBUS_BLOCK_MAX, length - suboffset), | |
302 | values + suboffset); | |
303 | if (retval < 0) | |
304 | return retval; | |
305 | ||
306 | suboffset += I2C_SMBUS_BLOCK_MAX; | |
307 | } | |
308 | return length; | |
309 | } | |
310 | ||
311 | /*----------------------------------------------------------------------*/ | |
312 | ||
cb49a5e9 RG |
313 | /* |
314 | * The IRQ logic includes a "real" handler running in IRQ context just | |
315 | * long enough to schedule this workqueue entry. We need a task context | |
316 | * to talk to the RTC, since I2C I/O calls require that; and disable the | |
317 | * IRQ until we clear its status on the chip, so that this handler can | |
318 | * work with any type of triggering (not just falling edge). | |
319 | * | |
320 | * The ds1337 and ds1339 both have two alarms, but we only use the first | |
321 | * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm | |
322 | * signal; ds1339 chips have only one alarm signal. | |
323 | */ | |
324 | static void ds1307_work(struct work_struct *work) | |
325 | { | |
326 | struct ds1307 *ds1307; | |
327 | struct i2c_client *client; | |
328 | struct mutex *lock; | |
329 | int stat, control; | |
330 | ||
331 | ds1307 = container_of(work, struct ds1307, work); | |
332 | client = ds1307->client; | |
333 | lock = &ds1307->rtc->ops_lock; | |
334 | ||
335 | mutex_lock(lock); | |
336 | stat = i2c_smbus_read_byte_data(client, DS1337_REG_STATUS); | |
337 | if (stat < 0) | |
338 | goto out; | |
339 | ||
340 | if (stat & DS1337_BIT_A1I) { | |
341 | stat &= ~DS1337_BIT_A1I; | |
342 | i2c_smbus_write_byte_data(client, DS1337_REG_STATUS, stat); | |
343 | ||
344 | control = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL); | |
345 | if (control < 0) | |
346 | goto out; | |
347 | ||
348 | control &= ~DS1337_BIT_A1IE; | |
349 | i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, control); | |
350 | ||
cb49a5e9 | 351 | rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); |
cb49a5e9 RG |
352 | } |
353 | ||
354 | out: | |
355 | if (test_bit(HAS_ALARM, &ds1307->flags)) | |
356 | enable_irq(client->irq); | |
357 | mutex_unlock(lock); | |
358 | } | |
359 | ||
360 | static irqreturn_t ds1307_irq(int irq, void *dev_id) | |
361 | { | |
362 | struct i2c_client *client = dev_id; | |
363 | struct ds1307 *ds1307 = i2c_get_clientdata(client); | |
364 | ||
365 | disable_irq_nosync(irq); | |
366 | schedule_work(&ds1307->work); | |
367 | return IRQ_HANDLED; | |
368 | } | |
369 | ||
370 | /*----------------------------------------------------------------------*/ | |
371 | ||
1abb0dc9 DB |
372 | static int ds1307_get_time(struct device *dev, struct rtc_time *t) |
373 | { | |
374 | struct ds1307 *ds1307 = dev_get_drvdata(dev); | |
375 | int tmp; | |
376 | ||
045e0e85 | 377 | /* read the RTC date and time registers all at once */ |
30e7b039 | 378 | tmp = ds1307->read_block_data(ds1307->client, |
33df2ee1 | 379 | ds1307->offset, 7, ds1307->regs); |
fed40b73 | 380 | if (tmp != 7) { |
1abb0dc9 DB |
381 | dev_err(dev, "%s error %d\n", "read", tmp); |
382 | return -EIO; | |
383 | } | |
384 | ||
01a4ca16 | 385 | dev_dbg(dev, "%s: %7ph\n", "read", ds1307->regs); |
1abb0dc9 | 386 | |
fe20ba70 AB |
387 | t->tm_sec = bcd2bin(ds1307->regs[DS1307_REG_SECS] & 0x7f); |
388 | t->tm_min = bcd2bin(ds1307->regs[DS1307_REG_MIN] & 0x7f); | |
1abb0dc9 | 389 | tmp = ds1307->regs[DS1307_REG_HOUR] & 0x3f; |
fe20ba70 AB |
390 | t->tm_hour = bcd2bin(tmp); |
391 | t->tm_wday = bcd2bin(ds1307->regs[DS1307_REG_WDAY] & 0x07) - 1; | |
392 | t->tm_mday = bcd2bin(ds1307->regs[DS1307_REG_MDAY] & 0x3f); | |
1abb0dc9 | 393 | tmp = ds1307->regs[DS1307_REG_MONTH] & 0x1f; |
fe20ba70 | 394 | t->tm_mon = bcd2bin(tmp) - 1; |
1abb0dc9 DB |
395 | |
396 | /* assume 20YY not 19YY, and ignore DS1337_BIT_CENTURY */ | |
fe20ba70 | 397 | t->tm_year = bcd2bin(ds1307->regs[DS1307_REG_YEAR]) + 100; |
1abb0dc9 DB |
398 | |
399 | dev_dbg(dev, "%s secs=%d, mins=%d, " | |
400 | "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", | |
401 | "read", t->tm_sec, t->tm_min, | |
402 | t->tm_hour, t->tm_mday, | |
403 | t->tm_mon, t->tm_year, t->tm_wday); | |
404 | ||
045e0e85 DB |
405 | /* initial clock setting can be undefined */ |
406 | return rtc_valid_tm(t); | |
1abb0dc9 DB |
407 | } |
408 | ||
409 | static int ds1307_set_time(struct device *dev, struct rtc_time *t) | |
410 | { | |
411 | struct ds1307 *ds1307 = dev_get_drvdata(dev); | |
412 | int result; | |
413 | int tmp; | |
414 | u8 *buf = ds1307->regs; | |
415 | ||
416 | dev_dbg(dev, "%s secs=%d, mins=%d, " | |
417 | "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", | |
11966adc JG |
418 | "write", t->tm_sec, t->tm_min, |
419 | t->tm_hour, t->tm_mday, | |
420 | t->tm_mon, t->tm_year, t->tm_wday); | |
1abb0dc9 | 421 | |
fe20ba70 AB |
422 | buf[DS1307_REG_SECS] = bin2bcd(t->tm_sec); |
423 | buf[DS1307_REG_MIN] = bin2bcd(t->tm_min); | |
424 | buf[DS1307_REG_HOUR] = bin2bcd(t->tm_hour); | |
425 | buf[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1); | |
426 | buf[DS1307_REG_MDAY] = bin2bcd(t->tm_mday); | |
427 | buf[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1); | |
1abb0dc9 DB |
428 | |
429 | /* assume 20YY not 19YY */ | |
430 | tmp = t->tm_year - 100; | |
fe20ba70 | 431 | buf[DS1307_REG_YEAR] = bin2bcd(tmp); |
1abb0dc9 | 432 | |
be5f59f4 RG |
433 | switch (ds1307->type) { |
434 | case ds_1337: | |
435 | case ds_1339: | |
97f902b7 | 436 | case ds_3231: |
1abb0dc9 | 437 | buf[DS1307_REG_MONTH] |= DS1337_BIT_CENTURY; |
be5f59f4 RG |
438 | break; |
439 | case ds_1340: | |
1abb0dc9 DB |
440 | buf[DS1307_REG_HOUR] |= DS1340_BIT_CENTURY_EN |
441 | | DS1340_BIT_CENTURY; | |
be5f59f4 | 442 | break; |
f4199f85 | 443 | case mcp794xx: |
40ce972d DA |
444 | /* |
445 | * these bits were cleared when preparing the date/time | |
446 | * values and need to be set again before writing the | |
447 | * buffer out to the device. | |
448 | */ | |
f4199f85 TN |
449 | buf[DS1307_REG_SECS] |= MCP794XX_BIT_ST; |
450 | buf[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN; | |
43fcb815 | 451 | break; |
be5f59f4 RG |
452 | default: |
453 | break; | |
454 | } | |
1abb0dc9 | 455 | |
01a4ca16 | 456 | dev_dbg(dev, "%s: %7ph\n", "write", buf); |
1abb0dc9 | 457 | |
33df2ee1 JT |
458 | result = ds1307->write_block_data(ds1307->client, |
459 | ds1307->offset, 7, buf); | |
fed40b73 BS |
460 | if (result < 0) { |
461 | dev_err(dev, "%s error %d\n", "write", result); | |
462 | return result; | |
1abb0dc9 DB |
463 | } |
464 | return 0; | |
465 | } | |
466 | ||
74d88eb2 | 467 | static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t) |
cb49a5e9 RG |
468 | { |
469 | struct i2c_client *client = to_i2c_client(dev); | |
470 | struct ds1307 *ds1307 = i2c_get_clientdata(client); | |
471 | int ret; | |
472 | ||
473 | if (!test_bit(HAS_ALARM, &ds1307->flags)) | |
474 | return -EINVAL; | |
475 | ||
476 | /* read all ALARM1, ALARM2, and status registers at once */ | |
30e7b039 | 477 | ret = ds1307->read_block_data(client, |
fed40b73 BS |
478 | DS1339_REG_ALARM1_SECS, 9, ds1307->regs); |
479 | if (ret != 9) { | |
cb49a5e9 RG |
480 | dev_err(dev, "%s error %d\n", "alarm read", ret); |
481 | return -EIO; | |
482 | } | |
483 | ||
484 | dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n", | |
485 | "alarm read", | |
486 | ds1307->regs[0], ds1307->regs[1], | |
487 | ds1307->regs[2], ds1307->regs[3], | |
488 | ds1307->regs[4], ds1307->regs[5], | |
489 | ds1307->regs[6], ds1307->regs[7], | |
490 | ds1307->regs[8]); | |
491 | ||
40ce972d DA |
492 | /* |
493 | * report alarm time (ALARM1); assume 24 hour and day-of-month modes, | |
cb49a5e9 RG |
494 | * and that all four fields are checked matches |
495 | */ | |
496 | t->time.tm_sec = bcd2bin(ds1307->regs[0] & 0x7f); | |
497 | t->time.tm_min = bcd2bin(ds1307->regs[1] & 0x7f); | |
498 | t->time.tm_hour = bcd2bin(ds1307->regs[2] & 0x3f); | |
499 | t->time.tm_mday = bcd2bin(ds1307->regs[3] & 0x3f); | |
500 | t->time.tm_mon = -1; | |
501 | t->time.tm_year = -1; | |
502 | t->time.tm_wday = -1; | |
503 | t->time.tm_yday = -1; | |
504 | t->time.tm_isdst = -1; | |
505 | ||
506 | /* ... and status */ | |
507 | t->enabled = !!(ds1307->regs[7] & DS1337_BIT_A1IE); | |
508 | t->pending = !!(ds1307->regs[8] & DS1337_BIT_A1I); | |
509 | ||
510 | dev_dbg(dev, "%s secs=%d, mins=%d, " | |
511 | "hours=%d, mday=%d, enabled=%d, pending=%d\n", | |
512 | "alarm read", t->time.tm_sec, t->time.tm_min, | |
513 | t->time.tm_hour, t->time.tm_mday, | |
514 | t->enabled, t->pending); | |
515 | ||
516 | return 0; | |
517 | } | |
518 | ||
74d88eb2 | 519 | static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t) |
cb49a5e9 | 520 | { |
40ce972d | 521 | struct i2c_client *client = to_i2c_client(dev); |
cb49a5e9 RG |
522 | struct ds1307 *ds1307 = i2c_get_clientdata(client); |
523 | unsigned char *buf = ds1307->regs; | |
524 | u8 control, status; | |
525 | int ret; | |
526 | ||
527 | if (!test_bit(HAS_ALARM, &ds1307->flags)) | |
528 | return -EINVAL; | |
529 | ||
530 | dev_dbg(dev, "%s secs=%d, mins=%d, " | |
531 | "hours=%d, mday=%d, enabled=%d, pending=%d\n", | |
532 | "alarm set", t->time.tm_sec, t->time.tm_min, | |
533 | t->time.tm_hour, t->time.tm_mday, | |
534 | t->enabled, t->pending); | |
535 | ||
536 | /* read current status of both alarms and the chip */ | |
30e7b039 | 537 | ret = ds1307->read_block_data(client, |
fed40b73 BS |
538 | DS1339_REG_ALARM1_SECS, 9, buf); |
539 | if (ret != 9) { | |
cb49a5e9 RG |
540 | dev_err(dev, "%s error %d\n", "alarm write", ret); |
541 | return -EIO; | |
542 | } | |
543 | control = ds1307->regs[7]; | |
544 | status = ds1307->regs[8]; | |
545 | ||
546 | dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n", | |
547 | "alarm set (old status)", | |
548 | ds1307->regs[0], ds1307->regs[1], | |
549 | ds1307->regs[2], ds1307->regs[3], | |
550 | ds1307->regs[4], ds1307->regs[5], | |
551 | ds1307->regs[6], control, status); | |
552 | ||
553 | /* set ALARM1, using 24 hour and day-of-month modes */ | |
cb49a5e9 RG |
554 | buf[0] = bin2bcd(t->time.tm_sec); |
555 | buf[1] = bin2bcd(t->time.tm_min); | |
556 | buf[2] = bin2bcd(t->time.tm_hour); | |
557 | buf[3] = bin2bcd(t->time.tm_mday); | |
558 | ||
559 | /* set ALARM2 to non-garbage */ | |
560 | buf[4] = 0; | |
561 | buf[5] = 0; | |
562 | buf[6] = 0; | |
563 | ||
564 | /* optionally enable ALARM1 */ | |
565 | buf[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE); | |
566 | if (t->enabled) { | |
567 | dev_dbg(dev, "alarm IRQ armed\n"); | |
568 | buf[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */ | |
569 | } | |
570 | buf[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I); | |
571 | ||
30e7b039 | 572 | ret = ds1307->write_block_data(client, |
fed40b73 BS |
573 | DS1339_REG_ALARM1_SECS, 9, buf); |
574 | if (ret < 0) { | |
cb49a5e9 | 575 | dev_err(dev, "can't set alarm time\n"); |
fed40b73 | 576 | return ret; |
cb49a5e9 RG |
577 | } |
578 | ||
579 | return 0; | |
580 | } | |
581 | ||
16380c15 | 582 | static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled) |
cb49a5e9 RG |
583 | { |
584 | struct i2c_client *client = to_i2c_client(dev); | |
585 | struct ds1307 *ds1307 = i2c_get_clientdata(client); | |
586 | int ret; | |
587 | ||
16380c15 JS |
588 | if (!test_bit(HAS_ALARM, &ds1307->flags)) |
589 | return -ENOTTY; | |
cb49a5e9 | 590 | |
16380c15 JS |
591 | ret = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL); |
592 | if (ret < 0) | |
593 | return ret; | |
cb49a5e9 | 594 | |
16380c15 | 595 | if (enabled) |
cb49a5e9 | 596 | ret |= DS1337_BIT_A1IE; |
16380c15 JS |
597 | else |
598 | ret &= ~DS1337_BIT_A1IE; | |
cb49a5e9 | 599 | |
16380c15 JS |
600 | ret = i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, ret); |
601 | if (ret < 0) | |
602 | return ret; | |
cb49a5e9 RG |
603 | |
604 | return 0; | |
605 | } | |
606 | ||
ff8371ac | 607 | static const struct rtc_class_ops ds13xx_rtc_ops = { |
1abb0dc9 DB |
608 | .read_time = ds1307_get_time, |
609 | .set_time = ds1307_set_time, | |
74d88eb2 JR |
610 | .read_alarm = ds1337_read_alarm, |
611 | .set_alarm = ds1337_set_alarm, | |
16380c15 | 612 | .alarm_irq_enable = ds1307_alarm_irq_enable, |
1abb0dc9 DB |
613 | }; |
614 | ||
682d73f6 DB |
615 | /*----------------------------------------------------------------------*/ |
616 | ||
1d1945d2 | 617 | /* |
f4199f85 | 618 | * Alarm support for mcp794xx devices. |
1d1945d2 SG |
619 | */ |
620 | ||
f4199f85 TN |
621 | #define MCP794XX_REG_CONTROL 0x07 |
622 | # define MCP794XX_BIT_ALM0_EN 0x10 | |
623 | # define MCP794XX_BIT_ALM1_EN 0x20 | |
624 | #define MCP794XX_REG_ALARM0_BASE 0x0a | |
625 | #define MCP794XX_REG_ALARM0_CTRL 0x0d | |
626 | #define MCP794XX_REG_ALARM1_BASE 0x11 | |
627 | #define MCP794XX_REG_ALARM1_CTRL 0x14 | |
628 | # define MCP794XX_BIT_ALMX_IF (1 << 3) | |
629 | # define MCP794XX_BIT_ALMX_C0 (1 << 4) | |
630 | # define MCP794XX_BIT_ALMX_C1 (1 << 5) | |
631 | # define MCP794XX_BIT_ALMX_C2 (1 << 6) | |
632 | # define MCP794XX_BIT_ALMX_POL (1 << 7) | |
633 | # define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \ | |
634 | MCP794XX_BIT_ALMX_C1 | \ | |
635 | MCP794XX_BIT_ALMX_C2) | |
636 | ||
637 | static void mcp794xx_work(struct work_struct *work) | |
1d1945d2 SG |
638 | { |
639 | struct ds1307 *ds1307 = container_of(work, struct ds1307, work); | |
640 | struct i2c_client *client = ds1307->client; | |
641 | int reg, ret; | |
642 | ||
643 | mutex_lock(&ds1307->rtc->ops_lock); | |
644 | ||
645 | /* Check and clear alarm 0 interrupt flag. */ | |
f4199f85 | 646 | reg = i2c_smbus_read_byte_data(client, MCP794XX_REG_ALARM0_CTRL); |
1d1945d2 SG |
647 | if (reg < 0) |
648 | goto out; | |
f4199f85 | 649 | if (!(reg & MCP794XX_BIT_ALMX_IF)) |
1d1945d2 | 650 | goto out; |
f4199f85 TN |
651 | reg &= ~MCP794XX_BIT_ALMX_IF; |
652 | ret = i2c_smbus_write_byte_data(client, MCP794XX_REG_ALARM0_CTRL, reg); | |
1d1945d2 SG |
653 | if (ret < 0) |
654 | goto out; | |
655 | ||
656 | /* Disable alarm 0. */ | |
f4199f85 | 657 | reg = i2c_smbus_read_byte_data(client, MCP794XX_REG_CONTROL); |
1d1945d2 SG |
658 | if (reg < 0) |
659 | goto out; | |
f4199f85 TN |
660 | reg &= ~MCP794XX_BIT_ALM0_EN; |
661 | ret = i2c_smbus_write_byte_data(client, MCP794XX_REG_CONTROL, reg); | |
1d1945d2 SG |
662 | if (ret < 0) |
663 | goto out; | |
664 | ||
665 | rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); | |
666 | ||
667 | out: | |
668 | if (test_bit(HAS_ALARM, &ds1307->flags)) | |
669 | enable_irq(client->irq); | |
670 | mutex_unlock(&ds1307->rtc->ops_lock); | |
671 | } | |
672 | ||
f4199f85 | 673 | static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t) |
1d1945d2 SG |
674 | { |
675 | struct i2c_client *client = to_i2c_client(dev); | |
676 | struct ds1307 *ds1307 = i2c_get_clientdata(client); | |
677 | u8 *regs = ds1307->regs; | |
678 | int ret; | |
679 | ||
680 | if (!test_bit(HAS_ALARM, &ds1307->flags)) | |
681 | return -EINVAL; | |
682 | ||
683 | /* Read control and alarm 0 registers. */ | |
f4199f85 | 684 | ret = ds1307->read_block_data(client, MCP794XX_REG_CONTROL, 10, regs); |
1d1945d2 SG |
685 | if (ret < 0) |
686 | return ret; | |
687 | ||
f4199f85 | 688 | t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN); |
1d1945d2 SG |
689 | |
690 | /* Report alarm 0 time assuming 24-hour and day-of-month modes. */ | |
691 | t->time.tm_sec = bcd2bin(ds1307->regs[3] & 0x7f); | |
692 | t->time.tm_min = bcd2bin(ds1307->regs[4] & 0x7f); | |
693 | t->time.tm_hour = bcd2bin(ds1307->regs[5] & 0x3f); | |
694 | t->time.tm_wday = bcd2bin(ds1307->regs[6] & 0x7) - 1; | |
695 | t->time.tm_mday = bcd2bin(ds1307->regs[7] & 0x3f); | |
696 | t->time.tm_mon = bcd2bin(ds1307->regs[8] & 0x1f) - 1; | |
697 | t->time.tm_year = -1; | |
698 | t->time.tm_yday = -1; | |
699 | t->time.tm_isdst = -1; | |
700 | ||
701 | dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d " | |
702 | "enabled=%d polarity=%d irq=%d match=%d\n", __func__, | |
703 | t->time.tm_sec, t->time.tm_min, t->time.tm_hour, | |
704 | t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled, | |
f4199f85 TN |
705 | !!(ds1307->regs[6] & MCP794XX_BIT_ALMX_POL), |
706 | !!(ds1307->regs[6] & MCP794XX_BIT_ALMX_IF), | |
707 | (ds1307->regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4); | |
1d1945d2 SG |
708 | |
709 | return 0; | |
710 | } | |
711 | ||
f4199f85 | 712 | static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t) |
1d1945d2 SG |
713 | { |
714 | struct i2c_client *client = to_i2c_client(dev); | |
715 | struct ds1307 *ds1307 = i2c_get_clientdata(client); | |
716 | unsigned char *regs = ds1307->regs; | |
717 | int ret; | |
718 | ||
719 | if (!test_bit(HAS_ALARM, &ds1307->flags)) | |
720 | return -EINVAL; | |
721 | ||
722 | dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d " | |
723 | "enabled=%d pending=%d\n", __func__, | |
724 | t->time.tm_sec, t->time.tm_min, t->time.tm_hour, | |
725 | t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, | |
726 | t->enabled, t->pending); | |
727 | ||
728 | /* Read control and alarm 0 registers. */ | |
f4199f85 | 729 | ret = ds1307->read_block_data(client, MCP794XX_REG_CONTROL, 10, regs); |
1d1945d2 SG |
730 | if (ret < 0) |
731 | return ret; | |
732 | ||
733 | /* Set alarm 0, using 24-hour and day-of-month modes. */ | |
734 | regs[3] = bin2bcd(t->time.tm_sec); | |
735 | regs[4] = bin2bcd(t->time.tm_min); | |
736 | regs[5] = bin2bcd(t->time.tm_hour); | |
737 | regs[6] = bin2bcd(t->time.tm_wday) + 1; | |
738 | regs[7] = bin2bcd(t->time.tm_mday); | |
739 | regs[8] = bin2bcd(t->time.tm_mon) + 1; | |
740 | ||
741 | /* Clear the alarm 0 interrupt flag. */ | |
f4199f85 | 742 | regs[6] &= ~MCP794XX_BIT_ALMX_IF; |
1d1945d2 | 743 | /* Set alarm match: second, minute, hour, day, date, month. */ |
f4199f85 | 744 | regs[6] |= MCP794XX_MSK_ALMX_MATCH; |
1d1945d2 SG |
745 | |
746 | if (t->enabled) | |
f4199f85 | 747 | regs[0] |= MCP794XX_BIT_ALM0_EN; |
1d1945d2 | 748 | else |
f4199f85 | 749 | regs[0] &= ~MCP794XX_BIT_ALM0_EN; |
1d1945d2 | 750 | |
f4199f85 | 751 | ret = ds1307->write_block_data(client, MCP794XX_REG_CONTROL, 10, regs); |
1d1945d2 SG |
752 | if (ret < 0) |
753 | return ret; | |
754 | ||
755 | return 0; | |
756 | } | |
757 | ||
f4199f85 | 758 | static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled) |
1d1945d2 SG |
759 | { |
760 | struct i2c_client *client = to_i2c_client(dev); | |
761 | struct ds1307 *ds1307 = i2c_get_clientdata(client); | |
762 | int reg; | |
763 | ||
764 | if (!test_bit(HAS_ALARM, &ds1307->flags)) | |
765 | return -EINVAL; | |
766 | ||
f4199f85 | 767 | reg = i2c_smbus_read_byte_data(client, MCP794XX_REG_CONTROL); |
1d1945d2 SG |
768 | if (reg < 0) |
769 | return reg; | |
770 | ||
771 | if (enabled) | |
f4199f85 | 772 | reg |= MCP794XX_BIT_ALM0_EN; |
1d1945d2 | 773 | else |
f4199f85 | 774 | reg &= ~MCP794XX_BIT_ALM0_EN; |
1d1945d2 | 775 | |
f4199f85 | 776 | return i2c_smbus_write_byte_data(client, MCP794XX_REG_CONTROL, reg); |
1d1945d2 SG |
777 | } |
778 | ||
f4199f85 | 779 | static const struct rtc_class_ops mcp794xx_rtc_ops = { |
1d1945d2 SG |
780 | .read_time = ds1307_get_time, |
781 | .set_time = ds1307_set_time, | |
f4199f85 TN |
782 | .read_alarm = mcp794xx_read_alarm, |
783 | .set_alarm = mcp794xx_set_alarm, | |
784 | .alarm_irq_enable = mcp794xx_alarm_irq_enable, | |
1d1945d2 SG |
785 | }; |
786 | ||
787 | /*----------------------------------------------------------------------*/ | |
788 | ||
682d73f6 | 789 | static ssize_t |
2c3c8bea CW |
790 | ds1307_nvram_read(struct file *filp, struct kobject *kobj, |
791 | struct bin_attribute *attr, | |
682d73f6 DB |
792 | char *buf, loff_t off, size_t count) |
793 | { | |
794 | struct i2c_client *client; | |
795 | struct ds1307 *ds1307; | |
682d73f6 DB |
796 | int result; |
797 | ||
fcd8db00 | 798 | client = kobj_to_i2c_client(kobj); |
682d73f6 DB |
799 | ds1307 = i2c_get_clientdata(client); |
800 | ||
9eab0a78 | 801 | if (unlikely(off >= ds1307->nvram->size)) |
682d73f6 | 802 | return 0; |
9eab0a78 AB |
803 | if ((off + count) > ds1307->nvram->size) |
804 | count = ds1307->nvram->size - off; | |
682d73f6 DB |
805 | if (unlikely(!count)) |
806 | return count; | |
807 | ||
9eab0a78 AB |
808 | result = ds1307->read_block_data(client, ds1307->nvram_offset + off, |
809 | count, buf); | |
fed40b73 | 810 | if (result < 0) |
682d73f6 | 811 | dev_err(&client->dev, "%s error %d\n", "nvram read", result); |
fed40b73 | 812 | return result; |
682d73f6 DB |
813 | } |
814 | ||
815 | static ssize_t | |
2c3c8bea CW |
816 | ds1307_nvram_write(struct file *filp, struct kobject *kobj, |
817 | struct bin_attribute *attr, | |
682d73f6 DB |
818 | char *buf, loff_t off, size_t count) |
819 | { | |
820 | struct i2c_client *client; | |
30e7b039 | 821 | struct ds1307 *ds1307; |
fed40b73 | 822 | int result; |
682d73f6 | 823 | |
fcd8db00 | 824 | client = kobj_to_i2c_client(kobj); |
30e7b039 | 825 | ds1307 = i2c_get_clientdata(client); |
682d73f6 | 826 | |
9eab0a78 | 827 | if (unlikely(off >= ds1307->nvram->size)) |
682d73f6 | 828 | return -EFBIG; |
9eab0a78 AB |
829 | if ((off + count) > ds1307->nvram->size) |
830 | count = ds1307->nvram->size - off; | |
682d73f6 DB |
831 | if (unlikely(!count)) |
832 | return count; | |
833 | ||
9eab0a78 AB |
834 | result = ds1307->write_block_data(client, ds1307->nvram_offset + off, |
835 | count, buf); | |
fed40b73 BS |
836 | if (result < 0) { |
837 | dev_err(&client->dev, "%s error %d\n", "nvram write", result); | |
838 | return result; | |
839 | } | |
840 | return count; | |
682d73f6 DB |
841 | } |
842 | ||
33b04b7b | 843 | |
682d73f6 DB |
844 | /*----------------------------------------------------------------------*/ |
845 | ||
33b04b7b MV |
846 | static u8 do_trickle_setup_ds1339(struct i2c_client *client, |
847 | uint32_t ohms, bool diode) | |
848 | { | |
849 | u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE : | |
850 | DS1307_TRICKLE_CHARGER_NO_DIODE; | |
851 | ||
852 | switch (ohms) { | |
853 | case 250: | |
854 | setup |= DS1307_TRICKLE_CHARGER_250_OHM; | |
855 | break; | |
856 | case 2000: | |
857 | setup |= DS1307_TRICKLE_CHARGER_2K_OHM; | |
858 | break; | |
859 | case 4000: | |
860 | setup |= DS1307_TRICKLE_CHARGER_4K_OHM; | |
861 | break; | |
862 | default: | |
863 | dev_warn(&client->dev, | |
864 | "Unsupported ohm value %u in dt\n", ohms); | |
865 | return 0; | |
866 | } | |
867 | return setup; | |
868 | } | |
869 | ||
870 | static void ds1307_trickle_of_init(struct i2c_client *client, | |
871 | struct chip_desc *chip) | |
872 | { | |
873 | uint32_t ohms = 0; | |
874 | bool diode = true; | |
875 | ||
876 | if (!chip->do_trickle_setup) | |
877 | goto out; | |
878 | if (of_property_read_u32(client->dev.of_node, "trickle-resistor-ohms" , &ohms)) | |
879 | goto out; | |
880 | if (of_property_read_bool(client->dev.of_node, "trickle-diode-disable")) | |
881 | diode = false; | |
882 | chip->trickle_charger_setup = chip->do_trickle_setup(client, | |
883 | ohms, diode); | |
884 | out: | |
885 | return; | |
886 | } | |
887 | ||
5a167f45 GKH |
888 | static int ds1307_probe(struct i2c_client *client, |
889 | const struct i2c_device_id *id) | |
1abb0dc9 DB |
890 | { |
891 | struct ds1307 *ds1307; | |
892 | int err = -ENODEV; | |
1abb0dc9 | 893 | int tmp; |
33b04b7b | 894 | struct chip_desc *chip = &chips[id->driver_data]; |
c065f35c | 895 | struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); |
c8b18da7 | 896 | bool want_irq = false; |
fed40b73 | 897 | unsigned char *buf; |
01ce893d | 898 | struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev); |
97f902b7 WS |
899 | static const int bbsqi_bitpos[] = { |
900 | [ds_1337] = 0, | |
901 | [ds_1339] = DS1339_BIT_BBSQI, | |
902 | [ds_3231] = DS3231_BIT_BBSQW, | |
903 | }; | |
1d1945d2 | 904 | const struct rtc_class_ops *rtc_ops = &ds13xx_rtc_ops; |
1abb0dc9 | 905 | |
30e7b039 ES |
906 | if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA) |
907 | && !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) | |
c065f35c DB |
908 | return -EIO; |
909 | ||
edca66d2 | 910 | ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL); |
40ce972d | 911 | if (!ds1307) |
c065f35c | 912 | return -ENOMEM; |
045e0e85 | 913 | |
1abb0dc9 | 914 | i2c_set_clientdata(client, ds1307); |
33df2ee1 JT |
915 | |
916 | ds1307->client = client; | |
917 | ds1307->type = id->driver_data; | |
33df2ee1 | 918 | |
33b04b7b MV |
919 | if (!pdata && client->dev.of_node) |
920 | ds1307_trickle_of_init(client, chip); | |
921 | else if (pdata && pdata->trickle_charger_setup) | |
922 | chip->trickle_charger_setup = pdata->trickle_charger_setup; | |
923 | ||
924 | if (chip->trickle_charger_setup && chip->trickle_charger_reg) { | |
925 | dev_dbg(&client->dev, "writing trickle charger info 0x%x to 0x%x\n", | |
926 | DS13XX_TRICKLE_CHARGER_MAGIC | chip->trickle_charger_setup, | |
927 | chip->trickle_charger_reg); | |
eb86c306 | 928 | i2c_smbus_write_byte_data(client, chip->trickle_charger_reg, |
33b04b7b MV |
929 | DS13XX_TRICKLE_CHARGER_MAGIC | |
930 | chip->trickle_charger_setup); | |
931 | } | |
eb86c306 | 932 | |
fed40b73 | 933 | buf = ds1307->regs; |
30e7b039 | 934 | if (i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) { |
bc48b902 BA |
935 | ds1307->read_block_data = ds1307_native_smbus_read_block_data; |
936 | ds1307->write_block_data = ds1307_native_smbus_write_block_data; | |
30e7b039 ES |
937 | } else { |
938 | ds1307->read_block_data = ds1307_read_block_data; | |
939 | ds1307->write_block_data = ds1307_write_block_data; | |
940 | } | |
045e0e85 DB |
941 | |
942 | switch (ds1307->type) { | |
943 | case ds_1337: | |
944 | case ds_1339: | |
97f902b7 | 945 | case ds_3231: |
be5f59f4 | 946 | /* get registers that the "rtc" read below won't read... */ |
30e7b039 | 947 | tmp = ds1307->read_block_data(ds1307->client, |
fed40b73 | 948 | DS1337_REG_CONTROL, 2, buf); |
1abb0dc9 | 949 | if (tmp != 2) { |
6df80e21 | 950 | dev_dbg(&client->dev, "read error %d\n", tmp); |
1abb0dc9 | 951 | err = -EIO; |
edca66d2 | 952 | goto exit; |
1abb0dc9 DB |
953 | } |
954 | ||
be5f59f4 RG |
955 | /* oscillator off? turn it on, so clock can tick. */ |
956 | if (ds1307->regs[0] & DS1337_BIT_nEOSC) | |
cb49a5e9 RG |
957 | ds1307->regs[0] &= ~DS1337_BIT_nEOSC; |
958 | ||
40ce972d DA |
959 | /* |
960 | * Using IRQ? Disable the square wave and both alarms. | |
97f902b7 WS |
961 | * For some variants, be sure alarms can trigger when we're |
962 | * running on Vbackup (BBSQI/BBSQW) | |
cb49a5e9 | 963 | */ |
b24a7267 WS |
964 | if (ds1307->client->irq > 0 && chip->alarm) { |
965 | INIT_WORK(&ds1307->work, ds1307_work); | |
966 | ||
97f902b7 WS |
967 | ds1307->regs[0] |= DS1337_BIT_INTCN |
968 | | bbsqi_bitpos[ds1307->type]; | |
cb49a5e9 | 969 | ds1307->regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE); |
b24a7267 WS |
970 | |
971 | want_irq = true; | |
cb49a5e9 RG |
972 | } |
973 | ||
974 | i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, | |
975 | ds1307->regs[0]); | |
be5f59f4 RG |
976 | |
977 | /* oscillator fault? clear flag, and warn */ | |
978 | if (ds1307->regs[1] & DS1337_BIT_OSF) { | |
979 | i2c_smbus_write_byte_data(client, DS1337_REG_STATUS, | |
980 | ds1307->regs[1] & ~DS1337_BIT_OSF); | |
981 | dev_warn(&client->dev, "SET TIME!\n"); | |
1abb0dc9 | 982 | } |
045e0e85 | 983 | break; |
a2166858 MF |
984 | |
985 | case rx_8025: | |
986 | tmp = i2c_smbus_read_i2c_block_data(ds1307->client, | |
987 | RX8025_REG_CTRL1 << 4 | 0x08, 2, buf); | |
988 | if (tmp != 2) { | |
6df80e21 | 989 | dev_dbg(&client->dev, "read error %d\n", tmp); |
a2166858 | 990 | err = -EIO; |
edca66d2 | 991 | goto exit; |
a2166858 MF |
992 | } |
993 | ||
994 | /* oscillator off? turn it on, so clock can tick. */ | |
995 | if (!(ds1307->regs[1] & RX8025_BIT_XST)) { | |
996 | ds1307->regs[1] |= RX8025_BIT_XST; | |
997 | i2c_smbus_write_byte_data(client, | |
998 | RX8025_REG_CTRL2 << 4 | 0x08, | |
999 | ds1307->regs[1]); | |
1000 | dev_warn(&client->dev, | |
1001 | "oscillator stop detected - SET TIME!\n"); | |
1002 | } | |
1003 | ||
1004 | if (ds1307->regs[1] & RX8025_BIT_PON) { | |
1005 | ds1307->regs[1] &= ~RX8025_BIT_PON; | |
1006 | i2c_smbus_write_byte_data(client, | |
1007 | RX8025_REG_CTRL2 << 4 | 0x08, | |
1008 | ds1307->regs[1]); | |
1009 | dev_warn(&client->dev, "power-on detected\n"); | |
1010 | } | |
1011 | ||
1012 | if (ds1307->regs[1] & RX8025_BIT_VDET) { | |
1013 | ds1307->regs[1] &= ~RX8025_BIT_VDET; | |
1014 | i2c_smbus_write_byte_data(client, | |
1015 | RX8025_REG_CTRL2 << 4 | 0x08, | |
1016 | ds1307->regs[1]); | |
1017 | dev_warn(&client->dev, "voltage drop detected\n"); | |
1018 | } | |
1019 | ||
1020 | /* make sure we are running in 24hour mode */ | |
1021 | if (!(ds1307->regs[0] & RX8025_BIT_2412)) { | |
1022 | u8 hour; | |
1023 | ||
1024 | /* switch to 24 hour mode */ | |
1025 | i2c_smbus_write_byte_data(client, | |
1026 | RX8025_REG_CTRL1 << 4 | 0x08, | |
1027 | ds1307->regs[0] | | |
1028 | RX8025_BIT_2412); | |
1029 | ||
1030 | tmp = i2c_smbus_read_i2c_block_data(ds1307->client, | |
1031 | RX8025_REG_CTRL1 << 4 | 0x08, 2, buf); | |
1032 | if (tmp != 2) { | |
6df80e21 | 1033 | dev_dbg(&client->dev, "read error %d\n", tmp); |
a2166858 | 1034 | err = -EIO; |
edca66d2 | 1035 | goto exit; |
a2166858 MF |
1036 | } |
1037 | ||
1038 | /* correct hour */ | |
1039 | hour = bcd2bin(ds1307->regs[DS1307_REG_HOUR]); | |
1040 | if (hour == 12) | |
1041 | hour = 0; | |
1042 | if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM) | |
1043 | hour += 12; | |
1044 | ||
1045 | i2c_smbus_write_byte_data(client, | |
1046 | DS1307_REG_HOUR << 4 | 0x08, | |
1047 | hour); | |
1048 | } | |
1049 | break; | |
33df2ee1 JT |
1050 | case ds_1388: |
1051 | ds1307->offset = 1; /* Seconds starts at 1 */ | |
1052 | break; | |
f4199f85 TN |
1053 | case mcp794xx: |
1054 | rtc_ops = &mcp794xx_rtc_ops; | |
1d1945d2 | 1055 | if (ds1307->client->irq > 0 && chip->alarm) { |
f4199f85 | 1056 | INIT_WORK(&ds1307->work, mcp794xx_work); |
1d1945d2 SG |
1057 | want_irq = true; |
1058 | } | |
1059 | break; | |
045e0e85 DB |
1060 | default: |
1061 | break; | |
1062 | } | |
1abb0dc9 DB |
1063 | |
1064 | read_rtc: | |
1065 | /* read RTC registers */ | |
96fc3a45 | 1066 | tmp = ds1307->read_block_data(ds1307->client, ds1307->offset, 8, buf); |
fed40b73 | 1067 | if (tmp != 8) { |
6df80e21 | 1068 | dev_dbg(&client->dev, "read error %d\n", tmp); |
1abb0dc9 | 1069 | err = -EIO; |
edca66d2 | 1070 | goto exit; |
1abb0dc9 DB |
1071 | } |
1072 | ||
40ce972d DA |
1073 | /* |
1074 | * minimal sanity checking; some chips (like DS1340) don't | |
1abb0dc9 DB |
1075 | * specify the extra bits as must-be-zero, but there are |
1076 | * still a few values that are clearly out-of-range. | |
1077 | */ | |
1078 | tmp = ds1307->regs[DS1307_REG_SECS]; | |
045e0e85 DB |
1079 | switch (ds1307->type) { |
1080 | case ds_1307: | |
045e0e85 | 1081 | case m41t00: |
be5f59f4 | 1082 | /* clock halted? turn it on, so clock can tick. */ |
045e0e85 | 1083 | if (tmp & DS1307_BIT_CH) { |
be5f59f4 RG |
1084 | i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0); |
1085 | dev_warn(&client->dev, "SET TIME!\n"); | |
045e0e85 | 1086 | goto read_rtc; |
1abb0dc9 | 1087 | } |
045e0e85 | 1088 | break; |
be5f59f4 RG |
1089 | case ds_1338: |
1090 | /* clock halted? turn it on, so clock can tick. */ | |
045e0e85 | 1091 | if (tmp & DS1307_BIT_CH) |
be5f59f4 RG |
1092 | i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0); |
1093 | ||
1094 | /* oscillator fault? clear flag, and warn */ | |
1095 | if (ds1307->regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) { | |
1096 | i2c_smbus_write_byte_data(client, DS1307_REG_CONTROL, | |
bd16f9eb | 1097 | ds1307->regs[DS1307_REG_CONTROL] |
be5f59f4 RG |
1098 | & ~DS1338_BIT_OSF); |
1099 | dev_warn(&client->dev, "SET TIME!\n"); | |
1100 | goto read_rtc; | |
1101 | } | |
045e0e85 | 1102 | break; |
fcd8db00 R |
1103 | case ds_1340: |
1104 | /* clock halted? turn it on, so clock can tick. */ | |
1105 | if (tmp & DS1340_BIT_nEOSC) | |
1106 | i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0); | |
1107 | ||
1108 | tmp = i2c_smbus_read_byte_data(client, DS1340_REG_FLAG); | |
1109 | if (tmp < 0) { | |
6df80e21 | 1110 | dev_dbg(&client->dev, "read error %d\n", tmp); |
fcd8db00 | 1111 | err = -EIO; |
edca66d2 | 1112 | goto exit; |
fcd8db00 R |
1113 | } |
1114 | ||
1115 | /* oscillator fault? clear flag, and warn */ | |
1116 | if (tmp & DS1340_BIT_OSF) { | |
1117 | i2c_smbus_write_byte_data(client, DS1340_REG_FLAG, 0); | |
1118 | dev_warn(&client->dev, "SET TIME!\n"); | |
1119 | } | |
43fcb815 | 1120 | break; |
f4199f85 | 1121 | case mcp794xx: |
43fcb815 | 1122 | /* make sure that the backup battery is enabled */ |
f4199f85 | 1123 | if (!(ds1307->regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) { |
43fcb815 DA |
1124 | i2c_smbus_write_byte_data(client, DS1307_REG_WDAY, |
1125 | ds1307->regs[DS1307_REG_WDAY] | |
f4199f85 | 1126 | | MCP794XX_BIT_VBATEN); |
43fcb815 DA |
1127 | } |
1128 | ||
1129 | /* clock halted? turn it on, so clock can tick. */ | |
f4199f85 | 1130 | if (!(tmp & MCP794XX_BIT_ST)) { |
43fcb815 | 1131 | i2c_smbus_write_byte_data(client, DS1307_REG_SECS, |
f4199f85 | 1132 | MCP794XX_BIT_ST); |
43fcb815 DA |
1133 | dev_warn(&client->dev, "SET TIME!\n"); |
1134 | goto read_rtc; | |
1135 | } | |
1136 | ||
fcd8db00 | 1137 | break; |
32d322bc | 1138 | default: |
045e0e85 | 1139 | break; |
1abb0dc9 | 1140 | } |
045e0e85 | 1141 | |
1abb0dc9 | 1142 | tmp = ds1307->regs[DS1307_REG_HOUR]; |
c065f35c DB |
1143 | switch (ds1307->type) { |
1144 | case ds_1340: | |
1145 | case m41t00: | |
40ce972d DA |
1146 | /* |
1147 | * NOTE: ignores century bits; fix before deploying | |
c065f35c DB |
1148 | * systems that will run through year 2100. |
1149 | */ | |
1150 | break; | |
a2166858 MF |
1151 | case rx_8025: |
1152 | break; | |
c065f35c DB |
1153 | default: |
1154 | if (!(tmp & DS1307_BIT_12HR)) | |
1155 | break; | |
1156 | ||
40ce972d DA |
1157 | /* |
1158 | * Be sure we're in 24 hour mode. Multi-master systems | |
c065f35c DB |
1159 | * take note... |
1160 | */ | |
fe20ba70 | 1161 | tmp = bcd2bin(tmp & 0x1f); |
c065f35c DB |
1162 | if (tmp == 12) |
1163 | tmp = 0; | |
1164 | if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM) | |
1165 | tmp += 12; | |
1abb0dc9 | 1166 | i2c_smbus_write_byte_data(client, |
96fc3a45 | 1167 | ds1307->offset + DS1307_REG_HOUR, |
fe20ba70 | 1168 | bin2bcd(tmp)); |
1abb0dc9 DB |
1169 | } |
1170 | ||
5ea73514 | 1171 | device_set_wakeup_capable(&client->dev, want_irq); |
edca66d2 | 1172 | ds1307->rtc = devm_rtc_device_register(&client->dev, client->name, |
1d1945d2 | 1173 | rtc_ops, THIS_MODULE); |
1abb0dc9 | 1174 | if (IS_ERR(ds1307->rtc)) { |
4071ea25 | 1175 | return PTR_ERR(ds1307->rtc); |
1abb0dc9 DB |
1176 | } |
1177 | ||
cb49a5e9 | 1178 | if (want_irq) { |
43d15bcd | 1179 | err = request_irq(client->irq, ds1307_irq, IRQF_SHARED, |
cb49a5e9 RG |
1180 | ds1307->rtc->name, client); |
1181 | if (err) { | |
4071ea25 AZ |
1182 | client->irq = 0; |
1183 | dev_err(&client->dev, "unable to request IRQ!\n"); | |
1184 | } else { | |
26b3c01f | 1185 | |
4071ea25 AZ |
1186 | set_bit(HAS_ALARM, &ds1307->flags); |
1187 | dev_dbg(&client->dev, "got IRQ %d\n", client->irq); | |
1188 | } | |
cb49a5e9 RG |
1189 | } |
1190 | ||
9eab0a78 | 1191 | if (chip->nvram_size) { |
4071ea25 | 1192 | |
edca66d2 JH |
1193 | ds1307->nvram = devm_kzalloc(&client->dev, |
1194 | sizeof(struct bin_attribute), | |
1195 | GFP_KERNEL); | |
9eab0a78 | 1196 | if (!ds1307->nvram) { |
4071ea25 AZ |
1197 | dev_err(&client->dev, "cannot allocate memory for nvram sysfs\n"); |
1198 | } else { | |
1199 | ||
1200 | ds1307->nvram->attr.name = "nvram"; | |
1201 | ds1307->nvram->attr.mode = S_IRUGO | S_IWUSR; | |
1202 | ||
1203 | sysfs_bin_attr_init(ds1307->nvram); | |
1204 | ||
1205 | ds1307->nvram->read = ds1307_nvram_read; | |
1206 | ds1307->nvram->write = ds1307_nvram_write; | |
1207 | ds1307->nvram->size = chip->nvram_size; | |
1208 | ds1307->nvram_offset = chip->nvram_offset; | |
1209 | ||
1210 | err = sysfs_create_bin_file(&client->dev.kobj, | |
1211 | ds1307->nvram); | |
1212 | if (err) { | |
1213 | dev_err(&client->dev, | |
1214 | "unable to create sysfs file: %s\n", | |
1215 | ds1307->nvram->attr.name); | |
1216 | } else { | |
1217 | set_bit(HAS_NVRAM, &ds1307->flags); | |
1218 | dev_info(&client->dev, "%zu bytes nvram\n", | |
1219 | ds1307->nvram->size); | |
1220 | } | |
9eab0a78 | 1221 | } |
682d73f6 DB |
1222 | } |
1223 | ||
1abb0dc9 DB |
1224 | return 0; |
1225 | ||
edca66d2 | 1226 | exit: |
1abb0dc9 DB |
1227 | return err; |
1228 | } | |
1229 | ||
5a167f45 | 1230 | static int ds1307_remove(struct i2c_client *client) |
1abb0dc9 | 1231 | { |
40ce972d | 1232 | struct ds1307 *ds1307 = i2c_get_clientdata(client); |
cb49a5e9 RG |
1233 | |
1234 | if (test_and_clear_bit(HAS_ALARM, &ds1307->flags)) { | |
1235 | free_irq(client->irq, client); | |
1236 | cancel_work_sync(&ds1307->work); | |
1237 | } | |
1abb0dc9 | 1238 | |
edca66d2 | 1239 | if (test_and_clear_bit(HAS_NVRAM, &ds1307->flags)) |
9eab0a78 | 1240 | sysfs_remove_bin_file(&client->dev.kobj, ds1307->nvram); |
682d73f6 | 1241 | |
1abb0dc9 DB |
1242 | return 0; |
1243 | } | |
1244 | ||
1245 | static struct i2c_driver ds1307_driver = { | |
1246 | .driver = { | |
c065f35c | 1247 | .name = "rtc-ds1307", |
1abb0dc9 DB |
1248 | .owner = THIS_MODULE, |
1249 | }, | |
c065f35c | 1250 | .probe = ds1307_probe, |
5a167f45 | 1251 | .remove = ds1307_remove, |
3760f736 | 1252 | .id_table = ds1307_id, |
1abb0dc9 DB |
1253 | }; |
1254 | ||
0abc9201 | 1255 | module_i2c_driver(ds1307_driver); |
1abb0dc9 DB |
1256 | |
1257 | MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips"); | |
1258 | MODULE_LICENSE("GPL"); |