rtc: ds1307: refactor chip_desc table
[deliverable/linux.git] / drivers / rtc / rtc-ds1307.c
CommitLineData
1abb0dc9
DB
1/*
2 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
3 *
4 * Copyright (C) 2005 James Chapman (ds1337 core)
5 * Copyright (C) 2006 David Brownell
a2166858 6 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
1abb0dc9
DB
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/slab.h>
16#include <linux/i2c.h>
17#include <linux/string.h>
18#include <linux/rtc.h>
19#include <linux/bcd.h>
20
21
22
23/* We can't determine type by probing, but if we expect pre-Linux code
24 * to have set the chip up as a clock (turning on the oscillator and
25 * setting the date and time), Linux can ignore the non-clock features.
26 * That's a natural job for a factory or repair bench.
1abb0dc9
DB
27 */
28enum ds_type {
045e0e85
DB
29 ds_1307,
30 ds_1337,
31 ds_1338,
32 ds_1339,
33 ds_1340,
33df2ee1 34 ds_1388,
97f902b7 35 ds_3231,
045e0e85 36 m41t00,
43fcb815 37 mcp7941x,
a2166858 38 rx_8025,
32d322bc 39 last_ds_type /* always last */
1abb0dc9
DB
40 // rs5c372 too? different address...
41};
42
1abb0dc9
DB
43
44/* RTC registers don't differ much, except for the century flag */
45#define DS1307_REG_SECS 0x00 /* 00-59 */
46# define DS1307_BIT_CH 0x80
be5f59f4 47# define DS1340_BIT_nEOSC 0x80
43fcb815 48# define MCP7941X_BIT_ST 0x80
1abb0dc9
DB
49#define DS1307_REG_MIN 0x01 /* 00-59 */
50#define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
c065f35c
DB
51# define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
52# define DS1307_BIT_PM 0x20 /* in REG_HOUR */
1abb0dc9
DB
53# define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
54# define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
55#define DS1307_REG_WDAY 0x03 /* 01-07 */
43fcb815 56# define MCP7941X_BIT_VBATEN 0x08
1abb0dc9
DB
57#define DS1307_REG_MDAY 0x04 /* 01-31 */
58#define DS1307_REG_MONTH 0x05 /* 01-12 */
59# define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
60#define DS1307_REG_YEAR 0x06 /* 00-99 */
61
62/* Other registers (control, status, alarms, trickle charge, NVRAM, etc)
045e0e85
DB
63 * start at 7, and they differ a LOT. Only control and status matter for
64 * basic RTC date and time functionality; be careful using them.
1abb0dc9 65 */
045e0e85 66#define DS1307_REG_CONTROL 0x07 /* or ds1338 */
1abb0dc9 67# define DS1307_BIT_OUT 0x80
be5f59f4 68# define DS1338_BIT_OSF 0x20
1abb0dc9
DB
69# define DS1307_BIT_SQWE 0x10
70# define DS1307_BIT_RS1 0x02
71# define DS1307_BIT_RS0 0x01
72#define DS1337_REG_CONTROL 0x0e
73# define DS1337_BIT_nEOSC 0x80
cb49a5e9 74# define DS1339_BIT_BBSQI 0x20
97f902b7 75# define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
1abb0dc9
DB
76# define DS1337_BIT_RS2 0x10
77# define DS1337_BIT_RS1 0x08
78# define DS1337_BIT_INTCN 0x04
79# define DS1337_BIT_A2IE 0x02
80# define DS1337_BIT_A1IE 0x01
045e0e85
DB
81#define DS1340_REG_CONTROL 0x07
82# define DS1340_BIT_OUT 0x80
83# define DS1340_BIT_FT 0x40
84# define DS1340_BIT_CALIB_SIGN 0x20
85# define DS1340_M_CALIBRATION 0x1f
be5f59f4
RG
86#define DS1340_REG_FLAG 0x09
87# define DS1340_BIT_OSF 0x80
1abb0dc9
DB
88#define DS1337_REG_STATUS 0x0f
89# define DS1337_BIT_OSF 0x80
90# define DS1337_BIT_A2I 0x02
91# define DS1337_BIT_A1I 0x01
cb49a5e9 92#define DS1339_REG_ALARM1_SECS 0x07
1abb0dc9
DB
93#define DS1339_REG_TRICKLE 0x10
94
a2166858
MF
95#define RX8025_REG_CTRL1 0x0e
96# define RX8025_BIT_2412 0x20
97#define RX8025_REG_CTRL2 0x0f
98# define RX8025_BIT_PON 0x10
99# define RX8025_BIT_VDET 0x40
100# define RX8025_BIT_XST 0x20
1abb0dc9
DB
101
102
103struct ds1307 {
33df2ee1 104 u8 offset; /* register's offset */
cb49a5e9 105 u8 regs[11];
1abb0dc9 106 enum ds_type type;
cb49a5e9
RG
107 unsigned long flags;
108#define HAS_NVRAM 0 /* bit 0 == sysfs file active */
109#define HAS_ALARM 1 /* bit 1 == irq claimed */
045e0e85 110 struct i2c_client *client;
1abb0dc9 111 struct rtc_device *rtc;
cb49a5e9 112 struct work_struct work;
0cc43a18 113 s32 (*read_block_data)(const struct i2c_client *client, u8 command,
30e7b039 114 u8 length, u8 *values);
0cc43a18 115 s32 (*write_block_data)(const struct i2c_client *client, u8 command,
30e7b039 116 u8 length, const u8 *values);
1abb0dc9
DB
117};
118
045e0e85 119struct chip_desc {
045e0e85
DB
120 unsigned nvram56:1;
121 unsigned alarm:1;
045e0e85
DB
122};
123
32d322bc
WS
124static const struct chip_desc chips[last_ds_type] = {
125 [ds_1307] = {
126 .nvram56 = 1,
127 },
128 [ds_1337] = {
129 .alarm = 1,
130 },
131 [ds_1338] = {
132 .nvram56 = 1,
133 },
134 [ds_1339] = {
135 .alarm = 1,
136 },
137 [ds_3231] = {
138 .alarm = 1,
139 },
140};
045e0e85 141
3760f736
JD
142static const struct i2c_device_id ds1307_id[] = {
143 { "ds1307", ds_1307 },
144 { "ds1337", ds_1337 },
145 { "ds1338", ds_1338 },
146 { "ds1339", ds_1339 },
33df2ee1 147 { "ds1388", ds_1388 },
3760f736 148 { "ds1340", ds_1340 },
97f902b7 149 { "ds3231", ds_3231 },
3760f736 150 { "m41t00", m41t00 },
43fcb815 151 { "mcp7941x", mcp7941x },
31c1771c 152 { "pt7c4338", ds_1307 },
a2166858 153 { "rx8025", rx_8025 },
3760f736
JD
154 { }
155};
156MODULE_DEVICE_TABLE(i2c, ds1307_id);
1abb0dc9 157
cb49a5e9
RG
158/*----------------------------------------------------------------------*/
159
30e7b039
ES
160#define BLOCK_DATA_MAX_TRIES 10
161
0cc43a18
JD
162static s32 ds1307_read_block_data_once(const struct i2c_client *client,
163 u8 command, u8 length, u8 *values)
30e7b039
ES
164{
165 s32 i, data;
166
167 for (i = 0; i < length; i++) {
168 data = i2c_smbus_read_byte_data(client, command + i);
169 if (data < 0)
170 return data;
171 values[i] = data;
172 }
173 return i;
174}
175
0cc43a18 176static s32 ds1307_read_block_data(const struct i2c_client *client, u8 command,
30e7b039
ES
177 u8 length, u8 *values)
178{
179 u8 oldvalues[I2C_SMBUS_BLOCK_MAX];
180 s32 ret;
181 int tries = 0;
182
183 dev_dbg(&client->dev, "ds1307_read_block_data (length=%d)\n", length);
184 ret = ds1307_read_block_data_once(client, command, length, values);
185 if (ret < 0)
186 return ret;
187 do {
188 if (++tries > BLOCK_DATA_MAX_TRIES) {
189 dev_err(&client->dev,
190 "ds1307_read_block_data failed\n");
191 return -EIO;
192 }
193 memcpy(oldvalues, values, length);
194 ret = ds1307_read_block_data_once(client, command, length,
195 values);
196 if (ret < 0)
197 return ret;
198 } while (memcmp(oldvalues, values, length));
199 return length;
200}
201
0cc43a18 202static s32 ds1307_write_block_data(const struct i2c_client *client, u8 command,
30e7b039
ES
203 u8 length, const u8 *values)
204{
205 u8 currvalues[I2C_SMBUS_BLOCK_MAX];
206 int tries = 0;
207
208 dev_dbg(&client->dev, "ds1307_write_block_data (length=%d)\n", length);
209 do {
210 s32 i, ret;
211
212 if (++tries > BLOCK_DATA_MAX_TRIES) {
213 dev_err(&client->dev,
214 "ds1307_write_block_data failed\n");
215 return -EIO;
216 }
217 for (i = 0; i < length; i++) {
218 ret = i2c_smbus_write_byte_data(client, command + i,
219 values[i]);
220 if (ret < 0)
221 return ret;
222 }
223 ret = ds1307_read_block_data_once(client, command, length,
224 currvalues);
225 if (ret < 0)
226 return ret;
227 } while (memcmp(currvalues, values, length));
228 return length;
229}
230
231/*----------------------------------------------------------------------*/
232
cb49a5e9
RG
233/*
234 * The IRQ logic includes a "real" handler running in IRQ context just
235 * long enough to schedule this workqueue entry. We need a task context
236 * to talk to the RTC, since I2C I/O calls require that; and disable the
237 * IRQ until we clear its status on the chip, so that this handler can
238 * work with any type of triggering (not just falling edge).
239 *
240 * The ds1337 and ds1339 both have two alarms, but we only use the first
241 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
242 * signal; ds1339 chips have only one alarm signal.
243 */
244static void ds1307_work(struct work_struct *work)
245{
246 struct ds1307 *ds1307;
247 struct i2c_client *client;
248 struct mutex *lock;
249 int stat, control;
250
251 ds1307 = container_of(work, struct ds1307, work);
252 client = ds1307->client;
253 lock = &ds1307->rtc->ops_lock;
254
255 mutex_lock(lock);
256 stat = i2c_smbus_read_byte_data(client, DS1337_REG_STATUS);
257 if (stat < 0)
258 goto out;
259
260 if (stat & DS1337_BIT_A1I) {
261 stat &= ~DS1337_BIT_A1I;
262 i2c_smbus_write_byte_data(client, DS1337_REG_STATUS, stat);
263
264 control = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
265 if (control < 0)
266 goto out;
267
268 control &= ~DS1337_BIT_A1IE;
269 i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, control);
270
cb49a5e9 271 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
cb49a5e9
RG
272 }
273
274out:
275 if (test_bit(HAS_ALARM, &ds1307->flags))
276 enable_irq(client->irq);
277 mutex_unlock(lock);
278}
279
280static irqreturn_t ds1307_irq(int irq, void *dev_id)
281{
282 struct i2c_client *client = dev_id;
283 struct ds1307 *ds1307 = i2c_get_clientdata(client);
284
285 disable_irq_nosync(irq);
286 schedule_work(&ds1307->work);
287 return IRQ_HANDLED;
288}
289
290/*----------------------------------------------------------------------*/
291
1abb0dc9
DB
292static int ds1307_get_time(struct device *dev, struct rtc_time *t)
293{
294 struct ds1307 *ds1307 = dev_get_drvdata(dev);
295 int tmp;
296
045e0e85 297 /* read the RTC date and time registers all at once */
30e7b039 298 tmp = ds1307->read_block_data(ds1307->client,
33df2ee1 299 ds1307->offset, 7, ds1307->regs);
fed40b73 300 if (tmp != 7) {
1abb0dc9
DB
301 dev_err(dev, "%s error %d\n", "read", tmp);
302 return -EIO;
303 }
304
305 dev_dbg(dev, "%s: %02x %02x %02x %02x %02x %02x %02x\n",
306 "read",
307 ds1307->regs[0], ds1307->regs[1],
308 ds1307->regs[2], ds1307->regs[3],
309 ds1307->regs[4], ds1307->regs[5],
310 ds1307->regs[6]);
311
fe20ba70
AB
312 t->tm_sec = bcd2bin(ds1307->regs[DS1307_REG_SECS] & 0x7f);
313 t->tm_min = bcd2bin(ds1307->regs[DS1307_REG_MIN] & 0x7f);
1abb0dc9 314 tmp = ds1307->regs[DS1307_REG_HOUR] & 0x3f;
fe20ba70
AB
315 t->tm_hour = bcd2bin(tmp);
316 t->tm_wday = bcd2bin(ds1307->regs[DS1307_REG_WDAY] & 0x07) - 1;
317 t->tm_mday = bcd2bin(ds1307->regs[DS1307_REG_MDAY] & 0x3f);
1abb0dc9 318 tmp = ds1307->regs[DS1307_REG_MONTH] & 0x1f;
fe20ba70 319 t->tm_mon = bcd2bin(tmp) - 1;
1abb0dc9
DB
320
321 /* assume 20YY not 19YY, and ignore DS1337_BIT_CENTURY */
fe20ba70 322 t->tm_year = bcd2bin(ds1307->regs[DS1307_REG_YEAR]) + 100;
1abb0dc9
DB
323
324 dev_dbg(dev, "%s secs=%d, mins=%d, "
325 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
326 "read", t->tm_sec, t->tm_min,
327 t->tm_hour, t->tm_mday,
328 t->tm_mon, t->tm_year, t->tm_wday);
329
045e0e85
DB
330 /* initial clock setting can be undefined */
331 return rtc_valid_tm(t);
1abb0dc9
DB
332}
333
334static int ds1307_set_time(struct device *dev, struct rtc_time *t)
335{
336 struct ds1307 *ds1307 = dev_get_drvdata(dev);
337 int result;
338 int tmp;
339 u8 *buf = ds1307->regs;
340
341 dev_dbg(dev, "%s secs=%d, mins=%d, "
342 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
11966adc
JG
343 "write", t->tm_sec, t->tm_min,
344 t->tm_hour, t->tm_mday,
345 t->tm_mon, t->tm_year, t->tm_wday);
1abb0dc9 346
fe20ba70
AB
347 buf[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
348 buf[DS1307_REG_MIN] = bin2bcd(t->tm_min);
349 buf[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
350 buf[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
351 buf[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
352 buf[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
1abb0dc9
DB
353
354 /* assume 20YY not 19YY */
355 tmp = t->tm_year - 100;
fe20ba70 356 buf[DS1307_REG_YEAR] = bin2bcd(tmp);
1abb0dc9 357
be5f59f4
RG
358 switch (ds1307->type) {
359 case ds_1337:
360 case ds_1339:
97f902b7 361 case ds_3231:
1abb0dc9 362 buf[DS1307_REG_MONTH] |= DS1337_BIT_CENTURY;
be5f59f4
RG
363 break;
364 case ds_1340:
1abb0dc9
DB
365 buf[DS1307_REG_HOUR] |= DS1340_BIT_CENTURY_EN
366 | DS1340_BIT_CENTURY;
be5f59f4 367 break;
43fcb815
DA
368 case mcp7941x:
369 buf[DS1307_REG_SECS] |= MCP7941X_BIT_ST;
370 buf[DS1307_REG_WDAY] |= MCP7941X_BIT_VBATEN;
371 break;
be5f59f4
RG
372 default:
373 break;
374 }
1abb0dc9 375
1abb0dc9
DB
376 dev_dbg(dev, "%s: %02x %02x %02x %02x %02x %02x %02x\n",
377 "write", buf[0], buf[1], buf[2], buf[3],
378 buf[4], buf[5], buf[6]);
379
33df2ee1
JT
380 result = ds1307->write_block_data(ds1307->client,
381 ds1307->offset, 7, buf);
fed40b73
BS
382 if (result < 0) {
383 dev_err(dev, "%s error %d\n", "write", result);
384 return result;
1abb0dc9
DB
385 }
386 return 0;
387}
388
74d88eb2 389static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
cb49a5e9
RG
390{
391 struct i2c_client *client = to_i2c_client(dev);
392 struct ds1307 *ds1307 = i2c_get_clientdata(client);
393 int ret;
394
395 if (!test_bit(HAS_ALARM, &ds1307->flags))
396 return -EINVAL;
397
398 /* read all ALARM1, ALARM2, and status registers at once */
30e7b039 399 ret = ds1307->read_block_data(client,
fed40b73
BS
400 DS1339_REG_ALARM1_SECS, 9, ds1307->regs);
401 if (ret != 9) {
cb49a5e9
RG
402 dev_err(dev, "%s error %d\n", "alarm read", ret);
403 return -EIO;
404 }
405
406 dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
407 "alarm read",
408 ds1307->regs[0], ds1307->regs[1],
409 ds1307->regs[2], ds1307->regs[3],
410 ds1307->regs[4], ds1307->regs[5],
411 ds1307->regs[6], ds1307->regs[7],
412 ds1307->regs[8]);
413
414 /* report alarm time (ALARM1); assume 24 hour and day-of-month modes,
415 * and that all four fields are checked matches
416 */
417 t->time.tm_sec = bcd2bin(ds1307->regs[0] & 0x7f);
418 t->time.tm_min = bcd2bin(ds1307->regs[1] & 0x7f);
419 t->time.tm_hour = bcd2bin(ds1307->regs[2] & 0x3f);
420 t->time.tm_mday = bcd2bin(ds1307->regs[3] & 0x3f);
421 t->time.tm_mon = -1;
422 t->time.tm_year = -1;
423 t->time.tm_wday = -1;
424 t->time.tm_yday = -1;
425 t->time.tm_isdst = -1;
426
427 /* ... and status */
428 t->enabled = !!(ds1307->regs[7] & DS1337_BIT_A1IE);
429 t->pending = !!(ds1307->regs[8] & DS1337_BIT_A1I);
430
431 dev_dbg(dev, "%s secs=%d, mins=%d, "
432 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
433 "alarm read", t->time.tm_sec, t->time.tm_min,
434 t->time.tm_hour, t->time.tm_mday,
435 t->enabled, t->pending);
436
437 return 0;
438}
439
74d88eb2 440static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
cb49a5e9
RG
441{
442 struct i2c_client *client = to_i2c_client(dev);
443 struct ds1307 *ds1307 = i2c_get_clientdata(client);
444 unsigned char *buf = ds1307->regs;
445 u8 control, status;
446 int ret;
447
448 if (!test_bit(HAS_ALARM, &ds1307->flags))
449 return -EINVAL;
450
451 dev_dbg(dev, "%s secs=%d, mins=%d, "
452 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
453 "alarm set", t->time.tm_sec, t->time.tm_min,
454 t->time.tm_hour, t->time.tm_mday,
455 t->enabled, t->pending);
456
457 /* read current status of both alarms and the chip */
30e7b039 458 ret = ds1307->read_block_data(client,
fed40b73
BS
459 DS1339_REG_ALARM1_SECS, 9, buf);
460 if (ret != 9) {
cb49a5e9
RG
461 dev_err(dev, "%s error %d\n", "alarm write", ret);
462 return -EIO;
463 }
464 control = ds1307->regs[7];
465 status = ds1307->regs[8];
466
467 dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
468 "alarm set (old status)",
469 ds1307->regs[0], ds1307->regs[1],
470 ds1307->regs[2], ds1307->regs[3],
471 ds1307->regs[4], ds1307->regs[5],
472 ds1307->regs[6], control, status);
473
474 /* set ALARM1, using 24 hour and day-of-month modes */
cb49a5e9
RG
475 buf[0] = bin2bcd(t->time.tm_sec);
476 buf[1] = bin2bcd(t->time.tm_min);
477 buf[2] = bin2bcd(t->time.tm_hour);
478 buf[3] = bin2bcd(t->time.tm_mday);
479
480 /* set ALARM2 to non-garbage */
481 buf[4] = 0;
482 buf[5] = 0;
483 buf[6] = 0;
484
485 /* optionally enable ALARM1 */
486 buf[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
487 if (t->enabled) {
488 dev_dbg(dev, "alarm IRQ armed\n");
489 buf[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
490 }
491 buf[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
492
30e7b039 493 ret = ds1307->write_block_data(client,
fed40b73
BS
494 DS1339_REG_ALARM1_SECS, 9, buf);
495 if (ret < 0) {
cb49a5e9 496 dev_err(dev, "can't set alarm time\n");
fed40b73 497 return ret;
cb49a5e9
RG
498 }
499
500 return 0;
501}
502
16380c15 503static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
cb49a5e9
RG
504{
505 struct i2c_client *client = to_i2c_client(dev);
506 struct ds1307 *ds1307 = i2c_get_clientdata(client);
507 int ret;
508
16380c15
JS
509 if (!test_bit(HAS_ALARM, &ds1307->flags))
510 return -ENOTTY;
cb49a5e9 511
16380c15
JS
512 ret = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
513 if (ret < 0)
514 return ret;
cb49a5e9 515
16380c15 516 if (enabled)
cb49a5e9 517 ret |= DS1337_BIT_A1IE;
16380c15
JS
518 else
519 ret &= ~DS1337_BIT_A1IE;
cb49a5e9 520
16380c15
JS
521 ret = i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, ret);
522 if (ret < 0)
523 return ret;
cb49a5e9
RG
524
525 return 0;
526}
527
ff8371ac 528static const struct rtc_class_ops ds13xx_rtc_ops = {
1abb0dc9
DB
529 .read_time = ds1307_get_time,
530 .set_time = ds1307_set_time,
74d88eb2
JR
531 .read_alarm = ds1337_read_alarm,
532 .set_alarm = ds1337_set_alarm,
16380c15 533 .alarm_irq_enable = ds1307_alarm_irq_enable,
1abb0dc9
DB
534};
535
682d73f6
DB
536/*----------------------------------------------------------------------*/
537
538#define NVRAM_SIZE 56
539
540static ssize_t
2c3c8bea
CW
541ds1307_nvram_read(struct file *filp, struct kobject *kobj,
542 struct bin_attribute *attr,
682d73f6
DB
543 char *buf, loff_t off, size_t count)
544{
545 struct i2c_client *client;
546 struct ds1307 *ds1307;
682d73f6
DB
547 int result;
548
fcd8db00 549 client = kobj_to_i2c_client(kobj);
682d73f6
DB
550 ds1307 = i2c_get_clientdata(client);
551
552 if (unlikely(off >= NVRAM_SIZE))
553 return 0;
554 if ((off + count) > NVRAM_SIZE)
555 count = NVRAM_SIZE - off;
556 if (unlikely(!count))
557 return count;
558
30e7b039 559 result = ds1307->read_block_data(client, 8 + off, count, buf);
fed40b73 560 if (result < 0)
682d73f6 561 dev_err(&client->dev, "%s error %d\n", "nvram read", result);
fed40b73 562 return result;
682d73f6
DB
563}
564
565static ssize_t
2c3c8bea
CW
566ds1307_nvram_write(struct file *filp, struct kobject *kobj,
567 struct bin_attribute *attr,
682d73f6
DB
568 char *buf, loff_t off, size_t count)
569{
570 struct i2c_client *client;
30e7b039 571 struct ds1307 *ds1307;
fed40b73 572 int result;
682d73f6 573
fcd8db00 574 client = kobj_to_i2c_client(kobj);
30e7b039 575 ds1307 = i2c_get_clientdata(client);
682d73f6
DB
576
577 if (unlikely(off >= NVRAM_SIZE))
578 return -EFBIG;
579 if ((off + count) > NVRAM_SIZE)
580 count = NVRAM_SIZE - off;
581 if (unlikely(!count))
582 return count;
583
30e7b039 584 result = ds1307->write_block_data(client, 8 + off, count, buf);
fed40b73
BS
585 if (result < 0) {
586 dev_err(&client->dev, "%s error %d\n", "nvram write", result);
587 return result;
588 }
589 return count;
682d73f6
DB
590}
591
592static struct bin_attribute nvram = {
593 .attr = {
594 .name = "nvram",
595 .mode = S_IRUGO | S_IWUSR,
682d73f6
DB
596 },
597
598 .read = ds1307_nvram_read,
599 .write = ds1307_nvram_write,
600 .size = NVRAM_SIZE,
601};
602
603/*----------------------------------------------------------------------*/
604
1abb0dc9
DB
605static struct i2c_driver ds1307_driver;
606
d2653e92
JD
607static int __devinit ds1307_probe(struct i2c_client *client,
608 const struct i2c_device_id *id)
1abb0dc9
DB
609{
610 struct ds1307 *ds1307;
611 int err = -ENODEV;
1abb0dc9 612 int tmp;
3760f736 613 const struct chip_desc *chip = &chips[id->driver_data];
c065f35c 614 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
cb49a5e9 615 int want_irq = false;
fed40b73 616 unsigned char *buf;
97f902b7
WS
617 static const int bbsqi_bitpos[] = {
618 [ds_1337] = 0,
619 [ds_1339] = DS1339_BIT_BBSQI,
620 [ds_3231] = DS3231_BIT_BBSQW,
621 };
1abb0dc9 622
30e7b039
ES
623 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)
624 && !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK))
c065f35c
DB
625 return -EIO;
626
627 if (!(ds1307 = kzalloc(sizeof(struct ds1307), GFP_KERNEL)))
628 return -ENOMEM;
045e0e85 629
1abb0dc9 630 i2c_set_clientdata(client, ds1307);
33df2ee1
JT
631
632 ds1307->client = client;
633 ds1307->type = id->driver_data;
634 ds1307->offset = 0;
635
fed40b73 636 buf = ds1307->regs;
30e7b039
ES
637 if (i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) {
638 ds1307->read_block_data = i2c_smbus_read_i2c_block_data;
639 ds1307->write_block_data = i2c_smbus_write_i2c_block_data;
640 } else {
641 ds1307->read_block_data = ds1307_read_block_data;
642 ds1307->write_block_data = ds1307_write_block_data;
643 }
045e0e85
DB
644
645 switch (ds1307->type) {
646 case ds_1337:
647 case ds_1339:
97f902b7 648 case ds_3231:
cb49a5e9
RG
649 /* has IRQ? */
650 if (ds1307->client->irq > 0 && chip->alarm) {
651 INIT_WORK(&ds1307->work, ds1307_work);
652 want_irq = true;
653 }
be5f59f4 654 /* get registers that the "rtc" read below won't read... */
30e7b039 655 tmp = ds1307->read_block_data(ds1307->client,
fed40b73 656 DS1337_REG_CONTROL, 2, buf);
1abb0dc9
DB
657 if (tmp != 2) {
658 pr_debug("read error %d\n", tmp);
659 err = -EIO;
660 goto exit_free;
661 }
662
be5f59f4
RG
663 /* oscillator off? turn it on, so clock can tick. */
664 if (ds1307->regs[0] & DS1337_BIT_nEOSC)
cb49a5e9
RG
665 ds1307->regs[0] &= ~DS1337_BIT_nEOSC;
666
667 /* Using IRQ? Disable the square wave and both alarms.
97f902b7
WS
668 * For some variants, be sure alarms can trigger when we're
669 * running on Vbackup (BBSQI/BBSQW)
cb49a5e9
RG
670 */
671 if (want_irq) {
97f902b7
WS
672 ds1307->regs[0] |= DS1337_BIT_INTCN
673 | bbsqi_bitpos[ds1307->type];
cb49a5e9
RG
674 ds1307->regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
675 }
676
677 i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL,
678 ds1307->regs[0]);
be5f59f4
RG
679
680 /* oscillator fault? clear flag, and warn */
681 if (ds1307->regs[1] & DS1337_BIT_OSF) {
682 i2c_smbus_write_byte_data(client, DS1337_REG_STATUS,
683 ds1307->regs[1] & ~DS1337_BIT_OSF);
684 dev_warn(&client->dev, "SET TIME!\n");
1abb0dc9 685 }
045e0e85 686 break;
a2166858
MF
687
688 case rx_8025:
689 tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
690 RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
691 if (tmp != 2) {
692 pr_debug("read error %d\n", tmp);
693 err = -EIO;
694 goto exit_free;
695 }
696
697 /* oscillator off? turn it on, so clock can tick. */
698 if (!(ds1307->regs[1] & RX8025_BIT_XST)) {
699 ds1307->regs[1] |= RX8025_BIT_XST;
700 i2c_smbus_write_byte_data(client,
701 RX8025_REG_CTRL2 << 4 | 0x08,
702 ds1307->regs[1]);
703 dev_warn(&client->dev,
704 "oscillator stop detected - SET TIME!\n");
705 }
706
707 if (ds1307->regs[1] & RX8025_BIT_PON) {
708 ds1307->regs[1] &= ~RX8025_BIT_PON;
709 i2c_smbus_write_byte_data(client,
710 RX8025_REG_CTRL2 << 4 | 0x08,
711 ds1307->regs[1]);
712 dev_warn(&client->dev, "power-on detected\n");
713 }
714
715 if (ds1307->regs[1] & RX8025_BIT_VDET) {
716 ds1307->regs[1] &= ~RX8025_BIT_VDET;
717 i2c_smbus_write_byte_data(client,
718 RX8025_REG_CTRL2 << 4 | 0x08,
719 ds1307->regs[1]);
720 dev_warn(&client->dev, "voltage drop detected\n");
721 }
722
723 /* make sure we are running in 24hour mode */
724 if (!(ds1307->regs[0] & RX8025_BIT_2412)) {
725 u8 hour;
726
727 /* switch to 24 hour mode */
728 i2c_smbus_write_byte_data(client,
729 RX8025_REG_CTRL1 << 4 | 0x08,
730 ds1307->regs[0] |
731 RX8025_BIT_2412);
732
733 tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
734 RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
735 if (tmp != 2) {
736 pr_debug("read error %d\n", tmp);
737 err = -EIO;
738 goto exit_free;
739 }
740
741 /* correct hour */
742 hour = bcd2bin(ds1307->regs[DS1307_REG_HOUR]);
743 if (hour == 12)
744 hour = 0;
745 if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
746 hour += 12;
747
748 i2c_smbus_write_byte_data(client,
749 DS1307_REG_HOUR << 4 | 0x08,
750 hour);
751 }
752 break;
33df2ee1
JT
753 case ds_1388:
754 ds1307->offset = 1; /* Seconds starts at 1 */
755 break;
045e0e85
DB
756 default:
757 break;
758 }
1abb0dc9
DB
759
760read_rtc:
761 /* read RTC registers */
96fc3a45 762 tmp = ds1307->read_block_data(ds1307->client, ds1307->offset, 8, buf);
fed40b73 763 if (tmp != 8) {
1abb0dc9
DB
764 pr_debug("read error %d\n", tmp);
765 err = -EIO;
766 goto exit_free;
767 }
768
769 /* minimal sanity checking; some chips (like DS1340) don't
770 * specify the extra bits as must-be-zero, but there are
771 * still a few values that are clearly out-of-range.
772 */
773 tmp = ds1307->regs[DS1307_REG_SECS];
045e0e85
DB
774 switch (ds1307->type) {
775 case ds_1307:
045e0e85 776 case m41t00:
be5f59f4 777 /* clock halted? turn it on, so clock can tick. */
045e0e85 778 if (tmp & DS1307_BIT_CH) {
be5f59f4
RG
779 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
780 dev_warn(&client->dev, "SET TIME!\n");
045e0e85 781 goto read_rtc;
1abb0dc9 782 }
045e0e85 783 break;
be5f59f4
RG
784 case ds_1338:
785 /* clock halted? turn it on, so clock can tick. */
045e0e85 786 if (tmp & DS1307_BIT_CH)
be5f59f4
RG
787 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
788
789 /* oscillator fault? clear flag, and warn */
790 if (ds1307->regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
791 i2c_smbus_write_byte_data(client, DS1307_REG_CONTROL,
bd16f9eb 792 ds1307->regs[DS1307_REG_CONTROL]
be5f59f4
RG
793 & ~DS1338_BIT_OSF);
794 dev_warn(&client->dev, "SET TIME!\n");
795 goto read_rtc;
796 }
045e0e85 797 break;
fcd8db00
R
798 case ds_1340:
799 /* clock halted? turn it on, so clock can tick. */
800 if (tmp & DS1340_BIT_nEOSC)
801 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
802
803 tmp = i2c_smbus_read_byte_data(client, DS1340_REG_FLAG);
804 if (tmp < 0) {
805 pr_debug("read error %d\n", tmp);
806 err = -EIO;
807 goto exit_free;
808 }
809
810 /* oscillator fault? clear flag, and warn */
811 if (tmp & DS1340_BIT_OSF) {
812 i2c_smbus_write_byte_data(client, DS1340_REG_FLAG, 0);
813 dev_warn(&client->dev, "SET TIME!\n");
814 }
43fcb815
DA
815 break;
816 case mcp7941x:
817 /* make sure that the backup battery is enabled */
818 if (!(ds1307->regs[DS1307_REG_WDAY] & MCP7941X_BIT_VBATEN)) {
819 i2c_smbus_write_byte_data(client, DS1307_REG_WDAY,
820 ds1307->regs[DS1307_REG_WDAY]
821 | MCP7941X_BIT_VBATEN);
822 }
823
824 /* clock halted? turn it on, so clock can tick. */
825 if (!(tmp & MCP7941X_BIT_ST)) {
826 i2c_smbus_write_byte_data(client, DS1307_REG_SECS,
827 MCP7941X_BIT_ST);
828 dev_warn(&client->dev, "SET TIME!\n");
829 goto read_rtc;
830 }
831
fcd8db00 832 break;
32d322bc 833 default:
045e0e85 834 break;
1abb0dc9 835 }
045e0e85 836
1abb0dc9 837 tmp = ds1307->regs[DS1307_REG_HOUR];
c065f35c
DB
838 switch (ds1307->type) {
839 case ds_1340:
840 case m41t00:
841 /* NOTE: ignores century bits; fix before deploying
842 * systems that will run through year 2100.
843 */
844 break;
a2166858
MF
845 case rx_8025:
846 break;
c065f35c
DB
847 default:
848 if (!(tmp & DS1307_BIT_12HR))
849 break;
850
851 /* Be sure we're in 24 hour mode. Multi-master systems
852 * take note...
853 */
fe20ba70 854 tmp = bcd2bin(tmp & 0x1f);
c065f35c
DB
855 if (tmp == 12)
856 tmp = 0;
857 if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
858 tmp += 12;
1abb0dc9 859 i2c_smbus_write_byte_data(client,
96fc3a45 860 ds1307->offset + DS1307_REG_HOUR,
fe20ba70 861 bin2bcd(tmp));
1abb0dc9
DB
862 }
863
1abb0dc9
DB
864 ds1307->rtc = rtc_device_register(client->name, &client->dev,
865 &ds13xx_rtc_ops, THIS_MODULE);
866 if (IS_ERR(ds1307->rtc)) {
867 err = PTR_ERR(ds1307->rtc);
868 dev_err(&client->dev,
869 "unable to register the class device\n");
c065f35c 870 goto exit_free;
1abb0dc9
DB
871 }
872
cb49a5e9 873 if (want_irq) {
43d15bcd 874 err = request_irq(client->irq, ds1307_irq, IRQF_SHARED,
cb49a5e9
RG
875 ds1307->rtc->name, client);
876 if (err) {
877 dev_err(&client->dev,
878 "unable to request IRQ!\n");
879 goto exit_irq;
880 }
26b3c01f
AV
881
882 device_set_wakeup_capable(&client->dev, 1);
cb49a5e9
RG
883 set_bit(HAS_ALARM, &ds1307->flags);
884 dev_dbg(&client->dev, "got IRQ %d\n", client->irq);
885 }
886
682d73f6
DB
887 if (chip->nvram56) {
888 err = sysfs_create_bin_file(&client->dev.kobj, &nvram);
889 if (err == 0) {
cb49a5e9 890 set_bit(HAS_NVRAM, &ds1307->flags);
682d73f6
DB
891 dev_info(&client->dev, "56 bytes nvram\n");
892 }
893 }
894
1abb0dc9
DB
895 return 0;
896
cb49a5e9 897exit_irq:
72445af8 898 rtc_device_unregister(ds1307->rtc);
1abb0dc9
DB
899exit_free:
900 kfree(ds1307);
1abb0dc9
DB
901 return err;
902}
903
c065f35c 904static int __devexit ds1307_remove(struct i2c_client *client)
1abb0dc9 905{
cb49a5e9
RG
906 struct ds1307 *ds1307 = i2c_get_clientdata(client);
907
908 if (test_and_clear_bit(HAS_ALARM, &ds1307->flags)) {
909 free_irq(client->irq, client);
910 cancel_work_sync(&ds1307->work);
911 }
1abb0dc9 912
cb49a5e9 913 if (test_and_clear_bit(HAS_NVRAM, &ds1307->flags))
682d73f6
DB
914 sysfs_remove_bin_file(&client->dev.kobj, &nvram);
915
1abb0dc9 916 rtc_device_unregister(ds1307->rtc);
1abb0dc9
DB
917 kfree(ds1307);
918 return 0;
919}
920
921static struct i2c_driver ds1307_driver = {
922 .driver = {
c065f35c 923 .name = "rtc-ds1307",
1abb0dc9
DB
924 .owner = THIS_MODULE,
925 },
c065f35c
DB
926 .probe = ds1307_probe,
927 .remove = __devexit_p(ds1307_remove),
3760f736 928 .id_table = ds1307_id,
1abb0dc9
DB
929};
930
0abc9201 931module_i2c_driver(ds1307_driver);
1abb0dc9
DB
932
933MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
934MODULE_LICENSE("GPL");
This page took 0.687038 seconds and 5 git commands to generate.