rtc: ds1307: comment and format cleanup
[deliverable/linux.git] / drivers / rtc / rtc-ds1307.c
CommitLineData
1abb0dc9
DB
1/*
2 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
3 *
4 * Copyright (C) 2005 James Chapman (ds1337 core)
5 * Copyright (C) 2006 David Brownell
a2166858 6 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
1abb0dc9
DB
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/slab.h>
16#include <linux/i2c.h>
17#include <linux/string.h>
18#include <linux/rtc.h>
19#include <linux/bcd.h>
20
21
22
40ce972d
DA
23/*
24 * We can't determine type by probing, but if we expect pre-Linux code
1abb0dc9
DB
25 * to have set the chip up as a clock (turning on the oscillator and
26 * setting the date and time), Linux can ignore the non-clock features.
27 * That's a natural job for a factory or repair bench.
1abb0dc9
DB
28 */
29enum ds_type {
045e0e85
DB
30 ds_1307,
31 ds_1337,
32 ds_1338,
33 ds_1339,
34 ds_1340,
33df2ee1 35 ds_1388,
97f902b7 36 ds_3231,
045e0e85 37 m41t00,
43fcb815 38 mcp7941x,
a2166858 39 rx_8025,
32d322bc 40 last_ds_type /* always last */
40ce972d 41 /* rs5c372 too? different address... */
1abb0dc9
DB
42};
43
1abb0dc9
DB
44
45/* RTC registers don't differ much, except for the century flag */
46#define DS1307_REG_SECS 0x00 /* 00-59 */
47# define DS1307_BIT_CH 0x80
be5f59f4 48# define DS1340_BIT_nEOSC 0x80
43fcb815 49# define MCP7941X_BIT_ST 0x80
1abb0dc9
DB
50#define DS1307_REG_MIN 0x01 /* 00-59 */
51#define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
c065f35c
DB
52# define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
53# define DS1307_BIT_PM 0x20 /* in REG_HOUR */
1abb0dc9
DB
54# define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
55# define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
56#define DS1307_REG_WDAY 0x03 /* 01-07 */
43fcb815 57# define MCP7941X_BIT_VBATEN 0x08
1abb0dc9
DB
58#define DS1307_REG_MDAY 0x04 /* 01-31 */
59#define DS1307_REG_MONTH 0x05 /* 01-12 */
60# define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
61#define DS1307_REG_YEAR 0x06 /* 00-99 */
62
40ce972d
DA
63/*
64 * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
045e0e85
DB
65 * start at 7, and they differ a LOT. Only control and status matter for
66 * basic RTC date and time functionality; be careful using them.
1abb0dc9 67 */
045e0e85 68#define DS1307_REG_CONTROL 0x07 /* or ds1338 */
1abb0dc9 69# define DS1307_BIT_OUT 0x80
be5f59f4 70# define DS1338_BIT_OSF 0x20
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DB
71# define DS1307_BIT_SQWE 0x10
72# define DS1307_BIT_RS1 0x02
73# define DS1307_BIT_RS0 0x01
74#define DS1337_REG_CONTROL 0x0e
75# define DS1337_BIT_nEOSC 0x80
cb49a5e9 76# define DS1339_BIT_BBSQI 0x20
97f902b7 77# define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
1abb0dc9
DB
78# define DS1337_BIT_RS2 0x10
79# define DS1337_BIT_RS1 0x08
80# define DS1337_BIT_INTCN 0x04
81# define DS1337_BIT_A2IE 0x02
82# define DS1337_BIT_A1IE 0x01
045e0e85
DB
83#define DS1340_REG_CONTROL 0x07
84# define DS1340_BIT_OUT 0x80
85# define DS1340_BIT_FT 0x40
86# define DS1340_BIT_CALIB_SIGN 0x20
87# define DS1340_M_CALIBRATION 0x1f
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RG
88#define DS1340_REG_FLAG 0x09
89# define DS1340_BIT_OSF 0x80
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DB
90#define DS1337_REG_STATUS 0x0f
91# define DS1337_BIT_OSF 0x80
92# define DS1337_BIT_A2I 0x02
93# define DS1337_BIT_A1I 0x01
cb49a5e9 94#define DS1339_REG_ALARM1_SECS 0x07
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DB
95#define DS1339_REG_TRICKLE 0x10
96
a2166858
MF
97#define RX8025_REG_CTRL1 0x0e
98# define RX8025_BIT_2412 0x20
99#define RX8025_REG_CTRL2 0x0f
100# define RX8025_BIT_PON 0x10
101# define RX8025_BIT_VDET 0x40
102# define RX8025_BIT_XST 0x20
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103
104
105struct ds1307 {
33df2ee1 106 u8 offset; /* register's offset */
cb49a5e9 107 u8 regs[11];
1abb0dc9 108 enum ds_type type;
cb49a5e9
RG
109 unsigned long flags;
110#define HAS_NVRAM 0 /* bit 0 == sysfs file active */
111#define HAS_ALARM 1 /* bit 1 == irq claimed */
045e0e85 112 struct i2c_client *client;
1abb0dc9 113 struct rtc_device *rtc;
cb49a5e9 114 struct work_struct work;
0cc43a18 115 s32 (*read_block_data)(const struct i2c_client *client, u8 command,
30e7b039 116 u8 length, u8 *values);
0cc43a18 117 s32 (*write_block_data)(const struct i2c_client *client, u8 command,
30e7b039 118 u8 length, const u8 *values);
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119};
120
045e0e85 121struct chip_desc {
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DB
122 unsigned nvram56:1;
123 unsigned alarm:1;
045e0e85
DB
124};
125
32d322bc
WS
126static const struct chip_desc chips[last_ds_type] = {
127 [ds_1307] = {
128 .nvram56 = 1,
129 },
130 [ds_1337] = {
131 .alarm = 1,
132 },
133 [ds_1338] = {
134 .nvram56 = 1,
135 },
136 [ds_1339] = {
137 .alarm = 1,
138 },
139 [ds_3231] = {
140 .alarm = 1,
141 },
142};
045e0e85 143
3760f736
JD
144static const struct i2c_device_id ds1307_id[] = {
145 { "ds1307", ds_1307 },
146 { "ds1337", ds_1337 },
147 { "ds1338", ds_1338 },
148 { "ds1339", ds_1339 },
33df2ee1 149 { "ds1388", ds_1388 },
3760f736 150 { "ds1340", ds_1340 },
97f902b7 151 { "ds3231", ds_3231 },
3760f736 152 { "m41t00", m41t00 },
43fcb815 153 { "mcp7941x", mcp7941x },
31c1771c 154 { "pt7c4338", ds_1307 },
a2166858 155 { "rx8025", rx_8025 },
3760f736
JD
156 { }
157};
158MODULE_DEVICE_TABLE(i2c, ds1307_id);
1abb0dc9 159
cb49a5e9
RG
160/*----------------------------------------------------------------------*/
161
30e7b039
ES
162#define BLOCK_DATA_MAX_TRIES 10
163
0cc43a18
JD
164static s32 ds1307_read_block_data_once(const struct i2c_client *client,
165 u8 command, u8 length, u8 *values)
30e7b039
ES
166{
167 s32 i, data;
168
169 for (i = 0; i < length; i++) {
170 data = i2c_smbus_read_byte_data(client, command + i);
171 if (data < 0)
172 return data;
173 values[i] = data;
174 }
175 return i;
176}
177
0cc43a18 178static s32 ds1307_read_block_data(const struct i2c_client *client, u8 command,
30e7b039
ES
179 u8 length, u8 *values)
180{
181 u8 oldvalues[I2C_SMBUS_BLOCK_MAX];
182 s32 ret;
183 int tries = 0;
184
185 dev_dbg(&client->dev, "ds1307_read_block_data (length=%d)\n", length);
186 ret = ds1307_read_block_data_once(client, command, length, values);
187 if (ret < 0)
188 return ret;
189 do {
190 if (++tries > BLOCK_DATA_MAX_TRIES) {
191 dev_err(&client->dev,
192 "ds1307_read_block_data failed\n");
193 return -EIO;
194 }
195 memcpy(oldvalues, values, length);
196 ret = ds1307_read_block_data_once(client, command, length,
197 values);
198 if (ret < 0)
199 return ret;
200 } while (memcmp(oldvalues, values, length));
201 return length;
202}
203
0cc43a18 204static s32 ds1307_write_block_data(const struct i2c_client *client, u8 command,
30e7b039
ES
205 u8 length, const u8 *values)
206{
207 u8 currvalues[I2C_SMBUS_BLOCK_MAX];
208 int tries = 0;
209
210 dev_dbg(&client->dev, "ds1307_write_block_data (length=%d)\n", length);
211 do {
212 s32 i, ret;
213
214 if (++tries > BLOCK_DATA_MAX_TRIES) {
215 dev_err(&client->dev,
216 "ds1307_write_block_data failed\n");
217 return -EIO;
218 }
219 for (i = 0; i < length; i++) {
220 ret = i2c_smbus_write_byte_data(client, command + i,
221 values[i]);
222 if (ret < 0)
223 return ret;
224 }
225 ret = ds1307_read_block_data_once(client, command, length,
226 currvalues);
227 if (ret < 0)
228 return ret;
229 } while (memcmp(currvalues, values, length));
230 return length;
231}
232
233/*----------------------------------------------------------------------*/
234
cb49a5e9
RG
235/*
236 * The IRQ logic includes a "real" handler running in IRQ context just
237 * long enough to schedule this workqueue entry. We need a task context
238 * to talk to the RTC, since I2C I/O calls require that; and disable the
239 * IRQ until we clear its status on the chip, so that this handler can
240 * work with any type of triggering (not just falling edge).
241 *
242 * The ds1337 and ds1339 both have two alarms, but we only use the first
243 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
244 * signal; ds1339 chips have only one alarm signal.
245 */
246static void ds1307_work(struct work_struct *work)
247{
248 struct ds1307 *ds1307;
249 struct i2c_client *client;
250 struct mutex *lock;
251 int stat, control;
252
253 ds1307 = container_of(work, struct ds1307, work);
254 client = ds1307->client;
255 lock = &ds1307->rtc->ops_lock;
256
257 mutex_lock(lock);
258 stat = i2c_smbus_read_byte_data(client, DS1337_REG_STATUS);
259 if (stat < 0)
260 goto out;
261
262 if (stat & DS1337_BIT_A1I) {
263 stat &= ~DS1337_BIT_A1I;
264 i2c_smbus_write_byte_data(client, DS1337_REG_STATUS, stat);
265
266 control = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
267 if (control < 0)
268 goto out;
269
270 control &= ~DS1337_BIT_A1IE;
271 i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, control);
272
cb49a5e9 273 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
cb49a5e9
RG
274 }
275
276out:
277 if (test_bit(HAS_ALARM, &ds1307->flags))
278 enable_irq(client->irq);
279 mutex_unlock(lock);
280}
281
282static irqreturn_t ds1307_irq(int irq, void *dev_id)
283{
284 struct i2c_client *client = dev_id;
285 struct ds1307 *ds1307 = i2c_get_clientdata(client);
286
287 disable_irq_nosync(irq);
288 schedule_work(&ds1307->work);
289 return IRQ_HANDLED;
290}
291
292/*----------------------------------------------------------------------*/
293
1abb0dc9
DB
294static int ds1307_get_time(struct device *dev, struct rtc_time *t)
295{
296 struct ds1307 *ds1307 = dev_get_drvdata(dev);
297 int tmp;
298
045e0e85 299 /* read the RTC date and time registers all at once */
30e7b039 300 tmp = ds1307->read_block_data(ds1307->client,
33df2ee1 301 ds1307->offset, 7, ds1307->regs);
fed40b73 302 if (tmp != 7) {
1abb0dc9
DB
303 dev_err(dev, "%s error %d\n", "read", tmp);
304 return -EIO;
305 }
306
307 dev_dbg(dev, "%s: %02x %02x %02x %02x %02x %02x %02x\n",
308 "read",
309 ds1307->regs[0], ds1307->regs[1],
310 ds1307->regs[2], ds1307->regs[3],
311 ds1307->regs[4], ds1307->regs[5],
312 ds1307->regs[6]);
313
fe20ba70
AB
314 t->tm_sec = bcd2bin(ds1307->regs[DS1307_REG_SECS] & 0x7f);
315 t->tm_min = bcd2bin(ds1307->regs[DS1307_REG_MIN] & 0x7f);
1abb0dc9 316 tmp = ds1307->regs[DS1307_REG_HOUR] & 0x3f;
fe20ba70
AB
317 t->tm_hour = bcd2bin(tmp);
318 t->tm_wday = bcd2bin(ds1307->regs[DS1307_REG_WDAY] & 0x07) - 1;
319 t->tm_mday = bcd2bin(ds1307->regs[DS1307_REG_MDAY] & 0x3f);
1abb0dc9 320 tmp = ds1307->regs[DS1307_REG_MONTH] & 0x1f;
fe20ba70 321 t->tm_mon = bcd2bin(tmp) - 1;
1abb0dc9
DB
322
323 /* assume 20YY not 19YY, and ignore DS1337_BIT_CENTURY */
fe20ba70 324 t->tm_year = bcd2bin(ds1307->regs[DS1307_REG_YEAR]) + 100;
1abb0dc9
DB
325
326 dev_dbg(dev, "%s secs=%d, mins=%d, "
327 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
328 "read", t->tm_sec, t->tm_min,
329 t->tm_hour, t->tm_mday,
330 t->tm_mon, t->tm_year, t->tm_wday);
331
045e0e85
DB
332 /* initial clock setting can be undefined */
333 return rtc_valid_tm(t);
1abb0dc9
DB
334}
335
336static int ds1307_set_time(struct device *dev, struct rtc_time *t)
337{
338 struct ds1307 *ds1307 = dev_get_drvdata(dev);
339 int result;
340 int tmp;
341 u8 *buf = ds1307->regs;
342
343 dev_dbg(dev, "%s secs=%d, mins=%d, "
344 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
11966adc
JG
345 "write", t->tm_sec, t->tm_min,
346 t->tm_hour, t->tm_mday,
347 t->tm_mon, t->tm_year, t->tm_wday);
1abb0dc9 348
fe20ba70
AB
349 buf[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
350 buf[DS1307_REG_MIN] = bin2bcd(t->tm_min);
351 buf[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
352 buf[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
353 buf[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
354 buf[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
1abb0dc9
DB
355
356 /* assume 20YY not 19YY */
357 tmp = t->tm_year - 100;
fe20ba70 358 buf[DS1307_REG_YEAR] = bin2bcd(tmp);
1abb0dc9 359
be5f59f4
RG
360 switch (ds1307->type) {
361 case ds_1337:
362 case ds_1339:
97f902b7 363 case ds_3231:
1abb0dc9 364 buf[DS1307_REG_MONTH] |= DS1337_BIT_CENTURY;
be5f59f4
RG
365 break;
366 case ds_1340:
1abb0dc9
DB
367 buf[DS1307_REG_HOUR] |= DS1340_BIT_CENTURY_EN
368 | DS1340_BIT_CENTURY;
be5f59f4 369 break;
43fcb815 370 case mcp7941x:
40ce972d
DA
371 /*
372 * these bits were cleared when preparing the date/time
373 * values and need to be set again before writing the
374 * buffer out to the device.
375 */
43fcb815
DA
376 buf[DS1307_REG_SECS] |= MCP7941X_BIT_ST;
377 buf[DS1307_REG_WDAY] |= MCP7941X_BIT_VBATEN;
378 break;
be5f59f4
RG
379 default:
380 break;
381 }
1abb0dc9 382
1abb0dc9
DB
383 dev_dbg(dev, "%s: %02x %02x %02x %02x %02x %02x %02x\n",
384 "write", buf[0], buf[1], buf[2], buf[3],
385 buf[4], buf[5], buf[6]);
386
33df2ee1
JT
387 result = ds1307->write_block_data(ds1307->client,
388 ds1307->offset, 7, buf);
fed40b73
BS
389 if (result < 0) {
390 dev_err(dev, "%s error %d\n", "write", result);
391 return result;
1abb0dc9
DB
392 }
393 return 0;
394}
395
74d88eb2 396static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
cb49a5e9
RG
397{
398 struct i2c_client *client = to_i2c_client(dev);
399 struct ds1307 *ds1307 = i2c_get_clientdata(client);
400 int ret;
401
402 if (!test_bit(HAS_ALARM, &ds1307->flags))
403 return -EINVAL;
404
405 /* read all ALARM1, ALARM2, and status registers at once */
30e7b039 406 ret = ds1307->read_block_data(client,
fed40b73
BS
407 DS1339_REG_ALARM1_SECS, 9, ds1307->regs);
408 if (ret != 9) {
cb49a5e9
RG
409 dev_err(dev, "%s error %d\n", "alarm read", ret);
410 return -EIO;
411 }
412
413 dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
414 "alarm read",
415 ds1307->regs[0], ds1307->regs[1],
416 ds1307->regs[2], ds1307->regs[3],
417 ds1307->regs[4], ds1307->regs[5],
418 ds1307->regs[6], ds1307->regs[7],
419 ds1307->regs[8]);
420
40ce972d
DA
421 /*
422 * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
cb49a5e9
RG
423 * and that all four fields are checked matches
424 */
425 t->time.tm_sec = bcd2bin(ds1307->regs[0] & 0x7f);
426 t->time.tm_min = bcd2bin(ds1307->regs[1] & 0x7f);
427 t->time.tm_hour = bcd2bin(ds1307->regs[2] & 0x3f);
428 t->time.tm_mday = bcd2bin(ds1307->regs[3] & 0x3f);
429 t->time.tm_mon = -1;
430 t->time.tm_year = -1;
431 t->time.tm_wday = -1;
432 t->time.tm_yday = -1;
433 t->time.tm_isdst = -1;
434
435 /* ... and status */
436 t->enabled = !!(ds1307->regs[7] & DS1337_BIT_A1IE);
437 t->pending = !!(ds1307->regs[8] & DS1337_BIT_A1I);
438
439 dev_dbg(dev, "%s secs=%d, mins=%d, "
440 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
441 "alarm read", t->time.tm_sec, t->time.tm_min,
442 t->time.tm_hour, t->time.tm_mday,
443 t->enabled, t->pending);
444
445 return 0;
446}
447
74d88eb2 448static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
cb49a5e9 449{
40ce972d 450 struct i2c_client *client = to_i2c_client(dev);
cb49a5e9
RG
451 struct ds1307 *ds1307 = i2c_get_clientdata(client);
452 unsigned char *buf = ds1307->regs;
453 u8 control, status;
454 int ret;
455
456 if (!test_bit(HAS_ALARM, &ds1307->flags))
457 return -EINVAL;
458
459 dev_dbg(dev, "%s secs=%d, mins=%d, "
460 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
461 "alarm set", t->time.tm_sec, t->time.tm_min,
462 t->time.tm_hour, t->time.tm_mday,
463 t->enabled, t->pending);
464
465 /* read current status of both alarms and the chip */
30e7b039 466 ret = ds1307->read_block_data(client,
fed40b73
BS
467 DS1339_REG_ALARM1_SECS, 9, buf);
468 if (ret != 9) {
cb49a5e9
RG
469 dev_err(dev, "%s error %d\n", "alarm write", ret);
470 return -EIO;
471 }
472 control = ds1307->regs[7];
473 status = ds1307->regs[8];
474
475 dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
476 "alarm set (old status)",
477 ds1307->regs[0], ds1307->regs[1],
478 ds1307->regs[2], ds1307->regs[3],
479 ds1307->regs[4], ds1307->regs[5],
480 ds1307->regs[6], control, status);
481
482 /* set ALARM1, using 24 hour and day-of-month modes */
cb49a5e9
RG
483 buf[0] = bin2bcd(t->time.tm_sec);
484 buf[1] = bin2bcd(t->time.tm_min);
485 buf[2] = bin2bcd(t->time.tm_hour);
486 buf[3] = bin2bcd(t->time.tm_mday);
487
488 /* set ALARM2 to non-garbage */
489 buf[4] = 0;
490 buf[5] = 0;
491 buf[6] = 0;
492
493 /* optionally enable ALARM1 */
494 buf[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
495 if (t->enabled) {
496 dev_dbg(dev, "alarm IRQ armed\n");
497 buf[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
498 }
499 buf[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
500
30e7b039 501 ret = ds1307->write_block_data(client,
fed40b73
BS
502 DS1339_REG_ALARM1_SECS, 9, buf);
503 if (ret < 0) {
cb49a5e9 504 dev_err(dev, "can't set alarm time\n");
fed40b73 505 return ret;
cb49a5e9
RG
506 }
507
508 return 0;
509}
510
16380c15 511static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
cb49a5e9
RG
512{
513 struct i2c_client *client = to_i2c_client(dev);
514 struct ds1307 *ds1307 = i2c_get_clientdata(client);
515 int ret;
516
16380c15
JS
517 if (!test_bit(HAS_ALARM, &ds1307->flags))
518 return -ENOTTY;
cb49a5e9 519
16380c15
JS
520 ret = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
521 if (ret < 0)
522 return ret;
cb49a5e9 523
16380c15 524 if (enabled)
cb49a5e9 525 ret |= DS1337_BIT_A1IE;
16380c15
JS
526 else
527 ret &= ~DS1337_BIT_A1IE;
cb49a5e9 528
16380c15
JS
529 ret = i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, ret);
530 if (ret < 0)
531 return ret;
cb49a5e9
RG
532
533 return 0;
534}
535
ff8371ac 536static const struct rtc_class_ops ds13xx_rtc_ops = {
1abb0dc9
DB
537 .read_time = ds1307_get_time,
538 .set_time = ds1307_set_time,
74d88eb2
JR
539 .read_alarm = ds1337_read_alarm,
540 .set_alarm = ds1337_set_alarm,
16380c15 541 .alarm_irq_enable = ds1307_alarm_irq_enable,
1abb0dc9
DB
542};
543
682d73f6
DB
544/*----------------------------------------------------------------------*/
545
546#define NVRAM_SIZE 56
547
548static ssize_t
2c3c8bea
CW
549ds1307_nvram_read(struct file *filp, struct kobject *kobj,
550 struct bin_attribute *attr,
682d73f6
DB
551 char *buf, loff_t off, size_t count)
552{
553 struct i2c_client *client;
554 struct ds1307 *ds1307;
682d73f6
DB
555 int result;
556
fcd8db00 557 client = kobj_to_i2c_client(kobj);
682d73f6
DB
558 ds1307 = i2c_get_clientdata(client);
559
560 if (unlikely(off >= NVRAM_SIZE))
561 return 0;
562 if ((off + count) > NVRAM_SIZE)
563 count = NVRAM_SIZE - off;
564 if (unlikely(!count))
565 return count;
566
30e7b039 567 result = ds1307->read_block_data(client, 8 + off, count, buf);
fed40b73 568 if (result < 0)
682d73f6 569 dev_err(&client->dev, "%s error %d\n", "nvram read", result);
fed40b73 570 return result;
682d73f6
DB
571}
572
573static ssize_t
2c3c8bea
CW
574ds1307_nvram_write(struct file *filp, struct kobject *kobj,
575 struct bin_attribute *attr,
682d73f6
DB
576 char *buf, loff_t off, size_t count)
577{
578 struct i2c_client *client;
30e7b039 579 struct ds1307 *ds1307;
fed40b73 580 int result;
682d73f6 581
fcd8db00 582 client = kobj_to_i2c_client(kobj);
30e7b039 583 ds1307 = i2c_get_clientdata(client);
682d73f6
DB
584
585 if (unlikely(off >= NVRAM_SIZE))
586 return -EFBIG;
587 if ((off + count) > NVRAM_SIZE)
588 count = NVRAM_SIZE - off;
589 if (unlikely(!count))
590 return count;
591
30e7b039 592 result = ds1307->write_block_data(client, 8 + off, count, buf);
fed40b73
BS
593 if (result < 0) {
594 dev_err(&client->dev, "%s error %d\n", "nvram write", result);
595 return result;
596 }
597 return count;
682d73f6
DB
598}
599
600static struct bin_attribute nvram = {
601 .attr = {
602 .name = "nvram",
603 .mode = S_IRUGO | S_IWUSR,
682d73f6
DB
604 },
605
606 .read = ds1307_nvram_read,
607 .write = ds1307_nvram_write,
608 .size = NVRAM_SIZE,
609};
610
611/*----------------------------------------------------------------------*/
612
d2653e92
JD
613static int __devinit ds1307_probe(struct i2c_client *client,
614 const struct i2c_device_id *id)
1abb0dc9
DB
615{
616 struct ds1307 *ds1307;
617 int err = -ENODEV;
1abb0dc9 618 int tmp;
3760f736 619 const struct chip_desc *chip = &chips[id->driver_data];
c065f35c 620 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
cb49a5e9 621 int want_irq = false;
fed40b73 622 unsigned char *buf;
97f902b7
WS
623 static const int bbsqi_bitpos[] = {
624 [ds_1337] = 0,
625 [ds_1339] = DS1339_BIT_BBSQI,
626 [ds_3231] = DS3231_BIT_BBSQW,
627 };
1abb0dc9 628
30e7b039
ES
629 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)
630 && !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK))
c065f35c
DB
631 return -EIO;
632
40ce972d
DA
633 ds1307 = kzalloc(sizeof(struct ds1307), GFP_KERNEL);
634 if (!ds1307)
c065f35c 635 return -ENOMEM;
045e0e85 636
1abb0dc9 637 i2c_set_clientdata(client, ds1307);
33df2ee1
JT
638
639 ds1307->client = client;
640 ds1307->type = id->driver_data;
641 ds1307->offset = 0;
642
fed40b73 643 buf = ds1307->regs;
30e7b039
ES
644 if (i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) {
645 ds1307->read_block_data = i2c_smbus_read_i2c_block_data;
646 ds1307->write_block_data = i2c_smbus_write_i2c_block_data;
647 } else {
648 ds1307->read_block_data = ds1307_read_block_data;
649 ds1307->write_block_data = ds1307_write_block_data;
650 }
045e0e85
DB
651
652 switch (ds1307->type) {
653 case ds_1337:
654 case ds_1339:
97f902b7 655 case ds_3231:
be5f59f4 656 /* get registers that the "rtc" read below won't read... */
30e7b039 657 tmp = ds1307->read_block_data(ds1307->client,
fed40b73 658 DS1337_REG_CONTROL, 2, buf);
1abb0dc9
DB
659 if (tmp != 2) {
660 pr_debug("read error %d\n", tmp);
661 err = -EIO;
662 goto exit_free;
663 }
664
be5f59f4
RG
665 /* oscillator off? turn it on, so clock can tick. */
666 if (ds1307->regs[0] & DS1337_BIT_nEOSC)
cb49a5e9
RG
667 ds1307->regs[0] &= ~DS1337_BIT_nEOSC;
668
40ce972d
DA
669 /*
670 * Using IRQ? Disable the square wave and both alarms.
97f902b7
WS
671 * For some variants, be sure alarms can trigger when we're
672 * running on Vbackup (BBSQI/BBSQW)
cb49a5e9 673 */
b24a7267
WS
674 if (ds1307->client->irq > 0 && chip->alarm) {
675 INIT_WORK(&ds1307->work, ds1307_work);
676
97f902b7
WS
677 ds1307->regs[0] |= DS1337_BIT_INTCN
678 | bbsqi_bitpos[ds1307->type];
cb49a5e9 679 ds1307->regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
b24a7267
WS
680
681 want_irq = true;
cb49a5e9
RG
682 }
683
684 i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL,
685 ds1307->regs[0]);
be5f59f4
RG
686
687 /* oscillator fault? clear flag, and warn */
688 if (ds1307->regs[1] & DS1337_BIT_OSF) {
689 i2c_smbus_write_byte_data(client, DS1337_REG_STATUS,
690 ds1307->regs[1] & ~DS1337_BIT_OSF);
691 dev_warn(&client->dev, "SET TIME!\n");
1abb0dc9 692 }
045e0e85 693 break;
a2166858
MF
694
695 case rx_8025:
696 tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
697 RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
698 if (tmp != 2) {
699 pr_debug("read error %d\n", tmp);
700 err = -EIO;
701 goto exit_free;
702 }
703
704 /* oscillator off? turn it on, so clock can tick. */
705 if (!(ds1307->regs[1] & RX8025_BIT_XST)) {
706 ds1307->regs[1] |= RX8025_BIT_XST;
707 i2c_smbus_write_byte_data(client,
708 RX8025_REG_CTRL2 << 4 | 0x08,
709 ds1307->regs[1]);
710 dev_warn(&client->dev,
711 "oscillator stop detected - SET TIME!\n");
712 }
713
714 if (ds1307->regs[1] & RX8025_BIT_PON) {
715 ds1307->regs[1] &= ~RX8025_BIT_PON;
716 i2c_smbus_write_byte_data(client,
717 RX8025_REG_CTRL2 << 4 | 0x08,
718 ds1307->regs[1]);
719 dev_warn(&client->dev, "power-on detected\n");
720 }
721
722 if (ds1307->regs[1] & RX8025_BIT_VDET) {
723 ds1307->regs[1] &= ~RX8025_BIT_VDET;
724 i2c_smbus_write_byte_data(client,
725 RX8025_REG_CTRL2 << 4 | 0x08,
726 ds1307->regs[1]);
727 dev_warn(&client->dev, "voltage drop detected\n");
728 }
729
730 /* make sure we are running in 24hour mode */
731 if (!(ds1307->regs[0] & RX8025_BIT_2412)) {
732 u8 hour;
733
734 /* switch to 24 hour mode */
735 i2c_smbus_write_byte_data(client,
736 RX8025_REG_CTRL1 << 4 | 0x08,
737 ds1307->regs[0] |
738 RX8025_BIT_2412);
739
740 tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
741 RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
742 if (tmp != 2) {
743 pr_debug("read error %d\n", tmp);
744 err = -EIO;
745 goto exit_free;
746 }
747
748 /* correct hour */
749 hour = bcd2bin(ds1307->regs[DS1307_REG_HOUR]);
750 if (hour == 12)
751 hour = 0;
752 if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
753 hour += 12;
754
755 i2c_smbus_write_byte_data(client,
756 DS1307_REG_HOUR << 4 | 0x08,
757 hour);
758 }
759 break;
33df2ee1
JT
760 case ds_1388:
761 ds1307->offset = 1; /* Seconds starts at 1 */
762 break;
045e0e85
DB
763 default:
764 break;
765 }
1abb0dc9
DB
766
767read_rtc:
768 /* read RTC registers */
96fc3a45 769 tmp = ds1307->read_block_data(ds1307->client, ds1307->offset, 8, buf);
fed40b73 770 if (tmp != 8) {
1abb0dc9
DB
771 pr_debug("read error %d\n", tmp);
772 err = -EIO;
773 goto exit_free;
774 }
775
40ce972d
DA
776 /*
777 * minimal sanity checking; some chips (like DS1340) don't
1abb0dc9
DB
778 * specify the extra bits as must-be-zero, but there are
779 * still a few values that are clearly out-of-range.
780 */
781 tmp = ds1307->regs[DS1307_REG_SECS];
045e0e85
DB
782 switch (ds1307->type) {
783 case ds_1307:
045e0e85 784 case m41t00:
be5f59f4 785 /* clock halted? turn it on, so clock can tick. */
045e0e85 786 if (tmp & DS1307_BIT_CH) {
be5f59f4
RG
787 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
788 dev_warn(&client->dev, "SET TIME!\n");
045e0e85 789 goto read_rtc;
1abb0dc9 790 }
045e0e85 791 break;
be5f59f4
RG
792 case ds_1338:
793 /* clock halted? turn it on, so clock can tick. */
045e0e85 794 if (tmp & DS1307_BIT_CH)
be5f59f4
RG
795 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
796
797 /* oscillator fault? clear flag, and warn */
798 if (ds1307->regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
799 i2c_smbus_write_byte_data(client, DS1307_REG_CONTROL,
bd16f9eb 800 ds1307->regs[DS1307_REG_CONTROL]
be5f59f4
RG
801 & ~DS1338_BIT_OSF);
802 dev_warn(&client->dev, "SET TIME!\n");
803 goto read_rtc;
804 }
045e0e85 805 break;
fcd8db00
R
806 case ds_1340:
807 /* clock halted? turn it on, so clock can tick. */
808 if (tmp & DS1340_BIT_nEOSC)
809 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
810
811 tmp = i2c_smbus_read_byte_data(client, DS1340_REG_FLAG);
812 if (tmp < 0) {
813 pr_debug("read error %d\n", tmp);
814 err = -EIO;
815 goto exit_free;
816 }
817
818 /* oscillator fault? clear flag, and warn */
819 if (tmp & DS1340_BIT_OSF) {
820 i2c_smbus_write_byte_data(client, DS1340_REG_FLAG, 0);
821 dev_warn(&client->dev, "SET TIME!\n");
822 }
43fcb815
DA
823 break;
824 case mcp7941x:
825 /* make sure that the backup battery is enabled */
826 if (!(ds1307->regs[DS1307_REG_WDAY] & MCP7941X_BIT_VBATEN)) {
827 i2c_smbus_write_byte_data(client, DS1307_REG_WDAY,
828 ds1307->regs[DS1307_REG_WDAY]
829 | MCP7941X_BIT_VBATEN);
830 }
831
832 /* clock halted? turn it on, so clock can tick. */
833 if (!(tmp & MCP7941X_BIT_ST)) {
834 i2c_smbus_write_byte_data(client, DS1307_REG_SECS,
835 MCP7941X_BIT_ST);
836 dev_warn(&client->dev, "SET TIME!\n");
837 goto read_rtc;
838 }
839
fcd8db00 840 break;
32d322bc 841 default:
045e0e85 842 break;
1abb0dc9 843 }
045e0e85 844
1abb0dc9 845 tmp = ds1307->regs[DS1307_REG_HOUR];
c065f35c
DB
846 switch (ds1307->type) {
847 case ds_1340:
848 case m41t00:
40ce972d
DA
849 /*
850 * NOTE: ignores century bits; fix before deploying
c065f35c
DB
851 * systems that will run through year 2100.
852 */
853 break;
a2166858
MF
854 case rx_8025:
855 break;
c065f35c
DB
856 default:
857 if (!(tmp & DS1307_BIT_12HR))
858 break;
859
40ce972d
DA
860 /*
861 * Be sure we're in 24 hour mode. Multi-master systems
c065f35c
DB
862 * take note...
863 */
fe20ba70 864 tmp = bcd2bin(tmp & 0x1f);
c065f35c
DB
865 if (tmp == 12)
866 tmp = 0;
867 if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
868 tmp += 12;
1abb0dc9 869 i2c_smbus_write_byte_data(client,
96fc3a45 870 ds1307->offset + DS1307_REG_HOUR,
fe20ba70 871 bin2bcd(tmp));
1abb0dc9
DB
872 }
873
1abb0dc9
DB
874 ds1307->rtc = rtc_device_register(client->name, &client->dev,
875 &ds13xx_rtc_ops, THIS_MODULE);
876 if (IS_ERR(ds1307->rtc)) {
877 err = PTR_ERR(ds1307->rtc);
878 dev_err(&client->dev,
879 "unable to register the class device\n");
c065f35c 880 goto exit_free;
1abb0dc9
DB
881 }
882
cb49a5e9 883 if (want_irq) {
43d15bcd 884 err = request_irq(client->irq, ds1307_irq, IRQF_SHARED,
cb49a5e9
RG
885 ds1307->rtc->name, client);
886 if (err) {
887 dev_err(&client->dev,
888 "unable to request IRQ!\n");
889 goto exit_irq;
890 }
26b3c01f
AV
891
892 device_set_wakeup_capable(&client->dev, 1);
cb49a5e9
RG
893 set_bit(HAS_ALARM, &ds1307->flags);
894 dev_dbg(&client->dev, "got IRQ %d\n", client->irq);
895 }
896
682d73f6
DB
897 if (chip->nvram56) {
898 err = sysfs_create_bin_file(&client->dev.kobj, &nvram);
899 if (err == 0) {
cb49a5e9 900 set_bit(HAS_NVRAM, &ds1307->flags);
682d73f6
DB
901 dev_info(&client->dev, "56 bytes nvram\n");
902 }
903 }
904
1abb0dc9
DB
905 return 0;
906
cb49a5e9 907exit_irq:
72445af8 908 rtc_device_unregister(ds1307->rtc);
1abb0dc9
DB
909exit_free:
910 kfree(ds1307);
1abb0dc9
DB
911 return err;
912}
913
c065f35c 914static int __devexit ds1307_remove(struct i2c_client *client)
1abb0dc9 915{
40ce972d 916 struct ds1307 *ds1307 = i2c_get_clientdata(client);
cb49a5e9
RG
917
918 if (test_and_clear_bit(HAS_ALARM, &ds1307->flags)) {
919 free_irq(client->irq, client);
920 cancel_work_sync(&ds1307->work);
921 }
1abb0dc9 922
cb49a5e9 923 if (test_and_clear_bit(HAS_NVRAM, &ds1307->flags))
682d73f6
DB
924 sysfs_remove_bin_file(&client->dev.kobj, &nvram);
925
1abb0dc9 926 rtc_device_unregister(ds1307->rtc);
1abb0dc9
DB
927 kfree(ds1307);
928 return 0;
929}
930
931static struct i2c_driver ds1307_driver = {
932 .driver = {
c065f35c 933 .name = "rtc-ds1307",
1abb0dc9
DB
934 .owner = THIS_MODULE,
935 },
c065f35c
DB
936 .probe = ds1307_probe,
937 .remove = __devexit_p(ds1307_remove),
3760f736 938 .id_table = ds1307_id,
1abb0dc9
DB
939};
940
0abc9201 941module_i2c_driver(ds1307_driver);
1abb0dc9
DB
942
943MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
944MODULE_LICENSE("GPL");
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