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rtc: ds1307: fix kernel splat due to wakeup irq handling
[deliverable/linux.git] / drivers / rtc / rtc-ds1307.c
CommitLineData
1abb0dc9
DB		 1/*
2 * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
3 *
4 * Copyright (C) 2005 James Chapman (ds1337 core)
5 * Copyright (C) 2006 David Brownell
a2166858 6 * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
bc48b902 7 * Copyright (C) 2012 Bertrand Achard (nvram access fixes)
1abb0dc9
DB		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
eac7237f
NM		 14#include <linux/bcd.h>
15#include <linux/i2c.h>
1abb0dc9 16#include <linux/init.h>
eac7237f
NM		 17#include <linux/module.h>
18#include <linux/rtc/ds1307.h>
19#include <linux/rtc.h>
1abb0dc9 20#include <linux/slab.h>
1abb0dc9 21#include <linux/string.h>
1abb0dc9 22
40ce972d
DA		 23/*
24 * We can't determine type by probing, but if we expect pre-Linux code
1abb0dc9
DB		 25 * to have set the chip up as a clock (turning on the oscillator and
26 * setting the date and time), Linux can ignore the non-clock features.
27 * That's a natural job for a factory or repair bench.
1abb0dc9
DB		 28 */
29enum ds_type {
045e0e85
DB		 30 ds_1307,
31 ds_1337,
32 ds_1338,
33 ds_1339,
34 ds_1340,
33df2ee1 35 ds_1388,
97f902b7 36 ds_3231,
045e0e85 37 m41t00,
f4199f85 38 mcp794xx,
a2166858 39 rx_8025,
32d322bc 40 last_ds_type /* always last */
40ce972d 41 /* rs5c372 too? different address... */
1abb0dc9
DB		 42};
43
1abb0dc9
DB		 44
45/* RTC registers don't differ much, except for the century flag */
46#define DS1307_REG_SECS 0x00 /* 00-59 */
47# define DS1307_BIT_CH 0x80
be5f59f4 48# define DS1340_BIT_nEOSC 0x80
f4199f85 49# define MCP794XX_BIT_ST 0x80
1abb0dc9
DB		 50#define DS1307_REG_MIN 0x01 /* 00-59 */
51#define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
c065f35c
DB		 52# define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
53# define DS1307_BIT_PM 0x20 /* in REG_HOUR */
1abb0dc9
DB		 54# define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
55# define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
56#define DS1307_REG_WDAY 0x03 /* 01-07 */
f4199f85 57# define MCP794XX_BIT_VBATEN 0x08
1abb0dc9
DB		 58#define DS1307_REG_MDAY 0x04 /* 01-31 */
59#define DS1307_REG_MONTH 0x05 /* 01-12 */
60# define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
61#define DS1307_REG_YEAR 0x06 /* 00-99 */
62
40ce972d
DA		 63/*
64 * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
045e0e85
DB		 65 * start at 7, and they differ a LOT. Only control and status matter for
66 * basic RTC date and time functionality; be careful using them.
1abb0dc9 67 */
045e0e85 68#define DS1307_REG_CONTROL 0x07 /* or ds1338 */
1abb0dc9 69# define DS1307_BIT_OUT 0x80
be5f59f4 70# define DS1338_BIT_OSF 0x20
1abb0dc9
DB		 71# define DS1307_BIT_SQWE 0x10
72# define DS1307_BIT_RS1 0x02
73# define DS1307_BIT_RS0 0x01
74#define DS1337_REG_CONTROL 0x0e
75# define DS1337_BIT_nEOSC 0x80
cb49a5e9 76# define DS1339_BIT_BBSQI 0x20
97f902b7 77# define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
1abb0dc9
DB		 78# define DS1337_BIT_RS2 0x10
79# define DS1337_BIT_RS1 0x08
80# define DS1337_BIT_INTCN 0x04
81# define DS1337_BIT_A2IE 0x02
82# define DS1337_BIT_A1IE 0x01
045e0e85
DB		 83#define DS1340_REG_CONTROL 0x07
84# define DS1340_BIT_OUT 0x80
85# define DS1340_BIT_FT 0x40
86# define DS1340_BIT_CALIB_SIGN 0x20
87# define DS1340_M_CALIBRATION 0x1f
be5f59f4
RG		 88#define DS1340_REG_FLAG 0x09
89# define DS1340_BIT_OSF 0x80
1abb0dc9
DB		 90#define DS1337_REG_STATUS 0x0f
91# define DS1337_BIT_OSF 0x80
92# define DS1337_BIT_A2I 0x02
93# define DS1337_BIT_A1I 0x01
cb49a5e9 94#define DS1339_REG_ALARM1_SECS 0x07
eb86c306
WS		 95
96#define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
1abb0dc9 97
a2166858
MF		 98#define RX8025_REG_CTRL1 0x0e
99# define RX8025_BIT_2412 0x20
100#define RX8025_REG_CTRL2 0x0f
101# define RX8025_BIT_PON 0x10
102# define RX8025_BIT_VDET 0x40
103# define RX8025_BIT_XST 0x20
1abb0dc9
DB		 104
105
106struct ds1307 {
33df2ee1 107 u8 offset; /* register's offset */
cb49a5e9 108 u8 regs[11];
9eab0a78
AB		 109 u16 nvram_offset;
110 struct bin_attribute *nvram;
1abb0dc9 111 enum ds_type type;
cb49a5e9
RG		 112 unsigned long flags;
113#define HAS_NVRAM 0 /* bit 0 == sysfs file active */
114#define HAS_ALARM 1 /* bit 1 == irq claimed */
045e0e85 115 struct i2c_client *client;
1abb0dc9 116 struct rtc_device *rtc;
0cc43a18 117 s32 (*read_block_data)(const struct i2c_client *client, u8 command,
30e7b039 118 u8 length, u8 *values);
0cc43a18 119 s32 (*write_block_data)(const struct i2c_client *client, u8 command,
30e7b039 120 u8 length, const u8 *values);
1abb0dc9
DB		 121};
122
045e0e85 123struct chip_desc {
045e0e85 124 unsigned alarm:1;
9eab0a78
AB		 125 u16 nvram_offset;
126 u16 nvram_size;
eb86c306 127 u16 trickle_charger_reg;
33b04b7b
MV		 128 u8 trickle_charger_setup;
129 u8 (*do_trickle_setup)(struct i2c_client *, uint32_t, bool);
045e0e85
DB		 130};
131
33b04b7b
MV		 132static u8 do_trickle_setup_ds1339(struct i2c_client *,
133 uint32_t ohms, bool diode);
134
135static struct chip_desc chips[last_ds_type] = {
32d322bc 136 [ds_1307] = {
9eab0a78
AB		 137 .nvram_offset = 8,
138 .nvram_size = 56,
32d322bc
WS		 139 },
140 [ds_1337] = {
141 .alarm = 1,
142 },
143 [ds_1338] = {
9eab0a78
AB		 144 .nvram_offset = 8,
145 .nvram_size = 56,
32d322bc
WS		 146 },
147 [ds_1339] = {
148 .alarm = 1,
eb86c306 149 .trickle_charger_reg = 0x10,
33b04b7b 150 .do_trickle_setup = &do_trickle_setup_ds1339,
eb86c306
WS		 151 },
152 [ds_1340] = {
153 .trickle_charger_reg = 0x08,
154 },
155 [ds_1388] = {
156 .trickle_charger_reg = 0x0a,
32d322bc
WS		 157 },
158 [ds_3231] = {
159 .alarm = 1,
160 },
f4199f85 161 [mcp794xx] = {
1d1945d2 162 .alarm = 1,
9eab0a78
AB		 163 /* this is battery backed SRAM */
164 .nvram_offset = 0x20,
165 .nvram_size = 0x40,
166 },
32d322bc 167};
045e0e85 168
3760f736
JD		 169static const struct i2c_device_id ds1307_id[] = {
170 { "ds1307", ds_1307 },
171 { "ds1337", ds_1337 },
172 { "ds1338", ds_1338 },
173 { "ds1339", ds_1339 },
33df2ee1 174 { "ds1388", ds_1388 },
3760f736 175 { "ds1340", ds_1340 },
97f902b7 176 { "ds3231", ds_3231 },
3760f736 177 { "m41t00", m41t00 },
f4199f85
TN		 178 { "mcp7940x", mcp794xx },
179 { "mcp7941x", mcp794xx },
31c1771c 180 { "pt7c4338", ds_1307 },
a2166858 181 { "rx8025", rx_8025 },
3760f736
JD		 182 { }
183};
184MODULE_DEVICE_TABLE(i2c, ds1307_id);
1abb0dc9 185
cb49a5e9
RG		 186/*----------------------------------------------------------------------*/
187
30e7b039
ES		 188#define BLOCK_DATA_MAX_TRIES 10
189
0cc43a18
JD		 190static s32 ds1307_read_block_data_once(const struct i2c_client *client,
191 u8 command, u8 length, u8 *values)
30e7b039
ES		 192{
193 s32 i, data;
194
195 for (i = 0; i < length; i++) {
196 data = i2c_smbus_read_byte_data(client, command + i);
197 if (data < 0)
198 return data;
199 values[i] = data;
200 }
201 return i;
202}
203
0cc43a18 204static s32 ds1307_read_block_data(const struct i2c_client *client, u8 command,
30e7b039
ES		 205 u8 length, u8 *values)
206{
bc48b902 207 u8 oldvalues[255];
30e7b039
ES		 208 s32 ret;
209 int tries = 0;
210
211 dev_dbg(&client->dev, "ds1307_read_block_data (length=%d)\n", length);
212 ret = ds1307_read_block_data_once(client, command, length, values);
213 if (ret < 0)
214 return ret;
215 do {
216 if (++tries > BLOCK_DATA_MAX_TRIES) {
217 dev_err(&client->dev,
218 "ds1307_read_block_data failed\n");
219 return -EIO;
220 }
221 memcpy(oldvalues, values, length);
222 ret = ds1307_read_block_data_once(client, command, length,
223 values);
224 if (ret < 0)
225 return ret;
226 } while (memcmp(oldvalues, values, length));
227 return length;
228}
229
0cc43a18 230static s32 ds1307_write_block_data(const struct i2c_client *client, u8 command,
30e7b039
ES		 231 u8 length, const u8 *values)
232{
bc48b902 233 u8 currvalues[255];
30e7b039
ES		 234 int tries = 0;
235
236 dev_dbg(&client->dev, "ds1307_write_block_data (length=%d)\n", length);
237 do {
238 s32 i, ret;
239
240 if (++tries > BLOCK_DATA_MAX_TRIES) {
241 dev_err(&client->dev,
242 "ds1307_write_block_data failed\n");
243 return -EIO;
244 }
245 for (i = 0; i < length; i++) {
246 ret = i2c_smbus_write_byte_data(client, command + i,
247 values[i]);
248 if (ret < 0)
249 return ret;
250 }
251 ret = ds1307_read_block_data_once(client, command, length,
252 currvalues);
253 if (ret < 0)
254 return ret;
255 } while (memcmp(currvalues, values, length));
256 return length;
257}
258
259/*----------------------------------------------------------------------*/
260
bc48b902
BA		 261/* These RTC devices are not designed to be connected to a SMbus adapter.
262 SMbus limits block operations length to 32 bytes, whereas it's not
263 limited on I2C buses. As a result, accesses may exceed 32 bytes;
264 in that case, split them into smaller blocks */
265
266static s32 ds1307_native_smbus_write_block_data(const struct i2c_client *client,
267 u8 command, u8 length, const u8 *values)
268{
269 u8 suboffset = 0;
270
271 if (length <= I2C_SMBUS_BLOCK_MAX)
272 return i2c_smbus_write_i2c_block_data(client,
273 command, length, values);
274
275 while (suboffset < length) {
276 s32 retval = i2c_smbus_write_i2c_block_data(client,
277 command + suboffset,
278 min(I2C_SMBUS_BLOCK_MAX, length - suboffset),
279 values + suboffset);
280 if (retval < 0)
281 return retval;
282
283 suboffset += I2C_SMBUS_BLOCK_MAX;
284 }
285 return length;
286}
287
288static s32 ds1307_native_smbus_read_block_data(const struct i2c_client *client,
289 u8 command, u8 length, u8 *values)
290{
291 u8 suboffset = 0;
292
293 if (length <= I2C_SMBUS_BLOCK_MAX)
294 return i2c_smbus_read_i2c_block_data(client,
295 command, length, values);
296
297 while (suboffset < length) {
298 s32 retval = i2c_smbus_read_i2c_block_data(client,
299 command + suboffset,
300 min(I2C_SMBUS_BLOCK_MAX, length - suboffset),
301 values + suboffset);
302 if (retval < 0)
303 return retval;
304
305 suboffset += I2C_SMBUS_BLOCK_MAX;
306 }
307 return length;
308}
309
310/*----------------------------------------------------------------------*/
311
cb49a5e9 312/*
cb49a5e9
RG		 313 * The ds1337 and ds1339 both have two alarms, but we only use the first
314 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
315 * signal; ds1339 chips have only one alarm signal.
316 */
2fb07a10 317static irqreturn_t ds1307_irq(int irq, void *dev_id)
cb49a5e9 318{
2fb07a10
FB		 319 struct i2c_client *client = dev_id;
320 struct ds1307 *ds1307 = i2c_get_clientdata(client);
321 struct mutex *lock = &ds1307->rtc->ops_lock;
cb49a5e9
RG		 322 int stat, control;
323
cb49a5e9
RG		 324 mutex_lock(lock);
325 stat = i2c_smbus_read_byte_data(client, DS1337_REG_STATUS);
326 if (stat < 0)
327 goto out;
328
329 if (stat & DS1337_BIT_A1I) {
330 stat &= ~DS1337_BIT_A1I;
331 i2c_smbus_write_byte_data(client, DS1337_REG_STATUS, stat);
332
333 control = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
334 if (control < 0)
335 goto out;
336
337 control &= ~DS1337_BIT_A1IE;
338 i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, control);
339
cb49a5e9 340 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
cb49a5e9
RG		 341 }
342
343out:
cb49a5e9 344 mutex_unlock(lock);
cb49a5e9 345
cb49a5e9
RG		 346 return IRQ_HANDLED;
347}
348
349/*----------------------------------------------------------------------*/
350
1abb0dc9
DB		 351static int ds1307_get_time(struct device *dev, struct rtc_time *t)
352{
353 struct ds1307 *ds1307 = dev_get_drvdata(dev);
354 int tmp;
355
045e0e85 356 /* read the RTC date and time registers all at once */
30e7b039 357 tmp = ds1307->read_block_data(ds1307->client,
33df2ee1 358 ds1307->offset, 7, ds1307->regs);
fed40b73 359 if (tmp != 7) {
1abb0dc9
DB		 360 dev_err(dev, "%s error %d\n", "read", tmp);
361 return -EIO;
362 }
363
01a4ca16 364 dev_dbg(dev, "%s: %7ph\n", "read", ds1307->regs);
1abb0dc9 365
fe20ba70
AB		 366 t->tm_sec = bcd2bin(ds1307->regs[DS1307_REG_SECS] & 0x7f);
367 t->tm_min = bcd2bin(ds1307->regs[DS1307_REG_MIN] & 0x7f);
1abb0dc9 368 tmp = ds1307->regs[DS1307_REG_HOUR] & 0x3f;
fe20ba70
AB		 369 t->tm_hour = bcd2bin(tmp);
370 t->tm_wday = bcd2bin(ds1307->regs[DS1307_REG_WDAY] & 0x07) - 1;
371 t->tm_mday = bcd2bin(ds1307->regs[DS1307_REG_MDAY] & 0x3f);
1abb0dc9 372 tmp = ds1307->regs[DS1307_REG_MONTH] & 0x1f;
fe20ba70 373 t->tm_mon = bcd2bin(tmp) - 1;
1abb0dc9
DB		 374
375 /* assume 20YY not 19YY, and ignore DS1337_BIT_CENTURY */
fe20ba70 376 t->tm_year = bcd2bin(ds1307->regs[DS1307_REG_YEAR]) + 100;
1abb0dc9
DB		 377
378 dev_dbg(dev, "%s secs=%d, mins=%d, "
379 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
380 "read", t->tm_sec, t->tm_min,
381 t->tm_hour, t->tm_mday,
382 t->tm_mon, t->tm_year, t->tm_wday);
383
045e0e85
DB		 384 /* initial clock setting can be undefined */
385 return rtc_valid_tm(t);
1abb0dc9
DB		 386}
387
388static int ds1307_set_time(struct device *dev, struct rtc_time *t)
389{
390 struct ds1307 *ds1307 = dev_get_drvdata(dev);
391 int result;
392 int tmp;
393 u8 *buf = ds1307->regs;
394
395 dev_dbg(dev, "%s secs=%d, mins=%d, "
396 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
11966adc
JG		 397 "write", t->tm_sec, t->tm_min,
398 t->tm_hour, t->tm_mday,
399 t->tm_mon, t->tm_year, t->tm_wday);
1abb0dc9 400
fe20ba70
AB		 401 buf[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
402 buf[DS1307_REG_MIN] = bin2bcd(t->tm_min);
403 buf[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
404 buf[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
405 buf[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
406 buf[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
1abb0dc9
DB		 407
408 /* assume 20YY not 19YY */
409 tmp = t->tm_year - 100;
fe20ba70 410 buf[DS1307_REG_YEAR] = bin2bcd(tmp);
1abb0dc9 411
be5f59f4
RG		 412 switch (ds1307->type) {
413 case ds_1337:
414 case ds_1339:
97f902b7 415 case ds_3231:
1abb0dc9 416 buf[DS1307_REG_MONTH] |= DS1337_BIT_CENTURY;
be5f59f4
RG		 417 break;
418 case ds_1340:
1abb0dc9
DB		 419 buf[DS1307_REG_HOUR] |= DS1340_BIT_CENTURY_EN
420 | DS1340_BIT_CENTURY;
be5f59f4 421 break;
f4199f85 422 case mcp794xx:
40ce972d
DA		 423 /*
424 * these bits were cleared when preparing the date/time
425 * values and need to be set again before writing the
426 * buffer out to the device.
427 */
f4199f85
TN		 428 buf[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
429 buf[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
43fcb815 430 break;
be5f59f4
RG		 431 default:
432 break;
433 }
1abb0dc9 434
01a4ca16 435 dev_dbg(dev, "%s: %7ph\n", "write", buf);
1abb0dc9 436
33df2ee1
JT		 437 result = ds1307->write_block_data(ds1307->client,
438 ds1307->offset, 7, buf);
fed40b73
BS		 439 if (result < 0) {
440 dev_err(dev, "%s error %d\n", "write", result);
441 return result;
1abb0dc9
DB		 442 }
443 return 0;
444}
445
74d88eb2 446static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
cb49a5e9
RG		 447{
448 struct i2c_client *client = to_i2c_client(dev);
449 struct ds1307 *ds1307 = i2c_get_clientdata(client);
450 int ret;
451
452 if (!test_bit(HAS_ALARM, &ds1307->flags))
453 return -EINVAL;
454
455 /* read all ALARM1, ALARM2, and status registers at once */
30e7b039 456 ret = ds1307->read_block_data(client,
fed40b73
BS		 457 DS1339_REG_ALARM1_SECS, 9, ds1307->regs);
458 if (ret != 9) {
cb49a5e9
RG		 459 dev_err(dev, "%s error %d\n", "alarm read", ret);
460 return -EIO;
461 }
462
463 dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
464 "alarm read",
465 ds1307->regs[0], ds1307->regs[1],
466 ds1307->regs[2], ds1307->regs[3],
467 ds1307->regs[4], ds1307->regs[5],
468 ds1307->regs[6], ds1307->regs[7],
469 ds1307->regs[8]);
470
40ce972d
DA		 471 /*
472 * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
cb49a5e9
RG		 473 * and that all four fields are checked matches
474 */
475 t->time.tm_sec = bcd2bin(ds1307->regs[0] & 0x7f);
476 t->time.tm_min = bcd2bin(ds1307->regs[1] & 0x7f);
477 t->time.tm_hour = bcd2bin(ds1307->regs[2] & 0x3f);
478 t->time.tm_mday = bcd2bin(ds1307->regs[3] & 0x3f);
479 t->time.tm_mon = -1;
480 t->time.tm_year = -1;
481 t->time.tm_wday = -1;
482 t->time.tm_yday = -1;
483 t->time.tm_isdst = -1;
484
485 /* ... and status */
486 t->enabled = !!(ds1307->regs[7] & DS1337_BIT_A1IE);
487 t->pending = !!(ds1307->regs[8] & DS1337_BIT_A1I);
488
489 dev_dbg(dev, "%s secs=%d, mins=%d, "
490 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
491 "alarm read", t->time.tm_sec, t->time.tm_min,
492 t->time.tm_hour, t->time.tm_mday,
493 t->enabled, t->pending);
494
495 return 0;
496}
497
74d88eb2 498static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
cb49a5e9 499{
40ce972d 500 struct i2c_client *client = to_i2c_client(dev);
cb49a5e9
RG		 501 struct ds1307 *ds1307 = i2c_get_clientdata(client);
502 unsigned char *buf = ds1307->regs;
503 u8 control, status;
504 int ret;
505
506 if (!test_bit(HAS_ALARM, &ds1307->flags))
507 return -EINVAL;
508
509 dev_dbg(dev, "%s secs=%d, mins=%d, "
510 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
511 "alarm set", t->time.tm_sec, t->time.tm_min,
512 t->time.tm_hour, t->time.tm_mday,
513 t->enabled, t->pending);
514
515 /* read current status of both alarms and the chip */
30e7b039 516 ret = ds1307->read_block_data(client,
fed40b73
BS		 517 DS1339_REG_ALARM1_SECS, 9, buf);
518 if (ret != 9) {
cb49a5e9
RG		 519 dev_err(dev, "%s error %d\n", "alarm write", ret);
520 return -EIO;
521 }
522 control = ds1307->regs[7];
523 status = ds1307->regs[8];
524
525 dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
526 "alarm set (old status)",
527 ds1307->regs[0], ds1307->regs[1],
528 ds1307->regs[2], ds1307->regs[3],
529 ds1307->regs[4], ds1307->regs[5],
530 ds1307->regs[6], control, status);
531
532 /* set ALARM1, using 24 hour and day-of-month modes */
cb49a5e9
RG		 533 buf[0] = bin2bcd(t->time.tm_sec);
534 buf[1] = bin2bcd(t->time.tm_min);
535 buf[2] = bin2bcd(t->time.tm_hour);
536 buf[3] = bin2bcd(t->time.tm_mday);
537
538 /* set ALARM2 to non-garbage */
539 buf[4] = 0;
540 buf[5] = 0;
541 buf[6] = 0;
542
543 /* optionally enable ALARM1 */
544 buf[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
545 if (t->enabled) {
546 dev_dbg(dev, "alarm IRQ armed\n");
547 buf[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
548 }
549 buf[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
550
30e7b039 551 ret = ds1307->write_block_data(client,
fed40b73
BS		 552 DS1339_REG_ALARM1_SECS, 9, buf);
553 if (ret < 0) {
cb49a5e9 554 dev_err(dev, "can't set alarm time\n");
fed40b73 555 return ret;
cb49a5e9
RG		 556 }
557
558 return 0;
559}
560
16380c15 561static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
cb49a5e9
RG		 562{
563 struct i2c_client *client = to_i2c_client(dev);
564 struct ds1307 *ds1307 = i2c_get_clientdata(client);
565 int ret;
566
16380c15
JS		 567 if (!test_bit(HAS_ALARM, &ds1307->flags))
568 return -ENOTTY;
cb49a5e9 569
16380c15
JS		 570 ret = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
571 if (ret < 0)
572 return ret;
cb49a5e9 573
16380c15 574 if (enabled)
cb49a5e9 575 ret |= DS1337_BIT_A1IE;
16380c15
JS		 576 else
577 ret &= ~DS1337_BIT_A1IE;
cb49a5e9 578
16380c15
JS		 579 ret = i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, ret);
580 if (ret < 0)
581 return ret;
cb49a5e9
RG		 582
583 return 0;
584}
585
ff8371ac 586static const struct rtc_class_ops ds13xx_rtc_ops = {
1abb0dc9
DB		 587 .read_time = ds1307_get_time,
588 .set_time = ds1307_set_time,
74d88eb2
JR		 589 .read_alarm = ds1337_read_alarm,
590 .set_alarm = ds1337_set_alarm,
16380c15 591 .alarm_irq_enable = ds1307_alarm_irq_enable,
1abb0dc9
DB		 592};
593
682d73f6
DB		 594/*----------------------------------------------------------------------*/
595
1d1945d2 596/*
f4199f85 597 * Alarm support for mcp794xx devices.
1d1945d2
SG		 598 */
599
f4199f85
TN		 600#define MCP794XX_REG_CONTROL 0x07
601# define MCP794XX_BIT_ALM0_EN 0x10
602# define MCP794XX_BIT_ALM1_EN 0x20
603#define MCP794XX_REG_ALARM0_BASE 0x0a
604#define MCP794XX_REG_ALARM0_CTRL 0x0d
605#define MCP794XX_REG_ALARM1_BASE 0x11
606#define MCP794XX_REG_ALARM1_CTRL 0x14
607# define MCP794XX_BIT_ALMX_IF (1 << 3)
608# define MCP794XX_BIT_ALMX_C0 (1 << 4)
609# define MCP794XX_BIT_ALMX_C1 (1 << 5)
610# define MCP794XX_BIT_ALMX_C2 (1 << 6)
611# define MCP794XX_BIT_ALMX_POL (1 << 7)
612# define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
613 MCP794XX_BIT_ALMX_C1 | \
614 MCP794XX_BIT_ALMX_C2)
615
2fb07a10 616static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
1d1945d2 617{
2fb07a10
FB		 618 struct i2c_client *client = dev_id;
619 struct ds1307 *ds1307 = i2c_get_clientdata(client);
620 struct mutex *lock = &ds1307->rtc->ops_lock;
1d1945d2
SG		 621 int reg, ret;
622
2fb07a10 623 mutex_lock(lock);
1d1945d2
SG		 624
625 /* Check and clear alarm 0 interrupt flag. */
f4199f85 626 reg = i2c_smbus_read_byte_data(client, MCP794XX_REG_ALARM0_CTRL);
1d1945d2
SG		 627 if (reg < 0)
628 goto out;
f4199f85 629 if (!(reg & MCP794XX_BIT_ALMX_IF))
1d1945d2 630 goto out;
f4199f85
TN		 631 reg &= ~MCP794XX_BIT_ALMX_IF;
632 ret = i2c_smbus_write_byte_data(client, MCP794XX_REG_ALARM0_CTRL, reg);
1d1945d2
SG		 633 if (ret < 0)
634 goto out;
635
636 /* Disable alarm 0. */
f4199f85 637 reg = i2c_smbus_read_byte_data(client, MCP794XX_REG_CONTROL);
1d1945d2
SG		 638 if (reg < 0)
639 goto out;
f4199f85
TN		 640 reg &= ~MCP794XX_BIT_ALM0_EN;
641 ret = i2c_smbus_write_byte_data(client, MCP794XX_REG_CONTROL, reg);
1d1945d2
SG		 642 if (ret < 0)
643 goto out;
644
645 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
646
647out:
2fb07a10
FB		 648 mutex_unlock(lock);
649
650 return IRQ_HANDLED;
1d1945d2
SG		 651}
652
f4199f85 653static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
1d1945d2
SG		 654{
655 struct i2c_client *client = to_i2c_client(dev);
656 struct ds1307 *ds1307 = i2c_get_clientdata(client);
657 u8 *regs = ds1307->regs;
658 int ret;
659
660 if (!test_bit(HAS_ALARM, &ds1307->flags))
661 return -EINVAL;
662
663 /* Read control and alarm 0 registers. */
f4199f85 664 ret = ds1307->read_block_data(client, MCP794XX_REG_CONTROL, 10, regs);
1d1945d2
SG		 665 if (ret < 0)
666 return ret;
667
f4199f85 668 t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
1d1945d2
SG		 669
670 /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
671 t->time.tm_sec = bcd2bin(ds1307->regs[3] & 0x7f);
672 t->time.tm_min = bcd2bin(ds1307->regs[4] & 0x7f);
673 t->time.tm_hour = bcd2bin(ds1307->regs[5] & 0x3f);
674 t->time.tm_wday = bcd2bin(ds1307->regs[6] & 0x7) - 1;
675 t->time.tm_mday = bcd2bin(ds1307->regs[7] & 0x3f);
676 t->time.tm_mon = bcd2bin(ds1307->regs[8] & 0x1f) - 1;
677 t->time.tm_year = -1;
678 t->time.tm_yday = -1;
679 t->time.tm_isdst = -1;
680
681 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
682 "enabled=%d polarity=%d irq=%d match=%d\n", __func__,
683 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
684 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
f4199f85
TN		 685 !!(ds1307->regs[6] & MCP794XX_BIT_ALMX_POL),
686 !!(ds1307->regs[6] & MCP794XX_BIT_ALMX_IF),
687 (ds1307->regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
1d1945d2
SG		 688
689 return 0;
690}
691
f4199f85 692static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
1d1945d2
SG		 693{
694 struct i2c_client *client = to_i2c_client(dev);
695 struct ds1307 *ds1307 = i2c_get_clientdata(client);
696 unsigned char *regs = ds1307->regs;
697 int ret;
698
699 if (!test_bit(HAS_ALARM, &ds1307->flags))
700 return -EINVAL;
701
702 dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
703 "enabled=%d pending=%d\n", __func__,
704 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
705 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
706 t->enabled, t->pending);
707
708 /* Read control and alarm 0 registers. */
f4199f85 709 ret = ds1307->read_block_data(client, MCP794XX_REG_CONTROL, 10, regs);
1d1945d2
SG		 710 if (ret < 0)
711 return ret;
712
713 /* Set alarm 0, using 24-hour and day-of-month modes. */
714 regs[3] = bin2bcd(t->time.tm_sec);
715 regs[4] = bin2bcd(t->time.tm_min);
716 regs[5] = bin2bcd(t->time.tm_hour);
62c8c20a 717 regs[6] = bin2bcd(t->time.tm_wday + 1);
1d1945d2 718 regs[7] = bin2bcd(t->time.tm_mday);
62c8c20a 719 regs[8] = bin2bcd(t->time.tm_mon + 1);
1d1945d2
SG		 720
721 /* Clear the alarm 0 interrupt flag. */
f4199f85 722 regs[6] &= ~MCP794XX_BIT_ALMX_IF;
1d1945d2 723 /* Set alarm match: second, minute, hour, day, date, month. */
f4199f85 724 regs[6] |= MCP794XX_MSK_ALMX_MATCH;
e3edd671
NM		 725 /* Disable interrupt. We will not enable until completely programmed */
726 regs[0] &= ~MCP794XX_BIT_ALM0_EN;
1d1945d2 727
f4199f85 728 ret = ds1307->write_block_data(client, MCP794XX_REG_CONTROL, 10, regs);
1d1945d2
SG		 729 if (ret < 0)
730 return ret;
731
e3edd671
NM		 732 if (!t->enabled)
733 return 0;
734 regs[0] |= MCP794XX_BIT_ALM0_EN;
735 return i2c_smbus_write_byte_data(client, MCP794XX_REG_CONTROL, regs[0]);
1d1945d2
SG		 736}
737
f4199f85 738static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
1d1945d2
SG		 739{
740 struct i2c_client *client = to_i2c_client(dev);
741 struct ds1307 *ds1307 = i2c_get_clientdata(client);
742 int reg;
743
744 if (!test_bit(HAS_ALARM, &ds1307->flags))
745 return -EINVAL;
746
f4199f85 747 reg = i2c_smbus_read_byte_data(client, MCP794XX_REG_CONTROL);
1d1945d2
SG		 748 if (reg < 0)
749 return reg;
750
751 if (enabled)
f4199f85 752 reg |= MCP794XX_BIT_ALM0_EN;
1d1945d2 753 else
f4199f85 754 reg &= ~MCP794XX_BIT_ALM0_EN;
1d1945d2 755
f4199f85 756 return i2c_smbus_write_byte_data(client, MCP794XX_REG_CONTROL, reg);
1d1945d2
SG		 757}
758
f4199f85 759static const struct rtc_class_ops mcp794xx_rtc_ops = {
1d1945d2
SG		 760 .read_time = ds1307_get_time,
761 .set_time = ds1307_set_time,
f4199f85
TN		 762 .read_alarm = mcp794xx_read_alarm,
763 .set_alarm = mcp794xx_set_alarm,
764 .alarm_irq_enable = mcp794xx_alarm_irq_enable,
1d1945d2
SG		 765};
766
767/*----------------------------------------------------------------------*/
768
682d73f6 769static ssize_t
2c3c8bea
CW		 770ds1307_nvram_read(struct file *filp, struct kobject *kobj,
771 struct bin_attribute *attr,
682d73f6
DB		 772 char *buf, loff_t off, size_t count)
773{
774 struct i2c_client *client;
775 struct ds1307 *ds1307;
682d73f6
DB		 776 int result;
777
fcd8db00 778 client = kobj_to_i2c_client(kobj);
682d73f6
DB		 779 ds1307 = i2c_get_clientdata(client);
780
9eab0a78
AB		 781 result = ds1307->read_block_data(client, ds1307->nvram_offset + off,
782 count, buf);
fed40b73 783 if (result < 0)
682d73f6 784 dev_err(&client->dev, "%s error %d\n", "nvram read", result);
fed40b73 785 return result;
682d73f6
DB		 786}
787
788static ssize_t
2c3c8bea
CW		 789ds1307_nvram_write(struct file *filp, struct kobject *kobj,
790 struct bin_attribute *attr,
682d73f6
DB		 791 char *buf, loff_t off, size_t count)
792{
793 struct i2c_client *client;
30e7b039 794 struct ds1307 *ds1307;
fed40b73 795 int result;
682d73f6 796
fcd8db00 797 client = kobj_to_i2c_client(kobj);
30e7b039 798 ds1307 = i2c_get_clientdata(client);
682d73f6 799
9eab0a78
AB		 800 result = ds1307->write_block_data(client, ds1307->nvram_offset + off,
801 count, buf);
fed40b73
BS		 802 if (result < 0) {
803 dev_err(&client->dev, "%s error %d\n", "nvram write", result);
804 return result;
805 }
806 return count;
682d73f6
DB		 807}
808
33b04b7b 809
682d73f6
DB		 810/*----------------------------------------------------------------------*/
811
33b04b7b
MV		 812static u8 do_trickle_setup_ds1339(struct i2c_client *client,
813 uint32_t ohms, bool diode)
814{
815 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
816 DS1307_TRICKLE_CHARGER_NO_DIODE;
817
818 switch (ohms) {
819 case 250:
820 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
821 break;
822 case 2000:
823 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
824 break;
825 case 4000:
826 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
827 break;
828 default:
829 dev_warn(&client->dev,
830 "Unsupported ohm value %u in dt\n", ohms);
831 return 0;
832 }
833 return setup;
834}
835
836static void ds1307_trickle_of_init(struct i2c_client *client,
837 struct chip_desc *chip)
838{
839 uint32_t ohms = 0;
840 bool diode = true;
841
842 if (!chip->do_trickle_setup)
843 goto out;
844 if (of_property_read_u32(client->dev.of_node, "trickle-resistor-ohms" , &ohms))
845 goto out;
846 if (of_property_read_bool(client->dev.of_node, "trickle-diode-disable"))
847 diode = false;
848 chip->trickle_charger_setup = chip->do_trickle_setup(client,
849 ohms, diode);
850out:
851 return;
852}
853
5a167f45
GKH		 854static int ds1307_probe(struct i2c_client *client,
855 const struct i2c_device_id *id)
1abb0dc9
DB		 856{
857 struct ds1307 *ds1307;
858 int err = -ENODEV;
1abb0dc9 859 int tmp;
33b04b7b 860 struct chip_desc *chip = &chips[id->driver_data];
c065f35c 861 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
c8b18da7 862 bool want_irq = false;
fed40b73 863 unsigned char *buf;
01ce893d 864 struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
2fb07a10
FB		 865 irq_handler_t irq_handler = ds1307_irq;
866
97f902b7
WS		 867 static const int bbsqi_bitpos[] = {
868 [ds_1337] = 0,
869 [ds_1339] = DS1339_BIT_BBSQI,
870 [ds_3231] = DS3231_BIT_BBSQW,
871 };
1d1945d2 872 const struct rtc_class_ops *rtc_ops = &ds13xx_rtc_ops;
1abb0dc9 873
30e7b039
ES		 874 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)
875 && !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK))
c065f35c
DB		 876 return -EIO;
877
edca66d2 878 ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
40ce972d 879 if (!ds1307)
c065f35c 880 return -ENOMEM;
045e0e85 881
1abb0dc9 882 i2c_set_clientdata(client, ds1307);
33df2ee1
JT		 883
884 ds1307->client = client;
885 ds1307->type = id->driver_data;
33df2ee1 886
33b04b7b
MV		 887 if (!pdata && client->dev.of_node)
888 ds1307_trickle_of_init(client, chip);
889 else if (pdata && pdata->trickle_charger_setup)
890 chip->trickle_charger_setup = pdata->trickle_charger_setup;
891
892 if (chip->trickle_charger_setup && chip->trickle_charger_reg) {
893 dev_dbg(&client->dev, "writing trickle charger info 0x%x to 0x%x\n",
894 DS13XX_TRICKLE_CHARGER_MAGIC | chip->trickle_charger_setup,
895 chip->trickle_charger_reg);
eb86c306 896 i2c_smbus_write_byte_data(client, chip->trickle_charger_reg,
33b04b7b
MV		 897 DS13XX_TRICKLE_CHARGER_MAGIC |
898 chip->trickle_charger_setup);
899 }
eb86c306 900
fed40b73 901 buf = ds1307->regs;
30e7b039 902 if (i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) {
bc48b902
BA		 903 ds1307->read_block_data = ds1307_native_smbus_read_block_data;
904 ds1307->write_block_data = ds1307_native_smbus_write_block_data;
30e7b039
ES		 905 } else {
906 ds1307->read_block_data = ds1307_read_block_data;
907 ds1307->write_block_data = ds1307_write_block_data;
908 }
045e0e85
DB		 909
910 switch (ds1307->type) {
911 case ds_1337:
912 case ds_1339:
97f902b7 913 case ds_3231:
be5f59f4 914 /* get registers that the "rtc" read below won't read... */
30e7b039 915 tmp = ds1307->read_block_data(ds1307->client,
fed40b73 916 DS1337_REG_CONTROL, 2, buf);
1abb0dc9 917 if (tmp != 2) {
6df80e21 918 dev_dbg(&client->dev, "read error %d\n", tmp);
1abb0dc9 919 err = -EIO;
edca66d2 920 goto exit;
1abb0dc9
DB		 921 }
922
be5f59f4
RG		 923 /* oscillator off? turn it on, so clock can tick. */
924 if (ds1307->regs[0] & DS1337_BIT_nEOSC)
cb49a5e9
RG		 925 ds1307->regs[0] &= ~DS1337_BIT_nEOSC;
926
40ce972d
DA		 927 /*
928 * Using IRQ? Disable the square wave and both alarms.
97f902b7
WS		 929 * For some variants, be sure alarms can trigger when we're
930 * running on Vbackup (BBSQI/BBSQW)
cb49a5e9 931 */
b24a7267 932 if (ds1307->client->irq > 0 && chip->alarm) {
97f902b7
WS		 933 ds1307->regs[0] |= DS1337_BIT_INTCN
934 | bbsqi_bitpos[ds1307->type];
cb49a5e9 935 ds1307->regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
b24a7267
WS		 936
937 want_irq = true;
cb49a5e9
RG		 938 }
939
940 i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL,
941 ds1307->regs[0]);
be5f59f4
RG		 942
943 /* oscillator fault? clear flag, and warn */
944 if (ds1307->regs[1] & DS1337_BIT_OSF) {
945 i2c_smbus_write_byte_data(client, DS1337_REG_STATUS,
946 ds1307->regs[1] & ~DS1337_BIT_OSF);
947 dev_warn(&client->dev, "SET TIME!\n");
1abb0dc9 948 }
045e0e85 949 break;
a2166858
MF		 950
951 case rx_8025:
952 tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
953 RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
954 if (tmp != 2) {
6df80e21 955 dev_dbg(&client->dev, "read error %d\n", tmp);
a2166858 956 err = -EIO;
edca66d2 957 goto exit;
a2166858
MF		 958 }
959
960 /* oscillator off? turn it on, so clock can tick. */
961 if (!(ds1307->regs[1] & RX8025_BIT_XST)) {
962 ds1307->regs[1] |= RX8025_BIT_XST;
963 i2c_smbus_write_byte_data(client,
964 RX8025_REG_CTRL2 << 4 | 0x08,
965 ds1307->regs[1]);
966 dev_warn(&client->dev,
967 "oscillator stop detected - SET TIME!\n");
968 }
969
970 if (ds1307->regs[1] & RX8025_BIT_PON) {
971 ds1307->regs[1] &= ~RX8025_BIT_PON;
972 i2c_smbus_write_byte_data(client,
973 RX8025_REG_CTRL2 << 4 | 0x08,
974 ds1307->regs[1]);
975 dev_warn(&client->dev, "power-on detected\n");
976 }
977
978 if (ds1307->regs[1] & RX8025_BIT_VDET) {
979 ds1307->regs[1] &= ~RX8025_BIT_VDET;
980 i2c_smbus_write_byte_data(client,
981 RX8025_REG_CTRL2 << 4 | 0x08,
982 ds1307->regs[1]);
983 dev_warn(&client->dev, "voltage drop detected\n");
984 }
985
986 /* make sure we are running in 24hour mode */
987 if (!(ds1307->regs[0] & RX8025_BIT_2412)) {
988 u8 hour;
989
990 /* switch to 24 hour mode */
991 i2c_smbus_write_byte_data(client,
992 RX8025_REG_CTRL1 << 4 | 0x08,
993 ds1307->regs[0] |
994 RX8025_BIT_2412);
995
996 tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
997 RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
998 if (tmp != 2) {
6df80e21 999 dev_dbg(&client->dev, "read error %d\n", tmp);
a2166858 1000 err = -EIO;
edca66d2 1001 goto exit;
a2166858
MF		 1002 }
1003
1004 /* correct hour */
1005 hour = bcd2bin(ds1307->regs[DS1307_REG_HOUR]);
1006 if (hour == 12)
1007 hour = 0;
1008 if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1009 hour += 12;
1010
1011 i2c_smbus_write_byte_data(client,
1012 DS1307_REG_HOUR << 4 | 0x08,
1013 hour);
1014 }
1015 break;
33df2ee1
JT		 1016 case ds_1388:
1017 ds1307->offset = 1; /* Seconds starts at 1 */
1018 break;
f4199f85
TN		 1019 case mcp794xx:
1020 rtc_ops = &mcp794xx_rtc_ops;
1d1945d2 1021 if (ds1307->client->irq > 0 && chip->alarm) {
2fb07a10 1022 irq_handler = mcp794xx_irq;
1d1945d2
SG		 1023 want_irq = true;
1024 }
1025 break;
045e0e85
DB		 1026 default:
1027 break;
1028 }
1abb0dc9
DB		 1029
1030read_rtc:
1031 /* read RTC registers */
96fc3a45 1032 tmp = ds1307->read_block_data(ds1307->client, ds1307->offset, 8, buf);
fed40b73 1033 if (tmp != 8) {
6df80e21 1034 dev_dbg(&client->dev, "read error %d\n", tmp);
1abb0dc9 1035 err = -EIO;
edca66d2 1036 goto exit;
1abb0dc9
DB		 1037 }
1038
40ce972d
DA		 1039 /*
1040 * minimal sanity checking; some chips (like DS1340) don't
1abb0dc9
DB		 1041 * specify the extra bits as must-be-zero, but there are
1042 * still a few values that are clearly out-of-range.
1043 */
1044 tmp = ds1307->regs[DS1307_REG_SECS];
045e0e85
DB		 1045 switch (ds1307->type) {
1046 case ds_1307:
045e0e85 1047 case m41t00:
be5f59f4 1048 /* clock halted? turn it on, so clock can tick. */
045e0e85 1049 if (tmp & DS1307_BIT_CH) {
be5f59f4
RG		 1050 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
1051 dev_warn(&client->dev, "SET TIME!\n");
045e0e85 1052 goto read_rtc;
1abb0dc9 1053 }
045e0e85 1054 break;
be5f59f4
RG		 1055 case ds_1338:
1056 /* clock halted? turn it on, so clock can tick. */
045e0e85 1057 if (tmp & DS1307_BIT_CH)
be5f59f4
RG		 1058 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
1059
1060 /* oscillator fault? clear flag, and warn */
1061 if (ds1307->regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
1062 i2c_smbus_write_byte_data(client, DS1307_REG_CONTROL,
bd16f9eb 1063 ds1307->regs[DS1307_REG_CONTROL]
be5f59f4
RG		 1064 & ~DS1338_BIT_OSF);
1065 dev_warn(&client->dev, "SET TIME!\n");
1066 goto read_rtc;
1067 }
045e0e85 1068 break;
fcd8db00
R		 1069 case ds_1340:
1070 /* clock halted? turn it on, so clock can tick. */
1071 if (tmp & DS1340_BIT_nEOSC)
1072 i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
1073
1074 tmp = i2c_smbus_read_byte_data(client, DS1340_REG_FLAG);
1075 if (tmp < 0) {
6df80e21 1076 dev_dbg(&client->dev, "read error %d\n", tmp);
fcd8db00 1077 err = -EIO;
edca66d2 1078 goto exit;
fcd8db00
R		 1079 }
1080
1081 /* oscillator fault? clear flag, and warn */
1082 if (tmp & DS1340_BIT_OSF) {
1083 i2c_smbus_write_byte_data(client, DS1340_REG_FLAG, 0);
1084 dev_warn(&client->dev, "SET TIME!\n");
1085 }
43fcb815 1086 break;
f4199f85 1087 case mcp794xx:
43fcb815 1088 /* make sure that the backup battery is enabled */
f4199f85 1089 if (!(ds1307->regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
43fcb815
DA		 1090 i2c_smbus_write_byte_data(client, DS1307_REG_WDAY,
1091 ds1307->regs[DS1307_REG_WDAY]
f4199f85 1092 | MCP794XX_BIT_VBATEN);
43fcb815
DA		 1093 }
1094
1095 /* clock halted? turn it on, so clock can tick. */
f4199f85 1096 if (!(tmp & MCP794XX_BIT_ST)) {
43fcb815 1097 i2c_smbus_write_byte_data(client, DS1307_REG_SECS,
f4199f85 1098 MCP794XX_BIT_ST);
43fcb815
DA		 1099 dev_warn(&client->dev, "SET TIME!\n");
1100 goto read_rtc;
1101 }
1102
fcd8db00 1103 break;
32d322bc 1104 default:
045e0e85 1105 break;
1abb0dc9 1106 }
045e0e85 1107
1abb0dc9 1108 tmp = ds1307->regs[DS1307_REG_HOUR];
c065f35c
DB		 1109 switch (ds1307->type) {
1110 case ds_1340:
1111 case m41t00:
40ce972d
DA		 1112 /*
1113 * NOTE: ignores century bits; fix before deploying
c065f35c
DB		 1114 * systems that will run through year 2100.
1115 */
1116 break;
a2166858
MF		 1117 case rx_8025:
1118 break;
c065f35c
DB		 1119 default:
1120 if (!(tmp & DS1307_BIT_12HR))
1121 break;
1122
40ce972d
DA		 1123 /*
1124 * Be sure we're in 24 hour mode. Multi-master systems
c065f35c
DB		 1125 * take note...
1126 */
fe20ba70 1127 tmp = bcd2bin(tmp & 0x1f);
c065f35c
DB		 1128 if (tmp == 12)
1129 tmp = 0;
1130 if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1131 tmp += 12;
1abb0dc9 1132 i2c_smbus_write_byte_data(client,
96fc3a45 1133 ds1307->offset + DS1307_REG_HOUR,
fe20ba70 1134 bin2bcd(tmp));
1abb0dc9
DB		 1135 }
1136
5ea73514 1137 device_set_wakeup_capable(&client->dev, want_irq);
edca66d2 1138 ds1307->rtc = devm_rtc_device_register(&client->dev, client->name,
1d1945d2 1139 rtc_ops, THIS_MODULE);
1abb0dc9 1140 if (IS_ERR(ds1307->rtc)) {
4071ea25 1141 return PTR_ERR(ds1307->rtc);
1abb0dc9
DB		 1142 }
1143
cb49a5e9 1144 if (want_irq) {
c5983191
NM		 1145 err = devm_request_threaded_irq(&client->dev,
1146 client->irq, NULL, irq_handler,
1147 IRQF_SHARED | IRQF_ONESHOT,
1148 ds1307->rtc->name, client);
cb49a5e9 1149 if (err) {
4071ea25
AZ		 1150 client->irq = 0;
1151 dev_err(&client->dev, "unable to request IRQ!\n");
51c4cfef 1152 } else {
7abea617 1153
51c4cfef
FB		 1154 set_bit(HAS_ALARM, &ds1307->flags);
1155 dev_dbg(&client->dev, "got IRQ %d\n", client->irq);
4071ea25 1156 }
cb49a5e9
RG		 1157 }
1158
9eab0a78 1159 if (chip->nvram_size) {
4071ea25 1160
edca66d2
JH		 1161 ds1307->nvram = devm_kzalloc(&client->dev,
1162 sizeof(struct bin_attribute),
1163 GFP_KERNEL);
9eab0a78 1164 if (!ds1307->nvram) {
4071ea25
AZ		 1165 dev_err(&client->dev, "cannot allocate memory for nvram sysfs\n");
1166 } else {
1167
1168 ds1307->nvram->attr.name = "nvram";
1169 ds1307->nvram->attr.mode = S_IRUGO | S_IWUSR;
1170
1171 sysfs_bin_attr_init(ds1307->nvram);
1172
1173 ds1307->nvram->read = ds1307_nvram_read;
1174 ds1307->nvram->write = ds1307_nvram_write;
1175 ds1307->nvram->size = chip->nvram_size;
1176 ds1307->nvram_offset = chip->nvram_offset;
1177
1178 err = sysfs_create_bin_file(&client->dev.kobj,
1179 ds1307->nvram);
1180 if (err) {
1181 dev_err(&client->dev,
1182 "unable to create sysfs file: %s\n",
1183 ds1307->nvram->attr.name);
1184 } else {
1185 set_bit(HAS_NVRAM, &ds1307->flags);
1186 dev_info(&client->dev, "%zu bytes nvram\n",
1187 ds1307->nvram->size);
1188 }
9eab0a78 1189 }
682d73f6
DB		 1190 }
1191
1abb0dc9
DB		 1192 return 0;
1193
edca66d2 1194exit:
1abb0dc9
DB		 1195 return err;
1196}
1197
5a167f45 1198static int ds1307_remove(struct i2c_client *client)
1abb0dc9 1199{
40ce972d 1200 struct ds1307 *ds1307 = i2c_get_clientdata(client);
cb49a5e9 1201
edca66d2 1202 if (test_and_clear_bit(HAS_NVRAM, &ds1307->flags))
9eab0a78 1203 sysfs_remove_bin_file(&client->dev.kobj, ds1307->nvram);
682d73f6 1204
1abb0dc9
DB		 1205 return 0;
1206}
1207
1208static struct i2c_driver ds1307_driver = {
1209 .driver = {
c065f35c 1210 .name = "rtc-ds1307",
1abb0dc9 1211 },
c065f35c 1212 .probe = ds1307_probe,
5a167f45 1213 .remove = ds1307_remove,
3760f736 1214 .id_table = ds1307_id,
1abb0dc9
DB		 1215};
1216
0abc9201 1217module_i2c_driver(ds1307_driver);
1abb0dc9
DB		 1218
1219MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
1220MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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