Commit | Line | Data |
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8f26795a AS |
1 | /* |
2 | * An rtc driver for the Dallas DS1511 | |
3 | * | |
4 | * Copyright (C) 2006 Atsushi Nemoto <anemo@mba.ocn.ne.jp> | |
5b73a41c | 5 | * Copyright (C) 2007 Andrew Sharp <andy.sharp@lsi.com> |
8f26795a AS |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * Real time clock driver for the Dallas 1511 chip, which also | |
12 | * contains a watchdog timer. There is a tiny amount of code that | |
13 | * platform code could use to mess with the watchdog device a little | |
14 | * bit, but not a full watchdog driver. | |
15 | */ | |
16 | ||
17 | #include <linux/bcd.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/kernel.h> | |
5a0e3ad6 | 20 | #include <linux/gfp.h> |
8f26795a AS |
21 | #include <linux/delay.h> |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/rtc.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/io.h> | |
2113852b | 26 | #include <linux/module.h> |
8f26795a AS |
27 | |
28 | #define DRV_VERSION "0.6" | |
29 | ||
30 | enum ds1511reg { | |
31 | DS1511_SEC = 0x0, | |
32 | DS1511_MIN = 0x1, | |
33 | DS1511_HOUR = 0x2, | |
34 | DS1511_DOW = 0x3, | |
35 | DS1511_DOM = 0x4, | |
36 | DS1511_MONTH = 0x5, | |
37 | DS1511_YEAR = 0x6, | |
38 | DS1511_CENTURY = 0x7, | |
39 | DS1511_AM1_SEC = 0x8, | |
40 | DS1511_AM2_MIN = 0x9, | |
41 | DS1511_AM3_HOUR = 0xa, | |
42 | DS1511_AM4_DATE = 0xb, | |
43 | DS1511_WD_MSEC = 0xc, | |
44 | DS1511_WD_SEC = 0xd, | |
45 | DS1511_CONTROL_A = 0xe, | |
46 | DS1511_CONTROL_B = 0xf, | |
47 | DS1511_RAMADDR_LSB = 0x10, | |
48 | DS1511_RAMDATA = 0x13 | |
49 | }; | |
50 | ||
51 | #define DS1511_BLF1 0x80 | |
52 | #define DS1511_BLF2 0x40 | |
53 | #define DS1511_PRS 0x20 | |
54 | #define DS1511_PAB 0x10 | |
55 | #define DS1511_TDF 0x08 | |
56 | #define DS1511_KSF 0x04 | |
57 | #define DS1511_WDF 0x02 | |
58 | #define DS1511_IRQF 0x01 | |
59 | #define DS1511_TE 0x80 | |
60 | #define DS1511_CS 0x40 | |
61 | #define DS1511_BME 0x20 | |
62 | #define DS1511_TPE 0x10 | |
63 | #define DS1511_TIE 0x08 | |
64 | #define DS1511_KIE 0x04 | |
65 | #define DS1511_WDE 0x02 | |
66 | #define DS1511_WDS 0x01 | |
8ccba142 | 67 | #define DS1511_RAM_MAX 0x100 |
8f26795a AS |
68 | |
69 | #define RTC_CMD DS1511_CONTROL_B | |
70 | #define RTC_CMD1 DS1511_CONTROL_A | |
71 | ||
72 | #define RTC_ALARM_SEC DS1511_AM1_SEC | |
73 | #define RTC_ALARM_MIN DS1511_AM2_MIN | |
74 | #define RTC_ALARM_HOUR DS1511_AM3_HOUR | |
75 | #define RTC_ALARM_DATE DS1511_AM4_DATE | |
76 | ||
77 | #define RTC_SEC DS1511_SEC | |
78 | #define RTC_MIN DS1511_MIN | |
79 | #define RTC_HOUR DS1511_HOUR | |
80 | #define RTC_DOW DS1511_DOW | |
81 | #define RTC_DOM DS1511_DOM | |
82 | #define RTC_MON DS1511_MONTH | |
83 | #define RTC_YEAR DS1511_YEAR | |
84 | #define RTC_CENTURY DS1511_CENTURY | |
85 | ||
86 | #define RTC_TIE DS1511_TIE | |
87 | #define RTC_TE DS1511_TE | |
88 | ||
89 | struct rtc_plat_data { | |
90 | struct rtc_device *rtc; | |
91 | void __iomem *ioaddr; /* virtual base address */ | |
8f26795a AS |
92 | int irq; |
93 | unsigned int irqen; | |
94 | int alrm_sec; | |
95 | int alrm_min; | |
96 | int alrm_hour; | |
97 | int alrm_mday; | |
ba4f3e47 | 98 | spinlock_t lock; |
8f26795a AS |
99 | }; |
100 | ||
101 | static DEFINE_SPINLOCK(ds1511_lock); | |
102 | ||
103 | static __iomem char *ds1511_base; | |
104 | static u32 reg_spacing = 1; | |
105 | ||
7b2f0053 | 106 | static noinline void |
8f26795a AS |
107 | rtc_write(uint8_t val, uint32_t reg) |
108 | { | |
109 | writeb(val, ds1511_base + (reg * reg_spacing)); | |
110 | } | |
111 | ||
7b2f0053 | 112 | static inline void |
8f26795a AS |
113 | rtc_write_alarm(uint8_t val, enum ds1511reg reg) |
114 | { | |
115 | rtc_write((val | 0x80), reg); | |
116 | } | |
117 | ||
7b2f0053 | 118 | static noinline uint8_t |
8f26795a AS |
119 | rtc_read(enum ds1511reg reg) |
120 | { | |
121 | return readb(ds1511_base + (reg * reg_spacing)); | |
122 | } | |
123 | ||
7b2f0053 | 124 | static inline void |
8f26795a AS |
125 | rtc_disable_update(void) |
126 | { | |
127 | rtc_write((rtc_read(RTC_CMD) & ~RTC_TE), RTC_CMD); | |
128 | } | |
129 | ||
7b2f0053 | 130 | static void |
8f26795a AS |
131 | rtc_enable_update(void) |
132 | { | |
133 | rtc_write((rtc_read(RTC_CMD) | RTC_TE), RTC_CMD); | |
134 | } | |
135 | ||
136 | /* | |
137 | * #define DS1511_WDOG_RESET_SUPPORT | |
138 | * | |
139 | * Uncomment this if you want to use these routines in | |
140 | * some platform code. | |
141 | */ | |
142 | #ifdef DS1511_WDOG_RESET_SUPPORT | |
143 | /* | |
144 | * just enough code to set the watchdog timer so that it | |
145 | * will reboot the system | |
146 | */ | |
7b2f0053 | 147 | void |
8f26795a AS |
148 | ds1511_wdog_set(unsigned long deciseconds) |
149 | { | |
150 | /* | |
151 | * the wdog timer can take 99.99 seconds | |
152 | */ | |
153 | deciseconds %= 10000; | |
154 | /* | |
155 | * set the wdog values in the wdog registers | |
156 | */ | |
fe20ba70 AB |
157 | rtc_write(bin2bcd(deciseconds % 100), DS1511_WD_MSEC); |
158 | rtc_write(bin2bcd(deciseconds / 100), DS1511_WD_SEC); | |
8f26795a AS |
159 | /* |
160 | * set wdog enable and wdog 'steering' bit to issue a reset | |
161 | */ | |
8ccba142 | 162 | rtc_write(rtc_read(RTC_CMD) | DS1511_WDE | DS1511_WDS, RTC_CMD); |
8f26795a AS |
163 | } |
164 | ||
7b2f0053 | 165 | void |
8f26795a AS |
166 | ds1511_wdog_disable(void) |
167 | { | |
168 | /* | |
169 | * clear wdog enable and wdog 'steering' bits | |
170 | */ | |
171 | rtc_write(rtc_read(RTC_CMD) & ~(DS1511_WDE | DS1511_WDS), RTC_CMD); | |
172 | /* | |
173 | * clear the wdog counter | |
174 | */ | |
175 | rtc_write(0, DS1511_WD_MSEC); | |
176 | rtc_write(0, DS1511_WD_SEC); | |
177 | } | |
178 | #endif | |
179 | ||
180 | /* | |
181 | * set the rtc chip's idea of the time. | |
182 | * stupidly, some callers call with year unmolested; | |
183 | * and some call with year = year - 1900. thanks. | |
184 | */ | |
a3ed107e | 185 | static int ds1511_rtc_set_time(struct device *dev, struct rtc_time *rtc_tm) |
8f26795a AS |
186 | { |
187 | u8 mon, day, dow, hrs, min, sec, yrs, cen; | |
9a0f4aea | 188 | unsigned long flags; |
8f26795a AS |
189 | |
190 | /* | |
191 | * won't have to change this for a while | |
192 | */ | |
7b2f0053 | 193 | if (rtc_tm->tm_year < 1900) |
8f26795a | 194 | rtc_tm->tm_year += 1900; |
8f26795a | 195 | |
7b2f0053 | 196 | if (rtc_tm->tm_year < 1970) |
8f26795a | 197 | return -EINVAL; |
7b2f0053 | 198 | |
8f26795a AS |
199 | yrs = rtc_tm->tm_year % 100; |
200 | cen = rtc_tm->tm_year / 100; | |
201 | mon = rtc_tm->tm_mon + 1; /* tm_mon starts at zero */ | |
202 | day = rtc_tm->tm_mday; | |
203 | dow = rtc_tm->tm_wday & 0x7; /* automatic BCD */ | |
204 | hrs = rtc_tm->tm_hour; | |
205 | min = rtc_tm->tm_min; | |
206 | sec = rtc_tm->tm_sec; | |
207 | ||
7b2f0053 | 208 | if ((mon > 12) || (day == 0)) |
8f26795a | 209 | return -EINVAL; |
8f26795a | 210 | |
7b2f0053 | 211 | if (day > rtc_month_days(rtc_tm->tm_mon, rtc_tm->tm_year)) |
8f26795a | 212 | return -EINVAL; |
8f26795a | 213 | |
7b2f0053 | 214 | if ((hrs >= 24) || (min >= 60) || (sec >= 60)) |
8f26795a | 215 | return -EINVAL; |
8f26795a AS |
216 | |
217 | /* | |
218 | * each register is a different number of valid bits | |
219 | */ | |
fe20ba70 AB |
220 | sec = bin2bcd(sec) & 0x7f; |
221 | min = bin2bcd(min) & 0x7f; | |
222 | hrs = bin2bcd(hrs) & 0x3f; | |
223 | day = bin2bcd(day) & 0x3f; | |
224 | mon = bin2bcd(mon) & 0x1f; | |
225 | yrs = bin2bcd(yrs) & 0xff; | |
226 | cen = bin2bcd(cen) & 0xff; | |
8f26795a AS |
227 | |
228 | spin_lock_irqsave(&ds1511_lock, flags); | |
229 | rtc_disable_update(); | |
230 | rtc_write(cen, RTC_CENTURY); | |
231 | rtc_write(yrs, RTC_YEAR); | |
232 | rtc_write((rtc_read(RTC_MON) & 0xe0) | mon, RTC_MON); | |
233 | rtc_write(day, RTC_DOM); | |
234 | rtc_write(hrs, RTC_HOUR); | |
235 | rtc_write(min, RTC_MIN); | |
236 | rtc_write(sec, RTC_SEC); | |
237 | rtc_write(dow, RTC_DOW); | |
238 | rtc_enable_update(); | |
239 | spin_unlock_irqrestore(&ds1511_lock, flags); | |
240 | ||
241 | return 0; | |
242 | } | |
243 | ||
a3ed107e | 244 | static int ds1511_rtc_read_time(struct device *dev, struct rtc_time *rtc_tm) |
8f26795a AS |
245 | { |
246 | unsigned int century; | |
9a0f4aea | 247 | unsigned long flags; |
8f26795a AS |
248 | |
249 | spin_lock_irqsave(&ds1511_lock, flags); | |
250 | rtc_disable_update(); | |
251 | ||
252 | rtc_tm->tm_sec = rtc_read(RTC_SEC) & 0x7f; | |
253 | rtc_tm->tm_min = rtc_read(RTC_MIN) & 0x7f; | |
254 | rtc_tm->tm_hour = rtc_read(RTC_HOUR) & 0x3f; | |
255 | rtc_tm->tm_mday = rtc_read(RTC_DOM) & 0x3f; | |
256 | rtc_tm->tm_wday = rtc_read(RTC_DOW) & 0x7; | |
257 | rtc_tm->tm_mon = rtc_read(RTC_MON) & 0x1f; | |
258 | rtc_tm->tm_year = rtc_read(RTC_YEAR) & 0x7f; | |
259 | century = rtc_read(RTC_CENTURY); | |
260 | ||
261 | rtc_enable_update(); | |
262 | spin_unlock_irqrestore(&ds1511_lock, flags); | |
263 | ||
fe20ba70 AB |
264 | rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec); |
265 | rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min); | |
266 | rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour); | |
267 | rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday); | |
268 | rtc_tm->tm_wday = bcd2bin(rtc_tm->tm_wday); | |
269 | rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon); | |
270 | rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year); | |
271 | century = bcd2bin(century) * 100; | |
8f26795a AS |
272 | |
273 | /* | |
274 | * Account for differences between how the RTC uses the values | |
275 | * and how they are defined in a struct rtc_time; | |
276 | */ | |
277 | century += rtc_tm->tm_year; | |
278 | rtc_tm->tm_year = century - 1900; | |
279 | ||
280 | rtc_tm->tm_mon--; | |
281 | ||
282 | if (rtc_valid_tm(rtc_tm) < 0) { | |
283 | dev_err(dev, "retrieved date/time is not valid.\n"); | |
284 | rtc_time_to_tm(0, rtc_tm); | |
285 | } | |
286 | return 0; | |
287 | } | |
288 | ||
289 | /* | |
290 | * write the alarm register settings | |
291 | * | |
292 | * we only have the use to interrupt every second, otherwise | |
293 | * known as the update interrupt, or the interrupt if the whole | |
294 | * date/hours/mins/secs matches. the ds1511 has many more | |
295 | * permutations, but the kernel doesn't. | |
296 | */ | |
7b2f0053 | 297 | static void |
8f26795a AS |
298 | ds1511_rtc_update_alarm(struct rtc_plat_data *pdata) |
299 | { | |
300 | unsigned long flags; | |
301 | ||
ba4f3e47 | 302 | spin_lock_irqsave(&pdata->lock, flags); |
8f26795a | 303 | rtc_write(pdata->alrm_mday < 0 || (pdata->irqen & RTC_UF) ? |
fe20ba70 | 304 | 0x80 : bin2bcd(pdata->alrm_mday) & 0x3f, |
8f26795a AS |
305 | RTC_ALARM_DATE); |
306 | rtc_write(pdata->alrm_hour < 0 || (pdata->irqen & RTC_UF) ? | |
fe20ba70 | 307 | 0x80 : bin2bcd(pdata->alrm_hour) & 0x3f, |
8f26795a AS |
308 | RTC_ALARM_HOUR); |
309 | rtc_write(pdata->alrm_min < 0 || (pdata->irqen & RTC_UF) ? | |
fe20ba70 | 310 | 0x80 : bin2bcd(pdata->alrm_min) & 0x7f, |
8f26795a AS |
311 | RTC_ALARM_MIN); |
312 | rtc_write(pdata->alrm_sec < 0 || (pdata->irqen & RTC_UF) ? | |
fe20ba70 | 313 | 0x80 : bin2bcd(pdata->alrm_sec) & 0x7f, |
8f26795a AS |
314 | RTC_ALARM_SEC); |
315 | rtc_write(rtc_read(RTC_CMD) | (pdata->irqen ? RTC_TIE : 0), RTC_CMD); | |
316 | rtc_read(RTC_CMD1); /* clear interrupts */ | |
ba4f3e47 | 317 | spin_unlock_irqrestore(&pdata->lock, flags); |
8f26795a AS |
318 | } |
319 | ||
7b2f0053 | 320 | static int |
8f26795a AS |
321 | ds1511_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) |
322 | { | |
323 | struct platform_device *pdev = to_platform_device(dev); | |
324 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
325 | ||
2fac6674 | 326 | if (pdata->irq <= 0) |
8f26795a | 327 | return -EINVAL; |
2fac6674 | 328 | |
8f26795a AS |
329 | pdata->alrm_mday = alrm->time.tm_mday; |
330 | pdata->alrm_hour = alrm->time.tm_hour; | |
331 | pdata->alrm_min = alrm->time.tm_min; | |
332 | pdata->alrm_sec = alrm->time.tm_sec; | |
7b2f0053 | 333 | if (alrm->enabled) |
8f26795a | 334 | pdata->irqen |= RTC_AF; |
7b2f0053 | 335 | |
8f26795a AS |
336 | ds1511_rtc_update_alarm(pdata); |
337 | return 0; | |
338 | } | |
339 | ||
7b2f0053 | 340 | static int |
8f26795a AS |
341 | ds1511_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) |
342 | { | |
343 | struct platform_device *pdev = to_platform_device(dev); | |
344 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
345 | ||
2fac6674 | 346 | if (pdata->irq <= 0) |
8f26795a | 347 | return -EINVAL; |
2fac6674 | 348 | |
8f26795a AS |
349 | alrm->time.tm_mday = pdata->alrm_mday < 0 ? 0 : pdata->alrm_mday; |
350 | alrm->time.tm_hour = pdata->alrm_hour < 0 ? 0 : pdata->alrm_hour; | |
351 | alrm->time.tm_min = pdata->alrm_min < 0 ? 0 : pdata->alrm_min; | |
352 | alrm->time.tm_sec = pdata->alrm_sec < 0 ? 0 : pdata->alrm_sec; | |
353 | alrm->enabled = (pdata->irqen & RTC_AF) ? 1 : 0; | |
354 | return 0; | |
355 | } | |
356 | ||
7b2f0053 | 357 | static irqreturn_t |
8f26795a AS |
358 | ds1511_interrupt(int irq, void *dev_id) |
359 | { | |
360 | struct platform_device *pdev = dev_id; | |
361 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
ba4f3e47 | 362 | unsigned long events = 0; |
8f26795a | 363 | |
ba4f3e47 | 364 | spin_lock(&pdata->lock); |
8f26795a AS |
365 | /* |
366 | * read and clear interrupt | |
367 | */ | |
ba4f3e47 AN |
368 | if (rtc_read(RTC_CMD1) & DS1511_IRQF) { |
369 | events = RTC_IRQF; | |
370 | if (rtc_read(RTC_ALARM_SEC) & 0x80) | |
371 | events |= RTC_UF; | |
372 | else | |
373 | events |= RTC_AF; | |
0d71915d | 374 | rtc_update_irq(pdata->rtc, 1, events); |
ba4f3e47 AN |
375 | } |
376 | spin_unlock(&pdata->lock); | |
377 | return events ? IRQ_HANDLED : IRQ_NONE; | |
8f26795a AS |
378 | } |
379 | ||
ba4f3e47 | 380 | static int ds1511_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
8f26795a AS |
381 | { |
382 | struct platform_device *pdev = to_platform_device(dev); | |
383 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
384 | ||
ba4f3e47 AN |
385 | if (pdata->irq <= 0) |
386 | return -EINVAL; | |
387 | if (enabled) | |
8f26795a | 388 | pdata->irqen |= RTC_AF; |
ba4f3e47 AN |
389 | else |
390 | pdata->irqen &= ~RTC_AF; | |
391 | ds1511_rtc_update_alarm(pdata); | |
392 | return 0; | |
393 | } | |
394 | ||
8f26795a | 395 | static const struct rtc_class_ops ds1511_rtc_ops = { |
ba4f3e47 AN |
396 | .read_time = ds1511_rtc_read_time, |
397 | .set_time = ds1511_rtc_set_time, | |
398 | .read_alarm = ds1511_rtc_read_alarm, | |
399 | .set_alarm = ds1511_rtc_set_alarm, | |
400 | .alarm_irq_enable = ds1511_rtc_alarm_irq_enable, | |
8f26795a AS |
401 | }; |
402 | ||
7b2f0053 | 403 | static ssize_t |
2c3c8bea CW |
404 | ds1511_nvram_read(struct file *filp, struct kobject *kobj, |
405 | struct bin_attribute *ba, | |
406 | char *buf, loff_t pos, size_t size) | |
8f26795a AS |
407 | { |
408 | ssize_t count; | |
409 | ||
8f26795a | 410 | rtc_write(pos, DS1511_RAMADDR_LSB); |
8ccba142 | 411 | for (count = 0; count < size; count++) |
8f26795a | 412 | *buf++ = rtc_read(DS1511_RAMDATA); |
7b2f0053 | 413 | |
8f26795a AS |
414 | return count; |
415 | } | |
416 | ||
7b2f0053 | 417 | static ssize_t |
2c3c8bea CW |
418 | ds1511_nvram_write(struct file *filp, struct kobject *kobj, |
419 | struct bin_attribute *bin_attr, | |
420 | char *buf, loff_t pos, size_t size) | |
8f26795a AS |
421 | { |
422 | ssize_t count; | |
423 | ||
8f26795a | 424 | rtc_write(pos, DS1511_RAMADDR_LSB); |
8ccba142 | 425 | for (count = 0; count < size; count++) |
8f26795a | 426 | rtc_write(*buf++, DS1511_RAMDATA); |
7b2f0053 | 427 | |
8f26795a AS |
428 | return count; |
429 | } | |
430 | ||
431 | static struct bin_attribute ds1511_nvram_attr = { | |
432 | .attr = { | |
433 | .name = "nvram", | |
49d50fb1 | 434 | .mode = S_IRUGO | S_IWUSR, |
8f26795a AS |
435 | }, |
436 | .size = DS1511_RAM_MAX, | |
437 | .read = ds1511_nvram_read, | |
438 | .write = ds1511_nvram_write, | |
439 | }; | |
440 | ||
5a167f45 | 441 | static int ds1511_rtc_probe(struct platform_device *pdev) |
8f26795a | 442 | { |
8f26795a | 443 | struct resource *res; |
ba4f3e47 | 444 | struct rtc_plat_data *pdata; |
8f26795a AS |
445 | int ret = 0; |
446 | ||
ba4f3e47 AN |
447 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
448 | if (!pdata) | |
8f26795a | 449 | return -ENOMEM; |
7c1d69ee JL |
450 | |
451 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
452 | ds1511_base = devm_ioremap_resource(&pdev->dev, res); | |
453 | if (IS_ERR(ds1511_base)) | |
454 | return PTR_ERR(ds1511_base); | |
8f26795a AS |
455 | pdata->ioaddr = ds1511_base; |
456 | pdata->irq = platform_get_irq(pdev, 0); | |
457 | ||
458 | /* | |
459 | * turn on the clock and the crystal, etc. | |
460 | */ | |
8ccba142 | 461 | rtc_write(DS1511_BME, RTC_CMD); |
8f26795a AS |
462 | rtc_write(0, RTC_CMD1); |
463 | /* | |
464 | * clear the wdog counter | |
465 | */ | |
466 | rtc_write(0, DS1511_WD_MSEC); | |
467 | rtc_write(0, DS1511_WD_SEC); | |
468 | /* | |
469 | * start the clock | |
470 | */ | |
471 | rtc_enable_update(); | |
472 | ||
473 | /* | |
474 | * check for a dying bat-tree | |
475 | */ | |
7b2f0053 | 476 | if (rtc_read(RTC_CMD1) & DS1511_BLF1) |
8f26795a | 477 | dev_warn(&pdev->dev, "voltage-low detected.\n"); |
8f26795a | 478 | |
ba4f3e47 AN |
479 | spin_lock_init(&pdata->lock); |
480 | platform_set_drvdata(pdev, pdata); | |
4071ea25 AZ |
481 | |
482 | pdata->rtc = devm_rtc_device_register(&pdev->dev, pdev->name, | |
483 | &ds1511_rtc_ops, THIS_MODULE); | |
484 | if (IS_ERR(pdata->rtc)) | |
485 | return PTR_ERR(pdata->rtc); | |
486 | ||
8f26795a AS |
487 | /* |
488 | * if the platform has an interrupt in mind for this device, | |
489 | * then by all means, set it | |
490 | */ | |
2fac6674 | 491 | if (pdata->irq > 0) { |
8f26795a | 492 | rtc_read(RTC_CMD1); |
ba4f3e47 | 493 | if (devm_request_irq(&pdev->dev, pdata->irq, ds1511_interrupt, |
2f6e5f94 | 494 | IRQF_SHARED, pdev->name, pdev) < 0) { |
8f26795a AS |
495 | |
496 | dev_warn(&pdev->dev, "interrupt not available.\n"); | |
2fac6674 | 497 | pdata->irq = 0; |
8f26795a AS |
498 | } |
499 | } | |
500 | ||
8f26795a | 501 | ret = sysfs_create_bin_file(&pdev->dev.kobj, &ds1511_nvram_attr); |
4071ea25 AZ |
502 | if (ret) |
503 | dev_err(&pdev->dev, "Unable to create sysfs entry: %s\n", | |
504 | ds1511_nvram_attr.attr.name); | |
f650e657 | 505 | |
4071ea25 | 506 | return 0; |
8f26795a AS |
507 | } |
508 | ||
5a167f45 | 509 | static int ds1511_rtc_remove(struct platform_device *pdev) |
8f26795a AS |
510 | { |
511 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
512 | ||
513 | sysfs_remove_bin_file(&pdev->dev.kobj, &ds1511_nvram_attr); | |
2fac6674 | 514 | if (pdata->irq > 0) { |
8f26795a AS |
515 | /* |
516 | * disable the alarm interrupt | |
517 | */ | |
518 | rtc_write(rtc_read(RTC_CMD) & ~RTC_TIE, RTC_CMD); | |
519 | rtc_read(RTC_CMD1); | |
8f26795a | 520 | } |
8f26795a AS |
521 | return 0; |
522 | } | |
523 | ||
ad28a07b KS |
524 | /* work with hotplug and coldplug */ |
525 | MODULE_ALIAS("platform:ds1511"); | |
526 | ||
8f26795a AS |
527 | static struct platform_driver ds1511_rtc_driver = { |
528 | .probe = ds1511_rtc_probe, | |
5a167f45 | 529 | .remove = ds1511_rtc_remove, |
8f26795a AS |
530 | .driver = { |
531 | .name = "ds1511", | |
8f26795a AS |
532 | }, |
533 | }; | |
534 | ||
0c4eae66 | 535 | module_platform_driver(ds1511_rtc_driver); |
8f26795a | 536 | |
5b73a41c | 537 | MODULE_AUTHOR("Andrew Sharp <andy.sharp@lsi.com>"); |
8f26795a AS |
538 | MODULE_DESCRIPTION("Dallas DS1511 RTC driver"); |
539 | MODULE_LICENSE("GPL"); | |
540 | MODULE_VERSION(DRV_VERSION); |