Commit | Line | Data |
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8f26795a AS |
1 | /* |
2 | * An rtc driver for the Dallas DS1511 | |
3 | * | |
4 | * Copyright (C) 2006 Atsushi Nemoto <anemo@mba.ocn.ne.jp> | |
5b73a41c | 5 | * Copyright (C) 2007 Andrew Sharp <andy.sharp@lsi.com> |
8f26795a AS |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * Real time clock driver for the Dallas 1511 chip, which also | |
12 | * contains a watchdog timer. There is a tiny amount of code that | |
13 | * platform code could use to mess with the watchdog device a little | |
14 | * bit, but not a full watchdog driver. | |
15 | */ | |
16 | ||
17 | #include <linux/bcd.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/kernel.h> | |
5a0e3ad6 | 20 | #include <linux/gfp.h> |
8f26795a AS |
21 | #include <linux/delay.h> |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/rtc.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/io.h> | |
2113852b | 26 | #include <linux/module.h> |
8f26795a AS |
27 | |
28 | #define DRV_VERSION "0.6" | |
29 | ||
30 | enum ds1511reg { | |
31 | DS1511_SEC = 0x0, | |
32 | DS1511_MIN = 0x1, | |
33 | DS1511_HOUR = 0x2, | |
34 | DS1511_DOW = 0x3, | |
35 | DS1511_DOM = 0x4, | |
36 | DS1511_MONTH = 0x5, | |
37 | DS1511_YEAR = 0x6, | |
38 | DS1511_CENTURY = 0x7, | |
39 | DS1511_AM1_SEC = 0x8, | |
40 | DS1511_AM2_MIN = 0x9, | |
41 | DS1511_AM3_HOUR = 0xa, | |
42 | DS1511_AM4_DATE = 0xb, | |
43 | DS1511_WD_MSEC = 0xc, | |
44 | DS1511_WD_SEC = 0xd, | |
45 | DS1511_CONTROL_A = 0xe, | |
46 | DS1511_CONTROL_B = 0xf, | |
47 | DS1511_RAMADDR_LSB = 0x10, | |
48 | DS1511_RAMDATA = 0x13 | |
49 | }; | |
50 | ||
51 | #define DS1511_BLF1 0x80 | |
52 | #define DS1511_BLF2 0x40 | |
53 | #define DS1511_PRS 0x20 | |
54 | #define DS1511_PAB 0x10 | |
55 | #define DS1511_TDF 0x08 | |
56 | #define DS1511_KSF 0x04 | |
57 | #define DS1511_WDF 0x02 | |
58 | #define DS1511_IRQF 0x01 | |
59 | #define DS1511_TE 0x80 | |
60 | #define DS1511_CS 0x40 | |
61 | #define DS1511_BME 0x20 | |
62 | #define DS1511_TPE 0x10 | |
63 | #define DS1511_TIE 0x08 | |
64 | #define DS1511_KIE 0x04 | |
65 | #define DS1511_WDE 0x02 | |
66 | #define DS1511_WDS 0x01 | |
67 | #define DS1511_RAM_MAX 0xff | |
68 | ||
69 | #define RTC_CMD DS1511_CONTROL_B | |
70 | #define RTC_CMD1 DS1511_CONTROL_A | |
71 | ||
72 | #define RTC_ALARM_SEC DS1511_AM1_SEC | |
73 | #define RTC_ALARM_MIN DS1511_AM2_MIN | |
74 | #define RTC_ALARM_HOUR DS1511_AM3_HOUR | |
75 | #define RTC_ALARM_DATE DS1511_AM4_DATE | |
76 | ||
77 | #define RTC_SEC DS1511_SEC | |
78 | #define RTC_MIN DS1511_MIN | |
79 | #define RTC_HOUR DS1511_HOUR | |
80 | #define RTC_DOW DS1511_DOW | |
81 | #define RTC_DOM DS1511_DOM | |
82 | #define RTC_MON DS1511_MONTH | |
83 | #define RTC_YEAR DS1511_YEAR | |
84 | #define RTC_CENTURY DS1511_CENTURY | |
85 | ||
86 | #define RTC_TIE DS1511_TIE | |
87 | #define RTC_TE DS1511_TE | |
88 | ||
89 | struct rtc_plat_data { | |
90 | struct rtc_device *rtc; | |
91 | void __iomem *ioaddr; /* virtual base address */ | |
8f26795a AS |
92 | int size; /* amount of memory mapped */ |
93 | int irq; | |
94 | unsigned int irqen; | |
95 | int alrm_sec; | |
96 | int alrm_min; | |
97 | int alrm_hour; | |
98 | int alrm_mday; | |
ba4f3e47 | 99 | spinlock_t lock; |
8f26795a AS |
100 | }; |
101 | ||
102 | static DEFINE_SPINLOCK(ds1511_lock); | |
103 | ||
104 | static __iomem char *ds1511_base; | |
105 | static u32 reg_spacing = 1; | |
106 | ||
7b2f0053 | 107 | static noinline void |
8f26795a AS |
108 | rtc_write(uint8_t val, uint32_t reg) |
109 | { | |
110 | writeb(val, ds1511_base + (reg * reg_spacing)); | |
111 | } | |
112 | ||
7b2f0053 | 113 | static inline void |
8f26795a AS |
114 | rtc_write_alarm(uint8_t val, enum ds1511reg reg) |
115 | { | |
116 | rtc_write((val | 0x80), reg); | |
117 | } | |
118 | ||
7b2f0053 | 119 | static noinline uint8_t |
8f26795a AS |
120 | rtc_read(enum ds1511reg reg) |
121 | { | |
122 | return readb(ds1511_base + (reg * reg_spacing)); | |
123 | } | |
124 | ||
7b2f0053 | 125 | static inline void |
8f26795a AS |
126 | rtc_disable_update(void) |
127 | { | |
128 | rtc_write((rtc_read(RTC_CMD) & ~RTC_TE), RTC_CMD); | |
129 | } | |
130 | ||
7b2f0053 | 131 | static void |
8f26795a AS |
132 | rtc_enable_update(void) |
133 | { | |
134 | rtc_write((rtc_read(RTC_CMD) | RTC_TE), RTC_CMD); | |
135 | } | |
136 | ||
137 | /* | |
138 | * #define DS1511_WDOG_RESET_SUPPORT | |
139 | * | |
140 | * Uncomment this if you want to use these routines in | |
141 | * some platform code. | |
142 | */ | |
143 | #ifdef DS1511_WDOG_RESET_SUPPORT | |
144 | /* | |
145 | * just enough code to set the watchdog timer so that it | |
146 | * will reboot the system | |
147 | */ | |
7b2f0053 | 148 | void |
8f26795a AS |
149 | ds1511_wdog_set(unsigned long deciseconds) |
150 | { | |
151 | /* | |
152 | * the wdog timer can take 99.99 seconds | |
153 | */ | |
154 | deciseconds %= 10000; | |
155 | /* | |
156 | * set the wdog values in the wdog registers | |
157 | */ | |
fe20ba70 AB |
158 | rtc_write(bin2bcd(deciseconds % 100), DS1511_WD_MSEC); |
159 | rtc_write(bin2bcd(deciseconds / 100), DS1511_WD_SEC); | |
8f26795a AS |
160 | /* |
161 | * set wdog enable and wdog 'steering' bit to issue a reset | |
162 | */ | |
163 | rtc_write(DS1511_WDE | DS1511_WDS, RTC_CMD); | |
164 | } | |
165 | ||
7b2f0053 | 166 | void |
8f26795a AS |
167 | ds1511_wdog_disable(void) |
168 | { | |
169 | /* | |
170 | * clear wdog enable and wdog 'steering' bits | |
171 | */ | |
172 | rtc_write(rtc_read(RTC_CMD) & ~(DS1511_WDE | DS1511_WDS), RTC_CMD); | |
173 | /* | |
174 | * clear the wdog counter | |
175 | */ | |
176 | rtc_write(0, DS1511_WD_MSEC); | |
177 | rtc_write(0, DS1511_WD_SEC); | |
178 | } | |
179 | #endif | |
180 | ||
181 | /* | |
182 | * set the rtc chip's idea of the time. | |
183 | * stupidly, some callers call with year unmolested; | |
184 | * and some call with year = year - 1900. thanks. | |
185 | */ | |
a3ed107e | 186 | static int ds1511_rtc_set_time(struct device *dev, struct rtc_time *rtc_tm) |
8f26795a AS |
187 | { |
188 | u8 mon, day, dow, hrs, min, sec, yrs, cen; | |
9a0f4aea | 189 | unsigned long flags; |
8f26795a AS |
190 | |
191 | /* | |
192 | * won't have to change this for a while | |
193 | */ | |
7b2f0053 | 194 | if (rtc_tm->tm_year < 1900) |
8f26795a | 195 | rtc_tm->tm_year += 1900; |
8f26795a | 196 | |
7b2f0053 | 197 | if (rtc_tm->tm_year < 1970) |
8f26795a | 198 | return -EINVAL; |
7b2f0053 | 199 | |
8f26795a AS |
200 | yrs = rtc_tm->tm_year % 100; |
201 | cen = rtc_tm->tm_year / 100; | |
202 | mon = rtc_tm->tm_mon + 1; /* tm_mon starts at zero */ | |
203 | day = rtc_tm->tm_mday; | |
204 | dow = rtc_tm->tm_wday & 0x7; /* automatic BCD */ | |
205 | hrs = rtc_tm->tm_hour; | |
206 | min = rtc_tm->tm_min; | |
207 | sec = rtc_tm->tm_sec; | |
208 | ||
7b2f0053 | 209 | if ((mon > 12) || (day == 0)) |
8f26795a | 210 | return -EINVAL; |
8f26795a | 211 | |
7b2f0053 | 212 | if (day > rtc_month_days(rtc_tm->tm_mon, rtc_tm->tm_year)) |
8f26795a | 213 | return -EINVAL; |
8f26795a | 214 | |
7b2f0053 | 215 | if ((hrs >= 24) || (min >= 60) || (sec >= 60)) |
8f26795a | 216 | return -EINVAL; |
8f26795a AS |
217 | |
218 | /* | |
219 | * each register is a different number of valid bits | |
220 | */ | |
fe20ba70 AB |
221 | sec = bin2bcd(sec) & 0x7f; |
222 | min = bin2bcd(min) & 0x7f; | |
223 | hrs = bin2bcd(hrs) & 0x3f; | |
224 | day = bin2bcd(day) & 0x3f; | |
225 | mon = bin2bcd(mon) & 0x1f; | |
226 | yrs = bin2bcd(yrs) & 0xff; | |
227 | cen = bin2bcd(cen) & 0xff; | |
8f26795a AS |
228 | |
229 | spin_lock_irqsave(&ds1511_lock, flags); | |
230 | rtc_disable_update(); | |
231 | rtc_write(cen, RTC_CENTURY); | |
232 | rtc_write(yrs, RTC_YEAR); | |
233 | rtc_write((rtc_read(RTC_MON) & 0xe0) | mon, RTC_MON); | |
234 | rtc_write(day, RTC_DOM); | |
235 | rtc_write(hrs, RTC_HOUR); | |
236 | rtc_write(min, RTC_MIN); | |
237 | rtc_write(sec, RTC_SEC); | |
238 | rtc_write(dow, RTC_DOW); | |
239 | rtc_enable_update(); | |
240 | spin_unlock_irqrestore(&ds1511_lock, flags); | |
241 | ||
242 | return 0; | |
243 | } | |
244 | ||
a3ed107e | 245 | static int ds1511_rtc_read_time(struct device *dev, struct rtc_time *rtc_tm) |
8f26795a AS |
246 | { |
247 | unsigned int century; | |
9a0f4aea | 248 | unsigned long flags; |
8f26795a AS |
249 | |
250 | spin_lock_irqsave(&ds1511_lock, flags); | |
251 | rtc_disable_update(); | |
252 | ||
253 | rtc_tm->tm_sec = rtc_read(RTC_SEC) & 0x7f; | |
254 | rtc_tm->tm_min = rtc_read(RTC_MIN) & 0x7f; | |
255 | rtc_tm->tm_hour = rtc_read(RTC_HOUR) & 0x3f; | |
256 | rtc_tm->tm_mday = rtc_read(RTC_DOM) & 0x3f; | |
257 | rtc_tm->tm_wday = rtc_read(RTC_DOW) & 0x7; | |
258 | rtc_tm->tm_mon = rtc_read(RTC_MON) & 0x1f; | |
259 | rtc_tm->tm_year = rtc_read(RTC_YEAR) & 0x7f; | |
260 | century = rtc_read(RTC_CENTURY); | |
261 | ||
262 | rtc_enable_update(); | |
263 | spin_unlock_irqrestore(&ds1511_lock, flags); | |
264 | ||
fe20ba70 AB |
265 | rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec); |
266 | rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min); | |
267 | rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour); | |
268 | rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday); | |
269 | rtc_tm->tm_wday = bcd2bin(rtc_tm->tm_wday); | |
270 | rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon); | |
271 | rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year); | |
272 | century = bcd2bin(century) * 100; | |
8f26795a AS |
273 | |
274 | /* | |
275 | * Account for differences between how the RTC uses the values | |
276 | * and how they are defined in a struct rtc_time; | |
277 | */ | |
278 | century += rtc_tm->tm_year; | |
279 | rtc_tm->tm_year = century - 1900; | |
280 | ||
281 | rtc_tm->tm_mon--; | |
282 | ||
283 | if (rtc_valid_tm(rtc_tm) < 0) { | |
284 | dev_err(dev, "retrieved date/time is not valid.\n"); | |
285 | rtc_time_to_tm(0, rtc_tm); | |
286 | } | |
287 | return 0; | |
288 | } | |
289 | ||
290 | /* | |
291 | * write the alarm register settings | |
292 | * | |
293 | * we only have the use to interrupt every second, otherwise | |
294 | * known as the update interrupt, or the interrupt if the whole | |
295 | * date/hours/mins/secs matches. the ds1511 has many more | |
296 | * permutations, but the kernel doesn't. | |
297 | */ | |
7b2f0053 | 298 | static void |
8f26795a AS |
299 | ds1511_rtc_update_alarm(struct rtc_plat_data *pdata) |
300 | { | |
301 | unsigned long flags; | |
302 | ||
ba4f3e47 | 303 | spin_lock_irqsave(&pdata->lock, flags); |
8f26795a | 304 | rtc_write(pdata->alrm_mday < 0 || (pdata->irqen & RTC_UF) ? |
fe20ba70 | 305 | 0x80 : bin2bcd(pdata->alrm_mday) & 0x3f, |
8f26795a AS |
306 | RTC_ALARM_DATE); |
307 | rtc_write(pdata->alrm_hour < 0 || (pdata->irqen & RTC_UF) ? | |
fe20ba70 | 308 | 0x80 : bin2bcd(pdata->alrm_hour) & 0x3f, |
8f26795a AS |
309 | RTC_ALARM_HOUR); |
310 | rtc_write(pdata->alrm_min < 0 || (pdata->irqen & RTC_UF) ? | |
fe20ba70 | 311 | 0x80 : bin2bcd(pdata->alrm_min) & 0x7f, |
8f26795a AS |
312 | RTC_ALARM_MIN); |
313 | rtc_write(pdata->alrm_sec < 0 || (pdata->irqen & RTC_UF) ? | |
fe20ba70 | 314 | 0x80 : bin2bcd(pdata->alrm_sec) & 0x7f, |
8f26795a AS |
315 | RTC_ALARM_SEC); |
316 | rtc_write(rtc_read(RTC_CMD) | (pdata->irqen ? RTC_TIE : 0), RTC_CMD); | |
317 | rtc_read(RTC_CMD1); /* clear interrupts */ | |
ba4f3e47 | 318 | spin_unlock_irqrestore(&pdata->lock, flags); |
8f26795a AS |
319 | } |
320 | ||
7b2f0053 | 321 | static int |
8f26795a AS |
322 | ds1511_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) |
323 | { | |
324 | struct platform_device *pdev = to_platform_device(dev); | |
325 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
326 | ||
2fac6674 | 327 | if (pdata->irq <= 0) |
8f26795a | 328 | return -EINVAL; |
2fac6674 | 329 | |
8f26795a AS |
330 | pdata->alrm_mday = alrm->time.tm_mday; |
331 | pdata->alrm_hour = alrm->time.tm_hour; | |
332 | pdata->alrm_min = alrm->time.tm_min; | |
333 | pdata->alrm_sec = alrm->time.tm_sec; | |
7b2f0053 | 334 | if (alrm->enabled) |
8f26795a | 335 | pdata->irqen |= RTC_AF; |
7b2f0053 | 336 | |
8f26795a AS |
337 | ds1511_rtc_update_alarm(pdata); |
338 | return 0; | |
339 | } | |
340 | ||
7b2f0053 | 341 | static int |
8f26795a AS |
342 | ds1511_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) |
343 | { | |
344 | struct platform_device *pdev = to_platform_device(dev); | |
345 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
346 | ||
2fac6674 | 347 | if (pdata->irq <= 0) |
8f26795a | 348 | return -EINVAL; |
2fac6674 | 349 | |
8f26795a AS |
350 | alrm->time.tm_mday = pdata->alrm_mday < 0 ? 0 : pdata->alrm_mday; |
351 | alrm->time.tm_hour = pdata->alrm_hour < 0 ? 0 : pdata->alrm_hour; | |
352 | alrm->time.tm_min = pdata->alrm_min < 0 ? 0 : pdata->alrm_min; | |
353 | alrm->time.tm_sec = pdata->alrm_sec < 0 ? 0 : pdata->alrm_sec; | |
354 | alrm->enabled = (pdata->irqen & RTC_AF) ? 1 : 0; | |
355 | return 0; | |
356 | } | |
357 | ||
7b2f0053 | 358 | static irqreturn_t |
8f26795a AS |
359 | ds1511_interrupt(int irq, void *dev_id) |
360 | { | |
361 | struct platform_device *pdev = dev_id; | |
362 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
ba4f3e47 | 363 | unsigned long events = 0; |
8f26795a | 364 | |
ba4f3e47 | 365 | spin_lock(&pdata->lock); |
8f26795a AS |
366 | /* |
367 | * read and clear interrupt | |
368 | */ | |
ba4f3e47 AN |
369 | if (rtc_read(RTC_CMD1) & DS1511_IRQF) { |
370 | events = RTC_IRQF; | |
371 | if (rtc_read(RTC_ALARM_SEC) & 0x80) | |
372 | events |= RTC_UF; | |
373 | else | |
374 | events |= RTC_AF; | |
375 | if (likely(pdata->rtc)) | |
376 | rtc_update_irq(pdata->rtc, 1, events); | |
377 | } | |
378 | spin_unlock(&pdata->lock); | |
379 | return events ? IRQ_HANDLED : IRQ_NONE; | |
8f26795a AS |
380 | } |
381 | ||
ba4f3e47 | 382 | static int ds1511_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
8f26795a AS |
383 | { |
384 | struct platform_device *pdev = to_platform_device(dev); | |
385 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
386 | ||
ba4f3e47 AN |
387 | if (pdata->irq <= 0) |
388 | return -EINVAL; | |
389 | if (enabled) | |
8f26795a | 390 | pdata->irqen |= RTC_AF; |
ba4f3e47 AN |
391 | else |
392 | pdata->irqen &= ~RTC_AF; | |
393 | ds1511_rtc_update_alarm(pdata); | |
394 | return 0; | |
395 | } | |
396 | ||
8f26795a | 397 | static const struct rtc_class_ops ds1511_rtc_ops = { |
ba4f3e47 AN |
398 | .read_time = ds1511_rtc_read_time, |
399 | .set_time = ds1511_rtc_set_time, | |
400 | .read_alarm = ds1511_rtc_read_alarm, | |
401 | .set_alarm = ds1511_rtc_set_alarm, | |
402 | .alarm_irq_enable = ds1511_rtc_alarm_irq_enable, | |
8f26795a AS |
403 | }; |
404 | ||
7b2f0053 | 405 | static ssize_t |
2c3c8bea CW |
406 | ds1511_nvram_read(struct file *filp, struct kobject *kobj, |
407 | struct bin_attribute *ba, | |
408 | char *buf, loff_t pos, size_t size) | |
8f26795a AS |
409 | { |
410 | ssize_t count; | |
411 | ||
412 | /* | |
413 | * if count is more than one, turn on "burst" mode | |
414 | * turn it off when you're done | |
415 | */ | |
7b2f0053 | 416 | if (size > 1) |
8f26795a | 417 | rtc_write((rtc_read(RTC_CMD) | DS1511_BME), RTC_CMD); |
7b2f0053 SK |
418 | |
419 | if (pos > DS1511_RAM_MAX) | |
8f26795a | 420 | pos = DS1511_RAM_MAX; |
7b2f0053 SK |
421 | |
422 | if (size + pos > DS1511_RAM_MAX + 1) | |
8f26795a | 423 | size = DS1511_RAM_MAX - pos + 1; |
7b2f0053 | 424 | |
8f26795a | 425 | rtc_write(pos, DS1511_RAMADDR_LSB); |
7b2f0053 | 426 | for (count = 0; size > 0; count++, size--) |
8f26795a | 427 | *buf++ = rtc_read(DS1511_RAMDATA); |
7b2f0053 SK |
428 | |
429 | if (count > 1) | |
8f26795a | 430 | rtc_write((rtc_read(RTC_CMD) & ~DS1511_BME), RTC_CMD); |
7b2f0053 | 431 | |
8f26795a AS |
432 | return count; |
433 | } | |
434 | ||
7b2f0053 | 435 | static ssize_t |
2c3c8bea CW |
436 | ds1511_nvram_write(struct file *filp, struct kobject *kobj, |
437 | struct bin_attribute *bin_attr, | |
438 | char *buf, loff_t pos, size_t size) | |
8f26795a AS |
439 | { |
440 | ssize_t count; | |
441 | ||
442 | /* | |
443 | * if count is more than one, turn on "burst" mode | |
444 | * turn it off when you're done | |
445 | */ | |
7b2f0053 | 446 | if (size > 1) |
8f26795a | 447 | rtc_write((rtc_read(RTC_CMD) | DS1511_BME), RTC_CMD); |
7b2f0053 SK |
448 | |
449 | if (pos > DS1511_RAM_MAX) | |
8f26795a | 450 | pos = DS1511_RAM_MAX; |
7b2f0053 SK |
451 | |
452 | if (size + pos > DS1511_RAM_MAX + 1) | |
8f26795a | 453 | size = DS1511_RAM_MAX - pos + 1; |
7b2f0053 | 454 | |
8f26795a | 455 | rtc_write(pos, DS1511_RAMADDR_LSB); |
7b2f0053 | 456 | for (count = 0; size > 0; count++, size--) |
8f26795a | 457 | rtc_write(*buf++, DS1511_RAMDATA); |
7b2f0053 SK |
458 | |
459 | if (count > 1) | |
8f26795a | 460 | rtc_write((rtc_read(RTC_CMD) & ~DS1511_BME), RTC_CMD); |
7b2f0053 | 461 | |
8f26795a AS |
462 | return count; |
463 | } | |
464 | ||
465 | static struct bin_attribute ds1511_nvram_attr = { | |
466 | .attr = { | |
467 | .name = "nvram", | |
49d50fb1 | 468 | .mode = S_IRUGO | S_IWUSR, |
8f26795a AS |
469 | }, |
470 | .size = DS1511_RAM_MAX, | |
471 | .read = ds1511_nvram_read, | |
472 | .write = ds1511_nvram_write, | |
473 | }; | |
474 | ||
5a167f45 | 475 | static int ds1511_rtc_probe(struct platform_device *pdev) |
8f26795a AS |
476 | { |
477 | struct rtc_device *rtc; | |
478 | struct resource *res; | |
ba4f3e47 | 479 | struct rtc_plat_data *pdata; |
8f26795a AS |
480 | int ret = 0; |
481 | ||
482 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
7b2f0053 | 483 | if (!res) |
8f26795a | 484 | return -ENODEV; |
7b2f0053 | 485 | |
ba4f3e47 AN |
486 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
487 | if (!pdata) | |
8f26795a | 488 | return -ENOMEM; |
28f65c11 | 489 | pdata->size = resource_size(res); |
ba4f3e47 AN |
490 | if (!devm_request_mem_region(&pdev->dev, res->start, pdata->size, |
491 | pdev->name)) | |
492 | return -EBUSY; | |
493 | ds1511_base = devm_ioremap(&pdev->dev, res->start, pdata->size); | |
494 | if (!ds1511_base) | |
495 | return -ENOMEM; | |
8f26795a AS |
496 | pdata->ioaddr = ds1511_base; |
497 | pdata->irq = platform_get_irq(pdev, 0); | |
498 | ||
499 | /* | |
500 | * turn on the clock and the crystal, etc. | |
501 | */ | |
502 | rtc_write(0, RTC_CMD); | |
503 | rtc_write(0, RTC_CMD1); | |
504 | /* | |
505 | * clear the wdog counter | |
506 | */ | |
507 | rtc_write(0, DS1511_WD_MSEC); | |
508 | rtc_write(0, DS1511_WD_SEC); | |
509 | /* | |
510 | * start the clock | |
511 | */ | |
512 | rtc_enable_update(); | |
513 | ||
514 | /* | |
515 | * check for a dying bat-tree | |
516 | */ | |
7b2f0053 | 517 | if (rtc_read(RTC_CMD1) & DS1511_BLF1) |
8f26795a | 518 | dev_warn(&pdev->dev, "voltage-low detected.\n"); |
8f26795a | 519 | |
ba4f3e47 AN |
520 | spin_lock_init(&pdata->lock); |
521 | platform_set_drvdata(pdev, pdata); | |
8f26795a AS |
522 | /* |
523 | * if the platform has an interrupt in mind for this device, | |
524 | * then by all means, set it | |
525 | */ | |
2fac6674 | 526 | if (pdata->irq > 0) { |
8f26795a | 527 | rtc_read(RTC_CMD1); |
ba4f3e47 | 528 | if (devm_request_irq(&pdev->dev, pdata->irq, ds1511_interrupt, |
2f6e5f94 | 529 | IRQF_SHARED, pdev->name, pdev) < 0) { |
8f26795a AS |
530 | |
531 | dev_warn(&pdev->dev, "interrupt not available.\n"); | |
2fac6674 | 532 | pdata->irq = 0; |
8f26795a AS |
533 | } |
534 | } | |
535 | ||
f650e657 JH |
536 | rtc = devm_rtc_device_register(&pdev->dev, pdev->name, &ds1511_rtc_ops, |
537 | THIS_MODULE); | |
ba4f3e47 AN |
538 | if (IS_ERR(rtc)) |
539 | return PTR_ERR(rtc); | |
8f26795a | 540 | pdata->rtc = rtc; |
ba4f3e47 | 541 | |
8f26795a | 542 | ret = sysfs_create_bin_file(&pdev->dev.kobj, &ds1511_nvram_attr); |
f650e657 | 543 | |
8f26795a AS |
544 | return ret; |
545 | } | |
546 | ||
5a167f45 | 547 | static int ds1511_rtc_remove(struct platform_device *pdev) |
8f26795a AS |
548 | { |
549 | struct rtc_plat_data *pdata = platform_get_drvdata(pdev); | |
550 | ||
551 | sysfs_remove_bin_file(&pdev->dev.kobj, &ds1511_nvram_attr); | |
2fac6674 | 552 | if (pdata->irq > 0) { |
8f26795a AS |
553 | /* |
554 | * disable the alarm interrupt | |
555 | */ | |
556 | rtc_write(rtc_read(RTC_CMD) & ~RTC_TIE, RTC_CMD); | |
557 | rtc_read(RTC_CMD1); | |
8f26795a | 558 | } |
8f26795a AS |
559 | return 0; |
560 | } | |
561 | ||
ad28a07b KS |
562 | /* work with hotplug and coldplug */ |
563 | MODULE_ALIAS("platform:ds1511"); | |
564 | ||
8f26795a AS |
565 | static struct platform_driver ds1511_rtc_driver = { |
566 | .probe = ds1511_rtc_probe, | |
5a167f45 | 567 | .remove = ds1511_rtc_remove, |
8f26795a AS |
568 | .driver = { |
569 | .name = "ds1511", | |
570 | .owner = THIS_MODULE, | |
571 | }, | |
572 | }; | |
573 | ||
0c4eae66 | 574 | module_platform_driver(ds1511_rtc_driver); |
8f26795a | 575 | |
5b73a41c | 576 | MODULE_AUTHOR("Andrew Sharp <andy.sharp@lsi.com>"); |
8f26795a AS |
577 | MODULE_DESCRIPTION("Dallas DS1511 RTC driver"); |
578 | MODULE_LICENSE("GPL"); | |
579 | MODULE_VERSION(DRV_VERSION); |