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rtc: max77686: Fix unsupported year message
[deliverable/linux.git] / drivers / rtc / rtc-max77686.c
CommitLineData
fca1dd03 1/*
f903129b 2 * RTC driver for Maxim MAX77686 and MAX77802
fca1dd03
JL		 3 *
4 * Copyright (C) 2012 Samsung Electronics Co.Ltd
5 *
6 * based on rtc-max8997.c
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#include <linux/slab.h>
16#include <linux/rtc.h>
17#include <linux/delay.h>
18#include <linux/mutex.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21#include <linux/mfd/max77686-private.h>
22#include <linux/irqdomain.h>
23#include <linux/regmap.h>
24
25/* RTC Control Register */
26#define BCD_EN_SHIFT 0
ac60bf31 27#define BCD_EN_MASK (1 << BCD_EN_SHIFT)
fca1dd03
JL		 28#define MODEL24_SHIFT 1
29#define MODEL24_MASK (1 << MODEL24_SHIFT)
30/* RTC Update Register1 */
31#define RTC_UDR_SHIFT 0
32#define RTC_UDR_MASK (1 << RTC_UDR_SHIFT)
33#define RTC_RBUDR_SHIFT 4
34#define RTC_RBUDR_MASK (1 << RTC_RBUDR_SHIFT)
fca1dd03
JL		 35/* RTC Hour register */
36#define HOUR_PM_SHIFT 6
37#define HOUR_PM_MASK (1 << HOUR_PM_SHIFT)
38/* RTC Alarm Enable */
39#define ALARM_ENABLE_SHIFT 7
40#define ALARM_ENABLE_MASK (1 << ALARM_ENABLE_SHIFT)
41
f903129b
JMC		 42#define REG_RTC_NONE 0xdeadbeef
43
44/*
45 * MAX77802 has separate register (RTCAE1) for alarm enable instead
46 * using 1 bit from registers RTC{SEC,MIN,HOUR,DAY,MONTH,YEAR,DATE}
47 * as in done in MAX77686.
48 */
49#define MAX77802_ALARM_ENABLE_VALUE 0x77
50
fca1dd03
JL		 51enum {
52 RTC_SEC = 0,
53 RTC_MIN,
54 RTC_HOUR,
55 RTC_WEEKDAY,
56 RTC_MONTH,
57 RTC_YEAR,
58 RTC_DATE,
59 RTC_NR_TIME
60};
61
01ea01b3
JMC		 62struct max77686_rtc_driver_data {
63 /* Minimum usecs needed for a RTC update */
64 unsigned long delay;
65 /* Mask used to read RTC registers value */
66 u8 mask;
90a5698a
JMC		 67 /* Registers offset to I2C addresses map */
68 const unsigned int *map;
f903129b
JMC		 69 /* Has a separate alarm enable register? */
70 bool alarm_enable_reg;
71 /* Has a separate I2C regmap for the RTC? */
72 bool separate_i2c_addr;
01ea01b3
JMC		 73};
74
fca1dd03
JL		 75struct max77686_rtc_info {
76 struct device *dev;
77 struct max77686_dev *max77686;
78 struct i2c_client *rtc;
79 struct rtc_device *rtc_dev;
80 struct mutex lock;
81
82 struct regmap *regmap;
83
01ea01b3
JMC		 84 const struct max77686_rtc_driver_data *drv_data;
85
fca1dd03
JL		 86 int virq;
87 int rtc_24hr_mode;
88};
89
90enum MAX77686_RTC_OP {
91 MAX77686_RTC_WRITE,
92 MAX77686_RTC_READ,
93};
94
90a5698a
JMC		 95/* These are not registers but just offsets that are mapped to addresses */
96enum max77686_rtc_reg_offset {
97 REG_RTC_CONTROLM = 0,
98 REG_RTC_CONTROL,
99 REG_RTC_UPDATE0,
100 REG_WTSR_SMPL_CNTL,
101 REG_RTC_SEC,
102 REG_RTC_MIN,
103 REG_RTC_HOUR,
104 REG_RTC_WEEKDAY,
105 REG_RTC_MONTH,
106 REG_RTC_YEAR,
107 REG_RTC_DATE,
108 REG_ALARM1_SEC,
109 REG_ALARM1_MIN,
110 REG_ALARM1_HOUR,
111 REG_ALARM1_WEEKDAY,
112 REG_ALARM1_MONTH,
113 REG_ALARM1_YEAR,
114 REG_ALARM1_DATE,
115 REG_ALARM2_SEC,
116 REG_ALARM2_MIN,
117 REG_ALARM2_HOUR,
118 REG_ALARM2_WEEKDAY,
119 REG_ALARM2_MONTH,
120 REG_ALARM2_YEAR,
121 REG_ALARM2_DATE,
f903129b 122 REG_RTC_AE1,
90a5698a
JMC		 123 REG_RTC_END,
124};
125
126/* Maps RTC registers offset to the MAX77686 register addresses */
127static const unsigned int max77686_map[REG_RTC_END] = {
128 [REG_RTC_CONTROLM] = MAX77686_RTC_CONTROLM,
129 [REG_RTC_CONTROL] = MAX77686_RTC_CONTROL,
130 [REG_RTC_UPDATE0] = MAX77686_RTC_UPDATE0,
131 [REG_WTSR_SMPL_CNTL] = MAX77686_WTSR_SMPL_CNTL,
132 [REG_RTC_SEC] = MAX77686_RTC_SEC,
133 [REG_RTC_MIN] = MAX77686_RTC_MIN,
134 [REG_RTC_HOUR] = MAX77686_RTC_HOUR,
135 [REG_RTC_WEEKDAY] = MAX77686_RTC_WEEKDAY,
136 [REG_RTC_MONTH] = MAX77686_RTC_MONTH,
137 [REG_RTC_YEAR] = MAX77686_RTC_YEAR,
138 [REG_RTC_DATE] = MAX77686_RTC_DATE,
139 [REG_ALARM1_SEC] = MAX77686_ALARM1_SEC,
140 [REG_ALARM1_MIN] = MAX77686_ALARM1_MIN,
141 [REG_ALARM1_HOUR] = MAX77686_ALARM1_HOUR,
142 [REG_ALARM1_WEEKDAY] = MAX77686_ALARM1_WEEKDAY,
143 [REG_ALARM1_MONTH] = MAX77686_ALARM1_MONTH,
144 [REG_ALARM1_YEAR] = MAX77686_ALARM1_YEAR,
145 [REG_ALARM1_DATE] = MAX77686_ALARM1_DATE,
146 [REG_ALARM2_SEC] = MAX77686_ALARM2_SEC,
147 [REG_ALARM2_MIN] = MAX77686_ALARM2_MIN,
148 [REG_ALARM2_HOUR] = MAX77686_ALARM2_HOUR,
149 [REG_ALARM2_WEEKDAY] = MAX77686_ALARM2_WEEKDAY,
150 [REG_ALARM2_MONTH] = MAX77686_ALARM2_MONTH,
151 [REG_ALARM2_YEAR] = MAX77686_ALARM2_YEAR,
152 [REG_ALARM2_DATE] = MAX77686_ALARM2_DATE,
f903129b 153 [REG_RTC_AE1] = REG_RTC_NONE,
90a5698a
JMC		 154};
155
01ea01b3
JMC		 156static const struct max77686_rtc_driver_data max77686_drv_data = {
157 .delay = 16000,
158 .mask = 0x7f,
90a5698a 159 .map = max77686_map,
f903129b
JMC		 160 .alarm_enable_reg = false,
161 .separate_i2c_addr = true,
162};
163
164static const unsigned int max77802_map[REG_RTC_END] = {
165 [REG_RTC_CONTROLM] = MAX77802_RTC_CONTROLM,
166 [REG_RTC_CONTROL] = MAX77802_RTC_CONTROL,
167 [REG_RTC_UPDATE0] = MAX77802_RTC_UPDATE0,
168 [REG_WTSR_SMPL_CNTL] = MAX77802_WTSR_SMPL_CNTL,
169 [REG_RTC_SEC] = MAX77802_RTC_SEC,
170 [REG_RTC_MIN] = MAX77802_RTC_MIN,
171 [REG_RTC_HOUR] = MAX77802_RTC_HOUR,
172 [REG_RTC_WEEKDAY] = MAX77802_RTC_WEEKDAY,
173 [REG_RTC_MONTH] = MAX77802_RTC_MONTH,
174 [REG_RTC_YEAR] = MAX77802_RTC_YEAR,
175 [REG_RTC_DATE] = MAX77802_RTC_DATE,
176 [REG_ALARM1_SEC] = MAX77802_ALARM1_SEC,
177 [REG_ALARM1_MIN] = MAX77802_ALARM1_MIN,
178 [REG_ALARM1_HOUR] = MAX77802_ALARM1_HOUR,
179 [REG_ALARM1_WEEKDAY] = MAX77802_ALARM1_WEEKDAY,
180 [REG_ALARM1_MONTH] = MAX77802_ALARM1_MONTH,
181 [REG_ALARM1_YEAR] = MAX77802_ALARM1_YEAR,
182 [REG_ALARM1_DATE] = MAX77802_ALARM1_DATE,
183 [REG_ALARM2_SEC] = MAX77802_ALARM2_SEC,
184 [REG_ALARM2_MIN] = MAX77802_ALARM2_MIN,
185 [REG_ALARM2_HOUR] = MAX77802_ALARM2_HOUR,
186 [REG_ALARM2_WEEKDAY] = MAX77802_ALARM2_WEEKDAY,
187 [REG_ALARM2_MONTH] = MAX77802_ALARM2_MONTH,
188 [REG_ALARM2_YEAR] = MAX77802_ALARM2_YEAR,
189 [REG_ALARM2_DATE] = MAX77802_ALARM2_DATE,
190 [REG_RTC_AE1] = MAX77802_RTC_AE1,
191};
192
193static const struct max77686_rtc_driver_data max77802_drv_data = {
194 .delay = 200,
195 .mask = 0xff,
196 .map = max77802_map,
197 .alarm_enable_reg = true,
198 .separate_i2c_addr = false,
01ea01b3
JMC		 199};
200
fca1dd03 201static void max77686_rtc_data_to_tm(u8 *data, struct rtc_time *tm,
01ea01b3 202 struct max77686_rtc_info *info)
fca1dd03 203{
01ea01b3
JMC		 204 u8 mask = info->drv_data->mask;
205
206 tm->tm_sec = data[RTC_SEC] & mask;
207 tm->tm_min = data[RTC_MIN] & mask;
208 if (info->rtc_24hr_mode)
fca1dd03
JL		 209 tm->tm_hour = data[RTC_HOUR] & 0x1f;
210 else {
211 tm->tm_hour = data[RTC_HOUR] & 0x0f;
212 if (data[RTC_HOUR] & HOUR_PM_MASK)
213 tm->tm_hour += 12;
214 }
215
a20cd88e 216 /* Only a single bit is set in data[], so fls() would be equivalent */
01ea01b3 217 tm->tm_wday = ffs(data[RTC_WEEKDAY] & mask) - 1;
fca1dd03
JL		 218 tm->tm_mday = data[RTC_DATE] & 0x1f;
219 tm->tm_mon = (data[RTC_MONTH] & 0x0f) - 1;
f903129b 220 tm->tm_year = data[RTC_YEAR] & mask;
fca1dd03
JL		 221 tm->tm_yday = 0;
222 tm->tm_isdst = 0;
f903129b
JMC		 223
224 /*
225 * MAX77686 uses 1 bit from sec/min/hour/etc RTC registers and the
226 * year values are just 0..99 so add 100 to support up to 2099.
227 */
228 if (!info->drv_data->alarm_enable_reg)
229 tm->tm_year += 100;
fca1dd03
JL		 230}
231
f903129b
JMC		 232static int max77686_rtc_tm_to_data(struct rtc_time *tm, u8 *data,
233 struct max77686_rtc_info *info)
fca1dd03
JL		 234{
235 data[RTC_SEC] = tm->tm_sec;
236 data[RTC_MIN] = tm->tm_min;
237 data[RTC_HOUR] = tm->tm_hour;
238 data[RTC_WEEKDAY] = 1 << tm->tm_wday;
239 data[RTC_DATE] = tm->tm_mday;
240 data[RTC_MONTH] = tm->tm_mon + 1;
f903129b
JMC		 241
242 if (info->drv_data->alarm_enable_reg) {
243 data[RTC_YEAR] = tm->tm_year;
244 return 0;
245 }
246
cdf5f4ac 247 data[RTC_YEAR] = tm->tm_year > 100 ? (tm->tm_year - 100) : 0;
fca1dd03
JL		 248
249 if (tm->tm_year < 100) {
1e5813bd 250 dev_err(info->dev, "RTC cannot handle the year %d.\n",
a737e835 251 1900 + tm->tm_year);
fca1dd03
JL		 252 return -EINVAL;
253 }
f903129b 254
fca1dd03
JL		 255 return 0;
256}
257
258static int max77686_rtc_update(struct max77686_rtc_info *info,
259 enum MAX77686_RTC_OP op)
260{
261 int ret;
262 unsigned int data;
01ea01b3 263 unsigned long delay = info->drv_data->delay;
fca1dd03
JL		 264
265 if (op == MAX77686_RTC_WRITE)
266 data = 1 << RTC_UDR_SHIFT;
267 else
268 data = 1 << RTC_RBUDR_SHIFT;
269
270 ret = regmap_update_bits(info->max77686->rtc_regmap,
90a5698a
JMC		 271 info->drv_data->map[REG_RTC_UPDATE0],
272 data, data);
fca1dd03
JL		 273 if (ret < 0)
274 dev_err(info->dev, "%s: fail to write update reg(ret=%d, data=0x%x)\n",
275 __func__, ret, data);
276 else {
01ea01b3
JMC		 277 /* Minimum delay required before RTC update. */
278 usleep_range(delay, delay * 2);
fca1dd03
JL		 279 }
280
281 return ret;
282}
283
284static int max77686_rtc_read_time(struct device *dev, struct rtc_time *tm)
285{
286 struct max77686_rtc_info *info = dev_get_drvdata(dev);
287 u8 data[RTC_NR_TIME];
288 int ret;
289
290 mutex_lock(&info->lock);
291
292 ret = max77686_rtc_update(info, MAX77686_RTC_READ);
293 if (ret < 0)
294 goto out;
295
296 ret = regmap_bulk_read(info->max77686->rtc_regmap,
90a5698a
JMC		 297 info->drv_data->map[REG_RTC_SEC],
298 data, ARRAY_SIZE(data));
fca1dd03
JL		 299 if (ret < 0) {
300 dev_err(info->dev, "%s: fail to read time reg(%d)\n", __func__, ret);
301 goto out;
302 }
303
01ea01b3 304 max77686_rtc_data_to_tm(data, tm, info);
fca1dd03
JL		 305
306 ret = rtc_valid_tm(tm);
307
308out:
309 mutex_unlock(&info->lock);
310 return ret;
311}
312
313static int max77686_rtc_set_time(struct device *dev, struct rtc_time *tm)
314{
315 struct max77686_rtc_info *info = dev_get_drvdata(dev);
316 u8 data[RTC_NR_TIME];
317 int ret;
318
f903129b 319 ret = max77686_rtc_tm_to_data(tm, data, info);
fca1dd03
JL		 320 if (ret < 0)
321 return ret;
322
323 mutex_lock(&info->lock);
324
325 ret = regmap_bulk_write(info->max77686->rtc_regmap,
90a5698a
JMC		 326 info->drv_data->map[REG_RTC_SEC],
327 data, ARRAY_SIZE(data));
fca1dd03
JL		 328 if (ret < 0) {
329 dev_err(info->dev, "%s: fail to write time reg(%d)\n", __func__,
330 ret);
331 goto out;
332 }
333
334 ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
335
336out:
337 mutex_unlock(&info->lock);
338 return ret;
339}
340
341static int max77686_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
342{
343 struct max77686_rtc_info *info = dev_get_drvdata(dev);
344 u8 data[RTC_NR_TIME];
345 unsigned int val;
90a5698a 346 const unsigned int *map = info->drv_data->map;
fca1dd03
JL		 347 int i, ret;
348
349 mutex_lock(&info->lock);
350
351 ret = max77686_rtc_update(info, MAX77686_RTC_READ);
352 if (ret < 0)
353 goto out;
354
355 ret = regmap_bulk_read(info->max77686->rtc_regmap,
90a5698a 356 map[REG_ALARM1_SEC], data, ARRAY_SIZE(data));
fca1dd03
JL		 357 if (ret < 0) {
358 dev_err(info->dev, "%s:%d fail to read alarm reg(%d)\n",
359 __func__, __LINE__, ret);
360 goto out;
361 }
362
01ea01b3 363 max77686_rtc_data_to_tm(data, &alrm->time, info);
fca1dd03
JL		 364
365 alrm->enabled = 0;
f903129b
JMC		 366
367 if (info->drv_data->alarm_enable_reg) {
368 if (map[REG_RTC_AE1] == REG_RTC_NONE) {
369 ret = -EINVAL;
370 dev_err(info->dev,
371 "alarm enable register not set(%d)\n", ret);
372 goto out;
373 }
374
375 ret = regmap_read(info->max77686->regmap,
376 map[REG_RTC_AE1], &val);
377 if (ret < 0) {
378 dev_err(info->dev,
379 "fail to read alarm enable(%d)\n", ret);
380 goto out;
381 }
382
383 if (val)
fca1dd03 384 alrm->enabled = 1;
f903129b
JMC		 385 } else {
386 for (i = 0; i < ARRAY_SIZE(data); i++) {
387 if (data[i] & ALARM_ENABLE_MASK) {
388 alrm->enabled = 1;
389 break;
390 }
fca1dd03
JL		 391 }
392 }
393
394 alrm->pending = 0;
1748cbf7 395 ret = regmap_read(info->max77686->regmap, MAX77686_REG_STATUS2, &val);
fca1dd03 396 if (ret < 0) {
1748cbf7 397 dev_err(info->dev, "%s:%d fail to read status2 reg(%d)\n",
fca1dd03
JL		 398 __func__, __LINE__, ret);
399 goto out;
400 }
401
402 if (val & (1 << 4)) /* RTCA1 */
403 alrm->pending = 1;
404
405out:
406 mutex_unlock(&info->lock);
7cdffeb5 407 return ret;
fca1dd03
JL		 408}
409
410static int max77686_rtc_stop_alarm(struct max77686_rtc_info *info)
411{
412 u8 data[RTC_NR_TIME];
413 int ret, i;
414 struct rtc_time tm;
90a5698a 415 const unsigned int *map = info->drv_data->map;
fca1dd03
JL		 416
417 if (!mutex_is_locked(&info->lock))
418 dev_warn(info->dev, "%s: should have mutex locked\n", __func__);
419
420 ret = max77686_rtc_update(info, MAX77686_RTC_READ);
421 if (ret < 0)
422 goto out;
423
f903129b
JMC		 424 if (info->drv_data->alarm_enable_reg) {
425 if (map[REG_RTC_AE1] == REG_RTC_NONE) {
426 ret = -EINVAL;
427 dev_err(info->dev,
428 "alarm enable register not set(%d)\n", ret);
429 goto out;
430 }
431
432 ret = regmap_write(info->max77686->regmap, map[REG_RTC_AE1], 0);
433 } else {
434 ret = regmap_bulk_read(info->max77686->rtc_regmap,
435 map[REG_ALARM1_SEC], data,
436 ARRAY_SIZE(data));
437 if (ret < 0) {
438 dev_err(info->dev, "%s: fail to read alarm reg(%d)\n",
fca1dd03 439 __func__, ret);
f903129b
JMC		 440 goto out;
441 }
fca1dd03 442
f903129b 443 max77686_rtc_data_to_tm(data, &tm, info);
fca1dd03 444
f903129b
JMC		 445 for (i = 0; i < ARRAY_SIZE(data); i++)
446 data[i] &= ~ALARM_ENABLE_MASK;
447
448 ret = regmap_bulk_write(info->max77686->rtc_regmap,
449 map[REG_ALARM1_SEC], data,
450 ARRAY_SIZE(data));
451 }
fca1dd03 452
fca1dd03
JL		 453 if (ret < 0) {
454 dev_err(info->dev, "%s: fail to write alarm reg(%d)\n",
455 __func__, ret);
456 goto out;
457 }
458
459 ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
460out:
461 return ret;
462}
463
464static int max77686_rtc_start_alarm(struct max77686_rtc_info *info)
465{
466 u8 data[RTC_NR_TIME];
467 int ret;
468 struct rtc_time tm;
90a5698a 469 const unsigned int *map = info->drv_data->map;
fca1dd03
JL		 470
471 if (!mutex_is_locked(&info->lock))
472 dev_warn(info->dev, "%s: should have mutex locked\n", __func__);
473
474 ret = max77686_rtc_update(info, MAX77686_RTC_READ);
475 if (ret < 0)
476 goto out;
477
f903129b
JMC		 478 if (info->drv_data->alarm_enable_reg) {
479 ret = regmap_write(info->max77686->regmap, map[REG_RTC_AE1],
480 MAX77802_ALARM_ENABLE_VALUE);
481 } else {
482 ret = regmap_bulk_read(info->max77686->rtc_regmap,
483 map[REG_ALARM1_SEC], data,
484 ARRAY_SIZE(data));
485 if (ret < 0) {
486 dev_err(info->dev, "%s: fail to read alarm reg(%d)\n",
fca1dd03 487 __func__, ret);
f903129b
JMC		 488 goto out;
489 }
fca1dd03 490
f903129b
JMC		 491 max77686_rtc_data_to_tm(data, &tm, info);
492
493 data[RTC_SEC] |= (1 << ALARM_ENABLE_SHIFT);
494 data[RTC_MIN] |= (1 << ALARM_ENABLE_SHIFT);
495 data[RTC_HOUR] |= (1 << ALARM_ENABLE_SHIFT);
496 data[RTC_WEEKDAY] &= ~ALARM_ENABLE_MASK;
497 if (data[RTC_MONTH] & 0xf)
498 data[RTC_MONTH] |= (1 << ALARM_ENABLE_SHIFT);
499 if (data[RTC_YEAR] & info->drv_data->mask)
500 data[RTC_YEAR] |= (1 << ALARM_ENABLE_SHIFT);
501 if (data[RTC_DATE] & 0x1f)
502 data[RTC_DATE] |= (1 << ALARM_ENABLE_SHIFT);
503
504 ret = regmap_bulk_write(info->max77686->rtc_regmap,
505 map[REG_ALARM1_SEC], data,
506 ARRAY_SIZE(data));
507 }
fca1dd03 508
fca1dd03
JL		 509 if (ret < 0) {
510 dev_err(info->dev, "%s: fail to write alarm reg(%d)\n",
511 __func__, ret);
512 goto out;
513 }
514
515 ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
516out:
517 return ret;
518}
519
520static int max77686_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
521{
522 struct max77686_rtc_info *info = dev_get_drvdata(dev);
523 u8 data[RTC_NR_TIME];
524 int ret;
525
f903129b 526 ret = max77686_rtc_tm_to_data(&alrm->time, data, info);
fca1dd03
JL		 527 if (ret < 0)
528 return ret;
529
530 mutex_lock(&info->lock);
531
532 ret = max77686_rtc_stop_alarm(info);
533 if (ret < 0)
534 goto out;
535
536 ret = regmap_bulk_write(info->max77686->rtc_regmap,
90a5698a
JMC		 537 info->drv_data->map[REG_ALARM1_SEC],
538 data, ARRAY_SIZE(data));
fca1dd03
JL		 539
540 if (ret < 0) {
541 dev_err(info->dev, "%s: fail to write alarm reg(%d)\n",
542 __func__, ret);
543 goto out;
544 }
545
546 ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
547 if (ret < 0)
548 goto out;
549
550 if (alrm->enabled)
551 ret = max77686_rtc_start_alarm(info);
552out:
553 mutex_unlock(&info->lock);
554 return ret;
555}
556
557static int max77686_rtc_alarm_irq_enable(struct device *dev,
558 unsigned int enabled)
559{
560 struct max77686_rtc_info *info = dev_get_drvdata(dev);
561 int ret;
562
563 mutex_lock(&info->lock);
564 if (enabled)
565 ret = max77686_rtc_start_alarm(info);
566 else
567 ret = max77686_rtc_stop_alarm(info);
568 mutex_unlock(&info->lock);
569
570 return ret;
571}
572
573static irqreturn_t max77686_rtc_alarm_irq(int irq, void *data)
574{
575 struct max77686_rtc_info *info = data;
576
577 dev_info(info->dev, "%s:irq(%d)\n", __func__, irq);
578
579 rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF);
580
581 return IRQ_HANDLED;
582}
583
584static const struct rtc_class_ops max77686_rtc_ops = {
585 .read_time = max77686_rtc_read_time,
586 .set_time = max77686_rtc_set_time,
587 .read_alarm = max77686_rtc_read_alarm,
588 .set_alarm = max77686_rtc_set_alarm,
589 .alarm_irq_enable = max77686_rtc_alarm_irq_enable,
590};
591
fca1dd03
JL		 592static int max77686_rtc_init_reg(struct max77686_rtc_info *info)
593{
594 u8 data[2];
595 int ret;
596
597 /* Set RTC control register : Binary mode, 24hour mdoe */
598 data[0] = (1 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
599 data[1] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
600
601 info->rtc_24hr_mode = 1;
602
862f9453 603 ret = regmap_bulk_write(info->max77686->rtc_regmap,
90a5698a
JMC		 604 info->drv_data->map[REG_RTC_CONTROLM],
605 data, ARRAY_SIZE(data));
fca1dd03
JL		 606 if (ret < 0) {
607 dev_err(info->dev, "%s: fail to write controlm reg(%d)\n",
608 __func__, ret);
609 return ret;
610 }
611
612 ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
613 return ret;
614}
615
fca1dd03
JL		 616static int max77686_rtc_probe(struct platform_device *pdev)
617{
618 struct max77686_dev *max77686 = dev_get_drvdata(pdev->dev.parent);
619 struct max77686_rtc_info *info;
01ea01b3 620 const struct platform_device_id *id = platform_get_device_id(pdev);
6f1c1e71 621 int ret;
fca1dd03 622
3cebeb53 623 dev_info(&pdev->dev, "%s\n", __func__);
fca1dd03 624
0f64f853
JH		 625 info = devm_kzalloc(&pdev->dev, sizeof(struct max77686_rtc_info),
626 GFP_KERNEL);
fca1dd03
JL		 627 if (!info)
628 return -ENOMEM;
629
630 mutex_init(&info->lock);
631 info->dev = &pdev->dev;
632 info->max77686 = max77686;
633 info->rtc = max77686->rtc;
01ea01b3
JMC		 634 info->drv_data = (const struct max77686_rtc_driver_data *)
635 id->driver_data;
6f1c1e71 636
f903129b
JMC		 637 if (!info->drv_data->separate_i2c_addr)
638 info->max77686->rtc_regmap = info->max77686->regmap;
639
fca1dd03
JL		 640 platform_set_drvdata(pdev, info);
641
642 ret = max77686_rtc_init_reg(info);
643
644 if (ret < 0) {
645 dev_err(&pdev->dev, "Failed to initialize RTC reg:%d\n", ret);
646 goto err_rtc;
647 }
648
fca1dd03
JL		 649 device_init_wakeup(&pdev->dev, 1);
650
f903129b 651 info->rtc_dev = devm_rtc_device_register(&pdev->dev, id->name,
f56950ec 652 &max77686_rtc_ops, THIS_MODULE);
fca1dd03
JL		 653
654 if (IS_ERR(info->rtc_dev)) {
fca1dd03
JL		 655 ret = PTR_ERR(info->rtc_dev);
656 dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret);
657 if (ret == 0)
658 ret = -EINVAL;
659 goto err_rtc;
660 }
6f1c1e71 661
1745d6d3
JMC		 662 if (!max77686->rtc_irq_data) {
663 ret = -EINVAL;
664 dev_err(&pdev->dev, "%s: no RTC regmap IRQ chip\n", __func__);
665 goto err_rtc;
666 }
667
6f1c1e71
JMC		 668 info->virq = regmap_irq_get_virq(max77686->rtc_irq_data,
669 MAX77686_RTCIRQ_RTCA1);
670 if (!info->virq) {
ad819039 671 ret = -ENXIO;
fca1dd03 672 goto err_rtc;
ad819039 673 }
fca1dd03 674
6f1c1e71
JMC		 675 ret = devm_request_threaded_irq(&pdev->dev, info->virq, NULL,
676 max77686_rtc_alarm_irq, 0, "rtc-alarm1", info);
ad819039 677 if (ret < 0)
fca1dd03
JL		 678 dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n",
679 info->virq, ret);
fca1dd03 680
fca1dd03 681err_rtc:
fca1dd03
JL		 682 return ret;
683}
684
e7f7fc73
DA		 685#ifdef CONFIG_PM_SLEEP
686static int max77686_rtc_suspend(struct device *dev)
687{
688 if (device_may_wakeup(dev)) {
689 struct max77686_rtc_info *info = dev_get_drvdata(dev);
690
691 return enable_irq_wake(info->virq);
692 }
693
694 return 0;
695}
696
697static int max77686_rtc_resume(struct device *dev)
698{
699 if (device_may_wakeup(dev)) {
700 struct max77686_rtc_info *info = dev_get_drvdata(dev);
701
702 return disable_irq_wake(info->virq);
703 }
704
705 return 0;
706}
707#endif
708
709static SIMPLE_DEV_PM_OPS(max77686_rtc_pm_ops,
710 max77686_rtc_suspend, max77686_rtc_resume);
711
fca1dd03 712static const struct platform_device_id rtc_id[] = {
01ea01b3 713 { "max77686-rtc", .driver_data = (kernel_ulong_t)&max77686_drv_data, },
f903129b 714 { "max77802-rtc", .driver_data = (kernel_ulong_t)&max77802_drv_data, },
fca1dd03
JL		 715 {},
716};
2d0cca0d 717MODULE_DEVICE_TABLE(platform, rtc_id);
fca1dd03
JL		 718
719static struct platform_driver max77686_rtc_driver = {
720 .driver = {
721 .name = "max77686-rtc",
e7f7fc73 722 .pm = &max77686_rtc_pm_ops,
fca1dd03
JL		 723 },
724 .probe = max77686_rtc_probe,
fca1dd03
JL		 725 .id_table = rtc_id,
726};
727
0c58ff58 728module_platform_driver(max77686_rtc_driver);
fca1dd03
JL		 729
730MODULE_DESCRIPTION("Maxim MAX77686 RTC driver");
f5b1d3c5 731MODULE_AUTHOR("Chiwoong Byun <woong.byun@samsung.com>");
fca1dd03 732MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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