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db68b189 | 1 | /* |
10211ae3 | 2 | * TI OMAP Real Time Clock interface for Linux |
db68b189 DB |
3 | * |
4 | * Copyright (C) 2003 MontaVista Software, Inc. | |
5 | * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com> | |
6 | * | |
7 | * Copyright (C) 2006 David Brownell (new RTC framework) | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version | |
12 | * 2 of the License, or (at your option) any later version. | |
13 | */ | |
14 | ||
15 | #include <linux/kernel.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/ioport.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/rtc.h> | |
21 | #include <linux/bcd.h> | |
22 | #include <linux/platform_device.h> | |
9e0344dc AM |
23 | #include <linux/of.h> |
24 | #include <linux/of_device.h> | |
fc9bd902 | 25 | #include <linux/pm_runtime.h> |
4b30c9fc | 26 | #include <linux/io.h> |
db68b189 | 27 | |
10211ae3 JH |
28 | /* |
29 | * The OMAP RTC is a year/month/day/hours/minutes/seconds BCD clock | |
db68b189 DB |
30 | * with century-range alarm matching, driven by the 32kHz clock. |
31 | * | |
32 | * The main user-visible ways it differs from PC RTCs are by omitting | |
33 | * "don't care" alarm fields and sub-second periodic IRQs, and having | |
34 | * an autoadjust mechanism to calibrate to the true oscillator rate. | |
35 | * | |
36 | * Board-specific wiring options include using split power mode with | |
37 | * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset), | |
38 | * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from | |
fa5b0782 SN |
39 | * low power modes) for OMAP1 boards (OMAP-L138 has this built into |
40 | * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment. | |
db68b189 DB |
41 | */ |
42 | ||
db68b189 DB |
43 | /* RTC registers */ |
44 | #define OMAP_RTC_SECONDS_REG 0x00 | |
45 | #define OMAP_RTC_MINUTES_REG 0x04 | |
46 | #define OMAP_RTC_HOURS_REG 0x08 | |
47 | #define OMAP_RTC_DAYS_REG 0x0C | |
48 | #define OMAP_RTC_MONTHS_REG 0x10 | |
49 | #define OMAP_RTC_YEARS_REG 0x14 | |
50 | #define OMAP_RTC_WEEKS_REG 0x18 | |
51 | ||
52 | #define OMAP_RTC_ALARM_SECONDS_REG 0x20 | |
53 | #define OMAP_RTC_ALARM_MINUTES_REG 0x24 | |
54 | #define OMAP_RTC_ALARM_HOURS_REG 0x28 | |
55 | #define OMAP_RTC_ALARM_DAYS_REG 0x2c | |
56 | #define OMAP_RTC_ALARM_MONTHS_REG 0x30 | |
57 | #define OMAP_RTC_ALARM_YEARS_REG 0x34 | |
58 | ||
59 | #define OMAP_RTC_CTRL_REG 0x40 | |
60 | #define OMAP_RTC_STATUS_REG 0x44 | |
61 | #define OMAP_RTC_INTERRUPTS_REG 0x48 | |
62 | ||
63 | #define OMAP_RTC_COMP_LSB_REG 0x4c | |
64 | #define OMAP_RTC_COMP_MSB_REG 0x50 | |
65 | #define OMAP_RTC_OSC_REG 0x54 | |
66 | ||
cab1458c AM |
67 | #define OMAP_RTC_KICK0_REG 0x6c |
68 | #define OMAP_RTC_KICK1_REG 0x70 | |
69 | ||
8af750e3 HG |
70 | #define OMAP_RTC_IRQWAKEEN 0x7c |
71 | ||
222a12fc JH |
72 | #define OMAP_RTC_ALARM2_SECONDS_REG 0x80 |
73 | #define OMAP_RTC_ALARM2_MINUTES_REG 0x84 | |
74 | #define OMAP_RTC_ALARM2_HOURS_REG 0x88 | |
75 | #define OMAP_RTC_ALARM2_DAYS_REG 0x8c | |
76 | #define OMAP_RTC_ALARM2_MONTHS_REG 0x90 | |
77 | #define OMAP_RTC_ALARM2_YEARS_REG 0x94 | |
78 | ||
79 | #define OMAP_RTC_PMIC_REG 0x98 | |
80 | ||
db68b189 | 81 | /* OMAP_RTC_CTRL_REG bit fields: */ |
92adb96a SN |
82 | #define OMAP_RTC_CTRL_SPLIT BIT(7) |
83 | #define OMAP_RTC_CTRL_DISABLE BIT(6) | |
84 | #define OMAP_RTC_CTRL_SET_32_COUNTER BIT(5) | |
85 | #define OMAP_RTC_CTRL_TEST BIT(4) | |
86 | #define OMAP_RTC_CTRL_MODE_12_24 BIT(3) | |
87 | #define OMAP_RTC_CTRL_AUTO_COMP BIT(2) | |
88 | #define OMAP_RTC_CTRL_ROUND_30S BIT(1) | |
89 | #define OMAP_RTC_CTRL_STOP BIT(0) | |
db68b189 DB |
90 | |
91 | /* OMAP_RTC_STATUS_REG bit fields: */ | |
92adb96a | 92 | #define OMAP_RTC_STATUS_POWER_UP BIT(7) |
222a12fc | 93 | #define OMAP_RTC_STATUS_ALARM2 BIT(7) |
92adb96a SN |
94 | #define OMAP_RTC_STATUS_ALARM BIT(6) |
95 | #define OMAP_RTC_STATUS_1D_EVENT BIT(5) | |
96 | #define OMAP_RTC_STATUS_1H_EVENT BIT(4) | |
97 | #define OMAP_RTC_STATUS_1M_EVENT BIT(3) | |
98 | #define OMAP_RTC_STATUS_1S_EVENT BIT(2) | |
99 | #define OMAP_RTC_STATUS_RUN BIT(1) | |
100 | #define OMAP_RTC_STATUS_BUSY BIT(0) | |
db68b189 DB |
101 | |
102 | /* OMAP_RTC_INTERRUPTS_REG bit fields: */ | |
222a12fc | 103 | #define OMAP_RTC_INTERRUPTS_IT_ALARM2 BIT(4) |
92adb96a SN |
104 | #define OMAP_RTC_INTERRUPTS_IT_ALARM BIT(3) |
105 | #define OMAP_RTC_INTERRUPTS_IT_TIMER BIT(2) | |
db68b189 | 106 | |
cd914bba SN |
107 | /* OMAP_RTC_OSC_REG bit fields: */ |
108 | #define OMAP_RTC_OSC_32KCLK_EN BIT(6) | |
109 | ||
8af750e3 | 110 | /* OMAP_RTC_IRQWAKEEN bit fields: */ |
92adb96a | 111 | #define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN BIT(1) |
8af750e3 | 112 | |
222a12fc JH |
113 | /* OMAP_RTC_PMIC bit fields: */ |
114 | #define OMAP_RTC_PMIC_POWER_EN_EN BIT(16) | |
115 | ||
cab1458c AM |
116 | /* OMAP_RTC_KICKER values */ |
117 | #define KICK0_VALUE 0x83e70b13 | |
118 | #define KICK1_VALUE 0x95a4f1e0 | |
119 | ||
2153f949 JH |
120 | struct omap_rtc_device_type { |
121 | bool has_32kclk_en; | |
122 | bool has_kicker; | |
123 | bool has_irqwakeen; | |
222a12fc | 124 | bool has_pmic_mode; |
9291e340 | 125 | bool has_power_up_reset; |
2153f949 | 126 | }; |
cd914bba | 127 | |
55ba953a JH |
128 | struct omap_rtc { |
129 | struct rtc_device *rtc; | |
130 | void __iomem *base; | |
131 | int irq_alarm; | |
132 | int irq_timer; | |
133 | u8 interrupts_reg; | |
222a12fc | 134 | bool is_pmic_controller; |
2153f949 | 135 | const struct omap_rtc_device_type *type; |
55ba953a | 136 | }; |
db68b189 | 137 | |
55ba953a JH |
138 | static inline u8 rtc_read(struct omap_rtc *rtc, unsigned int reg) |
139 | { | |
140 | return readb(rtc->base + reg); | |
141 | } | |
cab1458c | 142 | |
c253a896 JH |
143 | static inline u32 rtc_readl(struct omap_rtc *rtc, unsigned int reg) |
144 | { | |
145 | return readl(rtc->base + reg); | |
146 | } | |
147 | ||
55ba953a JH |
148 | static inline void rtc_write(struct omap_rtc *rtc, unsigned int reg, u8 val) |
149 | { | |
150 | writeb(val, rtc->base + reg); | |
151 | } | |
db68b189 | 152 | |
55ba953a JH |
153 | static inline void rtc_writel(struct omap_rtc *rtc, unsigned int reg, u32 val) |
154 | { | |
155 | writel(val, rtc->base + reg); | |
156 | } | |
db68b189 | 157 | |
10211ae3 JH |
158 | /* |
159 | * We rely on the rtc framework to handle locking (rtc->ops_lock), | |
db68b189 DB |
160 | * so the only other requirement is that register accesses which |
161 | * require BUSY to be clear are made with IRQs locally disabled | |
162 | */ | |
55ba953a | 163 | static void rtc_wait_not_busy(struct omap_rtc *rtc) |
db68b189 | 164 | { |
10211ae3 JH |
165 | int count; |
166 | u8 status; | |
db68b189 DB |
167 | |
168 | /* BUSY may stay active for 1/32768 second (~30 usec) */ | |
169 | for (count = 0; count < 50; count++) { | |
55ba953a | 170 | status = rtc_read(rtc, OMAP_RTC_STATUS_REG); |
10211ae3 | 171 | if (!(status & OMAP_RTC_STATUS_BUSY)) |
db68b189 DB |
172 | break; |
173 | udelay(1); | |
174 | } | |
175 | /* now we have ~15 usec to read/write various registers */ | |
176 | } | |
177 | ||
55ba953a | 178 | static irqreturn_t rtc_irq(int irq, void *dev_id) |
db68b189 | 179 | { |
10211ae3 JH |
180 | struct omap_rtc *rtc = dev_id; |
181 | unsigned long events = 0; | |
182 | u8 irq_data; | |
db68b189 | 183 | |
55ba953a | 184 | irq_data = rtc_read(rtc, OMAP_RTC_STATUS_REG); |
db68b189 DB |
185 | |
186 | /* alarm irq? */ | |
187 | if (irq_data & OMAP_RTC_STATUS_ALARM) { | |
55ba953a | 188 | rtc_write(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM); |
db68b189 DB |
189 | events |= RTC_IRQF | RTC_AF; |
190 | } | |
191 | ||
192 | /* 1/sec periodic/update irq? */ | |
193 | if (irq_data & OMAP_RTC_STATUS_1S_EVENT) | |
194 | events |= RTC_IRQF | RTC_UF; | |
195 | ||
55ba953a | 196 | rtc_update_irq(rtc->rtc, 1, events); |
db68b189 DB |
197 | |
198 | return IRQ_HANDLED; | |
199 | } | |
200 | ||
16380c15 JS |
201 | static int omap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
202 | { | |
55ba953a | 203 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
ab7f580b | 204 | u8 reg, irqwake_reg = 0; |
16380c15 JS |
205 | |
206 | local_irq_disable(); | |
55ba953a JH |
207 | rtc_wait_not_busy(rtc); |
208 | reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); | |
2153f949 | 209 | if (rtc->type->has_irqwakeen) |
55ba953a | 210 | irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN); |
ab7f580b LV |
211 | |
212 | if (enabled) { | |
16380c15 | 213 | reg |= OMAP_RTC_INTERRUPTS_IT_ALARM; |
ab7f580b LV |
214 | irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; |
215 | } else { | |
16380c15 | 216 | reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM; |
ab7f580b LV |
217 | irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; |
218 | } | |
55ba953a JH |
219 | rtc_wait_not_busy(rtc); |
220 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg); | |
2153f949 | 221 | if (rtc->type->has_irqwakeen) |
55ba953a | 222 | rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg); |
16380c15 JS |
223 | local_irq_enable(); |
224 | ||
225 | return 0; | |
226 | } | |
227 | ||
db68b189 DB |
228 | /* this hardware doesn't support "don't care" alarm fields */ |
229 | static int tm2bcd(struct rtc_time *tm) | |
230 | { | |
231 | if (rtc_valid_tm(tm) != 0) | |
232 | return -EINVAL; | |
233 | ||
fe20ba70 AB |
234 | tm->tm_sec = bin2bcd(tm->tm_sec); |
235 | tm->tm_min = bin2bcd(tm->tm_min); | |
236 | tm->tm_hour = bin2bcd(tm->tm_hour); | |
237 | tm->tm_mday = bin2bcd(tm->tm_mday); | |
db68b189 | 238 | |
fe20ba70 | 239 | tm->tm_mon = bin2bcd(tm->tm_mon + 1); |
db68b189 DB |
240 | |
241 | /* epoch == 1900 */ | |
242 | if (tm->tm_year < 100 || tm->tm_year > 199) | |
243 | return -EINVAL; | |
fe20ba70 | 244 | tm->tm_year = bin2bcd(tm->tm_year - 100); |
db68b189 DB |
245 | |
246 | return 0; | |
247 | } | |
248 | ||
249 | static void bcd2tm(struct rtc_time *tm) | |
250 | { | |
fe20ba70 AB |
251 | tm->tm_sec = bcd2bin(tm->tm_sec); |
252 | tm->tm_min = bcd2bin(tm->tm_min); | |
253 | tm->tm_hour = bcd2bin(tm->tm_hour); | |
254 | tm->tm_mday = bcd2bin(tm->tm_mday); | |
255 | tm->tm_mon = bcd2bin(tm->tm_mon) - 1; | |
db68b189 | 256 | /* epoch == 1900 */ |
fe20ba70 | 257 | tm->tm_year = bcd2bin(tm->tm_year) + 100; |
db68b189 DB |
258 | } |
259 | ||
cbbe326f | 260 | static void omap_rtc_read_time_raw(struct omap_rtc *rtc, struct rtc_time *tm) |
db68b189 | 261 | { |
55ba953a JH |
262 | tm->tm_sec = rtc_read(rtc, OMAP_RTC_SECONDS_REG); |
263 | tm->tm_min = rtc_read(rtc, OMAP_RTC_MINUTES_REG); | |
264 | tm->tm_hour = rtc_read(rtc, OMAP_RTC_HOURS_REG); | |
265 | tm->tm_mday = rtc_read(rtc, OMAP_RTC_DAYS_REG); | |
266 | tm->tm_mon = rtc_read(rtc, OMAP_RTC_MONTHS_REG); | |
267 | tm->tm_year = rtc_read(rtc, OMAP_RTC_YEARS_REG); | |
cbbe326f JH |
268 | } |
269 | ||
270 | static int omap_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
271 | { | |
272 | struct omap_rtc *rtc = dev_get_drvdata(dev); | |
db68b189 | 273 | |
cbbe326f JH |
274 | /* we don't report wday/yday/isdst ... */ |
275 | local_irq_disable(); | |
276 | rtc_wait_not_busy(rtc); | |
277 | omap_rtc_read_time_raw(rtc, tm); | |
db68b189 DB |
278 | local_irq_enable(); |
279 | ||
280 | bcd2tm(tm); | |
10211ae3 | 281 | |
db68b189 DB |
282 | return 0; |
283 | } | |
284 | ||
285 | static int omap_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
286 | { | |
55ba953a JH |
287 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
288 | ||
db68b189 DB |
289 | if (tm2bcd(tm) < 0) |
290 | return -EINVAL; | |
10211ae3 | 291 | |
db68b189 | 292 | local_irq_disable(); |
55ba953a | 293 | rtc_wait_not_busy(rtc); |
db68b189 | 294 | |
55ba953a JH |
295 | rtc_write(rtc, OMAP_RTC_YEARS_REG, tm->tm_year); |
296 | rtc_write(rtc, OMAP_RTC_MONTHS_REG, tm->tm_mon); | |
297 | rtc_write(rtc, OMAP_RTC_DAYS_REG, tm->tm_mday); | |
298 | rtc_write(rtc, OMAP_RTC_HOURS_REG, tm->tm_hour); | |
299 | rtc_write(rtc, OMAP_RTC_MINUTES_REG, tm->tm_min); | |
300 | rtc_write(rtc, OMAP_RTC_SECONDS_REG, tm->tm_sec); | |
db68b189 DB |
301 | |
302 | local_irq_enable(); | |
303 | ||
304 | return 0; | |
305 | } | |
306 | ||
307 | static int omap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm) | |
308 | { | |
55ba953a | 309 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
10211ae3 | 310 | u8 interrupts; |
55ba953a | 311 | |
db68b189 | 312 | local_irq_disable(); |
55ba953a | 313 | rtc_wait_not_busy(rtc); |
db68b189 | 314 | |
55ba953a JH |
315 | alm->time.tm_sec = rtc_read(rtc, OMAP_RTC_ALARM_SECONDS_REG); |
316 | alm->time.tm_min = rtc_read(rtc, OMAP_RTC_ALARM_MINUTES_REG); | |
317 | alm->time.tm_hour = rtc_read(rtc, OMAP_RTC_ALARM_HOURS_REG); | |
318 | alm->time.tm_mday = rtc_read(rtc, OMAP_RTC_ALARM_DAYS_REG); | |
319 | alm->time.tm_mon = rtc_read(rtc, OMAP_RTC_ALARM_MONTHS_REG); | |
320 | alm->time.tm_year = rtc_read(rtc, OMAP_RTC_ALARM_YEARS_REG); | |
db68b189 DB |
321 | |
322 | local_irq_enable(); | |
323 | ||
324 | bcd2tm(&alm->time); | |
10211ae3 JH |
325 | |
326 | interrupts = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); | |
327 | alm->enabled = !!(interrupts & OMAP_RTC_INTERRUPTS_IT_ALARM); | |
db68b189 DB |
328 | |
329 | return 0; | |
330 | } | |
331 | ||
332 | static int omap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm) | |
333 | { | |
55ba953a | 334 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
ab7f580b | 335 | u8 reg, irqwake_reg = 0; |
db68b189 | 336 | |
db68b189 DB |
337 | if (tm2bcd(&alm->time) < 0) |
338 | return -EINVAL; | |
339 | ||
340 | local_irq_disable(); | |
55ba953a | 341 | rtc_wait_not_busy(rtc); |
db68b189 | 342 | |
55ba953a JH |
343 | rtc_write(rtc, OMAP_RTC_ALARM_YEARS_REG, alm->time.tm_year); |
344 | rtc_write(rtc, OMAP_RTC_ALARM_MONTHS_REG, alm->time.tm_mon); | |
345 | rtc_write(rtc, OMAP_RTC_ALARM_DAYS_REG, alm->time.tm_mday); | |
346 | rtc_write(rtc, OMAP_RTC_ALARM_HOURS_REG, alm->time.tm_hour); | |
347 | rtc_write(rtc, OMAP_RTC_ALARM_MINUTES_REG, alm->time.tm_min); | |
348 | rtc_write(rtc, OMAP_RTC_ALARM_SECONDS_REG, alm->time.tm_sec); | |
db68b189 | 349 | |
55ba953a | 350 | reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); |
2153f949 | 351 | if (rtc->type->has_irqwakeen) |
55ba953a | 352 | irqwake_reg = rtc_read(rtc, OMAP_RTC_IRQWAKEEN); |
ab7f580b LV |
353 | |
354 | if (alm->enabled) { | |
db68b189 | 355 | reg |= OMAP_RTC_INTERRUPTS_IT_ALARM; |
ab7f580b LV |
356 | irqwake_reg |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; |
357 | } else { | |
db68b189 | 358 | reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM; |
ab7f580b LV |
359 | irqwake_reg &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN; |
360 | } | |
55ba953a | 361 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, reg); |
2153f949 | 362 | if (rtc->type->has_irqwakeen) |
55ba953a | 363 | rtc_write(rtc, OMAP_RTC_IRQWAKEEN, irqwake_reg); |
db68b189 DB |
364 | |
365 | local_irq_enable(); | |
366 | ||
367 | return 0; | |
368 | } | |
369 | ||
222a12fc JH |
370 | static struct omap_rtc *omap_rtc_power_off_rtc; |
371 | ||
372 | /* | |
373 | * omap_rtc_poweroff: RTC-controlled power off | |
374 | * | |
375 | * The RTC can be used to control an external PMIC via the pmic_power_en pin, | |
376 | * which can be configured to transition to OFF on ALARM2 events. | |
377 | * | |
378 | * Notes: | |
379 | * The two-second alarm offset is the shortest offset possible as the alarm | |
380 | * registers must be set before the next timer update and the offset | |
381 | * calculation is too heavy for everything to be done within a single access | |
382 | * period (~15 us). | |
383 | * | |
384 | * Called with local interrupts disabled. | |
385 | */ | |
386 | static void omap_rtc_power_off(void) | |
387 | { | |
388 | struct omap_rtc *rtc = omap_rtc_power_off_rtc; | |
389 | struct rtc_time tm; | |
390 | unsigned long now; | |
391 | u32 val; | |
392 | ||
393 | /* enable pmic_power_en control */ | |
394 | val = rtc_readl(rtc, OMAP_RTC_PMIC_REG); | |
395 | rtc_writel(rtc, OMAP_RTC_PMIC_REG, val | OMAP_RTC_PMIC_POWER_EN_EN); | |
396 | ||
397 | /* set alarm two seconds from now */ | |
398 | omap_rtc_read_time_raw(rtc, &tm); | |
399 | bcd2tm(&tm); | |
400 | rtc_tm_to_time(&tm, &now); | |
401 | rtc_time_to_tm(now + 2, &tm); | |
402 | ||
403 | if (tm2bcd(&tm) < 0) { | |
404 | dev_err(&rtc->rtc->dev, "power off failed\n"); | |
405 | return; | |
406 | } | |
407 | ||
408 | rtc_wait_not_busy(rtc); | |
409 | ||
410 | rtc_write(rtc, OMAP_RTC_ALARM2_SECONDS_REG, tm.tm_sec); | |
411 | rtc_write(rtc, OMAP_RTC_ALARM2_MINUTES_REG, tm.tm_min); | |
412 | rtc_write(rtc, OMAP_RTC_ALARM2_HOURS_REG, tm.tm_hour); | |
413 | rtc_write(rtc, OMAP_RTC_ALARM2_DAYS_REG, tm.tm_mday); | |
414 | rtc_write(rtc, OMAP_RTC_ALARM2_MONTHS_REG, tm.tm_mon); | |
415 | rtc_write(rtc, OMAP_RTC_ALARM2_YEARS_REG, tm.tm_year); | |
416 | ||
417 | /* | |
418 | * enable ALARM2 interrupt | |
419 | * | |
420 | * NOTE: this fails on AM3352 if rtc_write (writeb) is used | |
421 | */ | |
422 | val = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); | |
423 | rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, | |
424 | val | OMAP_RTC_INTERRUPTS_IT_ALARM2); | |
425 | ||
426 | /* | |
427 | * Wait for alarm to trigger (within two seconds) and external PMIC to | |
428 | * power off the system. Add a 500 ms margin for external latencies | |
429 | * (e.g. debounce circuits). | |
430 | */ | |
431 | mdelay(2500); | |
432 | } | |
433 | ||
db68b189 | 434 | static struct rtc_class_ops omap_rtc_ops = { |
db68b189 DB |
435 | .read_time = omap_rtc_read_time, |
436 | .set_time = omap_rtc_set_time, | |
437 | .read_alarm = omap_rtc_read_alarm, | |
438 | .set_alarm = omap_rtc_set_alarm, | |
16380c15 | 439 | .alarm_irq_enable = omap_rtc_alarm_irq_enable, |
db68b189 DB |
440 | }; |
441 | ||
2153f949 | 442 | static const struct omap_rtc_device_type omap_rtc_default_type = { |
9291e340 | 443 | .has_power_up_reset = true, |
2153f949 JH |
444 | }; |
445 | ||
446 | static const struct omap_rtc_device_type omap_rtc_am3352_type = { | |
447 | .has_32kclk_en = true, | |
448 | .has_kicker = true, | |
449 | .has_irqwakeen = true, | |
222a12fc | 450 | .has_pmic_mode = true, |
2153f949 JH |
451 | }; |
452 | ||
453 | static const struct omap_rtc_device_type omap_rtc_da830_type = { | |
454 | .has_kicker = true, | |
455 | }; | |
9e0344dc | 456 | |
2153f949 | 457 | static const struct platform_device_id omap_rtc_id_table[] = { |
cab1458c | 458 | { |
a430ca22 | 459 | .name = "omap_rtc", |
2153f949 JH |
460 | .driver_data = (kernel_ulong_t)&omap_rtc_default_type, |
461 | }, { | |
8af750e3 | 462 | .name = "am3352-rtc", |
2153f949 JH |
463 | .driver_data = (kernel_ulong_t)&omap_rtc_am3352_type, |
464 | }, { | |
cab1458c | 465 | .name = "da830-rtc", |
2153f949 JH |
466 | .driver_data = (kernel_ulong_t)&omap_rtc_da830_type, |
467 | }, { | |
468 | /* sentinel */ | |
469 | } | |
cab1458c | 470 | }; |
2153f949 | 471 | MODULE_DEVICE_TABLE(platform, omap_rtc_id_table); |
cab1458c | 472 | |
9e0344dc | 473 | static const struct of_device_id omap_rtc_of_match[] = { |
2153f949 JH |
474 | { |
475 | .compatible = "ti,am3352-rtc", | |
476 | .data = &omap_rtc_am3352_type, | |
477 | }, { | |
478 | .compatible = "ti,da830-rtc", | |
479 | .data = &omap_rtc_da830_type, | |
480 | }, { | |
481 | /* sentinel */ | |
482 | } | |
9e0344dc AM |
483 | }; |
484 | MODULE_DEVICE_TABLE(of, omap_rtc_of_match); | |
485 | ||
71fc8224 | 486 | static int __init omap_rtc_probe(struct platform_device *pdev) |
db68b189 | 487 | { |
10211ae3 JH |
488 | struct omap_rtc *rtc; |
489 | struct resource *res; | |
490 | u8 reg, mask, new_ctrl; | |
cab1458c | 491 | const struct platform_device_id *id_entry; |
9e0344dc | 492 | const struct of_device_id *of_id; |
437b37a6 | 493 | int ret; |
9e0344dc | 494 | |
55ba953a JH |
495 | rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); |
496 | if (!rtc) | |
497 | return -ENOMEM; | |
498 | ||
9e0344dc | 499 | of_id = of_match_device(omap_rtc_of_match, &pdev->dev); |
2153f949 JH |
500 | if (of_id) { |
501 | rtc->type = of_id->data; | |
222a12fc JH |
502 | rtc->is_pmic_controller = rtc->type->has_pmic_mode && |
503 | of_property_read_bool(pdev->dev.of_node, | |
504 | "ti,system-power-controller"); | |
2153f949 JH |
505 | } else { |
506 | id_entry = platform_get_device_id(pdev); | |
507 | rtc->type = (void *)id_entry->driver_data; | |
337b600f SN |
508 | } |
509 | ||
55ba953a JH |
510 | rtc->irq_timer = platform_get_irq(pdev, 0); |
511 | if (rtc->irq_timer <= 0) | |
db68b189 | 512 | return -ENOENT; |
db68b189 | 513 | |
55ba953a JH |
514 | rtc->irq_alarm = platform_get_irq(pdev, 1); |
515 | if (rtc->irq_alarm <= 0) | |
db68b189 | 516 | return -ENOENT; |
db68b189 | 517 | |
db68b189 | 518 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
55ba953a JH |
519 | rtc->base = devm_ioremap_resource(&pdev->dev, res); |
520 | if (IS_ERR(rtc->base)) | |
521 | return PTR_ERR(rtc->base); | |
522 | ||
523 | platform_set_drvdata(pdev, rtc); | |
8cfde8c1 | 524 | |
fc9bd902 VH |
525 | /* Enable the clock/module so that we can access the registers */ |
526 | pm_runtime_enable(&pdev->dev); | |
527 | pm_runtime_get_sync(&pdev->dev); | |
528 | ||
2153f949 | 529 | if (rtc->type->has_kicker) { |
55ba953a JH |
530 | rtc_writel(rtc, OMAP_RTC_KICK0_REG, KICK0_VALUE); |
531 | rtc_writel(rtc, OMAP_RTC_KICK1_REG, KICK1_VALUE); | |
cab1458c AM |
532 | } |
533 | ||
1ed8b5d2 JH |
534 | /* |
535 | * disable interrupts | |
536 | * | |
537 | * NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used | |
db68b189 | 538 | */ |
55ba953a | 539 | rtc_writel(rtc, OMAP_RTC_INTERRUPTS_REG, 0); |
db68b189 | 540 | |
cd914bba | 541 | /* enable RTC functional clock */ |
2153f949 | 542 | if (rtc->type->has_32kclk_en) { |
55ba953a JH |
543 | reg = rtc_read(rtc, OMAP_RTC_OSC_REG); |
544 | rtc_writel(rtc, OMAP_RTC_OSC_REG, | |
545 | reg | OMAP_RTC_OSC_32KCLK_EN); | |
44c63a57 | 546 | } |
cd914bba | 547 | |
db68b189 | 548 | /* clear old status */ |
55ba953a | 549 | reg = rtc_read(rtc, OMAP_RTC_STATUS_REG); |
9291e340 JH |
550 | |
551 | mask = OMAP_RTC_STATUS_ALARM; | |
552 | ||
222a12fc JH |
553 | if (rtc->type->has_pmic_mode) |
554 | mask |= OMAP_RTC_STATUS_ALARM2; | |
555 | ||
9291e340 JH |
556 | if (rtc->type->has_power_up_reset) { |
557 | mask |= OMAP_RTC_STATUS_POWER_UP; | |
558 | if (reg & OMAP_RTC_STATUS_POWER_UP) | |
559 | dev_info(&pdev->dev, "RTC power up reset detected\n"); | |
db68b189 | 560 | } |
9291e340 JH |
561 | |
562 | if (reg & mask) | |
563 | rtc_write(rtc, OMAP_RTC_STATUS_REG, reg & mask); | |
db68b189 | 564 | |
db68b189 | 565 | /* On boards with split power, RTC_ON_NOFF won't reset the RTC */ |
55ba953a | 566 | reg = rtc_read(rtc, OMAP_RTC_CTRL_REG); |
10211ae3 | 567 | if (reg & OMAP_RTC_CTRL_STOP) |
397b630a | 568 | dev_info(&pdev->dev, "already running\n"); |
db68b189 DB |
569 | |
570 | /* force to 24 hour mode */ | |
10211ae3 | 571 | new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT | OMAP_RTC_CTRL_AUTO_COMP); |
db68b189 DB |
572 | new_ctrl |= OMAP_RTC_CTRL_STOP; |
573 | ||
10211ae3 JH |
574 | /* |
575 | * BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE: | |
db68b189 | 576 | * |
fa5b0782 SN |
577 | * - Device wake-up capability setting should come through chip |
578 | * init logic. OMAP1 boards should initialize the "wakeup capable" | |
579 | * flag in the platform device if the board is wired right for | |
580 | * being woken up by RTC alarm. For OMAP-L138, this capability | |
581 | * is built into the SoC by the "Deep Sleep" capability. | |
db68b189 DB |
582 | * |
583 | * - Boards wired so RTC_ON_nOFF is used as the reset signal, | |
584 | * rather than nPWRON_RESET, should forcibly enable split | |
585 | * power mode. (Some chip errata report that RTC_CTRL_SPLIT | |
586 | * is write-only, and always reads as zero...) | |
587 | */ | |
db68b189 | 588 | |
10211ae3 | 589 | if (new_ctrl & OMAP_RTC_CTRL_SPLIT) |
397b630a | 590 | dev_info(&pdev->dev, "split power mode\n"); |
db68b189 DB |
591 | |
592 | if (reg != new_ctrl) | |
55ba953a | 593 | rtc_write(rtc, OMAP_RTC_CTRL_REG, new_ctrl); |
db68b189 | 594 | |
4390ce00 JH |
595 | device_init_wakeup(&pdev->dev, true); |
596 | ||
55ba953a | 597 | rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name, |
4390ce00 | 598 | &omap_rtc_ops, THIS_MODULE); |
55ba953a JH |
599 | if (IS_ERR(rtc->rtc)) { |
600 | ret = PTR_ERR(rtc->rtc); | |
4390ce00 JH |
601 | goto err; |
602 | } | |
4390ce00 JH |
603 | |
604 | /* handle periodic and alarm irqs */ | |
55ba953a JH |
605 | ret = devm_request_irq(&pdev->dev, rtc->irq_timer, rtc_irq, 0, |
606 | dev_name(&rtc->rtc->dev), rtc); | |
4390ce00 JH |
607 | if (ret) |
608 | goto err; | |
609 | ||
55ba953a JH |
610 | if (rtc->irq_timer != rtc->irq_alarm) { |
611 | ret = devm_request_irq(&pdev->dev, rtc->irq_alarm, rtc_irq, 0, | |
612 | dev_name(&rtc->rtc->dev), rtc); | |
4390ce00 JH |
613 | if (ret) |
614 | goto err; | |
615 | } | |
616 | ||
222a12fc JH |
617 | if (rtc->is_pmic_controller) { |
618 | if (!pm_power_off) { | |
619 | omap_rtc_power_off_rtc = rtc; | |
620 | pm_power_off = omap_rtc_power_off; | |
621 | } | |
622 | } | |
623 | ||
db68b189 DB |
624 | return 0; |
625 | ||
437b37a6 | 626 | err: |
7ecd9a3f | 627 | device_init_wakeup(&pdev->dev, false); |
2153f949 | 628 | if (rtc->type->has_kicker) |
55ba953a | 629 | rtc_writel(rtc, OMAP_RTC_KICK0_REG, 0); |
fc9bd902 VH |
630 | pm_runtime_put_sync(&pdev->dev); |
631 | pm_runtime_disable(&pdev->dev); | |
437b37a6 JH |
632 | |
633 | return ret; | |
db68b189 DB |
634 | } |
635 | ||
71fc8224 | 636 | static int __exit omap_rtc_remove(struct platform_device *pdev) |
db68b189 | 637 | { |
55ba953a | 638 | struct omap_rtc *rtc = platform_get_drvdata(pdev); |
db68b189 | 639 | |
222a12fc JH |
640 | if (pm_power_off == omap_rtc_power_off && |
641 | omap_rtc_power_off_rtc == rtc) { | |
642 | pm_power_off = NULL; | |
643 | omap_rtc_power_off_rtc = NULL; | |
644 | } | |
645 | ||
db68b189 DB |
646 | device_init_wakeup(&pdev->dev, 0); |
647 | ||
648 | /* leave rtc running, but disable irqs */ | |
55ba953a | 649 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0); |
db68b189 | 650 | |
2153f949 | 651 | if (rtc->type->has_kicker) |
55ba953a | 652 | rtc_writel(rtc, OMAP_RTC_KICK0_REG, 0); |
fc9bd902 VH |
653 | |
654 | /* Disable the clock/module */ | |
655 | pm_runtime_put_sync(&pdev->dev); | |
656 | pm_runtime_disable(&pdev->dev); | |
657 | ||
db68b189 DB |
658 | return 0; |
659 | } | |
660 | ||
04ebc359 | 661 | #ifdef CONFIG_PM_SLEEP |
04ebc359 | 662 | static int omap_rtc_suspend(struct device *dev) |
db68b189 | 663 | { |
55ba953a JH |
664 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
665 | ||
666 | rtc->interrupts_reg = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); | |
db68b189 | 667 | |
10211ae3 JH |
668 | /* |
669 | * FIXME: the RTC alarm is not currently acting as a wakeup event | |
8af750e3 HG |
670 | * source on some platforms, and in fact this enable() call is just |
671 | * saving a flag that's never used... | |
db68b189 | 672 | */ |
ab7f580b | 673 | if (device_may_wakeup(dev)) |
55ba953a | 674 | enable_irq_wake(rtc->irq_alarm); |
ab7f580b | 675 | else |
55ba953a | 676 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, 0); |
db68b189 | 677 | |
fc9bd902 | 678 | /* Disable the clock/module */ |
04ebc359 | 679 | pm_runtime_put_sync(dev); |
fc9bd902 | 680 | |
db68b189 DB |
681 | return 0; |
682 | } | |
683 | ||
04ebc359 | 684 | static int omap_rtc_resume(struct device *dev) |
db68b189 | 685 | { |
55ba953a JH |
686 | struct omap_rtc *rtc = dev_get_drvdata(dev); |
687 | ||
fc9bd902 | 688 | /* Enable the clock/module so that we can access the registers */ |
04ebc359 | 689 | pm_runtime_get_sync(dev); |
fc9bd902 | 690 | |
ab7f580b | 691 | if (device_may_wakeup(dev)) |
55ba953a | 692 | disable_irq_wake(rtc->irq_alarm); |
ab7f580b | 693 | else |
55ba953a | 694 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, rtc->interrupts_reg); |
ab7f580b | 695 | |
db68b189 DB |
696 | return 0; |
697 | } | |
db68b189 DB |
698 | #endif |
699 | ||
04ebc359 JH |
700 | static SIMPLE_DEV_PM_OPS(omap_rtc_pm_ops, omap_rtc_suspend, omap_rtc_resume); |
701 | ||
db68b189 DB |
702 | static void omap_rtc_shutdown(struct platform_device *pdev) |
703 | { | |
55ba953a | 704 | struct omap_rtc *rtc = platform_get_drvdata(pdev); |
8ad5c722 | 705 | u8 mask; |
55ba953a | 706 | |
8ad5c722 JH |
707 | /* |
708 | * Keep the ALARM interrupt enabled to allow the system to power up on | |
709 | * alarm events. | |
710 | */ | |
711 | mask = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); | |
712 | mask &= OMAP_RTC_INTERRUPTS_IT_ALARM; | |
713 | rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, mask); | |
db68b189 DB |
714 | } |
715 | ||
db68b189 | 716 | static struct platform_driver omap_rtc_driver = { |
71fc8224 | 717 | .remove = __exit_p(omap_rtc_remove), |
db68b189 DB |
718 | .shutdown = omap_rtc_shutdown, |
719 | .driver = { | |
a430ca22 | 720 | .name = "omap_rtc", |
db68b189 | 721 | .owner = THIS_MODULE, |
04ebc359 | 722 | .pm = &omap_rtc_pm_ops, |
616b7341 | 723 | .of_match_table = omap_rtc_of_match, |
db68b189 | 724 | }, |
2153f949 | 725 | .id_table = omap_rtc_id_table, |
db68b189 DB |
726 | }; |
727 | ||
09c5a36b | 728 | module_platform_driver_probe(omap_rtc_driver, omap_rtc_probe); |
db68b189 | 729 | |
a430ca22 | 730 | MODULE_ALIAS("platform:omap_rtc"); |
db68b189 DB |
731 | MODULE_AUTHOR("George G. Davis (and others)"); |
732 | MODULE_LICENSE("GPL"); |