[deliverable/linux.git] / drivers / rtc / rtc-omap.c

/*
 * TI OMAP1 Real Time Clock interface for Linux
 *
 * Copyright (C) 2003 MontaVista Software, Inc.
 * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
 *
 * Copyright (C) 2006 David Brownell (new RTC framework)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/delay.h>
#include <linux/rtc.h>
#include <linux/bcd.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>
#include <linux/io.h>

/* The OMAP1 RTC is a year/month/day/hours/minutes/seconds BCD clock
 * with century-range alarm matching, driven by the 32kHz clock.
 *
 * The main user-visible ways it differs from PC RTCs are by omitting
 * "don't care" alarm fields and sub-second periodic IRQs, and having
 * an autoadjust mechanism to calibrate to the true oscillator rate.
 *
 * Board-specific wiring options include using split power mode with
 * RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset),
 * and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from
 * low power modes) for OMAP1 boards (OMAP-L138 has this built into
 * the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment.
 */

#define	DRIVER_NAME			"omap_rtc"

#define OMAP_RTC_BASE			0xfffb4800

/* RTC registers */
#define OMAP_RTC_SECONDS_REG		0x00
#define OMAP_RTC_MINUTES_REG		0x04
#define OMAP_RTC_HOURS_REG		0x08
#define OMAP_RTC_DAYS_REG		0x0C
#define OMAP_RTC_MONTHS_REG		0x10
#define OMAP_RTC_YEARS_REG		0x14
#define OMAP_RTC_WEEKS_REG		0x18

#define OMAP_RTC_ALARM_SECONDS_REG	0x20
#define OMAP_RTC_ALARM_MINUTES_REG	0x24
#define OMAP_RTC_ALARM_HOURS_REG	0x28
#define OMAP_RTC_ALARM_DAYS_REG		0x2c
#define OMAP_RTC_ALARM_MONTHS_REG	0x30
#define OMAP_RTC_ALARM_YEARS_REG	0x34

#define OMAP_RTC_CTRL_REG		0x40
#define OMAP_RTC_STATUS_REG		0x44
#define OMAP_RTC_INTERRUPTS_REG		0x48

#define OMAP_RTC_COMP_LSB_REG		0x4c
#define OMAP_RTC_COMP_MSB_REG		0x50
#define OMAP_RTC_OSC_REG		0x54

#define OMAP_RTC_KICK0_REG		0x6c
#define OMAP_RTC_KICK1_REG		0x70

#define OMAP_RTC_IRQWAKEEN		0x7c

/* OMAP_RTC_CTRL_REG bit fields: */
#define OMAP_RTC_CTRL_SPLIT		BIT(7)
#define OMAP_RTC_CTRL_DISABLE		BIT(6)
#define OMAP_RTC_CTRL_SET_32_COUNTER	BIT(5)
#define OMAP_RTC_CTRL_TEST		BIT(4)
#define OMAP_RTC_CTRL_MODE_12_24	BIT(3)
#define OMAP_RTC_CTRL_AUTO_COMP		BIT(2)
#define OMAP_RTC_CTRL_ROUND_30S		BIT(1)
#define OMAP_RTC_CTRL_STOP		BIT(0)

/* OMAP_RTC_STATUS_REG bit fields: */
#define OMAP_RTC_STATUS_POWER_UP	BIT(7)
#define OMAP_RTC_STATUS_ALARM		BIT(6)
#define OMAP_RTC_STATUS_1D_EVENT	BIT(5)
#define OMAP_RTC_STATUS_1H_EVENT	BIT(4)
#define OMAP_RTC_STATUS_1M_EVENT	BIT(3)
#define OMAP_RTC_STATUS_1S_EVENT	BIT(2)
#define OMAP_RTC_STATUS_RUN		BIT(1)
#define OMAP_RTC_STATUS_BUSY		BIT(0)

/* OMAP_RTC_INTERRUPTS_REG bit fields: */
#define OMAP_RTC_INTERRUPTS_IT_ALARM	BIT(3)
#define OMAP_RTC_INTERRUPTS_IT_TIMER	BIT(2)

/* OMAP_RTC_OSC_REG bit fields: */
#define OMAP_RTC_OSC_32KCLK_EN		BIT(6)

/* OMAP_RTC_IRQWAKEEN bit fields: */
#define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN	BIT(1)

/* OMAP_RTC_KICKER values */
#define	KICK0_VALUE			0x83e70b13
#define	KICK1_VALUE			0x95a4f1e0

#define	OMAP_RTC_HAS_KICKER		BIT(0)

/*
 * Few RTC IP revisions has special WAKE-EN Register to enable Wakeup
 * generation for event Alarm.
 */
#define	OMAP_RTC_HAS_IRQWAKEEN		BIT(1)

/*
 * Some RTC IP revisions (like those in AM335x and DRA7x) need
 * the 32KHz clock to be explicitly enabled.
 */
#define OMAP_RTC_HAS_32KCLK_EN		BIT(2)

static void __iomem	*rtc_base;

#define rtc_read(addr)		readb(rtc_base + (addr))
#define rtc_write(val, addr)	writeb(val, rtc_base + (addr))

#define rtc_writel(val, addr)	writel(val, rtc_base + (addr))


/* we rely on the rtc framework to handle locking (rtc->ops_lock),
 * so the only other requirement is that register accesses which
 * require BUSY to be clear are made with IRQs locally disabled
 */
static void rtc_wait_not_busy(void)
{
	int	count = 0;
	u8	status;

	/* BUSY may stay active for 1/32768 second (~30 usec) */
	for (count = 0; count < 50; count++) {
		status = rtc_read(OMAP_RTC_STATUS_REG);
		if ((status & (u8)OMAP_RTC_STATUS_BUSY) == 0)
			break;
		udelay(1);
	}
	/* now we have ~15 usec to read/write various registers */
}

static irqreturn_t rtc_irq(int irq, void *rtc)
{
	unsigned long		events = 0;
	u8			irq_data;

	irq_data = rtc_read(OMAP_RTC_STATUS_REG);

	/* alarm irq? */
	if (irq_data & OMAP_RTC_STATUS_ALARM) {
		rtc_write(OMAP_RTC_STATUS_ALARM, OMAP_RTC_STATUS_REG);
		events |= RTC_IRQF | RTC_AF;
	}

	/* 1/sec periodic/update irq? */
	if (irq_data & OMAP_RTC_STATUS_1S_EVENT)
		events |= RTC_IRQF | RTC_UF;

	rtc_update_irq(rtc, 1, events);

	return IRQ_HANDLED;
}

static int omap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	u8 reg;

	local_irq_disable();
	rtc_wait_not_busy();
	reg = rtc_read(OMAP_RTC_INTERRUPTS_REG);
	if (enabled)
		reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
	else
		reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
	rtc_wait_not_busy();
	rtc_write(reg, OMAP_RTC_INTERRUPTS_REG);
	local_irq_enable();

	return 0;
}

/* this hardware doesn't support "don't care" alarm fields */
static int tm2bcd(struct rtc_time *tm)
{
	if (rtc_valid_tm(tm) != 0)
		return -EINVAL;

	tm->tm_sec = bin2bcd(tm->tm_sec);
	tm->tm_min = bin2bcd(tm->tm_min);
	tm->tm_hour = bin2bcd(tm->tm_hour);
	tm->tm_mday = bin2bcd(tm->tm_mday);

	tm->tm_mon = bin2bcd(tm->tm_mon + 1);

	/* epoch == 1900 */
	if (tm->tm_year < 100 || tm->tm_year > 199)
		return -EINVAL;
	tm->tm_year = bin2bcd(tm->tm_year - 100);

	return 0;
}

static void bcd2tm(struct rtc_time *tm)
{
	tm->tm_sec = bcd2bin(tm->tm_sec);
	tm->tm_min = bcd2bin(tm->tm_min);
	tm->tm_hour = bcd2bin(tm->tm_hour);
	tm->tm_mday = bcd2bin(tm->tm_mday);
	tm->tm_mon = bcd2bin(tm->tm_mon) - 1;
	/* epoch == 1900 */
	tm->tm_year = bcd2bin(tm->tm_year) + 100;
}


static int omap_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	/* we don't report wday/yday/isdst ... */
	local_irq_disable();
	rtc_wait_not_busy();

	tm->tm_sec = rtc_read(OMAP_RTC_SECONDS_REG);
	tm->tm_min = rtc_read(OMAP_RTC_MINUTES_REG);
	tm->tm_hour = rtc_read(OMAP_RTC_HOURS_REG);
	tm->tm_mday = rtc_read(OMAP_RTC_DAYS_REG);
	tm->tm_mon = rtc_read(OMAP_RTC_MONTHS_REG);
	tm->tm_year = rtc_read(OMAP_RTC_YEARS_REG);

	local_irq_enable();

	bcd2tm(tm);
	return 0;
}

static int omap_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	if (tm2bcd(tm) < 0)
		return -EINVAL;
	local_irq_disable();
	rtc_wait_not_busy();

	rtc_write(tm->tm_year, OMAP_RTC_YEARS_REG);
	rtc_write(tm->tm_mon, OMAP_RTC_MONTHS_REG);
	rtc_write(tm->tm_mday, OMAP_RTC_DAYS_REG);
	rtc_write(tm->tm_hour, OMAP_RTC_HOURS_REG);
	rtc_write(tm->tm_min, OMAP_RTC_MINUTES_REG);
	rtc_write(tm->tm_sec, OMAP_RTC_SECONDS_REG);

	local_irq_enable();

	return 0;
}

static int omap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
	local_irq_disable();
	rtc_wait_not_busy();

	alm->time.tm_sec = rtc_read(OMAP_RTC_ALARM_SECONDS_REG);
	alm->time.tm_min = rtc_read(OMAP_RTC_ALARM_MINUTES_REG);
	alm->time.tm_hour = rtc_read(OMAP_RTC_ALARM_HOURS_REG);
	alm->time.tm_mday = rtc_read(OMAP_RTC_ALARM_DAYS_REG);
	alm->time.tm_mon = rtc_read(OMAP_RTC_ALARM_MONTHS_REG);
	alm->time.tm_year = rtc_read(OMAP_RTC_ALARM_YEARS_REG);

	local_irq_enable();

	bcd2tm(&alm->time);
	alm->enabled = !!(rtc_read(OMAP_RTC_INTERRUPTS_REG)
			& OMAP_RTC_INTERRUPTS_IT_ALARM);

	return 0;
}

static int omap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
	u8 reg;

	if (tm2bcd(&alm->time) < 0)
		return -EINVAL;

	local_irq_disable();
	rtc_wait_not_busy();

	rtc_write(alm->time.tm_year, OMAP_RTC_ALARM_YEARS_REG);
	rtc_write(alm->time.tm_mon, OMAP_RTC_ALARM_MONTHS_REG);
	rtc_write(alm->time.tm_mday, OMAP_RTC_ALARM_DAYS_REG);
	rtc_write(alm->time.tm_hour, OMAP_RTC_ALARM_HOURS_REG);
	rtc_write(alm->time.tm_min, OMAP_RTC_ALARM_MINUTES_REG);
	rtc_write(alm->time.tm_sec, OMAP_RTC_ALARM_SECONDS_REG);

	reg = rtc_read(OMAP_RTC_INTERRUPTS_REG);
	if (alm->enabled)
		reg |= OMAP_RTC_INTERRUPTS_IT_ALARM;
	else
		reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
	rtc_write(reg, OMAP_RTC_INTERRUPTS_REG);

	local_irq_enable();

	return 0;
}

static struct rtc_class_ops omap_rtc_ops = {
	.read_time	= omap_rtc_read_time,
	.set_time	= omap_rtc_set_time,
	.read_alarm	= omap_rtc_read_alarm,
	.set_alarm	= omap_rtc_set_alarm,
	.alarm_irq_enable = omap_rtc_alarm_irq_enable,
};

static int omap_rtc_alarm;
static int omap_rtc_timer;

#define	OMAP_RTC_DATA_AM3352_IDX	1
#define	OMAP_RTC_DATA_DA830_IDX		2

static struct platform_device_id omap_rtc_devtype[] = {
	{
		.name	= DRIVER_NAME,
	},
	[OMAP_RTC_DATA_AM3352_IDX] = {
		.name	= "am3352-rtc",
		.driver_data = OMAP_RTC_HAS_KICKER | OMAP_RTC_HAS_IRQWAKEEN |
			       OMAP_RTC_HAS_32KCLK_EN,
	},
	[OMAP_RTC_DATA_DA830_IDX] = {
		.name	= "da830-rtc",
		.driver_data = OMAP_RTC_HAS_KICKER,
	},
	{},
};
MODULE_DEVICE_TABLE(platform, omap_rtc_devtype);

static const struct of_device_id omap_rtc_of_match[] = {
	{	.compatible	= "ti,da830-rtc",
		.data		= &omap_rtc_devtype[OMAP_RTC_DATA_DA830_IDX],
	},
	{	.compatible	= "ti,am3352-rtc",
		.data		= &omap_rtc_devtype[OMAP_RTC_DATA_AM3352_IDX],
	},
	{},
};
MODULE_DEVICE_TABLE(of, omap_rtc_of_match);

static int __init omap_rtc_probe(struct platform_device *pdev)
{
	struct resource		*res;
	struct rtc_device	*rtc;
	u8			reg, new_ctrl;
	const struct platform_device_id *id_entry;
	const struct of_device_id *of_id;

	of_id = of_match_device(omap_rtc_of_match, &pdev->dev);
	if (of_id)
		pdev->id_entry = of_id->data;

	id_entry = platform_get_device_id(pdev);
	if (!id_entry) {
		dev_err(&pdev->dev, "no matching device entry\n");
		return -ENODEV;
	}

	omap_rtc_timer = platform_get_irq(pdev, 0);
	if (omap_rtc_timer <= 0) {
		pr_debug("%s: no update irq?\n", pdev->name);
		return -ENOENT;
	}

	omap_rtc_alarm = platform_get_irq(pdev, 1);
	if (omap_rtc_alarm <= 0) {
		pr_debug("%s: no alarm irq?\n", pdev->name);
		return -ENOENT;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	rtc_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(rtc_base))
		return PTR_ERR(rtc_base);

	/* Enable the clock/module so that we can access the registers */
	pm_runtime_enable(&pdev->dev);
	pm_runtime_get_sync(&pdev->dev);

	if (id_entry->driver_data & OMAP_RTC_HAS_KICKER) {
		rtc_writel(KICK0_VALUE, OMAP_RTC_KICK0_REG);
		rtc_writel(KICK1_VALUE, OMAP_RTC_KICK1_REG);
	}

	rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
			&omap_rtc_ops, THIS_MODULE);
	if (IS_ERR(rtc)) {
		pr_debug("%s: can't register RTC device, err %ld\n",
			pdev->name, PTR_ERR(rtc));
		goto fail0;
	}
	platform_set_drvdata(pdev, rtc);

	/* clear pending irqs, and set 1/second periodic,
	 * which we'll use instead of update irqs
	 */
	rtc_write(0, OMAP_RTC_INTERRUPTS_REG);

	/* enable RTC functional clock */
	if (id_entry->driver_data & OMAP_RTC_HAS_32KCLK_EN)
		rtc_writel(OMAP_RTC_OSC_32KCLK_EN, OMAP_RTC_OSC_REG);

	/* clear old status */
	reg = rtc_read(OMAP_RTC_STATUS_REG);
	if (reg & (u8) OMAP_RTC_STATUS_POWER_UP) {
		pr_info("%s: RTC power up reset detected\n",
			pdev->name);
		rtc_write(OMAP_RTC_STATUS_POWER_UP, OMAP_RTC_STATUS_REG);
	}
	if (reg & (u8) OMAP_RTC_STATUS_ALARM)
		rtc_write(OMAP_RTC_STATUS_ALARM, OMAP_RTC_STATUS_REG);

	/* handle periodic and alarm irqs */
	if (devm_request_irq(&pdev->dev, omap_rtc_timer, rtc_irq, 0,
			dev_name(&rtc->dev), rtc)) {
		pr_debug("%s: RTC timer interrupt IRQ%d already claimed\n",
			pdev->name, omap_rtc_timer);
		goto fail0;
	}
	if ((omap_rtc_timer != omap_rtc_alarm) &&
		(devm_request_irq(&pdev->dev, omap_rtc_alarm, rtc_irq, 0,
			dev_name(&rtc->dev), rtc))) {
		pr_debug("%s: RTC alarm interrupt IRQ%d already claimed\n",
			pdev->name, omap_rtc_alarm);
		goto fail0;
	}

	/* On boards with split power, RTC_ON_NOFF won't reset the RTC */
	reg = rtc_read(OMAP_RTC_CTRL_REG);
	if (reg & (u8) OMAP_RTC_CTRL_STOP)
		pr_info("%s: already running\n", pdev->name);

	/* force to 24 hour mode */
	new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT|OMAP_RTC_CTRL_AUTO_COMP);
	new_ctrl |= OMAP_RTC_CTRL_STOP;

	/* BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE:
	 *
	 *  - Device wake-up capability setting should come through chip
	 *    init logic. OMAP1 boards should initialize the "wakeup capable"
	 *    flag in the platform device if the board is wired right for
	 *    being woken up by RTC alarm. For OMAP-L138, this capability
	 *    is built into the SoC by the "Deep Sleep" capability.
	 *
	 *  - Boards wired so RTC_ON_nOFF is used as the reset signal,
	 *    rather than nPWRON_RESET, should forcibly enable split
	 *    power mode.  (Some chip errata report that RTC_CTRL_SPLIT
	 *    is write-only, and always reads as zero...)
	 */

	device_init_wakeup(&pdev->dev, true);

	if (new_ctrl & (u8) OMAP_RTC_CTRL_SPLIT)
		pr_info("%s: split power mode\n", pdev->name);

	if (reg != new_ctrl)
		rtc_write(new_ctrl, OMAP_RTC_CTRL_REG);

	return 0;

fail0:
	if (id_entry->driver_data & OMAP_RTC_HAS_KICKER)
		rtc_writel(0, OMAP_RTC_KICK0_REG);
	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
	return -EIO;
}

static int __exit omap_rtc_remove(struct platform_device *pdev)
{
	const struct platform_device_id *id_entry =
				platform_get_device_id(pdev);

	device_init_wakeup(&pdev->dev, 0);

	/* leave rtc running, but disable irqs */
	rtc_write(0, OMAP_RTC_INTERRUPTS_REG);

	if (id_entry->driver_data & OMAP_RTC_HAS_KICKER)
		rtc_writel(0, OMAP_RTC_KICK0_REG);

	/* Disable the clock/module */
	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static u8 irqstat;

static int omap_rtc_suspend(struct device *dev)
{
	u8 irqwake_stat;
	struct platform_device *pdev = to_platform_device(dev);
	const struct platform_device_id *id_entry =
					platform_get_device_id(pdev);

	irqstat = rtc_read(OMAP_RTC_INTERRUPTS_REG);

	/* FIXME the RTC alarm is not currently acting as a wakeup event
	 * source on some platforms, and in fact this enable() call is just
	 * saving a flag that's never used...
	 */
	if (device_may_wakeup(dev)) {
		enable_irq_wake(omap_rtc_alarm);

		if (id_entry->driver_data & OMAP_RTC_HAS_IRQWAKEEN) {
			irqwake_stat = rtc_read(OMAP_RTC_IRQWAKEEN);
			irqwake_stat |= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
			rtc_write(irqwake_stat, OMAP_RTC_IRQWAKEEN);
		}
	} else {
		rtc_write(0, OMAP_RTC_INTERRUPTS_REG);
	}

	/* Disable the clock/module */
	pm_runtime_put_sync(dev);

	return 0;
}

static int omap_rtc_resume(struct device *dev)
{
	u8 irqwake_stat;
	struct platform_device *pdev = to_platform_device(dev);
	const struct platform_device_id *id_entry =
				platform_get_device_id(pdev);

	/* Enable the clock/module so that we can access the registers */
	pm_runtime_get_sync(dev);

	if (device_may_wakeup(dev)) {
		disable_irq_wake(omap_rtc_alarm);

		if (id_entry->driver_data & OMAP_RTC_HAS_IRQWAKEEN) {
			irqwake_stat = rtc_read(OMAP_RTC_IRQWAKEEN);
			irqwake_stat &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
			rtc_write(irqwake_stat, OMAP_RTC_IRQWAKEEN);
		}
	} else {
		rtc_write(irqstat, OMAP_RTC_INTERRUPTS_REG);
	}
	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(omap_rtc_pm_ops, omap_rtc_suspend, omap_rtc_resume);

static void omap_rtc_shutdown(struct platform_device *pdev)
{
	rtc_write(0, OMAP_RTC_INTERRUPTS_REG);
}

MODULE_ALIAS("platform:omap_rtc");
static struct platform_driver omap_rtc_driver = {
	.remove		= __exit_p(omap_rtc_remove),
	.shutdown	= omap_rtc_shutdown,
	.driver		= {
		.name	= DRIVER_NAME,
		.owner	= THIS_MODULE,
		.pm	= &omap_rtc_pm_ops,
		.of_match_table = omap_rtc_of_match,
	},
	.id_table	= omap_rtc_devtype,
};

module_platform_driver_probe(omap_rtc_driver, omap_rtc_probe);

MODULE_AUTHOR("George G. Davis (and others)");
MODULE_LICENSE("GPL");
Commit	Line	Data
db68b189 DB	1	/*
	2	* TI OMAP1 Real Time Clock interface for Linux
	3	*
	4	* Copyright (C) 2003 MontaVista Software, Inc.
	5	* Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
	6	*
	7	* Copyright (C) 2006 David Brownell (new RTC framework)
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; either version
	12	* 2 of the License, or (at your option) any later version.
	13	*/
	14
	15	#include <linux/kernel.h>
	16	#include <linux/init.h>
	17	#include <linux/module.h>
	18	#include <linux/ioport.h>
	19	#include <linux/delay.h>
	20	#include <linux/rtc.h>
	21	#include <linux/bcd.h>
	22	#include <linux/platform_device.h>
9e0344dc AM	23	#include <linux/of.h>
9e0344dc AM	24	#include <linux/of_device.h>
fc9bd902	25	#include <linux/pm_runtime.h>
4b30c9fc	26	#include <linux/io.h>
db68b189 DB	27
	28	/* The OMAP1 RTC is a year/month/day/hours/minutes/seconds BCD clock
	29	* with century-range alarm matching, driven by the 32kHz clock.
	30	*
	31	* The main user-visible ways it differs from PC RTCs are by omitting
	32	* "don't care" alarm fields and sub-second periodic IRQs, and having
	33	* an autoadjust mechanism to calibrate to the true oscillator rate.
	34	*
	35	* Board-specific wiring options include using split power mode with
	36	* RTC_OFF_NOFF used as the reset signal (so the RTC won't be reset),
	37	* and wiring RTC_WAKE_INT (so the RTC alarm can wake the system from
fa5b0782 SN	38	* low power modes) for OMAP1 boards (OMAP-L138 has this built into
fa5b0782 SN	39	* the SoC). See the BOARD-SPECIFIC CUSTOMIZATION comment.
db68b189 DB	40	*/
db68b189 DB	41
cab1458c AM	42	#define DRIVER_NAME "omap_rtc"
cab1458c AM	43
db68b189 DB	44	#define OMAP_RTC_BASE 0xfffb4800
	45
	46	/* RTC registers */
	47	#define OMAP_RTC_SECONDS_REG 0x00
	48	#define OMAP_RTC_MINUTES_REG 0x04
	49	#define OMAP_RTC_HOURS_REG 0x08
	50	#define OMAP_RTC_DAYS_REG 0x0C
	51	#define OMAP_RTC_MONTHS_REG 0x10
	52	#define OMAP_RTC_YEARS_REG 0x14
	53	#define OMAP_RTC_WEEKS_REG 0x18
	54
	55	#define OMAP_RTC_ALARM_SECONDS_REG 0x20
	56	#define OMAP_RTC_ALARM_MINUTES_REG 0x24
	57	#define OMAP_RTC_ALARM_HOURS_REG 0x28
	58	#define OMAP_RTC_ALARM_DAYS_REG 0x2c
	59	#define OMAP_RTC_ALARM_MONTHS_REG 0x30
	60	#define OMAP_RTC_ALARM_YEARS_REG 0x34
	61
	62	#define OMAP_RTC_CTRL_REG 0x40
	63	#define OMAP_RTC_STATUS_REG 0x44
	64	#define OMAP_RTC_INTERRUPTS_REG 0x48
	65
	66	#define OMAP_RTC_COMP_LSB_REG 0x4c
	67	#define OMAP_RTC_COMP_MSB_REG 0x50
	68	#define OMAP_RTC_OSC_REG 0x54
	69
cab1458c AM	70	#define OMAP_RTC_KICK0_REG 0x6c
	71	#define OMAP_RTC_KICK1_REG 0x70
	72
8af750e3 HG	73	#define OMAP_RTC_IRQWAKEEN 0x7c
8af750e3 HG	74
db68b189	75	/* OMAP_RTC_CTRL_REG bit fields: */
92adb96a SN	76	#define OMAP_RTC_CTRL_SPLIT BIT(7)
	77	#define OMAP_RTC_CTRL_DISABLE BIT(6)
	78	#define OMAP_RTC_CTRL_SET_32_COUNTER BIT(5)
	79	#define OMAP_RTC_CTRL_TEST BIT(4)
	80	#define OMAP_RTC_CTRL_MODE_12_24 BIT(3)
	81	#define OMAP_RTC_CTRL_AUTO_COMP BIT(2)
	82	#define OMAP_RTC_CTRL_ROUND_30S BIT(1)
	83	#define OMAP_RTC_CTRL_STOP BIT(0)
db68b189 DB	84
db68b189 DB	85	/* OMAP_RTC_STATUS_REG bit fields: */
92adb96a SN	86	#define OMAP_RTC_STATUS_POWER_UP BIT(7)
	87	#define OMAP_RTC_STATUS_ALARM BIT(6)
	88	#define OMAP_RTC_STATUS_1D_EVENT BIT(5)
	89	#define OMAP_RTC_STATUS_1H_EVENT BIT(4)
	90	#define OMAP_RTC_STATUS_1M_EVENT BIT(3)
	91	#define OMAP_RTC_STATUS_1S_EVENT BIT(2)
	92	#define OMAP_RTC_STATUS_RUN BIT(1)
	93	#define OMAP_RTC_STATUS_BUSY BIT(0)
db68b189 DB	94
db68b189 DB	95	/* OMAP_RTC_INTERRUPTS_REG bit fields: */
92adb96a SN	96	#define OMAP_RTC_INTERRUPTS_IT_ALARM BIT(3)
92adb96a SN	97	#define OMAP_RTC_INTERRUPTS_IT_TIMER BIT(2)
db68b189	98
cd914bba SN	99	/* OMAP_RTC_OSC_REG bit fields: */
	100	#define OMAP_RTC_OSC_32KCLK_EN BIT(6)
	101
8af750e3	102	/* OMAP_RTC_IRQWAKEEN bit fields: */
92adb96a	103	#define OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN BIT(1)
8af750e3	104
cab1458c AM	105	/* OMAP_RTC_KICKER values */
	106	#define KICK0_VALUE 0x83e70b13
	107	#define KICK1_VALUE 0x95a4f1e0
	108
92adb96a	109	#define OMAP_RTC_HAS_KICKER BIT(0)
cab1458c	110
8af750e3 HG	111	/*
	112	* Few RTC IP revisions has special WAKE-EN Register to enable Wakeup
	113	* generation for event Alarm.
	114	*/
92adb96a	115	#define OMAP_RTC_HAS_IRQWAKEEN BIT(1)
8af750e3	116
cd914bba SN	117	/*
	118	* Some RTC IP revisions (like those in AM335x and DRA7x) need
	119	* the 32KHz clock to be explicitly enabled.
	120	*/
	121	#define OMAP_RTC_HAS_32KCLK_EN BIT(2)
	122
8cfde8c1	123	static void __iomem *rtc_base;
db68b189	124
cab1458c AM	125	#define rtc_read(addr) readb(rtc_base + (addr))
	126	#define rtc_write(val, addr) writeb(val, rtc_base + (addr))
	127
	128	#define rtc_writel(val, addr) writel(val, rtc_base + (addr))
db68b189 DB	129
db68b189 DB	130
db68b189 DB	131	/* we rely on the rtc framework to handle locking (rtc->ops_lock),
	132	* so the only other requirement is that register accesses which
	133	* require BUSY to be clear are made with IRQs locally disabled
	134	*/
	135	static void rtc_wait_not_busy(void)
	136	{
	137	int count = 0;
	138	u8 status;
	139
	140	/* BUSY may stay active for 1/32768 second (~30 usec) */
	141	for (count = 0; count < 50; count++) {
	142	status = rtc_read(OMAP_RTC_STATUS_REG);
	143	if ((status & (u8)OMAP_RTC_STATUS_BUSY) == 0)
	144	break;
	145	udelay(1);
	146	}
	147	/* now we have ~15 usec to read/write various registers */
	148	}
	149
ab6a2d70	150	static irqreturn_t rtc_irq(int irq, void *rtc)
db68b189 DB	151	{
	152	unsigned long events = 0;
	153	u8 irq_data;
	154
	155	irq_data = rtc_read(OMAP_RTC_STATUS_REG);
	156
	157	/* alarm irq? */
	158	if (irq_data & OMAP_RTC_STATUS_ALARM) {
	159	rtc_write(OMAP_RTC_STATUS_ALARM, OMAP_RTC_STATUS_REG);
	160	events \|= RTC_IRQF \| RTC_AF;
	161	}
	162
	163	/* 1/sec periodic/update irq? */
	164	if (irq_data & OMAP_RTC_STATUS_1S_EVENT)
	165	events \|= RTC_IRQF \| RTC_UF;
	166
ab6a2d70	167	rtc_update_irq(rtc, 1, events);
db68b189 DB	168
	169	return IRQ_HANDLED;
	170	}
	171
16380c15 JS	172	static int omap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
	173	{
	174	u8 reg;
	175
	176	local_irq_disable();
	177	rtc_wait_not_busy();
	178	reg = rtc_read(OMAP_RTC_INTERRUPTS_REG);
	179	if (enabled)
	180	reg \|= OMAP_RTC_INTERRUPTS_IT_ALARM;
	181	else
	182	reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
	183	rtc_wait_not_busy();
	184	rtc_write(reg, OMAP_RTC_INTERRUPTS_REG);
	185	local_irq_enable();
	186
	187	return 0;
	188	}
	189
db68b189 DB	190	/* this hardware doesn't support "don't care" alarm fields */
	191	static int tm2bcd(struct rtc_time *tm)
	192	{
	193	if (rtc_valid_tm(tm) != 0)
	194	return -EINVAL;
	195
fe20ba70 AB	196	tm->tm_sec = bin2bcd(tm->tm_sec);
	197	tm->tm_min = bin2bcd(tm->tm_min);
	198	tm->tm_hour = bin2bcd(tm->tm_hour);
	199	tm->tm_mday = bin2bcd(tm->tm_mday);
db68b189	200
fe20ba70	201	tm->tm_mon = bin2bcd(tm->tm_mon + 1);
db68b189 DB	202
	203	/* epoch == 1900 */
	204	if (tm->tm_year < 100 \|\| tm->tm_year > 199)
	205	return -EINVAL;
fe20ba70	206	tm->tm_year = bin2bcd(tm->tm_year - 100);
db68b189 DB	207
	208	return 0;
	209	}
	210
	211	static void bcd2tm(struct rtc_time *tm)
	212	{
fe20ba70 AB	213	tm->tm_sec = bcd2bin(tm->tm_sec);
	214	tm->tm_min = bcd2bin(tm->tm_min);
	215	tm->tm_hour = bcd2bin(tm->tm_hour);
	216	tm->tm_mday = bcd2bin(tm->tm_mday);
	217	tm->tm_mon = bcd2bin(tm->tm_mon) - 1;
db68b189	218	/* epoch == 1900 */
fe20ba70	219	tm->tm_year = bcd2bin(tm->tm_year) + 100;
db68b189 DB	220	}
	221
	222
	223	static int omap_rtc_read_time(struct device dev, struct rtc_time tm)
	224	{
	225	/* we don't report wday/yday/isdst ... */
	226	local_irq_disable();
	227	rtc_wait_not_busy();
	228
	229	tm->tm_sec = rtc_read(OMAP_RTC_SECONDS_REG);
	230	tm->tm_min = rtc_read(OMAP_RTC_MINUTES_REG);
	231	tm->tm_hour = rtc_read(OMAP_RTC_HOURS_REG);
	232	tm->tm_mday = rtc_read(OMAP_RTC_DAYS_REG);
	233	tm->tm_mon = rtc_read(OMAP_RTC_MONTHS_REG);
	234	tm->tm_year = rtc_read(OMAP_RTC_YEARS_REG);
	235
	236	local_irq_enable();
	237
	238	bcd2tm(tm);
	239	return 0;
	240	}
	241
	242	static int omap_rtc_set_time(struct device dev, struct rtc_time tm)
	243	{
	244	if (tm2bcd(tm) < 0)
	245	return -EINVAL;
	246	local_irq_disable();
	247	rtc_wait_not_busy();
	248
	249	rtc_write(tm->tm_year, OMAP_RTC_YEARS_REG);
	250	rtc_write(tm->tm_mon, OMAP_RTC_MONTHS_REG);
	251	rtc_write(tm->tm_mday, OMAP_RTC_DAYS_REG);
	252	rtc_write(tm->tm_hour, OMAP_RTC_HOURS_REG);
	253	rtc_write(tm->tm_min, OMAP_RTC_MINUTES_REG);
	254	rtc_write(tm->tm_sec, OMAP_RTC_SECONDS_REG);
	255
	256	local_irq_enable();
	257
	258	return 0;
	259	}
	260
	261	static int omap_rtc_read_alarm(struct device dev, struct rtc_wkalrm alm)
	262	{
	263	local_irq_disable();
	264	rtc_wait_not_busy();
	265
	266	alm->time.tm_sec = rtc_read(OMAP_RTC_ALARM_SECONDS_REG);
	267	alm->time.tm_min = rtc_read(OMAP_RTC_ALARM_MINUTES_REG);
	268	alm->time.tm_hour = rtc_read(OMAP_RTC_ALARM_HOURS_REG);
	269	alm->time.tm_mday = rtc_read(OMAP_RTC_ALARM_DAYS_REG);
	270	alm->time.tm_mon = rtc_read(OMAP_RTC_ALARM_MONTHS_REG);
	271	alm->time.tm_year = rtc_read(OMAP_RTC_ALARM_YEARS_REG);
	272
	273	local_irq_enable();
	274
	275	bcd2tm(&alm->time);
a2db8dfc	276	alm->enabled = !!(rtc_read(OMAP_RTC_INTERRUPTS_REG)
db68b189	277	& OMAP_RTC_INTERRUPTS_IT_ALARM);
db68b189 DB	278
	279	return 0;
	280	}
	281
	282	static int omap_rtc_set_alarm(struct device dev, struct rtc_wkalrm alm)
	283	{
	284	u8 reg;
	285
db68b189 DB	286	if (tm2bcd(&alm->time) < 0)
	287	return -EINVAL;
	288
	289	local_irq_disable();
	290	rtc_wait_not_busy();
	291
	292	rtc_write(alm->time.tm_year, OMAP_RTC_ALARM_YEARS_REG);
	293	rtc_write(alm->time.tm_mon, OMAP_RTC_ALARM_MONTHS_REG);
	294	rtc_write(alm->time.tm_mday, OMAP_RTC_ALARM_DAYS_REG);
	295	rtc_write(alm->time.tm_hour, OMAP_RTC_ALARM_HOURS_REG);
	296	rtc_write(alm->time.tm_min, OMAP_RTC_ALARM_MINUTES_REG);
	297	rtc_write(alm->time.tm_sec, OMAP_RTC_ALARM_SECONDS_REG);
	298
	299	reg = rtc_read(OMAP_RTC_INTERRUPTS_REG);
	300	if (alm->enabled)
	301	reg \|= OMAP_RTC_INTERRUPTS_IT_ALARM;
	302	else
	303	reg &= ~OMAP_RTC_INTERRUPTS_IT_ALARM;
	304	rtc_write(reg, OMAP_RTC_INTERRUPTS_REG);
	305
	306	local_irq_enable();
	307
	308	return 0;
	309	}
	310
	311	static struct rtc_class_ops omap_rtc_ops = {
db68b189 DB	312	.read_time = omap_rtc_read_time,
	313	.set_time = omap_rtc_set_time,
	314	.read_alarm = omap_rtc_read_alarm,
	315	.set_alarm = omap_rtc_set_alarm,
16380c15	316	.alarm_irq_enable = omap_rtc_alarm_irq_enable,
db68b189 DB	317	};
	318
	319	static int omap_rtc_alarm;
	320	static int omap_rtc_timer;
	321
8af750e3 HG	322	#define OMAP_RTC_DATA_AM3352_IDX 1
8af750e3 HG	323	#define OMAP_RTC_DATA_DA830_IDX 2
9e0344dc	324
cab1458c AM	325	static struct platform_device_id omap_rtc_devtype[] = {
	326	{
	327	.name = DRIVER_NAME,
8af750e3 HG	328	},
	329	[OMAP_RTC_DATA_AM3352_IDX] = {
	330	.name = "am3352-rtc",
cd914bba SN	331	.driver_data = OMAP_RTC_HAS_KICKER \| OMAP_RTC_HAS_IRQWAKEEN \|
cd914bba SN	332	OMAP_RTC_HAS_32KCLK_EN,
8af750e3 HG	333	},
8af750e3 HG	334	[OMAP_RTC_DATA_DA830_IDX] = {
cab1458c AM	335	.name = "da830-rtc",
	336	.driver_data = OMAP_RTC_HAS_KICKER,
	337	},
	338	{},
	339	};
	340	MODULE_DEVICE_TABLE(platform, omap_rtc_devtype);
	341
9e0344dc AM	342	static const struct of_device_id omap_rtc_of_match[] = {
	343	{ .compatible = "ti,da830-rtc",
	344	.data = &omap_rtc_devtype[OMAP_RTC_DATA_DA830_IDX],
	345	},
8af750e3 HG	346	{ .compatible = "ti,am3352-rtc",
	347	.data = &omap_rtc_devtype[OMAP_RTC_DATA_AM3352_IDX],
	348	},
9e0344dc AM	349	{},
	350	};
	351	MODULE_DEVICE_TABLE(of, omap_rtc_of_match);
	352
71fc8224	353	static int __init omap_rtc_probe(struct platform_device *pdev)
db68b189	354	{
3765e8f1	355	struct resource *res;
db68b189 DB	356	struct rtc_device *rtc;
db68b189 DB	357	u8 reg, new_ctrl;
cab1458c	358	const struct platform_device_id *id_entry;
9e0344dc AM	359	const struct of_device_id *of_id;
	360
	361	of_id = of_match_device(omap_rtc_of_match, &pdev->dev);
	362	if (of_id)
	363	pdev->id_entry = of_id->data;
db68b189	364
337b600f SN	365	id_entry = platform_get_device_id(pdev);
	366	if (!id_entry) {
	367	dev_err(&pdev->dev, "no matching device entry\n");
	368	return -ENODEV;
	369	}
	370
db68b189 DB	371	omap_rtc_timer = platform_get_irq(pdev, 0);
	372	if (omap_rtc_timer <= 0) {
	373	pr_debug("%s: no update irq?\n", pdev->name);
	374	return -ENOENT;
	375	}
	376
	377	omap_rtc_alarm = platform_get_irq(pdev, 1);
	378	if (omap_rtc_alarm <= 0) {
	379	pr_debug("%s: no alarm irq?\n", pdev->name);
	380	return -ENOENT;
	381	}
	382
db68b189	383	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3765e8f1 VBM	384	rtc_base = devm_ioremap_resource(&pdev->dev, res);
	385	if (IS_ERR(rtc_base))
	386	return PTR_ERR(rtc_base);
8cfde8c1	387
fc9bd902 VH	388	/* Enable the clock/module so that we can access the registers */
	389	pm_runtime_enable(&pdev->dev);
	390	pm_runtime_get_sync(&pdev->dev);
	391
337b600f	392	if (id_entry->driver_data & OMAP_RTC_HAS_KICKER) {
cab1458c AM	393	rtc_writel(KICK0_VALUE, OMAP_RTC_KICK0_REG);
	394	rtc_writel(KICK1_VALUE, OMAP_RTC_KICK1_REG);
	395	}
	396
3765e8f1	397	rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
db68b189 DB	398	&omap_rtc_ops, THIS_MODULE);
	399	if (IS_ERR(rtc)) {
	400	pr_debug("%s: can't register RTC device, err %ld\n",
	401	pdev->name, PTR_ERR(rtc));
8cfde8c1	402	goto fail0;
db68b189 DB	403	}
db68b189 DB	404	platform_set_drvdata(pdev, rtc);
db68b189 DB	405
	406	/* clear pending irqs, and set 1/second periodic,
	407	* which we'll use instead of update irqs
	408	*/
	409	rtc_write(0, OMAP_RTC_INTERRUPTS_REG);
	410
cd914bba SN	411	/* enable RTC functional clock */
	412	if (id_entry->driver_data & OMAP_RTC_HAS_32KCLK_EN)
	413	rtc_writel(OMAP_RTC_OSC_32KCLK_EN, OMAP_RTC_OSC_REG);
	414
db68b189 DB	415	/* clear old status */
	416	reg = rtc_read(OMAP_RTC_STATUS_REG);
	417	if (reg & (u8) OMAP_RTC_STATUS_POWER_UP) {
	418	pr_info("%s: RTC power up reset detected\n",
	419	pdev->name);
	420	rtc_write(OMAP_RTC_STATUS_POWER_UP, OMAP_RTC_STATUS_REG);
	421	}
	422	if (reg & (u8) OMAP_RTC_STATUS_ALARM)
	423	rtc_write(OMAP_RTC_STATUS_ALARM, OMAP_RTC_STATUS_REG);
	424
	425	/* handle periodic and alarm irqs */
3765e8f1	426	if (devm_request_irq(&pdev->dev, omap_rtc_timer, rtc_irq, 0,
744bcb13	427	dev_name(&rtc->dev), rtc)) {
db68b189 DB	428	pr_debug("%s: RTC timer interrupt IRQ%d already claimed\n",
db68b189 DB	429	pdev->name, omap_rtc_timer);
3765e8f1	430	goto fail0;
db68b189	431	}
8cfde8c1	432	if ((omap_rtc_timer != omap_rtc_alarm) &&
3765e8f1	433	(devm_request_irq(&pdev->dev, omap_rtc_alarm, rtc_irq, 0,
8cfde8c1	434	dev_name(&rtc->dev), rtc))) {
db68b189 DB	435	pr_debug("%s: RTC alarm interrupt IRQ%d already claimed\n",
db68b189 DB	436	pdev->name, omap_rtc_alarm);
3765e8f1	437	goto fail0;
db68b189 DB	438	}
	439
	440	/* On boards with split power, RTC_ON_NOFF won't reset the RTC */
	441	reg = rtc_read(OMAP_RTC_CTRL_REG);
	442	if (reg & (u8) OMAP_RTC_CTRL_STOP)
	443	pr_info("%s: already running\n", pdev->name);
	444
	445	/* force to 24 hour mode */
12b3e038	446	new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT\|OMAP_RTC_CTRL_AUTO_COMP);
db68b189 DB	447	new_ctrl \|= OMAP_RTC_CTRL_STOP;
	448
	449	/* BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE:
	450	*
fa5b0782 SN	451	* - Device wake-up capability setting should come through chip
	452	* init logic. OMAP1 boards should initialize the "wakeup capable"
	453	* flag in the platform device if the board is wired right for
	454	* being woken up by RTC alarm. For OMAP-L138, this capability
	455	* is built into the SoC by the "Deep Sleep" capability.
db68b189 DB	456	*
	457	* - Boards wired so RTC_ON_nOFF is used as the reset signal,
	458	* rather than nPWRON_RESET, should forcibly enable split
	459	* power mode. (Some chip errata report that RTC_CTRL_SPLIT
	460	* is write-only, and always reads as zero...)
	461	*/
db68b189	462
1d2e2b65 HG	463	device_init_wakeup(&pdev->dev, true);
1d2e2b65 HG	464
db68b189 DB	465	if (new_ctrl & (u8) OMAP_RTC_CTRL_SPLIT)
	466	pr_info("%s: split power mode\n", pdev->name);
	467
	468	if (reg != new_ctrl)
	469	rtc_write(new_ctrl, OMAP_RTC_CTRL_REG);
	470
	471	return 0;
	472
8cfde8c1	473	fail0:
337b600f	474	if (id_entry->driver_data & OMAP_RTC_HAS_KICKER)
cab1458c	475	rtc_writel(0, OMAP_RTC_KICK0_REG);
fc9bd902 VH	476	pm_runtime_put_sync(&pdev->dev);
fc9bd902 VH	477	pm_runtime_disable(&pdev->dev);
db68b189 DB	478	return -EIO;
	479	}
	480
71fc8224	481	static int __exit omap_rtc_remove(struct platform_device *pdev)
db68b189	482	{
cab1458c AM	483	const struct platform_device_id *id_entry =
cab1458c AM	484	platform_get_device_id(pdev);
db68b189 DB	485
	486	device_init_wakeup(&pdev->dev, 0);
	487
	488	/* leave rtc running, but disable irqs */
	489	rtc_write(0, OMAP_RTC_INTERRUPTS_REG);
	490
337b600f	491	if (id_entry->driver_data & OMAP_RTC_HAS_KICKER)
cab1458c	492	rtc_writel(0, OMAP_RTC_KICK0_REG);
fc9bd902 VH	493
	494	/* Disable the clock/module */
	495	pm_runtime_put_sync(&pdev->dev);
	496	pm_runtime_disable(&pdev->dev);
	497
db68b189 DB	498	return 0;
	499	}
	500
04ebc359	501	#ifdef CONFIG_PM_SLEEP
db68b189 DB	502	static u8 irqstat;
db68b189 DB	503
04ebc359	504	static int omap_rtc_suspend(struct device *dev)
db68b189	505	{
8af750e3 HG	506	u8 irqwake_stat;
	507	struct platform_device *pdev = to_platform_device(dev);
	508	const struct platform_device_id *id_entry =
	509	platform_get_device_id(pdev);
	510
db68b189 DB	511	irqstat = rtc_read(OMAP_RTC_INTERRUPTS_REG);
	512
	513	/* FIXME the RTC alarm is not currently acting as a wakeup event
8af750e3 HG	514	* source on some platforms, and in fact this enable() call is just
8af750e3 HG	515	* saving a flag that's never used...
db68b189	516	*/
8af750e3	517	if (device_may_wakeup(dev)) {
db68b189	518	enable_irq_wake(omap_rtc_alarm);
8af750e3 HG	519
	520	if (id_entry->driver_data & OMAP_RTC_HAS_IRQWAKEEN) {
	521	irqwake_stat = rtc_read(OMAP_RTC_IRQWAKEEN);
	522	irqwake_stat \|= OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
	523	rtc_write(irqwake_stat, OMAP_RTC_IRQWAKEEN);
	524	}
	525	} else {
db68b189	526	rtc_write(0, OMAP_RTC_INTERRUPTS_REG);
8af750e3	527	}
db68b189	528
fc9bd902	529	/* Disable the clock/module */
04ebc359	530	pm_runtime_put_sync(dev);
fc9bd902	531
db68b189 DB	532	return 0;
	533	}
	534
04ebc359	535	static int omap_rtc_resume(struct device *dev)
db68b189	536	{
8af750e3 HG	537	u8 irqwake_stat;
	538	struct platform_device *pdev = to_platform_device(dev);
	539	const struct platform_device_id *id_entry =
	540	platform_get_device_id(pdev);
	541
fc9bd902	542	/* Enable the clock/module so that we can access the registers */
04ebc359	543	pm_runtime_get_sync(dev);
fc9bd902	544
8af750e3	545	if (device_may_wakeup(dev)) {
db68b189	546	disable_irq_wake(omap_rtc_alarm);
8af750e3 HG	547
	548	if (id_entry->driver_data & OMAP_RTC_HAS_IRQWAKEEN) {
	549	irqwake_stat = rtc_read(OMAP_RTC_IRQWAKEEN);
	550	irqwake_stat &= ~OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN;
	551	rtc_write(irqwake_stat, OMAP_RTC_IRQWAKEEN);
	552	}
	553	} else {
db68b189	554	rtc_write(irqstat, OMAP_RTC_INTERRUPTS_REG);
8af750e3	555	}
db68b189 DB	556	return 0;
db68b189 DB	557	}
db68b189 DB	558	#endif
db68b189 DB	559
04ebc359 JH	560	static SIMPLE_DEV_PM_OPS(omap_rtc_pm_ops, omap_rtc_suspend, omap_rtc_resume);
04ebc359 JH	561
db68b189 DB	562	static void omap_rtc_shutdown(struct platform_device *pdev)
	563	{
	564	rtc_write(0, OMAP_RTC_INTERRUPTS_REG);
	565	}
	566
ad28a07b	567	MODULE_ALIAS("platform:omap_rtc");
db68b189	568	static struct platform_driver omap_rtc_driver = {
71fc8224	569	.remove = __exit_p(omap_rtc_remove),
db68b189 DB	570	.shutdown = omap_rtc_shutdown,
db68b189 DB	571	.driver = {
cab1458c	572	.name = DRIVER_NAME,
db68b189	573	.owner = THIS_MODULE,
04ebc359	574	.pm = &omap_rtc_pm_ops,
616b7341	575	.of_match_table = omap_rtc_of_match,
db68b189	576	},
cab1458c	577	.id_table = omap_rtc_devtype,
db68b189 DB	578	};
db68b189 DB	579
09c5a36b	580	module_platform_driver_probe(omap_rtc_driver, omap_rtc_probe);
db68b189 DB	581
	582	MODULE_AUTHOR("George G. Davis (and others)");
	583	MODULE_LICENSE("GPL");