Commit | Line | Data |
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9a9a54ad AG |
1 | /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. |
2 | * | |
3 | * This program is free software; you can redistribute it and/or modify | |
4 | * it under the terms of the GNU General Public License version 2 and | |
5 | * only version 2 as published by the Free Software Foundation. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | */ | |
5a418558 | 12 | #include <linux/of.h> |
9a9a54ad AG |
13 | #include <linux/module.h> |
14 | #include <linux/init.h> | |
15 | #include <linux/rtc.h> | |
5d7dc4cf | 16 | #include <linux/platform_device.h> |
9a9a54ad | 17 | #include <linux/pm.h> |
5d7dc4cf | 18 | #include <linux/regmap.h> |
9a9a54ad AG |
19 | #include <linux/slab.h> |
20 | #include <linux/spinlock.h> | |
21 | ||
9a9a54ad AG |
22 | /* RTC Register offsets from RTC CTRL REG */ |
23 | #define PM8XXX_ALARM_CTRL_OFFSET 0x01 | |
24 | #define PM8XXX_RTC_WRITE_OFFSET 0x02 | |
25 | #define PM8XXX_RTC_READ_OFFSET 0x06 | |
26 | #define PM8XXX_ALARM_RW_OFFSET 0x0A | |
27 | ||
28 | /* RTC_CTRL register bit fields */ | |
29 | #define PM8xxx_RTC_ENABLE BIT(7) | |
9a9a54ad AG |
30 | #define PM8xxx_RTC_ALARM_CLEAR BIT(0) |
31 | ||
32 | #define NUM_8_BIT_RTC_REGS 0x4 | |
33 | ||
c8d523a4 SV |
34 | /** |
35 | * struct pm8xxx_rtc_regs - describe RTC registers per PMIC versions | |
36 | * @ctrl: base address of control register | |
37 | * @write: base address of write register | |
38 | * @read: base address of read register | |
39 | * @alarm_ctrl: base address of alarm control register | |
40 | * @alarm_ctrl2: base address of alarm control2 register | |
41 | * @alarm_rw: base address of alarm read-write register | |
42 | * @alarm_en: alarm enable mask | |
43 | */ | |
44 | struct pm8xxx_rtc_regs { | |
45 | unsigned int ctrl; | |
46 | unsigned int write; | |
47 | unsigned int read; | |
48 | unsigned int alarm_ctrl; | |
49 | unsigned int alarm_ctrl2; | |
50 | unsigned int alarm_rw; | |
51 | unsigned int alarm_en; | |
52 | }; | |
53 | ||
9a9a54ad AG |
54 | /** |
55 | * struct pm8xxx_rtc - rtc driver internal structure | |
56 | * @rtc: rtc device for this driver. | |
5d7dc4cf | 57 | * @regmap: regmap used to access RTC registers |
5a418558 | 58 | * @allow_set_time: indicates whether writing to the RTC is allowed |
9a9a54ad | 59 | * @rtc_alarm_irq: rtc alarm irq number. |
9a9a54ad AG |
60 | * @ctrl_reg: rtc control register. |
61 | * @rtc_dev: device structure. | |
62 | * @ctrl_reg_lock: spinlock protecting access to ctrl_reg. | |
63 | */ | |
64 | struct pm8xxx_rtc { | |
65 | struct rtc_device *rtc; | |
5d7dc4cf | 66 | struct regmap *regmap; |
5a418558 | 67 | bool allow_set_time; |
9a9a54ad | 68 | int rtc_alarm_irq; |
c8d523a4 | 69 | const struct pm8xxx_rtc_regs *regs; |
9a9a54ad AG |
70 | struct device *rtc_dev; |
71 | spinlock_t ctrl_reg_lock; | |
72 | }; | |
73 | ||
9a9a54ad AG |
74 | /* |
75 | * Steps to write the RTC registers. | |
76 | * 1. Disable alarm if enabled. | |
77 | * 2. Write 0x00 to LSB. | |
78 | * 3. Write Byte[1], Byte[2], Byte[3] then Byte[0]. | |
79 | * 4. Enable alarm if disabled in step 1. | |
80 | */ | |
81 | static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
82 | { | |
83 | int rc, i; | |
84 | unsigned long secs, irq_flags; | |
c8d523a4 SV |
85 | u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0; |
86 | unsigned int ctrl_reg; | |
9a9a54ad | 87 | struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); |
c8d523a4 | 88 | const struct pm8xxx_rtc_regs *regs = rtc_dd->regs; |
9a9a54ad | 89 | |
5a418558 JC |
90 | if (!rtc_dd->allow_set_time) |
91 | return -EACCES; | |
92 | ||
9a9a54ad AG |
93 | rtc_tm_to_time(tm, &secs); |
94 | ||
95 | for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) { | |
96 | value[i] = secs & 0xFF; | |
97 | secs >>= 8; | |
98 | } | |
99 | ||
100 | dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs); | |
101 | ||
102 | spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags); | |
9a9a54ad | 103 | |
c8d523a4 SV |
104 | rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg); |
105 | if (rc) | |
106 | goto rtc_rw_fail; | |
107 | ||
108 | if (ctrl_reg & regs->alarm_en) { | |
9a9a54ad | 109 | alarm_enabled = 1; |
c8d523a4 SV |
110 | ctrl_reg &= ~regs->alarm_en; |
111 | rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg); | |
5d7dc4cf | 112 | if (rc) { |
5bed811d | 113 | dev_err(dev, "Write to RTC control register failed\n"); |
9a9a54ad AG |
114 | goto rtc_rw_fail; |
115 | } | |
5bed811d | 116 | } |
9a9a54ad AG |
117 | |
118 | /* Write 0 to Byte[0] */ | |
c8d523a4 | 119 | rc = regmap_write(rtc_dd->regmap, regs->write, 0); |
5d7dc4cf | 120 | if (rc) { |
9a9a54ad AG |
121 | dev_err(dev, "Write to RTC write data register failed\n"); |
122 | goto rtc_rw_fail; | |
123 | } | |
124 | ||
125 | /* Write Byte[1], Byte[2], Byte[3] */ | |
c8d523a4 | 126 | rc = regmap_bulk_write(rtc_dd->regmap, regs->write + 1, |
5d7dc4cf JC |
127 | &value[1], sizeof(value) - 1); |
128 | if (rc) { | |
9a9a54ad AG |
129 | dev_err(dev, "Write to RTC write data register failed\n"); |
130 | goto rtc_rw_fail; | |
131 | } | |
132 | ||
133 | /* Write Byte[0] */ | |
c8d523a4 | 134 | rc = regmap_write(rtc_dd->regmap, regs->write, value[0]); |
5d7dc4cf | 135 | if (rc) { |
9a9a54ad AG |
136 | dev_err(dev, "Write to RTC write data register failed\n"); |
137 | goto rtc_rw_fail; | |
138 | } | |
139 | ||
140 | if (alarm_enabled) { | |
c8d523a4 SV |
141 | ctrl_reg |= regs->alarm_en; |
142 | rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg); | |
5d7dc4cf | 143 | if (rc) { |
5bed811d | 144 | dev_err(dev, "Write to RTC control register failed\n"); |
9a9a54ad AG |
145 | goto rtc_rw_fail; |
146 | } | |
9a9a54ad AG |
147 | } |
148 | ||
149 | rtc_rw_fail: | |
c8d523a4 | 150 | spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); |
9a9a54ad AG |
151 | |
152 | return rc; | |
153 | } | |
154 | ||
155 | static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
156 | { | |
157 | int rc; | |
5d7dc4cf | 158 | u8 value[NUM_8_BIT_RTC_REGS]; |
9a9a54ad | 159 | unsigned long secs; |
5d7dc4cf | 160 | unsigned int reg; |
9a9a54ad | 161 | struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); |
c8d523a4 | 162 | const struct pm8xxx_rtc_regs *regs = rtc_dd->regs; |
9a9a54ad | 163 | |
c8d523a4 | 164 | rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value, sizeof(value)); |
5d7dc4cf | 165 | if (rc) { |
9a9a54ad AG |
166 | dev_err(dev, "RTC read data register failed\n"); |
167 | return rc; | |
168 | } | |
169 | ||
170 | /* | |
171 | * Read the LSB again and check if there has been a carry over. | |
172 | * If there is, redo the read operation. | |
173 | */ | |
c8d523a4 | 174 | rc = regmap_read(rtc_dd->regmap, regs->read, ®); |
9a9a54ad AG |
175 | if (rc < 0) { |
176 | dev_err(dev, "RTC read data register failed\n"); | |
177 | return rc; | |
178 | } | |
179 | ||
180 | if (unlikely(reg < value[0])) { | |
c8d523a4 | 181 | rc = regmap_bulk_read(rtc_dd->regmap, regs->read, |
5d7dc4cf JC |
182 | value, sizeof(value)); |
183 | if (rc) { | |
9a9a54ad AG |
184 | dev_err(dev, "RTC read data register failed\n"); |
185 | return rc; | |
186 | } | |
187 | } | |
188 | ||
189 | secs = value[0] | (value[1] << 8) | (value[2] << 16) | (value[3] << 24); | |
190 | ||
191 | rtc_time_to_tm(secs, tm); | |
192 | ||
193 | rc = rtc_valid_tm(tm); | |
194 | if (rc < 0) { | |
195 | dev_err(dev, "Invalid time read from RTC\n"); | |
196 | return rc; | |
197 | } | |
198 | ||
199 | dev_dbg(dev, "secs = %lu, h:m:s == %d:%d:%d, d/m/y = %d/%d/%d\n", | |
5bed811d JC |
200 | secs, tm->tm_hour, tm->tm_min, tm->tm_sec, |
201 | tm->tm_mday, tm->tm_mon, tm->tm_year); | |
9a9a54ad AG |
202 | |
203 | return 0; | |
204 | } | |
205 | ||
206 | static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) | |
207 | { | |
208 | int rc, i; | |
c8d523a4 SV |
209 | u8 value[NUM_8_BIT_RTC_REGS]; |
210 | unsigned int ctrl_reg; | |
9a9a54ad AG |
211 | unsigned long secs, irq_flags; |
212 | struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); | |
c8d523a4 | 213 | const struct pm8xxx_rtc_regs *regs = rtc_dd->regs; |
9a9a54ad AG |
214 | |
215 | rtc_tm_to_time(&alarm->time, &secs); | |
216 | ||
217 | for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) { | |
218 | value[i] = secs & 0xFF; | |
219 | secs >>= 8; | |
220 | } | |
221 | ||
222 | spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags); | |
223 | ||
c8d523a4 | 224 | rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value, |
5d7dc4cf JC |
225 | sizeof(value)); |
226 | if (rc) { | |
9a9a54ad AG |
227 | dev_err(dev, "Write to RTC ALARM register failed\n"); |
228 | goto rtc_rw_fail; | |
229 | } | |
230 | ||
c8d523a4 SV |
231 | rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg); |
232 | if (rc) | |
233 | goto rtc_rw_fail; | |
5bed811d JC |
234 | |
235 | if (alarm->enabled) | |
c8d523a4 | 236 | ctrl_reg |= regs->alarm_en; |
5bed811d | 237 | else |
c8d523a4 | 238 | ctrl_reg &= ~regs->alarm_en; |
9a9a54ad | 239 | |
c8d523a4 | 240 | rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg); |
5d7dc4cf | 241 | if (rc) { |
c8d523a4 | 242 | dev_err(dev, "Write to RTC alarm control register failed\n"); |
9a9a54ad AG |
243 | goto rtc_rw_fail; |
244 | } | |
245 | ||
9a9a54ad | 246 | dev_dbg(dev, "Alarm Set for h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n", |
5bed811d JC |
247 | alarm->time.tm_hour, alarm->time.tm_min, |
248 | alarm->time.tm_sec, alarm->time.tm_mday, | |
249 | alarm->time.tm_mon, alarm->time.tm_year); | |
9a9a54ad AG |
250 | rtc_rw_fail: |
251 | spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); | |
252 | return rc; | |
253 | } | |
254 | ||
255 | static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) | |
256 | { | |
257 | int rc; | |
258 | u8 value[NUM_8_BIT_RTC_REGS]; | |
259 | unsigned long secs; | |
260 | struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); | |
c8d523a4 | 261 | const struct pm8xxx_rtc_regs *regs = rtc_dd->regs; |
9a9a54ad | 262 | |
c8d523a4 | 263 | rc = regmap_bulk_read(rtc_dd->regmap, regs->alarm_rw, value, |
5d7dc4cf JC |
264 | sizeof(value)); |
265 | if (rc) { | |
9a9a54ad AG |
266 | dev_err(dev, "RTC alarm time read failed\n"); |
267 | return rc; | |
268 | } | |
269 | ||
270 | secs = value[0] | (value[1] << 8) | (value[2] << 16) | (value[3] << 24); | |
271 | ||
272 | rtc_time_to_tm(secs, &alarm->time); | |
273 | ||
274 | rc = rtc_valid_tm(&alarm->time); | |
275 | if (rc < 0) { | |
276 | dev_err(dev, "Invalid alarm time read from RTC\n"); | |
277 | return rc; | |
278 | } | |
279 | ||
280 | dev_dbg(dev, "Alarm set for - h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n", | |
5bed811d JC |
281 | alarm->time.tm_hour, alarm->time.tm_min, |
282 | alarm->time.tm_sec, alarm->time.tm_mday, | |
283 | alarm->time.tm_mon, alarm->time.tm_year); | |
9a9a54ad AG |
284 | |
285 | return 0; | |
286 | } | |
287 | ||
288 | static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable) | |
289 | { | |
290 | int rc; | |
291 | unsigned long irq_flags; | |
292 | struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); | |
c8d523a4 SV |
293 | const struct pm8xxx_rtc_regs *regs = rtc_dd->regs; |
294 | unsigned int ctrl_reg; | |
9a9a54ad AG |
295 | |
296 | spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags); | |
5bed811d | 297 | |
c8d523a4 SV |
298 | rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg); |
299 | if (rc) | |
300 | goto rtc_rw_fail; | |
5bed811d JC |
301 | |
302 | if (enable) | |
c8d523a4 | 303 | ctrl_reg |= regs->alarm_en; |
5bed811d | 304 | else |
c8d523a4 | 305 | ctrl_reg &= ~regs->alarm_en; |
9a9a54ad | 306 | |
c8d523a4 | 307 | rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg); |
5d7dc4cf | 308 | if (rc) { |
9a9a54ad AG |
309 | dev_err(dev, "Write to RTC control register failed\n"); |
310 | goto rtc_rw_fail; | |
311 | } | |
312 | ||
9a9a54ad AG |
313 | rtc_rw_fail: |
314 | spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); | |
315 | return rc; | |
316 | } | |
317 | ||
5a418558 | 318 | static const struct rtc_class_ops pm8xxx_rtc_ops = { |
9a9a54ad | 319 | .read_time = pm8xxx_rtc_read_time, |
5a418558 | 320 | .set_time = pm8xxx_rtc_set_time, |
9a9a54ad AG |
321 | .set_alarm = pm8xxx_rtc_set_alarm, |
322 | .read_alarm = pm8xxx_rtc_read_alarm, | |
323 | .alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable, | |
324 | }; | |
325 | ||
326 | static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id) | |
327 | { | |
328 | struct pm8xxx_rtc *rtc_dd = dev_id; | |
c8d523a4 | 329 | const struct pm8xxx_rtc_regs *regs = rtc_dd->regs; |
5d7dc4cf | 330 | unsigned int ctrl_reg; |
9a9a54ad AG |
331 | int rc; |
332 | unsigned long irq_flags; | |
333 | ||
334 | rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF); | |
335 | ||
336 | spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags); | |
337 | ||
338 | /* Clear the alarm enable bit */ | |
c8d523a4 SV |
339 | rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg); |
340 | if (rc) { | |
341 | spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); | |
342 | goto rtc_alarm_handled; | |
343 | } | |
344 | ||
345 | ctrl_reg &= ~regs->alarm_en; | |
9a9a54ad | 346 | |
c8d523a4 | 347 | rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg); |
5d7dc4cf | 348 | if (rc) { |
9a9a54ad | 349 | spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); |
5bed811d | 350 | dev_err(rtc_dd->rtc_dev, |
c8d523a4 | 351 | "Write to alarm control register failed\n"); |
9a9a54ad AG |
352 | goto rtc_alarm_handled; |
353 | } | |
354 | ||
9a9a54ad AG |
355 | spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags); |
356 | ||
357 | /* Clear RTC alarm register */ | |
c8d523a4 | 358 | rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl2, &ctrl_reg); |
5d7dc4cf | 359 | if (rc) { |
5bed811d | 360 | dev_err(rtc_dd->rtc_dev, |
c8d523a4 | 361 | "RTC Alarm control2 register read failed\n"); |
9a9a54ad AG |
362 | goto rtc_alarm_handled; |
363 | } | |
364 | ||
c8d523a4 SV |
365 | ctrl_reg |= PM8xxx_RTC_ALARM_CLEAR; |
366 | rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl2, ctrl_reg); | |
5d7dc4cf | 367 | if (rc) |
5bed811d | 368 | dev_err(rtc_dd->rtc_dev, |
c8d523a4 | 369 | "Write to RTC Alarm control2 register failed\n"); |
9a9a54ad AG |
370 | |
371 | rtc_alarm_handled: | |
372 | return IRQ_HANDLED; | |
373 | } | |
374 | ||
c8d523a4 SV |
375 | static int pm8xxx_rtc_enable(struct pm8xxx_rtc *rtc_dd) |
376 | { | |
377 | const struct pm8xxx_rtc_regs *regs = rtc_dd->regs; | |
378 | unsigned int ctrl_reg; | |
379 | int rc; | |
380 | ||
381 | /* Check if the RTC is on, else turn it on */ | |
382 | rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg); | |
383 | if (rc) | |
384 | return rc; | |
385 | ||
386 | if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) { | |
387 | ctrl_reg |= PM8xxx_RTC_ENABLE; | |
388 | rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg); | |
389 | if (rc) | |
390 | return rc; | |
391 | } | |
392 | ||
393 | return 0; | |
394 | } | |
395 | ||
396 | static const struct pm8xxx_rtc_regs pm8921_regs = { | |
397 | .ctrl = 0x11d, | |
398 | .write = 0x11f, | |
399 | .read = 0x123, | |
400 | .alarm_rw = 0x127, | |
401 | .alarm_ctrl = 0x11d, | |
402 | .alarm_ctrl2 = 0x11e, | |
403 | .alarm_en = BIT(1), | |
404 | }; | |
405 | ||
406 | static const struct pm8xxx_rtc_regs pm8058_regs = { | |
407 | .ctrl = 0x1e8, | |
408 | .write = 0x1ea, | |
409 | .read = 0x1ee, | |
410 | .alarm_rw = 0x1f2, | |
411 | .alarm_ctrl = 0x1e8, | |
412 | .alarm_ctrl2 = 0x1e9, | |
413 | .alarm_en = BIT(1), | |
414 | }; | |
415 | ||
416 | static const struct pm8xxx_rtc_regs pm8941_regs = { | |
417 | .ctrl = 0x6046, | |
418 | .write = 0x6040, | |
419 | .read = 0x6048, | |
420 | .alarm_rw = 0x6140, | |
421 | .alarm_ctrl = 0x6146, | |
422 | .alarm_ctrl2 = 0x6148, | |
423 | .alarm_en = BIT(7), | |
424 | }; | |
425 | ||
5a418558 JC |
426 | /* |
427 | * Hardcoded RTC bases until IORESOURCE_REG mapping is figured out | |
428 | */ | |
429 | static const struct of_device_id pm8xxx_id_table[] = { | |
c8d523a4 SV |
430 | { .compatible = "qcom,pm8921-rtc", .data = &pm8921_regs }, |
431 | { .compatible = "qcom,pm8058-rtc", .data = &pm8058_regs }, | |
432 | { .compatible = "qcom,pm8941-rtc", .data = &pm8941_regs }, | |
5a418558 JC |
433 | { }, |
434 | }; | |
435 | MODULE_DEVICE_TABLE(of, pm8xxx_id_table); | |
436 | ||
5a167f45 | 437 | static int pm8xxx_rtc_probe(struct platform_device *pdev) |
9a9a54ad AG |
438 | { |
439 | int rc; | |
9a9a54ad | 440 | struct pm8xxx_rtc *rtc_dd; |
5a418558 | 441 | const struct of_device_id *match; |
9a9a54ad | 442 | |
5a418558 JC |
443 | match = of_match_node(pm8xxx_id_table, pdev->dev.of_node); |
444 | if (!match) | |
445 | return -ENXIO; | |
9a9a54ad | 446 | |
c417299c | 447 | rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL); |
49ae425b | 448 | if (rtc_dd == NULL) |
9a9a54ad | 449 | return -ENOMEM; |
9a9a54ad AG |
450 | |
451 | /* Initialise spinlock to protect RTC control register */ | |
452 | spin_lock_init(&rtc_dd->ctrl_reg_lock); | |
453 | ||
5d7dc4cf JC |
454 | rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL); |
455 | if (!rtc_dd->regmap) { | |
456 | dev_err(&pdev->dev, "Parent regmap unavailable.\n"); | |
457 | return -ENXIO; | |
458 | } | |
459 | ||
9a9a54ad AG |
460 | rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0); |
461 | if (rtc_dd->rtc_alarm_irq < 0) { | |
462 | dev_err(&pdev->dev, "Alarm IRQ resource absent!\n"); | |
c417299c | 463 | return -ENXIO; |
9a9a54ad AG |
464 | } |
465 | ||
5a418558 JC |
466 | rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node, |
467 | "allow-set-time"); | |
9a9a54ad | 468 | |
c8d523a4 | 469 | rtc_dd->regs = match->data; |
9a9a54ad AG |
470 | rtc_dd->rtc_dev = &pdev->dev; |
471 | ||
c8d523a4 SV |
472 | rc = pm8xxx_rtc_enable(rtc_dd); |
473 | if (rc) | |
c417299c | 474 | return rc; |
9a9a54ad AG |
475 | |
476 | platform_set_drvdata(pdev, rtc_dd); | |
477 | ||
fda9909d JC |
478 | device_init_wakeup(&pdev->dev, 1); |
479 | ||
9a9a54ad | 480 | /* Register the RTC device */ |
c417299c | 481 | rtc_dd->rtc = devm_rtc_device_register(&pdev->dev, "pm8xxx_rtc", |
5bed811d | 482 | &pm8xxx_rtc_ops, THIS_MODULE); |
9a9a54ad AG |
483 | if (IS_ERR(rtc_dd->rtc)) { |
484 | dev_err(&pdev->dev, "%s: RTC registration failed (%ld)\n", | |
5bed811d | 485 | __func__, PTR_ERR(rtc_dd->rtc)); |
c417299c | 486 | return PTR_ERR(rtc_dd->rtc); |
9a9a54ad AG |
487 | } |
488 | ||
489 | /* Request the alarm IRQ */ | |
bffcbc08 JC |
490 | rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->rtc_alarm_irq, |
491 | pm8xxx_alarm_trigger, | |
492 | IRQF_TRIGGER_RISING, | |
493 | "pm8xxx_rtc_alarm", rtc_dd); | |
9a9a54ad AG |
494 | if (rc < 0) { |
495 | dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc); | |
c417299c | 496 | return rc; |
9a9a54ad AG |
497 | } |
498 | ||
9a9a54ad AG |
499 | dev_dbg(&pdev->dev, "Probe success !!\n"); |
500 | ||
501 | return 0; | |
9a9a54ad AG |
502 | } |
503 | ||
9a9a54ad AG |
504 | #ifdef CONFIG_PM_SLEEP |
505 | static int pm8xxx_rtc_resume(struct device *dev) | |
506 | { | |
507 | struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); | |
508 | ||
509 | if (device_may_wakeup(dev)) | |
510 | disable_irq_wake(rtc_dd->rtc_alarm_irq); | |
511 | ||
512 | return 0; | |
513 | } | |
514 | ||
515 | static int pm8xxx_rtc_suspend(struct device *dev) | |
516 | { | |
517 | struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); | |
518 | ||
519 | if (device_may_wakeup(dev)) | |
520 | enable_irq_wake(rtc_dd->rtc_alarm_irq); | |
521 | ||
522 | return 0; | |
523 | } | |
524 | #endif | |
525 | ||
5bed811d JC |
526 | static SIMPLE_DEV_PM_OPS(pm8xxx_rtc_pm_ops, |
527 | pm8xxx_rtc_suspend, | |
528 | pm8xxx_rtc_resume); | |
9a9a54ad AG |
529 | |
530 | static struct platform_driver pm8xxx_rtc_driver = { | |
531 | .probe = pm8xxx_rtc_probe, | |
9a9a54ad | 532 | .driver = { |
5a418558 | 533 | .name = "rtc-pm8xxx", |
5a418558 JC |
534 | .pm = &pm8xxx_rtc_pm_ops, |
535 | .of_match_table = pm8xxx_id_table, | |
9a9a54ad AG |
536 | }, |
537 | }; | |
538 | ||
0c4eae66 | 539 | module_platform_driver(pm8xxx_rtc_driver); |
9a9a54ad AG |
540 | |
541 | MODULE_ALIAS("platform:rtc-pm8xxx"); | |
542 | MODULE_DESCRIPTION("PMIC8xxx RTC driver"); | |
543 | MODULE_LICENSE("GPL v2"); | |
544 | MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>"); |