Commit | Line | Data |
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e9f2bd81 NI |
1 | /* |
2 | * Ricoh RS5C313 RTC device/driver | |
3 | * Copyright (C) 2007 Nobuhiro Iwamatsu | |
4 | * | |
5 | * 2005-09-19 modifed by kogiidena | |
6 | * | |
7 | * Based on the old drivers/char/rs5c313_rtc.c by: | |
8 | * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org> | |
9 | * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka | |
10 | * | |
11 | * Based on code written by Paul Gortmaker. | |
12 | * Copyright (C) 1996 Paul Gortmaker | |
13 | * | |
14 | * This file is subject to the terms and conditions of the GNU General Public | |
15 | * License. See the file "COPYING" in the main directory of this archive | |
16 | * for more details. | |
17 | * | |
18 | * Based on other minimal char device drivers, like Alan's | |
19 | * watchdog, Ted's random, etc. etc. | |
20 | * | |
21 | * 1.07 Paul Gortmaker. | |
22 | * 1.08 Miquel van Smoorenburg: disallow certain things on the | |
23 | * DEC Alpha as the CMOS clock is also used for other things. | |
24 | * 1.09 Nikita Schmidt: epoch support and some Alpha cleanup. | |
25 | * 1.09a Pete Zaitcev: Sun SPARC | |
26 | * 1.09b Jeff Garzik: Modularize, init cleanup | |
27 | * 1.09c Jeff Garzik: SMP cleanup | |
28 | * 1.10 Paul Barton-Davis: add support for async I/O | |
29 | * 1.10a Andrea Arcangeli: Alpha updates | |
30 | * 1.10b Andrew Morton: SMP lock fix | |
31 | * 1.10c Cesar Barros: SMP locking fixes and cleanup | |
32 | * 1.10d Paul Gortmaker: delete paranoia check in rtc_exit | |
33 | * 1.10e Maciej W. Rozycki: Handle DECstation's year weirdness. | |
34 | * 1.11 Takashi Iwai: Kernel access functions | |
35 | * rtc_register/rtc_unregister/rtc_control | |
36 | * 1.11a Daniele Bellucci: Audit create_proc_read_entry in rtc_init | |
37 | * 1.12 Venkatesh Pallipadi: Hooks for emulating rtc on HPET base-timer | |
38 | * CONFIG_HPET_EMULATE_RTC | |
39 | * 1.13 Nobuhiro Iwamatsu: Updata driver. | |
40 | */ | |
41 | ||
42 | #include <linux/module.h> | |
43 | #include <linux/err.h> | |
44 | #include <linux/rtc.h> | |
45 | #include <linux/platform_device.h> | |
46 | #include <linux/bcd.h> | |
47 | #include <linux/delay.h> | |
48 | #include <asm/io.h> | |
49 | ||
50 | #define DRV_NAME "rs5c313" | |
51 | #define DRV_VERSION "1.13" | |
52 | ||
53 | #ifdef CONFIG_SH_LANDISK | |
54 | /*****************************************************/ | |
55 | /* LANDISK dependence part of RS5C313 */ | |
56 | /*****************************************************/ | |
57 | ||
58 | #define SCSMR1 0xFFE00000 | |
59 | #define SCSCR1 0xFFE00008 | |
60 | #define SCSMR1_CA 0x80 | |
61 | #define SCSCR1_CKE 0x03 | |
62 | #define SCSPTR1 0xFFE0001C | |
63 | #define SCSPTR1_EIO 0x80 | |
64 | #define SCSPTR1_SPB1IO 0x08 | |
65 | #define SCSPTR1_SPB1DT 0x04 | |
66 | #define SCSPTR1_SPB0IO 0x02 | |
67 | #define SCSPTR1_SPB0DT 0x01 | |
68 | ||
69 | #define SDA_OEN SCSPTR1_SPB1IO | |
70 | #define SDA SCSPTR1_SPB1DT | |
71 | #define SCL_OEN SCSPTR1_SPB0IO | |
72 | #define SCL SCSPTR1_SPB0DT | |
73 | ||
74 | /* RICOH RS5C313 CE port */ | |
75 | #define RS5C313_CE 0xB0000003 | |
76 | ||
77 | /* RICOH RS5C313 CE port bit */ | |
78 | #define RS5C313_CE_RTCCE 0x02 | |
79 | ||
80 | /* SCSPTR1 data */ | |
81 | unsigned char scsptr1_data; | |
82 | ||
83 | #define RS5C313_CEENABLE ctrl_outb(RS5C313_CE_RTCCE, RS5C313_CE); | |
84 | #define RS5C313_CEDISABLE ctrl_outb(0x00, RS5C313_CE) | |
85 | #define RS5C313_MISCOP ctrl_outb(0x02, 0xB0000008) | |
86 | ||
87 | static void rs5c313_init_port(void) | |
88 | { | |
89 | /* Set SCK as I/O port and Initialize SCSPTR1 data & I/O port. */ | |
90 | ctrl_outb(ctrl_inb(SCSMR1) & ~SCSMR1_CA, SCSMR1); | |
91 | ctrl_outb(ctrl_inb(SCSCR1) & ~SCSCR1_CKE, SCSCR1); | |
92 | ||
93 | /* And Initialize SCL for RS5C313 clock */ | |
94 | scsptr1_data = ctrl_inb(SCSPTR1) | SCL; /* SCL:H */ | |
95 | ctrl_outb(scsptr1_data, SCSPTR1); | |
96 | scsptr1_data = ctrl_inb(SCSPTR1) | SCL_OEN; /* SCL output enable */ | |
97 | ctrl_outb(scsptr1_data, SCSPTR1); | |
98 | RS5C313_CEDISABLE; /* CE:L */ | |
99 | } | |
100 | ||
101 | static void rs5c313_write_data(unsigned char data) | |
102 | { | |
103 | int i; | |
104 | ||
105 | for (i = 0; i < 8; i++) { | |
106 | /* SDA:Write Data */ | |
107 | scsptr1_data = (scsptr1_data & ~SDA) | | |
108 | ((((0x80 >> i) & data) >> (7 - i)) << 2); | |
109 | ctrl_outb(scsptr1_data, SCSPTR1); | |
110 | if (i == 0) { | |
111 | scsptr1_data |= SDA_OEN; /* SDA:output enable */ | |
112 | ctrl_outb(scsptr1_data, SCSPTR1); | |
113 | } | |
114 | ndelay(700); | |
115 | scsptr1_data &= ~SCL; /* SCL:L */ | |
116 | ctrl_outb(scsptr1_data, SCSPTR1); | |
117 | ndelay(700); | |
118 | scsptr1_data |= SCL; /* SCL:H */ | |
119 | ctrl_outb(scsptr1_data, SCSPTR1); | |
120 | } | |
121 | ||
122 | scsptr1_data &= ~SDA_OEN; /* SDA:output disable */ | |
123 | ctrl_outb(scsptr1_data, SCSPTR1); | |
124 | } | |
125 | ||
126 | static unsigned char rs5c313_read_data(void) | |
127 | { | |
128 | int i; | |
129 | unsigned char data; | |
130 | ||
131 | for (i = 0; i < 8; i++) { | |
132 | ndelay(700); | |
133 | /* SDA:Read Data */ | |
134 | data |= ((ctrl_inb(SCSPTR1) & SDA) >> 2) << (7 - i); | |
135 | scsptr1_data &= ~SCL; /* SCL:L */ | |
136 | ctrl_outb(scsptr1_data, SCSPTR1); | |
137 | ndelay(700); | |
138 | scsptr1_data |= SCL; /* SCL:H */ | |
139 | ctrl_outb(scsptr1_data, SCSPTR1); | |
140 | } | |
141 | return data & 0x0F; | |
142 | } | |
143 | ||
144 | #endif /* CONFIG_SH_LANDISK */ | |
145 | ||
146 | /*****************************************************/ | |
147 | /* machine independence part of RS5C313 */ | |
148 | /*****************************************************/ | |
149 | ||
150 | /* RICOH RS5C313 address */ | |
151 | #define RS5C313_ADDR_SEC 0x00 | |
152 | #define RS5C313_ADDR_SEC10 0x01 | |
153 | #define RS5C313_ADDR_MIN 0x02 | |
154 | #define RS5C313_ADDR_MIN10 0x03 | |
155 | #define RS5C313_ADDR_HOUR 0x04 | |
156 | #define RS5C313_ADDR_HOUR10 0x05 | |
157 | #define RS5C313_ADDR_WEEK 0x06 | |
158 | #define RS5C313_ADDR_INTINTVREG 0x07 | |
159 | #define RS5C313_ADDR_DAY 0x08 | |
160 | #define RS5C313_ADDR_DAY10 0x09 | |
161 | #define RS5C313_ADDR_MON 0x0A | |
162 | #define RS5C313_ADDR_MON10 0x0B | |
163 | #define RS5C313_ADDR_YEAR 0x0C | |
164 | #define RS5C313_ADDR_YEAR10 0x0D | |
165 | #define RS5C313_ADDR_CNTREG 0x0E | |
166 | #define RS5C313_ADDR_TESTREG 0x0F | |
167 | ||
168 | /* RICOH RS5C313 control register */ | |
169 | #define RS5C313_CNTREG_ADJ_BSY 0x01 | |
170 | #define RS5C313_CNTREG_WTEN_XSTP 0x02 | |
171 | #define RS5C313_CNTREG_12_24 0x04 | |
172 | #define RS5C313_CNTREG_CTFG 0x08 | |
173 | ||
174 | /* RICOH RS5C313 test register */ | |
175 | #define RS5C313_TESTREG_TEST 0x01 | |
176 | ||
177 | /* RICOH RS5C313 control bit */ | |
178 | #define RS5C313_CNTBIT_READ 0x40 | |
179 | #define RS5C313_CNTBIT_AD 0x20 | |
180 | #define RS5C313_CNTBIT_DT 0x10 | |
181 | ||
182 | static unsigned char rs5c313_read_reg(unsigned char addr) | |
183 | { | |
184 | ||
185 | rs5c313_write_data(addr | RS5C313_CNTBIT_READ | RS5C313_CNTBIT_AD); | |
186 | return rs5c313_read_data(); | |
187 | } | |
188 | ||
189 | static void rs5c313_write_reg(unsigned char addr, unsigned char data) | |
190 | { | |
191 | data &= 0x0f; | |
192 | rs5c313_write_data(addr | RS5C313_CNTBIT_AD); | |
193 | rs5c313_write_data(data | RS5C313_CNTBIT_DT); | |
194 | return; | |
195 | } | |
196 | ||
197 | static inline unsigned char rs5c313_read_cntreg(unsigned char addr) | |
198 | { | |
199 | return rs5c313_read_reg(RS5C313_ADDR_CNTREG); | |
200 | } | |
201 | ||
202 | static inline void rs5c313_write_cntreg(unsigned char data) | |
203 | { | |
204 | rs5c313_write_reg(RS5C313_ADDR_CNTREG, data); | |
205 | } | |
206 | ||
207 | static inline void rs5c313_write_intintvreg(unsigned char data) | |
208 | { | |
209 | rs5c313_write_reg(RS5C313_ADDR_INTINTVREG, data); | |
210 | } | |
211 | ||
212 | static int rs5c313_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
213 | { | |
214 | int data; | |
215 | ||
216 | while (1) { | |
217 | RS5C313_CEENABLE; /* CE:H */ | |
218 | ||
219 | /* Initialize control reg. 24 hour */ | |
220 | rs5c313_write_cntreg(0x04); | |
221 | ||
222 | if (!(rs5c313_read_cntreg() & RS5C313_CNTREG_ADJ_BSY)) | |
223 | break; | |
224 | ||
225 | RS5C313_CEDISABLE; | |
226 | ndelay(700); /* CE:L */ | |
227 | ||
228 | } | |
229 | ||
230 | data = rs5c313_read_reg(RS5C313_ADDR_SEC); | |
231 | data |= (rs5c313_read_reg(RS5C313_ADDR_SEC10) << 4); | |
232 | tm->tm_sec = BCD2BIN(data); | |
233 | ||
234 | data = rs5c313_read_reg(RS5C313_ADDR_MIN); | |
235 | data |= (rs5c313_read_reg(RS5C313_ADDR_MIN10) << 4); | |
236 | tm->tm_min = BCD2BIN(data); | |
237 | ||
238 | data = rs5c313_read_reg(RS5C313_ADDR_HOUR); | |
239 | data |= (rs5c313_read_reg(RS5C313_ADDR_HOUR10) << 4); | |
240 | tm->tm_hour = BCD2BIN(data); | |
241 | ||
242 | data = rs5c313_read_reg(RS5C313_ADDR_DAY); | |
243 | data |= (rs5c313_read_reg(RS5C313_ADDR_DAY10) << 4); | |
244 | tm->tm_mday = BCD2BIN(data); | |
245 | ||
246 | data = rs5c313_read_reg(RS5C313_ADDR_MON); | |
247 | data |= (rs5c313_read_reg(RS5C313_ADDR_MON10) << 4); | |
248 | tm->tm_mon = BCD2BIN(data) - 1; | |
249 | ||
250 | data = rs5c313_read_reg(RS5C313_ADDR_YEAR); | |
251 | data |= (rs5c313_read_reg(RS5C313_ADDR_YEAR10) << 4); | |
252 | tm->tm_year = BCD2BIN(data); | |
253 | ||
254 | if (tm->tm_year < 70) | |
255 | tm->tm_year += 100; | |
256 | ||
257 | data = rs5c313_read_reg(RS5C313_ADDR_WEEK); | |
258 | tm->tm_wday = BCD2BIN(data); | |
259 | ||
260 | RS5C313_CEDISABLE; | |
261 | ndelay(700); /* CE:L */ | |
262 | ||
263 | return 0; | |
264 | } | |
265 | ||
266 | static int rs5c313_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
267 | { | |
268 | int data; | |
269 | ||
270 | /* busy check. */ | |
271 | while (1) { | |
272 | RS5C313_CEENABLE; /* CE:H */ | |
273 | ||
274 | /* Initiatlize control reg. 24 hour */ | |
275 | rs5c313_write_cntreg(0x04); | |
276 | ||
277 | if (!(rs5c313_read_cntreg() & RS5C313_CNTREG_ADJ_BSY)) | |
278 | break; | |
279 | RS5C313_MISCOP; | |
280 | RS5C313_CEDISABLE; | |
281 | ndelay(700); /* CE:L */ | |
282 | } | |
283 | ||
284 | data = BIN2BCD(tm->tm_sec); | |
285 | rs5c313_write_reg(RS5C313_ADDR_SEC, data); | |
286 | rs5c313_write_reg(RS5C313_ADDR_SEC10, (data >> 4)); | |
287 | ||
288 | data = BIN2BCD(tm->tm_min); | |
289 | rs5c313_write_reg(RS5C313_ADDR_MIN, data ); | |
290 | rs5c313_write_reg(RS5C313_ADDR_MIN10, (data >> 4)); | |
291 | ||
292 | data = BIN2BCD(tm->tm_hour); | |
293 | rs5c313_write_reg(RS5C313_ADDR_HOUR, data); | |
294 | rs5c313_write_reg(RS5C313_ADDR_HOUR10, (data >> 4)); | |
295 | ||
296 | data = BIN2BCD(tm->tm_mday); | |
297 | rs5c313_write_reg(RS5C313_ADDR_DAY, data); | |
298 | rs5c313_write_reg(RS5C313_ADDR_DAY10, (data>> 4)); | |
299 | ||
300 | data = BIN2BCD(tm->tm_mon + 1); | |
301 | rs5c313_write_reg(RS5C313_ADDR_MON, data); | |
302 | rs5c313_write_reg(RS5C313_ADDR_MON10, (data >> 4)); | |
303 | ||
304 | data = BIN2BCD(tm->tm_year % 100); | |
305 | rs5c313_write_reg(RS5C313_ADDR_YEAR, data); | |
306 | rs5c313_write_reg(RS5C313_ADDR_YEAR10, (data >> 4)); | |
307 | ||
308 | data = BIN2BCD(tm->tm_wday); | |
309 | rs5c313_write_reg(RS5C313_ADDR_WEEK, data); | |
310 | ||
311 | RS5C313_CEDISABLE; /* CE:H */ | |
312 | ndelay(700); | |
313 | ||
314 | return 0; | |
315 | } | |
316 | ||
317 | static void rs5c313_check_xstp_bit(void) | |
318 | { | |
319 | struct rtc_time tm; | |
320 | ||
321 | RS5C313_CEENABLE; /* CE:H */ | |
322 | if (rs5c313_read_cntreg() & RS5C313_CNTREG_WTEN_XSTP) { | |
323 | /* INT interval reg. OFF */ | |
324 | rs5c313_write_intintvreg(0x00); | |
325 | /* Initialize control reg. 24 hour & adjust */ | |
326 | rs5c313_write_cntreg(0x07); | |
327 | ||
328 | /* busy check. */ | |
329 | while (rs5c313_read_cntreg() & RS5C313_CNTREG_ADJ_BSY) | |
330 | RS5C313_MISCOP; | |
331 | ||
332 | memset(&tm, 0, sizeof(struct rtc_time)); | |
333 | tm.tm_mday = 1; | |
334 | tm.tm_mon = 1; | |
335 | ||
336 | rs5c313_rtc_set_time(NULL, &tm); | |
337 | printk(KERN_ERR "RICHO RS5C313: invalid value, resetting to " | |
338 | "1 Jan 2000\n"); | |
339 | } | |
340 | RS5C313_CEDISABLE; | |
341 | ndelay(700); /* CE:L */ | |
342 | } | |
343 | ||
344 | static const struct rtc_class_ops rs5c313_rtc_ops = { | |
345 | .read_time = rs5c313_rtc_read_time, | |
346 | .set_time = rs5c313_rtc_set_time, | |
347 | }; | |
348 | ||
349 | static int rs5c313_rtc_probe(struct platform_device *pdev) | |
350 | { | |
351 | struct rtc_device *rtc = rtc_device_register("rs5c313", &pdev->dev, | |
352 | &rs5c313_rtc_ops, THIS_MODULE); | |
353 | ||
354 | if (IS_ERR(rtc)) | |
355 | return PTR_ERR(rtc); | |
356 | ||
357 | platform_set_drvdata(pdev, rtc); | |
358 | ||
359 | return err; | |
360 | } | |
361 | ||
362 | static int __devexit rs5c313_rtc_remove(struct platform_device *pdev) | |
363 | { | |
364 | struct rtc_device *rtc = platform_get_drvdata( pdev ); | |
365 | ||
366 | rtc_device_unregister(rtc); | |
367 | ||
368 | return 0; | |
369 | } | |
370 | ||
371 | static struct platform_driver rs5c313_rtc_platform_driver = { | |
372 | .driver = { | |
373 | .name = DRV_NAME, | |
374 | .owner = THIS_MODULE, | |
375 | }, | |
376 | .probe = rs5c313_rtc_probe, | |
377 | .remove = __devexit_p( rs5c313_rtc_remove ), | |
378 | }; | |
379 | ||
380 | static int __init rs5c313_rtc_init(void) | |
381 | { | |
382 | int err; | |
383 | ||
384 | err = platform_driver_register(&rs5c313_rtc_platform_driver); | |
385 | if (err) | |
386 | return err; | |
387 | ||
388 | rs5c313_init_port(); | |
389 | rs5c313_check_xstp_bit(); | |
390 | ||
391 | return 0; | |
392 | } | |
393 | ||
394 | static void __exit rs5c313_rtc_exit(void) | |
395 | { | |
396 | platform_driver_unregister( &rs5c313_rtc_platform_driver ); | |
397 | } | |
398 | ||
399 | module_init(rs5c313_rtc_init); | |
400 | module_exit(rs5c313_rtc_exit); | |
401 | ||
402 | MODULE_VERSION(DRV_VERSION); | |
403 | MODULE_AUTHOR("kogiidena , Nobuhiro Iwamatsu <iwamatsu@nigauri.org>"); | |
404 | MODULE_DESCRIPTION("Ricoh RS5C313 RTC device driver"); | |
405 | MODULE_LICENSE("GPL"); |