Commit | Line | Data |
---|---|---|
7520b94d | 1 | /* |
37fc5e2c | 2 | * An I2C driver for Ricoh RS5C372, R2025S/D and RV5C38[67] RTCs |
7520b94d AZ |
3 | * |
4 | * Copyright (C) 2005 Pavel Mironchik <pmironchik@optifacio.net> | |
5 | * Copyright (C) 2006 Tower Technologies | |
0053dc0d | 6 | * Copyright (C) 2008 Paul Mundt |
7520b94d AZ |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/i2c.h> | |
14 | #include <linux/rtc.h> | |
15 | #include <linux/bcd.h> | |
16 | ||
0053dc0d | 17 | #define DRV_VERSION "0.6" |
7520b94d | 18 | |
cb26b572 DB |
19 | |
20 | /* | |
21 | * Ricoh has a family of I2C based RTCs, which differ only slightly from | |
22 | * each other. Differences center on pinout (e.g. how many interrupts, | |
23 | * output clock, etc) and how the control registers are used. The '372 | |
24 | * is significant only because that's the one this driver first supported. | |
25 | */ | |
7520b94d AZ |
26 | #define RS5C372_REG_SECS 0 |
27 | #define RS5C372_REG_MINS 1 | |
28 | #define RS5C372_REG_HOURS 2 | |
29 | #define RS5C372_REG_WDAY 3 | |
30 | #define RS5C372_REG_DAY 4 | |
31 | #define RS5C372_REG_MONTH 5 | |
32 | #define RS5C372_REG_YEAR 6 | |
33 | #define RS5C372_REG_TRIM 7 | |
cb26b572 DB |
34 | # define RS5C372_TRIM_XSL 0x80 |
35 | # define RS5C372_TRIM_MASK 0x7F | |
36 | ||
37 | #define RS5C_REG_ALARM_A_MIN 8 /* or ALARM_W */ | |
38 | #define RS5C_REG_ALARM_A_HOURS 9 | |
39 | #define RS5C_REG_ALARM_A_WDAY 10 | |
40 | ||
41 | #define RS5C_REG_ALARM_B_MIN 11 /* or ALARM_D */ | |
42 | #define RS5C_REG_ALARM_B_HOURS 12 | |
43 | #define RS5C_REG_ALARM_B_WDAY 13 /* (ALARM_B only) */ | |
44 | ||
45 | #define RS5C_REG_CTRL1 14 | |
46 | # define RS5C_CTRL1_AALE (1 << 7) /* or WALE */ | |
47 | # define RS5C_CTRL1_BALE (1 << 6) /* or DALE */ | |
48 | # define RV5C387_CTRL1_24 (1 << 5) | |
49 | # define RS5C372A_CTRL1_SL1 (1 << 5) | |
50 | # define RS5C_CTRL1_CT_MASK (7 << 0) | |
51 | # define RS5C_CTRL1_CT0 (0 << 0) /* no periodic irq */ | |
52 | # define RS5C_CTRL1_CT4 (4 << 0) /* 1 Hz level irq */ | |
53 | #define RS5C_REG_CTRL2 15 | |
54 | # define RS5C372_CTRL2_24 (1 << 5) | |
37fc5e2c PM |
55 | # define R2025_CTRL2_XST (1 << 5) |
56 | # define RS5C_CTRL2_XSTP (1 << 4) /* only if !R2025S/D */ | |
cb26b572 DB |
57 | # define RS5C_CTRL2_CTFG (1 << 2) |
58 | # define RS5C_CTRL2_AAFG (1 << 1) /* or WAFG */ | |
59 | # define RS5C_CTRL2_BAFG (1 << 0) /* or DAFG */ | |
60 | ||
61 | ||
62 | /* to read (style 1) or write registers starting at R */ | |
63 | #define RS5C_ADDR(R) (((R) << 4) | 0) | |
64 | ||
65 | ||
66 | enum rtc_type { | |
67 | rtc_undef = 0, | |
37fc5e2c | 68 | rtc_r2025sd, |
cb26b572 DB |
69 | rtc_rs5c372a, |
70 | rtc_rs5c372b, | |
71 | rtc_rv5c386, | |
72 | rtc_rv5c387a, | |
73 | }; | |
7520b94d | 74 | |
3760f736 | 75 | static const struct i2c_device_id rs5c372_id[] = { |
37fc5e2c | 76 | { "r2025sd", rtc_r2025sd }, |
3760f736 JD |
77 | { "rs5c372a", rtc_rs5c372a }, |
78 | { "rs5c372b", rtc_rs5c372b }, | |
79 | { "rv5c386", rtc_rv5c386 }, | |
80 | { "rv5c387a", rtc_rv5c387a }, | |
81 | { } | |
82 | }; | |
83 | MODULE_DEVICE_TABLE(i2c, rs5c372_id); | |
84 | ||
cb26b572 DB |
85 | /* REVISIT: this assumes that: |
86 | * - we're in the 21st century, so it's safe to ignore the century | |
87 | * bit for rv5c38[67] (REG_MONTH bit 7); | |
88 | * - we should use ALARM_A not ALARM_B (may be wrong on some boards) | |
89 | */ | |
90 | struct rs5c372 { | |
91 | struct i2c_client *client; | |
92 | struct rtc_device *rtc; | |
93 | enum rtc_type type; | |
94 | unsigned time24:1; | |
95 | unsigned has_irq:1; | |
0053dc0d | 96 | unsigned smbus:1; |
cb26b572 DB |
97 | char buf[17]; |
98 | char *regs; | |
cb26b572 | 99 | }; |
7520b94d | 100 | |
cb26b572 DB |
101 | static int rs5c_get_regs(struct rs5c372 *rs5c) |
102 | { | |
103 | struct i2c_client *client = rs5c->client; | |
104 | struct i2c_msg msgs[] = { | |
105 | { client->addr, I2C_M_RD, sizeof rs5c->buf, rs5c->buf }, | |
106 | }; | |
107 | ||
108 | /* This implements the third reading method from the datasheet, using | |
109 | * an internal address that's reset after each transaction (by STOP) | |
110 | * to 0x0f ... so we read extra registers, and skip the first one. | |
111 | * | |
112 | * The first method doesn't work with the iop3xx adapter driver, on at | |
113 | * least 80219 chips; this works around that bug. | |
0053dc0d PM |
114 | * |
115 | * The third method on the other hand doesn't work for the SMBus-only | |
116 | * configurations, so we use the the first method there, stripping off | |
117 | * the extra register in the process. | |
cb26b572 | 118 | */ |
0053dc0d PM |
119 | if (rs5c->smbus) { |
120 | int addr = RS5C_ADDR(RS5C372_REG_SECS); | |
121 | int size = sizeof(rs5c->buf) - 1; | |
122 | ||
123 | if (i2c_smbus_read_i2c_block_data(client, addr, size, | |
124 | rs5c->buf + 1) != size) { | |
125 | dev_warn(&client->dev, "can't read registers\n"); | |
126 | return -EIO; | |
127 | } | |
128 | } else { | |
129 | if ((i2c_transfer(client->adapter, msgs, 1)) != 1) { | |
130 | dev_warn(&client->dev, "can't read registers\n"); | |
131 | return -EIO; | |
132 | } | |
cb26b572 | 133 | } |
7520b94d | 134 | |
cb26b572 DB |
135 | dev_dbg(&client->dev, |
136 | "%02x %02x %02x (%02x) %02x %02x %02x (%02x), " | |
137 | "%02x %02x %02x, %02x %02x %02x; %02x %02x\n", | |
138 | rs5c->regs[0], rs5c->regs[1], rs5c->regs[2], rs5c->regs[3], | |
139 | rs5c->regs[4], rs5c->regs[5], rs5c->regs[6], rs5c->regs[7], | |
140 | rs5c->regs[8], rs5c->regs[9], rs5c->regs[10], rs5c->regs[11], | |
141 | rs5c->regs[12], rs5c->regs[13], rs5c->regs[14], rs5c->regs[15]); | |
7520b94d | 142 | |
cb26b572 DB |
143 | return 0; |
144 | } | |
c6f24f99 | 145 | |
cb26b572 DB |
146 | static unsigned rs5c_reg2hr(struct rs5c372 *rs5c, unsigned reg) |
147 | { | |
148 | unsigned hour; | |
7520b94d | 149 | |
cb26b572 | 150 | if (rs5c->time24) |
fe20ba70 | 151 | return bcd2bin(reg & 0x3f); |
cb26b572 | 152 | |
fe20ba70 | 153 | hour = bcd2bin(reg & 0x1f); |
cb26b572 DB |
154 | if (hour == 12) |
155 | hour = 0; | |
156 | if (reg & 0x20) | |
157 | hour += 12; | |
158 | return hour; | |
159 | } | |
160 | ||
161 | static unsigned rs5c_hr2reg(struct rs5c372 *rs5c, unsigned hour) | |
7520b94d | 162 | { |
cb26b572 | 163 | if (rs5c->time24) |
fe20ba70 | 164 | return bin2bcd(hour); |
cb26b572 DB |
165 | |
166 | if (hour > 12) | |
fe20ba70 | 167 | return 0x20 | bin2bcd(hour - 12); |
cb26b572 | 168 | if (hour == 12) |
fe20ba70 | 169 | return 0x20 | bin2bcd(12); |
cb26b572 | 170 | if (hour == 0) |
fe20ba70 AB |
171 | return bin2bcd(12); |
172 | return bin2bcd(hour); | |
cb26b572 | 173 | } |
7520b94d | 174 | |
cb26b572 DB |
175 | static int rs5c372_get_datetime(struct i2c_client *client, struct rtc_time *tm) |
176 | { | |
177 | struct rs5c372 *rs5c = i2c_get_clientdata(client); | |
178 | int status = rs5c_get_regs(rs5c); | |
c6f24f99 | 179 | |
cb26b572 DB |
180 | if (status < 0) |
181 | return status; | |
7520b94d | 182 | |
fe20ba70 AB |
183 | tm->tm_sec = bcd2bin(rs5c->regs[RS5C372_REG_SECS] & 0x7f); |
184 | tm->tm_min = bcd2bin(rs5c->regs[RS5C372_REG_MINS] & 0x7f); | |
cb26b572 | 185 | tm->tm_hour = rs5c_reg2hr(rs5c, rs5c->regs[RS5C372_REG_HOURS]); |
7520b94d | 186 | |
fe20ba70 AB |
187 | tm->tm_wday = bcd2bin(rs5c->regs[RS5C372_REG_WDAY] & 0x07); |
188 | tm->tm_mday = bcd2bin(rs5c->regs[RS5C372_REG_DAY] & 0x3f); | |
7520b94d AZ |
189 | |
190 | /* tm->tm_mon is zero-based */ | |
fe20ba70 | 191 | tm->tm_mon = bcd2bin(rs5c->regs[RS5C372_REG_MONTH] & 0x1f) - 1; |
7520b94d AZ |
192 | |
193 | /* year is 1900 + tm->tm_year */ | |
fe20ba70 | 194 | tm->tm_year = bcd2bin(rs5c->regs[RS5C372_REG_YEAR]) + 100; |
7520b94d AZ |
195 | |
196 | dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d, " | |
197 | "mday=%d, mon=%d, year=%d, wday=%d\n", | |
2a4e2b87 | 198 | __func__, |
7520b94d AZ |
199 | tm->tm_sec, tm->tm_min, tm->tm_hour, |
200 | tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); | |
201 | ||
cb26b572 DB |
202 | /* rtc might need initialization */ |
203 | return rtc_valid_tm(tm); | |
7520b94d AZ |
204 | } |
205 | ||
206 | static int rs5c372_set_datetime(struct i2c_client *client, struct rtc_time *tm) | |
207 | { | |
cb26b572 DB |
208 | struct rs5c372 *rs5c = i2c_get_clientdata(client); |
209 | unsigned char buf[8]; | |
0053dc0d | 210 | int addr; |
7520b94d | 211 | |
cb26b572 | 212 | dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d " |
7520b94d | 213 | "mday=%d, mon=%d, year=%d, wday=%d\n", |
2a4e2b87 | 214 | __func__, |
cb26b572 | 215 | tm->tm_sec, tm->tm_min, tm->tm_hour, |
7520b94d AZ |
216 | tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); |
217 | ||
0053dc0d | 218 | addr = RS5C_ADDR(RS5C372_REG_SECS); |
fe20ba70 AB |
219 | buf[0] = bin2bcd(tm->tm_sec); |
220 | buf[1] = bin2bcd(tm->tm_min); | |
0053dc0d | 221 | buf[2] = rs5c_hr2reg(rs5c, tm->tm_hour); |
fe20ba70 AB |
222 | buf[3] = bin2bcd(tm->tm_wday); |
223 | buf[4] = bin2bcd(tm->tm_mday); | |
224 | buf[5] = bin2bcd(tm->tm_mon + 1); | |
225 | buf[6] = bin2bcd(tm->tm_year - 100); | |
7520b94d | 226 | |
0053dc0d | 227 | if (i2c_smbus_write_i2c_block_data(client, addr, sizeof(buf), buf) < 0) { |
2a4e2b87 | 228 | dev_err(&client->dev, "%s: write error\n", __func__); |
7520b94d AZ |
229 | return -EIO; |
230 | } | |
231 | ||
232 | return 0; | |
233 | } | |
234 | ||
cb26b572 DB |
235 | #if defined(CONFIG_RTC_INTF_PROC) || defined(CONFIG_RTC_INTF_PROC_MODULE) |
236 | #define NEED_TRIM | |
237 | #endif | |
238 | ||
239 | #if defined(CONFIG_RTC_INTF_SYSFS) || defined(CONFIG_RTC_INTF_SYSFS_MODULE) | |
240 | #define NEED_TRIM | |
241 | #endif | |
242 | ||
243 | #ifdef NEED_TRIM | |
7520b94d AZ |
244 | static int rs5c372_get_trim(struct i2c_client *client, int *osc, int *trim) |
245 | { | |
c6f24f99 | 246 | struct rs5c372 *rs5c372 = i2c_get_clientdata(client); |
cb26b572 | 247 | u8 tmp = rs5c372->regs[RS5C372_REG_TRIM]; |
7520b94d | 248 | |
7520b94d | 249 | if (osc) |
c6f24f99 | 250 | *osc = (tmp & RS5C372_TRIM_XSL) ? 32000 : 32768; |
7520b94d | 251 | |
17ad78e5 | 252 | if (trim) { |
2a4e2b87 | 253 | dev_dbg(&client->dev, "%s: raw trim=%x\n", __func__, tmp); |
cb26b572 DB |
254 | tmp &= RS5C372_TRIM_MASK; |
255 | if (tmp & 0x3e) { | |
256 | int t = tmp & 0x3f; | |
257 | ||
258 | if (tmp & 0x40) | |
259 | t = (~t | (s8)0xc0) + 1; | |
260 | else | |
261 | t = t - 1; | |
262 | ||
263 | tmp = t * 2; | |
264 | } else | |
265 | tmp = 0; | |
266 | *trim = tmp; | |
17ad78e5 | 267 | } |
7520b94d AZ |
268 | |
269 | return 0; | |
270 | } | |
cb26b572 | 271 | #endif |
7520b94d AZ |
272 | |
273 | static int rs5c372_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
274 | { | |
275 | return rs5c372_get_datetime(to_i2c_client(dev), tm); | |
276 | } | |
277 | ||
278 | static int rs5c372_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
279 | { | |
280 | return rs5c372_set_datetime(to_i2c_client(dev), tm); | |
281 | } | |
282 | ||
cb26b572 DB |
283 | #if defined(CONFIG_RTC_INTF_DEV) || defined(CONFIG_RTC_INTF_DEV_MODULE) |
284 | ||
285 | static int | |
286 | rs5c_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) | |
287 | { | |
288 | struct i2c_client *client = to_i2c_client(dev); | |
289 | struct rs5c372 *rs5c = i2c_get_clientdata(client); | |
0053dc0d PM |
290 | unsigned char buf; |
291 | int status, addr; | |
cb26b572 | 292 | |
0053dc0d | 293 | buf = rs5c->regs[RS5C_REG_CTRL1]; |
cb26b572 DB |
294 | switch (cmd) { |
295 | case RTC_UIE_OFF: | |
296 | case RTC_UIE_ON: | |
297 | /* some 327a modes use a different IRQ pin for 1Hz irqs */ | |
298 | if (rs5c->type == rtc_rs5c372a | |
0053dc0d | 299 | && (buf & RS5C372A_CTRL1_SL1)) |
cb26b572 DB |
300 | return -ENOIOCTLCMD; |
301 | case RTC_AIE_OFF: | |
302 | case RTC_AIE_ON: | |
303 | /* these irq management calls only make sense for chips | |
304 | * which are wired up to an IRQ. | |
305 | */ | |
306 | if (!rs5c->has_irq) | |
307 | return -ENOIOCTLCMD; | |
308 | break; | |
309 | default: | |
310 | return -ENOIOCTLCMD; | |
311 | } | |
312 | ||
313 | status = rs5c_get_regs(rs5c); | |
314 | if (status < 0) | |
315 | return status; | |
316 | ||
0053dc0d | 317 | addr = RS5C_ADDR(RS5C_REG_CTRL1); |
cb26b572 DB |
318 | switch (cmd) { |
319 | case RTC_AIE_OFF: /* alarm off */ | |
0053dc0d | 320 | buf &= ~RS5C_CTRL1_AALE; |
cb26b572 DB |
321 | break; |
322 | case RTC_AIE_ON: /* alarm on */ | |
0053dc0d | 323 | buf |= RS5C_CTRL1_AALE; |
cb26b572 DB |
324 | break; |
325 | case RTC_UIE_OFF: /* update off */ | |
0053dc0d | 326 | buf &= ~RS5C_CTRL1_CT_MASK; |
cb26b572 DB |
327 | break; |
328 | case RTC_UIE_ON: /* update on */ | |
0053dc0d PM |
329 | buf &= ~RS5C_CTRL1_CT_MASK; |
330 | buf |= RS5C_CTRL1_CT4; | |
cb26b572 DB |
331 | break; |
332 | } | |
0053dc0d PM |
333 | |
334 | if (i2c_smbus_write_byte_data(client, addr, buf) < 0) { | |
cb26b572 DB |
335 | printk(KERN_WARNING "%s: can't update alarm\n", |
336 | rs5c->rtc->name); | |
337 | status = -EIO; | |
338 | } else | |
0053dc0d PM |
339 | rs5c->regs[RS5C_REG_CTRL1] = buf; |
340 | ||
cb26b572 DB |
341 | return status; |
342 | } | |
343 | ||
344 | #else | |
345 | #define rs5c_rtc_ioctl NULL | |
346 | #endif | |
347 | ||
348 | ||
349 | /* NOTE: Since RTC_WKALM_{RD,SET} were originally defined for EFI, | |
350 | * which only exposes a polled programming interface; and since | |
351 | * these calls map directly to those EFI requests; we don't demand | |
352 | * we have an IRQ for this chip when we go through this API. | |
353 | * | |
354 | * The older x86_pc derived RTC_ALM_{READ,SET} calls require irqs | |
355 | * though, managed through RTC_AIE_{ON,OFF} requests. | |
356 | */ | |
357 | ||
358 | static int rs5c_read_alarm(struct device *dev, struct rtc_wkalrm *t) | |
359 | { | |
360 | struct i2c_client *client = to_i2c_client(dev); | |
361 | struct rs5c372 *rs5c = i2c_get_clientdata(client); | |
362 | int status; | |
363 | ||
364 | status = rs5c_get_regs(rs5c); | |
365 | if (status < 0) | |
366 | return status; | |
367 | ||
368 | /* report alarm time */ | |
369 | t->time.tm_sec = 0; | |
fe20ba70 | 370 | t->time.tm_min = bcd2bin(rs5c->regs[RS5C_REG_ALARM_A_MIN] & 0x7f); |
cb26b572 DB |
371 | t->time.tm_hour = rs5c_reg2hr(rs5c, rs5c->regs[RS5C_REG_ALARM_A_HOURS]); |
372 | t->time.tm_mday = -1; | |
373 | t->time.tm_mon = -1; | |
374 | t->time.tm_year = -1; | |
375 | t->time.tm_wday = -1; | |
376 | t->time.tm_yday = -1; | |
377 | t->time.tm_isdst = -1; | |
378 | ||
379 | /* ... and status */ | |
380 | t->enabled = !!(rs5c->regs[RS5C_REG_CTRL1] & RS5C_CTRL1_AALE); | |
381 | t->pending = !!(rs5c->regs[RS5C_REG_CTRL2] & RS5C_CTRL2_AAFG); | |
382 | ||
383 | return 0; | |
384 | } | |
385 | ||
386 | static int rs5c_set_alarm(struct device *dev, struct rtc_wkalrm *t) | |
387 | { | |
388 | struct i2c_client *client = to_i2c_client(dev); | |
389 | struct rs5c372 *rs5c = i2c_get_clientdata(client); | |
0053dc0d PM |
390 | int status, addr, i; |
391 | unsigned char buf[3]; | |
cb26b572 DB |
392 | |
393 | /* only handle up to 24 hours in the future, like RTC_ALM_SET */ | |
394 | if (t->time.tm_mday != -1 | |
395 | || t->time.tm_mon != -1 | |
396 | || t->time.tm_year != -1) | |
397 | return -EINVAL; | |
398 | ||
399 | /* REVISIT: round up tm_sec */ | |
400 | ||
401 | /* if needed, disable irq (clears pending status) */ | |
402 | status = rs5c_get_regs(rs5c); | |
403 | if (status < 0) | |
404 | return status; | |
405 | if (rs5c->regs[RS5C_REG_CTRL1] & RS5C_CTRL1_AALE) { | |
0053dc0d PM |
406 | addr = RS5C_ADDR(RS5C_REG_CTRL1); |
407 | buf[0] = rs5c->regs[RS5C_REG_CTRL1] & ~RS5C_CTRL1_AALE; | |
408 | if (i2c_smbus_write_byte_data(client, addr, buf[0]) < 0) { | |
cb26b572 DB |
409 | pr_debug("%s: can't disable alarm\n", rs5c->rtc->name); |
410 | return -EIO; | |
411 | } | |
0053dc0d | 412 | rs5c->regs[RS5C_REG_CTRL1] = buf[0]; |
cb26b572 DB |
413 | } |
414 | ||
415 | /* set alarm */ | |
fe20ba70 | 416 | buf[0] = bin2bcd(t->time.tm_min); |
0053dc0d PM |
417 | buf[1] = rs5c_hr2reg(rs5c, t->time.tm_hour); |
418 | buf[2] = 0x7f; /* any/all days */ | |
419 | ||
420 | for (i = 0; i < sizeof(buf); i++) { | |
421 | addr = RS5C_ADDR(RS5C_REG_ALARM_A_MIN + i); | |
422 | if (i2c_smbus_write_byte_data(client, addr, buf[i]) < 0) { | |
423 | pr_debug("%s: can't set alarm time\n", rs5c->rtc->name); | |
424 | return -EIO; | |
425 | } | |
cb26b572 DB |
426 | } |
427 | ||
428 | /* ... and maybe enable its irq */ | |
429 | if (t->enabled) { | |
0053dc0d PM |
430 | addr = RS5C_ADDR(RS5C_REG_CTRL1); |
431 | buf[0] = rs5c->regs[RS5C_REG_CTRL1] | RS5C_CTRL1_AALE; | |
432 | if (i2c_smbus_write_byte_data(client, addr, buf[0]) < 0) | |
cb26b572 DB |
433 | printk(KERN_WARNING "%s: can't enable alarm\n", |
434 | rs5c->rtc->name); | |
0053dc0d | 435 | rs5c->regs[RS5C_REG_CTRL1] = buf[0]; |
cb26b572 DB |
436 | } |
437 | ||
438 | return 0; | |
439 | } | |
440 | ||
441 | #if defined(CONFIG_RTC_INTF_PROC) || defined(CONFIG_RTC_INTF_PROC_MODULE) | |
442 | ||
7520b94d AZ |
443 | static int rs5c372_rtc_proc(struct device *dev, struct seq_file *seq) |
444 | { | |
445 | int err, osc, trim; | |
446 | ||
adfb4341 AZ |
447 | err = rs5c372_get_trim(to_i2c_client(dev), &osc, &trim); |
448 | if (err == 0) { | |
cb26b572 DB |
449 | seq_printf(seq, "crystal\t\t: %d.%03d KHz\n", |
450 | osc / 1000, osc % 1000); | |
451 | seq_printf(seq, "trim\t\t: %d\n", trim); | |
7520b94d AZ |
452 | } |
453 | ||
454 | return 0; | |
455 | } | |
456 | ||
cb26b572 DB |
457 | #else |
458 | #define rs5c372_rtc_proc NULL | |
459 | #endif | |
460 | ||
ff8371ac | 461 | static const struct rtc_class_ops rs5c372_rtc_ops = { |
7520b94d | 462 | .proc = rs5c372_rtc_proc, |
cb26b572 | 463 | .ioctl = rs5c_rtc_ioctl, |
7520b94d AZ |
464 | .read_time = rs5c372_rtc_read_time, |
465 | .set_time = rs5c372_rtc_set_time, | |
cb26b572 DB |
466 | .read_alarm = rs5c_read_alarm, |
467 | .set_alarm = rs5c_set_alarm, | |
7520b94d AZ |
468 | }; |
469 | ||
cb26b572 DB |
470 | #if defined(CONFIG_RTC_INTF_SYSFS) || defined(CONFIG_RTC_INTF_SYSFS_MODULE) |
471 | ||
7520b94d AZ |
472 | static ssize_t rs5c372_sysfs_show_trim(struct device *dev, |
473 | struct device_attribute *attr, char *buf) | |
474 | { | |
82896072 | 475 | int err, trim; |
7520b94d | 476 | |
82896072 AZ |
477 | err = rs5c372_get_trim(to_i2c_client(dev), NULL, &trim); |
478 | if (err) | |
479 | return err; | |
7520b94d | 480 | |
cb26b572 | 481 | return sprintf(buf, "%d\n", trim); |
7520b94d AZ |
482 | } |
483 | static DEVICE_ATTR(trim, S_IRUGO, rs5c372_sysfs_show_trim, NULL); | |
484 | ||
485 | static ssize_t rs5c372_sysfs_show_osc(struct device *dev, | |
486 | struct device_attribute *attr, char *buf) | |
487 | { | |
82896072 | 488 | int err, osc; |
7520b94d | 489 | |
82896072 AZ |
490 | err = rs5c372_get_trim(to_i2c_client(dev), &osc, NULL); |
491 | if (err) | |
492 | return err; | |
7520b94d | 493 | |
82896072 | 494 | return sprintf(buf, "%d.%03d KHz\n", osc / 1000, osc % 1000); |
7520b94d AZ |
495 | } |
496 | static DEVICE_ATTR(osc, S_IRUGO, rs5c372_sysfs_show_osc, NULL); | |
497 | ||
cb26b572 | 498 | static int rs5c_sysfs_register(struct device *dev) |
7520b94d | 499 | { |
cb26b572 DB |
500 | int err; |
501 | ||
502 | err = device_create_file(dev, &dev_attr_trim); | |
503 | if (err) | |
504 | return err; | |
505 | err = device_create_file(dev, &dev_attr_osc); | |
506 | if (err) | |
507 | device_remove_file(dev, &dev_attr_trim); | |
508 | ||
509 | return err; | |
510 | } | |
511 | ||
d815461c DB |
512 | static void rs5c_sysfs_unregister(struct device *dev) |
513 | { | |
514 | device_remove_file(dev, &dev_attr_trim); | |
515 | device_remove_file(dev, &dev_attr_osc); | |
516 | } | |
517 | ||
cb26b572 DB |
518 | #else |
519 | static int rs5c_sysfs_register(struct device *dev) | |
520 | { | |
521 | return 0; | |
7520b94d | 522 | } |
d815461c DB |
523 | |
524 | static void rs5c_sysfs_unregister(struct device *dev) | |
525 | { | |
526 | /* nothing */ | |
527 | } | |
cb26b572 DB |
528 | #endif /* SYSFS */ |
529 | ||
530 | static struct i2c_driver rs5c372_driver; | |
7520b94d | 531 | |
0053dc0d PM |
532 | static int rs5c_oscillator_setup(struct rs5c372 *rs5c372) |
533 | { | |
534 | unsigned char buf[2]; | |
535 | int addr, i, ret = 0; | |
536 | ||
37fc5e2c PM |
537 | if (rs5c372->type == rtc_r2025sd) { |
538 | if (!(rs5c372->regs[RS5C_REG_CTRL2] & R2025_CTRL2_XST)) | |
539 | return ret; | |
540 | rs5c372->regs[RS5C_REG_CTRL2] &= ~R2025_CTRL2_XST; | |
541 | } else { | |
542 | if (!(rs5c372->regs[RS5C_REG_CTRL2] & RS5C_CTRL2_XSTP)) | |
543 | return ret; | |
544 | rs5c372->regs[RS5C_REG_CTRL2] &= ~RS5C_CTRL2_XSTP; | |
545 | } | |
0053dc0d PM |
546 | |
547 | addr = RS5C_ADDR(RS5C_REG_CTRL1); | |
548 | buf[0] = rs5c372->regs[RS5C_REG_CTRL1]; | |
549 | buf[1] = rs5c372->regs[RS5C_REG_CTRL2]; | |
550 | ||
551 | /* use 24hr mode */ | |
552 | switch (rs5c372->type) { | |
553 | case rtc_rs5c372a: | |
554 | case rtc_rs5c372b: | |
555 | buf[1] |= RS5C372_CTRL2_24; | |
556 | rs5c372->time24 = 1; | |
557 | break; | |
37fc5e2c | 558 | case rtc_r2025sd: |
0053dc0d PM |
559 | case rtc_rv5c386: |
560 | case rtc_rv5c387a: | |
561 | buf[0] |= RV5C387_CTRL1_24; | |
562 | rs5c372->time24 = 1; | |
563 | break; | |
564 | default: | |
565 | /* impossible */ | |
566 | break; | |
567 | } | |
568 | ||
569 | for (i = 0; i < sizeof(buf); i++) { | |
570 | addr = RS5C_ADDR(RS5C_REG_CTRL1 + i); | |
571 | ret = i2c_smbus_write_byte_data(rs5c372->client, addr, buf[i]); | |
572 | if (unlikely(ret < 0)) | |
573 | return ret; | |
574 | } | |
575 | ||
576 | rs5c372->regs[RS5C_REG_CTRL1] = buf[0]; | |
577 | rs5c372->regs[RS5C_REG_CTRL2] = buf[1]; | |
578 | ||
579 | return 0; | |
580 | } | |
581 | ||
d2653e92 JD |
582 | static int rs5c372_probe(struct i2c_client *client, |
583 | const struct i2c_device_id *id) | |
7520b94d AZ |
584 | { |
585 | int err = 0; | |
0053dc0d | 586 | int smbus_mode = 0; |
c6f24f99 | 587 | struct rs5c372 *rs5c372; |
cb26b572 | 588 | struct rtc_time tm; |
7520b94d | 589 | |
2a4e2b87 | 590 | dev_dbg(&client->dev, "%s\n", __func__); |
7520b94d | 591 | |
0053dc0d PM |
592 | if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C | |
593 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_I2C_BLOCK)) { | |
594 | /* | |
595 | * If we don't have any master mode adapter, try breaking | |
596 | * it down in to the barest of capabilities. | |
597 | */ | |
598 | if (i2c_check_functionality(client->adapter, | |
599 | I2C_FUNC_SMBUS_BYTE_DATA | | |
600 | I2C_FUNC_SMBUS_I2C_BLOCK)) | |
601 | smbus_mode = 1; | |
602 | else { | |
603 | /* Still no good, give up */ | |
604 | err = -ENODEV; | |
605 | goto exit; | |
606 | } | |
7520b94d AZ |
607 | } |
608 | ||
c6f24f99 | 609 | if (!(rs5c372 = kzalloc(sizeof(struct rs5c372), GFP_KERNEL))) { |
7520b94d AZ |
610 | err = -ENOMEM; |
611 | goto exit; | |
612 | } | |
cb26b572 | 613 | |
cb26b572 | 614 | rs5c372->client = client; |
c6f24f99 | 615 | i2c_set_clientdata(client, rs5c372); |
3760f736 | 616 | rs5c372->type = id->driver_data; |
c6f24f99 | 617 | |
e2bfe342 PM |
618 | /* we read registers 0x0f then 0x00-0x0f; skip the first one */ |
619 | rs5c372->regs = &rs5c372->buf[1]; | |
0053dc0d | 620 | rs5c372->smbus = smbus_mode; |
e2bfe342 | 621 | |
cb26b572 DB |
622 | err = rs5c_get_regs(rs5c372); |
623 | if (err < 0) | |
d815461c | 624 | goto exit_kfree; |
cb26b572 | 625 | |
cb26b572 DB |
626 | /* clock may be set for am/pm or 24 hr time */ |
627 | switch (rs5c372->type) { | |
628 | case rtc_rs5c372a: | |
629 | case rtc_rs5c372b: | |
630 | /* alarm uses ALARM_A; and nINTRA on 372a, nINTR on 372b. | |
631 | * so does periodic irq, except some 327a modes. | |
632 | */ | |
633 | if (rs5c372->regs[RS5C_REG_CTRL2] & RS5C372_CTRL2_24) | |
634 | rs5c372->time24 = 1; | |
635 | break; | |
37fc5e2c | 636 | case rtc_r2025sd: |
cb26b572 DB |
637 | case rtc_rv5c386: |
638 | case rtc_rv5c387a: | |
639 | if (rs5c372->regs[RS5C_REG_CTRL1] & RV5C387_CTRL1_24) | |
640 | rs5c372->time24 = 1; | |
641 | /* alarm uses ALARM_W; and nINTRB for alarm and periodic | |
642 | * irq, on both 386 and 387 | |
643 | */ | |
644 | break; | |
645 | default: | |
646 | dev_err(&client->dev, "unknown RTC type\n"); | |
d815461c | 647 | goto exit_kfree; |
cb26b572 DB |
648 | } |
649 | ||
650 | /* if the oscillator lost power and no other software (like | |
651 | * the bootloader) set it up, do it here. | |
37fc5e2c PM |
652 | * |
653 | * The R2025S/D does this a little differently than the other | |
654 | * parts, so we special case that.. | |
cb26b572 | 655 | */ |
0053dc0d PM |
656 | err = rs5c_oscillator_setup(rs5c372); |
657 | if (unlikely(err < 0)) { | |
658 | dev_err(&client->dev, "setup error\n"); | |
659 | goto exit_kfree; | |
cb26b572 DB |
660 | } |
661 | ||
662 | if (rs5c372_get_datetime(client, &tm) < 0) | |
663 | dev_warn(&client->dev, "clock needs to be set\n"); | |
664 | ||
665 | dev_info(&client->dev, "%s found, %s, driver version " DRV_VERSION "\n", | |
666 | ({ char *s; switch (rs5c372->type) { | |
37fc5e2c | 667 | case rtc_r2025sd: s = "r2025sd"; break; |
cb26b572 DB |
668 | case rtc_rs5c372a: s = "rs5c372a"; break; |
669 | case rtc_rs5c372b: s = "rs5c372b"; break; | |
670 | case rtc_rv5c386: s = "rv5c386"; break; | |
671 | case rtc_rv5c387a: s = "rv5c387a"; break; | |
672 | default: s = "chip"; break; | |
673 | }; s;}), | |
674 | rs5c372->time24 ? "24hr" : "am/pm" | |
675 | ); | |
676 | ||
d815461c | 677 | /* REVISIT use client->irq to register alarm irq ... */ |
7520b94d | 678 | |
c6f24f99 RV |
679 | rs5c372->rtc = rtc_device_register(rs5c372_driver.driver.name, |
680 | &client->dev, &rs5c372_rtc_ops, THIS_MODULE); | |
7520b94d | 681 | |
c6f24f99 RV |
682 | if (IS_ERR(rs5c372->rtc)) { |
683 | err = PTR_ERR(rs5c372->rtc); | |
d815461c | 684 | goto exit_kfree; |
7520b94d AZ |
685 | } |
686 | ||
cb26b572 | 687 | err = rs5c_sysfs_register(&client->dev); |
c6f24f99 RV |
688 | if (err) |
689 | goto exit_devreg; | |
7520b94d AZ |
690 | |
691 | return 0; | |
692 | ||
91046a8a | 693 | exit_devreg: |
c6f24f99 | 694 | rtc_device_unregister(rs5c372->rtc); |
91046a8a | 695 | |
7520b94d | 696 | exit_kfree: |
c6f24f99 | 697 | kfree(rs5c372); |
7520b94d AZ |
698 | |
699 | exit: | |
700 | return err; | |
701 | } | |
702 | ||
d815461c | 703 | static int rs5c372_remove(struct i2c_client *client) |
cb26b572 | 704 | { |
c6f24f99 | 705 | struct rs5c372 *rs5c372 = i2c_get_clientdata(client); |
7520b94d | 706 | |
d815461c DB |
707 | rtc_device_unregister(rs5c372->rtc); |
708 | rs5c_sysfs_unregister(&client->dev); | |
c6f24f99 | 709 | kfree(rs5c372); |
7520b94d AZ |
710 | return 0; |
711 | } | |
712 | ||
cb26b572 DB |
713 | static struct i2c_driver rs5c372_driver = { |
714 | .driver = { | |
715 | .name = "rtc-rs5c372", | |
716 | }, | |
d815461c DB |
717 | .probe = rs5c372_probe, |
718 | .remove = rs5c372_remove, | |
3760f736 | 719 | .id_table = rs5c372_id, |
cb26b572 DB |
720 | }; |
721 | ||
7520b94d AZ |
722 | static __init int rs5c372_init(void) |
723 | { | |
724 | return i2c_add_driver(&rs5c372_driver); | |
725 | } | |
726 | ||
727 | static __exit void rs5c372_exit(void) | |
728 | { | |
729 | i2c_del_driver(&rs5c372_driver); | |
730 | } | |
731 | ||
732 | module_init(rs5c372_init); | |
733 | module_exit(rs5c372_exit); | |
734 | ||
735 | MODULE_AUTHOR( | |
736 | "Pavel Mironchik <pmironchik@optifacio.net>, " | |
0053dc0d PM |
737 | "Alessandro Zummo <a.zummo@towertech.it>, " |
738 | "Paul Mundt <lethal@linux-sh.org>"); | |
7520b94d AZ |
739 | MODULE_DESCRIPTION("Ricoh RS5C372 RTC driver"); |
740 | MODULE_LICENSE("GPL"); | |
741 | MODULE_VERSION(DRV_VERSION); |