Commit | Line | Data |
---|---|---|
7520b94d | 1 | /* |
37fc5e2c | 2 | * An I2C driver for Ricoh RS5C372, R2025S/D and RV5C38[67] RTCs |
7520b94d AZ |
3 | * |
4 | * Copyright (C) 2005 Pavel Mironchik <pmironchik@optifacio.net> | |
5 | * Copyright (C) 2006 Tower Technologies | |
0053dc0d | 6 | * Copyright (C) 2008 Paul Mundt |
7520b94d AZ |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/i2c.h> | |
14 | #include <linux/rtc.h> | |
15 | #include <linux/bcd.h> | |
5a0e3ad6 | 16 | #include <linux/slab.h> |
2113852b | 17 | #include <linux/module.h> |
7520b94d | 18 | |
cb26b572 DB |
19 | /* |
20 | * Ricoh has a family of I2C based RTCs, which differ only slightly from | |
21 | * each other. Differences center on pinout (e.g. how many interrupts, | |
22 | * output clock, etc) and how the control registers are used. The '372 | |
23 | * is significant only because that's the one this driver first supported. | |
24 | */ | |
7520b94d AZ |
25 | #define RS5C372_REG_SECS 0 |
26 | #define RS5C372_REG_MINS 1 | |
27 | #define RS5C372_REG_HOURS 2 | |
28 | #define RS5C372_REG_WDAY 3 | |
29 | #define RS5C372_REG_DAY 4 | |
30 | #define RS5C372_REG_MONTH 5 | |
31 | #define RS5C372_REG_YEAR 6 | |
32 | #define RS5C372_REG_TRIM 7 | |
cb26b572 DB |
33 | # define RS5C372_TRIM_XSL 0x80 |
34 | # define RS5C372_TRIM_MASK 0x7F | |
35 | ||
36 | #define RS5C_REG_ALARM_A_MIN 8 /* or ALARM_W */ | |
37 | #define RS5C_REG_ALARM_A_HOURS 9 | |
38 | #define RS5C_REG_ALARM_A_WDAY 10 | |
39 | ||
40 | #define RS5C_REG_ALARM_B_MIN 11 /* or ALARM_D */ | |
41 | #define RS5C_REG_ALARM_B_HOURS 12 | |
42 | #define RS5C_REG_ALARM_B_WDAY 13 /* (ALARM_B only) */ | |
43 | ||
44 | #define RS5C_REG_CTRL1 14 | |
45 | # define RS5C_CTRL1_AALE (1 << 7) /* or WALE */ | |
46 | # define RS5C_CTRL1_BALE (1 << 6) /* or DALE */ | |
47 | # define RV5C387_CTRL1_24 (1 << 5) | |
48 | # define RS5C372A_CTRL1_SL1 (1 << 5) | |
49 | # define RS5C_CTRL1_CT_MASK (7 << 0) | |
50 | # define RS5C_CTRL1_CT0 (0 << 0) /* no periodic irq */ | |
51 | # define RS5C_CTRL1_CT4 (4 << 0) /* 1 Hz level irq */ | |
52 | #define RS5C_REG_CTRL2 15 | |
53 | # define RS5C372_CTRL2_24 (1 << 5) | |
37fc5e2c PM |
54 | # define R2025_CTRL2_XST (1 << 5) |
55 | # define RS5C_CTRL2_XSTP (1 << 4) /* only if !R2025S/D */ | |
cb26b572 DB |
56 | # define RS5C_CTRL2_CTFG (1 << 2) |
57 | # define RS5C_CTRL2_AAFG (1 << 1) /* or WAFG */ | |
58 | # define RS5C_CTRL2_BAFG (1 << 0) /* or DAFG */ | |
59 | ||
60 | ||
61 | /* to read (style 1) or write registers starting at R */ | |
62 | #define RS5C_ADDR(R) (((R) << 4) | 0) | |
63 | ||
64 | ||
65 | enum rtc_type { | |
66 | rtc_undef = 0, | |
37fc5e2c | 67 | rtc_r2025sd, |
550fcb8f | 68 | rtc_r2221tl, |
cb26b572 DB |
69 | rtc_rs5c372a, |
70 | rtc_rs5c372b, | |
71 | rtc_rv5c386, | |
72 | rtc_rv5c387a, | |
73 | }; | |
7520b94d | 74 | |
3760f736 | 75 | static const struct i2c_device_id rs5c372_id[] = { |
37fc5e2c | 76 | { "r2025sd", rtc_r2025sd }, |
550fcb8f | 77 | { "r2221tl", rtc_r2221tl }, |
3760f736 JD |
78 | { "rs5c372a", rtc_rs5c372a }, |
79 | { "rs5c372b", rtc_rs5c372b }, | |
80 | { "rv5c386", rtc_rv5c386 }, | |
81 | { "rv5c387a", rtc_rv5c387a }, | |
82 | { } | |
83 | }; | |
84 | MODULE_DEVICE_TABLE(i2c, rs5c372_id); | |
85 | ||
cb26b572 DB |
86 | /* REVISIT: this assumes that: |
87 | * - we're in the 21st century, so it's safe to ignore the century | |
88 | * bit for rv5c38[67] (REG_MONTH bit 7); | |
89 | * - we should use ALARM_A not ALARM_B (may be wrong on some boards) | |
90 | */ | |
91 | struct rs5c372 { | |
92 | struct i2c_client *client; | |
93 | struct rtc_device *rtc; | |
94 | enum rtc_type type; | |
95 | unsigned time24:1; | |
96 | unsigned has_irq:1; | |
0053dc0d | 97 | unsigned smbus:1; |
cb26b572 DB |
98 | char buf[17]; |
99 | char *regs; | |
cb26b572 | 100 | }; |
7520b94d | 101 | |
cb26b572 DB |
102 | static int rs5c_get_regs(struct rs5c372 *rs5c) |
103 | { | |
104 | struct i2c_client *client = rs5c->client; | |
105 | struct i2c_msg msgs[] = { | |
a606757f S |
106 | { |
107 | .addr = client->addr, | |
108 | .flags = I2C_M_RD, | |
109 | .len = sizeof(rs5c->buf), | |
110 | .buf = rs5c->buf | |
111 | }, | |
cb26b572 DB |
112 | }; |
113 | ||
114 | /* This implements the third reading method from the datasheet, using | |
115 | * an internal address that's reset after each transaction (by STOP) | |
116 | * to 0x0f ... so we read extra registers, and skip the first one. | |
117 | * | |
118 | * The first method doesn't work with the iop3xx adapter driver, on at | |
119 | * least 80219 chips; this works around that bug. | |
0053dc0d PM |
120 | * |
121 | * The third method on the other hand doesn't work for the SMBus-only | |
122 | * configurations, so we use the the first method there, stripping off | |
123 | * the extra register in the process. | |
cb26b572 | 124 | */ |
0053dc0d PM |
125 | if (rs5c->smbus) { |
126 | int addr = RS5C_ADDR(RS5C372_REG_SECS); | |
127 | int size = sizeof(rs5c->buf) - 1; | |
128 | ||
129 | if (i2c_smbus_read_i2c_block_data(client, addr, size, | |
130 | rs5c->buf + 1) != size) { | |
131 | dev_warn(&client->dev, "can't read registers\n"); | |
132 | return -EIO; | |
133 | } | |
134 | } else { | |
135 | if ((i2c_transfer(client->adapter, msgs, 1)) != 1) { | |
136 | dev_warn(&client->dev, "can't read registers\n"); | |
137 | return -EIO; | |
138 | } | |
cb26b572 | 139 | } |
7520b94d | 140 | |
cb26b572 | 141 | dev_dbg(&client->dev, |
b513e522 AS |
142 | "%3ph (%02x) %3ph (%02x), %3ph, %3ph; %02x %02x\n", |
143 | rs5c->regs + 0, rs5c->regs[3], | |
144 | rs5c->regs + 4, rs5c->regs[7], | |
145 | rs5c->regs + 8, rs5c->regs + 11, | |
146 | rs5c->regs[14], rs5c->regs[15]); | |
7520b94d | 147 | |
cb26b572 DB |
148 | return 0; |
149 | } | |
c6f24f99 | 150 | |
cb26b572 DB |
151 | static unsigned rs5c_reg2hr(struct rs5c372 *rs5c, unsigned reg) |
152 | { | |
153 | unsigned hour; | |
7520b94d | 154 | |
cb26b572 | 155 | if (rs5c->time24) |
fe20ba70 | 156 | return bcd2bin(reg & 0x3f); |
cb26b572 | 157 | |
fe20ba70 | 158 | hour = bcd2bin(reg & 0x1f); |
cb26b572 DB |
159 | if (hour == 12) |
160 | hour = 0; | |
161 | if (reg & 0x20) | |
162 | hour += 12; | |
163 | return hour; | |
164 | } | |
165 | ||
166 | static unsigned rs5c_hr2reg(struct rs5c372 *rs5c, unsigned hour) | |
7520b94d | 167 | { |
cb26b572 | 168 | if (rs5c->time24) |
fe20ba70 | 169 | return bin2bcd(hour); |
cb26b572 DB |
170 | |
171 | if (hour > 12) | |
fe20ba70 | 172 | return 0x20 | bin2bcd(hour - 12); |
cb26b572 | 173 | if (hour == 12) |
fe20ba70 | 174 | return 0x20 | bin2bcd(12); |
cb26b572 | 175 | if (hour == 0) |
fe20ba70 AB |
176 | return bin2bcd(12); |
177 | return bin2bcd(hour); | |
cb26b572 | 178 | } |
7520b94d | 179 | |
cb26b572 DB |
180 | static int rs5c372_get_datetime(struct i2c_client *client, struct rtc_time *tm) |
181 | { | |
182 | struct rs5c372 *rs5c = i2c_get_clientdata(client); | |
183 | int status = rs5c_get_regs(rs5c); | |
c6f24f99 | 184 | |
cb26b572 DB |
185 | if (status < 0) |
186 | return status; | |
7520b94d | 187 | |
fe20ba70 AB |
188 | tm->tm_sec = bcd2bin(rs5c->regs[RS5C372_REG_SECS] & 0x7f); |
189 | tm->tm_min = bcd2bin(rs5c->regs[RS5C372_REG_MINS] & 0x7f); | |
cb26b572 | 190 | tm->tm_hour = rs5c_reg2hr(rs5c, rs5c->regs[RS5C372_REG_HOURS]); |
7520b94d | 191 | |
fe20ba70 AB |
192 | tm->tm_wday = bcd2bin(rs5c->regs[RS5C372_REG_WDAY] & 0x07); |
193 | tm->tm_mday = bcd2bin(rs5c->regs[RS5C372_REG_DAY] & 0x3f); | |
7520b94d AZ |
194 | |
195 | /* tm->tm_mon is zero-based */ | |
fe20ba70 | 196 | tm->tm_mon = bcd2bin(rs5c->regs[RS5C372_REG_MONTH] & 0x1f) - 1; |
7520b94d AZ |
197 | |
198 | /* year is 1900 + tm->tm_year */ | |
fe20ba70 | 199 | tm->tm_year = bcd2bin(rs5c->regs[RS5C372_REG_YEAR]) + 100; |
7520b94d AZ |
200 | |
201 | dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d, " | |
202 | "mday=%d, mon=%d, year=%d, wday=%d\n", | |
2a4e2b87 | 203 | __func__, |
7520b94d AZ |
204 | tm->tm_sec, tm->tm_min, tm->tm_hour, |
205 | tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); | |
206 | ||
cb26b572 DB |
207 | /* rtc might need initialization */ |
208 | return rtc_valid_tm(tm); | |
7520b94d AZ |
209 | } |
210 | ||
211 | static int rs5c372_set_datetime(struct i2c_client *client, struct rtc_time *tm) | |
212 | { | |
cb26b572 | 213 | struct rs5c372 *rs5c = i2c_get_clientdata(client); |
11836494 | 214 | unsigned char buf[7]; |
0053dc0d | 215 | int addr; |
7520b94d | 216 | |
cb26b572 | 217 | dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d " |
7520b94d | 218 | "mday=%d, mon=%d, year=%d, wday=%d\n", |
2a4e2b87 | 219 | __func__, |
cb26b572 | 220 | tm->tm_sec, tm->tm_min, tm->tm_hour, |
7520b94d AZ |
221 | tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); |
222 | ||
0053dc0d | 223 | addr = RS5C_ADDR(RS5C372_REG_SECS); |
fe20ba70 AB |
224 | buf[0] = bin2bcd(tm->tm_sec); |
225 | buf[1] = bin2bcd(tm->tm_min); | |
0053dc0d | 226 | buf[2] = rs5c_hr2reg(rs5c, tm->tm_hour); |
fe20ba70 AB |
227 | buf[3] = bin2bcd(tm->tm_wday); |
228 | buf[4] = bin2bcd(tm->tm_mday); | |
229 | buf[5] = bin2bcd(tm->tm_mon + 1); | |
230 | buf[6] = bin2bcd(tm->tm_year - 100); | |
7520b94d | 231 | |
0053dc0d | 232 | if (i2c_smbus_write_i2c_block_data(client, addr, sizeof(buf), buf) < 0) { |
2a4e2b87 | 233 | dev_err(&client->dev, "%s: write error\n", __func__); |
7520b94d AZ |
234 | return -EIO; |
235 | } | |
236 | ||
237 | return 0; | |
238 | } | |
239 | ||
6fca3fc5 | 240 | #if IS_ENABLED(CONFIG_RTC_INTF_PROC) |
cb26b572 DB |
241 | #define NEED_TRIM |
242 | #endif | |
243 | ||
6fca3fc5 | 244 | #if IS_ENABLED(CONFIG_RTC_INTF_SYSFS) |
cb26b572 DB |
245 | #define NEED_TRIM |
246 | #endif | |
247 | ||
248 | #ifdef NEED_TRIM | |
7520b94d AZ |
249 | static int rs5c372_get_trim(struct i2c_client *client, int *osc, int *trim) |
250 | { | |
c6f24f99 | 251 | struct rs5c372 *rs5c372 = i2c_get_clientdata(client); |
cb26b572 | 252 | u8 tmp = rs5c372->regs[RS5C372_REG_TRIM]; |
7520b94d | 253 | |
7520b94d | 254 | if (osc) |
c6f24f99 | 255 | *osc = (tmp & RS5C372_TRIM_XSL) ? 32000 : 32768; |
7520b94d | 256 | |
17ad78e5 | 257 | if (trim) { |
2a4e2b87 | 258 | dev_dbg(&client->dev, "%s: raw trim=%x\n", __func__, tmp); |
cb26b572 DB |
259 | tmp &= RS5C372_TRIM_MASK; |
260 | if (tmp & 0x3e) { | |
261 | int t = tmp & 0x3f; | |
262 | ||
263 | if (tmp & 0x40) | |
264 | t = (~t | (s8)0xc0) + 1; | |
265 | else | |
266 | t = t - 1; | |
267 | ||
268 | tmp = t * 2; | |
269 | } else | |
270 | tmp = 0; | |
271 | *trim = tmp; | |
17ad78e5 | 272 | } |
7520b94d AZ |
273 | |
274 | return 0; | |
275 | } | |
cb26b572 | 276 | #endif |
7520b94d AZ |
277 | |
278 | static int rs5c372_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
279 | { | |
280 | return rs5c372_get_datetime(to_i2c_client(dev), tm); | |
281 | } | |
282 | ||
283 | static int rs5c372_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
284 | { | |
285 | return rs5c372_set_datetime(to_i2c_client(dev), tm); | |
286 | } | |
287 | ||
cb26b572 | 288 | |
16380c15 JS |
289 | static int rs5c_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
290 | { | |
291 | struct i2c_client *client = to_i2c_client(dev); | |
292 | struct rs5c372 *rs5c = i2c_get_clientdata(client); | |
293 | unsigned char buf; | |
294 | int status, addr; | |
295 | ||
296 | buf = rs5c->regs[RS5C_REG_CTRL1]; | |
297 | ||
298 | if (!rs5c->has_irq) | |
299 | return -EINVAL; | |
300 | ||
301 | status = rs5c_get_regs(rs5c); | |
302 | if (status < 0) | |
303 | return status; | |
304 | ||
305 | addr = RS5C_ADDR(RS5C_REG_CTRL1); | |
306 | if (enabled) | |
307 | buf |= RS5C_CTRL1_AALE; | |
308 | else | |
309 | buf &= ~RS5C_CTRL1_AALE; | |
310 | ||
311 | if (i2c_smbus_write_byte_data(client, addr, buf) < 0) { | |
0c6516ea | 312 | dev_warn(dev, "can't update alarm\n"); |
16380c15 JS |
313 | status = -EIO; |
314 | } else | |
315 | rs5c->regs[RS5C_REG_CTRL1] = buf; | |
316 | ||
317 | return status; | |
318 | } | |
319 | ||
320 | ||
cb26b572 DB |
321 | /* NOTE: Since RTC_WKALM_{RD,SET} were originally defined for EFI, |
322 | * which only exposes a polled programming interface; and since | |
323 | * these calls map directly to those EFI requests; we don't demand | |
324 | * we have an IRQ for this chip when we go through this API. | |
325 | * | |
326 | * The older x86_pc derived RTC_ALM_{READ,SET} calls require irqs | |
327 | * though, managed through RTC_AIE_{ON,OFF} requests. | |
328 | */ | |
329 | ||
330 | static int rs5c_read_alarm(struct device *dev, struct rtc_wkalrm *t) | |
331 | { | |
332 | struct i2c_client *client = to_i2c_client(dev); | |
333 | struct rs5c372 *rs5c = i2c_get_clientdata(client); | |
334 | int status; | |
335 | ||
336 | status = rs5c_get_regs(rs5c); | |
337 | if (status < 0) | |
338 | return status; | |
339 | ||
340 | /* report alarm time */ | |
341 | t->time.tm_sec = 0; | |
fe20ba70 | 342 | t->time.tm_min = bcd2bin(rs5c->regs[RS5C_REG_ALARM_A_MIN] & 0x7f); |
cb26b572 DB |
343 | t->time.tm_hour = rs5c_reg2hr(rs5c, rs5c->regs[RS5C_REG_ALARM_A_HOURS]); |
344 | t->time.tm_mday = -1; | |
345 | t->time.tm_mon = -1; | |
346 | t->time.tm_year = -1; | |
347 | t->time.tm_wday = -1; | |
348 | t->time.tm_yday = -1; | |
349 | t->time.tm_isdst = -1; | |
350 | ||
351 | /* ... and status */ | |
352 | t->enabled = !!(rs5c->regs[RS5C_REG_CTRL1] & RS5C_CTRL1_AALE); | |
353 | t->pending = !!(rs5c->regs[RS5C_REG_CTRL2] & RS5C_CTRL2_AAFG); | |
354 | ||
355 | return 0; | |
356 | } | |
357 | ||
358 | static int rs5c_set_alarm(struct device *dev, struct rtc_wkalrm *t) | |
359 | { | |
360 | struct i2c_client *client = to_i2c_client(dev); | |
361 | struct rs5c372 *rs5c = i2c_get_clientdata(client); | |
0053dc0d PM |
362 | int status, addr, i; |
363 | unsigned char buf[3]; | |
cb26b572 DB |
364 | |
365 | /* only handle up to 24 hours in the future, like RTC_ALM_SET */ | |
366 | if (t->time.tm_mday != -1 | |
367 | || t->time.tm_mon != -1 | |
368 | || t->time.tm_year != -1) | |
369 | return -EINVAL; | |
370 | ||
371 | /* REVISIT: round up tm_sec */ | |
372 | ||
373 | /* if needed, disable irq (clears pending status) */ | |
374 | status = rs5c_get_regs(rs5c); | |
375 | if (status < 0) | |
376 | return status; | |
377 | if (rs5c->regs[RS5C_REG_CTRL1] & RS5C_CTRL1_AALE) { | |
0053dc0d PM |
378 | addr = RS5C_ADDR(RS5C_REG_CTRL1); |
379 | buf[0] = rs5c->regs[RS5C_REG_CTRL1] & ~RS5C_CTRL1_AALE; | |
380 | if (i2c_smbus_write_byte_data(client, addr, buf[0]) < 0) { | |
0c6516ea | 381 | dev_dbg(dev, "can't disable alarm\n"); |
cb26b572 DB |
382 | return -EIO; |
383 | } | |
0053dc0d | 384 | rs5c->regs[RS5C_REG_CTRL1] = buf[0]; |
cb26b572 DB |
385 | } |
386 | ||
387 | /* set alarm */ | |
fe20ba70 | 388 | buf[0] = bin2bcd(t->time.tm_min); |
0053dc0d PM |
389 | buf[1] = rs5c_hr2reg(rs5c, t->time.tm_hour); |
390 | buf[2] = 0x7f; /* any/all days */ | |
391 | ||
392 | for (i = 0; i < sizeof(buf); i++) { | |
393 | addr = RS5C_ADDR(RS5C_REG_ALARM_A_MIN + i); | |
394 | if (i2c_smbus_write_byte_data(client, addr, buf[i]) < 0) { | |
0c6516ea | 395 | dev_dbg(dev, "can't set alarm time\n"); |
0053dc0d PM |
396 | return -EIO; |
397 | } | |
cb26b572 DB |
398 | } |
399 | ||
400 | /* ... and maybe enable its irq */ | |
401 | if (t->enabled) { | |
0053dc0d PM |
402 | addr = RS5C_ADDR(RS5C_REG_CTRL1); |
403 | buf[0] = rs5c->regs[RS5C_REG_CTRL1] | RS5C_CTRL1_AALE; | |
404 | if (i2c_smbus_write_byte_data(client, addr, buf[0]) < 0) | |
0c6516ea | 405 | dev_warn(dev, "can't enable alarm\n"); |
0053dc0d | 406 | rs5c->regs[RS5C_REG_CTRL1] = buf[0]; |
cb26b572 DB |
407 | } |
408 | ||
409 | return 0; | |
410 | } | |
411 | ||
6fca3fc5 | 412 | #if IS_ENABLED(CONFIG_RTC_INTF_PROC) |
cb26b572 | 413 | |
7520b94d AZ |
414 | static int rs5c372_rtc_proc(struct device *dev, struct seq_file *seq) |
415 | { | |
416 | int err, osc, trim; | |
417 | ||
adfb4341 AZ |
418 | err = rs5c372_get_trim(to_i2c_client(dev), &osc, &trim); |
419 | if (err == 0) { | |
cb26b572 DB |
420 | seq_printf(seq, "crystal\t\t: %d.%03d KHz\n", |
421 | osc / 1000, osc % 1000); | |
422 | seq_printf(seq, "trim\t\t: %d\n", trim); | |
7520b94d AZ |
423 | } |
424 | ||
425 | return 0; | |
426 | } | |
427 | ||
cb26b572 DB |
428 | #else |
429 | #define rs5c372_rtc_proc NULL | |
430 | #endif | |
431 | ||
ff8371ac | 432 | static const struct rtc_class_ops rs5c372_rtc_ops = { |
7520b94d AZ |
433 | .proc = rs5c372_rtc_proc, |
434 | .read_time = rs5c372_rtc_read_time, | |
435 | .set_time = rs5c372_rtc_set_time, | |
cb26b572 DB |
436 | .read_alarm = rs5c_read_alarm, |
437 | .set_alarm = rs5c_set_alarm, | |
16380c15 | 438 | .alarm_irq_enable = rs5c_rtc_alarm_irq_enable, |
7520b94d AZ |
439 | }; |
440 | ||
6fca3fc5 | 441 | #if IS_ENABLED(CONFIG_RTC_INTF_SYSFS) |
cb26b572 | 442 | |
7520b94d AZ |
443 | static ssize_t rs5c372_sysfs_show_trim(struct device *dev, |
444 | struct device_attribute *attr, char *buf) | |
445 | { | |
82896072 | 446 | int err, trim; |
7520b94d | 447 | |
82896072 AZ |
448 | err = rs5c372_get_trim(to_i2c_client(dev), NULL, &trim); |
449 | if (err) | |
450 | return err; | |
7520b94d | 451 | |
cb26b572 | 452 | return sprintf(buf, "%d\n", trim); |
7520b94d AZ |
453 | } |
454 | static DEVICE_ATTR(trim, S_IRUGO, rs5c372_sysfs_show_trim, NULL); | |
455 | ||
456 | static ssize_t rs5c372_sysfs_show_osc(struct device *dev, | |
457 | struct device_attribute *attr, char *buf) | |
458 | { | |
82896072 | 459 | int err, osc; |
7520b94d | 460 | |
82896072 AZ |
461 | err = rs5c372_get_trim(to_i2c_client(dev), &osc, NULL); |
462 | if (err) | |
463 | return err; | |
7520b94d | 464 | |
82896072 | 465 | return sprintf(buf, "%d.%03d KHz\n", osc / 1000, osc % 1000); |
7520b94d AZ |
466 | } |
467 | static DEVICE_ATTR(osc, S_IRUGO, rs5c372_sysfs_show_osc, NULL); | |
468 | ||
cb26b572 | 469 | static int rs5c_sysfs_register(struct device *dev) |
7520b94d | 470 | { |
cb26b572 DB |
471 | int err; |
472 | ||
473 | err = device_create_file(dev, &dev_attr_trim); | |
474 | if (err) | |
475 | return err; | |
476 | err = device_create_file(dev, &dev_attr_osc); | |
477 | if (err) | |
478 | device_remove_file(dev, &dev_attr_trim); | |
479 | ||
480 | return err; | |
481 | } | |
482 | ||
d815461c DB |
483 | static void rs5c_sysfs_unregister(struct device *dev) |
484 | { | |
485 | device_remove_file(dev, &dev_attr_trim); | |
486 | device_remove_file(dev, &dev_attr_osc); | |
487 | } | |
488 | ||
cb26b572 DB |
489 | #else |
490 | static int rs5c_sysfs_register(struct device *dev) | |
491 | { | |
492 | return 0; | |
7520b94d | 493 | } |
d815461c DB |
494 | |
495 | static void rs5c_sysfs_unregister(struct device *dev) | |
496 | { | |
497 | /* nothing */ | |
498 | } | |
cb26b572 DB |
499 | #endif /* SYSFS */ |
500 | ||
501 | static struct i2c_driver rs5c372_driver; | |
7520b94d | 502 | |
0053dc0d PM |
503 | static int rs5c_oscillator_setup(struct rs5c372 *rs5c372) |
504 | { | |
505 | unsigned char buf[2]; | |
506 | int addr, i, ret = 0; | |
507 | ||
37fc5e2c | 508 | if (rs5c372->type == rtc_r2025sd) { |
a9dbe558 | 509 | if (rs5c372->regs[RS5C_REG_CTRL2] & R2025_CTRL2_XST) |
37fc5e2c | 510 | return ret; |
a9dbe558 | 511 | rs5c372->regs[RS5C_REG_CTRL2] |= R2025_CTRL2_XST; |
37fc5e2c PM |
512 | } else { |
513 | if (!(rs5c372->regs[RS5C_REG_CTRL2] & RS5C_CTRL2_XSTP)) | |
514 | return ret; | |
515 | rs5c372->regs[RS5C_REG_CTRL2] &= ~RS5C_CTRL2_XSTP; | |
516 | } | |
0053dc0d PM |
517 | |
518 | addr = RS5C_ADDR(RS5C_REG_CTRL1); | |
519 | buf[0] = rs5c372->regs[RS5C_REG_CTRL1]; | |
520 | buf[1] = rs5c372->regs[RS5C_REG_CTRL2]; | |
521 | ||
522 | /* use 24hr mode */ | |
523 | switch (rs5c372->type) { | |
524 | case rtc_rs5c372a: | |
525 | case rtc_rs5c372b: | |
526 | buf[1] |= RS5C372_CTRL2_24; | |
527 | rs5c372->time24 = 1; | |
528 | break; | |
37fc5e2c | 529 | case rtc_r2025sd: |
550fcb8f | 530 | case rtc_r2221tl: |
0053dc0d PM |
531 | case rtc_rv5c386: |
532 | case rtc_rv5c387a: | |
533 | buf[0] |= RV5C387_CTRL1_24; | |
534 | rs5c372->time24 = 1; | |
535 | break; | |
536 | default: | |
537 | /* impossible */ | |
538 | break; | |
539 | } | |
540 | ||
541 | for (i = 0; i < sizeof(buf); i++) { | |
542 | addr = RS5C_ADDR(RS5C_REG_CTRL1 + i); | |
543 | ret = i2c_smbus_write_byte_data(rs5c372->client, addr, buf[i]); | |
544 | if (unlikely(ret < 0)) | |
545 | return ret; | |
546 | } | |
547 | ||
548 | rs5c372->regs[RS5C_REG_CTRL1] = buf[0]; | |
549 | rs5c372->regs[RS5C_REG_CTRL2] = buf[1]; | |
550 | ||
551 | return 0; | |
552 | } | |
553 | ||
d2653e92 JD |
554 | static int rs5c372_probe(struct i2c_client *client, |
555 | const struct i2c_device_id *id) | |
7520b94d AZ |
556 | { |
557 | int err = 0; | |
0053dc0d | 558 | int smbus_mode = 0; |
c6f24f99 | 559 | struct rs5c372 *rs5c372; |
cb26b572 | 560 | struct rtc_time tm; |
7520b94d | 561 | |
2a4e2b87 | 562 | dev_dbg(&client->dev, "%s\n", __func__); |
7520b94d | 563 | |
0053dc0d PM |
564 | if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C | |
565 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_I2C_BLOCK)) { | |
566 | /* | |
567 | * If we don't have any master mode adapter, try breaking | |
568 | * it down in to the barest of capabilities. | |
569 | */ | |
570 | if (i2c_check_functionality(client->adapter, | |
571 | I2C_FUNC_SMBUS_BYTE_DATA | | |
572 | I2C_FUNC_SMBUS_I2C_BLOCK)) | |
573 | smbus_mode = 1; | |
574 | else { | |
575 | /* Still no good, give up */ | |
576 | err = -ENODEV; | |
577 | goto exit; | |
578 | } | |
7520b94d AZ |
579 | } |
580 | ||
b8a4b4e2 JH |
581 | rs5c372 = devm_kzalloc(&client->dev, sizeof(struct rs5c372), |
582 | GFP_KERNEL); | |
583 | if (!rs5c372) { | |
7520b94d AZ |
584 | err = -ENOMEM; |
585 | goto exit; | |
586 | } | |
cb26b572 | 587 | |
cb26b572 | 588 | rs5c372->client = client; |
c6f24f99 | 589 | i2c_set_clientdata(client, rs5c372); |
3760f736 | 590 | rs5c372->type = id->driver_data; |
c6f24f99 | 591 | |
e2bfe342 PM |
592 | /* we read registers 0x0f then 0x00-0x0f; skip the first one */ |
593 | rs5c372->regs = &rs5c372->buf[1]; | |
0053dc0d | 594 | rs5c372->smbus = smbus_mode; |
e2bfe342 | 595 | |
cb26b572 DB |
596 | err = rs5c_get_regs(rs5c372); |
597 | if (err < 0) | |
b8a4b4e2 | 598 | goto exit; |
cb26b572 | 599 | |
cb26b572 DB |
600 | /* clock may be set for am/pm or 24 hr time */ |
601 | switch (rs5c372->type) { | |
602 | case rtc_rs5c372a: | |
603 | case rtc_rs5c372b: | |
604 | /* alarm uses ALARM_A; and nINTRA on 372a, nINTR on 372b. | |
605 | * so does periodic irq, except some 327a modes. | |
606 | */ | |
607 | if (rs5c372->regs[RS5C_REG_CTRL2] & RS5C372_CTRL2_24) | |
608 | rs5c372->time24 = 1; | |
609 | break; | |
37fc5e2c | 610 | case rtc_r2025sd: |
550fcb8f | 611 | case rtc_r2221tl: |
cb26b572 DB |
612 | case rtc_rv5c386: |
613 | case rtc_rv5c387a: | |
614 | if (rs5c372->regs[RS5C_REG_CTRL1] & RV5C387_CTRL1_24) | |
615 | rs5c372->time24 = 1; | |
616 | /* alarm uses ALARM_W; and nINTRB for alarm and periodic | |
617 | * irq, on both 386 and 387 | |
618 | */ | |
619 | break; | |
620 | default: | |
621 | dev_err(&client->dev, "unknown RTC type\n"); | |
b8a4b4e2 | 622 | goto exit; |
cb26b572 DB |
623 | } |
624 | ||
625 | /* if the oscillator lost power and no other software (like | |
626 | * the bootloader) set it up, do it here. | |
37fc5e2c PM |
627 | * |
628 | * The R2025S/D does this a little differently than the other | |
629 | * parts, so we special case that.. | |
cb26b572 | 630 | */ |
0053dc0d PM |
631 | err = rs5c_oscillator_setup(rs5c372); |
632 | if (unlikely(err < 0)) { | |
633 | dev_err(&client->dev, "setup error\n"); | |
b8a4b4e2 | 634 | goto exit; |
cb26b572 DB |
635 | } |
636 | ||
637 | if (rs5c372_get_datetime(client, &tm) < 0) | |
638 | dev_warn(&client->dev, "clock needs to be set\n"); | |
639 | ||
fa569113 | 640 | dev_info(&client->dev, "%s found, %s\n", |
cb26b572 | 641 | ({ char *s; switch (rs5c372->type) { |
37fc5e2c | 642 | case rtc_r2025sd: s = "r2025sd"; break; |
550fcb8f | 643 | case rtc_r2221tl: s = "r2221tl"; break; |
cb26b572 DB |
644 | case rtc_rs5c372a: s = "rs5c372a"; break; |
645 | case rtc_rs5c372b: s = "rs5c372b"; break; | |
646 | case rtc_rv5c386: s = "rv5c386"; break; | |
647 | case rtc_rv5c387a: s = "rv5c387a"; break; | |
648 | default: s = "chip"; break; | |
649 | }; s;}), | |
650 | rs5c372->time24 ? "24hr" : "am/pm" | |
651 | ); | |
652 | ||
d815461c | 653 | /* REVISIT use client->irq to register alarm irq ... */ |
b8a4b4e2 JH |
654 | rs5c372->rtc = devm_rtc_device_register(&client->dev, |
655 | rs5c372_driver.driver.name, | |
656 | &rs5c372_rtc_ops, THIS_MODULE); | |
7520b94d | 657 | |
c6f24f99 RV |
658 | if (IS_ERR(rs5c372->rtc)) { |
659 | err = PTR_ERR(rs5c372->rtc); | |
b8a4b4e2 | 660 | goto exit; |
7520b94d AZ |
661 | } |
662 | ||
cb26b572 | 663 | err = rs5c_sysfs_register(&client->dev); |
c6f24f99 | 664 | if (err) |
b8a4b4e2 | 665 | goto exit; |
7520b94d AZ |
666 | |
667 | return 0; | |
668 | ||
7520b94d AZ |
669 | exit: |
670 | return err; | |
671 | } | |
672 | ||
d815461c | 673 | static int rs5c372_remove(struct i2c_client *client) |
cb26b572 | 674 | { |
d815461c | 675 | rs5c_sysfs_unregister(&client->dev); |
7520b94d AZ |
676 | return 0; |
677 | } | |
678 | ||
cb26b572 DB |
679 | static struct i2c_driver rs5c372_driver = { |
680 | .driver = { | |
681 | .name = "rtc-rs5c372", | |
682 | }, | |
d815461c DB |
683 | .probe = rs5c372_probe, |
684 | .remove = rs5c372_remove, | |
3760f736 | 685 | .id_table = rs5c372_id, |
cb26b572 DB |
686 | }; |
687 | ||
0abc9201 | 688 | module_i2c_driver(rs5c372_driver); |
7520b94d AZ |
689 | |
690 | MODULE_AUTHOR( | |
691 | "Pavel Mironchik <pmironchik@optifacio.net>, " | |
0053dc0d PM |
692 | "Alessandro Zummo <a.zummo@towertech.it>, " |
693 | "Paul Mundt <lethal@linux-sh.org>"); | |
7520b94d AZ |
694 | MODULE_DESCRIPTION("Ricoh RS5C372 RTC driver"); |
695 | MODULE_LICENSE("GPL"); |