Commit | Line | Data |
---|---|---|
1add6781 | 1 | /* drivers/rtc/rtc-s3c.c |
e48add8c AD |
2 | * |
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com/ | |
1add6781 BD |
5 | * |
6 | * Copyright (c) 2004,2006 Simtec Electronics | |
7 | * Ben Dooks, <ben@simtec.co.uk> | |
8 | * http://armlinux.simtec.co.uk/ | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * S3C2410/S3C2440/S3C24XX Internal RTC Driver | |
15 | */ | |
16 | ||
17 | #include <linux/module.h> | |
18 | #include <linux/fs.h> | |
19 | #include <linux/string.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/rtc.h> | |
24 | #include <linux/bcd.h> | |
25 | #include <linux/clk.h> | |
9974b6ea | 26 | #include <linux/log2.h> |
5a0e3ad6 | 27 | #include <linux/slab.h> |
39ce4084 | 28 | #include <linux/of.h> |
dbd9acbe SK |
29 | #include <linux/uaccess.h> |
30 | #include <linux/io.h> | |
1add6781 | 31 | |
1add6781 | 32 | #include <asm/irq.h> |
b9d7c5d3 | 33 | #include "rtc-s3c.h" |
1add6781 | 34 | |
19be09f5 CC |
35 | struct s3c_rtc { |
36 | struct device *dev; | |
37 | struct rtc_device *rtc; | |
38 | ||
39 | void __iomem *base; | |
40 | struct clk *rtc_clk; | |
df9e26d0 | 41 | struct clk *rtc_src_clk; |
19be09f5 CC |
42 | bool enabled; |
43 | ||
ae05c950 | 44 | struct s3c_rtc_data *data; |
1add6781 | 45 | |
19be09f5 CC |
46 | int irq_alarm; |
47 | int irq_tick; | |
1add6781 | 48 | |
19be09f5 CC |
49 | spinlock_t pie_lock; |
50 | spinlock_t alarm_clk_lock; | |
1add6781 | 51 | |
19be09f5 CC |
52 | int ticnt_save, ticnt_en_save; |
53 | bool wake_en; | |
54 | }; | |
55 | ||
ae05c950 CC |
56 | struct s3c_rtc_data { |
57 | int max_user_freq; | |
df9e26d0 | 58 | bool needs_src_clk; |
ae05c950 CC |
59 | |
60 | void (*irq_handler) (struct s3c_rtc *info, int mask); | |
61 | void (*set_freq) (struct s3c_rtc *info, int freq); | |
62 | void (*enable_tick) (struct s3c_rtc *info, struct seq_file *seq); | |
63 | void (*select_tick_clk) (struct s3c_rtc *info); | |
64 | void (*save_tick_cnt) (struct s3c_rtc *info); | |
65 | void (*restore_tick_cnt) (struct s3c_rtc *info); | |
66 | void (*enable) (struct s3c_rtc *info); | |
67 | void (*disable) (struct s3c_rtc *info); | |
68 | }; | |
69 | ||
19be09f5 | 70 | static void s3c_rtc_alarm_clk_enable(struct s3c_rtc *info, bool enable) |
88cee8fd | 71 | { |
88cee8fd DK |
72 | unsigned long irq_flags; |
73 | ||
19be09f5 | 74 | spin_lock_irqsave(&info->alarm_clk_lock, irq_flags); |
88cee8fd | 75 | if (enable) { |
19be09f5 CC |
76 | if (!info->enabled) { |
77 | clk_enable(info->rtc_clk); | |
df9e26d0 CC |
78 | if (info->data->needs_src_clk) |
79 | clk_enable(info->rtc_src_clk); | |
19be09f5 | 80 | info->enabled = true; |
88cee8fd DK |
81 | } |
82 | } else { | |
19be09f5 | 83 | if (info->enabled) { |
df9e26d0 CC |
84 | if (info->data->needs_src_clk) |
85 | clk_disable(info->rtc_src_clk); | |
19be09f5 CC |
86 | clk_disable(info->rtc_clk); |
87 | info->enabled = false; | |
88cee8fd DK |
88 | } |
89 | } | |
19be09f5 | 90 | spin_unlock_irqrestore(&info->alarm_clk_lock, irq_flags); |
88cee8fd DK |
91 | } |
92 | ||
1add6781 | 93 | /* IRQ Handlers */ |
ae05c950 | 94 | static irqreturn_t s3c_rtc_tickirq(int irq, void *id) |
1add6781 | 95 | { |
19be09f5 | 96 | struct s3c_rtc *info = (struct s3c_rtc *)id; |
1add6781 | 97 | |
ae05c950 CC |
98 | if (info->data->irq_handler) |
99 | info->data->irq_handler(info, S3C2410_INTP_TIC); | |
88cee8fd | 100 | |
1add6781 BD |
101 | return IRQ_HANDLED; |
102 | } | |
103 | ||
ae05c950 | 104 | static irqreturn_t s3c_rtc_alarmirq(int irq, void *id) |
1add6781 | 105 | { |
19be09f5 | 106 | struct s3c_rtc *info = (struct s3c_rtc *)id; |
1add6781 | 107 | |
ae05c950 CC |
108 | if (info->data->irq_handler) |
109 | info->data->irq_handler(info, S3C2410_INTP_ALM); | |
2f3478f6 | 110 | |
1add6781 BD |
111 | return IRQ_HANDLED; |
112 | } | |
113 | ||
114 | /* Update control registers */ | |
2ec38a03 | 115 | static int s3c_rtc_setaie(struct device *dev, unsigned int enabled) |
1add6781 | 116 | { |
19be09f5 | 117 | struct s3c_rtc *info = dev_get_drvdata(dev); |
1add6781 BD |
118 | unsigned int tmp; |
119 | ||
19be09f5 | 120 | dev_dbg(info->dev, "%s: aie=%d\n", __func__, enabled); |
1add6781 | 121 | |
19be09f5 | 122 | clk_enable(info->rtc_clk); |
df9e26d0 CC |
123 | if (info->data->needs_src_clk) |
124 | clk_enable(info->rtc_src_clk); | |
19be09f5 | 125 | tmp = readb(info->base + S3C2410_RTCALM) & ~S3C2410_RTCALM_ALMEN; |
1add6781 | 126 | |
2ec38a03 | 127 | if (enabled) |
1add6781 BD |
128 | tmp |= S3C2410_RTCALM_ALMEN; |
129 | ||
19be09f5 | 130 | writeb(tmp, info->base + S3C2410_RTCALM); |
df9e26d0 CC |
131 | if (info->data->needs_src_clk) |
132 | clk_disable(info->rtc_src_clk); | |
19be09f5 | 133 | clk_disable(info->rtc_clk); |
2ec38a03 | 134 | |
19be09f5 | 135 | s3c_rtc_alarm_clk_enable(info, enabled); |
88cee8fd | 136 | |
2ec38a03 | 137 | return 0; |
1add6781 BD |
138 | } |
139 | ||
ae05c950 | 140 | /* Set RTC frequency */ |
19be09f5 | 141 | static int s3c_rtc_setfreq(struct s3c_rtc *info, int freq) |
1add6781 | 142 | { |
5d2a5037 JC |
143 | if (!is_power_of_2(freq)) |
144 | return -EINVAL; | |
145 | ||
19be09f5 | 146 | clk_enable(info->rtc_clk); |
df9e26d0 CC |
147 | if (info->data->needs_src_clk) |
148 | clk_enable(info->rtc_src_clk); | |
19be09f5 | 149 | spin_lock_irq(&info->pie_lock); |
1add6781 | 150 | |
ae05c950 CC |
151 | if (info->data->set_freq) |
152 | info->data->set_freq(info, freq); | |
25c1a246 | 153 | |
19be09f5 | 154 | spin_unlock_irq(&info->pie_lock); |
df9e26d0 CC |
155 | if (info->data->needs_src_clk) |
156 | clk_disable(info->rtc_src_clk); | |
19be09f5 | 157 | clk_disable(info->rtc_clk); |
773be7ee BD |
158 | |
159 | return 0; | |
1add6781 BD |
160 | } |
161 | ||
162 | /* Time read/write */ | |
1add6781 BD |
163 | static int s3c_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm) |
164 | { | |
19be09f5 | 165 | struct s3c_rtc *info = dev_get_drvdata(dev); |
1add6781 BD |
166 | unsigned int have_retried = 0; |
167 | ||
19be09f5 | 168 | clk_enable(info->rtc_clk); |
df9e26d0 CC |
169 | if (info->data->needs_src_clk) |
170 | clk_enable(info->rtc_src_clk); | |
171 | ||
1add6781 | 172 | retry_get_time: |
19be09f5 CC |
173 | rtc_tm->tm_min = readb(info->base + S3C2410_RTCMIN); |
174 | rtc_tm->tm_hour = readb(info->base + S3C2410_RTCHOUR); | |
175 | rtc_tm->tm_mday = readb(info->base + S3C2410_RTCDATE); | |
176 | rtc_tm->tm_mon = readb(info->base + S3C2410_RTCMON); | |
177 | rtc_tm->tm_year = readb(info->base + S3C2410_RTCYEAR); | |
178 | rtc_tm->tm_sec = readb(info->base + S3C2410_RTCSEC); | |
1add6781 | 179 | |
48fc7f7e | 180 | /* the only way to work out whether the system was mid-update |
1add6781 BD |
181 | * when we read it is to check the second counter, and if it |
182 | * is zero, then we re-try the entire read | |
183 | */ | |
184 | ||
185 | if (rtc_tm->tm_sec == 0 && !have_retried) { | |
186 | have_retried = 1; | |
187 | goto retry_get_time; | |
188 | } | |
189 | ||
fe20ba70 AB |
190 | rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec); |
191 | rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min); | |
192 | rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour); | |
193 | rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday); | |
194 | rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon); | |
195 | rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year); | |
1add6781 BD |
196 | |
197 | rtc_tm->tm_year += 100; | |
4e8896cd | 198 | |
d4a48c2a | 199 | dev_dbg(dev, "read time %04d.%02d.%02d %02d:%02d:%02d\n", |
4e8896cd MH |
200 | 1900 + rtc_tm->tm_year, rtc_tm->tm_mon, rtc_tm->tm_mday, |
201 | rtc_tm->tm_hour, rtc_tm->tm_min, rtc_tm->tm_sec); | |
202 | ||
1add6781 BD |
203 | rtc_tm->tm_mon -= 1; |
204 | ||
df9e26d0 CC |
205 | if (info->data->needs_src_clk) |
206 | clk_disable(info->rtc_src_clk); | |
19be09f5 CC |
207 | clk_disable(info->rtc_clk); |
208 | ||
5b3ffddd | 209 | return rtc_valid_tm(rtc_tm); |
1add6781 BD |
210 | } |
211 | ||
212 | static int s3c_rtc_settime(struct device *dev, struct rtc_time *tm) | |
213 | { | |
19be09f5 | 214 | struct s3c_rtc *info = dev_get_drvdata(dev); |
641741e0 | 215 | int year = tm->tm_year - 100; |
9a654518 | 216 | |
d4a48c2a | 217 | dev_dbg(dev, "set time %04d.%02d.%02d %02d:%02d:%02d\n", |
30ffc40c | 218 | 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday, |
641741e0 BD |
219 | tm->tm_hour, tm->tm_min, tm->tm_sec); |
220 | ||
221 | /* we get around y2k by simply not supporting it */ | |
1add6781 | 222 | |
641741e0 | 223 | if (year < 0 || year >= 100) { |
9a654518 | 224 | dev_err(dev, "rtc only supports 100 years\n"); |
1add6781 | 225 | return -EINVAL; |
9a654518 BD |
226 | } |
227 | ||
19be09f5 | 228 | clk_enable(info->rtc_clk); |
df9e26d0 CC |
229 | if (info->data->needs_src_clk) |
230 | clk_enable(info->rtc_src_clk); | |
19be09f5 CC |
231 | |
232 | writeb(bin2bcd(tm->tm_sec), info->base + S3C2410_RTCSEC); | |
233 | writeb(bin2bcd(tm->tm_min), info->base + S3C2410_RTCMIN); | |
234 | writeb(bin2bcd(tm->tm_hour), info->base + S3C2410_RTCHOUR); | |
235 | writeb(bin2bcd(tm->tm_mday), info->base + S3C2410_RTCDATE); | |
236 | writeb(bin2bcd(tm->tm_mon + 1), info->base + S3C2410_RTCMON); | |
237 | writeb(bin2bcd(year), info->base + S3C2410_RTCYEAR); | |
238 | ||
df9e26d0 CC |
239 | if (info->data->needs_src_clk) |
240 | clk_disable(info->rtc_src_clk); | |
19be09f5 | 241 | clk_disable(info->rtc_clk); |
1add6781 BD |
242 | |
243 | return 0; | |
244 | } | |
245 | ||
246 | static int s3c_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm) | |
247 | { | |
19be09f5 | 248 | struct s3c_rtc *info = dev_get_drvdata(dev); |
1add6781 BD |
249 | struct rtc_time *alm_tm = &alrm->time; |
250 | unsigned int alm_en; | |
251 | ||
19be09f5 | 252 | clk_enable(info->rtc_clk); |
df9e26d0 CC |
253 | if (info->data->needs_src_clk) |
254 | clk_enable(info->rtc_src_clk); | |
255 | ||
19be09f5 CC |
256 | alm_tm->tm_sec = readb(info->base + S3C2410_ALMSEC); |
257 | alm_tm->tm_min = readb(info->base + S3C2410_ALMMIN); | |
258 | alm_tm->tm_hour = readb(info->base + S3C2410_ALMHOUR); | |
259 | alm_tm->tm_mon = readb(info->base + S3C2410_ALMMON); | |
260 | alm_tm->tm_mday = readb(info->base + S3C2410_ALMDATE); | |
261 | alm_tm->tm_year = readb(info->base + S3C2410_ALMYEAR); | |
1add6781 | 262 | |
19be09f5 | 263 | alm_en = readb(info->base + S3C2410_RTCALM); |
1add6781 | 264 | |
a2db8dfc DB |
265 | alrm->enabled = (alm_en & S3C2410_RTCALM_ALMEN) ? 1 : 0; |
266 | ||
d4a48c2a | 267 | dev_dbg(dev, "read alarm %d, %04d.%02d.%02d %02d:%02d:%02d\n", |
1add6781 | 268 | alm_en, |
30ffc40c | 269 | 1900 + alm_tm->tm_year, alm_tm->tm_mon, alm_tm->tm_mday, |
1add6781 BD |
270 | alm_tm->tm_hour, alm_tm->tm_min, alm_tm->tm_sec); |
271 | ||
272 | ||
273 | /* decode the alarm enable field */ | |
274 | ||
275 | if (alm_en & S3C2410_RTCALM_SECEN) | |
fe20ba70 | 276 | alm_tm->tm_sec = bcd2bin(alm_tm->tm_sec); |
1add6781 | 277 | else |
dd061d1a | 278 | alm_tm->tm_sec = -1; |
1add6781 BD |
279 | |
280 | if (alm_en & S3C2410_RTCALM_MINEN) | |
fe20ba70 | 281 | alm_tm->tm_min = bcd2bin(alm_tm->tm_min); |
1add6781 | 282 | else |
dd061d1a | 283 | alm_tm->tm_min = -1; |
1add6781 BD |
284 | |
285 | if (alm_en & S3C2410_RTCALM_HOUREN) | |
fe20ba70 | 286 | alm_tm->tm_hour = bcd2bin(alm_tm->tm_hour); |
1add6781 | 287 | else |
dd061d1a | 288 | alm_tm->tm_hour = -1; |
1add6781 BD |
289 | |
290 | if (alm_en & S3C2410_RTCALM_DAYEN) | |
fe20ba70 | 291 | alm_tm->tm_mday = bcd2bin(alm_tm->tm_mday); |
1add6781 | 292 | else |
dd061d1a | 293 | alm_tm->tm_mday = -1; |
1add6781 BD |
294 | |
295 | if (alm_en & S3C2410_RTCALM_MONEN) { | |
fe20ba70 | 296 | alm_tm->tm_mon = bcd2bin(alm_tm->tm_mon); |
1add6781 BD |
297 | alm_tm->tm_mon -= 1; |
298 | } else { | |
dd061d1a | 299 | alm_tm->tm_mon = -1; |
1add6781 BD |
300 | } |
301 | ||
302 | if (alm_en & S3C2410_RTCALM_YEAREN) | |
fe20ba70 | 303 | alm_tm->tm_year = bcd2bin(alm_tm->tm_year); |
1add6781 | 304 | else |
dd061d1a | 305 | alm_tm->tm_year = -1; |
1add6781 | 306 | |
df9e26d0 CC |
307 | if (info->data->needs_src_clk) |
308 | clk_disable(info->rtc_src_clk); | |
19be09f5 | 309 | clk_disable(info->rtc_clk); |
df9e26d0 | 310 | |
1add6781 BD |
311 | return 0; |
312 | } | |
313 | ||
314 | static int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) | |
315 | { | |
19be09f5 | 316 | struct s3c_rtc *info = dev_get_drvdata(dev); |
1add6781 BD |
317 | struct rtc_time *tm = &alrm->time; |
318 | unsigned int alrm_en; | |
319 | ||
19be09f5 | 320 | clk_enable(info->rtc_clk); |
df9e26d0 CC |
321 | if (info->data->needs_src_clk) |
322 | clk_enable(info->rtc_src_clk); | |
323 | ||
d4a48c2a | 324 | dev_dbg(dev, "s3c_rtc_setalarm: %d, %04d.%02d.%02d %02d:%02d:%02d\n", |
1add6781 | 325 | alrm->enabled, |
4e8896cd | 326 | 1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday, |
30ffc40c | 327 | tm->tm_hour, tm->tm_min, tm->tm_sec); |
1add6781 | 328 | |
19be09f5 CC |
329 | alrm_en = readb(info->base + S3C2410_RTCALM) & S3C2410_RTCALM_ALMEN; |
330 | writeb(0x00, info->base + S3C2410_RTCALM); | |
1add6781 BD |
331 | |
332 | if (tm->tm_sec < 60 && tm->tm_sec >= 0) { | |
333 | alrm_en |= S3C2410_RTCALM_SECEN; | |
19be09f5 | 334 | writeb(bin2bcd(tm->tm_sec), info->base + S3C2410_ALMSEC); |
1add6781 BD |
335 | } |
336 | ||
337 | if (tm->tm_min < 60 && tm->tm_min >= 0) { | |
338 | alrm_en |= S3C2410_RTCALM_MINEN; | |
19be09f5 | 339 | writeb(bin2bcd(tm->tm_min), info->base + S3C2410_ALMMIN); |
1add6781 BD |
340 | } |
341 | ||
342 | if (tm->tm_hour < 24 && tm->tm_hour >= 0) { | |
343 | alrm_en |= S3C2410_RTCALM_HOUREN; | |
19be09f5 | 344 | writeb(bin2bcd(tm->tm_hour), info->base + S3C2410_ALMHOUR); |
1add6781 BD |
345 | } |
346 | ||
d4a48c2a | 347 | dev_dbg(dev, "setting S3C2410_RTCALM to %08x\n", alrm_en); |
1add6781 | 348 | |
19be09f5 | 349 | writeb(alrm_en, info->base + S3C2410_RTCALM); |
1add6781 | 350 | |
2ec38a03 | 351 | s3c_rtc_setaie(dev, alrm->enabled); |
1add6781 | 352 | |
df9e26d0 CC |
353 | if (info->data->needs_src_clk) |
354 | clk_disable(info->rtc_src_clk); | |
19be09f5 CC |
355 | clk_disable(info->rtc_clk); |
356 | ||
1add6781 BD |
357 | return 0; |
358 | } | |
359 | ||
1add6781 BD |
360 | static int s3c_rtc_proc(struct device *dev, struct seq_file *seq) |
361 | { | |
19be09f5 | 362 | struct s3c_rtc *info = dev_get_drvdata(dev); |
1add6781 | 363 | |
19be09f5 | 364 | clk_enable(info->rtc_clk); |
df9e26d0 CC |
365 | if (info->data->needs_src_clk) |
366 | clk_enable(info->rtc_src_clk); | |
9f4123b7 | 367 | |
ae05c950 CC |
368 | if (info->data->enable_tick) |
369 | info->data->enable_tick(info, seq); | |
370 | ||
df9e26d0 CC |
371 | if (info->data->needs_src_clk) |
372 | clk_disable(info->rtc_src_clk); | |
19be09f5 | 373 | clk_disable(info->rtc_clk); |
ae05c950 | 374 | |
1add6781 BD |
375 | return 0; |
376 | } | |
377 | ||
ff8371ac | 378 | static const struct rtc_class_ops s3c_rtcops = { |
1add6781 BD |
379 | .read_time = s3c_rtc_gettime, |
380 | .set_time = s3c_rtc_settime, | |
381 | .read_alarm = s3c_rtc_getalarm, | |
382 | .set_alarm = s3c_rtc_setalarm, | |
e6eb524e CY |
383 | .proc = s3c_rtc_proc, |
384 | .alarm_irq_enable = s3c_rtc_setaie, | |
1add6781 BD |
385 | }; |
386 | ||
ae05c950 | 387 | static void s3c24xx_rtc_enable(struct s3c_rtc *info) |
1add6781 | 388 | { |
d67288da | 389 | unsigned int con, tmp; |
1add6781 | 390 | |
19be09f5 | 391 | clk_enable(info->rtc_clk); |
df9e26d0 CC |
392 | if (info->data->needs_src_clk) |
393 | clk_enable(info->rtc_src_clk); | |
d67288da CC |
394 | |
395 | con = readw(info->base + S3C2410_RTCCON); | |
ae05c950 CC |
396 | /* re-enable the device, and check it is ok */ |
397 | if ((con & S3C2410_RTCCON_RTCEN) == 0) { | |
398 | dev_info(info->dev, "rtc disabled, re-enabling\n"); | |
1add6781 | 399 | |
ae05c950 CC |
400 | tmp = readw(info->base + S3C2410_RTCCON); |
401 | writew(tmp | S3C2410_RTCCON_RTCEN, | |
402 | info->base + S3C2410_RTCCON); | |
403 | } | |
1add6781 | 404 | |
ae05c950 CC |
405 | if (con & S3C2410_RTCCON_CNTSEL) { |
406 | dev_info(info->dev, "removing RTCCON_CNTSEL\n"); | |
1add6781 | 407 | |
ae05c950 CC |
408 | tmp = readw(info->base + S3C2410_RTCCON); |
409 | writew(tmp & ~S3C2410_RTCCON_CNTSEL, | |
410 | info->base + S3C2410_RTCCON); | |
411 | } | |
1add6781 | 412 | |
ae05c950 CC |
413 | if (con & S3C2410_RTCCON_CLKRST) { |
414 | dev_info(info->dev, "removing RTCCON_CLKRST\n"); | |
1add6781 | 415 | |
ae05c950 CC |
416 | tmp = readw(info->base + S3C2410_RTCCON); |
417 | writew(tmp & ~S3C2410_RTCCON_CLKRST, | |
418 | info->base + S3C2410_RTCCON); | |
1add6781 | 419 | } |
ae05c950 | 420 | |
df9e26d0 CC |
421 | if (info->data->needs_src_clk) |
422 | clk_disable(info->rtc_src_clk); | |
ae05c950 CC |
423 | clk_disable(info->rtc_clk); |
424 | } | |
425 | ||
426 | static void s3c24xx_rtc_disable(struct s3c_rtc *info) | |
427 | { | |
428 | unsigned int con; | |
429 | ||
430 | clk_enable(info->rtc_clk); | |
df9e26d0 CC |
431 | if (info->data->needs_src_clk) |
432 | clk_enable(info->rtc_src_clk); | |
ae05c950 CC |
433 | |
434 | con = readw(info->base + S3C2410_RTCCON); | |
435 | con &= ~S3C2410_RTCCON_RTCEN; | |
436 | writew(con, info->base + S3C2410_RTCCON); | |
437 | ||
438 | con = readb(info->base + S3C2410_TICNT); | |
439 | con &= ~S3C2410_TICNT_ENABLE; | |
440 | writeb(con, info->base + S3C2410_TICNT); | |
441 | ||
df9e26d0 CC |
442 | if (info->data->needs_src_clk) |
443 | clk_disable(info->rtc_src_clk); | |
ae05c950 CC |
444 | clk_disable(info->rtc_clk); |
445 | } | |
446 | ||
447 | static void s3c6410_rtc_disable(struct s3c_rtc *info) | |
448 | { | |
449 | unsigned int con; | |
450 | ||
451 | clk_enable(info->rtc_clk); | |
df9e26d0 CC |
452 | if (info->data->needs_src_clk) |
453 | clk_enable(info->rtc_src_clk); | |
ae05c950 CC |
454 | |
455 | con = readw(info->base + S3C2410_RTCCON); | |
456 | con &= ~S3C64XX_RTCCON_TICEN; | |
457 | con &= ~S3C2410_RTCCON_RTCEN; | |
458 | writew(con, info->base + S3C2410_RTCCON); | |
459 | ||
df9e26d0 CC |
460 | if (info->data->needs_src_clk) |
461 | clk_disable(info->rtc_src_clk); | |
19be09f5 | 462 | clk_disable(info->rtc_clk); |
1add6781 BD |
463 | } |
464 | ||
19be09f5 | 465 | static int s3c_rtc_remove(struct platform_device *pdev) |
1add6781 | 466 | { |
19be09f5 CC |
467 | struct s3c_rtc *info = platform_get_drvdata(pdev); |
468 | ||
469 | s3c_rtc_setaie(info->dev, 0); | |
1add6781 | 470 | |
19be09f5 CC |
471 | clk_unprepare(info->rtc_clk); |
472 | info->rtc_clk = NULL; | |
e48add8c | 473 | |
1add6781 BD |
474 | return 0; |
475 | } | |
476 | ||
d2524caa HS |
477 | static const struct of_device_id s3c_rtc_dt_match[]; |
478 | ||
ae05c950 | 479 | static struct s3c_rtc_data *s3c_rtc_get_data(struct platform_device *pdev) |
d2524caa | 480 | { |
ae05c950 | 481 | const struct of_device_id *match; |
d67288da | 482 | |
ae05c950 CC |
483 | match = of_match_node(s3c_rtc_dt_match, pdev->dev.of_node); |
484 | return (struct s3c_rtc_data *)match->data; | |
d2524caa HS |
485 | } |
486 | ||
5a167f45 | 487 | static int s3c_rtc_probe(struct platform_device *pdev) |
1add6781 | 488 | { |
19be09f5 | 489 | struct s3c_rtc *info = NULL; |
e1df962e | 490 | struct rtc_time rtc_tm; |
1add6781 BD |
491 | struct resource *res; |
492 | int ret; | |
493 | ||
19be09f5 CC |
494 | info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); |
495 | if (!info) | |
496 | return -ENOMEM; | |
1add6781 BD |
497 | |
498 | /* find the IRQs */ | |
19be09f5 CC |
499 | info->irq_tick = platform_get_irq(pdev, 1); |
500 | if (info->irq_tick < 0) { | |
1add6781 | 501 | dev_err(&pdev->dev, "no irq for rtc tick\n"); |
19be09f5 | 502 | return info->irq_tick; |
1add6781 BD |
503 | } |
504 | ||
19be09f5 | 505 | info->dev = &pdev->dev; |
ae05c950 CC |
506 | info->data = s3c_rtc_get_data(pdev); |
507 | if (!info->data) { | |
508 | dev_err(&pdev->dev, "failed getting s3c_rtc_data\n"); | |
509 | return -EINVAL; | |
510 | } | |
19be09f5 CC |
511 | spin_lock_init(&info->pie_lock); |
512 | spin_lock_init(&info->alarm_clk_lock); | |
513 | ||
514 | platform_set_drvdata(pdev, info); | |
515 | ||
516 | info->irq_alarm = platform_get_irq(pdev, 0); | |
517 | if (info->irq_alarm < 0) { | |
1add6781 | 518 | dev_err(&pdev->dev, "no irq for alarm\n"); |
19be09f5 | 519 | return info->irq_alarm; |
1add6781 BD |
520 | } |
521 | ||
d4a48c2a | 522 | dev_dbg(&pdev->dev, "s3c2410_rtc: tick irq %d, alarm irq %d\n", |
19be09f5 | 523 | info->irq_tick, info->irq_alarm); |
1add6781 BD |
524 | |
525 | /* get the memory region */ | |
1add6781 | 526 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
19be09f5 CC |
527 | info->base = devm_ioremap_resource(&pdev->dev, res); |
528 | if (IS_ERR(info->base)) | |
529 | return PTR_ERR(info->base); | |
1add6781 | 530 | |
19be09f5 CC |
531 | info->rtc_clk = devm_clk_get(&pdev->dev, "rtc"); |
532 | if (IS_ERR(info->rtc_clk)) { | |
df9e26d0 | 533 | dev_err(&pdev->dev, "failed to find rtc clock\n"); |
19be09f5 | 534 | return PTR_ERR(info->rtc_clk); |
e48add8c | 535 | } |
19be09f5 | 536 | clk_prepare_enable(info->rtc_clk); |
e48add8c | 537 | |
eaf3a659 MS |
538 | if (info->data->needs_src_clk) { |
539 | info->rtc_src_clk = devm_clk_get(&pdev->dev, "rtc_src"); | |
540 | if (IS_ERR(info->rtc_src_clk)) { | |
541 | dev_err(&pdev->dev, | |
542 | "failed to find rtc source clock\n"); | |
543 | return PTR_ERR(info->rtc_src_clk); | |
544 | } | |
545 | clk_prepare_enable(info->rtc_src_clk); | |
df9e26d0 | 546 | } |
df9e26d0 | 547 | |
1add6781 | 548 | /* check to see if everything is setup correctly */ |
ae05c950 CC |
549 | if (info->data->enable) |
550 | info->data->enable(info); | |
1add6781 | 551 | |
d4a48c2a | 552 | dev_dbg(&pdev->dev, "s3c2410_rtc: RTCCON=%02x\n", |
19be09f5 | 553 | readw(info->base + S3C2410_RTCCON)); |
1add6781 | 554 | |
51b7616e YK |
555 | device_init_wakeup(&pdev->dev, 1); |
556 | ||
1add6781 | 557 | /* register RTC and exit */ |
19be09f5 | 558 | info->rtc = devm_rtc_device_register(&pdev->dev, "s3c", &s3c_rtcops, |
1add6781 | 559 | THIS_MODULE); |
19be09f5 | 560 | if (IS_ERR(info->rtc)) { |
1add6781 | 561 | dev_err(&pdev->dev, "cannot attach rtc\n"); |
19be09f5 | 562 | ret = PTR_ERR(info->rtc); |
1add6781 BD |
563 | goto err_nortc; |
564 | } | |
565 | ||
19be09f5 CC |
566 | ret = devm_request_irq(&pdev->dev, info->irq_alarm, s3c_rtc_alarmirq, |
567 | 0, "s3c2410-rtc alarm", info); | |
568 | if (ret) { | |
569 | dev_err(&pdev->dev, "IRQ%d error %d\n", info->irq_alarm, ret); | |
570 | goto err_nortc; | |
571 | } | |
eaa6e4dd | 572 | |
19be09f5 CC |
573 | ret = devm_request_irq(&pdev->dev, info->irq_tick, s3c_rtc_tickirq, |
574 | 0, "s3c2410-rtc tick", info); | |
575 | if (ret) { | |
576 | dev_err(&pdev->dev, "IRQ%d error %d\n", info->irq_tick, ret); | |
577 | goto err_nortc; | |
578 | } | |
051fe54e | 579 | |
19be09f5 CC |
580 | /* Check RTC Time */ |
581 | s3c_rtc_gettime(&pdev->dev, &rtc_tm); | |
051fe54e | 582 | |
e1df962e CY |
583 | if (rtc_valid_tm(&rtc_tm)) { |
584 | rtc_tm.tm_year = 100; | |
585 | rtc_tm.tm_mon = 0; | |
586 | rtc_tm.tm_mday = 1; | |
587 | rtc_tm.tm_hour = 0; | |
588 | rtc_tm.tm_min = 0; | |
589 | rtc_tm.tm_sec = 0; | |
590 | ||
19be09f5 | 591 | s3c_rtc_settime(&pdev->dev, &rtc_tm); |
e1df962e CY |
592 | |
593 | dev_warn(&pdev->dev, "warning: invalid RTC value so initializing it\n"); | |
051fe54e TK |
594 | } |
595 | ||
ae05c950 CC |
596 | if (info->data->select_tick_clk) |
597 | info->data->select_tick_clk(info); | |
62d17601 | 598 | |
19be09f5 | 599 | s3c_rtc_setfreq(info, 1); |
62d17601 | 600 | |
df9e26d0 CC |
601 | if (info->data->needs_src_clk) |
602 | clk_disable(info->rtc_src_clk); | |
19be09f5 | 603 | clk_disable(info->rtc_clk); |
cefe4fbb | 604 | |
1add6781 BD |
605 | return 0; |
606 | ||
607 | err_nortc: | |
ae05c950 CC |
608 | if (info->data->disable) |
609 | info->data->disable(info); | |
19be09f5 | 610 | clk_disable_unprepare(info->rtc_clk); |
1add6781 | 611 | |
1add6781 BD |
612 | return ret; |
613 | } | |
614 | ||
32e445aa | 615 | #ifdef CONFIG_PM_SLEEP |
1add6781 | 616 | |
32e445aa | 617 | static int s3c_rtc_suspend(struct device *dev) |
1add6781 | 618 | { |
19be09f5 | 619 | struct s3c_rtc *info = dev_get_drvdata(dev); |
32e445aa | 620 | |
19be09f5 | 621 | clk_enable(info->rtc_clk); |
df9e26d0 CC |
622 | if (info->data->needs_src_clk) |
623 | clk_enable(info->rtc_src_clk); | |
ae05c950 | 624 | |
1add6781 | 625 | /* save TICNT for anyone using periodic interrupts */ |
ae05c950 CC |
626 | if (info->data->save_tick_cnt) |
627 | info->data->save_tick_cnt(info); | |
628 | ||
629 | if (info->data->disable) | |
630 | info->data->disable(info); | |
f501ed52 | 631 | |
19be09f5 CC |
632 | if (device_may_wakeup(dev) && !info->wake_en) { |
633 | if (enable_irq_wake(info->irq_alarm) == 0) | |
634 | info->wake_en = true; | |
52cd4e5c | 635 | else |
32e445aa | 636 | dev_err(dev, "enable_irq_wake failed\n"); |
52cd4e5c | 637 | } |
ae05c950 | 638 | |
df9e26d0 CC |
639 | if (info->data->needs_src_clk) |
640 | clk_disable(info->rtc_src_clk); | |
19be09f5 | 641 | clk_disable(info->rtc_clk); |
f501ed52 | 642 | |
1add6781 BD |
643 | return 0; |
644 | } | |
645 | ||
32e445aa | 646 | static int s3c_rtc_resume(struct device *dev) |
1add6781 | 647 | { |
19be09f5 | 648 | struct s3c_rtc *info = dev_get_drvdata(dev); |
9f4123b7 | 649 | |
19be09f5 | 650 | clk_enable(info->rtc_clk); |
df9e26d0 CC |
651 | if (info->data->needs_src_clk) |
652 | clk_enable(info->rtc_src_clk); | |
ae05c950 CC |
653 | |
654 | if (info->data->enable) | |
655 | info->data->enable(info); | |
656 | ||
657 | if (info->data->restore_tick_cnt) | |
658 | info->data->restore_tick_cnt(info); | |
f501ed52 | 659 | |
19be09f5 CC |
660 | if (device_may_wakeup(dev) && info->wake_en) { |
661 | disable_irq_wake(info->irq_alarm); | |
662 | info->wake_en = false; | |
52cd4e5c | 663 | } |
ae05c950 | 664 | |
df9e26d0 CC |
665 | if (info->data->needs_src_clk) |
666 | clk_disable(info->rtc_src_clk); | |
19be09f5 | 667 | clk_disable(info->rtc_clk); |
f501ed52 | 668 | |
1add6781 BD |
669 | return 0; |
670 | } | |
1add6781 | 671 | #endif |
32e445aa JH |
672 | static SIMPLE_DEV_PM_OPS(s3c_rtc_pm_ops, s3c_rtc_suspend, s3c_rtc_resume); |
673 | ||
ae05c950 CC |
674 | static void s3c24xx_rtc_irq(struct s3c_rtc *info, int mask) |
675 | { | |
676 | clk_enable(info->rtc_clk); | |
df9e26d0 CC |
677 | if (info->data->needs_src_clk) |
678 | clk_enable(info->rtc_src_clk); | |
ae05c950 | 679 | rtc_update_irq(info->rtc, 1, RTC_AF | RTC_IRQF); |
df9e26d0 CC |
680 | if (info->data->needs_src_clk) |
681 | clk_disable(info->rtc_src_clk); | |
ae05c950 CC |
682 | clk_disable(info->rtc_clk); |
683 | ||
684 | s3c_rtc_alarm_clk_enable(info, false); | |
685 | } | |
686 | ||
687 | static void s3c6410_rtc_irq(struct s3c_rtc *info, int mask) | |
688 | { | |
689 | clk_enable(info->rtc_clk); | |
df9e26d0 CC |
690 | if (info->data->needs_src_clk) |
691 | clk_enable(info->rtc_src_clk); | |
ae05c950 CC |
692 | rtc_update_irq(info->rtc, 1, RTC_AF | RTC_IRQF); |
693 | writeb(mask, info->base + S3C2410_INTP); | |
df9e26d0 CC |
694 | if (info->data->needs_src_clk) |
695 | clk_disable(info->rtc_src_clk); | |
ae05c950 CC |
696 | clk_disable(info->rtc_clk); |
697 | ||
698 | s3c_rtc_alarm_clk_enable(info, false); | |
699 | } | |
700 | ||
701 | static void s3c2410_rtc_setfreq(struct s3c_rtc *info, int freq) | |
702 | { | |
703 | unsigned int tmp = 0; | |
704 | int val; | |
705 | ||
706 | tmp = readb(info->base + S3C2410_TICNT); | |
707 | tmp &= S3C2410_TICNT_ENABLE; | |
708 | ||
709 | val = (info->rtc->max_user_freq / freq) - 1; | |
710 | tmp |= val; | |
711 | ||
712 | writel(tmp, info->base + S3C2410_TICNT); | |
713 | } | |
714 | ||
715 | static void s3c2416_rtc_setfreq(struct s3c_rtc *info, int freq) | |
716 | { | |
717 | unsigned int tmp = 0; | |
718 | int val; | |
719 | ||
720 | tmp = readb(info->base + S3C2410_TICNT); | |
721 | tmp &= S3C2410_TICNT_ENABLE; | |
722 | ||
723 | val = (info->rtc->max_user_freq / freq) - 1; | |
724 | ||
725 | tmp |= S3C2443_TICNT_PART(val); | |
726 | writel(S3C2443_TICNT1_PART(val), info->base + S3C2443_TICNT1); | |
727 | ||
728 | writel(S3C2416_TICNT2_PART(val), info->base + S3C2416_TICNT2); | |
729 | ||
730 | writel(tmp, info->base + S3C2410_TICNT); | |
731 | } | |
732 | ||
733 | static void s3c2443_rtc_setfreq(struct s3c_rtc *info, int freq) | |
734 | { | |
735 | unsigned int tmp = 0; | |
736 | int val; | |
737 | ||
738 | tmp = readb(info->base + S3C2410_TICNT); | |
739 | tmp &= S3C2410_TICNT_ENABLE; | |
740 | ||
741 | val = (info->rtc->max_user_freq / freq) - 1; | |
742 | ||
743 | tmp |= S3C2443_TICNT_PART(val); | |
744 | writel(S3C2443_TICNT1_PART(val), info->base + S3C2443_TICNT1); | |
745 | ||
746 | writel(tmp, info->base + S3C2410_TICNT); | |
747 | } | |
748 | ||
749 | static void s3c6410_rtc_setfreq(struct s3c_rtc *info, int freq) | |
750 | { | |
751 | int val; | |
752 | ||
753 | val = (info->rtc->max_user_freq / freq) - 1; | |
754 | writel(val, info->base + S3C2410_TICNT); | |
755 | } | |
756 | ||
757 | static void s3c24xx_rtc_enable_tick(struct s3c_rtc *info, struct seq_file *seq) | |
758 | { | |
759 | unsigned int ticnt; | |
760 | ||
761 | ticnt = readb(info->base + S3C2410_TICNT); | |
762 | ticnt &= S3C2410_TICNT_ENABLE; | |
763 | ||
764 | seq_printf(seq, "periodic_IRQ\t: %s\n", ticnt ? "yes" : "no"); | |
765 | } | |
766 | ||
767 | static void s3c2416_rtc_select_tick_clk(struct s3c_rtc *info) | |
768 | { | |
769 | unsigned int con; | |
770 | ||
771 | con = readw(info->base + S3C2410_RTCCON); | |
772 | con |= S3C2443_RTCCON_TICSEL; | |
773 | writew(con, info->base + S3C2410_RTCCON); | |
774 | } | |
775 | ||
776 | static void s3c6410_rtc_enable_tick(struct s3c_rtc *info, struct seq_file *seq) | |
777 | { | |
778 | unsigned int ticnt; | |
779 | ||
780 | ticnt = readw(info->base + S3C2410_RTCCON); | |
781 | ticnt &= S3C64XX_RTCCON_TICEN; | |
782 | ||
783 | seq_printf(seq, "periodic_IRQ\t: %s\n", ticnt ? "yes" : "no"); | |
784 | } | |
785 | ||
786 | static void s3c24xx_rtc_save_tick_cnt(struct s3c_rtc *info) | |
787 | { | |
788 | info->ticnt_save = readb(info->base + S3C2410_TICNT); | |
789 | } | |
790 | ||
791 | static void s3c24xx_rtc_restore_tick_cnt(struct s3c_rtc *info) | |
792 | { | |
793 | writeb(info->ticnt_save, info->base + S3C2410_TICNT); | |
794 | } | |
795 | ||
796 | static void s3c6410_rtc_save_tick_cnt(struct s3c_rtc *info) | |
797 | { | |
798 | info->ticnt_en_save = readw(info->base + S3C2410_RTCCON); | |
799 | info->ticnt_en_save &= S3C64XX_RTCCON_TICEN; | |
800 | info->ticnt_save = readl(info->base + S3C2410_TICNT); | |
801 | } | |
802 | ||
803 | static void s3c6410_rtc_restore_tick_cnt(struct s3c_rtc *info) | |
804 | { | |
805 | unsigned int con; | |
806 | ||
807 | writel(info->ticnt_save, info->base + S3C2410_TICNT); | |
808 | if (info->ticnt_en_save) { | |
809 | con = readw(info->base + S3C2410_RTCCON); | |
810 | writew(con | info->ticnt_en_save, | |
811 | info->base + S3C2410_RTCCON); | |
812 | } | |
813 | } | |
814 | ||
815 | static struct s3c_rtc_data const s3c2410_rtc_data = { | |
816 | .max_user_freq = 128, | |
817 | .irq_handler = s3c24xx_rtc_irq, | |
818 | .set_freq = s3c2410_rtc_setfreq, | |
819 | .enable_tick = s3c24xx_rtc_enable_tick, | |
820 | .save_tick_cnt = s3c24xx_rtc_save_tick_cnt, | |
821 | .restore_tick_cnt = s3c24xx_rtc_restore_tick_cnt, | |
822 | .enable = s3c24xx_rtc_enable, | |
823 | .disable = s3c24xx_rtc_disable, | |
824 | }; | |
825 | ||
826 | static struct s3c_rtc_data const s3c2416_rtc_data = { | |
827 | .max_user_freq = 32768, | |
828 | .irq_handler = s3c24xx_rtc_irq, | |
829 | .set_freq = s3c2416_rtc_setfreq, | |
830 | .enable_tick = s3c24xx_rtc_enable_tick, | |
831 | .select_tick_clk = s3c2416_rtc_select_tick_clk, | |
832 | .save_tick_cnt = s3c24xx_rtc_save_tick_cnt, | |
833 | .restore_tick_cnt = s3c24xx_rtc_restore_tick_cnt, | |
834 | .enable = s3c24xx_rtc_enable, | |
835 | .disable = s3c24xx_rtc_disable, | |
836 | }; | |
837 | ||
838 | static struct s3c_rtc_data const s3c2443_rtc_data = { | |
839 | .max_user_freq = 32768, | |
840 | .irq_handler = s3c24xx_rtc_irq, | |
841 | .set_freq = s3c2443_rtc_setfreq, | |
842 | .enable_tick = s3c24xx_rtc_enable_tick, | |
843 | .select_tick_clk = s3c2416_rtc_select_tick_clk, | |
844 | .save_tick_cnt = s3c24xx_rtc_save_tick_cnt, | |
845 | .restore_tick_cnt = s3c24xx_rtc_restore_tick_cnt, | |
846 | .enable = s3c24xx_rtc_enable, | |
847 | .disable = s3c24xx_rtc_disable, | |
848 | }; | |
849 | ||
850 | static struct s3c_rtc_data const s3c6410_rtc_data = { | |
851 | .max_user_freq = 32768, | |
852 | .irq_handler = s3c6410_rtc_irq, | |
853 | .set_freq = s3c6410_rtc_setfreq, | |
854 | .enable_tick = s3c6410_rtc_enable_tick, | |
855 | .save_tick_cnt = s3c6410_rtc_save_tick_cnt, | |
856 | .restore_tick_cnt = s3c6410_rtc_restore_tick_cnt, | |
857 | .enable = s3c24xx_rtc_enable, | |
858 | .disable = s3c6410_rtc_disable, | |
c3cba928 TB |
859 | }; |
860 | ||
df9e26d0 CC |
861 | static struct s3c_rtc_data const exynos3250_rtc_data = { |
862 | .max_user_freq = 32768, | |
863 | .needs_src_clk = true, | |
864 | .irq_handler = s3c6410_rtc_irq, | |
865 | .set_freq = s3c6410_rtc_setfreq, | |
866 | .enable_tick = s3c6410_rtc_enable_tick, | |
867 | .save_tick_cnt = s3c6410_rtc_save_tick_cnt, | |
868 | .restore_tick_cnt = s3c6410_rtc_restore_tick_cnt, | |
869 | .enable = s3c24xx_rtc_enable, | |
870 | .disable = s3c6410_rtc_disable, | |
871 | }; | |
872 | ||
39ce4084 | 873 | static const struct of_device_id s3c_rtc_dt_match[] = { |
d2524caa | 874 | { |
cd1e6f9e | 875 | .compatible = "samsung,s3c2410-rtc", |
ae05c950 | 876 | .data = (void *)&s3c2410_rtc_data, |
25c1a246 | 877 | }, { |
cd1e6f9e | 878 | .compatible = "samsung,s3c2416-rtc", |
ae05c950 | 879 | .data = (void *)&s3c2416_rtc_data, |
25c1a246 | 880 | }, { |
cd1e6f9e | 881 | .compatible = "samsung,s3c2443-rtc", |
ae05c950 | 882 | .data = (void *)&s3c2443_rtc_data, |
d2524caa | 883 | }, { |
cd1e6f9e | 884 | .compatible = "samsung,s3c6410-rtc", |
ae05c950 | 885 | .data = (void *)&s3c6410_rtc_data, |
df9e26d0 CC |
886 | }, { |
887 | .compatible = "samsung,exynos3250-rtc", | |
888 | .data = (void *)&exynos3250_rtc_data, | |
d2524caa | 889 | }, |
ae05c950 | 890 | { /* sentinel */ }, |
39ce4084 TA |
891 | }; |
892 | MODULE_DEVICE_TABLE(of, s3c_rtc_dt_match); | |
9f4123b7 MC |
893 | |
894 | static struct platform_driver s3c_rtc_driver = { | |
1add6781 | 895 | .probe = s3c_rtc_probe, |
5a167f45 | 896 | .remove = s3c_rtc_remove, |
1add6781 | 897 | .driver = { |
9f4123b7 | 898 | .name = "s3c-rtc", |
32e445aa | 899 | .pm = &s3c_rtc_pm_ops, |
04a373fd | 900 | .of_match_table = of_match_ptr(s3c_rtc_dt_match), |
1add6781 BD |
901 | }, |
902 | }; | |
0c4eae66 | 903 | module_platform_driver(s3c_rtc_driver); |
1add6781 BD |
904 | |
905 | MODULE_DESCRIPTION("Samsung S3C RTC Driver"); | |
906 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | |
907 | MODULE_LICENSE("GPL"); | |
ad28a07b | 908 | MODULE_ALIAS("platform:s3c2410-rtc"); |