rtc: s3c: define s3c_rtc structure to remove global variables.
[deliverable/linux.git] / drivers / rtc / rtc-s3c.c
CommitLineData
1add6781 1/* drivers/rtc/rtc-s3c.c
e48add8c
AD
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
1add6781
BD
5 *
6 * Copyright (c) 2004,2006 Simtec Electronics
7 * Ben Dooks, <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * S3C2410/S3C2440/S3C24XX Internal RTC Driver
15*/
16
17#include <linux/module.h>
18#include <linux/fs.h>
19#include <linux/string.h>
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/interrupt.h>
23#include <linux/rtc.h>
24#include <linux/bcd.h>
25#include <linux/clk.h>
9974b6ea 26#include <linux/log2.h>
5a0e3ad6 27#include <linux/slab.h>
39ce4084 28#include <linux/of.h>
dbd9acbe
SK
29#include <linux/uaccess.h>
30#include <linux/io.h>
1add6781 31
1add6781 32#include <asm/irq.h>
b9d7c5d3 33#include "rtc-s3c.h"
1add6781 34
9f4123b7
MC
35enum s3c_cpu_type {
36 TYPE_S3C2410,
25c1a246
HS
37 TYPE_S3C2416,
38 TYPE_S3C2443,
9f4123b7
MC
39 TYPE_S3C64XX,
40};
41
c3cba928
TB
42struct s3c_rtc_drv_data {
43 int cpu_type;
44};
45
19be09f5
CC
46struct s3c_rtc {
47 struct device *dev;
48 struct rtc_device *rtc;
49
50 void __iomem *base;
51 struct clk *rtc_clk;
52 bool enabled;
53
54 enum s3c_cpu_type cpu_type;
1add6781 55
19be09f5
CC
56 int irq_alarm;
57 int irq_tick;
1add6781 58
19be09f5
CC
59 spinlock_t pie_lock;
60 spinlock_t alarm_clk_lock;
1add6781 61
19be09f5
CC
62 int ticnt_save, ticnt_en_save;
63 bool wake_en;
64};
65
66static void s3c_rtc_alarm_clk_enable(struct s3c_rtc *info, bool enable)
88cee8fd 67{
88cee8fd
DK
68 unsigned long irq_flags;
69
19be09f5 70 spin_lock_irqsave(&info->alarm_clk_lock, irq_flags);
88cee8fd 71 if (enable) {
19be09f5
CC
72 if (!info->enabled) {
73 clk_enable(info->rtc_clk);
74 info->enabled = true;
88cee8fd
DK
75 }
76 } else {
19be09f5
CC
77 if (info->enabled) {
78 clk_disable(info->rtc_clk);
79 info->enabled = false;
88cee8fd
DK
80 }
81 }
19be09f5 82 spin_unlock_irqrestore(&info->alarm_clk_lock, irq_flags);
88cee8fd
DK
83}
84
1add6781 85/* IRQ Handlers */
7d12e780 86static irqreturn_t s3c_rtc_alarmirq(int irq, void *id)
1add6781 87{
19be09f5 88 struct s3c_rtc *info = (struct s3c_rtc *)id;
1add6781 89
19be09f5
CC
90 clk_enable(info->rtc_clk);
91 rtc_update_irq(info->rtc, 1, RTC_AF | RTC_IRQF);
2f3478f6 92
19be09f5
CC
93 if (info->cpu_type == TYPE_S3C64XX)
94 writeb(S3C2410_INTP_ALM, info->base + S3C2410_INTP);
2f3478f6 95
19be09f5 96 clk_disable(info->rtc_clk);
88cee8fd 97
19be09f5 98 s3c_rtc_alarm_clk_enable(info, false);
88cee8fd 99
1add6781
BD
100 return IRQ_HANDLED;
101}
102
7d12e780 103static irqreturn_t s3c_rtc_tickirq(int irq, void *id)
1add6781 104{
19be09f5 105 struct s3c_rtc *info = (struct s3c_rtc *)id;
1add6781 106
19be09f5
CC
107 clk_enable(info->rtc_clk);
108 rtc_update_irq(info->rtc, 1, RTC_PF | RTC_IRQF);
2f3478f6 109
19be09f5
CC
110 if (info->cpu_type == TYPE_S3C64XX)
111 writeb(S3C2410_INTP_TIC, info->base + S3C2410_INTP);
112
113 clk_disable(info->rtc_clk);
2f3478f6 114
1add6781
BD
115 return IRQ_HANDLED;
116}
117
118/* Update control registers */
2ec38a03 119static int s3c_rtc_setaie(struct device *dev, unsigned int enabled)
1add6781 120{
19be09f5 121 struct s3c_rtc *info = dev_get_drvdata(dev);
1add6781
BD
122 unsigned int tmp;
123
19be09f5 124 dev_dbg(info->dev, "%s: aie=%d\n", __func__, enabled);
1add6781 125
19be09f5
CC
126 clk_enable(info->rtc_clk);
127 tmp = readb(info->base + S3C2410_RTCALM) & ~S3C2410_RTCALM_ALMEN;
1add6781 128
2ec38a03 129 if (enabled)
1add6781
BD
130 tmp |= S3C2410_RTCALM_ALMEN;
131
19be09f5
CC
132 writeb(tmp, info->base + S3C2410_RTCALM);
133 clk_disable(info->rtc_clk);
2ec38a03 134
19be09f5 135 s3c_rtc_alarm_clk_enable(info, enabled);
88cee8fd 136
2ec38a03 137 return 0;
1add6781
BD
138}
139
19be09f5 140static int s3c_rtc_setfreq(struct s3c_rtc *info, int freq)
1add6781 141{
9f4123b7 142 unsigned int tmp = 0;
25c1a246 143 int val;
1add6781 144
5d2a5037
JC
145 if (!is_power_of_2(freq))
146 return -EINVAL;
147
19be09f5
CC
148 clk_enable(info->rtc_clk);
149 spin_lock_irq(&info->pie_lock);
1add6781 150
19be09f5
CC
151 if (info->cpu_type != TYPE_S3C64XX) {
152 tmp = readb(info->base + S3C2410_TICNT);
9f4123b7
MC
153 tmp &= S3C2410_TICNT_ENABLE;
154 }
155
19be09f5 156 val = (info->rtc->max_user_freq / freq) - 1;
25c1a246 157
19be09f5 158 if (info->cpu_type == TYPE_S3C2416 || info->cpu_type == TYPE_S3C2443) {
25c1a246 159 tmp |= S3C2443_TICNT_PART(val);
19be09f5 160 writel(S3C2443_TICNT1_PART(val), info->base + S3C2443_TICNT1);
25c1a246 161
19be09f5
CC
162 if (info->cpu_type == TYPE_S3C2416)
163 writel(S3C2416_TICNT2_PART(val),
164 info->base + S3C2416_TICNT2);
25c1a246
HS
165 } else {
166 tmp |= val;
167 }
1add6781 168
19be09f5
CC
169 writel(tmp, info->base + S3C2410_TICNT);
170 spin_unlock_irq(&info->pie_lock);
171 clk_disable(info->rtc_clk);
773be7ee
BD
172
173 return 0;
1add6781
BD
174}
175
176/* Time read/write */
177
178static int s3c_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
179{
19be09f5 180 struct s3c_rtc *info = dev_get_drvdata(dev);
1add6781
BD
181 unsigned int have_retried = 0;
182
19be09f5 183 clk_enable(info->rtc_clk);
1add6781 184 retry_get_time:
19be09f5
CC
185 rtc_tm->tm_min = readb(info->base + S3C2410_RTCMIN);
186 rtc_tm->tm_hour = readb(info->base + S3C2410_RTCHOUR);
187 rtc_tm->tm_mday = readb(info->base + S3C2410_RTCDATE);
188 rtc_tm->tm_mon = readb(info->base + S3C2410_RTCMON);
189 rtc_tm->tm_year = readb(info->base + S3C2410_RTCYEAR);
190 rtc_tm->tm_sec = readb(info->base + S3C2410_RTCSEC);
1add6781 191
48fc7f7e 192 /* the only way to work out whether the system was mid-update
1add6781
BD
193 * when we read it is to check the second counter, and if it
194 * is zero, then we re-try the entire read
195 */
196
197 if (rtc_tm->tm_sec == 0 && !have_retried) {
198 have_retried = 1;
199 goto retry_get_time;
200 }
201
fe20ba70
AB
202 rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec);
203 rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min);
204 rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour);
205 rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday);
206 rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon);
207 rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year);
1add6781
BD
208
209 rtc_tm->tm_year += 100;
4e8896cd 210
d4a48c2a 211 dev_dbg(dev, "read time %04d.%02d.%02d %02d:%02d:%02d\n",
4e8896cd
MH
212 1900 + rtc_tm->tm_year, rtc_tm->tm_mon, rtc_tm->tm_mday,
213 rtc_tm->tm_hour, rtc_tm->tm_min, rtc_tm->tm_sec);
214
1add6781
BD
215 rtc_tm->tm_mon -= 1;
216
19be09f5
CC
217 clk_disable(info->rtc_clk);
218
5b3ffddd 219 return rtc_valid_tm(rtc_tm);
1add6781
BD
220}
221
222static int s3c_rtc_settime(struct device *dev, struct rtc_time *tm)
223{
19be09f5 224 struct s3c_rtc *info = dev_get_drvdata(dev);
641741e0 225 int year = tm->tm_year - 100;
9a654518 226
d4a48c2a 227 dev_dbg(dev, "set time %04d.%02d.%02d %02d:%02d:%02d\n",
30ffc40c 228 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
641741e0
BD
229 tm->tm_hour, tm->tm_min, tm->tm_sec);
230
231 /* we get around y2k by simply not supporting it */
1add6781 232
641741e0 233 if (year < 0 || year >= 100) {
9a654518 234 dev_err(dev, "rtc only supports 100 years\n");
1add6781 235 return -EINVAL;
9a654518
BD
236 }
237
19be09f5
CC
238 clk_enable(info->rtc_clk);
239
240 writeb(bin2bcd(tm->tm_sec), info->base + S3C2410_RTCSEC);
241 writeb(bin2bcd(tm->tm_min), info->base + S3C2410_RTCMIN);
242 writeb(bin2bcd(tm->tm_hour), info->base + S3C2410_RTCHOUR);
243 writeb(bin2bcd(tm->tm_mday), info->base + S3C2410_RTCDATE);
244 writeb(bin2bcd(tm->tm_mon + 1), info->base + S3C2410_RTCMON);
245 writeb(bin2bcd(year), info->base + S3C2410_RTCYEAR);
246
247 clk_disable(info->rtc_clk);
1add6781
BD
248
249 return 0;
250}
251
252static int s3c_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm)
253{
19be09f5 254 struct s3c_rtc *info = dev_get_drvdata(dev);
1add6781
BD
255 struct rtc_time *alm_tm = &alrm->time;
256 unsigned int alm_en;
257
19be09f5
CC
258 clk_enable(info->rtc_clk);
259 alm_tm->tm_sec = readb(info->base + S3C2410_ALMSEC);
260 alm_tm->tm_min = readb(info->base + S3C2410_ALMMIN);
261 alm_tm->tm_hour = readb(info->base + S3C2410_ALMHOUR);
262 alm_tm->tm_mon = readb(info->base + S3C2410_ALMMON);
263 alm_tm->tm_mday = readb(info->base + S3C2410_ALMDATE);
264 alm_tm->tm_year = readb(info->base + S3C2410_ALMYEAR);
1add6781 265
19be09f5 266 alm_en = readb(info->base + S3C2410_RTCALM);
1add6781 267
a2db8dfc
DB
268 alrm->enabled = (alm_en & S3C2410_RTCALM_ALMEN) ? 1 : 0;
269
d4a48c2a 270 dev_dbg(dev, "read alarm %d, %04d.%02d.%02d %02d:%02d:%02d\n",
1add6781 271 alm_en,
30ffc40c 272 1900 + alm_tm->tm_year, alm_tm->tm_mon, alm_tm->tm_mday,
1add6781
BD
273 alm_tm->tm_hour, alm_tm->tm_min, alm_tm->tm_sec);
274
275
276 /* decode the alarm enable field */
277
278 if (alm_en & S3C2410_RTCALM_SECEN)
fe20ba70 279 alm_tm->tm_sec = bcd2bin(alm_tm->tm_sec);
1add6781 280 else
dd061d1a 281 alm_tm->tm_sec = -1;
1add6781
BD
282
283 if (alm_en & S3C2410_RTCALM_MINEN)
fe20ba70 284 alm_tm->tm_min = bcd2bin(alm_tm->tm_min);
1add6781 285 else
dd061d1a 286 alm_tm->tm_min = -1;
1add6781
BD
287
288 if (alm_en & S3C2410_RTCALM_HOUREN)
fe20ba70 289 alm_tm->tm_hour = bcd2bin(alm_tm->tm_hour);
1add6781 290 else
dd061d1a 291 alm_tm->tm_hour = -1;
1add6781
BD
292
293 if (alm_en & S3C2410_RTCALM_DAYEN)
fe20ba70 294 alm_tm->tm_mday = bcd2bin(alm_tm->tm_mday);
1add6781 295 else
dd061d1a 296 alm_tm->tm_mday = -1;
1add6781
BD
297
298 if (alm_en & S3C2410_RTCALM_MONEN) {
fe20ba70 299 alm_tm->tm_mon = bcd2bin(alm_tm->tm_mon);
1add6781
BD
300 alm_tm->tm_mon -= 1;
301 } else {
dd061d1a 302 alm_tm->tm_mon = -1;
1add6781
BD
303 }
304
305 if (alm_en & S3C2410_RTCALM_YEAREN)
fe20ba70 306 alm_tm->tm_year = bcd2bin(alm_tm->tm_year);
1add6781 307 else
dd061d1a 308 alm_tm->tm_year = -1;
1add6781 309
19be09f5 310 clk_disable(info->rtc_clk);
1add6781
BD
311 return 0;
312}
313
314static int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
315{
19be09f5 316 struct s3c_rtc *info = dev_get_drvdata(dev);
1add6781
BD
317 struct rtc_time *tm = &alrm->time;
318 unsigned int alrm_en;
319
19be09f5 320 clk_enable(info->rtc_clk);
d4a48c2a 321 dev_dbg(dev, "s3c_rtc_setalarm: %d, %04d.%02d.%02d %02d:%02d:%02d\n",
1add6781 322 alrm->enabled,
4e8896cd 323 1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday,
30ffc40c 324 tm->tm_hour, tm->tm_min, tm->tm_sec);
1add6781 325
19be09f5
CC
326 alrm_en = readb(info->base + S3C2410_RTCALM) & S3C2410_RTCALM_ALMEN;
327 writeb(0x00, info->base + S3C2410_RTCALM);
1add6781
BD
328
329 if (tm->tm_sec < 60 && tm->tm_sec >= 0) {
330 alrm_en |= S3C2410_RTCALM_SECEN;
19be09f5 331 writeb(bin2bcd(tm->tm_sec), info->base + S3C2410_ALMSEC);
1add6781
BD
332 }
333
334 if (tm->tm_min < 60 && tm->tm_min >= 0) {
335 alrm_en |= S3C2410_RTCALM_MINEN;
19be09f5 336 writeb(bin2bcd(tm->tm_min), info->base + S3C2410_ALMMIN);
1add6781
BD
337 }
338
339 if (tm->tm_hour < 24 && tm->tm_hour >= 0) {
340 alrm_en |= S3C2410_RTCALM_HOUREN;
19be09f5 341 writeb(bin2bcd(tm->tm_hour), info->base + S3C2410_ALMHOUR);
1add6781
BD
342 }
343
d4a48c2a 344 dev_dbg(dev, "setting S3C2410_RTCALM to %08x\n", alrm_en);
1add6781 345
19be09f5 346 writeb(alrm_en, info->base + S3C2410_RTCALM);
1add6781 347
2ec38a03 348 s3c_rtc_setaie(dev, alrm->enabled);
1add6781 349
19be09f5
CC
350 clk_disable(info->rtc_clk);
351
1add6781
BD
352 return 0;
353}
354
1add6781
BD
355static int s3c_rtc_proc(struct device *dev, struct seq_file *seq)
356{
19be09f5 357 struct s3c_rtc *info = dev_get_drvdata(dev);
9f4123b7 358 unsigned int ticnt;
1add6781 359
19be09f5
CC
360 clk_enable(info->rtc_clk);
361 if (info->cpu_type == TYPE_S3C64XX) {
362 ticnt = readw(info->base + S3C2410_RTCCON);
9f4123b7
MC
363 ticnt &= S3C64XX_RTCCON_TICEN;
364 } else {
19be09f5 365 ticnt = readb(info->base + S3C2410_TICNT);
9f4123b7
MC
366 ticnt &= S3C2410_TICNT_ENABLE;
367 }
368
369 seq_printf(seq, "periodic_IRQ\t: %s\n", ticnt ? "yes" : "no");
19be09f5 370 clk_disable(info->rtc_clk);
1add6781
BD
371 return 0;
372}
373
ff8371ac 374static const struct rtc_class_ops s3c_rtcops = {
1add6781
BD
375 .read_time = s3c_rtc_gettime,
376 .set_time = s3c_rtc_settime,
377 .read_alarm = s3c_rtc_getalarm,
378 .set_alarm = s3c_rtc_setalarm,
e6eb524e
CY
379 .proc = s3c_rtc_proc,
380 .alarm_irq_enable = s3c_rtc_setaie,
1add6781
BD
381};
382
19be09f5 383static void s3c_rtc_enable(struct s3c_rtc *info, int en)
1add6781
BD
384{
385 unsigned int tmp;
386
19be09f5 387 clk_enable(info->rtc_clk);
1add6781 388 if (!en) {
19be09f5
CC
389 tmp = readw(info->base + S3C2410_RTCCON);
390 if (info->cpu_type == TYPE_S3C64XX)
9f4123b7
MC
391 tmp &= ~S3C64XX_RTCCON_TICEN;
392 tmp &= ~S3C2410_RTCCON_RTCEN;
19be09f5 393 writew(tmp, info->base + S3C2410_RTCCON);
9f4123b7 394
19be09f5
CC
395 if (info->cpu_type != TYPE_S3C64XX) {
396 tmp = readb(info->base + S3C2410_TICNT);
9f4123b7 397 tmp &= ~S3C2410_TICNT_ENABLE;
19be09f5 398 writeb(tmp, info->base + S3C2410_TICNT);
9f4123b7 399 }
1add6781
BD
400 } else {
401 /* re-enable the device, and check it is ok */
402
19be09f5
CC
403 if ((readw(info->base + S3C2410_RTCCON) & S3C2410_RTCCON_RTCEN) == 0) {
404 dev_info(info->dev, "rtc disabled, re-enabling\n");
1add6781 405
19be09f5 406 tmp = readw(info->base + S3C2410_RTCCON);
f61ae671 407 writew(tmp | S3C2410_RTCCON_RTCEN,
19be09f5 408 info->base + S3C2410_RTCCON);
1add6781
BD
409 }
410
19be09f5
CC
411 if ((readw(info->base + S3C2410_RTCCON) & S3C2410_RTCCON_CNTSEL)) {
412 dev_info(info->dev, "removing RTCCON_CNTSEL\n");
1add6781 413
19be09f5 414 tmp = readw(info->base + S3C2410_RTCCON);
f61ae671 415 writew(tmp & ~S3C2410_RTCCON_CNTSEL,
19be09f5 416 info->base + S3C2410_RTCCON);
1add6781
BD
417 }
418
19be09f5
CC
419 if ((readw(info->base + S3C2410_RTCCON) & S3C2410_RTCCON_CLKRST)) {
420 dev_info(info->dev, "removing RTCCON_CLKRST\n");
1add6781 421
19be09f5 422 tmp = readw(info->base + S3C2410_RTCCON);
f61ae671 423 writew(tmp & ~S3C2410_RTCCON_CLKRST,
19be09f5 424 info->base + S3C2410_RTCCON);
1add6781
BD
425 }
426 }
19be09f5 427 clk_disable(info->rtc_clk);
1add6781
BD
428}
429
19be09f5 430static int s3c_rtc_remove(struct platform_device *pdev)
1add6781 431{
19be09f5
CC
432 struct s3c_rtc *info = platform_get_drvdata(pdev);
433
434 s3c_rtc_setaie(info->dev, 0);
1add6781 435
19be09f5
CC
436 clk_unprepare(info->rtc_clk);
437 info->rtc_clk = NULL;
e48add8c 438
1add6781
BD
439 return 0;
440}
441
d2524caa
HS
442static const struct of_device_id s3c_rtc_dt_match[];
443
444static inline int s3c_rtc_get_driver_data(struct platform_device *pdev)
445{
446#ifdef CONFIG_OF
c3cba928 447 struct s3c_rtc_drv_data *data;
d2524caa
HS
448 if (pdev->dev.of_node) {
449 const struct of_device_id *match;
450 match = of_match_node(s3c_rtc_dt_match, pdev->dev.of_node);
c3cba928
TB
451 data = (struct s3c_rtc_drv_data *) match->data;
452 return data->cpu_type;
d2524caa
HS
453 }
454#endif
455 return platform_get_device_id(pdev)->driver_data;
456}
457
5a167f45 458static int s3c_rtc_probe(struct platform_device *pdev)
1add6781 459{
19be09f5 460 struct s3c_rtc *info = NULL;
e1df962e 461 struct rtc_time rtc_tm;
1add6781
BD
462 struct resource *res;
463 int ret;
25c1a246 464 int tmp;
1add6781 465
19be09f5
CC
466 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
467 if (!info)
468 return -ENOMEM;
1add6781
BD
469
470 /* find the IRQs */
19be09f5
CC
471 info->irq_tick = platform_get_irq(pdev, 1);
472 if (info->irq_tick < 0) {
1add6781 473 dev_err(&pdev->dev, "no irq for rtc tick\n");
19be09f5 474 return info->irq_tick;
1add6781
BD
475 }
476
19be09f5
CC
477 info->dev = &pdev->dev;
478 info->cpu_type = s3c_rtc_get_driver_data(pdev);
479 spin_lock_init(&info->pie_lock);
480 spin_lock_init(&info->alarm_clk_lock);
481
482 platform_set_drvdata(pdev, info);
483
484 info->irq_alarm = platform_get_irq(pdev, 0);
485 if (info->irq_alarm < 0) {
1add6781 486 dev_err(&pdev->dev, "no irq for alarm\n");
19be09f5 487 return info->irq_alarm;
1add6781
BD
488 }
489
d4a48c2a 490 dev_dbg(&pdev->dev, "s3c2410_rtc: tick irq %d, alarm irq %d\n",
19be09f5 491 info->irq_tick, info->irq_alarm);
1add6781
BD
492
493 /* get the memory region */
1add6781 494 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
19be09f5
CC
495 info->base = devm_ioremap_resource(&pdev->dev, res);
496 if (IS_ERR(info->base))
497 return PTR_ERR(info->base);
1add6781 498
19be09f5
CC
499 info->rtc_clk = devm_clk_get(&pdev->dev, "rtc");
500 if (IS_ERR(info->rtc_clk)) {
e48add8c 501 dev_err(&pdev->dev, "failed to find rtc clock source\n");
19be09f5 502 return PTR_ERR(info->rtc_clk);
e48add8c 503 }
19be09f5 504 clk_prepare_enable(info->rtc_clk);
e48add8c 505
1add6781 506 /* check to see if everything is setup correctly */
19be09f5 507 s3c_rtc_enable(info, 1);
1add6781 508
d4a48c2a 509 dev_dbg(&pdev->dev, "s3c2410_rtc: RTCCON=%02x\n",
19be09f5 510 readw(info->base + S3C2410_RTCCON));
1add6781 511
51b7616e
YK
512 device_init_wakeup(&pdev->dev, 1);
513
1add6781 514 /* register RTC and exit */
19be09f5 515 info->rtc = devm_rtc_device_register(&pdev->dev, "s3c", &s3c_rtcops,
1add6781 516 THIS_MODULE);
19be09f5 517 if (IS_ERR(info->rtc)) {
1add6781 518 dev_err(&pdev->dev, "cannot attach rtc\n");
19be09f5 519 ret = PTR_ERR(info->rtc);
1add6781
BD
520 goto err_nortc;
521 }
522
19be09f5
CC
523 ret = devm_request_irq(&pdev->dev, info->irq_alarm, s3c_rtc_alarmirq,
524 0, "s3c2410-rtc alarm", info);
525 if (ret) {
526 dev_err(&pdev->dev, "IRQ%d error %d\n", info->irq_alarm, ret);
527 goto err_nortc;
528 }
eaa6e4dd 529
19be09f5
CC
530 ret = devm_request_irq(&pdev->dev, info->irq_tick, s3c_rtc_tickirq,
531 0, "s3c2410-rtc tick", info);
532 if (ret) {
533 dev_err(&pdev->dev, "IRQ%d error %d\n", info->irq_tick, ret);
534 goto err_nortc;
535 }
051fe54e 536
19be09f5
CC
537 /* Check RTC Time */
538 s3c_rtc_gettime(&pdev->dev, &rtc_tm);
051fe54e 539
e1df962e
CY
540 if (rtc_valid_tm(&rtc_tm)) {
541 rtc_tm.tm_year = 100;
542 rtc_tm.tm_mon = 0;
543 rtc_tm.tm_mday = 1;
544 rtc_tm.tm_hour = 0;
545 rtc_tm.tm_min = 0;
546 rtc_tm.tm_sec = 0;
547
19be09f5 548 s3c_rtc_settime(&pdev->dev, &rtc_tm);
e1df962e
CY
549
550 dev_warn(&pdev->dev, "warning: invalid RTC value so initializing it\n");
051fe54e
TK
551 }
552
19be09f5
CC
553 if (info->cpu_type != TYPE_S3C2410)
554 info->rtc->max_user_freq = 32768;
9f4123b7 555 else
19be09f5 556 info->rtc->max_user_freq = 128;
9f4123b7 557
19be09f5
CC
558 if (info->cpu_type == TYPE_S3C2416 || info->cpu_type == TYPE_S3C2443) {
559 tmp = readw(info->base + S3C2410_RTCCON);
25c1a246 560 tmp |= S3C2443_RTCCON_TICSEL;
19be09f5 561 writew(tmp, info->base + S3C2410_RTCCON);
62d17601
MH
562 }
563
19be09f5 564 s3c_rtc_setfreq(info, 1);
62d17601 565
19be09f5 566 clk_disable(info->rtc_clk);
cefe4fbb 567
1add6781
BD
568 return 0;
569
570 err_nortc:
19be09f5
CC
571 s3c_rtc_enable(info, 0);
572 clk_disable_unprepare(info->rtc_clk);
1add6781 573
1add6781
BD
574 return ret;
575}
576
32e445aa 577#ifdef CONFIG_PM_SLEEP
1add6781 578
32e445aa 579static int s3c_rtc_suspend(struct device *dev)
1add6781 580{
19be09f5 581 struct s3c_rtc *info = dev_get_drvdata(dev);
32e445aa 582
19be09f5 583 clk_enable(info->rtc_clk);
1add6781 584 /* save TICNT for anyone using periodic interrupts */
19be09f5
CC
585 if (info->cpu_type == TYPE_S3C64XX) {
586 info->ticnt_en_save = readw(info->base + S3C2410_RTCCON);
587 info->ticnt_en_save &= S3C64XX_RTCCON_TICEN;
588 info->ticnt_save = readl(info->base + S3C2410_TICNT);
40d2d968 589 } else {
19be09f5 590 info->ticnt_save = readb(info->base + S3C2410_TICNT);
9f4123b7 591 }
19be09f5 592 s3c_rtc_enable(info, 0);
f501ed52 593
19be09f5
CC
594 if (device_may_wakeup(dev) && !info->wake_en) {
595 if (enable_irq_wake(info->irq_alarm) == 0)
596 info->wake_en = true;
52cd4e5c 597 else
32e445aa 598 dev_err(dev, "enable_irq_wake failed\n");
52cd4e5c 599 }
19be09f5 600 clk_disable(info->rtc_clk);
f501ed52 601
1add6781
BD
602 return 0;
603}
604
32e445aa 605static int s3c_rtc_resume(struct device *dev)
1add6781 606{
19be09f5 607 struct s3c_rtc *info = dev_get_drvdata(dev);
9f4123b7
MC
608 unsigned int tmp;
609
19be09f5
CC
610 clk_enable(info->rtc_clk);
611 s3c_rtc_enable(info, 1);
612 if (info->cpu_type == TYPE_S3C64XX) {
613 writel(info->ticnt_save, info->base + S3C2410_TICNT);
614 if (info->ticnt_en_save) {
615 tmp = readw(info->base + S3C2410_RTCCON);
616 writew(tmp | info->ticnt_en_save,
617 info->base + S3C2410_RTCCON);
40d2d968
VS
618 }
619 } else {
19be09f5 620 writeb(info->ticnt_save, info->base + S3C2410_TICNT);
9f4123b7 621 }
f501ed52 622
19be09f5
CC
623 if (device_may_wakeup(dev) && info->wake_en) {
624 disable_irq_wake(info->irq_alarm);
625 info->wake_en = false;
52cd4e5c 626 }
19be09f5 627 clk_disable(info->rtc_clk);
f501ed52 628
1add6781
BD
629 return 0;
630}
1add6781 631#endif
32e445aa
JH
632static SIMPLE_DEV_PM_OPS(s3c_rtc_pm_ops, s3c_rtc_suspend, s3c_rtc_resume);
633
ecb41a77 634#ifdef CONFIG_OF
c3cba928
TB
635static struct s3c_rtc_drv_data s3c_rtc_drv_data_array[] = {
636 [TYPE_S3C2410] = { TYPE_S3C2410 },
637 [TYPE_S3C2416] = { TYPE_S3C2416 },
638 [TYPE_S3C2443] = { TYPE_S3C2443 },
639 [TYPE_S3C64XX] = { TYPE_S3C64XX },
640};
641
39ce4084 642static const struct of_device_id s3c_rtc_dt_match[] = {
d2524caa 643 {
cd1e6f9e 644 .compatible = "samsung,s3c2410-rtc",
c3cba928 645 .data = &s3c_rtc_drv_data_array[TYPE_S3C2410],
25c1a246 646 }, {
cd1e6f9e 647 .compatible = "samsung,s3c2416-rtc",
c3cba928 648 .data = &s3c_rtc_drv_data_array[TYPE_S3C2416],
25c1a246 649 }, {
cd1e6f9e 650 .compatible = "samsung,s3c2443-rtc",
c3cba928 651 .data = &s3c_rtc_drv_data_array[TYPE_S3C2443],
d2524caa 652 }, {
cd1e6f9e 653 .compatible = "samsung,s3c6410-rtc",
c3cba928 654 .data = &s3c_rtc_drv_data_array[TYPE_S3C64XX],
d2524caa 655 },
39ce4084
TA
656 {},
657};
658MODULE_DEVICE_TABLE(of, s3c_rtc_dt_match);
39ce4084
TA
659#endif
660
9f4123b7
MC
661static struct platform_device_id s3c_rtc_driver_ids[] = {
662 {
663 .name = "s3c2410-rtc",
664 .driver_data = TYPE_S3C2410,
25c1a246
HS
665 }, {
666 .name = "s3c2416-rtc",
667 .driver_data = TYPE_S3C2416,
668 }, {
669 .name = "s3c2443-rtc",
670 .driver_data = TYPE_S3C2443,
9f4123b7
MC
671 }, {
672 .name = "s3c64xx-rtc",
673 .driver_data = TYPE_S3C64XX,
674 },
675 { }
676};
677
678MODULE_DEVICE_TABLE(platform, s3c_rtc_driver_ids);
679
680static struct platform_driver s3c_rtc_driver = {
1add6781 681 .probe = s3c_rtc_probe,
5a167f45 682 .remove = s3c_rtc_remove,
9f4123b7 683 .id_table = s3c_rtc_driver_ids,
1add6781 684 .driver = {
9f4123b7 685 .name = "s3c-rtc",
1add6781 686 .owner = THIS_MODULE,
32e445aa 687 .pm = &s3c_rtc_pm_ops,
04a373fd 688 .of_match_table = of_match_ptr(s3c_rtc_dt_match),
1add6781
BD
689 },
690};
691
0c4eae66 692module_platform_driver(s3c_rtc_driver);
1add6781
BD
693
694MODULE_DESCRIPTION("Samsung S3C RTC Driver");
695MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
696MODULE_LICENSE("GPL");
ad28a07b 697MODULE_ALIAS("platform:s3c2410-rtc");
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