Commit | Line | Data |
---|---|---|
1add6781 | 1 | /* drivers/rtc/rtc-s3c.c |
e48add8c AD |
2 | * |
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com/ | |
1add6781 BD |
5 | * |
6 | * Copyright (c) 2004,2006 Simtec Electronics | |
7 | * Ben Dooks, <ben@simtec.co.uk> | |
8 | * http://armlinux.simtec.co.uk/ | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * S3C2410/S3C2440/S3C24XX Internal RTC Driver | |
15 | */ | |
16 | ||
17 | #include <linux/module.h> | |
18 | #include <linux/fs.h> | |
19 | #include <linux/string.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/rtc.h> | |
24 | #include <linux/bcd.h> | |
25 | #include <linux/clk.h> | |
9974b6ea | 26 | #include <linux/log2.h> |
5a0e3ad6 | 27 | #include <linux/slab.h> |
39ce4084 | 28 | #include <linux/of.h> |
1add6781 | 29 | |
a09e64fb | 30 | #include <mach/hardware.h> |
1add6781 BD |
31 | #include <asm/uaccess.h> |
32 | #include <asm/io.h> | |
33 | #include <asm/irq.h> | |
e2cd00cf | 34 | #include <plat/regs-rtc.h> |
1add6781 | 35 | |
9f4123b7 MC |
36 | enum s3c_cpu_type { |
37 | TYPE_S3C2410, | |
38 | TYPE_S3C64XX, | |
39 | }; | |
40 | ||
1add6781 BD |
41 | /* I have yet to find an S3C implementation with more than one |
42 | * of these rtc blocks in */ | |
43 | ||
44 | static struct resource *s3c_rtc_mem; | |
45 | ||
e48add8c | 46 | static struct clk *rtc_clk; |
1add6781 BD |
47 | static void __iomem *s3c_rtc_base; |
48 | static int s3c_rtc_alarmno = NO_IRQ; | |
49 | static int s3c_rtc_tickno = NO_IRQ; | |
52cd4e5c | 50 | static bool wake_en; |
9f4123b7 | 51 | static enum s3c_cpu_type s3c_rtc_cpu_type; |
1add6781 BD |
52 | |
53 | static DEFINE_SPINLOCK(s3c_rtc_pie_lock); | |
1add6781 | 54 | |
88cee8fd DK |
55 | static void s3c_rtc_alarm_clk_enable(bool enable) |
56 | { | |
57 | static DEFINE_SPINLOCK(s3c_rtc_alarm_clk_lock); | |
58 | static bool alarm_clk_enabled; | |
59 | unsigned long irq_flags; | |
60 | ||
61 | spin_lock_irqsave(&s3c_rtc_alarm_clk_lock, irq_flags); | |
62 | if (enable) { | |
63 | if (!alarm_clk_enabled) { | |
64 | clk_enable(rtc_clk); | |
65 | alarm_clk_enabled = true; | |
66 | } | |
67 | } else { | |
68 | if (alarm_clk_enabled) { | |
69 | clk_disable(rtc_clk); | |
70 | alarm_clk_enabled = false; | |
71 | } | |
72 | } | |
73 | spin_unlock_irqrestore(&s3c_rtc_alarm_clk_lock, irq_flags); | |
74 | } | |
75 | ||
1add6781 BD |
76 | /* IRQ Handlers */ |
77 | ||
7d12e780 | 78 | static irqreturn_t s3c_rtc_alarmirq(int irq, void *id) |
1add6781 BD |
79 | { |
80 | struct rtc_device *rdev = id; | |
81 | ||
cefe4fbb | 82 | clk_enable(rtc_clk); |
ab6a2d70 | 83 | rtc_update_irq(rdev, 1, RTC_AF | RTC_IRQF); |
2f3478f6 AD |
84 | |
85 | if (s3c_rtc_cpu_type == TYPE_S3C64XX) | |
86 | writeb(S3C2410_INTP_ALM, s3c_rtc_base + S3C2410_INTP); | |
87 | ||
cefe4fbb | 88 | clk_disable(rtc_clk); |
88cee8fd DK |
89 | |
90 | s3c_rtc_alarm_clk_enable(false); | |
91 | ||
1add6781 BD |
92 | return IRQ_HANDLED; |
93 | } | |
94 | ||
7d12e780 | 95 | static irqreturn_t s3c_rtc_tickirq(int irq, void *id) |
1add6781 BD |
96 | { |
97 | struct rtc_device *rdev = id; | |
98 | ||
cefe4fbb | 99 | clk_enable(rtc_clk); |
773be7ee | 100 | rtc_update_irq(rdev, 1, RTC_PF | RTC_IRQF); |
2f3478f6 AD |
101 | |
102 | if (s3c_rtc_cpu_type == TYPE_S3C64XX) | |
103 | writeb(S3C2410_INTP_TIC, s3c_rtc_base + S3C2410_INTP); | |
104 | ||
cefe4fbb | 105 | clk_disable(rtc_clk); |
1add6781 BD |
106 | return IRQ_HANDLED; |
107 | } | |
108 | ||
109 | /* Update control registers */ | |
2ec38a03 | 110 | static int s3c_rtc_setaie(struct device *dev, unsigned int enabled) |
1add6781 BD |
111 | { |
112 | unsigned int tmp; | |
113 | ||
2ec38a03 | 114 | pr_debug("%s: aie=%d\n", __func__, enabled); |
1add6781 | 115 | |
cefe4fbb | 116 | clk_enable(rtc_clk); |
9a654518 | 117 | tmp = readb(s3c_rtc_base + S3C2410_RTCALM) & ~S3C2410_RTCALM_ALMEN; |
1add6781 | 118 | |
2ec38a03 | 119 | if (enabled) |
1add6781 BD |
120 | tmp |= S3C2410_RTCALM_ALMEN; |
121 | ||
9a654518 | 122 | writeb(tmp, s3c_rtc_base + S3C2410_RTCALM); |
cefe4fbb | 123 | clk_disable(rtc_clk); |
2ec38a03 | 124 | |
88cee8fd DK |
125 | s3c_rtc_alarm_clk_enable(enabled); |
126 | ||
2ec38a03 | 127 | return 0; |
1add6781 BD |
128 | } |
129 | ||
773be7ee | 130 | static int s3c_rtc_setfreq(struct device *dev, int freq) |
1add6781 | 131 | { |
9f4123b7 MC |
132 | struct platform_device *pdev = to_platform_device(dev); |
133 | struct rtc_device *rtc_dev = platform_get_drvdata(pdev); | |
134 | unsigned int tmp = 0; | |
1add6781 | 135 | |
5d2a5037 JC |
136 | if (!is_power_of_2(freq)) |
137 | return -EINVAL; | |
138 | ||
cefe4fbb | 139 | clk_enable(rtc_clk); |
1add6781 | 140 | spin_lock_irq(&s3c_rtc_pie_lock); |
1add6781 | 141 | |
9f4123b7 MC |
142 | if (s3c_rtc_cpu_type == TYPE_S3C2410) { |
143 | tmp = readb(s3c_rtc_base + S3C2410_TICNT); | |
144 | tmp &= S3C2410_TICNT_ENABLE; | |
145 | } | |
146 | ||
147 | tmp |= (rtc_dev->max_user_freq / freq)-1; | |
1add6781 | 148 | |
2f3478f6 | 149 | writel(tmp, s3c_rtc_base + S3C2410_TICNT); |
1add6781 | 150 | spin_unlock_irq(&s3c_rtc_pie_lock); |
cefe4fbb | 151 | clk_disable(rtc_clk); |
773be7ee BD |
152 | |
153 | return 0; | |
1add6781 BD |
154 | } |
155 | ||
156 | /* Time read/write */ | |
157 | ||
158 | static int s3c_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm) | |
159 | { | |
160 | unsigned int have_retried = 0; | |
9a654518 | 161 | void __iomem *base = s3c_rtc_base; |
1add6781 | 162 | |
cefe4fbb | 163 | clk_enable(rtc_clk); |
1add6781 | 164 | retry_get_time: |
9a654518 BD |
165 | rtc_tm->tm_min = readb(base + S3C2410_RTCMIN); |
166 | rtc_tm->tm_hour = readb(base + S3C2410_RTCHOUR); | |
167 | rtc_tm->tm_mday = readb(base + S3C2410_RTCDATE); | |
168 | rtc_tm->tm_mon = readb(base + S3C2410_RTCMON); | |
169 | rtc_tm->tm_year = readb(base + S3C2410_RTCYEAR); | |
170 | rtc_tm->tm_sec = readb(base + S3C2410_RTCSEC); | |
1add6781 BD |
171 | |
172 | /* the only way to work out wether the system was mid-update | |
173 | * when we read it is to check the second counter, and if it | |
174 | * is zero, then we re-try the entire read | |
175 | */ | |
176 | ||
177 | if (rtc_tm->tm_sec == 0 && !have_retried) { | |
178 | have_retried = 1; | |
179 | goto retry_get_time; | |
180 | } | |
181 | ||
fe20ba70 AB |
182 | rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec); |
183 | rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min); | |
184 | rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour); | |
185 | rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday); | |
186 | rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon); | |
187 | rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year); | |
1add6781 BD |
188 | |
189 | rtc_tm->tm_year += 100; | |
4e8896cd MH |
190 | |
191 | pr_debug("read time %04d.%02d.%02d %02d:%02d:%02d\n", | |
192 | 1900 + rtc_tm->tm_year, rtc_tm->tm_mon, rtc_tm->tm_mday, | |
193 | rtc_tm->tm_hour, rtc_tm->tm_min, rtc_tm->tm_sec); | |
194 | ||
1add6781 BD |
195 | rtc_tm->tm_mon -= 1; |
196 | ||
cefe4fbb | 197 | clk_disable(rtc_clk); |
5b3ffddd | 198 | return rtc_valid_tm(rtc_tm); |
1add6781 BD |
199 | } |
200 | ||
201 | static int s3c_rtc_settime(struct device *dev, struct rtc_time *tm) | |
202 | { | |
9a654518 | 203 | void __iomem *base = s3c_rtc_base; |
641741e0 | 204 | int year = tm->tm_year - 100; |
9a654518 | 205 | |
30ffc40c KK |
206 | pr_debug("set time %04d.%02d.%02d %02d:%02d:%02d\n", |
207 | 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday, | |
641741e0 BD |
208 | tm->tm_hour, tm->tm_min, tm->tm_sec); |
209 | ||
210 | /* we get around y2k by simply not supporting it */ | |
1add6781 | 211 | |
641741e0 | 212 | if (year < 0 || year >= 100) { |
9a654518 | 213 | dev_err(dev, "rtc only supports 100 years\n"); |
1add6781 | 214 | return -EINVAL; |
9a654518 BD |
215 | } |
216 | ||
2dbcd05f | 217 | clk_enable(rtc_clk); |
fe20ba70 AB |
218 | writeb(bin2bcd(tm->tm_sec), base + S3C2410_RTCSEC); |
219 | writeb(bin2bcd(tm->tm_min), base + S3C2410_RTCMIN); | |
220 | writeb(bin2bcd(tm->tm_hour), base + S3C2410_RTCHOUR); | |
221 | writeb(bin2bcd(tm->tm_mday), base + S3C2410_RTCDATE); | |
222 | writeb(bin2bcd(tm->tm_mon + 1), base + S3C2410_RTCMON); | |
223 | writeb(bin2bcd(year), base + S3C2410_RTCYEAR); | |
cefe4fbb | 224 | clk_disable(rtc_clk); |
1add6781 BD |
225 | |
226 | return 0; | |
227 | } | |
228 | ||
229 | static int s3c_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm) | |
230 | { | |
231 | struct rtc_time *alm_tm = &alrm->time; | |
9a654518 | 232 | void __iomem *base = s3c_rtc_base; |
1add6781 BD |
233 | unsigned int alm_en; |
234 | ||
cefe4fbb | 235 | clk_enable(rtc_clk); |
9a654518 BD |
236 | alm_tm->tm_sec = readb(base + S3C2410_ALMSEC); |
237 | alm_tm->tm_min = readb(base + S3C2410_ALMMIN); | |
238 | alm_tm->tm_hour = readb(base + S3C2410_ALMHOUR); | |
239 | alm_tm->tm_mon = readb(base + S3C2410_ALMMON); | |
240 | alm_tm->tm_mday = readb(base + S3C2410_ALMDATE); | |
241 | alm_tm->tm_year = readb(base + S3C2410_ALMYEAR); | |
1add6781 | 242 | |
9a654518 | 243 | alm_en = readb(base + S3C2410_RTCALM); |
1add6781 | 244 | |
a2db8dfc DB |
245 | alrm->enabled = (alm_en & S3C2410_RTCALM_ALMEN) ? 1 : 0; |
246 | ||
30ffc40c | 247 | pr_debug("read alarm %d, %04d.%02d.%02d %02d:%02d:%02d\n", |
1add6781 | 248 | alm_en, |
30ffc40c | 249 | 1900 + alm_tm->tm_year, alm_tm->tm_mon, alm_tm->tm_mday, |
1add6781 BD |
250 | alm_tm->tm_hour, alm_tm->tm_min, alm_tm->tm_sec); |
251 | ||
252 | ||
253 | /* decode the alarm enable field */ | |
254 | ||
255 | if (alm_en & S3C2410_RTCALM_SECEN) | |
fe20ba70 | 256 | alm_tm->tm_sec = bcd2bin(alm_tm->tm_sec); |
1add6781 | 257 | else |
dd061d1a | 258 | alm_tm->tm_sec = -1; |
1add6781 BD |
259 | |
260 | if (alm_en & S3C2410_RTCALM_MINEN) | |
fe20ba70 | 261 | alm_tm->tm_min = bcd2bin(alm_tm->tm_min); |
1add6781 | 262 | else |
dd061d1a | 263 | alm_tm->tm_min = -1; |
1add6781 BD |
264 | |
265 | if (alm_en & S3C2410_RTCALM_HOUREN) | |
fe20ba70 | 266 | alm_tm->tm_hour = bcd2bin(alm_tm->tm_hour); |
1add6781 | 267 | else |
dd061d1a | 268 | alm_tm->tm_hour = -1; |
1add6781 BD |
269 | |
270 | if (alm_en & S3C2410_RTCALM_DAYEN) | |
fe20ba70 | 271 | alm_tm->tm_mday = bcd2bin(alm_tm->tm_mday); |
1add6781 | 272 | else |
dd061d1a | 273 | alm_tm->tm_mday = -1; |
1add6781 BD |
274 | |
275 | if (alm_en & S3C2410_RTCALM_MONEN) { | |
fe20ba70 | 276 | alm_tm->tm_mon = bcd2bin(alm_tm->tm_mon); |
1add6781 BD |
277 | alm_tm->tm_mon -= 1; |
278 | } else { | |
dd061d1a | 279 | alm_tm->tm_mon = -1; |
1add6781 BD |
280 | } |
281 | ||
282 | if (alm_en & S3C2410_RTCALM_YEAREN) | |
fe20ba70 | 283 | alm_tm->tm_year = bcd2bin(alm_tm->tm_year); |
1add6781 | 284 | else |
dd061d1a | 285 | alm_tm->tm_year = -1; |
1add6781 | 286 | |
cefe4fbb | 287 | clk_disable(rtc_clk); |
1add6781 BD |
288 | return 0; |
289 | } | |
290 | ||
291 | static int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) | |
292 | { | |
293 | struct rtc_time *tm = &alrm->time; | |
9a654518 | 294 | void __iomem *base = s3c_rtc_base; |
1add6781 BD |
295 | unsigned int alrm_en; |
296 | ||
cefe4fbb | 297 | clk_enable(rtc_clk); |
30ffc40c | 298 | pr_debug("s3c_rtc_setalarm: %d, %04d.%02d.%02d %02d:%02d:%02d\n", |
1add6781 | 299 | alrm->enabled, |
4e8896cd | 300 | 1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday, |
30ffc40c | 301 | tm->tm_hour, tm->tm_min, tm->tm_sec); |
1add6781 | 302 | |
9a654518 BD |
303 | alrm_en = readb(base + S3C2410_RTCALM) & S3C2410_RTCALM_ALMEN; |
304 | writeb(0x00, base + S3C2410_RTCALM); | |
1add6781 BD |
305 | |
306 | if (tm->tm_sec < 60 && tm->tm_sec >= 0) { | |
307 | alrm_en |= S3C2410_RTCALM_SECEN; | |
fe20ba70 | 308 | writeb(bin2bcd(tm->tm_sec), base + S3C2410_ALMSEC); |
1add6781 BD |
309 | } |
310 | ||
311 | if (tm->tm_min < 60 && tm->tm_min >= 0) { | |
312 | alrm_en |= S3C2410_RTCALM_MINEN; | |
fe20ba70 | 313 | writeb(bin2bcd(tm->tm_min), base + S3C2410_ALMMIN); |
1add6781 BD |
314 | } |
315 | ||
316 | if (tm->tm_hour < 24 && tm->tm_hour >= 0) { | |
317 | alrm_en |= S3C2410_RTCALM_HOUREN; | |
fe20ba70 | 318 | writeb(bin2bcd(tm->tm_hour), base + S3C2410_ALMHOUR); |
1add6781 BD |
319 | } |
320 | ||
321 | pr_debug("setting S3C2410_RTCALM to %08x\n", alrm_en); | |
322 | ||
9a654518 | 323 | writeb(alrm_en, base + S3C2410_RTCALM); |
1add6781 | 324 | |
2ec38a03 | 325 | s3c_rtc_setaie(dev, alrm->enabled); |
1add6781 | 326 | |
cefe4fbb | 327 | clk_disable(rtc_clk); |
1add6781 BD |
328 | return 0; |
329 | } | |
330 | ||
1add6781 BD |
331 | static int s3c_rtc_proc(struct device *dev, struct seq_file *seq) |
332 | { | |
9f4123b7 | 333 | unsigned int ticnt; |
1add6781 | 334 | |
cefe4fbb | 335 | clk_enable(rtc_clk); |
9f4123b7 | 336 | if (s3c_rtc_cpu_type == TYPE_S3C64XX) { |
f61ae671 | 337 | ticnt = readw(s3c_rtc_base + S3C2410_RTCCON); |
9f4123b7 MC |
338 | ticnt &= S3C64XX_RTCCON_TICEN; |
339 | } else { | |
340 | ticnt = readb(s3c_rtc_base + S3C2410_TICNT); | |
341 | ticnt &= S3C2410_TICNT_ENABLE; | |
342 | } | |
343 | ||
344 | seq_printf(seq, "periodic_IRQ\t: %s\n", ticnt ? "yes" : "no"); | |
cefe4fbb | 345 | clk_disable(rtc_clk); |
1add6781 BD |
346 | return 0; |
347 | } | |
348 | ||
ff8371ac | 349 | static const struct rtc_class_ops s3c_rtcops = { |
1add6781 BD |
350 | .read_time = s3c_rtc_gettime, |
351 | .set_time = s3c_rtc_settime, | |
352 | .read_alarm = s3c_rtc_getalarm, | |
353 | .set_alarm = s3c_rtc_setalarm, | |
e6eb524e CY |
354 | .proc = s3c_rtc_proc, |
355 | .alarm_irq_enable = s3c_rtc_setaie, | |
1add6781 BD |
356 | }; |
357 | ||
358 | static void s3c_rtc_enable(struct platform_device *pdev, int en) | |
359 | { | |
9a654518 | 360 | void __iomem *base = s3c_rtc_base; |
1add6781 BD |
361 | unsigned int tmp; |
362 | ||
363 | if (s3c_rtc_base == NULL) | |
364 | return; | |
365 | ||
cefe4fbb | 366 | clk_enable(rtc_clk); |
1add6781 | 367 | if (!en) { |
f61ae671 | 368 | tmp = readw(base + S3C2410_RTCCON); |
9f4123b7 MC |
369 | if (s3c_rtc_cpu_type == TYPE_S3C64XX) |
370 | tmp &= ~S3C64XX_RTCCON_TICEN; | |
371 | tmp &= ~S3C2410_RTCCON_RTCEN; | |
f61ae671 | 372 | writew(tmp, base + S3C2410_RTCCON); |
9f4123b7 MC |
373 | |
374 | if (s3c_rtc_cpu_type == TYPE_S3C2410) { | |
375 | tmp = readb(base + S3C2410_TICNT); | |
376 | tmp &= ~S3C2410_TICNT_ENABLE; | |
377 | writeb(tmp, base + S3C2410_TICNT); | |
378 | } | |
1add6781 BD |
379 | } else { |
380 | /* re-enable the device, and check it is ok */ | |
381 | ||
f61ae671 | 382 | if ((readw(base+S3C2410_RTCCON) & S3C2410_RTCCON_RTCEN) == 0) { |
1add6781 BD |
383 | dev_info(&pdev->dev, "rtc disabled, re-enabling\n"); |
384 | ||
f61ae671 CY |
385 | tmp = readw(base + S3C2410_RTCCON); |
386 | writew(tmp | S3C2410_RTCCON_RTCEN, | |
387 | base + S3C2410_RTCCON); | |
1add6781 BD |
388 | } |
389 | ||
f61ae671 | 390 | if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CNTSEL)) { |
1add6781 BD |
391 | dev_info(&pdev->dev, "removing RTCCON_CNTSEL\n"); |
392 | ||
f61ae671 CY |
393 | tmp = readw(base + S3C2410_RTCCON); |
394 | writew(tmp & ~S3C2410_RTCCON_CNTSEL, | |
395 | base + S3C2410_RTCCON); | |
1add6781 BD |
396 | } |
397 | ||
f61ae671 | 398 | if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CLKRST)) { |
1add6781 BD |
399 | dev_info(&pdev->dev, "removing RTCCON_CLKRST\n"); |
400 | ||
f61ae671 CY |
401 | tmp = readw(base + S3C2410_RTCCON); |
402 | writew(tmp & ~S3C2410_RTCCON_CLKRST, | |
403 | base + S3C2410_RTCCON); | |
1add6781 BD |
404 | } |
405 | } | |
cefe4fbb | 406 | clk_disable(rtc_clk); |
1add6781 BD |
407 | } |
408 | ||
4cd0c5c4 | 409 | static int __devexit s3c_rtc_remove(struct platform_device *dev) |
1add6781 BD |
410 | { |
411 | struct rtc_device *rtc = platform_get_drvdata(dev); | |
412 | ||
62d17601 MH |
413 | free_irq(s3c_rtc_alarmno, rtc); |
414 | free_irq(s3c_rtc_tickno, rtc); | |
415 | ||
1add6781 BD |
416 | platform_set_drvdata(dev, NULL); |
417 | rtc_device_unregister(rtc); | |
418 | ||
2ec38a03 | 419 | s3c_rtc_setaie(&dev->dev, 0); |
1add6781 | 420 | |
e48add8c AD |
421 | clk_put(rtc_clk); |
422 | rtc_clk = NULL; | |
423 | ||
1add6781 BD |
424 | iounmap(s3c_rtc_base); |
425 | release_resource(s3c_rtc_mem); | |
426 | kfree(s3c_rtc_mem); | |
427 | ||
428 | return 0; | |
429 | } | |
430 | ||
d2524caa HS |
431 | static const struct of_device_id s3c_rtc_dt_match[]; |
432 | ||
433 | static inline int s3c_rtc_get_driver_data(struct platform_device *pdev) | |
434 | { | |
435 | #ifdef CONFIG_OF | |
436 | if (pdev->dev.of_node) { | |
437 | const struct of_device_id *match; | |
438 | match = of_match_node(s3c_rtc_dt_match, pdev->dev.of_node); | |
439 | return match->data; | |
440 | } | |
441 | #endif | |
442 | return platform_get_device_id(pdev)->driver_data; | |
443 | } | |
444 | ||
4cd0c5c4 | 445 | static int __devinit s3c_rtc_probe(struct platform_device *pdev) |
1add6781 BD |
446 | { |
447 | struct rtc_device *rtc; | |
e1df962e | 448 | struct rtc_time rtc_tm; |
1add6781 BD |
449 | struct resource *res; |
450 | int ret; | |
451 | ||
2a4e2b87 | 452 | pr_debug("%s: probe=%p\n", __func__, pdev); |
1add6781 BD |
453 | |
454 | /* find the IRQs */ | |
455 | ||
456 | s3c_rtc_tickno = platform_get_irq(pdev, 1); | |
457 | if (s3c_rtc_tickno < 0) { | |
458 | dev_err(&pdev->dev, "no irq for rtc tick\n"); | |
459 | return -ENOENT; | |
460 | } | |
461 | ||
462 | s3c_rtc_alarmno = platform_get_irq(pdev, 0); | |
463 | if (s3c_rtc_alarmno < 0) { | |
464 | dev_err(&pdev->dev, "no irq for alarm\n"); | |
465 | return -ENOENT; | |
466 | } | |
467 | ||
468 | pr_debug("s3c2410_rtc: tick irq %d, alarm irq %d\n", | |
469 | s3c_rtc_tickno, s3c_rtc_alarmno); | |
470 | ||
471 | /* get the memory region */ | |
472 | ||
473 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
474 | if (res == NULL) { | |
475 | dev_err(&pdev->dev, "failed to get memory region resource\n"); | |
476 | return -ENOENT; | |
477 | } | |
478 | ||
28f65c11 | 479 | s3c_rtc_mem = request_mem_region(res->start, resource_size(res), |
9a654518 | 480 | pdev->name); |
1add6781 BD |
481 | |
482 | if (s3c_rtc_mem == NULL) { | |
483 | dev_err(&pdev->dev, "failed to reserve memory region\n"); | |
484 | ret = -ENOENT; | |
485 | goto err_nores; | |
486 | } | |
487 | ||
28f65c11 | 488 | s3c_rtc_base = ioremap(res->start, resource_size(res)); |
1add6781 BD |
489 | if (s3c_rtc_base == NULL) { |
490 | dev_err(&pdev->dev, "failed ioremap()\n"); | |
491 | ret = -EINVAL; | |
492 | goto err_nomap; | |
493 | } | |
494 | ||
e48add8c AD |
495 | rtc_clk = clk_get(&pdev->dev, "rtc"); |
496 | if (IS_ERR(rtc_clk)) { | |
497 | dev_err(&pdev->dev, "failed to find rtc clock source\n"); | |
498 | ret = PTR_ERR(rtc_clk); | |
499 | rtc_clk = NULL; | |
500 | goto err_clk; | |
501 | } | |
502 | ||
503 | clk_enable(rtc_clk); | |
504 | ||
1add6781 BD |
505 | /* check to see if everything is setup correctly */ |
506 | ||
507 | s3c_rtc_enable(pdev, 1); | |
508 | ||
f61ae671 CY |
509 | pr_debug("s3c2410_rtc: RTCCON=%02x\n", |
510 | readw(s3c_rtc_base + S3C2410_RTCCON)); | |
1add6781 | 511 | |
51b7616e YK |
512 | device_init_wakeup(&pdev->dev, 1); |
513 | ||
1add6781 BD |
514 | /* register RTC and exit */ |
515 | ||
516 | rtc = rtc_device_register("s3c", &pdev->dev, &s3c_rtcops, | |
517 | THIS_MODULE); | |
518 | ||
519 | if (IS_ERR(rtc)) { | |
520 | dev_err(&pdev->dev, "cannot attach rtc\n"); | |
521 | ret = PTR_ERR(rtc); | |
522 | goto err_nortc; | |
523 | } | |
524 | ||
d2524caa | 525 | s3c_rtc_cpu_type = s3c_rtc_get_driver_data(pdev); |
eaa6e4dd | 526 | |
051fe54e TK |
527 | /* Check RTC Time */ |
528 | ||
e1df962e | 529 | s3c_rtc_gettime(NULL, &rtc_tm); |
051fe54e | 530 | |
e1df962e CY |
531 | if (rtc_valid_tm(&rtc_tm)) { |
532 | rtc_tm.tm_year = 100; | |
533 | rtc_tm.tm_mon = 0; | |
534 | rtc_tm.tm_mday = 1; | |
535 | rtc_tm.tm_hour = 0; | |
536 | rtc_tm.tm_min = 0; | |
537 | rtc_tm.tm_sec = 0; | |
538 | ||
539 | s3c_rtc_settime(NULL, &rtc_tm); | |
540 | ||
541 | dev_warn(&pdev->dev, "warning: invalid RTC value so initializing it\n"); | |
051fe54e TK |
542 | } |
543 | ||
9f4123b7 MC |
544 | if (s3c_rtc_cpu_type == TYPE_S3C64XX) |
545 | rtc->max_user_freq = 32768; | |
546 | else | |
547 | rtc->max_user_freq = 128; | |
548 | ||
1add6781 | 549 | platform_set_drvdata(pdev, rtc); |
e893de59 MC |
550 | |
551 | s3c_rtc_setfreq(&pdev->dev, 1); | |
552 | ||
62d17601 MH |
553 | ret = request_irq(s3c_rtc_alarmno, s3c_rtc_alarmirq, |
554 | IRQF_DISABLED, "s3c2410-rtc alarm", rtc); | |
555 | if (ret) { | |
556 | dev_err(&pdev->dev, "IRQ%d error %d\n", s3c_rtc_alarmno, ret); | |
557 | goto err_alarm_irq; | |
558 | } | |
559 | ||
560 | ret = request_irq(s3c_rtc_tickno, s3c_rtc_tickirq, | |
561 | IRQF_DISABLED, "s3c2410-rtc tick", rtc); | |
562 | if (ret) { | |
563 | dev_err(&pdev->dev, "IRQ%d error %d\n", s3c_rtc_tickno, ret); | |
564 | free_irq(s3c_rtc_alarmno, rtc); | |
565 | goto err_tick_irq; | |
566 | } | |
567 | ||
cefe4fbb DK |
568 | clk_disable(rtc_clk); |
569 | ||
1add6781 BD |
570 | return 0; |
571 | ||
62d17601 MH |
572 | err_tick_irq: |
573 | free_irq(s3c_rtc_alarmno, rtc); | |
574 | ||
575 | err_alarm_irq: | |
576 | platform_set_drvdata(pdev, NULL); | |
577 | rtc_device_unregister(rtc); | |
578 | ||
1add6781 BD |
579 | err_nortc: |
580 | s3c_rtc_enable(pdev, 0); | |
e48add8c AD |
581 | clk_disable(rtc_clk); |
582 | clk_put(rtc_clk); | |
583 | ||
584 | err_clk: | |
1add6781 BD |
585 | iounmap(s3c_rtc_base); |
586 | ||
587 | err_nomap: | |
588 | release_resource(s3c_rtc_mem); | |
589 | ||
590 | err_nores: | |
591 | return ret; | |
592 | } | |
593 | ||
594 | #ifdef CONFIG_PM | |
595 | ||
596 | /* RTC Power management control */ | |
597 | ||
9f4123b7 | 598 | static int ticnt_save, ticnt_en_save; |
1add6781 BD |
599 | |
600 | static int s3c_rtc_suspend(struct platform_device *pdev, pm_message_t state) | |
601 | { | |
cefe4fbb | 602 | clk_enable(rtc_clk); |
1add6781 | 603 | /* save TICNT for anyone using periodic interrupts */ |
9a654518 | 604 | ticnt_save = readb(s3c_rtc_base + S3C2410_TICNT); |
9f4123b7 | 605 | if (s3c_rtc_cpu_type == TYPE_S3C64XX) { |
f61ae671 | 606 | ticnt_en_save = readw(s3c_rtc_base + S3C2410_RTCCON); |
9f4123b7 MC |
607 | ticnt_en_save &= S3C64XX_RTCCON_TICEN; |
608 | } | |
1add6781 | 609 | s3c_rtc_enable(pdev, 0); |
f501ed52 | 610 | |
52cd4e5c BD |
611 | if (device_may_wakeup(&pdev->dev) && !wake_en) { |
612 | if (enable_irq_wake(s3c_rtc_alarmno) == 0) | |
613 | wake_en = true; | |
614 | else | |
615 | dev_err(&pdev->dev, "enable_irq_wake failed\n"); | |
616 | } | |
cefe4fbb | 617 | clk_disable(rtc_clk); |
f501ed52 | 618 | |
1add6781 BD |
619 | return 0; |
620 | } | |
621 | ||
622 | static int s3c_rtc_resume(struct platform_device *pdev) | |
623 | { | |
9f4123b7 MC |
624 | unsigned int tmp; |
625 | ||
cefe4fbb | 626 | clk_enable(rtc_clk); |
1add6781 | 627 | s3c_rtc_enable(pdev, 1); |
9a654518 | 628 | writeb(ticnt_save, s3c_rtc_base + S3C2410_TICNT); |
9f4123b7 | 629 | if (s3c_rtc_cpu_type == TYPE_S3C64XX && ticnt_en_save) { |
f61ae671 CY |
630 | tmp = readw(s3c_rtc_base + S3C2410_RTCCON); |
631 | writew(tmp | ticnt_en_save, s3c_rtc_base + S3C2410_RTCCON); | |
9f4123b7 | 632 | } |
f501ed52 | 633 | |
52cd4e5c | 634 | if (device_may_wakeup(&pdev->dev) && wake_en) { |
f501ed52 | 635 | disable_irq_wake(s3c_rtc_alarmno); |
52cd4e5c BD |
636 | wake_en = false; |
637 | } | |
cefe4fbb | 638 | clk_disable(rtc_clk); |
f501ed52 | 639 | |
1add6781 BD |
640 | return 0; |
641 | } | |
642 | #else | |
643 | #define s3c_rtc_suspend NULL | |
644 | #define s3c_rtc_resume NULL | |
645 | #endif | |
646 | ||
39ce4084 TA |
647 | #ifdef CONFIG_OF |
648 | static const struct of_device_id s3c_rtc_dt_match[] = { | |
d2524caa HS |
649 | { |
650 | .compatible = "samsung,s3c2410-rtc" | |
651 | .data = TYPE_S3C2410, | |
652 | }, { | |
653 | .compatible = "samsung,s3c6410-rtc" | |
654 | .data = TYPE_S3C64XX, | |
655 | }, | |
39ce4084 TA |
656 | {}, |
657 | }; | |
658 | MODULE_DEVICE_TABLE(of, s3c_rtc_dt_match); | |
659 | #else | |
660 | #define s3c_rtc_dt_match NULL | |
661 | #endif | |
662 | ||
9f4123b7 MC |
663 | static struct platform_device_id s3c_rtc_driver_ids[] = { |
664 | { | |
665 | .name = "s3c2410-rtc", | |
666 | .driver_data = TYPE_S3C2410, | |
667 | }, { | |
668 | .name = "s3c64xx-rtc", | |
669 | .driver_data = TYPE_S3C64XX, | |
670 | }, | |
671 | { } | |
672 | }; | |
673 | ||
674 | MODULE_DEVICE_TABLE(platform, s3c_rtc_driver_ids); | |
675 | ||
676 | static struct platform_driver s3c_rtc_driver = { | |
1add6781 | 677 | .probe = s3c_rtc_probe, |
4cd0c5c4 | 678 | .remove = __devexit_p(s3c_rtc_remove), |
1add6781 BD |
679 | .suspend = s3c_rtc_suspend, |
680 | .resume = s3c_rtc_resume, | |
9f4123b7 | 681 | .id_table = s3c_rtc_driver_ids, |
1add6781 | 682 | .driver = { |
9f4123b7 | 683 | .name = "s3c-rtc", |
1add6781 | 684 | .owner = THIS_MODULE, |
39ce4084 | 685 | .of_match_table = s3c_rtc_dt_match, |
1add6781 BD |
686 | }, |
687 | }; | |
688 | ||
0c4eae66 | 689 | module_platform_driver(s3c_rtc_driver); |
1add6781 BD |
690 | |
691 | MODULE_DESCRIPTION("Samsung S3C RTC Driver"); | |
692 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | |
693 | MODULE_LICENSE("GPL"); | |
ad28a07b | 694 | MODULE_ALIAS("platform:s3c2410-rtc"); |