Commit | Line | Data |
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5bccae6e | 1 | /* |
f8b23bbd | 2 | * Copyright (c) 2013-2014 Samsung Electronics Co., Ltd |
5bccae6e SK |
3 | * http://www.samsung.com |
4 | * | |
5 | * Copyright (C) 2013 Google, Inc | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | */ | |
17 | ||
a737e835 JP |
18 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
19 | ||
5bccae6e SK |
20 | #include <linux/module.h> |
21 | #include <linux/i2c.h> | |
5bccae6e | 22 | #include <linux/bcd.h> |
5bccae6e SK |
23 | #include <linux/regmap.h> |
24 | #include <linux/rtc.h> | |
5bccae6e SK |
25 | #include <linux/platform_device.h> |
26 | #include <linux/mfd/samsung/core.h> | |
27 | #include <linux/mfd/samsung/irq.h> | |
28 | #include <linux/mfd/samsung/rtc.h> | |
0c5deb1e | 29 | #include <linux/mfd/samsung/s2mps14.h> |
5bccae6e | 30 | |
d73238d4 KK |
31 | /* |
32 | * Maximum number of retries for checking changes in UDR field | |
602cb5bb | 33 | * of S5M_RTC_UDR_CON register (to limit possible endless loop). |
d73238d4 KK |
34 | * |
35 | * After writing to RTC registers (setting time or alarm) read the UDR field | |
602cb5bb | 36 | * in S5M_RTC_UDR_CON register. UDR is auto-cleared when data have |
d73238d4 KK |
37 | * been transferred. |
38 | */ | |
39 | #define UDR_READ_RETRY_CNT 5 | |
40 | ||
8ae83b6f KK |
41 | /* |
42 | * Registers used by the driver which are different between chipsets. | |
43 | * | |
44 | * Operations like read time and write alarm/time require updating | |
45 | * specific fields in UDR register. These fields usually are auto-cleared | |
46 | * (with some exceptions). | |
47 | * | |
48 | * Table of operations per device: | |
49 | * | |
50 | * Device | Write time | Read time | Write alarm | |
51 | * ================================================= | |
52 | * S5M8767 | UDR + TIME | | UDR | |
53 | * S2MPS11/14 | WUDR | RUDR | WUDR + RUDR | |
54 | * S2MPS13 | WUDR | RUDR | WUDR + AUDR | |
55 | * S2MPS15 | WUDR | RUDR | AUDR | |
56 | */ | |
f8b23bbd KK |
57 | struct s5m_rtc_reg_config { |
58 | /* Number of registers used for setting time/alarm0/alarm1 */ | |
59 | unsigned int regs_count; | |
60 | /* First register for time, seconds */ | |
61 | unsigned int time; | |
62 | /* RTC control register */ | |
63 | unsigned int ctrl; | |
64 | /* First register for alarm 0, seconds */ | |
65 | unsigned int alarm0; | |
66 | /* First register for alarm 1, seconds */ | |
67 | unsigned int alarm1; | |
f8b23bbd KK |
68 | /* |
69 | * Register for update flag (UDR). Typically setting UDR field to 1 | |
70 | * will enable update of time or alarm register. Then it will be | |
71 | * auto-cleared after successful update. | |
72 | */ | |
a83a793a | 73 | unsigned int udr_update; |
67a6025a KK |
74 | /* Auto-cleared mask in UDR field for writing time and alarm */ |
75 | unsigned int autoclear_udr_mask; | |
8ae83b6f KK |
76 | /* |
77 | * Masks in UDR field for time and alarm operations. | |
78 | * The read time mask can be 0. Rest should not. | |
79 | */ | |
80 | unsigned int read_time_udr_mask; | |
81 | unsigned int write_time_udr_mask; | |
82 | unsigned int write_alarm_udr_mask; | |
f8b23bbd KK |
83 | }; |
84 | ||
85 | /* Register map for S5M8763 and S5M8767 */ | |
86 | static const struct s5m_rtc_reg_config s5m_rtc_regs = { | |
87 | .regs_count = 8, | |
88 | .time = S5M_RTC_SEC, | |
89 | .ctrl = S5M_ALARM1_CONF, | |
90 | .alarm0 = S5M_ALARM0_SEC, | |
91 | .alarm1 = S5M_ALARM1_SEC, | |
a83a793a | 92 | .udr_update = S5M_RTC_UDR_CON, |
67a6025a | 93 | .autoclear_udr_mask = S5M_RTC_UDR_MASK, |
8ae83b6f KK |
94 | .read_time_udr_mask = 0, /* Not needed */ |
95 | .write_time_udr_mask = S5M_RTC_UDR_MASK | S5M_RTC_TIME_EN_MASK, | |
96 | .write_alarm_udr_mask = S5M_RTC_UDR_MASK, | |
97 | }; | |
98 | ||
99 | /* Register map for S2MPS13 */ | |
100 | static const struct s5m_rtc_reg_config s2mps13_rtc_regs = { | |
101 | .regs_count = 7, | |
102 | .time = S2MPS_RTC_SEC, | |
103 | .ctrl = S2MPS_RTC_CTRL, | |
104 | .alarm0 = S2MPS_ALARM0_SEC, | |
105 | .alarm1 = S2MPS_ALARM1_SEC, | |
106 | .udr_update = S2MPS_RTC_UDR_CON, | |
107 | .autoclear_udr_mask = S2MPS_RTC_WUDR_MASK, | |
108 | .read_time_udr_mask = S2MPS_RTC_RUDR_MASK, | |
109 | .write_time_udr_mask = S2MPS_RTC_WUDR_MASK, | |
110 | .write_alarm_udr_mask = S2MPS_RTC_WUDR_MASK | S2MPS13_RTC_AUDR_MASK, | |
111 | }; | |
112 | ||
113 | /* Register map for S2MPS11/14 */ | |
114 | static const struct s5m_rtc_reg_config s2mps14_rtc_regs = { | |
115 | .regs_count = 7, | |
116 | .time = S2MPS_RTC_SEC, | |
117 | .ctrl = S2MPS_RTC_CTRL, | |
118 | .alarm0 = S2MPS_ALARM0_SEC, | |
119 | .alarm1 = S2MPS_ALARM1_SEC, | |
120 | .udr_update = S2MPS_RTC_UDR_CON, | |
121 | .autoclear_udr_mask = S2MPS_RTC_WUDR_MASK, | |
122 | .read_time_udr_mask = S2MPS_RTC_RUDR_MASK, | |
123 | .write_time_udr_mask = S2MPS_RTC_WUDR_MASK, | |
124 | .write_alarm_udr_mask = S2MPS_RTC_WUDR_MASK | S2MPS_RTC_RUDR_MASK, | |
f8b23bbd KK |
125 | }; |
126 | ||
0c5deb1e | 127 | /* |
8ae83b6f KK |
128 | * Register map for S2MPS15 - in comparison to S2MPS14 the WUDR and AUDR bits |
129 | * are swapped. | |
0c5deb1e | 130 | */ |
8ae83b6f | 131 | static const struct s5m_rtc_reg_config s2mps15_rtc_regs = { |
0c5deb1e KK |
132 | .regs_count = 7, |
133 | .time = S2MPS_RTC_SEC, | |
134 | .ctrl = S2MPS_RTC_CTRL, | |
135 | .alarm0 = S2MPS_ALARM0_SEC, | |
136 | .alarm1 = S2MPS_ALARM1_SEC, | |
a83a793a | 137 | .udr_update = S2MPS_RTC_UDR_CON, |
67a6025a | 138 | .autoclear_udr_mask = S2MPS_RTC_WUDR_MASK, |
8ae83b6f KK |
139 | .read_time_udr_mask = S2MPS_RTC_RUDR_MASK, |
140 | .write_time_udr_mask = S2MPS15_RTC_WUDR_MASK, | |
141 | .write_alarm_udr_mask = S2MPS15_RTC_AUDR_MASK, | |
0c5deb1e KK |
142 | }; |
143 | ||
5bccae6e SK |
144 | struct s5m_rtc_info { |
145 | struct device *dev; | |
e349c910 | 146 | struct i2c_client *i2c; |
5bccae6e | 147 | struct sec_pmic_dev *s5m87xx; |
5ccb7d71 | 148 | struct regmap *regmap; |
5bccae6e SK |
149 | struct rtc_device *rtc_dev; |
150 | int irq; | |
94f91922 | 151 | enum sec_device_type device_type; |
5bccae6e | 152 | int rtc_24hr_mode; |
f8b23bbd | 153 | const struct s5m_rtc_reg_config *regs; |
5bccae6e SK |
154 | }; |
155 | ||
e349c910 KK |
156 | static const struct regmap_config s5m_rtc_regmap_config = { |
157 | .reg_bits = 8, | |
158 | .val_bits = 8, | |
159 | ||
602cb5bb | 160 | .max_register = S5M_RTC_REG_MAX, |
e349c910 KK |
161 | }; |
162 | ||
163 | static const struct regmap_config s2mps14_rtc_regmap_config = { | |
164 | .reg_bits = 8, | |
165 | .val_bits = 8, | |
166 | ||
167 | .max_register = S2MPS_RTC_REG_MAX, | |
168 | }; | |
169 | ||
5bccae6e SK |
170 | static void s5m8767_data_to_tm(u8 *data, struct rtc_time *tm, |
171 | int rtc_24hr_mode) | |
172 | { | |
173 | tm->tm_sec = data[RTC_SEC] & 0x7f; | |
174 | tm->tm_min = data[RTC_MIN] & 0x7f; | |
175 | if (rtc_24hr_mode) { | |
176 | tm->tm_hour = data[RTC_HOUR] & 0x1f; | |
177 | } else { | |
178 | tm->tm_hour = data[RTC_HOUR] & 0x0f; | |
179 | if (data[RTC_HOUR] & HOUR_PM_MASK) | |
180 | tm->tm_hour += 12; | |
181 | } | |
182 | ||
183 | tm->tm_wday = ffs(data[RTC_WEEKDAY] & 0x7f); | |
184 | tm->tm_mday = data[RTC_DATE] & 0x1f; | |
185 | tm->tm_mon = (data[RTC_MONTH] & 0x0f) - 1; | |
186 | tm->tm_year = (data[RTC_YEAR1] & 0x7f) + 100; | |
187 | tm->tm_yday = 0; | |
188 | tm->tm_isdst = 0; | |
189 | } | |
190 | ||
191 | static int s5m8767_tm_to_data(struct rtc_time *tm, u8 *data) | |
192 | { | |
193 | data[RTC_SEC] = tm->tm_sec; | |
194 | data[RTC_MIN] = tm->tm_min; | |
195 | ||
196 | if (tm->tm_hour >= 12) | |
197 | data[RTC_HOUR] = tm->tm_hour | HOUR_PM_MASK; | |
198 | else | |
199 | data[RTC_HOUR] = tm->tm_hour & ~HOUR_PM_MASK; | |
200 | ||
201 | data[RTC_WEEKDAY] = 1 << tm->tm_wday; | |
202 | data[RTC_DATE] = tm->tm_mday; | |
203 | data[RTC_MONTH] = tm->tm_mon + 1; | |
204 | data[RTC_YEAR1] = tm->tm_year > 100 ? (tm->tm_year - 100) : 0; | |
205 | ||
206 | if (tm->tm_year < 100) { | |
a737e835 | 207 | pr_err("RTC cannot handle the year %d\n", |
5bccae6e SK |
208 | 1900 + tm->tm_year); |
209 | return -EINVAL; | |
210 | } else { | |
211 | return 0; | |
212 | } | |
213 | } | |
214 | ||
d73238d4 KK |
215 | /* |
216 | * Read RTC_UDR_CON register and wait till UDR field is cleared. | |
217 | * This indicates that time/alarm update ended. | |
218 | */ | |
8124c711 | 219 | static int s5m8767_wait_for_udr_update(struct s5m_rtc_info *info) |
d73238d4 KK |
220 | { |
221 | int ret, retry = UDR_READ_RETRY_CNT; | |
222 | unsigned int data; | |
223 | ||
224 | do { | |
a83a793a | 225 | ret = regmap_read(info->regmap, info->regs->udr_update, &data); |
67a6025a | 226 | } while (--retry && (data & info->regs->autoclear_udr_mask) && !ret); |
d73238d4 KK |
227 | |
228 | if (!retry) | |
229 | dev_err(info->dev, "waiting for UDR update, reached max number of retries\n"); | |
230 | ||
231 | return ret; | |
232 | } | |
233 | ||
8124c711 | 234 | static int s5m_check_peding_alarm_interrupt(struct s5m_rtc_info *info, |
f8b23bbd KK |
235 | struct rtc_wkalrm *alarm) |
236 | { | |
237 | int ret; | |
238 | unsigned int val; | |
239 | ||
240 | switch (info->device_type) { | |
241 | case S5M8767X: | |
242 | case S5M8763X: | |
243 | ret = regmap_read(info->regmap, S5M_RTC_STATUS, &val); | |
244 | val &= S5M_ALARM0_STATUS; | |
245 | break; | |
a65e5efa | 246 | case S2MPS15X: |
0c5deb1e | 247 | case S2MPS14X: |
5281f94a | 248 | case S2MPS13X: |
0c5deb1e KK |
249 | ret = regmap_read(info->s5m87xx->regmap_pmic, S2MPS14_REG_ST2, |
250 | &val); | |
251 | val &= S2MPS_ALARM0_STATUS; | |
252 | break; | |
f8b23bbd KK |
253 | default: |
254 | return -EINVAL; | |
255 | } | |
256 | if (ret < 0) | |
257 | return ret; | |
258 | ||
259 | if (val) | |
260 | alarm->pending = 1; | |
261 | else | |
262 | alarm->pending = 0; | |
263 | ||
264 | return 0; | |
265 | } | |
266 | ||
8124c711 | 267 | static int s5m8767_rtc_set_time_reg(struct s5m_rtc_info *info) |
5bccae6e SK |
268 | { |
269 | int ret; | |
270 | unsigned int data; | |
271 | ||
a83a793a | 272 | ret = regmap_read(info->regmap, info->regs->udr_update, &data); |
5bccae6e SK |
273 | if (ret < 0) { |
274 | dev_err(info->dev, "failed to read update reg(%d)\n", ret); | |
275 | return ret; | |
276 | } | |
277 | ||
8ae83b6f | 278 | data |= info->regs->write_time_udr_mask; |
a65e5efa | 279 | |
a83a793a | 280 | ret = regmap_write(info->regmap, info->regs->udr_update, data); |
5bccae6e SK |
281 | if (ret < 0) { |
282 | dev_err(info->dev, "failed to write update reg(%d)\n", ret); | |
283 | return ret; | |
284 | } | |
285 | ||
d73238d4 | 286 | ret = s5m8767_wait_for_udr_update(info); |
5bccae6e SK |
287 | |
288 | return ret; | |
289 | } | |
290 | ||
8124c711 | 291 | static int s5m8767_rtc_set_alarm_reg(struct s5m_rtc_info *info) |
5bccae6e SK |
292 | { |
293 | int ret; | |
294 | unsigned int data; | |
295 | ||
a83a793a | 296 | ret = regmap_read(info->regmap, info->regs->udr_update, &data); |
5bccae6e SK |
297 | if (ret < 0) { |
298 | dev_err(info->dev, "%s: fail to read update reg(%d)\n", | |
299 | __func__, ret); | |
300 | return ret; | |
301 | } | |
302 | ||
8ae83b6f | 303 | data |= info->regs->write_alarm_udr_mask; |
0c5deb1e KK |
304 | switch (info->device_type) { |
305 | case S5M8763X: | |
306 | case S5M8767X: | |
307 | data &= ~S5M_RTC_TIME_EN_MASK; | |
308 | break; | |
a65e5efa | 309 | case S2MPS15X: |
0c5deb1e | 310 | case S2MPS14X: |
5281f94a | 311 | case S2MPS13X: |
8ae83b6f | 312 | /* No exceptions needed */ |
5281f94a | 313 | break; |
0c5deb1e KK |
314 | default: |
315 | return -EINVAL; | |
316 | } | |
5bccae6e | 317 | |
a83a793a | 318 | ret = regmap_write(info->regmap, info->regs->udr_update, data); |
5bccae6e SK |
319 | if (ret < 0) { |
320 | dev_err(info->dev, "%s: fail to write update reg(%d)\n", | |
321 | __func__, ret); | |
322 | return ret; | |
323 | } | |
324 | ||
d73238d4 | 325 | ret = s5m8767_wait_for_udr_update(info); |
5bccae6e | 326 | |
5281f94a KK |
327 | /* On S2MPS13 the AUDR is not auto-cleared */ |
328 | if (info->device_type == S2MPS13X) | |
a83a793a | 329 | regmap_update_bits(info->regmap, info->regs->udr_update, |
5281f94a KK |
330 | S2MPS13_RTC_AUDR_MASK, 0); |
331 | ||
5bccae6e SK |
332 | return ret; |
333 | } | |
334 | ||
335 | static void s5m8763_data_to_tm(u8 *data, struct rtc_time *tm) | |
336 | { | |
337 | tm->tm_sec = bcd2bin(data[RTC_SEC]); | |
338 | tm->tm_min = bcd2bin(data[RTC_MIN]); | |
339 | ||
340 | if (data[RTC_HOUR] & HOUR_12) { | |
341 | tm->tm_hour = bcd2bin(data[RTC_HOUR] & 0x1f); | |
342 | if (data[RTC_HOUR] & HOUR_PM) | |
343 | tm->tm_hour += 12; | |
344 | } else { | |
345 | tm->tm_hour = bcd2bin(data[RTC_HOUR] & 0x3f); | |
346 | } | |
347 | ||
348 | tm->tm_wday = data[RTC_WEEKDAY] & 0x07; | |
349 | tm->tm_mday = bcd2bin(data[RTC_DATE]); | |
350 | tm->tm_mon = bcd2bin(data[RTC_MONTH]); | |
351 | tm->tm_year = bcd2bin(data[RTC_YEAR1]) + bcd2bin(data[RTC_YEAR2]) * 100; | |
352 | tm->tm_year -= 1900; | |
353 | } | |
354 | ||
355 | static void s5m8763_tm_to_data(struct rtc_time *tm, u8 *data) | |
356 | { | |
357 | data[RTC_SEC] = bin2bcd(tm->tm_sec); | |
358 | data[RTC_MIN] = bin2bcd(tm->tm_min); | |
359 | data[RTC_HOUR] = bin2bcd(tm->tm_hour); | |
360 | data[RTC_WEEKDAY] = tm->tm_wday; | |
361 | data[RTC_DATE] = bin2bcd(tm->tm_mday); | |
362 | data[RTC_MONTH] = bin2bcd(tm->tm_mon); | |
363 | data[RTC_YEAR1] = bin2bcd(tm->tm_year % 100); | |
364 | data[RTC_YEAR2] = bin2bcd((tm->tm_year + 1900) / 100); | |
365 | } | |
366 | ||
367 | static int s5m_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
368 | { | |
369 | struct s5m_rtc_info *info = dev_get_drvdata(dev); | |
f8b23bbd | 370 | u8 data[info->regs->regs_count]; |
5bccae6e SK |
371 | int ret; |
372 | ||
8ae83b6f | 373 | if (info->regs->read_time_udr_mask) { |
0c5deb1e | 374 | ret = regmap_update_bits(info->regmap, |
a83a793a | 375 | info->regs->udr_update, |
8ae83b6f KK |
376 | info->regs->read_time_udr_mask, |
377 | info->regs->read_time_udr_mask); | |
0c5deb1e KK |
378 | if (ret) { |
379 | dev_err(dev, | |
380 | "Failed to prepare registers for time reading: %d\n", | |
381 | ret); | |
382 | return ret; | |
383 | } | |
384 | } | |
f8b23bbd KK |
385 | ret = regmap_bulk_read(info->regmap, info->regs->time, data, |
386 | info->regs->regs_count); | |
5bccae6e SK |
387 | if (ret < 0) |
388 | return ret; | |
389 | ||
390 | switch (info->device_type) { | |
391 | case S5M8763X: | |
392 | s5m8763_data_to_tm(data, tm); | |
393 | break; | |
394 | ||
395 | case S5M8767X: | |
a65e5efa | 396 | case S2MPS15X: |
0c5deb1e | 397 | case S2MPS14X: |
5281f94a | 398 | case S2MPS13X: |
5bccae6e SK |
399 | s5m8767_data_to_tm(data, tm, info->rtc_24hr_mode); |
400 | break; | |
401 | ||
402 | default: | |
403 | return -EINVAL; | |
404 | } | |
405 | ||
406 | dev_dbg(dev, "%s: %d/%d/%d %d:%d:%d(%d)\n", __func__, | |
407 | 1900 + tm->tm_year, 1 + tm->tm_mon, tm->tm_mday, | |
408 | tm->tm_hour, tm->tm_min, tm->tm_sec, tm->tm_wday); | |
409 | ||
410 | return rtc_valid_tm(tm); | |
411 | } | |
412 | ||
413 | static int s5m_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
414 | { | |
415 | struct s5m_rtc_info *info = dev_get_drvdata(dev); | |
f8b23bbd | 416 | u8 data[info->regs->regs_count]; |
5bccae6e SK |
417 | int ret = 0; |
418 | ||
419 | switch (info->device_type) { | |
420 | case S5M8763X: | |
421 | s5m8763_tm_to_data(tm, data); | |
422 | break; | |
423 | case S5M8767X: | |
a65e5efa | 424 | case S2MPS15X: |
0c5deb1e | 425 | case S2MPS14X: |
5281f94a | 426 | case S2MPS13X: |
5bccae6e SK |
427 | ret = s5m8767_tm_to_data(tm, data); |
428 | break; | |
429 | default: | |
430 | return -EINVAL; | |
431 | } | |
432 | ||
433 | if (ret < 0) | |
434 | return ret; | |
435 | ||
436 | dev_dbg(dev, "%s: %d/%d/%d %d:%d:%d(%d)\n", __func__, | |
437 | 1900 + tm->tm_year, 1 + tm->tm_mon, tm->tm_mday, | |
438 | tm->tm_hour, tm->tm_min, tm->tm_sec, tm->tm_wday); | |
439 | ||
f8b23bbd KK |
440 | ret = regmap_raw_write(info->regmap, info->regs->time, data, |
441 | info->regs->regs_count); | |
5bccae6e SK |
442 | if (ret < 0) |
443 | return ret; | |
444 | ||
445 | ret = s5m8767_rtc_set_time_reg(info); | |
446 | ||
447 | return ret; | |
448 | } | |
449 | ||
450 | static int s5m_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
451 | { | |
452 | struct s5m_rtc_info *info = dev_get_drvdata(dev); | |
f8b23bbd | 453 | u8 data[info->regs->regs_count]; |
5bccae6e SK |
454 | unsigned int val; |
455 | int ret, i; | |
456 | ||
f8b23bbd KK |
457 | ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data, |
458 | info->regs->regs_count); | |
5bccae6e SK |
459 | if (ret < 0) |
460 | return ret; | |
461 | ||
462 | switch (info->device_type) { | |
463 | case S5M8763X: | |
464 | s5m8763_data_to_tm(data, &alrm->time); | |
602cb5bb | 465 | ret = regmap_read(info->regmap, S5M_ALARM0_CONF, &val); |
5bccae6e SK |
466 | if (ret < 0) |
467 | return ret; | |
468 | ||
469 | alrm->enabled = !!val; | |
5bccae6e SK |
470 | break; |
471 | ||
472 | case S5M8767X: | |
a65e5efa | 473 | case S2MPS15X: |
0c5deb1e | 474 | case S2MPS14X: |
5281f94a | 475 | case S2MPS13X: |
5bccae6e | 476 | s5m8767_data_to_tm(data, &alrm->time, info->rtc_24hr_mode); |
5bccae6e | 477 | alrm->enabled = 0; |
f8b23bbd | 478 | for (i = 0; i < info->regs->regs_count; i++) { |
5bccae6e SK |
479 | if (data[i] & ALARM_ENABLE_MASK) { |
480 | alrm->enabled = 1; | |
481 | break; | |
482 | } | |
483 | } | |
5bccae6e SK |
484 | break; |
485 | ||
486 | default: | |
487 | return -EINVAL; | |
488 | } | |
489 | ||
f8b23bbd KK |
490 | dev_dbg(dev, "%s: %d/%d/%d %d:%d:%d(%d)\n", __func__, |
491 | 1900 + alrm->time.tm_year, 1 + alrm->time.tm_mon, | |
492 | alrm->time.tm_mday, alrm->time.tm_hour, | |
493 | alrm->time.tm_min, alrm->time.tm_sec, | |
494 | alrm->time.tm_wday); | |
495 | ||
496 | ret = s5m_check_peding_alarm_interrupt(info, alrm); | |
5bccae6e SK |
497 | |
498 | return 0; | |
499 | } | |
500 | ||
501 | static int s5m_rtc_stop_alarm(struct s5m_rtc_info *info) | |
502 | { | |
f8b23bbd | 503 | u8 data[info->regs->regs_count]; |
5bccae6e SK |
504 | int ret, i; |
505 | struct rtc_time tm; | |
506 | ||
f8b23bbd KK |
507 | ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data, |
508 | info->regs->regs_count); | |
5bccae6e SK |
509 | if (ret < 0) |
510 | return ret; | |
511 | ||
512 | s5m8767_data_to_tm(data, &tm, info->rtc_24hr_mode); | |
513 | dev_dbg(info->dev, "%s: %d/%d/%d %d:%d:%d(%d)\n", __func__, | |
514 | 1900 + tm.tm_year, 1 + tm.tm_mon, tm.tm_mday, | |
515 | tm.tm_hour, tm.tm_min, tm.tm_sec, tm.tm_wday); | |
516 | ||
517 | switch (info->device_type) { | |
518 | case S5M8763X: | |
602cb5bb | 519 | ret = regmap_write(info->regmap, S5M_ALARM0_CONF, 0); |
5bccae6e SK |
520 | break; |
521 | ||
522 | case S5M8767X: | |
a65e5efa | 523 | case S2MPS15X: |
0c5deb1e | 524 | case S2MPS14X: |
5281f94a | 525 | case S2MPS13X: |
f8b23bbd | 526 | for (i = 0; i < info->regs->regs_count; i++) |
5bccae6e SK |
527 | data[i] &= ~ALARM_ENABLE_MASK; |
528 | ||
f8b23bbd KK |
529 | ret = regmap_raw_write(info->regmap, info->regs->alarm0, data, |
530 | info->regs->regs_count); | |
5bccae6e SK |
531 | if (ret < 0) |
532 | return ret; | |
533 | ||
534 | ret = s5m8767_rtc_set_alarm_reg(info); | |
535 | ||
536 | break; | |
537 | ||
538 | default: | |
539 | return -EINVAL; | |
540 | } | |
541 | ||
542 | return ret; | |
543 | } | |
544 | ||
545 | static int s5m_rtc_start_alarm(struct s5m_rtc_info *info) | |
546 | { | |
547 | int ret; | |
f8b23bbd | 548 | u8 data[info->regs->regs_count]; |
5bccae6e SK |
549 | u8 alarm0_conf; |
550 | struct rtc_time tm; | |
551 | ||
f8b23bbd KK |
552 | ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data, |
553 | info->regs->regs_count); | |
5bccae6e SK |
554 | if (ret < 0) |
555 | return ret; | |
556 | ||
557 | s5m8767_data_to_tm(data, &tm, info->rtc_24hr_mode); | |
558 | dev_dbg(info->dev, "%s: %d/%d/%d %d:%d:%d(%d)\n", __func__, | |
559 | 1900 + tm.tm_year, 1 + tm.tm_mon, tm.tm_mday, | |
560 | tm.tm_hour, tm.tm_min, tm.tm_sec, tm.tm_wday); | |
561 | ||
562 | switch (info->device_type) { | |
563 | case S5M8763X: | |
564 | alarm0_conf = 0x77; | |
602cb5bb | 565 | ret = regmap_write(info->regmap, S5M_ALARM0_CONF, alarm0_conf); |
5bccae6e SK |
566 | break; |
567 | ||
568 | case S5M8767X: | |
a65e5efa | 569 | case S2MPS15X: |
0c5deb1e | 570 | case S2MPS14X: |
5281f94a | 571 | case S2MPS13X: |
5bccae6e SK |
572 | data[RTC_SEC] |= ALARM_ENABLE_MASK; |
573 | data[RTC_MIN] |= ALARM_ENABLE_MASK; | |
574 | data[RTC_HOUR] |= ALARM_ENABLE_MASK; | |
575 | data[RTC_WEEKDAY] &= ~ALARM_ENABLE_MASK; | |
576 | if (data[RTC_DATE] & 0x1f) | |
577 | data[RTC_DATE] |= ALARM_ENABLE_MASK; | |
578 | if (data[RTC_MONTH] & 0xf) | |
579 | data[RTC_MONTH] |= ALARM_ENABLE_MASK; | |
580 | if (data[RTC_YEAR1] & 0x7f) | |
581 | data[RTC_YEAR1] |= ALARM_ENABLE_MASK; | |
582 | ||
f8b23bbd KK |
583 | ret = regmap_raw_write(info->regmap, info->regs->alarm0, data, |
584 | info->regs->regs_count); | |
5bccae6e SK |
585 | if (ret < 0) |
586 | return ret; | |
587 | ret = s5m8767_rtc_set_alarm_reg(info); | |
588 | ||
589 | break; | |
590 | ||
591 | default: | |
592 | return -EINVAL; | |
593 | } | |
594 | ||
595 | return ret; | |
596 | } | |
597 | ||
598 | static int s5m_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
599 | { | |
600 | struct s5m_rtc_info *info = dev_get_drvdata(dev); | |
f8b23bbd | 601 | u8 data[info->regs->regs_count]; |
5bccae6e SK |
602 | int ret; |
603 | ||
604 | switch (info->device_type) { | |
605 | case S5M8763X: | |
606 | s5m8763_tm_to_data(&alrm->time, data); | |
607 | break; | |
608 | ||
609 | case S5M8767X: | |
a65e5efa | 610 | case S2MPS15X: |
0c5deb1e | 611 | case S2MPS14X: |
5281f94a | 612 | case S2MPS13X: |
5bccae6e SK |
613 | s5m8767_tm_to_data(&alrm->time, data); |
614 | break; | |
615 | ||
616 | default: | |
617 | return -EINVAL; | |
618 | } | |
619 | ||
620 | dev_dbg(dev, "%s: %d/%d/%d %d:%d:%d(%d)\n", __func__, | |
621 | 1900 + alrm->time.tm_year, 1 + alrm->time.tm_mon, | |
622 | alrm->time.tm_mday, alrm->time.tm_hour, alrm->time.tm_min, | |
623 | alrm->time.tm_sec, alrm->time.tm_wday); | |
624 | ||
625 | ret = s5m_rtc_stop_alarm(info); | |
626 | if (ret < 0) | |
627 | return ret; | |
628 | ||
f8b23bbd KK |
629 | ret = regmap_raw_write(info->regmap, info->regs->alarm0, data, |
630 | info->regs->regs_count); | |
5bccae6e SK |
631 | if (ret < 0) |
632 | return ret; | |
633 | ||
634 | ret = s5m8767_rtc_set_alarm_reg(info); | |
635 | if (ret < 0) | |
636 | return ret; | |
637 | ||
638 | if (alrm->enabled) | |
639 | ret = s5m_rtc_start_alarm(info); | |
640 | ||
641 | return ret; | |
642 | } | |
643 | ||
644 | static int s5m_rtc_alarm_irq_enable(struct device *dev, | |
645 | unsigned int enabled) | |
646 | { | |
647 | struct s5m_rtc_info *info = dev_get_drvdata(dev); | |
648 | ||
649 | if (enabled) | |
650 | return s5m_rtc_start_alarm(info); | |
651 | else | |
652 | return s5m_rtc_stop_alarm(info); | |
653 | } | |
654 | ||
655 | static irqreturn_t s5m_rtc_alarm_irq(int irq, void *data) | |
656 | { | |
657 | struct s5m_rtc_info *info = data; | |
658 | ||
659 | rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF); | |
660 | ||
661 | return IRQ_HANDLED; | |
662 | } | |
663 | ||
664 | static const struct rtc_class_ops s5m_rtc_ops = { | |
665 | .read_time = s5m_rtc_read_time, | |
666 | .set_time = s5m_rtc_set_time, | |
667 | .read_alarm = s5m_rtc_read_alarm, | |
668 | .set_alarm = s5m_rtc_set_alarm, | |
669 | .alarm_irq_enable = s5m_rtc_alarm_irq_enable, | |
670 | }; | |
671 | ||
5bccae6e SK |
672 | static int s5m8767_rtc_init_reg(struct s5m_rtc_info *info) |
673 | { | |
674 | u8 data[2]; | |
5bccae6e | 675 | int ret; |
5bccae6e | 676 | |
0c5deb1e KK |
677 | switch (info->device_type) { |
678 | case S5M8763X: | |
679 | case S5M8767X: | |
680 | /* UDR update time. Default of 7.32 ms is too long. */ | |
681 | ret = regmap_update_bits(info->regmap, S5M_RTC_UDR_CON, | |
682 | S5M_RTC_UDR_T_MASK, S5M_RTC_UDR_T_450_US); | |
683 | if (ret < 0) | |
684 | dev_err(info->dev, "%s: fail to change UDR time: %d\n", | |
685 | __func__, ret); | |
0c5f5d9a | 686 | |
0c5deb1e KK |
687 | /* Set RTC control register : Binary mode, 24hour mode */ |
688 | data[0] = (1 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT); | |
689 | data[1] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT); | |
690 | ||
691 | ret = regmap_raw_write(info->regmap, S5M_ALARM0_CONF, data, 2); | |
692 | break; | |
693 | ||
a65e5efa | 694 | case S2MPS15X: |
0c5deb1e | 695 | case S2MPS14X: |
5281f94a | 696 | case S2MPS13X: |
0c5deb1e KK |
697 | data[0] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT); |
698 | ret = regmap_write(info->regmap, info->regs->ctrl, data[0]); | |
ff02c044 JS |
699 | if (ret < 0) |
700 | break; | |
701 | ||
702 | /* | |
703 | * Should set WUDR & (RUDR or AUDR) bits to high after writing | |
704 | * RTC_CTRL register like writing Alarm registers. We can't find | |
705 | * the description from datasheet but vendor code does that | |
706 | * really. | |
707 | */ | |
708 | ret = s5m8767_rtc_set_alarm_reg(info); | |
0c5deb1e KK |
709 | break; |
710 | ||
711 | default: | |
712 | return -EINVAL; | |
713 | } | |
5bccae6e SK |
714 | |
715 | info->rtc_24hr_mode = 1; | |
5bccae6e SK |
716 | if (ret < 0) { |
717 | dev_err(info->dev, "%s: fail to write controlm reg(%d)\n", | |
718 | __func__, ret); | |
719 | return ret; | |
720 | } | |
721 | ||
5bccae6e SK |
722 | return ret; |
723 | } | |
724 | ||
725 | static int s5m_rtc_probe(struct platform_device *pdev) | |
726 | { | |
727 | struct sec_pmic_dev *s5m87xx = dev_get_drvdata(pdev->dev.parent); | |
728 | struct sec_platform_data *pdata = s5m87xx->pdata; | |
729 | struct s5m_rtc_info *info; | |
e349c910 | 730 | const struct regmap_config *regmap_cfg; |
a0347f20 | 731 | int ret, alarm_irq; |
5bccae6e SK |
732 | |
733 | if (!pdata) { | |
734 | dev_err(pdev->dev.parent, "Platform data not supplied\n"); | |
735 | return -ENODEV; | |
736 | } | |
737 | ||
738 | info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); | |
739 | if (!info) | |
740 | return -ENOMEM; | |
741 | ||
94f91922 | 742 | switch (platform_get_device_id(pdev)->driver_data) { |
a65e5efa | 743 | case S2MPS15X: |
8ae83b6f KK |
744 | regmap_cfg = &s2mps14_rtc_regmap_config; |
745 | info->regs = &s2mps15_rtc_regs; | |
746 | alarm_irq = S2MPS14_IRQ_RTCA0; | |
747 | break; | |
e349c910 | 748 | case S2MPS14X: |
8ae83b6f KK |
749 | regmap_cfg = &s2mps14_rtc_regmap_config; |
750 | info->regs = &s2mps14_rtc_regs; | |
751 | alarm_irq = S2MPS14_IRQ_RTCA0; | |
752 | break; | |
5281f94a | 753 | case S2MPS13X: |
e349c910 | 754 | regmap_cfg = &s2mps14_rtc_regmap_config; |
8ae83b6f | 755 | info->regs = &s2mps13_rtc_regs; |
a0347f20 | 756 | alarm_irq = S2MPS14_IRQ_RTCA0; |
e349c910 KK |
757 | break; |
758 | case S5M8763X: | |
759 | regmap_cfg = &s5m_rtc_regmap_config; | |
f8b23bbd | 760 | info->regs = &s5m_rtc_regs; |
a0347f20 | 761 | alarm_irq = S5M8763_IRQ_ALARM0; |
e349c910 KK |
762 | break; |
763 | case S5M8767X: | |
764 | regmap_cfg = &s5m_rtc_regmap_config; | |
f8b23bbd | 765 | info->regs = &s5m_rtc_regs; |
a0347f20 | 766 | alarm_irq = S5M8767_IRQ_RTCA1; |
e349c910 KK |
767 | break; |
768 | default: | |
94f91922 KK |
769 | dev_err(&pdev->dev, |
770 | "Device type %lu is not supported by RTC driver\n", | |
771 | platform_get_device_id(pdev)->driver_data); | |
e349c910 KK |
772 | return -ENODEV; |
773 | } | |
774 | ||
775 | info->i2c = i2c_new_dummy(s5m87xx->i2c->adapter, RTC_I2C_ADDR); | |
776 | if (!info->i2c) { | |
777 | dev_err(&pdev->dev, "Failed to allocate I2C for RTC\n"); | |
778 | return -ENODEV; | |
779 | } | |
780 | ||
781 | info->regmap = devm_regmap_init_i2c(info->i2c, regmap_cfg); | |
782 | if (IS_ERR(info->regmap)) { | |
783 | ret = PTR_ERR(info->regmap); | |
784 | dev_err(&pdev->dev, "Failed to allocate RTC register map: %d\n", | |
785 | ret); | |
786 | goto err; | |
787 | } | |
788 | ||
5bccae6e SK |
789 | info->dev = &pdev->dev; |
790 | info->s5m87xx = s5m87xx; | |
94f91922 | 791 | info->device_type = platform_get_device_id(pdev)->driver_data; |
5bccae6e | 792 | |
b7d5b9a9 BZ |
793 | if (s5m87xx->irq_data) { |
794 | info->irq = regmap_irq_get_virq(s5m87xx->irq_data, alarm_irq); | |
795 | if (info->irq <= 0) { | |
796 | ret = -EINVAL; | |
797 | dev_err(&pdev->dev, "Failed to get virtual IRQ %d\n", | |
a0347f20 | 798 | alarm_irq); |
b7d5b9a9 BZ |
799 | goto err; |
800 | } | |
5bccae6e SK |
801 | } |
802 | ||
803 | platform_set_drvdata(pdev, info); | |
804 | ||
805 | ret = s5m8767_rtc_init_reg(info); | |
806 | ||
5bccae6e SK |
807 | device_init_wakeup(&pdev->dev, 1); |
808 | ||
809 | info->rtc_dev = devm_rtc_device_register(&pdev->dev, "s5m-rtc", | |
810 | &s5m_rtc_ops, THIS_MODULE); | |
811 | ||
e349c910 KK |
812 | if (IS_ERR(info->rtc_dev)) { |
813 | ret = PTR_ERR(info->rtc_dev); | |
814 | goto err; | |
815 | } | |
5bccae6e | 816 | |
b7d5b9a9 BZ |
817 | if (!info->irq) { |
818 | dev_info(&pdev->dev, "Alarm IRQ not available\n"); | |
819 | return 0; | |
820 | } | |
821 | ||
5bccae6e SK |
822 | ret = devm_request_threaded_irq(&pdev->dev, info->irq, NULL, |
823 | s5m_rtc_alarm_irq, 0, "rtc-alarm0", | |
824 | info); | |
e349c910 | 825 | if (ret < 0) { |
5bccae6e SK |
826 | dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n", |
827 | info->irq, ret); | |
e349c910 KK |
828 | goto err; |
829 | } | |
830 | ||
831 | return 0; | |
832 | ||
833 | err: | |
834 | i2c_unregister_device(info->i2c); | |
5bccae6e SK |
835 | |
836 | return ret; | |
837 | } | |
838 | ||
e349c910 KK |
839 | static int s5m_rtc_remove(struct platform_device *pdev) |
840 | { | |
841 | struct s5m_rtc_info *info = platform_get_drvdata(pdev); | |
842 | ||
e349c910 KK |
843 | i2c_unregister_device(info->i2c); |
844 | ||
845 | return 0; | |
846 | } | |
847 | ||
11ba5a1e | 848 | #ifdef CONFIG_PM_SLEEP |
222ead7f KK |
849 | static int s5m_rtc_resume(struct device *dev) |
850 | { | |
851 | struct s5m_rtc_info *info = dev_get_drvdata(dev); | |
852 | int ret = 0; | |
853 | ||
b7d5b9a9 | 854 | if (info->irq && device_may_wakeup(dev)) |
222ead7f KK |
855 | ret = disable_irq_wake(info->irq); |
856 | ||
857 | return ret; | |
858 | } | |
859 | ||
860 | static int s5m_rtc_suspend(struct device *dev) | |
861 | { | |
862 | struct s5m_rtc_info *info = dev_get_drvdata(dev); | |
863 | int ret = 0; | |
864 | ||
b7d5b9a9 | 865 | if (info->irq && device_may_wakeup(dev)) |
222ead7f KK |
866 | ret = enable_irq_wake(info->irq); |
867 | ||
868 | return ret; | |
869 | } | |
11ba5a1e | 870 | #endif /* CONFIG_PM_SLEEP */ |
222ead7f KK |
871 | |
872 | static SIMPLE_DEV_PM_OPS(s5m_rtc_pm_ops, s5m_rtc_suspend, s5m_rtc_resume); | |
873 | ||
5bccae6e | 874 | static const struct platform_device_id s5m_rtc_id[] = { |
0c5deb1e | 875 | { "s5m-rtc", S5M8767X }, |
5281f94a | 876 | { "s2mps13-rtc", S2MPS13X }, |
0c5deb1e | 877 | { "s2mps14-rtc", S2MPS14X }, |
a65e5efa | 878 | { "s2mps15-rtc", S2MPS15X }, |
45cd15e6 | 879 | { }, |
5bccae6e | 880 | }; |
63074cc3 | 881 | MODULE_DEVICE_TABLE(platform, s5m_rtc_id); |
5bccae6e SK |
882 | |
883 | static struct platform_driver s5m_rtc_driver = { | |
884 | .driver = { | |
885 | .name = "s5m-rtc", | |
222ead7f | 886 | .pm = &s5m_rtc_pm_ops, |
5bccae6e SK |
887 | }, |
888 | .probe = s5m_rtc_probe, | |
e349c910 | 889 | .remove = s5m_rtc_remove, |
5bccae6e SK |
890 | .id_table = s5m_rtc_id, |
891 | }; | |
892 | ||
893 | module_platform_driver(s5m_rtc_driver); | |
894 | ||
895 | /* Module information */ | |
896 | MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>"); | |
0c5deb1e | 897 | MODULE_DESCRIPTION("Samsung S5M/S2MPS14 RTC driver"); |
5bccae6e SK |
898 | MODULE_LICENSE("GPL"); |
899 | MODULE_ALIAS("platform:s5m-rtc"); |