Commit | Line | Data |
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e842f1c8 RP |
1 | /* |
2 | * Real Time Clock interface for StrongARM SA1x00 and XScale PXA2xx | |
3 | * | |
4 | * Copyright (c) 2000 Nils Faerber | |
5 | * | |
6 | * Based on rtc.c by Paul Gortmaker | |
7 | * | |
8 | * Original Driver by Nils Faerber <nils@kernelconcepts.de> | |
9 | * | |
10 | * Modifications from: | |
11 | * CIH <cih@coventive.com> | |
2f82af08 | 12 | * Nicolas Pitre <nico@fluxnic.net> |
e842f1c8 RP |
13 | * Andrew Christian <andrew.christian@hp.com> |
14 | * | |
15 | * Converted to the RTC subsystem and Driver Model | |
16 | * by Richard Purdie <rpurdie@rpsys.net> | |
17 | * | |
18 | * This program is free software; you can redistribute it and/or | |
19 | * modify it under the terms of the GNU General Public License | |
20 | * as published by the Free Software Foundation; either version | |
21 | * 2 of the License, or (at your option) any later version. | |
22 | */ | |
23 | ||
24 | #include <linux/platform_device.h> | |
25 | #include <linux/module.h> | |
8e8bbcb3 | 26 | #include <linux/clk.h> |
e842f1c8 RP |
27 | #include <linux/rtc.h> |
28 | #include <linux/init.h> | |
29 | #include <linux/fs.h> | |
30 | #include <linux/interrupt.h> | |
3888c090 | 31 | #include <linux/slab.h> |
a0164a57 | 32 | #include <linux/string.h> |
8bec2e9e | 33 | #include <linux/of.h> |
e842f1c8 | 34 | #include <linux/pm.h> |
a0164a57 | 35 | #include <linux/bitops.h> |
23019a73 | 36 | #include <linux/io.h> |
e842f1c8 | 37 | |
a09e64fb | 38 | #include <mach/hardware.h> |
905cdc88 | 39 | #include <mach/irqs.h> |
e842f1c8 | 40 | |
3888c090 | 41 | #if defined(CONFIG_ARCH_PXA) || defined(CONFIG_ARCH_MMP) |
a0164a57 RK |
42 | #include <mach/regs-rtc.h> |
43 | #endif | |
44 | ||
a404ad1f | 45 | #define RTC_DEF_DIVIDER (32768 - 1) |
e842f1c8 | 46 | #define RTC_DEF_TRIM 0 |
3888c090 | 47 | #define RTC_FREQ 1024 |
a0164a57 | 48 | |
3888c090 HZ |
49 | struct sa1100_rtc { |
50 | spinlock_t lock; | |
51 | int irq_1hz; | |
52 | int irq_alarm; | |
53 | struct rtc_device *rtc; | |
8e8bbcb3 | 54 | struct clk *clk; |
3888c090 | 55 | }; |
a0164a57 | 56 | |
7d12e780 | 57 | static irqreturn_t sa1100_rtc_interrupt(int irq, void *dev_id) |
e842f1c8 | 58 | { |
3888c090 HZ |
59 | struct sa1100_rtc *info = dev_get_drvdata(dev_id); |
60 | struct rtc_device *rtc = info->rtc; | |
e842f1c8 RP |
61 | unsigned int rtsr; |
62 | unsigned long events = 0; | |
63 | ||
3888c090 | 64 | spin_lock(&info->lock); |
e842f1c8 | 65 | |
a0164a57 | 66 | rtsr = RTSR; |
e842f1c8 | 67 | /* clear interrupt sources */ |
a0164a57 | 68 | RTSR = 0; |
7decaa55 MRJ |
69 | /* Fix for a nasty initialization problem the in SA11xx RTSR register. |
70 | * See also the comments in sa1100_rtc_probe(). */ | |
71 | if (rtsr & (RTSR_ALE | RTSR_HZE)) { | |
72 | /* This is the original code, before there was the if test | |
73 | * above. This code does not clear interrupts that were not | |
74 | * enabled. */ | |
a0164a57 | 75 | RTSR = (RTSR_AL | RTSR_HZ) & (rtsr >> 2); |
7decaa55 MRJ |
76 | } else { |
77 | /* For some reason, it is possible to enter this routine | |
78 | * without interruptions enabled, it has been tested with | |
79 | * several units (Bug in SA11xx chip?). | |
80 | * | |
81 | * This situation leads to an infinite "loop" of interrupt | |
82 | * routine calling and as a result the processor seems to | |
83 | * lock on its first call to open(). */ | |
a0164a57 | 84 | RTSR = RTSR_AL | RTSR_HZ; |
7decaa55 | 85 | } |
e842f1c8 RP |
86 | |
87 | /* clear alarm interrupt if it has occurred */ | |
88 | if (rtsr & RTSR_AL) | |
89 | rtsr &= ~RTSR_ALE; | |
a0164a57 | 90 | RTSR = rtsr & (RTSR_ALE | RTSR_HZE); |
e842f1c8 RP |
91 | |
92 | /* update irq data & counter */ | |
93 | if (rtsr & RTSR_AL) | |
94 | events |= RTC_AF | RTC_IRQF; | |
95 | if (rtsr & RTSR_HZ) | |
96 | events |= RTC_UF | RTC_IRQF; | |
97 | ||
a0164a57 | 98 | rtc_update_irq(rtc, 1, events); |
e842f1c8 | 99 | |
3888c090 | 100 | spin_unlock(&info->lock); |
e842f1c8 RP |
101 | |
102 | return IRQ_HANDLED; | |
103 | } | |
104 | ||
e842f1c8 RP |
105 | static int sa1100_rtc_open(struct device *dev) |
106 | { | |
3888c090 HZ |
107 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
108 | struct rtc_device *rtc = info->rtc; | |
e842f1c8 RP |
109 | int ret; |
110 | ||
34800598 | 111 | ret = request_irq(info->irq_1hz, sa1100_rtc_interrupt, 0, "rtc 1Hz", dev); |
e842f1c8 | 112 | if (ret) { |
3888c090 | 113 | dev_err(dev, "IRQ %d already in use.\n", info->irq_1hz); |
e842f1c8 RP |
114 | goto fail_ui; |
115 | } | |
34800598 | 116 | ret = request_irq(info->irq_alarm, sa1100_rtc_interrupt, 0, "rtc Alrm", dev); |
e842f1c8 | 117 | if (ret) { |
3888c090 | 118 | dev_err(dev, "IRQ %d already in use.\n", info->irq_alarm); |
e842f1c8 RP |
119 | goto fail_ai; |
120 | } | |
a0164a57 RK |
121 | rtc->max_user_freq = RTC_FREQ; |
122 | rtc_irq_set_freq(rtc, NULL, RTC_FREQ); | |
d2ccb52d | 123 | |
e842f1c8 RP |
124 | return 0; |
125 | ||
e842f1c8 | 126 | fail_ai: |
3888c090 | 127 | free_irq(info->irq_1hz, dev); |
e842f1c8 | 128 | fail_ui: |
8e8bbcb3 | 129 | clk_disable_unprepare(info->clk); |
e842f1c8 RP |
130 | return ret; |
131 | } | |
132 | ||
133 | static void sa1100_rtc_release(struct device *dev) | |
134 | { | |
3888c090 HZ |
135 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
136 | ||
137 | spin_lock_irq(&info->lock); | |
a0164a57 | 138 | RTSR = 0; |
3888c090 | 139 | spin_unlock_irq(&info->lock); |
e842f1c8 | 140 | |
3888c090 HZ |
141 | free_irq(info->irq_alarm, dev); |
142 | free_irq(info->irq_1hz, dev); | |
e842f1c8 RP |
143 | } |
144 | ||
16380c15 JS |
145 | static int sa1100_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
146 | { | |
3888c090 HZ |
147 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
148 | ||
149 | spin_lock_irq(&info->lock); | |
16380c15 | 150 | if (enabled) |
a0164a57 | 151 | RTSR |= RTSR_ALE; |
16380c15 | 152 | else |
a0164a57 | 153 | RTSR &= ~RTSR_ALE; |
3888c090 | 154 | spin_unlock_irq(&info->lock); |
16380c15 JS |
155 | return 0; |
156 | } | |
157 | ||
e842f1c8 RP |
158 | static int sa1100_rtc_read_time(struct device *dev, struct rtc_time *tm) |
159 | { | |
a0164a57 | 160 | rtc_time_to_tm(RCNR, tm); |
e842f1c8 RP |
161 | return 0; |
162 | } | |
163 | ||
164 | static int sa1100_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
165 | { | |
166 | unsigned long time; | |
167 | int ret; | |
168 | ||
169 | ret = rtc_tm_to_time(tm, &time); | |
170 | if (ret == 0) | |
a0164a57 | 171 | RCNR = time; |
e842f1c8 RP |
172 | return ret; |
173 | } | |
174 | ||
175 | static int sa1100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
176 | { | |
a0164a57 | 177 | u32 rtsr; |
32b49da4 | 178 | |
a0164a57 | 179 | rtsr = RTSR; |
32b49da4 DB |
180 | alrm->enabled = (rtsr & RTSR_ALE) ? 1 : 0; |
181 | alrm->pending = (rtsr & RTSR_AL) ? 1 : 0; | |
e842f1c8 RP |
182 | return 0; |
183 | } | |
184 | ||
185 | static int sa1100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
186 | { | |
3888c090 | 187 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
1d8c38c3 | 188 | unsigned long time; |
a0164a57 | 189 | int ret; |
e842f1c8 | 190 | |
3888c090 | 191 | spin_lock_irq(&info->lock); |
1d8c38c3 HZ |
192 | ret = rtc_tm_to_time(&alrm->time, &time); |
193 | if (ret != 0) | |
194 | goto out; | |
195 | RTSR = RTSR & (RTSR_HZE|RTSR_ALE|RTSR_AL); | |
196 | RTAR = time; | |
197 | if (alrm->enabled) | |
198 | RTSR |= RTSR_ALE; | |
199 | else | |
200 | RTSR &= ~RTSR_ALE; | |
201 | out: | |
3888c090 | 202 | spin_unlock_irq(&info->lock); |
e842f1c8 | 203 | |
a0164a57 | 204 | return ret; |
e842f1c8 RP |
205 | } |
206 | ||
207 | static int sa1100_rtc_proc(struct device *dev, struct seq_file *seq) | |
208 | { | |
a0164a57 RK |
209 | seq_printf(seq, "trim/divider\t\t: 0x%08x\n", (u32) RTTR); |
210 | seq_printf(seq, "RTSR\t\t\t: 0x%08x\n", (u32)RTSR); | |
e842f1c8 RP |
211 | |
212 | return 0; | |
213 | } | |
214 | ||
ff8371ac | 215 | static const struct rtc_class_ops sa1100_rtc_ops = { |
e842f1c8 | 216 | .open = sa1100_rtc_open, |
e842f1c8 | 217 | .release = sa1100_rtc_release, |
e842f1c8 RP |
218 | .read_time = sa1100_rtc_read_time, |
219 | .set_time = sa1100_rtc_set_time, | |
220 | .read_alarm = sa1100_rtc_read_alarm, | |
221 | .set_alarm = sa1100_rtc_set_alarm, | |
222 | .proc = sa1100_rtc_proc, | |
16380c15 | 223 | .alarm_irq_enable = sa1100_rtc_alarm_irq_enable, |
e842f1c8 RP |
224 | }; |
225 | ||
226 | static int sa1100_rtc_probe(struct platform_device *pdev) | |
227 | { | |
a0164a57 | 228 | struct rtc_device *rtc; |
3888c090 HZ |
229 | struct sa1100_rtc *info; |
230 | int irq_1hz, irq_alarm, ret = 0; | |
231 | ||
232 | irq_1hz = platform_get_irq_byname(pdev, "rtc 1Hz"); | |
233 | irq_alarm = platform_get_irq_byname(pdev, "rtc alarm"); | |
234 | if (irq_1hz < 0 || irq_alarm < 0) | |
235 | return -ENODEV; | |
236 | ||
55d735ef | 237 | info = devm_kzalloc(&pdev->dev, sizeof(struct sa1100_rtc), GFP_KERNEL); |
3888c090 HZ |
238 | if (!info) |
239 | return -ENOMEM; | |
55d735ef | 240 | info->clk = devm_clk_get(&pdev->dev, NULL); |
8e8bbcb3 HZ |
241 | if (IS_ERR(info->clk)) { |
242 | dev_err(&pdev->dev, "failed to find rtc clock source\n"); | |
55d735ef | 243 | return PTR_ERR(info->clk); |
8e8bbcb3 | 244 | } |
3888c090 HZ |
245 | info->irq_1hz = irq_1hz; |
246 | info->irq_alarm = irq_alarm; | |
247 | spin_lock_init(&info->lock); | |
248 | platform_set_drvdata(pdev, info); | |
e842f1c8 | 249 | |
0cc0c38e CX |
250 | ret = clk_prepare_enable(info->clk); |
251 | if (ret) | |
66600bbe | 252 | return ret; |
e842f1c8 RP |
253 | /* |
254 | * According to the manual we should be able to let RTTR be zero | |
255 | * and then a default diviser for a 32.768KHz clock is used. | |
256 | * Apparently this doesn't work, at least for my SA1110 rev 5. | |
257 | * If the clock divider is uninitialized then reset it to the | |
258 | * default value to get the 1Hz clock. | |
259 | */ | |
a0164a57 RK |
260 | if (RTTR == 0) { |
261 | RTTR = RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16); | |
262 | dev_warn(&pdev->dev, "warning: " | |
263 | "initializing default clock divider/trim value\n"); | |
e842f1c8 | 264 | /* The current RTC value probably doesn't make sense either */ |
a0164a57 | 265 | RCNR = 0; |
e842f1c8 RP |
266 | } |
267 | ||
e5a2c9cc UL |
268 | device_init_wakeup(&pdev->dev, 1); |
269 | ||
55d735ef JH |
270 | rtc = devm_rtc_device_register(&pdev->dev, pdev->name, &sa1100_rtc_ops, |
271 | THIS_MODULE); | |
a0164a57 | 272 | |
3888c090 HZ |
273 | if (IS_ERR(rtc)) { |
274 | ret = PTR_ERR(rtc); | |
275 | goto err_dev; | |
276 | } | |
277 | info->rtc = rtc; | |
a0164a57 | 278 | |
7decaa55 MRJ |
279 | /* Fix for a nasty initialization problem the in SA11xx RTSR register. |
280 | * See also the comments in sa1100_rtc_interrupt(). | |
281 | * | |
282 | * Sometimes bit 1 of the RTSR (RTSR_HZ) will wake up 1, which means an | |
283 | * interrupt pending, even though interrupts were never enabled. | |
284 | * In this case, this bit it must be reset before enabling | |
285 | * interruptions to avoid a nonexistent interrupt to occur. | |
286 | * | |
287 | * In principle, the same problem would apply to bit 0, although it has | |
288 | * never been observed to happen. | |
289 | * | |
290 | * This issue is addressed both here and in sa1100_rtc_interrupt(). | |
291 | * If the issue is not addressed here, in the times when the processor | |
292 | * wakes up with the bit set there will be one spurious interrupt. | |
293 | * | |
294 | * The issue is also dealt with in sa1100_rtc_interrupt() to be on the | |
295 | * safe side, once the condition that lead to this strange | |
296 | * initialization is unknown and could in principle happen during | |
297 | * normal processing. | |
298 | * | |
299 | * Notice that clearing bit 1 and 0 is accomplished by writting ONES to | |
300 | * the corresponding bits in RTSR. */ | |
a0164a57 | 301 | RTSR = RTSR_AL | RTSR_HZ; |
7decaa55 | 302 | |
e842f1c8 | 303 | return 0; |
3888c090 | 304 | err_dev: |
0cc0c38e | 305 | clk_disable_unprepare(info->clk); |
3888c090 | 306 | return ret; |
e842f1c8 RP |
307 | } |
308 | ||
309 | static int sa1100_rtc_remove(struct platform_device *pdev) | |
310 | { | |
3888c090 | 311 | struct sa1100_rtc *info = platform_get_drvdata(pdev); |
a0164a57 | 312 | |
66600bbe | 313 | if (info) |
0cc0c38e | 314 | clk_disable_unprepare(info->clk); |
e842f1c8 RP |
315 | |
316 | return 0; | |
317 | } | |
318 | ||
aaa92fae | 319 | #ifdef CONFIG_PM_SLEEP |
5d027cd2 | 320 | static int sa1100_rtc_suspend(struct device *dev) |
6bc54e69 | 321 | { |
3888c090 | 322 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
5d027cd2 | 323 | if (device_may_wakeup(dev)) |
3888c090 | 324 | enable_irq_wake(info->irq_alarm); |
6bc54e69 RK |
325 | return 0; |
326 | } | |
327 | ||
5d027cd2 | 328 | static int sa1100_rtc_resume(struct device *dev) |
6bc54e69 | 329 | { |
3888c090 | 330 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
5d027cd2 | 331 | if (device_may_wakeup(dev)) |
3888c090 | 332 | disable_irq_wake(info->irq_alarm); |
6bc54e69 RK |
333 | return 0; |
334 | } | |
6bc54e69 RK |
335 | #endif |
336 | ||
aaa92fae JH |
337 | static SIMPLE_DEV_PM_OPS(sa1100_rtc_pm_ops, sa1100_rtc_suspend, |
338 | sa1100_rtc_resume); | |
339 | ||
c8a6046e | 340 | #ifdef CONFIG_OF |
8bec2e9e HZ |
341 | static struct of_device_id sa1100_rtc_dt_ids[] = { |
342 | { .compatible = "mrvl,sa1100-rtc", }, | |
343 | { .compatible = "mrvl,mmp-rtc", }, | |
344 | {} | |
345 | }; | |
346 | MODULE_DEVICE_TABLE(of, sa1100_rtc_dt_ids); | |
c8a6046e | 347 | #endif |
8bec2e9e | 348 | |
e842f1c8 RP |
349 | static struct platform_driver sa1100_rtc_driver = { |
350 | .probe = sa1100_rtc_probe, | |
351 | .remove = sa1100_rtc_remove, | |
352 | .driver = { | |
5d027cd2 | 353 | .name = "sa1100-rtc", |
5d027cd2 | 354 | .pm = &sa1100_rtc_pm_ops, |
c8a6046e | 355 | .of_match_table = of_match_ptr(sa1100_rtc_dt_ids), |
e842f1c8 RP |
356 | }, |
357 | }; | |
358 | ||
0c4eae66 | 359 | module_platform_driver(sa1100_rtc_driver); |
e842f1c8 RP |
360 | |
361 | MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>"); | |
362 | MODULE_DESCRIPTION("SA11x0/PXA2xx Realtime Clock Driver (RTC)"); | |
363 | MODULE_LICENSE("GPL"); | |
ad28a07b | 364 | MODULE_ALIAS("platform:sa1100-rtc"); |