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e842f1c8 RP |
1 | /* |
2 | * Real Time Clock interface for StrongARM SA1x00 and XScale PXA2xx | |
3 | * | |
4 | * Copyright (c) 2000 Nils Faerber | |
5 | * | |
6 | * Based on rtc.c by Paul Gortmaker | |
7 | * | |
8 | * Original Driver by Nils Faerber <nils@kernelconcepts.de> | |
9 | * | |
10 | * Modifications from: | |
11 | * CIH <cih@coventive.com> | |
12 | * Nicolas Pitre <nico@cam.org> | |
13 | * Andrew Christian <andrew.christian@hp.com> | |
14 | * | |
15 | * Converted to the RTC subsystem and Driver Model | |
16 | * by Richard Purdie <rpurdie@rpsys.net> | |
17 | * | |
18 | * This program is free software; you can redistribute it and/or | |
19 | * modify it under the terms of the GNU General Public License | |
20 | * as published by the Free Software Foundation; either version | |
21 | * 2 of the License, or (at your option) any later version. | |
22 | */ | |
23 | ||
24 | #include <linux/platform_device.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/rtc.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/fs.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/string.h> | |
31 | #include <linux/pm.h> | |
32 | ||
33 | #include <asm/bitops.h> | |
34 | #include <asm/hardware.h> | |
35 | #include <asm/irq.h> | |
36 | #include <asm/rtc.h> | |
37 | ||
38 | #ifdef CONFIG_ARCH_PXA | |
39 | #include <asm/arch/pxa-regs.h> | |
40 | #endif | |
41 | ||
42 | #define TIMER_FREQ CLOCK_TICK_RATE | |
43 | #define RTC_DEF_DIVIDER 32768 - 1 | |
44 | #define RTC_DEF_TRIM 0 | |
45 | ||
46 | static unsigned long rtc_freq = 1024; | |
47 | static struct rtc_time rtc_alarm; | |
48 | static spinlock_t sa1100_rtc_lock = SPIN_LOCK_UNLOCKED; | |
49 | ||
50 | static int rtc_update_alarm(struct rtc_time *alrm) | |
51 | { | |
52 | struct rtc_time alarm_tm, now_tm; | |
53 | unsigned long now, time; | |
54 | int ret; | |
55 | ||
56 | do { | |
57 | now = RCNR; | |
58 | rtc_time_to_tm(now, &now_tm); | |
59 | rtc_next_alarm_time(&alarm_tm, &now_tm, alrm); | |
60 | ret = rtc_tm_to_time(&alarm_tm, &time); | |
61 | if (ret != 0) | |
62 | break; | |
63 | ||
64 | RTSR = RTSR & (RTSR_HZE|RTSR_ALE|RTSR_AL); | |
65 | RTAR = time; | |
66 | } while (now != RCNR); | |
67 | ||
68 | return ret; | |
69 | } | |
70 | ||
71 | static irqreturn_t sa1100_rtc_interrupt(int irq, void *dev_id, | |
72 | struct pt_regs *regs) | |
73 | { | |
74 | struct platform_device *pdev = to_platform_device(dev_id); | |
75 | struct rtc_device *rtc = platform_get_drvdata(pdev); | |
76 | unsigned int rtsr; | |
77 | unsigned long events = 0; | |
78 | ||
79 | spin_lock(&sa1100_rtc_lock); | |
80 | ||
81 | rtsr = RTSR; | |
82 | /* clear interrupt sources */ | |
83 | RTSR = 0; | |
84 | RTSR = (RTSR_AL | RTSR_HZ) & (rtsr >> 2); | |
85 | ||
86 | /* clear alarm interrupt if it has occurred */ | |
87 | if (rtsr & RTSR_AL) | |
88 | rtsr &= ~RTSR_ALE; | |
89 | RTSR = rtsr & (RTSR_ALE | RTSR_HZE); | |
90 | ||
91 | /* update irq data & counter */ | |
92 | if (rtsr & RTSR_AL) | |
93 | events |= RTC_AF | RTC_IRQF; | |
94 | if (rtsr & RTSR_HZ) | |
95 | events |= RTC_UF | RTC_IRQF; | |
96 | ||
97 | rtc_update_irq(&rtc->class_dev, 1, events); | |
98 | ||
99 | if (rtsr & RTSR_AL && rtc_periodic_alarm(&rtc_alarm)) | |
100 | rtc_update_alarm(&rtc_alarm); | |
101 | ||
102 | spin_unlock(&sa1100_rtc_lock); | |
103 | ||
104 | return IRQ_HANDLED; | |
105 | } | |
106 | ||
107 | static int rtc_timer1_count; | |
108 | ||
109 | static irqreturn_t timer1_interrupt(int irq, void *dev_id, | |
110 | struct pt_regs *regs) | |
111 | { | |
112 | struct platform_device *pdev = to_platform_device(dev_id); | |
113 | struct rtc_device *rtc = platform_get_drvdata(pdev); | |
114 | ||
115 | /* | |
116 | * If we match for the first time, rtc_timer1_count will be 1. | |
117 | * Otherwise, we wrapped around (very unlikely but | |
118 | * still possible) so compute the amount of missed periods. | |
119 | * The match reg is updated only when the data is actually retrieved | |
120 | * to avoid unnecessary interrupts. | |
121 | */ | |
122 | OSSR = OSSR_M1; /* clear match on timer1 */ | |
123 | ||
124 | rtc_update_irq(&rtc->class_dev, rtc_timer1_count, RTC_PF | RTC_IRQF); | |
125 | ||
126 | if (rtc_timer1_count == 1) | |
127 | rtc_timer1_count = (rtc_freq * ((1<<30)/(TIMER_FREQ>>2))); | |
128 | ||
129 | return IRQ_HANDLED; | |
130 | } | |
131 | ||
132 | static int sa1100_rtc_read_callback(struct device *dev, int data) | |
133 | { | |
134 | if (data & RTC_PF) { | |
135 | /* interpolate missed periods and set match for the next */ | |
136 | unsigned long period = TIMER_FREQ/rtc_freq; | |
137 | unsigned long oscr = OSCR; | |
138 | unsigned long osmr1 = OSMR1; | |
139 | unsigned long missed = (oscr - osmr1)/period; | |
140 | data += missed << 8; | |
141 | OSSR = OSSR_M1; /* clear match on timer 1 */ | |
142 | OSMR1 = osmr1 + (missed + 1)*period; | |
143 | /* Ensure we didn't miss another match in the mean time. | |
144 | * Here we compare (match - OSCR) 8 instead of 0 -- | |
145 | * see comment in pxa_timer_interrupt() for explanation. | |
146 | */ | |
147 | while( (signed long)((osmr1 = OSMR1) - OSCR) <= 8 ) { | |
148 | data += 0x100; | |
149 | OSSR = OSSR_M1; /* clear match on timer 1 */ | |
150 | OSMR1 = osmr1 + period; | |
151 | } | |
152 | } | |
153 | return data; | |
154 | } | |
155 | ||
156 | static int sa1100_rtc_open(struct device *dev) | |
157 | { | |
158 | int ret; | |
159 | ||
160 | ret = request_irq(IRQ_RTC1Hz, sa1100_rtc_interrupt, SA_INTERRUPT, | |
161 | "rtc 1Hz", dev); | |
162 | if (ret) { | |
2260a25c | 163 | dev_err(dev, "IRQ %d already in use.\n", IRQ_RTC1Hz); |
e842f1c8 RP |
164 | goto fail_ui; |
165 | } | |
166 | ret = request_irq(IRQ_RTCAlrm, sa1100_rtc_interrupt, SA_INTERRUPT, | |
167 | "rtc Alrm", dev); | |
168 | if (ret) { | |
2260a25c | 169 | dev_err(dev, "IRQ %d already in use.\n", IRQ_RTCAlrm); |
e842f1c8 RP |
170 | goto fail_ai; |
171 | } | |
172 | ret = request_irq(IRQ_OST1, timer1_interrupt, SA_INTERRUPT, | |
173 | "rtc timer", dev); | |
174 | if (ret) { | |
2260a25c | 175 | dev_err(dev, "IRQ %d already in use.\n", IRQ_OST1); |
e842f1c8 RP |
176 | goto fail_pi; |
177 | } | |
178 | return 0; | |
179 | ||
180 | fail_pi: | |
f1226701 | 181 | free_irq(IRQ_RTCAlrm, dev); |
e842f1c8 | 182 | fail_ai: |
f1226701 | 183 | free_irq(IRQ_RTC1Hz, dev); |
e842f1c8 RP |
184 | fail_ui: |
185 | return ret; | |
186 | } | |
187 | ||
188 | static void sa1100_rtc_release(struct device *dev) | |
189 | { | |
190 | spin_lock_irq(&sa1100_rtc_lock); | |
191 | RTSR = 0; | |
192 | OIER &= ~OIER_E1; | |
193 | OSSR = OSSR_M1; | |
194 | spin_unlock_irq(&sa1100_rtc_lock); | |
195 | ||
196 | free_irq(IRQ_OST1, dev); | |
197 | free_irq(IRQ_RTCAlrm, dev); | |
198 | free_irq(IRQ_RTC1Hz, dev); | |
199 | } | |
200 | ||
201 | ||
202 | static int sa1100_rtc_ioctl(struct device *dev, unsigned int cmd, | |
203 | unsigned long arg) | |
204 | { | |
205 | switch(cmd) { | |
206 | case RTC_AIE_OFF: | |
207 | spin_lock_irq(&sa1100_rtc_lock); | |
208 | RTSR &= ~RTSR_ALE; | |
209 | spin_unlock_irq(&sa1100_rtc_lock); | |
210 | return 0; | |
211 | case RTC_AIE_ON: | |
212 | spin_lock_irq(&sa1100_rtc_lock); | |
213 | RTSR |= RTSR_ALE; | |
214 | spin_unlock_irq(&sa1100_rtc_lock); | |
215 | return 0; | |
216 | case RTC_UIE_OFF: | |
217 | spin_lock_irq(&sa1100_rtc_lock); | |
218 | RTSR &= ~RTSR_HZE; | |
219 | spin_unlock_irq(&sa1100_rtc_lock); | |
220 | return 0; | |
221 | case RTC_UIE_ON: | |
222 | spin_lock_irq(&sa1100_rtc_lock); | |
223 | RTSR |= RTSR_HZE; | |
224 | spin_unlock_irq(&sa1100_rtc_lock); | |
225 | return 0; | |
226 | case RTC_PIE_OFF: | |
227 | spin_lock_irq(&sa1100_rtc_lock); | |
228 | OIER &= ~OIER_E1; | |
229 | spin_unlock_irq(&sa1100_rtc_lock); | |
230 | return 0; | |
231 | case RTC_PIE_ON: | |
232 | if ((rtc_freq > 64) && !capable(CAP_SYS_RESOURCE)) | |
233 | return -EACCES; | |
234 | spin_lock_irq(&sa1100_rtc_lock); | |
235 | OSMR1 = TIMER_FREQ/rtc_freq + OSCR; | |
236 | OIER |= OIER_E1; | |
237 | rtc_timer1_count = 1; | |
238 | spin_unlock_irq(&sa1100_rtc_lock); | |
239 | return 0; | |
240 | case RTC_IRQP_READ: | |
241 | return put_user(rtc_freq, (unsigned long *)arg); | |
242 | case RTC_IRQP_SET: | |
243 | if (arg < 1 || arg > TIMER_FREQ) | |
244 | return -EINVAL; | |
245 | if ((arg > 64) && (!capable(CAP_SYS_RESOURCE))) | |
246 | return -EACCES; | |
247 | rtc_freq = arg; | |
248 | return 0; | |
249 | } | |
250 | return -EINVAL; | |
251 | } | |
252 | ||
253 | static int sa1100_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
254 | { | |
255 | rtc_time_to_tm(RCNR, tm); | |
256 | return 0; | |
257 | } | |
258 | ||
259 | static int sa1100_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
260 | { | |
261 | unsigned long time; | |
262 | int ret; | |
263 | ||
264 | ret = rtc_tm_to_time(tm, &time); | |
265 | if (ret == 0) | |
266 | RCNR = time; | |
267 | return ret; | |
268 | } | |
269 | ||
270 | static int sa1100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
271 | { | |
272 | memcpy(&alrm->time, &rtc_alarm, sizeof(struct rtc_time)); | |
273 | alrm->pending = RTSR & RTSR_AL ? 1 : 0; | |
274 | return 0; | |
275 | } | |
276 | ||
277 | static int sa1100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
278 | { | |
279 | int ret; | |
280 | ||
281 | spin_lock_irq(&sa1100_rtc_lock); | |
282 | ret = rtc_update_alarm(&alrm->time); | |
283 | if (ret == 0) { | |
284 | memcpy(&rtc_alarm, &alrm->time, sizeof(struct rtc_time)); | |
285 | ||
286 | if (alrm->enabled) | |
287 | enable_irq_wake(IRQ_RTCAlrm); | |
288 | else | |
289 | disable_irq_wake(IRQ_RTCAlrm); | |
290 | } | |
291 | spin_unlock_irq(&sa1100_rtc_lock); | |
292 | ||
293 | return ret; | |
294 | } | |
295 | ||
296 | static int sa1100_rtc_proc(struct device *dev, struct seq_file *seq) | |
297 | { | |
f1226701 | 298 | seq_printf(seq, "trim/divider\t: 0x%08lx\n", RTTR); |
e842f1c8 RP |
299 | seq_printf(seq, "alarm_IRQ\t: %s\n", |
300 | (RTSR & RTSR_ALE) ? "yes" : "no" ); | |
301 | seq_printf(seq, "update_IRQ\t: %s\n", | |
302 | (RTSR & RTSR_HZE) ? "yes" : "no"); | |
303 | seq_printf(seq, "periodic_IRQ\t: %s\n", | |
304 | (OIER & OIER_E1) ? "yes" : "no"); | |
305 | seq_printf(seq, "periodic_freq\t: %ld\n", rtc_freq); | |
306 | ||
307 | return 0; | |
308 | } | |
309 | ||
310 | static struct rtc_class_ops sa1100_rtc_ops = { | |
311 | .open = sa1100_rtc_open, | |
312 | .read_callback = sa1100_rtc_read_callback, | |
313 | .release = sa1100_rtc_release, | |
314 | .ioctl = sa1100_rtc_ioctl, | |
315 | .read_time = sa1100_rtc_read_time, | |
316 | .set_time = sa1100_rtc_set_time, | |
317 | .read_alarm = sa1100_rtc_read_alarm, | |
318 | .set_alarm = sa1100_rtc_set_alarm, | |
319 | .proc = sa1100_rtc_proc, | |
320 | }; | |
321 | ||
322 | static int sa1100_rtc_probe(struct platform_device *pdev) | |
323 | { | |
324 | struct rtc_device *rtc; | |
325 | ||
326 | /* | |
327 | * According to the manual we should be able to let RTTR be zero | |
328 | * and then a default diviser for a 32.768KHz clock is used. | |
329 | * Apparently this doesn't work, at least for my SA1110 rev 5. | |
330 | * If the clock divider is uninitialized then reset it to the | |
331 | * default value to get the 1Hz clock. | |
332 | */ | |
333 | if (RTTR == 0) { | |
334 | RTTR = RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16); | |
2260a25c | 335 | dev_warn(&pdev->dev, "warning: initializing default clock divider/trim value\n"); |
e842f1c8 RP |
336 | /* The current RTC value probably doesn't make sense either */ |
337 | RCNR = 0; | |
338 | } | |
339 | ||
340 | rtc = rtc_device_register(pdev->name, &pdev->dev, &sa1100_rtc_ops, | |
341 | THIS_MODULE); | |
342 | ||
2260a25c | 343 | if (IS_ERR(rtc)) |
e842f1c8 | 344 | return PTR_ERR(rtc); |
e842f1c8 RP |
345 | |
346 | platform_set_drvdata(pdev, rtc); | |
347 | ||
e842f1c8 RP |
348 | return 0; |
349 | } | |
350 | ||
351 | static int sa1100_rtc_remove(struct platform_device *pdev) | |
352 | { | |
353 | struct rtc_device *rtc = platform_get_drvdata(pdev); | |
354 | ||
355 | if (rtc) | |
356 | rtc_device_unregister(rtc); | |
357 | ||
358 | return 0; | |
359 | } | |
360 | ||
361 | static struct platform_driver sa1100_rtc_driver = { | |
362 | .probe = sa1100_rtc_probe, | |
363 | .remove = sa1100_rtc_remove, | |
364 | .driver = { | |
365 | .name = "sa1100-rtc", | |
366 | }, | |
367 | }; | |
368 | ||
369 | static int __init sa1100_rtc_init(void) | |
370 | { | |
371 | return platform_driver_register(&sa1100_rtc_driver); | |
372 | } | |
373 | ||
374 | static void __exit sa1100_rtc_exit(void) | |
375 | { | |
376 | platform_driver_unregister(&sa1100_rtc_driver); | |
377 | } | |
378 | ||
379 | module_init(sa1100_rtc_init); | |
380 | module_exit(sa1100_rtc_exit); | |
381 | ||
382 | MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>"); | |
383 | MODULE_DESCRIPTION("SA11x0/PXA2xx Realtime Clock Driver (RTC)"); | |
384 | MODULE_LICENSE("GPL"); |