Commit | Line | Data |
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e842f1c8 RP |
1 | /* |
2 | * Real Time Clock interface for StrongARM SA1x00 and XScale PXA2xx | |
3 | * | |
4 | * Copyright (c) 2000 Nils Faerber | |
5 | * | |
6 | * Based on rtc.c by Paul Gortmaker | |
7 | * | |
8 | * Original Driver by Nils Faerber <nils@kernelconcepts.de> | |
9 | * | |
10 | * Modifications from: | |
11 | * CIH <cih@coventive.com> | |
2f82af08 | 12 | * Nicolas Pitre <nico@fluxnic.net> |
e842f1c8 RP |
13 | * Andrew Christian <andrew.christian@hp.com> |
14 | * | |
15 | * Converted to the RTC subsystem and Driver Model | |
16 | * by Richard Purdie <rpurdie@rpsys.net> | |
17 | * | |
18 | * This program is free software; you can redistribute it and/or | |
19 | * modify it under the terms of the GNU General Public License | |
20 | * as published by the Free Software Foundation; either version | |
21 | * 2 of the License, or (at your option) any later version. | |
22 | */ | |
23 | ||
24 | #include <linux/platform_device.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/rtc.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/fs.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/string.h> | |
31 | #include <linux/pm.h> | |
1977f032 | 32 | #include <linux/bitops.h> |
e842f1c8 | 33 | |
a09e64fb | 34 | #include <mach/hardware.h> |
e842f1c8 | 35 | #include <asm/irq.h> |
e842f1c8 RP |
36 | |
37 | #ifdef CONFIG_ARCH_PXA | |
5bf3df3f | 38 | #include <mach/regs-rtc.h> |
e842f1c8 RP |
39 | #endif |
40 | ||
a404ad1f | 41 | #define RTC_DEF_DIVIDER (32768 - 1) |
e842f1c8 RP |
42 | #define RTC_DEF_TRIM 0 |
43 | ||
d2ccb52d | 44 | static const unsigned long RTC_FREQ = 1024; |
e842f1c8 | 45 | static struct rtc_time rtc_alarm; |
34af946a | 46 | static DEFINE_SPINLOCK(sa1100_rtc_lock); |
e842f1c8 | 47 | |
797276ec RK |
48 | /* |
49 | * Calculate the next alarm time given the requested alarm time mask | |
50 | * and the current time. | |
51 | */ | |
a404ad1f MRJ |
52 | static void rtc_next_alarm_time(struct rtc_time *next, struct rtc_time *now, |
53 | struct rtc_time *alrm) | |
797276ec RK |
54 | { |
55 | unsigned long next_time; | |
56 | unsigned long now_time; | |
57 | ||
58 | next->tm_year = now->tm_year; | |
59 | next->tm_mon = now->tm_mon; | |
60 | next->tm_mday = now->tm_mday; | |
61 | next->tm_hour = alrm->tm_hour; | |
62 | next->tm_min = alrm->tm_min; | |
63 | next->tm_sec = alrm->tm_sec; | |
64 | ||
65 | rtc_tm_to_time(now, &now_time); | |
66 | rtc_tm_to_time(next, &next_time); | |
67 | ||
68 | if (next_time < now_time) { | |
69 | /* Advance one day */ | |
70 | next_time += 60 * 60 * 24; | |
71 | rtc_time_to_tm(next_time, next); | |
72 | } | |
73 | } | |
74 | ||
7d12e780 | 75 | static irqreturn_t sa1100_rtc_interrupt(int irq, void *dev_id) |
e842f1c8 RP |
76 | { |
77 | struct platform_device *pdev = to_platform_device(dev_id); | |
78 | struct rtc_device *rtc = platform_get_drvdata(pdev); | |
79 | unsigned int rtsr; | |
80 | unsigned long events = 0; | |
81 | ||
82 | spin_lock(&sa1100_rtc_lock); | |
83 | ||
84 | rtsr = RTSR; | |
85 | /* clear interrupt sources */ | |
86 | RTSR = 0; | |
7decaa55 MRJ |
87 | /* Fix for a nasty initialization problem the in SA11xx RTSR register. |
88 | * See also the comments in sa1100_rtc_probe(). */ | |
89 | if (rtsr & (RTSR_ALE | RTSR_HZE)) { | |
90 | /* This is the original code, before there was the if test | |
91 | * above. This code does not clear interrupts that were not | |
92 | * enabled. */ | |
93 | RTSR = (RTSR_AL | RTSR_HZ) & (rtsr >> 2); | |
94 | } else { | |
95 | /* For some reason, it is possible to enter this routine | |
96 | * without interruptions enabled, it has been tested with | |
97 | * several units (Bug in SA11xx chip?). | |
98 | * | |
99 | * This situation leads to an infinite "loop" of interrupt | |
100 | * routine calling and as a result the processor seems to | |
101 | * lock on its first call to open(). */ | |
102 | RTSR = RTSR_AL | RTSR_HZ; | |
103 | } | |
e842f1c8 RP |
104 | |
105 | /* clear alarm interrupt if it has occurred */ | |
106 | if (rtsr & RTSR_AL) | |
107 | rtsr &= ~RTSR_ALE; | |
108 | RTSR = rtsr & (RTSR_ALE | RTSR_HZE); | |
109 | ||
110 | /* update irq data & counter */ | |
111 | if (rtsr & RTSR_AL) | |
112 | events |= RTC_AF | RTC_IRQF; | |
113 | if (rtsr & RTSR_HZ) | |
114 | events |= RTC_UF | RTC_IRQF; | |
115 | ||
ab6a2d70 | 116 | rtc_update_irq(rtc, 1, events); |
e842f1c8 | 117 | |
e842f1c8 RP |
118 | spin_unlock(&sa1100_rtc_lock); |
119 | ||
120 | return IRQ_HANDLED; | |
121 | } | |
122 | ||
e842f1c8 RP |
123 | static int sa1100_rtc_open(struct device *dev) |
124 | { | |
125 | int ret; | |
416f0e80 MRJ |
126 | struct platform_device *plat_dev = to_platform_device(dev); |
127 | struct rtc_device *rtc = platform_get_drvdata(plat_dev); | |
e842f1c8 | 128 | |
dace1453 | 129 | ret = request_irq(IRQ_RTC1Hz, sa1100_rtc_interrupt, IRQF_DISABLED, |
a404ad1f | 130 | "rtc 1Hz", dev); |
e842f1c8 | 131 | if (ret) { |
2260a25c | 132 | dev_err(dev, "IRQ %d already in use.\n", IRQ_RTC1Hz); |
e842f1c8 RP |
133 | goto fail_ui; |
134 | } | |
dace1453 | 135 | ret = request_irq(IRQ_RTCAlrm, sa1100_rtc_interrupt, IRQF_DISABLED, |
a404ad1f | 136 | "rtc Alrm", dev); |
e842f1c8 | 137 | if (ret) { |
2260a25c | 138 | dev_err(dev, "IRQ %d already in use.\n", IRQ_RTCAlrm); |
e842f1c8 RP |
139 | goto fail_ai; |
140 | } | |
d2ccb52d | 141 | rtc->max_user_freq = RTC_FREQ; |
416f0e80 | 142 | rtc_irq_set_freq(rtc, NULL, RTC_FREQ); |
d2ccb52d | 143 | |
e842f1c8 RP |
144 | return 0; |
145 | ||
e842f1c8 | 146 | fail_ai: |
f1226701 | 147 | free_irq(IRQ_RTC1Hz, dev); |
e842f1c8 RP |
148 | fail_ui: |
149 | return ret; | |
150 | } | |
151 | ||
152 | static void sa1100_rtc_release(struct device *dev) | |
153 | { | |
154 | spin_lock_irq(&sa1100_rtc_lock); | |
155 | RTSR = 0; | |
e842f1c8 RP |
156 | spin_unlock_irq(&sa1100_rtc_lock); |
157 | ||
e842f1c8 RP |
158 | free_irq(IRQ_RTCAlrm, dev); |
159 | free_irq(IRQ_RTC1Hz, dev); | |
160 | } | |
161 | ||
16380c15 JS |
162 | static int sa1100_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
163 | { | |
164 | spin_lock_irq(&sa1100_rtc_lock); | |
165 | if (enabled) | |
166 | RTSR |= RTSR_ALE; | |
167 | else | |
168 | RTSR &= ~RTSR_ALE; | |
169 | spin_unlock_irq(&sa1100_rtc_lock); | |
170 | return 0; | |
171 | } | |
172 | ||
e842f1c8 RP |
173 | static int sa1100_rtc_read_time(struct device *dev, struct rtc_time *tm) |
174 | { | |
175 | rtc_time_to_tm(RCNR, tm); | |
176 | return 0; | |
177 | } | |
178 | ||
179 | static int sa1100_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
180 | { | |
181 | unsigned long time; | |
182 | int ret; | |
183 | ||
184 | ret = rtc_tm_to_time(tm, &time); | |
185 | if (ret == 0) | |
186 | RCNR = time; | |
187 | return ret; | |
188 | } | |
189 | ||
190 | static int sa1100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
191 | { | |
32b49da4 DB |
192 | u32 rtsr; |
193 | ||
e842f1c8 | 194 | memcpy(&alrm->time, &rtc_alarm, sizeof(struct rtc_time)); |
32b49da4 DB |
195 | rtsr = RTSR; |
196 | alrm->enabled = (rtsr & RTSR_ALE) ? 1 : 0; | |
197 | alrm->pending = (rtsr & RTSR_AL) ? 1 : 0; | |
e842f1c8 RP |
198 | return 0; |
199 | } | |
200 | ||
201 | static int sa1100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
202 | { | |
42874759 | 203 | struct rtc_time now_tm, alarm_tm; |
e842f1c8 RP |
204 | int ret; |
205 | ||
206 | spin_lock_irq(&sa1100_rtc_lock); | |
42874759 JZ |
207 | |
208 | now = RCNR; | |
209 | rtc_time_to_tm(now, &now_tm); | |
210 | rtc_next_alarm_time(&alarm_tm, &now_tm, alrm->time); | |
211 | rtc_tm_to_time(&alarm_tm, &time); | |
212 | RTAR = time; | |
213 | if (alrm->enabled) | |
214 | RTSR |= RTSR_ALE; | |
215 | else | |
216 | RTSR &= ~RTSR_ALE; | |
217 | ||
e842f1c8 RP |
218 | spin_unlock_irq(&sa1100_rtc_lock); |
219 | ||
220 | return ret; | |
221 | } | |
222 | ||
223 | static int sa1100_rtc_proc(struct device *dev, struct seq_file *seq) | |
224 | { | |
4cebe7aa MRJ |
225 | seq_printf(seq, "trim/divider\t\t: 0x%08x\n", (u32) RTTR); |
226 | seq_printf(seq, "RTSR\t\t\t: 0x%08x\n", (u32)RTSR); | |
e842f1c8 RP |
227 | |
228 | return 0; | |
229 | } | |
230 | ||
ff8371ac | 231 | static const struct rtc_class_ops sa1100_rtc_ops = { |
e842f1c8 | 232 | .open = sa1100_rtc_open, |
e842f1c8 | 233 | .release = sa1100_rtc_release, |
e842f1c8 RP |
234 | .read_time = sa1100_rtc_read_time, |
235 | .set_time = sa1100_rtc_set_time, | |
236 | .read_alarm = sa1100_rtc_read_alarm, | |
237 | .set_alarm = sa1100_rtc_set_alarm, | |
238 | .proc = sa1100_rtc_proc, | |
16380c15 | 239 | .alarm_irq_enable = sa1100_rtc_alarm_irq_enable, |
e842f1c8 RP |
240 | }; |
241 | ||
242 | static int sa1100_rtc_probe(struct platform_device *pdev) | |
243 | { | |
244 | struct rtc_device *rtc; | |
245 | ||
246 | /* | |
247 | * According to the manual we should be able to let RTTR be zero | |
248 | * and then a default diviser for a 32.768KHz clock is used. | |
249 | * Apparently this doesn't work, at least for my SA1110 rev 5. | |
250 | * If the clock divider is uninitialized then reset it to the | |
251 | * default value to get the 1Hz clock. | |
252 | */ | |
253 | if (RTTR == 0) { | |
254 | RTTR = RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16); | |
a404ad1f MRJ |
255 | dev_warn(&pdev->dev, "warning: " |
256 | "initializing default clock divider/trim value\n"); | |
e842f1c8 RP |
257 | /* The current RTC value probably doesn't make sense either */ |
258 | RCNR = 0; | |
259 | } | |
260 | ||
e5a2c9cc UL |
261 | device_init_wakeup(&pdev->dev, 1); |
262 | ||
e842f1c8 | 263 | rtc = rtc_device_register(pdev->name, &pdev->dev, &sa1100_rtc_ops, |
d2ccb52d | 264 | THIS_MODULE); |
e842f1c8 | 265 | |
2260a25c | 266 | if (IS_ERR(rtc)) |
e842f1c8 | 267 | return PTR_ERR(rtc); |
e842f1c8 RP |
268 | |
269 | platform_set_drvdata(pdev, rtc); | |
270 | ||
7decaa55 MRJ |
271 | /* Fix for a nasty initialization problem the in SA11xx RTSR register. |
272 | * See also the comments in sa1100_rtc_interrupt(). | |
273 | * | |
274 | * Sometimes bit 1 of the RTSR (RTSR_HZ) will wake up 1, which means an | |
275 | * interrupt pending, even though interrupts were never enabled. | |
276 | * In this case, this bit it must be reset before enabling | |
277 | * interruptions to avoid a nonexistent interrupt to occur. | |
278 | * | |
279 | * In principle, the same problem would apply to bit 0, although it has | |
280 | * never been observed to happen. | |
281 | * | |
282 | * This issue is addressed both here and in sa1100_rtc_interrupt(). | |
283 | * If the issue is not addressed here, in the times when the processor | |
284 | * wakes up with the bit set there will be one spurious interrupt. | |
285 | * | |
286 | * The issue is also dealt with in sa1100_rtc_interrupt() to be on the | |
287 | * safe side, once the condition that lead to this strange | |
288 | * initialization is unknown and could in principle happen during | |
289 | * normal processing. | |
290 | * | |
291 | * Notice that clearing bit 1 and 0 is accomplished by writting ONES to | |
292 | * the corresponding bits in RTSR. */ | |
293 | RTSR = RTSR_AL | RTSR_HZ; | |
294 | ||
e842f1c8 RP |
295 | return 0; |
296 | } | |
297 | ||
298 | static int sa1100_rtc_remove(struct platform_device *pdev) | |
299 | { | |
300 | struct rtc_device *rtc = platform_get_drvdata(pdev); | |
301 | ||
a404ad1f | 302 | if (rtc) |
e842f1c8 RP |
303 | rtc_device_unregister(rtc); |
304 | ||
305 | return 0; | |
306 | } | |
307 | ||
6bc54e69 | 308 | #ifdef CONFIG_PM |
5d027cd2 | 309 | static int sa1100_rtc_suspend(struct device *dev) |
6bc54e69 | 310 | { |
5d027cd2 | 311 | if (device_may_wakeup(dev)) |
f618258a | 312 | enable_irq_wake(IRQ_RTCAlrm); |
6bc54e69 RK |
313 | return 0; |
314 | } | |
315 | ||
5d027cd2 | 316 | static int sa1100_rtc_resume(struct device *dev) |
6bc54e69 | 317 | { |
5d027cd2 | 318 | if (device_may_wakeup(dev)) |
f618258a | 319 | disable_irq_wake(IRQ_RTCAlrm); |
6bc54e69 RK |
320 | return 0; |
321 | } | |
5d027cd2 | 322 | |
47145210 | 323 | static const struct dev_pm_ops sa1100_rtc_pm_ops = { |
5d027cd2 HZ |
324 | .suspend = sa1100_rtc_suspend, |
325 | .resume = sa1100_rtc_resume, | |
326 | }; | |
6bc54e69 RK |
327 | #endif |
328 | ||
e842f1c8 RP |
329 | static struct platform_driver sa1100_rtc_driver = { |
330 | .probe = sa1100_rtc_probe, | |
331 | .remove = sa1100_rtc_remove, | |
332 | .driver = { | |
5d027cd2 HZ |
333 | .name = "sa1100-rtc", |
334 | #ifdef CONFIG_PM | |
335 | .pm = &sa1100_rtc_pm_ops, | |
336 | #endif | |
e842f1c8 RP |
337 | }, |
338 | }; | |
339 | ||
340 | static int __init sa1100_rtc_init(void) | |
341 | { | |
342 | return platform_driver_register(&sa1100_rtc_driver); | |
343 | } | |
344 | ||
345 | static void __exit sa1100_rtc_exit(void) | |
346 | { | |
347 | platform_driver_unregister(&sa1100_rtc_driver); | |
348 | } | |
349 | ||
350 | module_init(sa1100_rtc_init); | |
351 | module_exit(sa1100_rtc_exit); | |
352 | ||
353 | MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>"); | |
354 | MODULE_DESCRIPTION("SA11x0/PXA2xx Realtime Clock Driver (RTC)"); | |
355 | MODULE_LICENSE("GPL"); | |
ad28a07b | 356 | MODULE_ALIAS("platform:sa1100-rtc"); |