[deliverable/linux.git] / drivers / rtc / rtc-sa1100.c

/*
 * Real Time Clock interface for StrongARM SA1x00 and XScale PXA2xx
 *
 * Copyright (c) 2000 Nils Faerber
 *
 * Based on rtc.c by Paul Gortmaker
 *
 * Original Driver by Nils Faerber <nils@kernelconcepts.de>
 *
 * Modifications from:
 *   CIH <cih@coventive.com>
 *   Nicolas Pitre <nico@fluxnic.net>
 *   Andrew Christian <andrew.christian@hp.com>
 *
 * Converted to the RTC subsystem and Driver Model
 *   by Richard Purdie <rpurdie@rpsys.net>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/rtc.h>
#include <linux/init.h>
#include <linux/fs.h>
#include <linux/interrupt.h>
#include <linux/string.h>
#include <linux/pm.h>
#include <linux/bitops.h>

#include <mach/hardware.h>
#include <asm/irq.h>

#ifdef CONFIG_ARCH_PXA
#include <mach/regs-rtc.h>
#include <mach/regs-ost.h>
#endif

#define RTC_DEF_DIVIDER		(32768 - 1)
#define RTC_DEF_TRIM		0

static unsigned long rtc_freq = 1024;
static unsigned long timer_freq;
static struct rtc_time rtc_alarm;
static DEFINE_SPINLOCK(sa1100_rtc_lock);

static inline int rtc_periodic_alarm(struct rtc_time *tm)
{
	return  (tm->tm_year == -1) ||
		((unsigned)tm->tm_mon >= 12) ||
		((unsigned)(tm->tm_mday - 1) >= 31) ||
		((unsigned)tm->tm_hour > 23) ||
		((unsigned)tm->tm_min > 59) ||
		((unsigned)tm->tm_sec > 59);
}

/*
 * Calculate the next alarm time given the requested alarm time mask
 * and the current time.
 */
static void rtc_next_alarm_time(struct rtc_time *next, struct rtc_time *now,
	struct rtc_time *alrm)
{
	unsigned long next_time;
	unsigned long now_time;

	next->tm_year = now->tm_year;
	next->tm_mon = now->tm_mon;
	next->tm_mday = now->tm_mday;
	next->tm_hour = alrm->tm_hour;
	next->tm_min = alrm->tm_min;
	next->tm_sec = alrm->tm_sec;

	rtc_tm_to_time(now, &now_time);
	rtc_tm_to_time(next, &next_time);

	if (next_time < now_time) {
		/* Advance one day */
		next_time += 60 * 60 * 24;
		rtc_time_to_tm(next_time, next);
	}
}

static int rtc_update_alarm(struct rtc_time *alrm)
{
	struct rtc_time alarm_tm, now_tm;
	unsigned long now, time;
	int ret;

	do {
		now = RCNR;
		rtc_time_to_tm(now, &now_tm);
		rtc_next_alarm_time(&alarm_tm, &now_tm, alrm);
		ret = rtc_tm_to_time(&alarm_tm, &time);
		if (ret != 0)
			break;

		RTSR = RTSR & (RTSR_HZE|RTSR_ALE|RTSR_AL);
		RTAR = time;
	} while (now != RCNR);

	return ret;
}

static irqreturn_t sa1100_rtc_interrupt(int irq, void *dev_id)
{
	struct platform_device *pdev = to_platform_device(dev_id);
	struct rtc_device *rtc = platform_get_drvdata(pdev);
	unsigned int rtsr;
	unsigned long events = 0;

	spin_lock(&sa1100_rtc_lock);

	rtsr = RTSR;
	/* clear interrupt sources */
	RTSR = 0;
	/* Fix for a nasty initialization problem the in SA11xx RTSR register.
	 * See also the comments in sa1100_rtc_probe(). */
	if (rtsr & (RTSR_ALE | RTSR_HZE)) {
		/* This is the original code, before there was the if test
		 * above. This code does not clear interrupts that were not
		 * enabled. */
		RTSR = (RTSR_AL | RTSR_HZ) & (rtsr >> 2);
	} else {
		/* For some reason, it is possible to enter this routine
		 * without interruptions enabled, it has been tested with
		 * several units (Bug in SA11xx chip?).
		 *
		 * This situation leads to an infinite "loop" of interrupt
		 * routine calling and as a result the processor seems to
		 * lock on its first call to open(). */
		RTSR = RTSR_AL | RTSR_HZ;
	}

	/* clear alarm interrupt if it has occurred */
	if (rtsr & RTSR_AL)
		rtsr &= ~RTSR_ALE;
	RTSR = rtsr & (RTSR_ALE | RTSR_HZE);

	/* update irq data & counter */
	if (rtsr & RTSR_AL)
		events |= RTC_AF | RTC_IRQF;
	if (rtsr & RTSR_HZ)
		events |= RTC_UF | RTC_IRQF;

	rtc_update_irq(rtc, 1, events);

	if (rtsr & RTSR_AL && rtc_periodic_alarm(&rtc_alarm))
		rtc_update_alarm(&rtc_alarm);

	spin_unlock(&sa1100_rtc_lock);

	return IRQ_HANDLED;
}

static int rtc_timer1_count;

static irqreturn_t timer1_interrupt(int irq, void *dev_id)
{
	struct platform_device *pdev = to_platform_device(dev_id);
	struct rtc_device *rtc = platform_get_drvdata(pdev);

	/*
	 * If we match for the first time, rtc_timer1_count will be 1.
	 * Otherwise, we wrapped around (very unlikely but
	 * still possible) so compute the amount of missed periods.
	 * The match reg is updated only when the data is actually retrieved
	 * to avoid unnecessary interrupts.
	 */
	OSSR = OSSR_M1;	/* clear match on timer1 */

	rtc_update_irq(rtc, rtc_timer1_count, RTC_PF | RTC_IRQF);

	if (rtc_timer1_count == 1)
		rtc_timer1_count = (rtc_freq * ((1 << 30) / (timer_freq >> 2)));

	return IRQ_HANDLED;
}

static int sa1100_rtc_read_callback(struct device *dev, int data)
{
	if (data & RTC_PF) {
		/* interpolate missed periods and set match for the next */
		unsigned long period = timer_freq / rtc_freq;
		unsigned long oscr = OSCR;
		unsigned long osmr1 = OSMR1;
		unsigned long missed = (oscr - osmr1)/period;
		data += missed << 8;
		OSSR = OSSR_M1;	/* clear match on timer 1 */
		OSMR1 = osmr1 + (missed + 1)*period;
		/* Ensure we didn't miss another match in the mean time.
		 * Here we compare (match - OSCR) 8 instead of 0 --
		 * see comment in pxa_timer_interrupt() for explanation.
		 */
		while ((signed long)((osmr1 = OSMR1) - OSCR) <= 8) {
			data += 0x100;
			OSSR = OSSR_M1;	/* clear match on timer 1 */
			OSMR1 = osmr1 + period;
		}
	}
	return data;
}

static int sa1100_rtc_open(struct device *dev)
{
	int ret;

	ret = request_irq(IRQ_RTC1Hz, sa1100_rtc_interrupt, IRQF_DISABLED,
		"rtc 1Hz", dev);
	if (ret) {
		dev_err(dev, "IRQ %d already in use.\n", IRQ_RTC1Hz);
		goto fail_ui;
	}
	ret = request_irq(IRQ_RTCAlrm, sa1100_rtc_interrupt, IRQF_DISABLED,
		"rtc Alrm", dev);
	if (ret) {
		dev_err(dev, "IRQ %d already in use.\n", IRQ_RTCAlrm);
		goto fail_ai;
	}
	ret = request_irq(IRQ_OST1, timer1_interrupt, IRQF_DISABLED,
		"rtc timer", dev);
	if (ret) {
		dev_err(dev, "IRQ %d already in use.\n", IRQ_OST1);
		goto fail_pi;
	}
	return 0;

 fail_pi:
	free_irq(IRQ_RTCAlrm, dev);
 fail_ai:
	free_irq(IRQ_RTC1Hz, dev);
 fail_ui:
	return ret;
}

static void sa1100_rtc_release(struct device *dev)
{
	spin_lock_irq(&sa1100_rtc_lock);
	RTSR = 0;
	OIER &= ~OIER_E1;
	OSSR = OSSR_M1;
	spin_unlock_irq(&sa1100_rtc_lock);

	free_irq(IRQ_OST1, dev);
	free_irq(IRQ_RTCAlrm, dev);
	free_irq(IRQ_RTC1Hz, dev);
}


static int sa1100_rtc_ioctl(struct device *dev, unsigned int cmd,
		unsigned long arg)
{
	switch (cmd) {
	case RTC_AIE_OFF:
		spin_lock_irq(&sa1100_rtc_lock);
		RTSR &= ~RTSR_ALE;
		spin_unlock_irq(&sa1100_rtc_lock);
		return 0;
	case RTC_AIE_ON:
		spin_lock_irq(&sa1100_rtc_lock);
		RTSR |= RTSR_ALE;
		spin_unlock_irq(&sa1100_rtc_lock);
		return 0;
	case RTC_UIE_OFF:
		spin_lock_irq(&sa1100_rtc_lock);
		RTSR &= ~RTSR_HZE;
		spin_unlock_irq(&sa1100_rtc_lock);
		return 0;
	case RTC_UIE_ON:
		spin_lock_irq(&sa1100_rtc_lock);
		RTSR |= RTSR_HZE;
		spin_unlock_irq(&sa1100_rtc_lock);
		return 0;
	case RTC_PIE_OFF:
		spin_lock_irq(&sa1100_rtc_lock);
		OIER &= ~OIER_E1;
		spin_unlock_irq(&sa1100_rtc_lock);
		return 0;
	case RTC_PIE_ON:
		spin_lock_irq(&sa1100_rtc_lock);
		OSMR1 = timer_freq / rtc_freq + OSCR;
		OIER |= OIER_E1;
		rtc_timer1_count = 1;
		spin_unlock_irq(&sa1100_rtc_lock);
		return 0;
	case RTC_IRQP_READ:
		return put_user(rtc_freq, (unsigned long *)arg);
	case RTC_IRQP_SET:
		if (arg < 1 || arg > timer_freq)
			return -EINVAL;
		rtc_freq = arg;
		return 0;
	}
	return -ENOIOCTLCMD;
}

static int sa1100_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	rtc_time_to_tm(RCNR, tm);
	return 0;
}

static int sa1100_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	unsigned long time;
	int ret;

	ret = rtc_tm_to_time(tm, &time);
	if (ret == 0)
		RCNR = time;
	return ret;
}

static int sa1100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	u32	rtsr;

	memcpy(&alrm->time, &rtc_alarm, sizeof(struct rtc_time));
	rtsr = RTSR;
	alrm->enabled = (rtsr & RTSR_ALE) ? 1 : 0;
	alrm->pending = (rtsr & RTSR_AL) ? 1 : 0;
	return 0;
}

static int sa1100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	int ret;

	spin_lock_irq(&sa1100_rtc_lock);
	ret = rtc_update_alarm(&alrm->time);
	if (ret == 0) {
		if (alrm->enabled)
			RTSR |= RTSR_ALE;
		else
			RTSR &= ~RTSR_ALE;
	}
	spin_unlock_irq(&sa1100_rtc_lock);

	return ret;
}

static int sa1100_rtc_proc(struct device *dev, struct seq_file *seq)
{
	seq_printf(seq, "trim/divider\t: 0x%08x\n", (u32) RTTR);
	seq_printf(seq, "update_IRQ\t: %s\n",
			(RTSR & RTSR_HZE) ? "yes" : "no");
	seq_printf(seq, "periodic_IRQ\t: %s\n",
			(OIER & OIER_E1) ? "yes" : "no");
	seq_printf(seq, "periodic_freq\t: %ld\n", rtc_freq);
	seq_printf(seq, "RTSR\t\t: 0x%08x\n", (u32)RTSR);

	return 0;
}

static const struct rtc_class_ops sa1100_rtc_ops = {
	.open = sa1100_rtc_open,
	.read_callback = sa1100_rtc_read_callback,
	.release = sa1100_rtc_release,
	.ioctl = sa1100_rtc_ioctl,
	.read_time = sa1100_rtc_read_time,
	.set_time = sa1100_rtc_set_time,
	.read_alarm = sa1100_rtc_read_alarm,
	.set_alarm = sa1100_rtc_set_alarm,
	.proc = sa1100_rtc_proc,
};

static int sa1100_rtc_probe(struct platform_device *pdev)
{
	struct rtc_device *rtc;

	timer_freq = get_clock_tick_rate();

	/*
	 * According to the manual we should be able to let RTTR be zero
	 * and then a default diviser for a 32.768KHz clock is used.
	 * Apparently this doesn't work, at least for my SA1110 rev 5.
	 * If the clock divider is uninitialized then reset it to the
	 * default value to get the 1Hz clock.
	 */
	if (RTTR == 0) {
		RTTR = RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16);
		dev_warn(&pdev->dev, "warning: "
			"initializing default clock divider/trim value\n");
		/* The current RTC value probably doesn't make sense either */
		RCNR = 0;
	}

	device_init_wakeup(&pdev->dev, 1);

	rtc = rtc_device_register(pdev->name, &pdev->dev, &sa1100_rtc_ops,
				THIS_MODULE);

	if (IS_ERR(rtc))
		return PTR_ERR(rtc);

	platform_set_drvdata(pdev, rtc);

	/* Fix for a nasty initialization problem the in SA11xx RTSR register.
	 * See also the comments in sa1100_rtc_interrupt().
	 *
	 * Sometimes bit 1 of the RTSR (RTSR_HZ) will wake up 1, which means an
	 * interrupt pending, even though interrupts were never enabled.
	 * In this case, this bit it must be reset before enabling
	 * interruptions to avoid a nonexistent interrupt to occur.
	 *
	 * In principle, the same problem would apply to bit 0, although it has
	 * never been observed to happen.
	 *
	 * This issue is addressed both here and in sa1100_rtc_interrupt().
	 * If the issue is not addressed here, in the times when the processor
	 * wakes up with the bit set there will be one spurious interrupt.
	 *
	 * The issue is also dealt with in sa1100_rtc_interrupt() to be on the
	 * safe side, once the condition that lead to this strange
	 * initialization is unknown and could in principle happen during
	 * normal processing.
	 *
	 * Notice that clearing bit 1 and 0 is accomplished by writting ONES to
	 * the corresponding bits in RTSR. */
	RTSR = RTSR_AL | RTSR_HZ;

	return 0;
}

static int sa1100_rtc_remove(struct platform_device *pdev)
{
	struct rtc_device *rtc = platform_get_drvdata(pdev);

	if (rtc)
		rtc_device_unregister(rtc);

	return 0;
}

#ifdef CONFIG_PM
static int sa1100_rtc_suspend(struct device *dev)
{
	if (device_may_wakeup(dev))
		enable_irq_wake(IRQ_RTCAlrm);
	return 0;
}

static int sa1100_rtc_resume(struct device *dev)
{
	if (device_may_wakeup(dev))
		disable_irq_wake(IRQ_RTCAlrm);
	return 0;
}

static const struct dev_pm_ops sa1100_rtc_pm_ops = {
	.suspend	= sa1100_rtc_suspend,
	.resume		= sa1100_rtc_resume,
};
#endif

static struct platform_driver sa1100_rtc_driver = {
	.probe		= sa1100_rtc_probe,
	.remove		= sa1100_rtc_remove,
	.driver		= {
		.name	= "sa1100-rtc",
#ifdef CONFIG_PM
		.pm	= &sa1100_rtc_pm_ops,
#endif
	},
};

static int __init sa1100_rtc_init(void)
{
	return platform_driver_register(&sa1100_rtc_driver);
}

static void __exit sa1100_rtc_exit(void)
{
	platform_driver_unregister(&sa1100_rtc_driver);
}

module_init(sa1100_rtc_init);
module_exit(sa1100_rtc_exit);

MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>");
MODULE_DESCRIPTION("SA11x0/PXA2xx Realtime Clock Driver (RTC)");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:sa1100-rtc");
Commit	Line	Data
e842f1c8 RP	1	/*
	2	* Real Time Clock interface for StrongARM SA1x00 and XScale PXA2xx
	3	*
	4	* Copyright (c) 2000 Nils Faerber
	5	*
	6	* Based on rtc.c by Paul Gortmaker
	7	*
	8	* Original Driver by Nils Faerber <nils@kernelconcepts.de>
	9	*
	10	* Modifications from:
	11	* CIH <cih@coventive.com>
2f82af08	12	* Nicolas Pitre <nico@fluxnic.net>
e842f1c8 RP	13	* Andrew Christian <andrew.christian@hp.com>
	14	*
	15	* Converted to the RTC subsystem and Driver Model
	16	* by Richard Purdie <rpurdie@rpsys.net>
	17	*
	18	* This program is free software; you can redistribute it and/or
	19	* modify it under the terms of the GNU General Public License
	20	* as published by the Free Software Foundation; either version
	21	* 2 of the License, or (at your option) any later version.
	22	*/
	23
	24	#include <linux/platform_device.h>
	25	#include <linux/module.h>
	26	#include <linux/rtc.h>
	27	#include <linux/init.h>
	28	#include <linux/fs.h>
	29	#include <linux/interrupt.h>
	30	#include <linux/string.h>
	31	#include <linux/pm.h>
1977f032	32	#include <linux/bitops.h>
e842f1c8	33
a09e64fb	34	#include <mach/hardware.h>
e842f1c8	35	#include <asm/irq.h>
e842f1c8 RP	36
e842f1c8 RP	37	#ifdef CONFIG_ARCH_PXA
5bf3df3f EM	38	#include <mach/regs-rtc.h>
5bf3df3f EM	39	#include <mach/regs-ost.h>
e842f1c8 RP	40	#endif
e842f1c8 RP	41
a404ad1f	42	#define RTC_DEF_DIVIDER (32768 - 1)
e842f1c8 RP	43	#define RTC_DEF_TRIM 0
	44
	45	static unsigned long rtc_freq = 1024;
6769717d	46	static unsigned long timer_freq;
e842f1c8	47	static struct rtc_time rtc_alarm;
34af946a	48	static DEFINE_SPINLOCK(sa1100_rtc_lock);
e842f1c8	49
797276ec RK	50	static inline int rtc_periodic_alarm(struct rtc_time *tm)
	51	{
	52	return (tm->tm_year == -1) \|\|
	53	((unsigned)tm->tm_mon >= 12) \|\|
	54	((unsigned)(tm->tm_mday - 1) >= 31) \|\|
	55	((unsigned)tm->tm_hour > 23) \|\|
	56	((unsigned)tm->tm_min > 59) \|\|
	57	((unsigned)tm->tm_sec > 59);
	58	}
	59
	60	/*
	61	* Calculate the next alarm time given the requested alarm time mask
	62	* and the current time.
	63	*/
a404ad1f MRJ	64	static void rtc_next_alarm_time(struct rtc_time next, struct rtc_time now,
a404ad1f MRJ	65	struct rtc_time *alrm)
797276ec RK	66	{
	67	unsigned long next_time;
	68	unsigned long now_time;
	69
	70	next->tm_year = now->tm_year;
	71	next->tm_mon = now->tm_mon;
	72	next->tm_mday = now->tm_mday;
	73	next->tm_hour = alrm->tm_hour;
	74	next->tm_min = alrm->tm_min;
	75	next->tm_sec = alrm->tm_sec;
	76
	77	rtc_tm_to_time(now, &now_time);
	78	rtc_tm_to_time(next, &next_time);
	79
	80	if (next_time < now_time) {
	81	/* Advance one day */
	82	next_time += 60 * 60 * 24;
	83	rtc_time_to_tm(next_time, next);
	84	}
	85	}
	86
e842f1c8 RP	87	static int rtc_update_alarm(struct rtc_time *alrm)
	88	{
	89	struct rtc_time alarm_tm, now_tm;
	90	unsigned long now, time;
	91	int ret;
	92
	93	do {
	94	now = RCNR;
	95	rtc_time_to_tm(now, &now_tm);
	96	rtc_next_alarm_time(&alarm_tm, &now_tm, alrm);
	97	ret = rtc_tm_to_time(&alarm_tm, &time);
	98	if (ret != 0)
	99	break;
	100
	101	RTSR = RTSR & (RTSR_HZE\|RTSR_ALE\|RTSR_AL);
	102	RTAR = time;
	103	} while (now != RCNR);
	104
	105	return ret;
	106	}
	107
7d12e780	108	static irqreturn_t sa1100_rtc_interrupt(int irq, void *dev_id)
e842f1c8 RP	109	{
	110	struct platform_device *pdev = to_platform_device(dev_id);
	111	struct rtc_device *rtc = platform_get_drvdata(pdev);
	112	unsigned int rtsr;
	113	unsigned long events = 0;
	114
	115	spin_lock(&sa1100_rtc_lock);
	116
	117	rtsr = RTSR;
	118	/* clear interrupt sources */
	119	RTSR = 0;
7decaa55 MRJ	120	/* Fix for a nasty initialization problem the in SA11xx RTSR register.
	121	* See also the comments in sa1100_rtc_probe(). */
	122	if (rtsr & (RTSR_ALE \| RTSR_HZE)) {
	123	/* This is the original code, before there was the if test
	124	* above. This code does not clear interrupts that were not
	125	* enabled. */
	126	RTSR = (RTSR_AL \| RTSR_HZ) & (rtsr >> 2);
	127	} else {
	128	/* For some reason, it is possible to enter this routine
	129	* without interruptions enabled, it has been tested with
	130	* several units (Bug in SA11xx chip?).
	131	*
	132	* This situation leads to an infinite "loop" of interrupt
	133	* routine calling and as a result the processor seems to
	134	* lock on its first call to open(). */
	135	RTSR = RTSR_AL \| RTSR_HZ;
	136	}
e842f1c8 RP	137
	138	/* clear alarm interrupt if it has occurred */
	139	if (rtsr & RTSR_AL)
	140	rtsr &= ~RTSR_ALE;
	141	RTSR = rtsr & (RTSR_ALE \| RTSR_HZE);
	142
	143	/* update irq data & counter */
	144	if (rtsr & RTSR_AL)
	145	events \|= RTC_AF \| RTC_IRQF;
	146	if (rtsr & RTSR_HZ)
	147	events \|= RTC_UF \| RTC_IRQF;
	148
ab6a2d70	149	rtc_update_irq(rtc, 1, events);
e842f1c8 RP	150
	151	if (rtsr & RTSR_AL && rtc_periodic_alarm(&rtc_alarm))
	152	rtc_update_alarm(&rtc_alarm);
	153
	154	spin_unlock(&sa1100_rtc_lock);
	155
	156	return IRQ_HANDLED;
	157	}
	158
	159	static int rtc_timer1_count;
	160
7d12e780	161	static irqreturn_t timer1_interrupt(int irq, void *dev_id)
e842f1c8 RP	162	{
	163	struct platform_device *pdev = to_platform_device(dev_id);
	164	struct rtc_device *rtc = platform_get_drvdata(pdev);
	165
	166	/*
	167	* If we match for the first time, rtc_timer1_count will be 1.
	168	* Otherwise, we wrapped around (very unlikely but
	169	* still possible) so compute the amount of missed periods.
	170	* The match reg is updated only when the data is actually retrieved
	171	* to avoid unnecessary interrupts.
	172	*/
	173	OSSR = OSSR_M1; /* clear match on timer1 */
	174
ab6a2d70	175	rtc_update_irq(rtc, rtc_timer1_count, RTC_PF \| RTC_IRQF);
e842f1c8 RP	176
e842f1c8 RP	177	if (rtc_timer1_count == 1)
6769717d	178	rtc_timer1_count = (rtc_freq * ((1 << 30) / (timer_freq >> 2)));
e842f1c8 RP	179
	180	return IRQ_HANDLED;
	181	}
	182
	183	static int sa1100_rtc_read_callback(struct device *dev, int data)
	184	{
	185	if (data & RTC_PF) {
	186	/* interpolate missed periods and set match for the next */
6769717d	187	unsigned long period = timer_freq / rtc_freq;
e842f1c8 RP	188	unsigned long oscr = OSCR;
	189	unsigned long osmr1 = OSMR1;
	190	unsigned long missed = (oscr - osmr1)/period;
	191	data += missed << 8;
	192	OSSR = OSSR_M1; /* clear match on timer 1 */
	193	OSMR1 = osmr1 + (missed + 1)*period;
	194	/* Ensure we didn't miss another match in the mean time.
	195	* Here we compare (match - OSCR) 8 instead of 0 --
	196	* see comment in pxa_timer_interrupt() for explanation.
	197	*/
a404ad1f	198	while ((signed long)((osmr1 = OSMR1) - OSCR) <= 8) {
e842f1c8 RP	199	data += 0x100;
	200	OSSR = OSSR_M1; /* clear match on timer 1 */
	201	OSMR1 = osmr1 + period;
	202	}
	203	}
	204	return data;
	205	}
	206
	207	static int sa1100_rtc_open(struct device *dev)
	208	{
	209	int ret;
	210
dace1453	211	ret = request_irq(IRQ_RTC1Hz, sa1100_rtc_interrupt, IRQF_DISABLED,
a404ad1f	212	"rtc 1Hz", dev);
e842f1c8	213	if (ret) {
2260a25c	214	dev_err(dev, "IRQ %d already in use.\n", IRQ_RTC1Hz);
e842f1c8 RP	215	goto fail_ui;
e842f1c8 RP	216	}
dace1453	217	ret = request_irq(IRQ_RTCAlrm, sa1100_rtc_interrupt, IRQF_DISABLED,
a404ad1f	218	"rtc Alrm", dev);
e842f1c8	219	if (ret) {
2260a25c	220	dev_err(dev, "IRQ %d already in use.\n", IRQ_RTCAlrm);
e842f1c8 RP	221	goto fail_ai;
e842f1c8 RP	222	}
dace1453	223	ret = request_irq(IRQ_OST1, timer1_interrupt, IRQF_DISABLED,
a404ad1f	224	"rtc timer", dev);
e842f1c8	225	if (ret) {
2260a25c	226	dev_err(dev, "IRQ %d already in use.\n", IRQ_OST1);
e842f1c8 RP	227	goto fail_pi;
	228	}
	229	return 0;
	230
	231	fail_pi:
f1226701	232	free_irq(IRQ_RTCAlrm, dev);
e842f1c8	233	fail_ai:
f1226701	234	free_irq(IRQ_RTC1Hz, dev);
e842f1c8 RP	235	fail_ui:
	236	return ret;
	237	}
	238
	239	static void sa1100_rtc_release(struct device *dev)
	240	{
	241	spin_lock_irq(&sa1100_rtc_lock);
	242	RTSR = 0;
	243	OIER &= ~OIER_E1;
	244	OSSR = OSSR_M1;
	245	spin_unlock_irq(&sa1100_rtc_lock);
	246
	247	free_irq(IRQ_OST1, dev);
	248	free_irq(IRQ_RTCAlrm, dev);
	249	free_irq(IRQ_RTC1Hz, dev);
	250	}
	251
	252
	253	static int sa1100_rtc_ioctl(struct device *dev, unsigned int cmd,
	254	unsigned long arg)
	255	{
a404ad1f	256	switch (cmd) {
e842f1c8 RP	257	case RTC_AIE_OFF:
	258	spin_lock_irq(&sa1100_rtc_lock);
	259	RTSR &= ~RTSR_ALE;
	260	spin_unlock_irq(&sa1100_rtc_lock);
	261	return 0;
	262	case RTC_AIE_ON:
	263	spin_lock_irq(&sa1100_rtc_lock);
	264	RTSR \|= RTSR_ALE;
	265	spin_unlock_irq(&sa1100_rtc_lock);
	266	return 0;
	267	case RTC_UIE_OFF:
	268	spin_lock_irq(&sa1100_rtc_lock);
	269	RTSR &= ~RTSR_HZE;
	270	spin_unlock_irq(&sa1100_rtc_lock);
	271	return 0;
	272	case RTC_UIE_ON:
	273	spin_lock_irq(&sa1100_rtc_lock);
	274	RTSR \|= RTSR_HZE;
	275	spin_unlock_irq(&sa1100_rtc_lock);
	276	return 0;
	277	case RTC_PIE_OFF:
	278	spin_lock_irq(&sa1100_rtc_lock);
	279	OIER &= ~OIER_E1;
	280	spin_unlock_irq(&sa1100_rtc_lock);
	281	return 0;
	282	case RTC_PIE_ON:
e842f1c8	283	spin_lock_irq(&sa1100_rtc_lock);
6769717d	284	OSMR1 = timer_freq / rtc_freq + OSCR;
e842f1c8 RP	285	OIER \|= OIER_E1;
	286	rtc_timer1_count = 1;
	287	spin_unlock_irq(&sa1100_rtc_lock);
	288	return 0;
	289	case RTC_IRQP_READ:
	290	return put_user(rtc_freq, (unsigned long *)arg);
	291	case RTC_IRQP_SET:
6769717d	292	if (arg < 1 \|\| arg > timer_freq)
e842f1c8	293	return -EINVAL;
e842f1c8 RP	294	rtc_freq = arg;
	295	return 0;
	296	}
b3969e58	297	return -ENOIOCTLCMD;
e842f1c8 RP	298	}
	299
	300	static int sa1100_rtc_read_time(struct device dev, struct rtc_time tm)
	301	{
	302	rtc_time_to_tm(RCNR, tm);
	303	return 0;
	304	}
	305
	306	static int sa1100_rtc_set_time(struct device dev, struct rtc_time tm)
	307	{
	308	unsigned long time;
	309	int ret;
	310
	311	ret = rtc_tm_to_time(tm, &time);
	312	if (ret == 0)
	313	RCNR = time;
	314	return ret;
	315	}
	316
	317	static int sa1100_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	318	{
32b49da4 DB	319	u32 rtsr;
32b49da4 DB	320
e842f1c8	321	memcpy(&alrm->time, &rtc_alarm, sizeof(struct rtc_time));
32b49da4 DB	322	rtsr = RTSR;
	323	alrm->enabled = (rtsr & RTSR_ALE) ? 1 : 0;
	324	alrm->pending = (rtsr & RTSR_AL) ? 1 : 0;
e842f1c8 RP	325	return 0;
	326	}
	327
	328	static int sa1100_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	329	{
	330	int ret;
	331
	332	spin_lock_irq(&sa1100_rtc_lock);
	333	ret = rtc_update_alarm(&alrm->time);
	334	if (ret == 0) {
e842f1c8	335	if (alrm->enabled)
32b49da4	336	RTSR \|= RTSR_ALE;
e842f1c8	337	else
32b49da4	338	RTSR &= ~RTSR_ALE;
e842f1c8 RP	339	}
	340	spin_unlock_irq(&sa1100_rtc_lock);
	341
	342	return ret;
	343	}
	344
	345	static int sa1100_rtc_proc(struct device dev, struct seq_file seq)
	346	{
a2db8dfc	347	seq_printf(seq, "trim/divider\t: 0x%08x\n", (u32) RTTR);
e842f1c8 RP	348	seq_printf(seq, "update_IRQ\t: %s\n",
	349	(RTSR & RTSR_HZE) ? "yes" : "no");
	350	seq_printf(seq, "periodic_IRQ\t: %s\n",
	351	(OIER & OIER_E1) ? "yes" : "no");
	352	seq_printf(seq, "periodic_freq\t: %ld\n", rtc_freq);
fd3ee6d3	353	seq_printf(seq, "RTSR\t\t: 0x%08x\n", (u32)RTSR);
e842f1c8 RP	354
	355	return 0;
	356	}
	357
ff8371ac	358	static const struct rtc_class_ops sa1100_rtc_ops = {
e842f1c8 RP	359	.open = sa1100_rtc_open,
	360	.read_callback = sa1100_rtc_read_callback,
	361	.release = sa1100_rtc_release,
	362	.ioctl = sa1100_rtc_ioctl,
	363	.read_time = sa1100_rtc_read_time,
	364	.set_time = sa1100_rtc_set_time,
	365	.read_alarm = sa1100_rtc_read_alarm,
	366	.set_alarm = sa1100_rtc_set_alarm,
	367	.proc = sa1100_rtc_proc,
	368	};
	369
	370	static int sa1100_rtc_probe(struct platform_device *pdev)
	371	{
	372	struct rtc_device *rtc;
	373
6769717d EM	374	timer_freq = get_clock_tick_rate();
6769717d EM	375
e842f1c8 RP	376	/*
	377	* According to the manual we should be able to let RTTR be zero
	378	* and then a default diviser for a 32.768KHz clock is used.
	379	* Apparently this doesn't work, at least for my SA1110 rev 5.
	380	* If the clock divider is uninitialized then reset it to the
	381	* default value to get the 1Hz clock.
	382	*/
	383	if (RTTR == 0) {
	384	RTTR = RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16);
a404ad1f MRJ	385	dev_warn(&pdev->dev, "warning: "
a404ad1f MRJ	386	"initializing default clock divider/trim value\n");
e842f1c8 RP	387	/* The current RTC value probably doesn't make sense either */
	388	RCNR = 0;
	389	}
	390
e5a2c9cc UL	391	device_init_wakeup(&pdev->dev, 1);
e5a2c9cc UL	392
e842f1c8 RP	393	rtc = rtc_device_register(pdev->name, &pdev->dev, &sa1100_rtc_ops,
	394	THIS_MODULE);
	395
2260a25c	396	if (IS_ERR(rtc))
e842f1c8	397	return PTR_ERR(rtc);
e842f1c8 RP	398
	399	platform_set_drvdata(pdev, rtc);
	400
7decaa55 MRJ	401	/* Fix for a nasty initialization problem the in SA11xx RTSR register.
	402	* See also the comments in sa1100_rtc_interrupt().
	403	*
	404	* Sometimes bit 1 of the RTSR (RTSR_HZ) will wake up 1, which means an
	405	* interrupt pending, even though interrupts were never enabled.
	406	* In this case, this bit it must be reset before enabling
	407	* interruptions to avoid a nonexistent interrupt to occur.
	408	*
	409	* In principle, the same problem would apply to bit 0, although it has
	410	* never been observed to happen.
	411	*
	412	* This issue is addressed both here and in sa1100_rtc_interrupt().
	413	* If the issue is not addressed here, in the times when the processor
	414	* wakes up with the bit set there will be one spurious interrupt.
	415	*
	416	* The issue is also dealt with in sa1100_rtc_interrupt() to be on the
	417	* safe side, once the condition that lead to this strange
	418	* initialization is unknown and could in principle happen during
	419	* normal processing.
	420	*
	421	* Notice that clearing bit 1 and 0 is accomplished by writting ONES to
	422	* the corresponding bits in RTSR. */
	423	RTSR = RTSR_AL \| RTSR_HZ;
	424
e842f1c8 RP	425	return 0;
	426	}
	427
	428	static int sa1100_rtc_remove(struct platform_device *pdev)
	429	{
	430	struct rtc_device *rtc = platform_get_drvdata(pdev);
	431
a404ad1f	432	if (rtc)
e842f1c8 RP	433	rtc_device_unregister(rtc);
	434
	435	return 0;
	436	}
	437
6bc54e69	438	#ifdef CONFIG_PM
5d027cd2	439	static int sa1100_rtc_suspend(struct device *dev)
6bc54e69	440	{
5d027cd2	441	if (device_may_wakeup(dev))
f618258a	442	enable_irq_wake(IRQ_RTCAlrm);
6bc54e69 RK	443	return 0;
	444	}
	445
5d027cd2	446	static int sa1100_rtc_resume(struct device *dev)
6bc54e69	447	{
5d027cd2	448	if (device_may_wakeup(dev))
f618258a	449	disable_irq_wake(IRQ_RTCAlrm);
6bc54e69 RK	450	return 0;
6bc54e69 RK	451	}
5d027cd2	452
47145210	453	static const struct dev_pm_ops sa1100_rtc_pm_ops = {
5d027cd2 HZ	454	.suspend = sa1100_rtc_suspend,
	455	.resume = sa1100_rtc_resume,
	456	};
6bc54e69 RK	457	#endif
6bc54e69 RK	458
e842f1c8 RP	459	static struct platform_driver sa1100_rtc_driver = {
	460	.probe = sa1100_rtc_probe,
	461	.remove = sa1100_rtc_remove,
	462	.driver = {
5d027cd2 HZ	463	.name = "sa1100-rtc",
	464	#ifdef CONFIG_PM
	465	.pm = &sa1100_rtc_pm_ops,
	466	#endif
e842f1c8 RP	467	},
	468	};
	469
	470	static int __init sa1100_rtc_init(void)
	471	{
	472	return platform_driver_register(&sa1100_rtc_driver);
	473	}
	474
	475	static void __exit sa1100_rtc_exit(void)
	476	{
	477	platform_driver_unregister(&sa1100_rtc_driver);
	478	}
	479
	480	module_init(sa1100_rtc_init);
	481	module_exit(sa1100_rtc_exit);
	482
	483	MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>");
	484	MODULE_DESCRIPTION("SA11x0/PXA2xx Realtime Clock Driver (RTC)");
	485	MODULE_LICENSE("GPL");
ad28a07b	486	MODULE_ALIAS("platform:sa1100-rtc");