Commit | Line | Data |
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e842f1c8 RP |
1 | /* |
2 | * Real Time Clock interface for StrongARM SA1x00 and XScale PXA2xx | |
3 | * | |
4 | * Copyright (c) 2000 Nils Faerber | |
5 | * | |
6 | * Based on rtc.c by Paul Gortmaker | |
7 | * | |
8 | * Original Driver by Nils Faerber <nils@kernelconcepts.de> | |
9 | * | |
10 | * Modifications from: | |
11 | * CIH <cih@coventive.com> | |
2f82af08 | 12 | * Nicolas Pitre <nico@fluxnic.net> |
e842f1c8 RP |
13 | * Andrew Christian <andrew.christian@hp.com> |
14 | * | |
15 | * Converted to the RTC subsystem and Driver Model | |
16 | * by Richard Purdie <rpurdie@rpsys.net> | |
17 | * | |
18 | * This program is free software; you can redistribute it and/or | |
19 | * modify it under the terms of the GNU General Public License | |
20 | * as published by the Free Software Foundation; either version | |
21 | * 2 of the License, or (at your option) any later version. | |
22 | */ | |
23 | ||
24 | #include <linux/platform_device.h> | |
25 | #include <linux/module.h> | |
8e8bbcb3 | 26 | #include <linux/clk.h> |
e842f1c8 RP |
27 | #include <linux/rtc.h> |
28 | #include <linux/init.h> | |
29 | #include <linux/fs.h> | |
30 | #include <linux/interrupt.h> | |
3888c090 | 31 | #include <linux/slab.h> |
a0164a57 | 32 | #include <linux/string.h> |
8bec2e9e | 33 | #include <linux/of.h> |
e842f1c8 | 34 | #include <linux/pm.h> |
a0164a57 | 35 | #include <linux/bitops.h> |
e842f1c8 | 36 | |
a09e64fb | 37 | #include <mach/hardware.h> |
e842f1c8 | 38 | #include <asm/irq.h> |
e842f1c8 | 39 | |
3888c090 | 40 | #if defined(CONFIG_ARCH_PXA) || defined(CONFIG_ARCH_MMP) |
a0164a57 RK |
41 | #include <mach/regs-rtc.h> |
42 | #endif | |
43 | ||
a404ad1f | 44 | #define RTC_DEF_DIVIDER (32768 - 1) |
e842f1c8 | 45 | #define RTC_DEF_TRIM 0 |
3888c090 | 46 | #define RTC_FREQ 1024 |
a0164a57 | 47 | |
3888c090 HZ |
48 | struct sa1100_rtc { |
49 | spinlock_t lock; | |
50 | int irq_1hz; | |
51 | int irq_alarm; | |
52 | struct rtc_device *rtc; | |
8e8bbcb3 | 53 | struct clk *clk; |
3888c090 | 54 | }; |
a0164a57 | 55 | |
7d12e780 | 56 | static irqreturn_t sa1100_rtc_interrupt(int irq, void *dev_id) |
e842f1c8 | 57 | { |
3888c090 HZ |
58 | struct sa1100_rtc *info = dev_get_drvdata(dev_id); |
59 | struct rtc_device *rtc = info->rtc; | |
e842f1c8 RP |
60 | unsigned int rtsr; |
61 | unsigned long events = 0; | |
62 | ||
3888c090 | 63 | spin_lock(&info->lock); |
e842f1c8 | 64 | |
a0164a57 | 65 | rtsr = RTSR; |
e842f1c8 | 66 | /* clear interrupt sources */ |
a0164a57 | 67 | RTSR = 0; |
7decaa55 MRJ |
68 | /* Fix for a nasty initialization problem the in SA11xx RTSR register. |
69 | * See also the comments in sa1100_rtc_probe(). */ | |
70 | if (rtsr & (RTSR_ALE | RTSR_HZE)) { | |
71 | /* This is the original code, before there was the if test | |
72 | * above. This code does not clear interrupts that were not | |
73 | * enabled. */ | |
a0164a57 | 74 | RTSR = (RTSR_AL | RTSR_HZ) & (rtsr >> 2); |
7decaa55 MRJ |
75 | } else { |
76 | /* For some reason, it is possible to enter this routine | |
77 | * without interruptions enabled, it has been tested with | |
78 | * several units (Bug in SA11xx chip?). | |
79 | * | |
80 | * This situation leads to an infinite "loop" of interrupt | |
81 | * routine calling and as a result the processor seems to | |
82 | * lock on its first call to open(). */ | |
a0164a57 | 83 | RTSR = RTSR_AL | RTSR_HZ; |
7decaa55 | 84 | } |
e842f1c8 RP |
85 | |
86 | /* clear alarm interrupt if it has occurred */ | |
87 | if (rtsr & RTSR_AL) | |
88 | rtsr &= ~RTSR_ALE; | |
a0164a57 | 89 | RTSR = rtsr & (RTSR_ALE | RTSR_HZE); |
e842f1c8 RP |
90 | |
91 | /* update irq data & counter */ | |
92 | if (rtsr & RTSR_AL) | |
93 | events |= RTC_AF | RTC_IRQF; | |
94 | if (rtsr & RTSR_HZ) | |
95 | events |= RTC_UF | RTC_IRQF; | |
96 | ||
a0164a57 | 97 | rtc_update_irq(rtc, 1, events); |
e842f1c8 | 98 | |
3888c090 | 99 | spin_unlock(&info->lock); |
e842f1c8 RP |
100 | |
101 | return IRQ_HANDLED; | |
102 | } | |
103 | ||
e842f1c8 RP |
104 | static int sa1100_rtc_open(struct device *dev) |
105 | { | |
3888c090 HZ |
106 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
107 | struct rtc_device *rtc = info->rtc; | |
e842f1c8 RP |
108 | int ret; |
109 | ||
8e8bbcb3 HZ |
110 | ret = clk_prepare_enable(info->clk); |
111 | if (ret) | |
112 | goto fail_clk; | |
3888c090 | 113 | ret = request_irq(info->irq_1hz, sa1100_rtc_interrupt, IRQF_DISABLED, |
a0164a57 | 114 | "rtc 1Hz", dev); |
e842f1c8 | 115 | if (ret) { |
3888c090 | 116 | dev_err(dev, "IRQ %d already in use.\n", info->irq_1hz); |
e842f1c8 RP |
117 | goto fail_ui; |
118 | } | |
3888c090 | 119 | ret = request_irq(info->irq_alarm, sa1100_rtc_interrupt, IRQF_DISABLED, |
a0164a57 | 120 | "rtc Alrm", dev); |
e842f1c8 | 121 | if (ret) { |
3888c090 | 122 | dev_err(dev, "IRQ %d already in use.\n", info->irq_alarm); |
e842f1c8 RP |
123 | goto fail_ai; |
124 | } | |
a0164a57 RK |
125 | rtc->max_user_freq = RTC_FREQ; |
126 | rtc_irq_set_freq(rtc, NULL, RTC_FREQ); | |
d2ccb52d | 127 | |
e842f1c8 RP |
128 | return 0; |
129 | ||
e842f1c8 | 130 | fail_ai: |
3888c090 | 131 | free_irq(info->irq_1hz, dev); |
e842f1c8 | 132 | fail_ui: |
8e8bbcb3 HZ |
133 | clk_disable_unprepare(info->clk); |
134 | fail_clk: | |
e842f1c8 RP |
135 | return ret; |
136 | } | |
137 | ||
138 | static void sa1100_rtc_release(struct device *dev) | |
139 | { | |
3888c090 HZ |
140 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
141 | ||
142 | spin_lock_irq(&info->lock); | |
a0164a57 | 143 | RTSR = 0; |
3888c090 | 144 | spin_unlock_irq(&info->lock); |
e842f1c8 | 145 | |
3888c090 HZ |
146 | free_irq(info->irq_alarm, dev); |
147 | free_irq(info->irq_1hz, dev); | |
8e8bbcb3 | 148 | clk_disable_unprepare(info->clk); |
e842f1c8 RP |
149 | } |
150 | ||
16380c15 JS |
151 | static int sa1100_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) |
152 | { | |
3888c090 HZ |
153 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
154 | ||
155 | spin_lock_irq(&info->lock); | |
16380c15 | 156 | if (enabled) |
a0164a57 | 157 | RTSR |= RTSR_ALE; |
16380c15 | 158 | else |
a0164a57 | 159 | RTSR &= ~RTSR_ALE; |
3888c090 | 160 | spin_unlock_irq(&info->lock); |
16380c15 JS |
161 | return 0; |
162 | } | |
163 | ||
e842f1c8 RP |
164 | static int sa1100_rtc_read_time(struct device *dev, struct rtc_time *tm) |
165 | { | |
a0164a57 | 166 | rtc_time_to_tm(RCNR, tm); |
e842f1c8 RP |
167 | return 0; |
168 | } | |
169 | ||
170 | static int sa1100_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
171 | { | |
172 | unsigned long time; | |
173 | int ret; | |
174 | ||
175 | ret = rtc_tm_to_time(tm, &time); | |
176 | if (ret == 0) | |
a0164a57 | 177 | RCNR = time; |
e842f1c8 RP |
178 | return ret; |
179 | } | |
180 | ||
181 | static int sa1100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
182 | { | |
a0164a57 | 183 | u32 rtsr; |
32b49da4 | 184 | |
a0164a57 | 185 | rtsr = RTSR; |
32b49da4 DB |
186 | alrm->enabled = (rtsr & RTSR_ALE) ? 1 : 0; |
187 | alrm->pending = (rtsr & RTSR_AL) ? 1 : 0; | |
e842f1c8 RP |
188 | return 0; |
189 | } | |
190 | ||
191 | static int sa1100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
192 | { | |
3888c090 | 193 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
1d8c38c3 | 194 | unsigned long time; |
a0164a57 | 195 | int ret; |
e842f1c8 | 196 | |
3888c090 | 197 | spin_lock_irq(&info->lock); |
1d8c38c3 HZ |
198 | ret = rtc_tm_to_time(&alrm->time, &time); |
199 | if (ret != 0) | |
200 | goto out; | |
201 | RTSR = RTSR & (RTSR_HZE|RTSR_ALE|RTSR_AL); | |
202 | RTAR = time; | |
203 | if (alrm->enabled) | |
204 | RTSR |= RTSR_ALE; | |
205 | else | |
206 | RTSR &= ~RTSR_ALE; | |
207 | out: | |
3888c090 | 208 | spin_unlock_irq(&info->lock); |
e842f1c8 | 209 | |
a0164a57 | 210 | return ret; |
e842f1c8 RP |
211 | } |
212 | ||
213 | static int sa1100_rtc_proc(struct device *dev, struct seq_file *seq) | |
214 | { | |
a0164a57 RK |
215 | seq_printf(seq, "trim/divider\t\t: 0x%08x\n", (u32) RTTR); |
216 | seq_printf(seq, "RTSR\t\t\t: 0x%08x\n", (u32)RTSR); | |
e842f1c8 RP |
217 | |
218 | return 0; | |
219 | } | |
220 | ||
ff8371ac | 221 | static const struct rtc_class_ops sa1100_rtc_ops = { |
e842f1c8 | 222 | .open = sa1100_rtc_open, |
e842f1c8 | 223 | .release = sa1100_rtc_release, |
e842f1c8 RP |
224 | .read_time = sa1100_rtc_read_time, |
225 | .set_time = sa1100_rtc_set_time, | |
226 | .read_alarm = sa1100_rtc_read_alarm, | |
227 | .set_alarm = sa1100_rtc_set_alarm, | |
228 | .proc = sa1100_rtc_proc, | |
16380c15 | 229 | .alarm_irq_enable = sa1100_rtc_alarm_irq_enable, |
e842f1c8 RP |
230 | }; |
231 | ||
232 | static int sa1100_rtc_probe(struct platform_device *pdev) | |
233 | { | |
a0164a57 | 234 | struct rtc_device *rtc; |
3888c090 HZ |
235 | struct sa1100_rtc *info; |
236 | int irq_1hz, irq_alarm, ret = 0; | |
237 | ||
238 | irq_1hz = platform_get_irq_byname(pdev, "rtc 1Hz"); | |
239 | irq_alarm = platform_get_irq_byname(pdev, "rtc alarm"); | |
240 | if (irq_1hz < 0 || irq_alarm < 0) | |
241 | return -ENODEV; | |
242 | ||
243 | info = kzalloc(sizeof(struct sa1100_rtc), GFP_KERNEL); | |
244 | if (!info) | |
245 | return -ENOMEM; | |
8e8bbcb3 HZ |
246 | info->clk = clk_get(&pdev->dev, NULL); |
247 | if (IS_ERR(info->clk)) { | |
248 | dev_err(&pdev->dev, "failed to find rtc clock source\n"); | |
249 | ret = PTR_ERR(info->clk); | |
250 | goto err_clk; | |
251 | } | |
3888c090 HZ |
252 | info->irq_1hz = irq_1hz; |
253 | info->irq_alarm = irq_alarm; | |
254 | spin_lock_init(&info->lock); | |
255 | platform_set_drvdata(pdev, info); | |
e842f1c8 RP |
256 | |
257 | /* | |
258 | * According to the manual we should be able to let RTTR be zero | |
259 | * and then a default diviser for a 32.768KHz clock is used. | |
260 | * Apparently this doesn't work, at least for my SA1110 rev 5. | |
261 | * If the clock divider is uninitialized then reset it to the | |
262 | * default value to get the 1Hz clock. | |
263 | */ | |
a0164a57 RK |
264 | if (RTTR == 0) { |
265 | RTTR = RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16); | |
266 | dev_warn(&pdev->dev, "warning: " | |
267 | "initializing default clock divider/trim value\n"); | |
e842f1c8 | 268 | /* The current RTC value probably doesn't make sense either */ |
a0164a57 | 269 | RCNR = 0; |
e842f1c8 RP |
270 | } |
271 | ||
e5a2c9cc UL |
272 | device_init_wakeup(&pdev->dev, 1); |
273 | ||
a0164a57 RK |
274 | rtc = rtc_device_register(pdev->name, &pdev->dev, &sa1100_rtc_ops, |
275 | THIS_MODULE); | |
276 | ||
3888c090 HZ |
277 | if (IS_ERR(rtc)) { |
278 | ret = PTR_ERR(rtc); | |
279 | goto err_dev; | |
280 | } | |
281 | info->rtc = rtc; | |
a0164a57 | 282 | |
7decaa55 MRJ |
283 | /* Fix for a nasty initialization problem the in SA11xx RTSR register. |
284 | * See also the comments in sa1100_rtc_interrupt(). | |
285 | * | |
286 | * Sometimes bit 1 of the RTSR (RTSR_HZ) will wake up 1, which means an | |
287 | * interrupt pending, even though interrupts were never enabled. | |
288 | * In this case, this bit it must be reset before enabling | |
289 | * interruptions to avoid a nonexistent interrupt to occur. | |
290 | * | |
291 | * In principle, the same problem would apply to bit 0, although it has | |
292 | * never been observed to happen. | |
293 | * | |
294 | * This issue is addressed both here and in sa1100_rtc_interrupt(). | |
295 | * If the issue is not addressed here, in the times when the processor | |
296 | * wakes up with the bit set there will be one spurious interrupt. | |
297 | * | |
298 | * The issue is also dealt with in sa1100_rtc_interrupt() to be on the | |
299 | * safe side, once the condition that lead to this strange | |
300 | * initialization is unknown and could in principle happen during | |
301 | * normal processing. | |
302 | * | |
303 | * Notice that clearing bit 1 and 0 is accomplished by writting ONES to | |
304 | * the corresponding bits in RTSR. */ | |
a0164a57 | 305 | RTSR = RTSR_AL | RTSR_HZ; |
7decaa55 | 306 | |
e842f1c8 | 307 | return 0; |
3888c090 HZ |
308 | err_dev: |
309 | platform_set_drvdata(pdev, NULL); | |
8e8bbcb3 HZ |
310 | clk_put(info->clk); |
311 | err_clk: | |
3888c090 HZ |
312 | kfree(info); |
313 | return ret; | |
e842f1c8 RP |
314 | } |
315 | ||
316 | static int sa1100_rtc_remove(struct platform_device *pdev) | |
317 | { | |
3888c090 | 318 | struct sa1100_rtc *info = platform_get_drvdata(pdev); |
a0164a57 | 319 | |
3888c090 HZ |
320 | if (info) { |
321 | rtc_device_unregister(info->rtc); | |
8e8bbcb3 | 322 | clk_put(info->clk); |
3888c090 HZ |
323 | platform_set_drvdata(pdev, NULL); |
324 | kfree(info); | |
325 | } | |
e842f1c8 RP |
326 | |
327 | return 0; | |
328 | } | |
329 | ||
6bc54e69 | 330 | #ifdef CONFIG_PM |
5d027cd2 | 331 | static int sa1100_rtc_suspend(struct device *dev) |
6bc54e69 | 332 | { |
3888c090 | 333 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
5d027cd2 | 334 | if (device_may_wakeup(dev)) |
3888c090 | 335 | enable_irq_wake(info->irq_alarm); |
6bc54e69 RK |
336 | return 0; |
337 | } | |
338 | ||
5d027cd2 | 339 | static int sa1100_rtc_resume(struct device *dev) |
6bc54e69 | 340 | { |
3888c090 | 341 | struct sa1100_rtc *info = dev_get_drvdata(dev); |
5d027cd2 | 342 | if (device_may_wakeup(dev)) |
3888c090 | 343 | disable_irq_wake(info->irq_alarm); |
6bc54e69 RK |
344 | return 0; |
345 | } | |
5d027cd2 | 346 | |
47145210 | 347 | static const struct dev_pm_ops sa1100_rtc_pm_ops = { |
5d027cd2 HZ |
348 | .suspend = sa1100_rtc_suspend, |
349 | .resume = sa1100_rtc_resume, | |
350 | }; | |
6bc54e69 RK |
351 | #endif |
352 | ||
8bec2e9e HZ |
353 | static struct of_device_id sa1100_rtc_dt_ids[] = { |
354 | { .compatible = "mrvl,sa1100-rtc", }, | |
355 | { .compatible = "mrvl,mmp-rtc", }, | |
356 | {} | |
357 | }; | |
358 | MODULE_DEVICE_TABLE(of, sa1100_rtc_dt_ids); | |
359 | ||
e842f1c8 RP |
360 | static struct platform_driver sa1100_rtc_driver = { |
361 | .probe = sa1100_rtc_probe, | |
362 | .remove = sa1100_rtc_remove, | |
363 | .driver = { | |
5d027cd2 HZ |
364 | .name = "sa1100-rtc", |
365 | #ifdef CONFIG_PM | |
366 | .pm = &sa1100_rtc_pm_ops, | |
367 | #endif | |
8bec2e9e | 368 | .of_match_table = sa1100_rtc_dt_ids, |
e842f1c8 RP |
369 | }, |
370 | }; | |
371 | ||
0c4eae66 | 372 | module_platform_driver(sa1100_rtc_driver); |
e842f1c8 RP |
373 | |
374 | MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>"); | |
375 | MODULE_DESCRIPTION("SA11x0/PXA2xx Realtime Clock Driver (RTC)"); | |
376 | MODULE_LICENSE("GPL"); | |
ad28a07b | 377 | MODULE_ALIAS("platform:sa1100-rtc"); |