[deliverable/linux.git] / drivers / rtc / rtc-vr41xx.c

/*
 *  Driver for NEC VR4100 series Real Time Clock unit.
 *
 *  Copyright (C) 2003-2006  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/err.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/spinlock.h>
#include <linux/types.h>

#include <asm/div64.h>
#include <asm/io.h>
#include <asm/uaccess.h>

MODULE_AUTHOR("Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>");
MODULE_DESCRIPTION("NEC VR4100 series RTC driver");
MODULE_LICENSE("GPL");

/* RTC 1 registers */
#define ETIMELREG		0x00
#define ETIMEMREG		0x02
#define ETIMEHREG		0x04
/* RFU */
#define ECMPLREG		0x08
#define ECMPMREG		0x0a
#define ECMPHREG		0x0c
/* RFU */
#define RTCL1LREG		0x10
#define RTCL1HREG		0x12
#define RTCL1CNTLREG		0x14
#define RTCL1CNTHREG		0x16
#define RTCL2LREG		0x18
#define RTCL2HREG		0x1a
#define RTCL2CNTLREG		0x1c
#define RTCL2CNTHREG		0x1e

/* RTC 2 registers */
#define TCLKLREG		0x00
#define TCLKHREG		0x02
#define TCLKCNTLREG		0x04
#define TCLKCNTHREG		0x06
/* RFU */
#define RTCINTREG		0x1e
 #define TCLOCK_INT		0x08
 #define RTCLONG2_INT		0x04
 #define RTCLONG1_INT		0x02
 #define ELAPSEDTIME_INT	0x01

#define RTC_FREQUENCY		32768
#define MAX_PERIODIC_RATE	6553

static void __iomem *rtc1_base;
static void __iomem *rtc2_base;

#define rtc1_read(offset)		readw(rtc1_base + (offset))
#define rtc1_write(offset, value)	writew((value), rtc1_base + (offset))

#define rtc2_read(offset)		readw(rtc2_base + (offset))
#define rtc2_write(offset, value)	writew((value), rtc2_base + (offset))

static unsigned long epoch = 1970;	/* Jan 1 1970 00:00:00 */

static DEFINE_SPINLOCK(rtc_lock);
static char rtc_name[] = "RTC";
static unsigned long periodic_frequency;
static unsigned long periodic_count;
static unsigned int alarm_enabled;
static int aie_irq = -1;
static int pie_irq = -1;

static inline unsigned long read_elapsed_second(void)
{

	unsigned long first_low, first_mid, first_high;

	unsigned long second_low, second_mid, second_high;

	do {
		first_low = rtc1_read(ETIMELREG);
		first_mid = rtc1_read(ETIMEMREG);
		first_high = rtc1_read(ETIMEHREG);
		second_low = rtc1_read(ETIMELREG);
		second_mid = rtc1_read(ETIMEMREG);
		second_high = rtc1_read(ETIMEHREG);
	} while (first_low != second_low || first_mid != second_mid ||
	         first_high != second_high);

	return (first_high << 17) | (first_mid << 1) | (first_low >> 15);
}

static inline void write_elapsed_second(unsigned long sec)
{
	spin_lock_irq(&rtc_lock);

	rtc1_write(ETIMELREG, (uint16_t)(sec << 15));
	rtc1_write(ETIMEMREG, (uint16_t)(sec >> 1));
	rtc1_write(ETIMEHREG, (uint16_t)(sec >> 17));

	spin_unlock_irq(&rtc_lock);
}

static void vr41xx_rtc_release(struct device *dev)
{

	spin_lock_irq(&rtc_lock);

	rtc1_write(ECMPLREG, 0);
	rtc1_write(ECMPMREG, 0);
	rtc1_write(ECMPHREG, 0);
	rtc1_write(RTCL1LREG, 0);
	rtc1_write(RTCL1HREG, 0);

	spin_unlock_irq(&rtc_lock);

	disable_irq(aie_irq);
	disable_irq(pie_irq);
}

static int vr41xx_rtc_read_time(struct device *dev, struct rtc_time *time)
{
	unsigned long epoch_sec, elapsed_sec;

	epoch_sec = mktime(epoch, 1, 1, 0, 0, 0);
	elapsed_sec = read_elapsed_second();

	rtc_time_to_tm(epoch_sec + elapsed_sec, time);

	return 0;
}

static int vr41xx_rtc_set_time(struct device *dev, struct rtc_time *time)
{
	unsigned long epoch_sec, current_sec;

	epoch_sec = mktime(epoch, 1, 1, 0, 0, 0);
	current_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday,
	                     time->tm_hour, time->tm_min, time->tm_sec);

	write_elapsed_second(current_sec - epoch_sec);

	return 0;
}

static int vr41xx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
{
	unsigned long low, mid, high;
	struct rtc_time *time = &wkalrm->time;

	spin_lock_irq(&rtc_lock);

	low = rtc1_read(ECMPLREG);
	mid = rtc1_read(ECMPMREG);
	high = rtc1_read(ECMPHREG);
	wkalrm->enabled = alarm_enabled;

	spin_unlock_irq(&rtc_lock);

	rtc_time_to_tm((high << 17) | (mid << 1) | (low >> 15), time);

	return 0;
}

static int vr41xx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
{
	unsigned long alarm_sec;
	struct rtc_time *time = &wkalrm->time;

	alarm_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday,
	                   time->tm_hour, time->tm_min, time->tm_sec);

	spin_lock_irq(&rtc_lock);

	if (alarm_enabled)
		disable_irq(aie_irq);

	rtc1_write(ECMPLREG, (uint16_t)(alarm_sec << 15));
	rtc1_write(ECMPMREG, (uint16_t)(alarm_sec >> 1));
	rtc1_write(ECMPHREG, (uint16_t)(alarm_sec >> 17));

	if (wkalrm->enabled)
		enable_irq(aie_irq);

	alarm_enabled = wkalrm->enabled;

	spin_unlock_irq(&rtc_lock);

	return 0;
}

static int vr41xx_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
{
	unsigned long count;

	switch (cmd) {
	case RTC_AIE_ON:
		spin_lock_irq(&rtc_lock);

		if (!alarm_enabled) {
			enable_irq(aie_irq);
			alarm_enabled = 1;
		}

		spin_unlock_irq(&rtc_lock);
		break;
	case RTC_AIE_OFF:
		spin_lock_irq(&rtc_lock);

		if (alarm_enabled) {
			disable_irq(aie_irq);
			alarm_enabled = 0;
		}

		spin_unlock_irq(&rtc_lock);
		break;
	case RTC_PIE_ON:
		enable_irq(pie_irq);
		break;
	case RTC_PIE_OFF:
		disable_irq(pie_irq);
		break;
	case RTC_IRQP_READ:
		return put_user(periodic_frequency, (unsigned long __user *)arg);
		break;
	case RTC_IRQP_SET:
		if (arg > MAX_PERIODIC_RATE)
			return -EINVAL;

		periodic_frequency = arg;

		count = RTC_FREQUENCY;
		do_div(count, arg);

		periodic_count = count;

		spin_lock_irq(&rtc_lock);

		rtc1_write(RTCL1LREG, count);
		rtc1_write(RTCL1HREG, count >> 16);

		spin_unlock_irq(&rtc_lock);
		break;
	case RTC_EPOCH_READ:
		return put_user(epoch, (unsigned long __user *)arg);
	case RTC_EPOCH_SET:
		/* Doesn't support before 1900 */
		if (arg < 1900)
			return -EINVAL;
		epoch = arg;
		break;
	default:
		return -ENOIOCTLCMD;
	}

	return 0;
}

static irqreturn_t elapsedtime_interrupt(int irq, void *dev_id)
{
	struct platform_device *pdev = (struct platform_device *)dev_id;
	struct rtc_device *rtc = platform_get_drvdata(pdev);

	rtc2_write(RTCINTREG, ELAPSEDTIME_INT);

	rtc_update_irq(rtc, 1, RTC_AF);

	return IRQ_HANDLED;
}

static irqreturn_t rtclong1_interrupt(int irq, void *dev_id)
{
	struct platform_device *pdev = (struct platform_device *)dev_id;
	struct rtc_device *rtc = platform_get_drvdata(pdev);
	unsigned long count = periodic_count;

	rtc2_write(RTCINTREG, RTCLONG1_INT);

	rtc1_write(RTCL1LREG, count);
	rtc1_write(RTCL1HREG, count >> 16);

	rtc_update_irq(rtc, 1, RTC_PF);

	return IRQ_HANDLED;
}

static const struct rtc_class_ops vr41xx_rtc_ops = {
	.release	= vr41xx_rtc_release,
	.ioctl		= vr41xx_rtc_ioctl,
	.read_time	= vr41xx_rtc_read_time,
	.set_time	= vr41xx_rtc_set_time,
	.read_alarm	= vr41xx_rtc_read_alarm,
	.set_alarm	= vr41xx_rtc_set_alarm,
};

static int __devinit rtc_probe(struct platform_device *pdev)
{
	struct resource *res;
	struct rtc_device *rtc;
	int retval;

	if (pdev->num_resources != 4)
		return -EBUSY;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -EBUSY;

	rtc1_base = ioremap(res->start, res->end - res->start + 1);
	if (!rtc1_base)
		return -EBUSY;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (!res) {
		retval = -EBUSY;
		goto err_rtc1_iounmap;
	}

	rtc2_base = ioremap(res->start, res->end - res->start + 1);
	if (!rtc2_base) {
		retval = -EBUSY;
		goto err_rtc1_iounmap;
	}

	rtc = rtc_device_register(rtc_name, &pdev->dev, &vr41xx_rtc_ops, THIS_MODULE);
	if (IS_ERR(rtc)) {
		retval = PTR_ERR(rtc);
		goto err_iounmap_all;
	}

	spin_lock_irq(&rtc_lock);

	rtc1_write(ECMPLREG, 0);
	rtc1_write(ECMPMREG, 0);
	rtc1_write(ECMPHREG, 0);
	rtc1_write(RTCL1LREG, 0);
	rtc1_write(RTCL1HREG, 0);

	spin_unlock_irq(&rtc_lock);

	aie_irq = platform_get_irq(pdev, 0);
	if (aie_irq < 0 || aie_irq >= NR_IRQS) {
		retval = -EBUSY;
		goto err_device_unregister;
	}

	retval = request_irq(aie_irq, elapsedtime_interrupt, IRQF_DISABLED,
	                     "elapsed_time", pdev);
	if (retval < 0)
		goto err_device_unregister;

	pie_irq = platform_get_irq(pdev, 1);
	if (pie_irq < 0 || pie_irq >= NR_IRQS)
		goto err_free_irq;

	retval = request_irq(pie_irq, rtclong1_interrupt, IRQF_DISABLED,
		             "rtclong1", pdev);
	if (retval < 0)
		goto err_free_irq;

	platform_set_drvdata(pdev, rtc);

	disable_irq(aie_irq);
	disable_irq(pie_irq);

	printk(KERN_INFO "rtc: Real Time Clock of NEC VR4100 series\n");

	return 0;

err_free_irq:
	free_irq(aie_irq, pdev);

err_device_unregister:
	rtc_device_unregister(rtc);

err_iounmap_all:
	iounmap(rtc2_base);
	rtc2_base = NULL;

err_rtc1_iounmap:
	iounmap(rtc1_base);
	rtc1_base = NULL;

	return retval;
}

static int __devexit rtc_remove(struct platform_device *pdev)
{
	struct rtc_device *rtc;

	rtc = platform_get_drvdata(pdev);
	if (rtc)
		rtc_device_unregister(rtc);

	platform_set_drvdata(pdev, NULL);

	free_irq(aie_irq, pdev);
	free_irq(pie_irq, pdev);
	if (rtc1_base)
		iounmap(rtc1_base);
	if (rtc2_base)
		iounmap(rtc2_base);

	return 0;
}

static struct platform_driver rtc_platform_driver = {
	.probe		= rtc_probe,
	.remove		= __devexit_p(rtc_remove),
	.driver		= {
		.name	= rtc_name,
		.owner	= THIS_MODULE,
	},
};

static int __init vr41xx_rtc_init(void)
{
	return platform_driver_register(&rtc_platform_driver);
}

static void __exit vr41xx_rtc_exit(void)
{
	platform_driver_unregister(&rtc_platform_driver);
}

module_init(vr41xx_rtc_init);
module_exit(vr41xx_rtc_exit);
Commit	Line	Data
1da177e4	1	/*
8417eb7a	2	* Driver for NEC VR4100 series Real Time Clock unit.
1da177e4	3	*
8417eb7a	4	* Copyright (C) 2003-2006 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
1da177e4 LT	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
bd076509	20	#include <linux/err.h>
1da177e4 LT	21	#include <linux/fs.h>
	22	#include <linux/init.h>
	23	#include <linux/ioport.h>
bd076509	24	#include <linux/interrupt.h>
1da177e4	25	#include <linux/module.h>
8417eb7a	26	#include <linux/platform_device.h>
1da177e4 LT	27	#include <linux/rtc.h>
	28	#include <linux/spinlock.h>
	29	#include <linux/types.h>
1da177e4 LT	30
	31	#include <asm/div64.h>
	32	#include <asm/io.h>
1da177e4	33	#include <asm/uaccess.h>
1da177e4	34
29ce2c76	35	MODULE_AUTHOR("Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>");
1da177e4 LT	36	MODULE_DESCRIPTION("NEC VR4100 series RTC driver");
	37	MODULE_LICENSE("GPL");
	38
1da177e4 LT	39	/* RTC 1 registers */
	40	#define ETIMELREG 0x00
	41	#define ETIMEMREG 0x02
	42	#define ETIMEHREG 0x04
	43	/* RFU */
	44	#define ECMPLREG 0x08
	45	#define ECMPMREG 0x0a
	46	#define ECMPHREG 0x0c
	47	/* RFU */
	48	#define RTCL1LREG 0x10
	49	#define RTCL1HREG 0x12
	50	#define RTCL1CNTLREG 0x14
	51	#define RTCL1CNTHREG 0x16
	52	#define RTCL2LREG 0x18
	53	#define RTCL2HREG 0x1a
	54	#define RTCL2CNTLREG 0x1c
	55	#define RTCL2CNTHREG 0x1e
	56
	57	/* RTC 2 registers */
	58	#define TCLKLREG 0x00
	59	#define TCLKHREG 0x02
	60	#define TCLKCNTLREG 0x04
	61	#define TCLKCNTHREG 0x06
	62	/* RFU */
	63	#define RTCINTREG 0x1e
	64	#define TCLOCK_INT 0x08
	65	#define RTCLONG2_INT 0x04
	66	#define RTCLONG1_INT 0x02
	67	#define ELAPSEDTIME_INT 0x01
	68
	69	#define RTC_FREQUENCY 32768
	70	#define MAX_PERIODIC_RATE 6553
1da177e4 LT	71
	72	static void __iomem *rtc1_base;
	73	static void __iomem *rtc2_base;
	74
	75	#define rtc1_read(offset) readw(rtc1_base + (offset))
	76	#define rtc1_write(offset, value) writew((value), rtc1_base + (offset))
	77
	78	#define rtc2_read(offset) readw(rtc2_base + (offset))
	79	#define rtc2_write(offset, value) writew((value), rtc2_base + (offset))
	80
	81	static unsigned long epoch = 1970; /* Jan 1 1970 00:00:00 */
	82
34af946a	83	static DEFINE_SPINLOCK(rtc_lock);
1da177e4 LT	84	static char rtc_name[] = "RTC";
	85	static unsigned long periodic_frequency;
	86	static unsigned long periodic_count;
9b5ef64a	87	static unsigned int alarm_enabled;
bd076509 YY	88	static int aie_irq = -1;
bd076509 YY	89	static int pie_irq = -1;
1da177e4	90
1da177e4 LT	91	static inline unsigned long read_elapsed_second(void)
1da177e4 LT	92	{
8417eb7a	93
1da177e4	94	unsigned long first_low, first_mid, first_high;
8417eb7a	95
1da177e4 LT	96	unsigned long second_low, second_mid, second_high;
	97
	98	do {
	99	first_low = rtc1_read(ETIMELREG);
	100	first_mid = rtc1_read(ETIMEMREG);
	101	first_high = rtc1_read(ETIMEHREG);
	102	second_low = rtc1_read(ETIMELREG);
	103	second_mid = rtc1_read(ETIMEMREG);
	104	second_high = rtc1_read(ETIMEHREG);
	105	} while (first_low != second_low \|\| first_mid != second_mid \|\|
	106	first_high != second_high);
	107
	108	return (first_high << 17) \| (first_mid << 1) \| (first_low >> 15);
	109	}
	110
	111	static inline void write_elapsed_second(unsigned long sec)
	112	{
	113	spin_lock_irq(&rtc_lock);
	114
	115	rtc1_write(ETIMELREG, (uint16_t)(sec << 15));
	116	rtc1_write(ETIMEMREG, (uint16_t)(sec >> 1));
	117	rtc1_write(ETIMEHREG, (uint16_t)(sec >> 17));
	118
	119	spin_unlock_irq(&rtc_lock);
	120	}
	121
8417eb7a	122	static void vr41xx_rtc_release(struct device *dev)
1da177e4	123	{
1da177e4 LT	124
	125	spin_lock_irq(&rtc_lock);
	126
8417eb7a YY	127	rtc1_write(ECMPLREG, 0);
	128	rtc1_write(ECMPMREG, 0);
	129	rtc1_write(ECMPHREG, 0);
	130	rtc1_write(RTCL1LREG, 0);
	131	rtc1_write(RTCL1HREG, 0);
1da177e4 LT	132
	133	spin_unlock_irq(&rtc_lock);
	134
bd076509 YY	135	disable_irq(aie_irq);
bd076509 YY	136	disable_irq(pie_irq);
1da177e4 LT	137	}
1da177e4 LT	138
8417eb7a	139	static int vr41xx_rtc_read_time(struct device dev, struct rtc_time time)
1da177e4 LT	140	{
	141	unsigned long epoch_sec, elapsed_sec;
	142
	143	epoch_sec = mktime(epoch, 1, 1, 0, 0, 0);
	144	elapsed_sec = read_elapsed_second();
	145
8417eb7a YY	146	rtc_time_to_tm(epoch_sec + elapsed_sec, time);
	147
	148	return 0;
1da177e4 LT	149	}
1da177e4 LT	150
8417eb7a	151	static int vr41xx_rtc_set_time(struct device dev, struct rtc_time time)
1da177e4 LT	152	{
	153	unsigned long epoch_sec, current_sec;
	154
	155	epoch_sec = mktime(epoch, 1, 1, 0, 0, 0);
	156	current_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday,
	157	time->tm_hour, time->tm_min, time->tm_sec);
	158
	159	write_elapsed_second(current_sec - epoch_sec);
8417eb7a YY	160
8417eb7a YY	161	return 0;
1da177e4 LT	162	}
1da177e4 LT	163
8417eb7a	164	static int vr41xx_rtc_read_alarm(struct device dev, struct rtc_wkalrm wkalrm)
1da177e4	165	{
8417eb7a YY	166	unsigned long low, mid, high;
8417eb7a YY	167	struct rtc_time *time = &wkalrm->time;
1da177e4	168
8417eb7a	169	spin_lock_irq(&rtc_lock);
1da177e4	170
8417eb7a YY	171	low = rtc1_read(ECMPLREG);
	172	mid = rtc1_read(ECMPMREG);
	173	high = rtc1_read(ECMPHREG);
9b5ef64a	174	wkalrm->enabled = alarm_enabled;
1da177e4	175
8417eb7a	176	spin_unlock_irq(&rtc_lock);
1da177e4	177
8417eb7a	178	rtc_time_to_tm((high << 17) \| (mid << 1) \| (low >> 15), time);
1da177e4	179
8417eb7a YY	180	return 0;
8417eb7a YY	181	}
1da177e4	182
8417eb7a YY	183	static int vr41xx_rtc_set_alarm(struct device dev, struct rtc_wkalrm wkalrm)
	184	{
	185	unsigned long alarm_sec;
	186	struct rtc_time *time = &wkalrm->time;
1da177e4	187
8417eb7a YY	188	alarm_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday,
8417eb7a YY	189	time->tm_hour, time->tm_min, time->tm_sec);
1da177e4	190
8417eb7a	191	spin_lock_irq(&rtc_lock);
1da177e4	192
9b5ef64a	193	if (alarm_enabled)
bd076509	194	disable_irq(aie_irq);
9b5ef64a	195
8417eb7a YY	196	rtc1_write(ECMPLREG, (uint16_t)(alarm_sec << 15));
	197	rtc1_write(ECMPMREG, (uint16_t)(alarm_sec >> 1));
	198	rtc1_write(ECMPHREG, (uint16_t)(alarm_sec >> 17));
1da177e4	199
9b5ef64a	200	if (wkalrm->enabled)
bd076509	201	enable_irq(aie_irq);
9b5ef64a YY	202
	203	alarm_enabled = wkalrm->enabled;
	204
8417eb7a	205	spin_unlock_irq(&rtc_lock);
1da177e4 LT	206
	207	return 0;
	208	}
	209
8417eb7a	210	static int vr41xx_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
1da177e4	211	{
1da177e4 LT	212	unsigned long count;
	213
	214	switch (cmd) {
	215	case RTC_AIE_ON:
9b5ef64a YY	216	spin_lock_irq(&rtc_lock);
	217
	218	if (!alarm_enabled) {
bd076509	219	enable_irq(aie_irq);
9b5ef64a YY	220	alarm_enabled = 1;
	221	}
	222
	223	spin_unlock_irq(&rtc_lock);
1da177e4 LT	224	break;
1da177e4 LT	225	case RTC_AIE_OFF:
9b5ef64a YY	226	spin_lock_irq(&rtc_lock);
	227
	228	if (alarm_enabled) {
bd076509	229	disable_irq(aie_irq);
9b5ef64a YY	230	alarm_enabled = 0;
	231	}
	232
	233	spin_unlock_irq(&rtc_lock);
1da177e4 LT	234	break;
1da177e4 LT	235	case RTC_PIE_ON:
bd076509	236	enable_irq(pie_irq);
1da177e4 LT	237	break;
1da177e4 LT	238	case RTC_PIE_OFF:
bd076509	239	disable_irq(pie_irq);
1da177e4	240	break;
1da177e4 LT	241	case RTC_IRQP_READ:
	242	return put_user(periodic_frequency, (unsigned long __user *)arg);
	243	break;
	244	case RTC_IRQP_SET:
	245	if (arg > MAX_PERIODIC_RATE)
	246	return -EINVAL;
	247
1da177e4 LT	248	periodic_frequency = arg;
	249
	250	count = RTC_FREQUENCY;
	251	do_div(count, arg);
	252
	253	periodic_count = count;
	254
	255	spin_lock_irq(&rtc_lock);
	256
	257	rtc1_write(RTCL1LREG, count);
	258	rtc1_write(RTCL1HREG, count >> 16);
	259
	260	spin_unlock_irq(&rtc_lock);
	261	break;
	262	case RTC_EPOCH_READ:
	263	return put_user(epoch, (unsigned long __user *)arg);
	264	case RTC_EPOCH_SET:
	265	/* Doesn't support before 1900 */
	266	if (arg < 1900)
	267	return -EINVAL;
1da177e4 LT	268	epoch = arg;
	269	break;
	270	default:
b3969e58	271	return -ENOIOCTLCMD;
1da177e4 LT	272	}
	273
	274	return 0;
	275	}
	276
7d12e780	277	static irqreturn_t elapsedtime_interrupt(int irq, void *dev_id)
1da177e4	278	{
8417eb7a YY	279	struct platform_device pdev = (struct platform_device )dev_id;
8417eb7a YY	280	struct rtc_device *rtc = platform_get_drvdata(pdev);
1da177e4	281
8417eb7a	282	rtc2_write(RTCINTREG, ELAPSEDTIME_INT);
1da177e4	283
ab6a2d70	284	rtc_update_irq(rtc, 1, RTC_AF);
1da177e4 LT	285
	286	return IRQ_HANDLED;
	287	}
	288
7d12e780	289	static irqreturn_t rtclong1_interrupt(int irq, void *dev_id)
1da177e4	290	{
8417eb7a YY	291	struct platform_device pdev = (struct platform_device )dev_id;
8417eb7a YY	292	struct rtc_device *rtc = platform_get_drvdata(pdev);
1da177e4 LT	293	unsigned long count = periodic_count;
1da177e4 LT	294
1da177e4 LT	295	rtc2_write(RTCINTREG, RTCLONG1_INT);
	296
	297	rtc1_write(RTCL1LREG, count);
	298	rtc1_write(RTCL1HREG, count >> 16);
	299
ab6a2d70	300	rtc_update_irq(rtc, 1, RTC_PF);
1da177e4 LT	301
	302	return IRQ_HANDLED;
	303	}
	304
ff8371ac	305	static const struct rtc_class_ops vr41xx_rtc_ops = {
8417eb7a YY	306	.release = vr41xx_rtc_release,
	307	.ioctl = vr41xx_rtc_ioctl,
	308	.read_time = vr41xx_rtc_read_time,
	309	.set_time = vr41xx_rtc_set_time,
	310	.read_alarm = vr41xx_rtc_read_alarm,
	311	.set_alarm = vr41xx_rtc_set_alarm,
1da177e4 LT	312	};
1da177e4 LT	313
d39b6cfe	314	static int __devinit rtc_probe(struct platform_device *pdev)
1da177e4	315	{
bd076509	316	struct resource *res;
8417eb7a	317	struct rtc_device *rtc;
1da177e4 LT	318	int retval;
1da177e4 LT	319
bd076509	320	if (pdev->num_resources != 4)
1da177e4 LT	321	return -EBUSY;
1da177e4 LT	322
bd076509 YY	323	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
bd076509 YY	324	if (!res)
1da177e4 LT	325	return -EBUSY;
1da177e4 LT	326
bd076509 YY	327	rtc1_base = ioremap(res->start, res->end - res->start + 1);
bd076509 YY	328	if (!rtc1_base)
1da177e4	329	return -EBUSY;
bd076509 YY	330
	331	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	332	if (!res) {
	333	retval = -EBUSY;
	334	goto err_rtc1_iounmap;
	335	}
	336
	337	rtc2_base = ioremap(res->start, res->end - res->start + 1);
	338	if (!rtc2_base) {
	339	retval = -EBUSY;
	340	goto err_rtc1_iounmap;
1da177e4 LT	341	}
1da177e4 LT	342
8417eb7a YY	343	rtc = rtc_device_register(rtc_name, &pdev->dev, &vr41xx_rtc_ops, THIS_MODULE);
8417eb7a YY	344	if (IS_ERR(rtc)) {
bd076509 YY	345	retval = PTR_ERR(rtc);
bd076509 YY	346	goto err_iounmap_all;
1da177e4 LT	347	}
	348
	349	spin_lock_irq(&rtc_lock);
	350
	351	rtc1_write(ECMPLREG, 0);
	352	rtc1_write(ECMPMREG, 0);
	353	rtc1_write(ECMPHREG, 0);
	354	rtc1_write(RTCL1LREG, 0);
	355	rtc1_write(RTCL1HREG, 0);
	356
1da177e4 LT	357	spin_unlock_irq(&rtc_lock);
1da177e4 LT	358
bd076509 YY	359	aie_irq = platform_get_irq(pdev, 0);
	360	if (aie_irq < 0 \|\| aie_irq >= NR_IRQS) {
	361	retval = -EBUSY;
	362	goto err_device_unregister;
1da177e4 LT	363	}
1da177e4 LT	364
bd076509 YY	365	retval = request_irq(aie_irq, elapsedtime_interrupt, IRQF_DISABLED,
	366	"elapsed_time", pdev);
	367	if (retval < 0)
	368	goto err_device_unregister;
	369
	370	pie_irq = platform_get_irq(pdev, 1);
	371	if (pie_irq < 0 \|\| pie_irq >= NR_IRQS)
	372	goto err_free_irq;
	373
	374	retval = request_irq(pie_irq, rtclong1_interrupt, IRQF_DISABLED,
	375	"rtclong1", pdev);
	376	if (retval < 0)
	377	goto err_free_irq;
1da177e4	378
8417eb7a YY	379	platform_set_drvdata(pdev, rtc);
8417eb7a YY	380
bd076509 YY	381	disable_irq(aie_irq);
bd076509 YY	382	disable_irq(pie_irq);
1da177e4	383
1da177e4 LT	384	printk(KERN_INFO "rtc: Real Time Clock of NEC VR4100 series\n");
	385
	386	return 0;
bd076509 YY	387
	388	err_free_irq:
	389	free_irq(aie_irq, pdev);
	390
	391	err_device_unregister:
	392	rtc_device_unregister(rtc);
	393
	394	err_iounmap_all:
	395	iounmap(rtc2_base);
	396	rtc2_base = NULL;
	397
	398	err_rtc1_iounmap:
	399	iounmap(rtc1_base);
	400	rtc1_base = NULL;
	401
	402	return retval;
1da177e4 LT	403	}
1da177e4 LT	404
8417eb7a	405	static int __devexit rtc_remove(struct platform_device *pdev)
1da177e4	406	{
8417eb7a	407	struct rtc_device *rtc;
1da177e4	408
8417eb7a	409	rtc = platform_get_drvdata(pdev);
bd076509	410	if (rtc)
8417eb7a YY	411	rtc_device_unregister(rtc);
	412
	413	platform_set_drvdata(pdev, NULL);
1da177e4	414
bd076509 YY	415	free_irq(aie_irq, pdev);
	416	free_irq(pie_irq, pdev);
	417	if (rtc1_base)
1da177e4	418	iounmap(rtc1_base);
bd076509	419	if (rtc2_base)
1da177e4 LT	420	iounmap(rtc2_base);
	421
	422	return 0;
	423	}
	424
8417eb7a	425	static struct platform_driver rtc_platform_driver = {
1da177e4	426	.probe = rtc_probe,
d39b6cfe	427	.remove = __devexit_p(rtc_remove),
3ae5eaec RK	428	.driver = {
3ae5eaec RK	429	.name = rtc_name,
d39b6cfe	430	.owner = THIS_MODULE,
3ae5eaec	431	},
1da177e4 LT	432	};
1da177e4 LT	433
d39b6cfe	434	static int __init vr41xx_rtc_init(void)
1da177e4	435	{
bd076509	436	return platform_driver_register(&rtc_platform_driver);
1da177e4 LT	437	}
1da177e4 LT	438
d39b6cfe	439	static void __exit vr41xx_rtc_exit(void)
1da177e4	440	{
8417eb7a	441	platform_driver_unregister(&rtc_platform_driver);
1da177e4 LT	442	}
	443
	444	module_init(vr41xx_rtc_init);
	445	module_exit(vr41xx_rtc_exit);