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11143c19 SG |
1 | /* |
2 | * Xilinx Zynq Ultrascale+ MPSoC Real Time Clock Driver | |
3 | * | |
4 | * Copyright (C) 2015 Xilinx, Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/delay.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/of.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/rtc.h> | |
27 | ||
28 | /* RTC Registers */ | |
29 | #define RTC_SET_TM_WR 0x00 | |
30 | #define RTC_SET_TM_RD 0x04 | |
31 | #define RTC_CALIB_WR 0x08 | |
32 | #define RTC_CALIB_RD 0x0C | |
33 | #define RTC_CUR_TM 0x10 | |
34 | #define RTC_CUR_TICK 0x14 | |
35 | #define RTC_ALRM 0x18 | |
36 | #define RTC_INT_STS 0x20 | |
37 | #define RTC_INT_MASK 0x24 | |
38 | #define RTC_INT_EN 0x28 | |
39 | #define RTC_INT_DIS 0x2C | |
40 | #define RTC_CTRL 0x40 | |
41 | ||
42 | #define RTC_FR_EN BIT(20) | |
43 | #define RTC_FR_DATSHIFT 16 | |
44 | #define RTC_TICK_MASK 0xFFFF | |
45 | #define RTC_INT_SEC BIT(0) | |
46 | #define RTC_INT_ALRM BIT(1) | |
47 | #define RTC_OSC_EN BIT(24) | |
48 | ||
49 | #define RTC_CALIB_DEF 0x198233 | |
50 | #define RTC_CALIB_MASK 0x1FFFFF | |
51 | #define RTC_SEC_MAX_VAL 0xFFFFFFFF | |
52 | ||
53 | struct xlnx_rtc_dev { | |
54 | struct rtc_device *rtc; | |
55 | void __iomem *reg_base; | |
56 | int alarm_irq; | |
57 | int sec_irq; | |
58 | }; | |
59 | ||
60 | static int xlnx_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
61 | { | |
62 | struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev); | |
63 | unsigned long new_time; | |
64 | ||
65 | new_time = rtc_tm_to_time64(tm); | |
66 | ||
67 | if (new_time > RTC_SEC_MAX_VAL) | |
68 | return -EINVAL; | |
69 | ||
70 | writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR); | |
71 | ||
72 | return 0; | |
73 | } | |
74 | ||
75 | static int xlnx_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
76 | { | |
77 | struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev); | |
78 | ||
79 | rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_CUR_TM), tm); | |
80 | ||
81 | return rtc_valid_tm(tm); | |
82 | } | |
83 | ||
84 | static int xlnx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
85 | { | |
86 | struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev); | |
87 | ||
88 | rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_ALRM), &alrm->time); | |
89 | alrm->enabled = readl(xrtcdev->reg_base + RTC_INT_MASK) & RTC_INT_ALRM; | |
90 | ||
91 | return 0; | |
92 | } | |
93 | ||
94 | static int xlnx_rtc_alarm_irq_enable(struct device *dev, u32 enabled) | |
95 | { | |
96 | struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev); | |
97 | ||
98 | if (enabled) | |
99 | writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_EN); | |
100 | else | |
101 | writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS); | |
102 | ||
103 | return 0; | |
104 | } | |
105 | ||
106 | static int xlnx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | |
107 | { | |
108 | struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev); | |
109 | unsigned long alarm_time; | |
110 | ||
111 | alarm_time = rtc_tm_to_time64(&alrm->time); | |
112 | ||
113 | if (alarm_time > RTC_SEC_MAX_VAL) | |
114 | return -EINVAL; | |
115 | ||
116 | writel((u32)alarm_time, (xrtcdev->reg_base + RTC_ALRM)); | |
117 | ||
118 | xlnx_rtc_alarm_irq_enable(dev, alrm->enabled); | |
119 | ||
120 | return 0; | |
121 | } | |
122 | ||
123 | static void xlnx_init_rtc(struct xlnx_rtc_dev *xrtcdev, u32 calibval) | |
124 | { | |
125 | /* | |
126 | * Based on crystal freq of 33.330 KHz | |
127 | * set the seconds counter and enable, set fractions counter | |
128 | * to default value suggested as per design spec | |
129 | * to correct RTC delay in frequency over period of time. | |
130 | */ | |
131 | calibval &= RTC_CALIB_MASK; | |
132 | writel(calibval, (xrtcdev->reg_base + RTC_CALIB_WR)); | |
133 | } | |
134 | ||
135 | static const struct rtc_class_ops xlnx_rtc_ops = { | |
136 | .set_time = xlnx_rtc_set_time, | |
137 | .read_time = xlnx_rtc_read_time, | |
138 | .read_alarm = xlnx_rtc_read_alarm, | |
139 | .set_alarm = xlnx_rtc_set_alarm, | |
140 | .alarm_irq_enable = xlnx_rtc_alarm_irq_enable, | |
141 | }; | |
142 | ||
143 | static irqreturn_t xlnx_rtc_interrupt(int irq, void *id) | |
144 | { | |
145 | struct xlnx_rtc_dev *xrtcdev = (struct xlnx_rtc_dev *)id; | |
146 | unsigned int status; | |
147 | ||
148 | status = readl(xrtcdev->reg_base + RTC_INT_STS); | |
149 | /* Check if interrupt asserted */ | |
150 | if (!(status & (RTC_INT_SEC | RTC_INT_ALRM))) | |
151 | return IRQ_NONE; | |
152 | ||
153 | /* Clear interrupt */ | |
154 | writel(status, xrtcdev->reg_base + RTC_INT_STS); | |
155 | ||
156 | if (status & RTC_INT_SEC) | |
157 | rtc_update_irq(xrtcdev->rtc, 1, RTC_IRQF | RTC_UF); | |
158 | if (status & RTC_INT_ALRM) | |
159 | rtc_update_irq(xrtcdev->rtc, 1, RTC_IRQF | RTC_AF); | |
160 | ||
161 | return IRQ_HANDLED; | |
162 | } | |
163 | ||
164 | static int xlnx_rtc_probe(struct platform_device *pdev) | |
165 | { | |
166 | struct xlnx_rtc_dev *xrtcdev; | |
167 | struct resource *res; | |
168 | int ret; | |
169 | unsigned int calibvalue; | |
170 | ||
171 | xrtcdev = devm_kzalloc(&pdev->dev, sizeof(*xrtcdev), GFP_KERNEL); | |
172 | if (!xrtcdev) | |
173 | return -ENOMEM; | |
174 | ||
175 | platform_set_drvdata(pdev, xrtcdev); | |
176 | ||
177 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
178 | ||
179 | xrtcdev->reg_base = devm_ioremap_resource(&pdev->dev, res); | |
180 | if (IS_ERR(xrtcdev->reg_base)) | |
181 | return PTR_ERR(xrtcdev->reg_base); | |
182 | ||
183 | xrtcdev->alarm_irq = platform_get_irq_byname(pdev, "alarm"); | |
184 | if (xrtcdev->alarm_irq < 0) { | |
185 | dev_err(&pdev->dev, "no irq resource\n"); | |
186 | return xrtcdev->alarm_irq; | |
187 | } | |
188 | ret = devm_request_irq(&pdev->dev, xrtcdev->alarm_irq, | |
189 | xlnx_rtc_interrupt, 0, | |
190 | dev_name(&pdev->dev), xrtcdev); | |
191 | if (ret) { | |
192 | dev_err(&pdev->dev, "request irq failed\n"); | |
193 | return ret; | |
194 | } | |
195 | ||
196 | xrtcdev->sec_irq = platform_get_irq_byname(pdev, "sec"); | |
197 | if (xrtcdev->sec_irq < 0) { | |
198 | dev_err(&pdev->dev, "no irq resource\n"); | |
199 | return xrtcdev->sec_irq; | |
200 | } | |
201 | ret = devm_request_irq(&pdev->dev, xrtcdev->sec_irq, | |
202 | xlnx_rtc_interrupt, 0, | |
203 | dev_name(&pdev->dev), xrtcdev); | |
204 | if (ret) { | |
205 | dev_err(&pdev->dev, "request irq failed\n"); | |
206 | return ret; | |
207 | } | |
208 | ||
209 | ret = of_property_read_u32(pdev->dev.of_node, "calibration", | |
210 | &calibvalue); | |
211 | if (ret) | |
212 | calibvalue = RTC_CALIB_DEF; | |
213 | ||
214 | xlnx_init_rtc(xrtcdev, calibvalue); | |
215 | ||
216 | device_init_wakeup(&pdev->dev, 1); | |
217 | ||
218 | xrtcdev->rtc = devm_rtc_device_register(&pdev->dev, pdev->name, | |
219 | &xlnx_rtc_ops, THIS_MODULE); | |
220 | return PTR_ERR_OR_ZERO(xrtcdev->rtc); | |
221 | } | |
222 | ||
223 | static int xlnx_rtc_remove(struct platform_device *pdev) | |
224 | { | |
225 | xlnx_rtc_alarm_irq_enable(&pdev->dev, 0); | |
226 | device_init_wakeup(&pdev->dev, 0); | |
227 | ||
228 | return 0; | |
229 | } | |
230 | ||
231 | static int __maybe_unused xlnx_rtc_suspend(struct device *dev) | |
232 | { | |
233 | struct platform_device *pdev = to_platform_device(dev); | |
234 | struct xlnx_rtc_dev *xrtcdev = platform_get_drvdata(pdev); | |
235 | ||
236 | if (device_may_wakeup(&pdev->dev)) | |
237 | enable_irq_wake(xrtcdev->alarm_irq); | |
238 | else | |
239 | xlnx_rtc_alarm_irq_enable(dev, 0); | |
240 | ||
241 | return 0; | |
242 | } | |
243 | ||
244 | static int __maybe_unused xlnx_rtc_resume(struct device *dev) | |
245 | { | |
246 | struct platform_device *pdev = to_platform_device(dev); | |
247 | struct xlnx_rtc_dev *xrtcdev = platform_get_drvdata(pdev); | |
248 | ||
249 | if (device_may_wakeup(&pdev->dev)) | |
250 | disable_irq_wake(xrtcdev->alarm_irq); | |
251 | else | |
252 | xlnx_rtc_alarm_irq_enable(dev, 1); | |
253 | ||
254 | return 0; | |
255 | } | |
256 | ||
257 | static SIMPLE_DEV_PM_OPS(xlnx_rtc_pm_ops, xlnx_rtc_suspend, xlnx_rtc_resume); | |
258 | ||
259 | static const struct of_device_id xlnx_rtc_of_match[] = { | |
260 | {.compatible = "xlnx,zynqmp-rtc" }, | |
261 | { } | |
262 | }; | |
263 | MODULE_DEVICE_TABLE(of, xlnx_rtc_of_match); | |
264 | ||
265 | static struct platform_driver xlnx_rtc_driver = { | |
266 | .probe = xlnx_rtc_probe, | |
267 | .remove = xlnx_rtc_remove, | |
268 | .driver = { | |
269 | .name = KBUILD_MODNAME, | |
270 | .pm = &xlnx_rtc_pm_ops, | |
271 | .of_match_table = xlnx_rtc_of_match, | |
272 | }, | |
273 | }; | |
274 | ||
275 | module_platform_driver(xlnx_rtc_driver); | |
276 | ||
277 | MODULE_DESCRIPTION("Xilinx Zynq MPSoC RTC driver"); | |
278 | MODULE_AUTHOR("Xilinx Inc."); | |
279 | MODULE_LICENSE("GPL v2"); |