[deliverable/linux.git] / drivers / s390 / cio / qdio.h

/*
 * linux/drivers/s390/cio/qdio.h
 *
 * Copyright 2000,2009 IBM Corp.
 * Author(s): Utz Bacher <utz.bacher@de.ibm.com>
 *	      Jan Glauber <jang@linux.vnet.ibm.com>
 */
#ifndef _CIO_QDIO_H
#define _CIO_QDIO_H

#include <asm/page.h>
#include <asm/schid.h>
#include <asm/debug.h>
#include "chsc.h"

#define QDIO_BUSY_BIT_PATIENCE		(100 << 12)	/* 100 microseconds */
#define QDIO_INPUT_THRESHOLD		(500 << 12)	/* 500 microseconds */

/*
 * if an asynchronous HiperSockets queue runs full, the 10 seconds timer wait
 * till next initiative to give transmitted skbs back to the stack is too long.
 * Therefore polling is started in case of multicast queue is filled more
 * than 50 percent.
 */
#define QDIO_IQDIO_POLL_LVL		65	/* HS multicast queue */

enum qdio_irq_states {
	QDIO_IRQ_STATE_INACTIVE,
	QDIO_IRQ_STATE_ESTABLISHED,
	QDIO_IRQ_STATE_ACTIVE,
	QDIO_IRQ_STATE_STOPPED,
	QDIO_IRQ_STATE_CLEANUP,
	QDIO_IRQ_STATE_ERR,
	NR_QDIO_IRQ_STATES,
};

/* used as intparm in do_IO */
#define QDIO_DOING_ESTABLISH	1
#define QDIO_DOING_ACTIVATE	2
#define QDIO_DOING_CLEANUP	3

#define SLSB_STATE_NOT_INIT	0x0
#define SLSB_STATE_EMPTY	0x1
#define SLSB_STATE_PRIMED	0x2
#define SLSB_STATE_HALTED	0xe
#define SLSB_STATE_ERROR	0xf
#define SLSB_TYPE_INPUT		0x0
#define SLSB_TYPE_OUTPUT	0x20
#define SLSB_OWNER_PROG		0x80
#define SLSB_OWNER_CU		0x40

#define SLSB_P_INPUT_NOT_INIT	\
	(SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_NOT_INIT)  /* 0x80 */
#define SLSB_P_INPUT_ACK	\
	(SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_EMPTY)	   /* 0x81 */
#define SLSB_CU_INPUT_EMPTY	\
	(SLSB_OWNER_CU | SLSB_TYPE_INPUT | SLSB_STATE_EMPTY)	   /* 0x41 */
#define SLSB_P_INPUT_PRIMED	\
	(SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_PRIMED)	   /* 0x82 */
#define SLSB_P_INPUT_HALTED	\
	(SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_HALTED)	   /* 0x8e */
#define SLSB_P_INPUT_ERROR	\
	(SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_ERROR)	   /* 0x8f */
#define SLSB_P_OUTPUT_NOT_INIT	\
	(SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_NOT_INIT) /* 0xa0 */
#define SLSB_P_OUTPUT_EMPTY	\
	(SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_EMPTY)	   /* 0xa1 */
#define SLSB_CU_OUTPUT_PRIMED	\
	(SLSB_OWNER_CU | SLSB_TYPE_OUTPUT | SLSB_STATE_PRIMED)	   /* 0x62 */
#define SLSB_P_OUTPUT_HALTED	\
	(SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_HALTED)   /* 0xae */
#define SLSB_P_OUTPUT_ERROR	\
	(SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_ERROR)	   /* 0xaf */

#define SLSB_ERROR_DURING_LOOKUP  0xff

/* additional CIWs returned by extended Sense-ID */
#define CIW_TYPE_EQUEUE			0x3 /* establish QDIO queues */
#define CIW_TYPE_AQUEUE			0x4 /* activate QDIO queues */

/* flags for st qdio sch data */
#define CHSC_FLAG_QDIO_CAPABILITY	0x80
#define CHSC_FLAG_VALIDITY		0x40

/* qdio adapter-characteristics-1 flag */
#define AC1_SIGA_INPUT_NEEDED		0x40	/* process input queues */
#define AC1_SIGA_OUTPUT_NEEDED		0x20	/* process output queues */
#define AC1_SIGA_SYNC_NEEDED		0x10	/* ask hypervisor to sync */
#define AC1_AUTOMATIC_SYNC_ON_THININT	0x08	/* set by hypervisor */
#define AC1_AUTOMATIC_SYNC_ON_OUT_PCI	0x04	/* set by hypervisor */
#define AC1_SC_QEBSM_AVAILABLE		0x02	/* available for subchannel */
#define AC1_SC_QEBSM_ENABLED		0x01	/* enabled for subchannel */

#ifdef CONFIG_64BIT
static inline int do_sqbs(u64 token, unsigned char state, int queue,
			  int *start, int *count)
{
	register unsigned long _ccq asm ("0") = *count;
	register unsigned long _token asm ("1") = token;
	unsigned long _queuestart = ((unsigned long)queue << 32) | *start;

	asm volatile(
		"	.insn	rsy,0xeb000000008A,%1,0,0(%2)"
		: "+d" (_ccq), "+d" (_queuestart)
		: "d" ((unsigned long)state), "d" (_token)
		: "memory", "cc");
	*count = _ccq & 0xff;
	*start = _queuestart & 0xff;

	return (_ccq >> 32) & 0xff;
}

static inline int do_eqbs(u64 token, unsigned char *state, int queue,
			  int *start, int *count, int ack)
{
	register unsigned long _ccq asm ("0") = *count;
	register unsigned long _token asm ("1") = token;
	unsigned long _queuestart = ((unsigned long)queue << 32) | *start;
	unsigned long _state = (unsigned long)ack << 63;

	asm volatile(
		"	.insn	rrf,0xB99c0000,%1,%2,0,0"
		: "+d" (_ccq), "+d" (_queuestart), "+d" (_state)
		: "d" (_token)
		: "memory", "cc");
	*count = _ccq & 0xff;
	*start = _queuestart & 0xff;
	*state = _state & 0xff;

	return (_ccq >> 32) & 0xff;
}
#else
static inline int do_sqbs(u64 token, unsigned char state, int queue,
			  int *start, int *count) { return 0; }
static inline int do_eqbs(u64 token, unsigned char *state, int queue,
			  int *start, int *count, int ack) { return 0; }
#endif /* CONFIG_64BIT */

struct qdio_irq;

struct siga_flag {
	u8 input:1;
	u8 output:1;
	u8 sync:1;
	u8 no_sync_ti:1;
	u8 no_sync_out_ti:1;
	u8 no_sync_out_pci:1;
	u8:2;
} __attribute__ ((packed));

struct chsc_ssqd_area {
	struct chsc_header request;
	u16:10;
	u8 ssid:2;
	u8 fmt:4;
	u16 first_sch;
	u16:16;
	u16 last_sch;
	u32:32;
	struct chsc_header response;
	u32:32;
	struct qdio_ssqd_desc qdio_ssqd;
} __attribute__ ((packed));

struct scssc_area {
	struct chsc_header request;
	u16 operation_code;
	u16:16;
	u32:32;
	u32:32;
	u64 summary_indicator_addr;
	u64 subchannel_indicator_addr;
	u32 ks:4;
	u32 kc:4;
	u32:21;
	u32 isc:3;
	u32 word_with_d_bit;
	u32:32;
	struct subchannel_id schid;
	u32 reserved[1004];
	struct chsc_header response;
	u32:32;
} __attribute__ ((packed));

struct qdio_dev_perf_stat {
	unsigned int adapter_int;
	unsigned int qdio_int;
	unsigned int pci_request_int;

	unsigned int tasklet_inbound;
	unsigned int tasklet_inbound_resched;
	unsigned int tasklet_inbound_resched2;
	unsigned int tasklet_outbound;

	unsigned int siga_read;
	unsigned int siga_write;
	unsigned int siga_sync;

	unsigned int inbound_call;
	unsigned int inbound_handler;
	unsigned int stop_polling;
	unsigned int inbound_queue_full;
	unsigned int outbound_call;
	unsigned int outbound_handler;
	unsigned int fast_requeue;
	unsigned int target_full;
	unsigned int eqbs;
	unsigned int eqbs_partial;
	unsigned int sqbs;
	unsigned int sqbs_partial;
	unsigned int int_discarded;
} ____cacheline_aligned;

struct qdio_queue_perf_stat {
	/*
	 * Sorted into order-2 buckets: 1, 2-3, 4-7, ... 64-127, 128.
	 * Since max. 127 SBALs are scanned reuse entry for 128 as queue full
	 * aka 127 SBALs found.
	 */
	unsigned int nr_sbals[8];
	unsigned int nr_sbal_error;
	unsigned int nr_sbal_nop;
	unsigned int nr_sbal_total;
};

enum qdio_queue_irq_states {
	QDIO_QUEUE_IRQS_DISABLED,
};

struct qdio_input_q {
	/* input buffer acknowledgement flag */
	int polling;
	/* first ACK'ed buffer */
	int ack_start;
	/* how much sbals are acknowledged with qebsm */
	int ack_count;
	/* last time of noticing incoming data */
	u64 timestamp;
	/* upper-layer polling flag */
	unsigned long queue_irq_state;
	/* callback to start upper-layer polling */
	void (*queue_start_poll) (struct ccw_device *, int, unsigned long);
};

struct qdio_output_q {
	/* PCIs are enabled for the queue */
	int pci_out_enabled;
	/* IQDIO: output multiple buffers (enhanced SIGA) */
	int use_enh_siga;
	/* timer to check for more outbound work */
	struct timer_list timer;
	/* used SBALs before tasklet schedule */
	int scan_threshold;
};

/*
 * Note on cache alignment: grouped slsb and write mostly data at the beginning
 * sbal[] is read-only and starts on a new cacheline followed by read mostly.
 */
struct qdio_q {
	struct slsb slsb;

	union {
		struct qdio_input_q in;
		struct qdio_output_q out;
	} u;

	/*
	 * inbound: next buffer the program should check for
	 * outbound: next buffer to check if adapter processed it
	 */
	int first_to_check;

	/* first_to_check of the last time */
	int last_move;

	/* beginning position for calling the program */
	int first_to_kick;

	/* number of buffers in use by the adapter */
	atomic_t nr_buf_used;

	/* error condition during a data transfer */
	unsigned int qdio_error;

	struct tasklet_struct tasklet;
	struct qdio_queue_perf_stat q_stats;

	struct qdio_buffer *sbal[QDIO_MAX_BUFFERS_PER_Q] ____cacheline_aligned;

	/* queue number */
	int nr;

	/* bitmask of queue number */
	int mask;

	/* input or output queue */
	int is_input_q;

	/* list of thinint input queues */
	struct list_head entry;

	/* upper-layer program handler */
	qdio_handler_t (*handler);

	struct dentry *debugfs_q;
	struct qdio_irq *irq_ptr;
	struct sl *sl;
	/*
	 * A page is allocated under this pointer and used for slib and sl.
	 * slib is 2048 bytes big and sl points to offset PAGE_SIZE / 2.
	 */
	struct slib *slib;
} __attribute__ ((aligned(256)));

struct qdio_irq {
	struct qib qib;
	u32 *dsci;		/* address of device state change indicator */
	struct ccw_device *cdev;
	struct dentry *debugfs_dev;
	struct dentry *debugfs_perf;

	unsigned long int_parm;
	struct subchannel_id schid;
	unsigned long sch_token;	/* QEBSM facility */

	enum qdio_irq_states state;

	struct siga_flag siga_flag;	/* siga sync information from qdioac */

	int nr_input_qs;
	int nr_output_qs;

	struct ccw1 ccw;
	struct ciw equeue;
	struct ciw aqueue;

	struct qdio_ssqd_desc ssqd_desc;
	void (*orig_handler) (struct ccw_device *, unsigned long, struct irb *);

	int perf_stat_enabled;

	struct qdr *qdr;
	unsigned long chsc_page;

	struct qdio_q *input_qs[QDIO_MAX_QUEUES_PER_IRQ];
	struct qdio_q *output_qs[QDIO_MAX_QUEUES_PER_IRQ];

	debug_info_t *debug_area;
	struct mutex setup_mutex;
	struct qdio_dev_perf_stat perf_stat;
};

/* helper functions */
#define queue_type(q)	q->irq_ptr->qib.qfmt
#define SCH_NO(q)	(q->irq_ptr->schid.sch_no)

#define is_thinint_irq(irq) \
	(irq->qib.qfmt == QDIO_IQDIO_QFMT || \
	 css_general_characteristics.aif_osa)

#define qperf(__qdev, __attr)	((__qdev)->perf_stat.(__attr))

#define qperf_inc(__q, __attr)						\
({									\
	struct qdio_irq *qdev = (__q)->irq_ptr;				\
	if (qdev->perf_stat_enabled)					\
		(qdev->perf_stat.__attr)++;				\
})

static inline void account_sbals_error(struct qdio_q *q, int count)
{
	q->q_stats.nr_sbal_error += count;
	q->q_stats.nr_sbal_total += count;
}

/* the highest iqdio queue is used for multicast */
static inline int multicast_outbound(struct qdio_q *q)
{
	return (q->irq_ptr->nr_output_qs > 1) &&
	       (q->nr == q->irq_ptr->nr_output_qs - 1);
}

#define pci_out_supported(q) \
	(q->irq_ptr->qib.ac & QIB_AC_OUTBOUND_PCI_SUPPORTED)
#define is_qebsm(q)			(q->irq_ptr->sch_token != 0)

#define need_siga_sync_thinint(q)	(!q->irq_ptr->siga_flag.no_sync_ti)
#define need_siga_sync_out_thinint(q)	(!q->irq_ptr->siga_flag.no_sync_out_ti)
#define need_siga_in(q)			(q->irq_ptr->siga_flag.input)
#define need_siga_out(q)		(q->irq_ptr->siga_flag.output)
#define need_siga_sync(q)		(q->irq_ptr->siga_flag.sync)
#define siga_syncs_out_pci(q)		(q->irq_ptr->siga_flag.no_sync_out_pci)

#define for_each_input_queue(irq_ptr, q, i)	\
	for (i = 0, q = irq_ptr->input_qs[0];	\
		i < irq_ptr->nr_input_qs;	\
		q = irq_ptr->input_qs[++i])
#define for_each_output_queue(irq_ptr, q, i)	\
	for (i = 0, q = irq_ptr->output_qs[0];	\
		i < irq_ptr->nr_output_qs;	\
		q = irq_ptr->output_qs[++i])

#define prev_buf(bufnr)	\
	((bufnr + QDIO_MAX_BUFFERS_MASK) & QDIO_MAX_BUFFERS_MASK)
#define next_buf(bufnr)	\
	((bufnr + 1) & QDIO_MAX_BUFFERS_MASK)
#define add_buf(bufnr, inc) \
	((bufnr + inc) & QDIO_MAX_BUFFERS_MASK)
#define sub_buf(bufnr, dec) \
	((bufnr - dec) & QDIO_MAX_BUFFERS_MASK)

#define queue_irqs_enabled(q)			\
	(test_bit(QDIO_QUEUE_IRQS_DISABLED, &q->u.in.queue_irq_state) == 0)
#define queue_irqs_disabled(q)			\
	(test_bit(QDIO_QUEUE_IRQS_DISABLED, &q->u.in.queue_irq_state) != 0)

#define TIQDIO_SHARED_IND		63

/* device state change indicators */
struct indicator_t {
	u32 ind;	/* u32 because of compare-and-swap performance */
	atomic_t count; /* use count, 0 or 1 for non-shared indicators */
};

extern struct indicator_t *q_indicators;

static inline int shared_ind(u32 *dsci)
{
	return dsci == &q_indicators[TIQDIO_SHARED_IND].ind;
}

/* prototypes for thin interrupt */
void qdio_setup_thinint(struct qdio_irq *irq_ptr);
int qdio_establish_thinint(struct qdio_irq *irq_ptr);
void qdio_shutdown_thinint(struct qdio_irq *irq_ptr);
void tiqdio_add_input_queues(struct qdio_irq *irq_ptr);
void tiqdio_remove_input_queues(struct qdio_irq *irq_ptr);
void tiqdio_inbound_processing(unsigned long q);
int tiqdio_allocate_memory(void);
void tiqdio_free_memory(void);
int tiqdio_register_thinints(void);
void tiqdio_unregister_thinints(void);

/* prototypes for setup */
void qdio_inbound_processing(unsigned long data);
void qdio_outbound_processing(unsigned long data);
void qdio_outbound_timer(unsigned long data);
void qdio_int_handler(struct ccw_device *cdev, unsigned long intparm,
		      struct irb *irb);
int qdio_allocate_qs(struct qdio_irq *irq_ptr, int nr_input_qs,
		     int nr_output_qs);
void qdio_setup_ssqd_info(struct qdio_irq *irq_ptr);
int qdio_setup_get_ssqd(struct qdio_irq *irq_ptr,
			struct subchannel_id *schid,
			struct qdio_ssqd_desc *data);
int qdio_setup_irq(struct qdio_initialize *init_data);
void qdio_print_subchannel_info(struct qdio_irq *irq_ptr,
				struct ccw_device *cdev);
void qdio_release_memory(struct qdio_irq *irq_ptr);
int qdio_setup_create_sysfs(struct ccw_device *cdev);
void qdio_setup_destroy_sysfs(struct ccw_device *cdev);
int qdio_setup_init(void);
void qdio_setup_exit(void);

int debug_get_buf_state(struct qdio_q *q, unsigned int bufnr,
			unsigned char *state);
#endif /* _CIO_QDIO_H */
Commit	Line	Data
779e6e1c JG	1	/*
	2	* linux/drivers/s390/cio/qdio.h
	3	*
3f09bb89	4	* Copyright 2000,2009 IBM Corp.
779e6e1c JG	5	* Author(s): Utz Bacher <utz.bacher@de.ibm.com>
	6	* Jan Glauber <jang@linux.vnet.ibm.com>
	7	*/
1da177e4 LT	8	#ifndef _CIO_QDIO_H
	9	#define _CIO_QDIO_H
	10
0b642ede	11	#include <asm/page.h>
9d92a7e1	12	#include <asm/schid.h>
22f99347	13	#include <asm/debug.h>
779e6e1c	14	#include "chsc.h"
a8237fc4	15
3a601bfe JG	16	#define QDIO_BUSY_BIT_PATIENCE (100 << 12) /* 100 microseconds */
3a601bfe JG	17	#define QDIO_INPUT_THRESHOLD (500 << 12) /* 500 microseconds */
1da177e4	18
4bcb3a37 UB	19	/*
	20	* if an asynchronous HiperSockets queue runs full, the 10 seconds timer wait
	21	* till next initiative to give transmitted skbs back to the stack is too long.
	22	* Therefore polling is started in case of multicast queue is filled more
	23	* than 50 percent.
	24	*/
	25	#define QDIO_IQDIO_POLL_LVL 65 /* HS multicast queue */
	26
1da177e4 LT	27	enum qdio_irq_states {
	28	QDIO_IRQ_STATE_INACTIVE,
	29	QDIO_IRQ_STATE_ESTABLISHED,
	30	QDIO_IRQ_STATE_ACTIVE,
	31	QDIO_IRQ_STATE_STOPPED,
	32	QDIO_IRQ_STATE_CLEANUP,
	33	QDIO_IRQ_STATE_ERR,
	34	NR_QDIO_IRQ_STATES,
	35	};
	36
779e6e1c JG	37	/* used as intparm in do_IO */
	38	#define QDIO_DOING_ESTABLISH 1
	39	#define QDIO_DOING_ACTIVATE 2
	40	#define QDIO_DOING_CLEANUP 3
	41
	42	#define SLSB_STATE_NOT_INIT 0x0
	43	#define SLSB_STATE_EMPTY 0x1
	44	#define SLSB_STATE_PRIMED 0x2
	45	#define SLSB_STATE_HALTED 0xe
	46	#define SLSB_STATE_ERROR 0xf
	47	#define SLSB_TYPE_INPUT 0x0
	48	#define SLSB_TYPE_OUTPUT 0x20
	49	#define SLSB_OWNER_PROG 0x80
	50	#define SLSB_OWNER_CU 0x40
	51
	52	#define SLSB_P_INPUT_NOT_INIT \
	53	(SLSB_OWNER_PROG \| SLSB_TYPE_INPUT \| SLSB_STATE_NOT_INIT) /* 0x80 */
	54	#define SLSB_P_INPUT_ACK \
	55	(SLSB_OWNER_PROG \| SLSB_TYPE_INPUT \| SLSB_STATE_EMPTY) /* 0x81 */
	56	#define SLSB_CU_INPUT_EMPTY \
	57	(SLSB_OWNER_CU \| SLSB_TYPE_INPUT \| SLSB_STATE_EMPTY) /* 0x41 */
	58	#define SLSB_P_INPUT_PRIMED \
	59	(SLSB_OWNER_PROG \| SLSB_TYPE_INPUT \| SLSB_STATE_PRIMED) /* 0x82 */
	60	#define SLSB_P_INPUT_HALTED \
	61	(SLSB_OWNER_PROG \| SLSB_TYPE_INPUT \| SLSB_STATE_HALTED) /* 0x8e */
	62	#define SLSB_P_INPUT_ERROR \
	63	(SLSB_OWNER_PROG \| SLSB_TYPE_INPUT \| SLSB_STATE_ERROR) /* 0x8f */
	64	#define SLSB_P_OUTPUT_NOT_INIT \
	65	(SLSB_OWNER_PROG \| SLSB_TYPE_OUTPUT \| SLSB_STATE_NOT_INIT) /* 0xa0 */
	66	#define SLSB_P_OUTPUT_EMPTY \
	67	(SLSB_OWNER_PROG \| SLSB_TYPE_OUTPUT \| SLSB_STATE_EMPTY) /* 0xa1 */
	68	#define SLSB_CU_OUTPUT_PRIMED \
	69	(SLSB_OWNER_CU \| SLSB_TYPE_OUTPUT \| SLSB_STATE_PRIMED) /* 0x62 */
	70	#define SLSB_P_OUTPUT_HALTED \
	71	(SLSB_OWNER_PROG \| SLSB_TYPE_OUTPUT \| SLSB_STATE_HALTED) /* 0xae */
	72	#define SLSB_P_OUTPUT_ERROR \
	73	(SLSB_OWNER_PROG \| SLSB_TYPE_OUTPUT \| SLSB_STATE_ERROR) /* 0xaf */
	74
	75	#define SLSB_ERROR_DURING_LOOKUP 0xff
	76
	77	/* additional CIWs returned by extended Sense-ID */
	78	#define CIW_TYPE_EQUEUE 0x3 /* establish QDIO queues */
	79	#define CIW_TYPE_AQUEUE 0x4 /* activate QDIO queues */
1da177e4	80
779e6e1c JG	81	/* flags for st qdio sch data */
	82	#define CHSC_FLAG_QDIO_CAPABILITY 0x80
	83	#define CHSC_FLAG_VALIDITY 0x40
	84
	85	/* qdio adapter-characteristics-1 flag */
	86	#define AC1_SIGA_INPUT_NEEDED 0x40 /* process input queues */
	87	#define AC1_SIGA_OUTPUT_NEEDED 0x20 /* process output queues */
	88	#define AC1_SIGA_SYNC_NEEDED 0x10 /* ask hypervisor to sync */
	89	#define AC1_AUTOMATIC_SYNC_ON_THININT 0x08 /* set by hypervisor */
	90	#define AC1_AUTOMATIC_SYNC_ON_OUT_PCI 0x04 /* set by hypervisor */
	91	#define AC1_SC_QEBSM_AVAILABLE 0x02 /* available for subchannel */
	92	#define AC1_SC_QEBSM_ENABLED 0x01 /* enabled for subchannel */
1da177e4	93
779e6e1c JG	94	#ifdef CONFIG_64BIT
	95	static inline int do_sqbs(u64 token, unsigned char state, int queue,
	96	int start, int count)
	97	{
	98	register unsigned long _ccq asm ("0") = *count;
	99	register unsigned long _token asm ("1") = token;
	100	unsigned long _queuestart = ((unsigned long)queue << 32) \| *start;
1da177e4	101
779e6e1c JG	102	asm volatile(
	103	" .insn rsy,0xeb000000008A,%1,0,0(%2)"
	104	: "+d" (_ccq), "+d" (_queuestart)
	105	: "d" ((unsigned long)state), "d" (_token)
	106	: "memory", "cc");
	107	*count = _ccq & 0xff;
	108	*start = _queuestart & 0xff;
8129ee16	109
779e6e1c	110	return (_ccq >> 32) & 0xff;
8129ee16 FP	111	}
8129ee16 FP	112
779e6e1c	113	static inline int do_eqbs(u64 token, unsigned char *state, int queue,
50f769df	114	int start, int count, int ack)
8129ee16	115	{
8129ee16	116	register unsigned long _ccq asm ("0") = *count;
779e6e1c	117	register unsigned long _token asm ("1") = token;
8129ee16	118	unsigned long _queuestart = ((unsigned long)queue << 32) \| *start;
50f769df	119	unsigned long _state = (unsigned long)ack << 63;
8129ee16	120
94c12cc7 MS	121	asm volatile(
	122	" .insn rrf,0xB99c0000,%1,%2,0,0"
	123	: "+d" (_ccq), "+d" (_queuestart), "+d" (_state)
779e6e1c JG	124	: "d" (_token)
779e6e1c JG	125	: "memory", "cc");
8129ee16 FP	126	*count = _ccq & 0xff;
	127	*start = _queuestart & 0xff;
	128	*state = _state & 0xff;
	129
	130	return (_ccq >> 32) & 0xff;
1da177e4	131	}
779e6e1c JG	132	#else
	133	static inline int do_sqbs(u64 token, unsigned char state, int queue,
	134	int start, int count) { return 0; }
	135	static inline int do_eqbs(u64 token, unsigned char *state, int queue,
50f769df	136	int start, int count, int ack) { return 0; }
779e6e1c	137	#endif /* CONFIG_64BIT */
1da177e4	138
779e6e1c	139	struct qdio_irq;
1da177e4	140
779e6e1c JG	141	struct siga_flag {
	142	u8 input:1;
	143	u8 output:1;
	144	u8 sync:1;
	145	u8 no_sync_ti:1;
	146	u8 no_sync_out_ti:1;
	147	u8 no_sync_out_pci:1;
	148	u8:2;
	149	} __attribute__ ((packed));
1da177e4	150
779e6e1c	151	struct chsc_ssqd_area {
e1776856	152	struct chsc_header request;
779e6e1c JG	153	u16:10;
	154	u8 ssid:2;
	155	u8 fmt:4;
e1776856	156	u16 first_sch;
779e6e1c	157	u16:16;
e1776856	158	u16 last_sch;
779e6e1c	159	u32:32;
e1776856	160	struct chsc_header response;
779e6e1c JG	161	u32:32;
	162	struct qdio_ssqd_desc qdio_ssqd;
	163	} __attribute__ ((packed));
e1776856	164
779e6e1c JG	165	struct scssc_area {
	166	struct chsc_header request;
	167	u16 operation_code;
	168	u16:16;
	169	u32:32;
	170	u32:32;
	171	u64 summary_indicator_addr;
	172	u64 subchannel_indicator_addr;
	173	u32 ks:4;
	174	u32 kc:4;
	175	u32:21;
	176	u32 isc:3;
	177	u32 word_with_d_bit;
	178	u32:32;
	179	struct subchannel_id schid;
	180	u32 reserved[1004];
	181	struct chsc_header response;
	182	u32:32;
	183	} __attribute__ ((packed));
	184
6486cda6 JG	185	struct qdio_dev_perf_stat {
	186	unsigned int adapter_int;
	187	unsigned int qdio_int;
	188	unsigned int pci_request_int;
	189
	190	unsigned int tasklet_inbound;
	191	unsigned int tasklet_inbound_resched;
	192	unsigned int tasklet_inbound_resched2;
	193	unsigned int tasklet_outbound;
	194
	195	unsigned int siga_read;
	196	unsigned int siga_write;
	197	unsigned int siga_sync;
	198
	199	unsigned int inbound_call;
	200	unsigned int inbound_handler;
	201	unsigned int stop_polling;
	202	unsigned int inbound_queue_full;
	203	unsigned int outbound_call;
	204	unsigned int outbound_handler;
	205	unsigned int fast_requeue;
	206	unsigned int target_full;
	207	unsigned int eqbs;
	208	unsigned int eqbs_partial;
	209	unsigned int sqbs;
	210	unsigned int sqbs_partial;
d36deae7	211	unsigned int int_discarded;
432ac5e0	212	} ____cacheline_aligned;
6486cda6	213
d307297f JG	214	struct qdio_queue_perf_stat {
	215	/*
	216	* Sorted into order-2 buckets: 1, 2-3, 4-7, ... 64-127, 128.
	217	* Since max. 127 SBALs are scanned reuse entry for 128 as queue full
	218	* aka 127 SBALs found.
	219	*/
	220	unsigned int nr_sbals[8];
	221	unsigned int nr_sbal_error;
	222	unsigned int nr_sbal_nop;
	223	unsigned int nr_sbal_total;
	224	};
	225
d36deae7 JG	226	enum qdio_queue_irq_states {
	227	QDIO_QUEUE_IRQS_DISABLED,
	228	};
	229
779e6e1c JG	230	struct qdio_input_q {
	231	/* input buffer acknowledgement flag */
	232	int polling;
e85dea0e JG	233	/* first ACK'ed buffer */
e85dea0e JG	234	int ack_start;
50f769df JG	235	/* how much sbals are acknowledged with qebsm */
50f769df JG	236	int ack_count;
779e6e1c JG	237	/* last time of noticing incoming data */
779e6e1c JG	238	u64 timestamp;
d36deae7 JG	239	/* upper-layer polling flag */
	240	unsigned long queue_irq_state;
	241	/* callback to start upper-layer polling */
	242	void (queue_start_poll) (struct ccw_device , int, unsigned long);
1da177e4	243	};
1da177e4	244
779e6e1c	245	struct qdio_output_q {
779e6e1c JG	246	/* PCIs are enabled for the queue */
779e6e1c JG	247	int pci_out_enabled;
7a0f4755 KDW	248	/* IQDIO: output multiple buffers (enhanced SIGA) */
7a0f4755 KDW	249	int use_enh_siga;
779e6e1c JG	250	/* timer to check for more outbound work */
779e6e1c JG	251	struct timer_list timer;
3d6c76ff JG	252	/* used SBALs before tasklet schedule */
3d6c76ff JG	253	int scan_threshold;
779e6e1c	254	};
1da177e4	255
d307297f JG	256	/*
	257	* Note on cache alignment: grouped slsb and write mostly data at the beginning
	258	* sbal[] is read-only and starts on a new cacheline followed by read mostly.
	259	*/
1da177e4	260	struct qdio_q {
779e6e1c	261	struct slsb slsb;
d307297f	262
779e6e1c JG	263	union {
	264	struct qdio_input_q in;
	265	struct qdio_output_q out;
	266	} u;
1da177e4	267
779e6e1c JG	268	/*
779e6e1c JG	269	* inbound: next buffer the program should check for
d307297f	270	* outbound: next buffer to check if adapter processed it
779e6e1c JG	271	*/
779e6e1c JG	272	int first_to_check;
1da177e4	273
779e6e1c	274	/* first_to_check of the last time */
e85dea0e	275	int last_move;
1da177e4	276
779e6e1c JG	277	/* beginning position for calling the program */
779e6e1c JG	278	int first_to_kick;
1da177e4	279
779e6e1c JG	280	/* number of buffers in use by the adapter */
779e6e1c JG	281	atomic_t nr_buf_used;
1da177e4	282
779e6e1c	283	/* error condition during a data transfer */
1da177e4	284	unsigned int qdio_error;
1da177e4	285
d307297f JG	286	struct tasklet_struct tasklet;
	287	struct qdio_queue_perf_stat q_stats;
	288
	289	struct qdio_buffer *sbal[QDIO_MAX_BUFFERS_PER_Q] ____cacheline_aligned;
	290
	291	/* queue number */
	292	int nr;
	293
	294	/* bitmask of queue number */
	295	int mask;
	296
	297	/* input or output queue */
	298	int is_input_q;
	299
	300	/* list of thinint input queues */
	301	struct list_head entry;
	302
	303	/* upper-layer program handler */
	304	qdio_handler_t (*handler);
779e6e1c	305
d307297f JG	306	struct dentry *debugfs_q;
	307	struct qdio_irq *irq_ptr;
	308	struct sl *sl;
779e6e1c	309	/*
5382fe11 JG	310	* A page is allocated under this pointer and used for slib and sl.
5382fe11 JG	311	* slib is 2048 bytes big and sl points to offset PAGE_SIZE / 2.
779e6e1c JG	312	*/
779e6e1c JG	313	struct slib *slib;
1da177e4 LT	314	} __attribute__ ((aligned(256)));
	315
	316	struct qdio_irq {
779e6e1c JG	317	struct qib qib;
	318	u32 dsci; / address of device state change indicator */
	319	struct ccw_device *cdev;
3f09bb89	320	struct dentry *debugfs_dev;
6486cda6	321	struct dentry *debugfs_perf;
1da177e4 LT	322
1da177e4 LT	323	unsigned long int_parm;
a8237fc4	324	struct subchannel_id schid;
779e6e1c	325	unsigned long sch_token; /* QEBSM facility */
8129ee16	326
1da177e4 LT	327	enum qdio_irq_states state;
1da177e4 LT	328
779e6e1c	329	struct siga_flag siga_flag; /* siga sync information from qdioac */
1da177e4	330
779e6e1c JG	331	int nr_input_qs;
779e6e1c JG	332	int nr_output_qs;
1da177e4 LT	333
1da177e4 LT	334	struct ccw1 ccw;
1da177e4 LT	335	struct ciw equeue;
	336	struct ciw aqueue;
	337
779e6e1c	338	struct qdio_ssqd_desc ssqd_desc;
779e6e1c	339	void (orig_handler) (struct ccw_device , unsigned long, struct irb *);
1da177e4	340
6486cda6	341	int perf_stat_enabled;
432ac5e0	342
1da177e4	343	struct qdr *qdr;
779e6e1c JG	344	unsigned long chsc_page;
779e6e1c JG	345
1da177e4 LT	346	struct qdio_q *input_qs[QDIO_MAX_QUEUES_PER_IRQ];
1da177e4 LT	347	struct qdio_q *output_qs[QDIO_MAX_QUEUES_PER_IRQ];
779e6e1c	348
22f99347	349	debug_info_t *debug_area;
779e6e1c	350	struct mutex setup_mutex;
432ac5e0	351	struct qdio_dev_perf_stat perf_stat;
1da177e4	352	};
779e6e1c JG	353
	354	/* helper functions */
	355	#define queue_type(q) q->irq_ptr->qib.qfmt
22f99347	356	#define SCH_NO(q) (q->irq_ptr->schid.sch_no)
779e6e1c JG	357
	358	#define is_thinint_irq(irq) \
	359	(irq->qib.qfmt == QDIO_IQDIO_QFMT \|\| \
	360	css_general_characteristics.aif_osa)
	361
d307297f JG	362	#define qperf(__qdev, __attr) ((__qdev)->perf_stat.(__attr))
	363
	364	#define qperf_inc(__q, __attr) \
	365	({ \
	366	struct qdio_irq *qdev = (__q)->irq_ptr; \
	367	if (qdev->perf_stat_enabled) \
	368	(qdev->perf_stat.__attr)++; \
	369	})
	370
	371	static inline void account_sbals_error(struct qdio_q *q, int count)
	372	{
	373	q->q_stats.nr_sbal_error += count;
	374	q->q_stats.nr_sbal_total += count;
	375	}
6486cda6	376
779e6e1c JG	377	/* the highest iqdio queue is used for multicast */
	378	static inline int multicast_outbound(struct qdio_q *q)
	379	{
	380	return (q->irq_ptr->nr_output_qs > 1) &&
	381	(q->nr == q->irq_ptr->nr_output_qs - 1);
	382	}
	383
779e6e1c JG	384	#define pci_out_supported(q) \
	385	(q->irq_ptr->qib.ac & QIB_AC_OUTBOUND_PCI_SUPPORTED)
	386	#define is_qebsm(q) (q->irq_ptr->sch_token != 0)
	387
	388	#define need_siga_sync_thinint(q) (!q->irq_ptr->siga_flag.no_sync_ti)
	389	#define need_siga_sync_out_thinint(q) (!q->irq_ptr->siga_flag.no_sync_out_ti)
	390	#define need_siga_in(q) (q->irq_ptr->siga_flag.input)
	391	#define need_siga_out(q) (q->irq_ptr->siga_flag.output)
	392	#define need_siga_sync(q) (q->irq_ptr->siga_flag.sync)
	393	#define siga_syncs_out_pci(q) (q->irq_ptr->siga_flag.no_sync_out_pci)
	394
	395	#define for_each_input_queue(irq_ptr, q, i) \
	396	for (i = 0, q = irq_ptr->input_qs[0]; \
	397	i < irq_ptr->nr_input_qs; \
	398	q = irq_ptr->input_qs[++i])
	399	#define for_each_output_queue(irq_ptr, q, i) \
	400	for (i = 0, q = irq_ptr->output_qs[0]; \
	401	i < irq_ptr->nr_output_qs; \
	402	q = irq_ptr->output_qs[++i])
	403
	404	#define prev_buf(bufnr) \
	405	((bufnr + QDIO_MAX_BUFFERS_MASK) & QDIO_MAX_BUFFERS_MASK)
	406	#define next_buf(bufnr) \
	407	((bufnr + 1) & QDIO_MAX_BUFFERS_MASK)
	408	#define add_buf(bufnr, inc) \
	409	((bufnr + inc) & QDIO_MAX_BUFFERS_MASK)
50f769df JG	410	#define sub_buf(bufnr, dec) \
50f769df JG	411	((bufnr - dec) & QDIO_MAX_BUFFERS_MASK)
779e6e1c	412
d36deae7 JG	413	#define queue_irqs_enabled(q) \
	414	(test_bit(QDIO_QUEUE_IRQS_DISABLED, &q->u.in.queue_irq_state) == 0)
	415	#define queue_irqs_disabled(q) \
	416	(test_bit(QDIO_QUEUE_IRQS_DISABLED, &q->u.in.queue_irq_state) != 0)
	417
	418	#define TIQDIO_SHARED_IND 63
	419
	420	/* device state change indicators */
	421	struct indicator_t {
	422	u32 ind; /* u32 because of compare-and-swap performance */
	423	atomic_t count; /* use count, 0 or 1 for non-shared indicators */
	424	};
	425
	426	extern struct indicator_t *q_indicators;
	427
4f325184	428	static inline int shared_ind(u32 *dsci)
d36deae7	429	{
4f325184	430	return dsci == &q_indicators[TIQDIO_SHARED_IND].ind;
d36deae7 JG	431	}
d36deae7 JG	432
779e6e1c	433	/* prototypes for thin interrupt */
779e6e1c JG	434	void qdio_setup_thinint(struct qdio_irq *irq_ptr);
	435	int qdio_establish_thinint(struct qdio_irq *irq_ptr);
	436	void qdio_shutdown_thinint(struct qdio_irq *irq_ptr);
	437	void tiqdio_add_input_queues(struct qdio_irq *irq_ptr);
	438	void tiqdio_remove_input_queues(struct qdio_irq *irq_ptr);
	439	void tiqdio_inbound_processing(unsigned long q);
	440	int tiqdio_allocate_memory(void);
	441	void tiqdio_free_memory(void);
	442	int tiqdio_register_thinints(void);
	443	void tiqdio_unregister_thinints(void);
	444
	445	/* prototypes for setup */
	446	void qdio_inbound_processing(unsigned long data);
	447	void qdio_outbound_processing(unsigned long data);
	448	void qdio_outbound_timer(unsigned long data);
	449	void qdio_int_handler(struct ccw_device *cdev, unsigned long intparm,
	450	struct irb *irb);
	451	int qdio_allocate_qs(struct qdio_irq *irq_ptr, int nr_input_qs,
	452	int nr_output_qs);
	453	void qdio_setup_ssqd_info(struct qdio_irq *irq_ptr);
bbd50e17 JG	454	int qdio_setup_get_ssqd(struct qdio_irq *irq_ptr,
	455	struct subchannel_id *schid,
	456	struct qdio_ssqd_desc *data);
779e6e1c JG	457	int qdio_setup_irq(struct qdio_initialize *init_data);
	458	void qdio_print_subchannel_info(struct qdio_irq *irq_ptr,
	459	struct ccw_device *cdev);
	460	void qdio_release_memory(struct qdio_irq *irq_ptr);
50f769df JG	461	int qdio_setup_create_sysfs(struct ccw_device *cdev);
50f769df JG	462	void qdio_setup_destroy_sysfs(struct ccw_device *cdev);
779e6e1c JG	463	int qdio_setup_init(void);
	464	void qdio_setup_exit(void);
	465
60b5df2f JG	466	int debug_get_buf_state(struct qdio_q *q, unsigned int bufnr,
60b5df2f JG	467	unsigned char *state);
779e6e1c	468	#endif /* _CIO_QDIO_H */