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1da177e4 LT |
1 | /* |
2 | 3w-xxxx.h -- 3ware Storage Controller device driver for Linux. | |
3 | ||
4deedd84 | 4 | Written By: Adam Radford <linuxraid@lsi.com> |
1da177e4 LT |
5 | Modifications By: Joel Jacobson <linux@3ware.com> |
6 | Arnaldo Carvalho de Melo <acme@conectiva.com.br> | |
7 | Brad Strand <linux@3ware.com> | |
8 | ||
4deedd84 | 9 | Copyright (C) 1999-2010 3ware Inc. |
1da177e4 | 10 | |
25985edc | 11 | Kernel compatibility By: Andre Hedrick <andre@suse.com> |
1da177e4 LT |
12 | Non-Copyright (C) 2000 Andre Hedrick <andre@suse.com> |
13 | ||
14 | This program is free software; you can redistribute it and/or modify | |
15 | it under the terms of the GNU General Public License as published by | |
16 | the Free Software Foundation; version 2 of the License. | |
17 | ||
18 | This program is distributed in the hope that it will be useful, | |
19 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | GNU General Public License for more details. | |
22 | ||
23 | NO WARRANTY | |
24 | THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR | |
25 | CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT | |
26 | LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, | |
27 | MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is | |
28 | solely responsible for determining the appropriateness of using and | |
29 | distributing the Program and assumes all risks associated with its | |
30 | exercise of rights under this Agreement, including but not limited to | |
31 | the risks and costs of program errors, damage to or loss of data, | |
32 | programs or equipment, and unavailability or interruption of operations. | |
33 | ||
34 | DISCLAIMER OF LIABILITY | |
35 | NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY | |
36 | DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
37 | DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND | |
38 | ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR | |
39 | TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE | |
40 | USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED | |
41 | HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES | |
42 | ||
43 | You should have received a copy of the GNU General Public License | |
44 | along with this program; if not, write to the Free Software | |
45 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
46 | ||
47 | Bugs/Comments/Suggestions should be mailed to: | |
4deedd84 | 48 | linuxraid@lsi.com |
1da177e4 LT |
49 | |
50 | For more information, goto: | |
4deedd84 | 51 | http://www.lsi.com |
1da177e4 LT |
52 | */ |
53 | ||
54 | #ifndef _3W_XXXX_H | |
55 | #define _3W_XXXX_H | |
56 | ||
1da177e4 LT |
57 | #include <linux/types.h> |
58 | ||
59 | /* AEN strings */ | |
60 | static char *tw_aen_string[] = { | |
61 | [0x000] = "INFO: AEN queue empty", | |
62 | [0x001] = "INFO: Soft reset occurred", | |
63 | [0x002] = "ERROR: Unit degraded: Unit #", | |
64 | [0x003] = "ERROR: Controller error", | |
65 | [0x004] = "ERROR: Rebuild failed: Unit #", | |
66 | [0x005] = "INFO: Rebuild complete: Unit #", | |
67 | [0x006] = "ERROR: Incomplete unit detected: Unit #", | |
68 | [0x007] = "INFO: Initialization complete: Unit #", | |
69 | [0x008] = "WARNING: Unclean shutdown detected: Unit #", | |
70 | [0x009] = "WARNING: ATA port timeout: Port #", | |
71 | [0x00A] = "ERROR: Drive error: Port #", | |
72 | [0x00B] = "INFO: Rebuild started: Unit #", | |
73 | [0x00C] = "INFO: Initialization started: Unit #", | |
74 | [0x00D] = "ERROR: Logical unit deleted: Unit #", | |
75 | [0x00F] = "WARNING: SMART threshold exceeded: Port #", | |
76 | [0x021] = "WARNING: ATA UDMA downgrade: Port #", | |
d41ba22a | 77 | [0x022] = "WARNING: ATA UDMA upgrade: Port #", |
1da177e4 LT |
78 | [0x023] = "WARNING: Sector repair occurred: Port #", |
79 | [0x024] = "ERROR: SBUF integrity check failure", | |
80 | [0x025] = "ERROR: Lost cached write: Port #", | |
81 | [0x026] = "ERROR: Drive ECC error detected: Port #", | |
82 | [0x027] = "ERROR: DCB checksum error: Port #", | |
83 | [0x028] = "ERROR: DCB unsupported version: Port #", | |
84 | [0x029] = "INFO: Verify started: Unit #", | |
85 | [0x02A] = "ERROR: Verify failed: Port #", | |
86 | [0x02B] = "INFO: Verify complete: Unit #", | |
87 | [0x02C] = "WARNING: Overwrote bad sector during rebuild: Port #", | |
88 | [0x02D] = "ERROR: Encountered bad sector during rebuild: Port #", | |
89 | [0x02E] = "ERROR: Replacement drive is too small: Port #", | |
90 | [0x02F] = "WARNING: Verify error: Unit not previously initialized: Unit #", | |
91 | [0x030] = "ERROR: Drive not supported: Port #" | |
92 | }; | |
93 | ||
94 | /* | |
95 | Sense key lookup table | |
96 | Format: ESDC/flags,SenseKey,AdditionalSenseCode,AdditionalSenseCodeQualifier | |
97 | */ | |
98 | static unsigned char tw_sense_table[][4] = | |
99 | { | |
100 | /* Codes for newer firmware */ | |
101 | // ATA Error SCSI Error | |
102 | {0x01, 0x03, 0x13, 0x00}, // Address mark not found Address mark not found for data field | |
103 | {0x04, 0x0b, 0x00, 0x00}, // Aborted command Aborted command | |
104 | {0x10, 0x0b, 0x14, 0x00}, // ID not found Recorded entity not found | |
105 | {0x40, 0x03, 0x11, 0x00}, // Uncorrectable ECC error Unrecovered read error | |
106 | {0x61, 0x04, 0x00, 0x00}, // Device fault Hardware error | |
107 | {0x84, 0x0b, 0x47, 0x00}, // Data CRC error SCSI parity error | |
108 | {0xd0, 0x0b, 0x00, 0x00}, // Device busy Aborted command | |
109 | {0xd1, 0x0b, 0x00, 0x00}, // Device busy Aborted command | |
110 | {0x37, 0x02, 0x04, 0x00}, // Unit offline Not ready | |
111 | {0x09, 0x02, 0x04, 0x00}, // Unrecovered disk error Not ready | |
112 | ||
113 | /* Codes for older firmware */ | |
114 | // 3ware Error SCSI Error | |
115 | {0x51, 0x0b, 0x00, 0x00} // Unspecified Aborted command | |
116 | }; | |
117 | ||
118 | /* Control register bit definitions */ | |
119 | #define TW_CONTROL_CLEAR_HOST_INTERRUPT 0x00080000 | |
120 | #define TW_CONTROL_CLEAR_ATTENTION_INTERRUPT 0x00040000 | |
121 | #define TW_CONTROL_MASK_COMMAND_INTERRUPT 0x00020000 | |
122 | #define TW_CONTROL_MASK_RESPONSE_INTERRUPT 0x00010000 | |
123 | #define TW_CONTROL_UNMASK_COMMAND_INTERRUPT 0x00008000 | |
124 | #define TW_CONTROL_UNMASK_RESPONSE_INTERRUPT 0x00004000 | |
125 | #define TW_CONTROL_CLEAR_ERROR_STATUS 0x00000200 | |
126 | #define TW_CONTROL_ISSUE_SOFT_RESET 0x00000100 | |
127 | #define TW_CONTROL_ENABLE_INTERRUPTS 0x00000080 | |
128 | #define TW_CONTROL_DISABLE_INTERRUPTS 0x00000040 | |
129 | #define TW_CONTROL_ISSUE_HOST_INTERRUPT 0x00000020 | |
130 | #define TW_CONTROL_CLEAR_PARITY_ERROR 0x00800000 | |
131 | #define TW_CONTROL_CLEAR_QUEUE_ERROR 0x00400000 | |
132 | #define TW_CONTROL_CLEAR_PCI_ABORT 0x00100000 | |
133 | #define TW_CONTROL_CLEAR_SBUF_WRITE_ERROR 0x00000008 | |
134 | ||
135 | /* Status register bit definitions */ | |
136 | #define TW_STATUS_MAJOR_VERSION_MASK 0xF0000000 | |
137 | #define TW_STATUS_MINOR_VERSION_MASK 0x0F000000 | |
138 | #define TW_STATUS_PCI_PARITY_ERROR 0x00800000 | |
139 | #define TW_STATUS_QUEUE_ERROR 0x00400000 | |
140 | #define TW_STATUS_MICROCONTROLLER_ERROR 0x00200000 | |
141 | #define TW_STATUS_PCI_ABORT 0x00100000 | |
142 | #define TW_STATUS_HOST_INTERRUPT 0x00080000 | |
143 | #define TW_STATUS_ATTENTION_INTERRUPT 0x00040000 | |
144 | #define TW_STATUS_COMMAND_INTERRUPT 0x00020000 | |
145 | #define TW_STATUS_RESPONSE_INTERRUPT 0x00010000 | |
146 | #define TW_STATUS_COMMAND_QUEUE_FULL 0x00008000 | |
147 | #define TW_STATUS_RESPONSE_QUEUE_EMPTY 0x00004000 | |
148 | #define TW_STATUS_MICROCONTROLLER_READY 0x00002000 | |
149 | #define TW_STATUS_COMMAND_QUEUE_EMPTY 0x00001000 | |
150 | #define TW_STATUS_ALL_INTERRUPTS 0x000F0000 | |
151 | #define TW_STATUS_CLEARABLE_BITS 0x00D00000 | |
152 | #define TW_STATUS_EXPECTED_BITS 0x00002000 | |
153 | #define TW_STATUS_UNEXPECTED_BITS 0x00F00008 | |
154 | #define TW_STATUS_SBUF_WRITE_ERROR 0x00000008 | |
155 | #define TW_STATUS_VALID_INTERRUPT 0x00DF0008 | |
156 | ||
157 | /* RESPONSE QUEUE BIT DEFINITIONS */ | |
158 | #define TW_RESPONSE_ID_MASK 0x00000FF0 | |
159 | ||
160 | /* PCI related defines */ | |
161 | #define TW_IO_ADDRESS_RANGE 0x10 | |
162 | #define TW_DEVICE_NAME "3ware Storage Controller" | |
163 | #define TW_VENDOR_ID (0x13C1) /* 3ware */ | |
164 | #define TW_DEVICE_ID (0x1000) /* Storage Controller */ | |
165 | #define TW_DEVICE_ID2 (0x1001) /* 7000 series controller */ | |
166 | #define TW_NUMDEVICES 2 | |
167 | #define TW_PCI_CLEAR_PARITY_ERRORS 0xc100 | |
168 | #define TW_PCI_CLEAR_PCI_ABORT 0x2000 | |
169 | ||
170 | /* Command packet opcodes */ | |
171 | #define TW_OP_NOP 0x0 | |
172 | #define TW_OP_INIT_CONNECTION 0x1 | |
173 | #define TW_OP_READ 0x2 | |
174 | #define TW_OP_WRITE 0x3 | |
175 | #define TW_OP_VERIFY 0x4 | |
176 | #define TW_OP_GET_PARAM 0x12 | |
177 | #define TW_OP_SET_PARAM 0x13 | |
178 | #define TW_OP_SECTOR_INFO 0x1a | |
179 | #define TW_OP_AEN_LISTEN 0x1c | |
180 | #define TW_OP_FLUSH_CACHE 0x0e | |
181 | #define TW_CMD_PACKET 0x1d | |
182 | #define TW_CMD_PACKET_WITH_DATA 0x1f | |
183 | ||
184 | /* Asynchronous Event Notification (AEN) Codes */ | |
185 | #define TW_AEN_QUEUE_EMPTY 0x0000 | |
186 | #define TW_AEN_SOFT_RESET 0x0001 | |
187 | #define TW_AEN_DEGRADED_MIRROR 0x0002 | |
188 | #define TW_AEN_CONTROLLER_ERROR 0x0003 | |
189 | #define TW_AEN_REBUILD_FAIL 0x0004 | |
190 | #define TW_AEN_REBUILD_DONE 0x0005 | |
191 | #define TW_AEN_QUEUE_FULL 0x00ff | |
192 | #define TW_AEN_TABLE_UNDEFINED 0x15 | |
193 | #define TW_AEN_APORT_TIMEOUT 0x0009 | |
194 | #define TW_AEN_DRIVE_ERROR 0x000A | |
195 | #define TW_AEN_SMART_FAIL 0x000F | |
196 | #define TW_AEN_SBUF_FAIL 0x0024 | |
197 | ||
1da177e4 LT |
198 | /* Misc defines */ |
199 | #define TW_ALIGNMENT_6000 64 /* 64 bytes */ | |
200 | #define TW_ALIGNMENT_7000 4 /* 4 bytes */ | |
201 | #define TW_MAX_UNITS 16 | |
202 | #define TW_COMMAND_ALIGNMENT_MASK 0x1ff | |
203 | #define TW_INIT_MESSAGE_CREDITS 0x100 | |
204 | #define TW_INIT_COMMAND_PACKET_SIZE 0x3 | |
205 | #define TW_POLL_MAX_RETRIES 20000 | |
206 | #define TW_MAX_SGL_LENGTH 62 | |
207 | #define TW_ATA_PASS_SGL_MAX 60 | |
208 | #define TW_Q_LENGTH 256 | |
209 | #define TW_Q_START 0 | |
210 | #define TW_MAX_SLOT 32 | |
211 | #define TW_MAX_PCI_BUSES 255 | |
212 | #define TW_MAX_RESET_TRIES 3 | |
213 | #define TW_UNIT_INFORMATION_TABLE_BASE 0x300 | |
214 | #define TW_MAX_CMDS_PER_LUN 254 /* 254 for io, 1 for | |
215 | chrdev ioctl, one for | |
216 | internal aen post */ | |
217 | #define TW_BLOCK_SIZE 0x200 /* 512-byte blocks */ | |
218 | #define TW_IOCTL 0x80 | |
219 | #define TW_UNIT_ONLINE 1 | |
220 | #define TW_IN_INTR 1 | |
221 | #define TW_IN_RESET 2 | |
222 | #define TW_IN_CHRDEV_IOCTL 3 | |
223 | #define TW_MAX_SECTORS 256 | |
224 | #define TW_MAX_IOCTL_SECTORS 512 | |
225 | #define TW_AEN_WAIT_TIME 1000 | |
226 | #define TW_IOCTL_WAIT_TIME (1 * HZ) /* 1 second */ | |
227 | #define TW_ISR_DONT_COMPLETE 2 | |
228 | #define TW_ISR_DONT_RESULT 3 | |
229 | #define TW_IOCTL_TIMEOUT 25 /* 25 seconds */ | |
230 | #define TW_IOCTL_CHRDEV_TIMEOUT 60 /* 60 seconds */ | |
231 | #define TW_IOCTL_CHRDEV_FREE -1 | |
284901a9 | 232 | #define TW_DMA_MASK DMA_BIT_MASK(32) |
1da177e4 LT |
233 | #define TW_MAX_CDB_LEN 16 |
234 | ||
235 | /* Bitmask macros to eliminate bitfields */ | |
236 | ||
237 | /* opcode: 5, sgloffset: 3 */ | |
238 | #define TW_OPSGL_IN(x,y) ((x << 5) | (y & 0x1f)) | |
239 | #define TW_SGL_OUT(x) ((x >> 5) & 0x7) | |
240 | ||
241 | /* reserved_1: 4, response_id: 8, reserved_2: 20 */ | |
242 | #define TW_RESID_OUT(x) ((x >> 4) & 0xff) | |
243 | ||
244 | /* unit: 4, host_id: 4 */ | |
245 | #define TW_UNITHOST_IN(x,y) ((x << 4) | ( y & 0xf)) | |
246 | #define TW_UNIT_OUT(x) (x & 0xf) | |
247 | ||
248 | /* Macros */ | |
249 | #define TW_CONTROL_REG_ADDR(x) (x->base_addr) | |
250 | #define TW_STATUS_REG_ADDR(x) (x->base_addr + 0x4) | |
251 | #define TW_COMMAND_QUEUE_REG_ADDR(x) (x->base_addr + 0x8) | |
252 | #define TW_RESPONSE_QUEUE_REG_ADDR(x) (x->base_addr + 0xC) | |
253 | #define TW_CLEAR_ALL_INTERRUPTS(x) (outl(TW_STATUS_VALID_INTERRUPT, TW_CONTROL_REG_ADDR(x))) | |
254 | #define TW_CLEAR_ATTENTION_INTERRUPT(x) (outl(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT, TW_CONTROL_REG_ADDR(x))) | |
255 | #define TW_CLEAR_HOST_INTERRUPT(x) (outl(TW_CONTROL_CLEAR_HOST_INTERRUPT, TW_CONTROL_REG_ADDR(x))) | |
256 | #define TW_DISABLE_INTERRUPTS(x) (outl(TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x))) | |
257 | #define TW_ENABLE_AND_CLEAR_INTERRUPTS(x) (outl(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | TW_CONTROL_UNMASK_RESPONSE_INTERRUPT | TW_CONTROL_ENABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x))) | |
258 | #define TW_MASK_COMMAND_INTERRUPT(x) (outl(TW_CONTROL_MASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x))) | |
259 | #define TW_UNMASK_COMMAND_INTERRUPT(x) (outl(TW_CONTROL_UNMASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x))) | |
260 | #define TW_SOFT_RESET(x) (outl(TW_CONTROL_ISSUE_SOFT_RESET | \ | |
261 | TW_CONTROL_CLEAR_HOST_INTERRUPT | \ | |
262 | TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | \ | |
263 | TW_CONTROL_MASK_COMMAND_INTERRUPT | \ | |
264 | TW_CONTROL_MASK_RESPONSE_INTERRUPT | \ | |
265 | TW_CONTROL_CLEAR_ERROR_STATUS | \ | |
266 | TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x))) | |
267 | #define TW_STATUS_ERRORS(x) \ | |
268 | (((x & TW_STATUS_PCI_ABORT) || \ | |
269 | (x & TW_STATUS_PCI_PARITY_ERROR) || \ | |
270 | (x & TW_STATUS_QUEUE_ERROR) || \ | |
271 | (x & TW_STATUS_MICROCONTROLLER_ERROR)) && \ | |
272 | (x & TW_STATUS_MICROCONTROLLER_READY)) | |
273 | ||
274 | #ifdef TW_DEBUG | |
275 | #define dprintk(msg...) printk(msg) | |
276 | #else | |
277 | #define dprintk(msg...) do { } while(0) | |
278 | #endif | |
279 | ||
280 | #pragma pack(1) | |
281 | ||
282 | /* Scatter Gather List Entry */ | |
283 | typedef struct TAG_TW_SG_Entry { | |
284 | u32 address; | |
285 | u32 length; | |
286 | } TW_SG_Entry; | |
287 | ||
288 | typedef unsigned char TW_Sector[512]; | |
289 | ||
290 | /* Command Packet */ | |
291 | typedef struct TW_Command { | |
292 | unsigned char opcode__sgloffset; | |
293 | unsigned char size; | |
294 | unsigned char request_id; | |
295 | unsigned char unit__hostid; | |
296 | /* Second DWORD */ | |
297 | unsigned char status; | |
298 | unsigned char flags; | |
299 | union { | |
300 | unsigned short block_count; | |
301 | unsigned short parameter_count; | |
302 | unsigned short message_credits; | |
303 | } byte6; | |
304 | union { | |
305 | struct { | |
306 | u32 lba; | |
307 | TW_SG_Entry sgl[TW_MAX_SGL_LENGTH]; | |
308 | u32 padding; /* pad to 512 bytes */ | |
309 | } io; | |
310 | struct { | |
311 | TW_SG_Entry sgl[TW_MAX_SGL_LENGTH]; | |
312 | u32 padding[2]; | |
313 | } param; | |
314 | struct { | |
315 | u32 response_queue_pointer; | |
316 | u32 padding[125]; | |
317 | } init_connection; | |
318 | struct { | |
319 | char version[504]; | |
320 | } ioctl_miniport_version; | |
321 | } byte8; | |
322 | } TW_Command; | |
323 | ||
324 | #pragma pack() | |
325 | ||
326 | typedef struct TAG_TW_Ioctl { | |
327 | unsigned char opcode; | |
328 | unsigned short table_id; | |
329 | unsigned char parameter_id; | |
330 | unsigned char parameter_size_bytes; | |
331 | unsigned char unit_index; | |
332 | unsigned char data[1]; | |
333 | } TW_Ioctl; | |
334 | ||
335 | #pragma pack(1) | |
336 | ||
337 | /* Structure for new chardev ioctls */ | |
338 | typedef struct TAG_TW_New_Ioctl { | |
339 | unsigned int data_buffer_length; | |
340 | unsigned char padding [508]; | |
341 | TW_Command firmware_command; | |
342 | char data_buffer[1]; | |
343 | } TW_New_Ioctl; | |
344 | ||
345 | /* GetParam descriptor */ | |
346 | typedef struct { | |
347 | unsigned short table_id; | |
348 | unsigned char parameter_id; | |
349 | unsigned char parameter_size_bytes; | |
350 | unsigned char data[1]; | |
351 | } TW_Param, *PTW_Param; | |
352 | ||
353 | /* Response queue */ | |
354 | typedef union TAG_TW_Response_Queue { | |
355 | u32 response_id; | |
356 | u32 value; | |
357 | } TW_Response_Queue; | |
358 | ||
359 | typedef int TW_Cmd_State; | |
360 | ||
361 | #define TW_S_INITIAL 0x1 /* Initial state */ | |
362 | #define TW_S_STARTED 0x2 /* Id in use */ | |
363 | #define TW_S_POSTED 0x4 /* Posted to the controller */ | |
364 | #define TW_S_PENDING 0x8 /* Waiting to be posted in isr */ | |
365 | #define TW_S_COMPLETED 0x10 /* Completed by isr */ | |
366 | #define TW_S_FINISHED 0x20 /* I/O completely done */ | |
367 | #define TW_START_MASK (TW_S_STARTED | TW_S_POSTED | TW_S_PENDING | TW_S_COMPLETED) | |
368 | ||
369 | /* Command header for ATA pass-thru */ | |
370 | typedef struct TAG_TW_Passthru | |
371 | { | |
372 | unsigned char opcode__sgloffset; | |
373 | unsigned char size; | |
374 | unsigned char request_id; | |
375 | unsigned char aport__hostid; | |
376 | unsigned char status; | |
377 | unsigned char flags; | |
378 | unsigned short param; | |
379 | unsigned short features; | |
380 | unsigned short sector_count; | |
381 | unsigned short sector_num; | |
382 | unsigned short cylinder_lo; | |
383 | unsigned short cylinder_hi; | |
384 | unsigned char drive_head; | |
385 | unsigned char command; | |
386 | TW_SG_Entry sg_list[TW_ATA_PASS_SGL_MAX]; | |
387 | unsigned char padding[12]; | |
388 | } TW_Passthru; | |
389 | ||
4bfaa5c4 AB |
390 | #pragma pack() |
391 | ||
1da177e4 LT |
392 | typedef struct TAG_TW_Device_Extension { |
393 | u32 base_addr; | |
394 | unsigned long *alignment_virtual_address[TW_Q_LENGTH]; | |
395 | unsigned long alignment_physical_address[TW_Q_LENGTH]; | |
396 | int is_unit_present[TW_MAX_UNITS]; | |
397 | unsigned long *command_packet_virtual_address[TW_Q_LENGTH]; | |
398 | unsigned long command_packet_physical_address[TW_Q_LENGTH]; | |
399 | struct pci_dev *tw_pci_dev; | |
400 | struct scsi_cmnd *srb[TW_Q_LENGTH]; | |
401 | unsigned char free_queue[TW_Q_LENGTH]; | |
402 | unsigned char free_head; | |
403 | unsigned char free_tail; | |
404 | unsigned char pending_queue[TW_Q_LENGTH]; | |
405 | unsigned char pending_head; | |
406 | unsigned char pending_tail; | |
407 | TW_Cmd_State state[TW_Q_LENGTH]; | |
408 | u32 posted_request_count; | |
409 | u32 max_posted_request_count; | |
410 | u32 request_count_marked_pending; | |
411 | u32 pending_request_count; | |
412 | u32 max_pending_request_count; | |
413 | u32 max_sgl_entries; | |
414 | u32 sgl_entries; | |
415 | u32 num_resets; | |
416 | u32 sector_count; | |
417 | u32 max_sector_count; | |
418 | u32 aen_count; | |
419 | struct Scsi_Host *host; | |
a12e25bd | 420 | struct mutex ioctl_lock; |
1da177e4 LT |
421 | unsigned short aen_queue[TW_Q_LENGTH]; |
422 | unsigned char aen_head; | |
423 | unsigned char aen_tail; | |
424 | volatile long flags; /* long req'd for set_bit --RR */ | |
425 | int reset_print; | |
426 | volatile int chrdev_request_id; | |
427 | wait_queue_head_t ioctl_wqueue; | |
428 | } TW_Device_Extension; | |
429 | ||
1da177e4 | 430 | #endif /* _3W_XXXX_H */ |