Commit | Line | Data |
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01fbfe0b | 1 | #define DRV_NAME "advansys" |
8c6af9e1 | 2 | #define ASC_VERSION "3.4" /* AdvanSys Driver Version */ |
1da177e4 LT |
3 | |
4 | /* | |
5 | * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters | |
6 | * | |
7 | * Copyright (c) 1995-2000 Advanced System Products, Inc. | |
8 | * Copyright (c) 2000-2001 ConnectCom Solutions, Inc. | |
8c6af9e1 | 9 | * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx> |
1da177e4 LT |
10 | * All Rights Reserved. |
11 | * | |
8c6af9e1 MW |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | */ | |
17 | ||
18 | /* | |
1da177e4 LT |
19 | * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys) |
20 | * changed its name to ConnectCom Solutions, Inc. | |
8c6af9e1 | 21 | * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets |
1da177e4 LT |
22 | */ |
23 | ||
1da177e4 | 24 | #include <linux/module.h> |
1da177e4 LT |
25 | #include <linux/string.h> |
26 | #include <linux/kernel.h> | |
27 | #include <linux/types.h> | |
28 | #include <linux/ioport.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/slab.h> | |
32 | #include <linux/mm.h> | |
33 | #include <linux/proc_fs.h> | |
34 | #include <linux/init.h> | |
35 | #include <linux/blkdev.h> | |
c304ec94 | 36 | #include <linux/isa.h> |
b09e05a7 | 37 | #include <linux/eisa.h> |
8c6af9e1 | 38 | #include <linux/pci.h> |
1da177e4 LT |
39 | #include <linux/spinlock.h> |
40 | #include <linux/dma-mapping.h> | |
41 | ||
42 | #include <asm/io.h> | |
43 | #include <asm/system.h> | |
44 | #include <asm/dma.h> | |
45 | ||
8c6af9e1 MW |
46 | #include <scsi/scsi_cmnd.h> |
47 | #include <scsi/scsi_device.h> | |
48 | #include <scsi/scsi_tcq.h> | |
49 | #include <scsi/scsi.h> | |
50 | #include <scsi/scsi_host.h> | |
51 | ||
4bd6d7f3 | 52 | /* FIXME: |
1da177e4 | 53 | * |
4bd6d7f3 MW |
54 | * 1. Although all of the necessary command mapping places have the |
55 | * appropriate dma_map.. APIs, the driver still processes its internal | |
56 | * queue using bus_to_virt() and virt_to_bus() which are illegal under | |
57 | * the API. The entire queue processing structure will need to be | |
58 | * altered to fix this. | |
59 | * 2. Need to add memory mapping workaround. Test the memory mapping. | |
60 | * If it doesn't work revert to I/O port access. Can a test be done | |
61 | * safely? | |
62 | * 3. Handle an interrupt not working. Keep an interrupt counter in | |
63 | * the interrupt handler. In the timeout function if the interrupt | |
64 | * has not occurred then print a message and run in polled mode. | |
65 | * 4. Need to add support for target mode commands, cf. CAM XPT. | |
66 | * 5. check DMA mapping functions for failure | |
349d2c44 MW |
67 | * 6. Use scsi_transport_spi |
68 | * 7. advansys_info is not safe against multiple simultaneous callers | |
69 | * 8. Kill boardp->id | |
70 | * 9. Add module_param to override ISA/VLB ioport array | |
1da177e4 LT |
71 | */ |
72 | #warning this driver is still not properly converted to the DMA API | |
73 | ||
1da177e4 LT |
74 | /* Enable driver /proc statistics. */ |
75 | #define ADVANSYS_STATS | |
76 | ||
77 | /* Enable driver tracing. */ | |
78 | /* #define ADVANSYS_DEBUG */ | |
79 | ||
1da177e4 LT |
80 | #define ASC_LIB_VERSION_MAJOR 1 |
81 | #define ASC_LIB_VERSION_MINOR 24 | |
82 | #define ASC_LIB_SERIAL_NUMBER 123 | |
83 | ||
84 | /* | |
85 | * Portable Data Types | |
86 | * | |
87 | * Any instance where a 32-bit long or pointer type is assumed | |
88 | * for precision or HW defined structures, the following define | |
89 | * types must be used. In Linux the char, short, and int types | |
90 | * are all consistent at 8, 16, and 32 bits respectively. Pointers | |
91 | * and long types are 64 bits on Alpha and UltraSPARC. | |
92 | */ | |
27c868c2 MW |
93 | #define ASC_PADDR __u32 /* Physical/Bus address data type. */ |
94 | #define ASC_VADDR __u32 /* Virtual address data type. */ | |
95 | #define ASC_DCNT __u32 /* Unsigned Data count type. */ | |
96 | #define ASC_SDCNT __s32 /* Signed Data count type. */ | |
1da177e4 LT |
97 | |
98 | /* | |
99 | * These macros are used to convert a virtual address to a | |
100 | * 32-bit value. This currently can be used on Linux Alpha | |
101 | * which uses 64-bit virtual address but a 32-bit bus address. | |
102 | * This is likely to break in the future, but doing this now | |
103 | * will give us time to change the HW and FW to handle 64-bit | |
104 | * addresses. | |
105 | */ | |
106 | #define ASC_VADDR_TO_U32 virt_to_bus | |
107 | #define ASC_U32_TO_VADDR bus_to_virt | |
108 | ||
109 | typedef unsigned char uchar; | |
110 | ||
111 | #ifndef TRUE | |
112 | #define TRUE (1) | |
113 | #endif | |
114 | #ifndef FALSE | |
115 | #define FALSE (0) | |
116 | #endif | |
117 | ||
1da177e4 LT |
118 | #define ERR (-1) |
119 | #define UW_ERR (uint)(0xFFFF) | |
120 | #define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0) | |
1da177e4 | 121 | |
2672ea86 DJ |
122 | #define PCI_VENDOR_ID_ASP 0x10cd |
123 | #define PCI_DEVICE_ID_ASP_1200A 0x1100 | |
124 | #define PCI_DEVICE_ID_ASP_ABP940 0x1200 | |
125 | #define PCI_DEVICE_ID_ASP_ABP940U 0x1300 | |
126 | #define PCI_DEVICE_ID_ASP_ABP940UW 0x2300 | |
127 | #define PCI_DEVICE_ID_38C0800_REV1 0x2500 | |
128 | #define PCI_DEVICE_ID_38C1600_REV1 0x2700 | |
129 | ||
1da177e4 LT |
130 | /* |
131 | * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists. | |
132 | * The SRB structure will have to be changed and the ASC_SRB2SCSIQ() | |
133 | * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the | |
134 | * SRB structure. | |
135 | */ | |
136 | #define CC_VERY_LONG_SG_LIST 0 | |
137 | #define ASC_SRB2SCSIQ(srb_ptr) (srb_ptr) | |
138 | ||
27c868c2 | 139 | #define PortAddr unsigned short /* port address size */ |
1da177e4 LT |
140 | #define inp(port) inb(port) |
141 | #define outp(port, byte) outb((byte), (port)) | |
142 | ||
143 | #define inpw(port) inw(port) | |
144 | #define outpw(port, word) outw((word), (port)) | |
145 | ||
146 | #define ASC_MAX_SG_QUEUE 7 | |
147 | #define ASC_MAX_SG_LIST 255 | |
148 | ||
149 | #define ASC_CS_TYPE unsigned short | |
150 | ||
151 | #define ASC_IS_ISA (0x0001) | |
152 | #define ASC_IS_ISAPNP (0x0081) | |
153 | #define ASC_IS_EISA (0x0002) | |
154 | #define ASC_IS_PCI (0x0004) | |
155 | #define ASC_IS_PCI_ULTRA (0x0104) | |
156 | #define ASC_IS_PCMCIA (0x0008) | |
157 | #define ASC_IS_MCA (0x0020) | |
158 | #define ASC_IS_VL (0x0040) | |
1da177e4 LT |
159 | #define ASC_IS_WIDESCSI_16 (0x0100) |
160 | #define ASC_IS_WIDESCSI_32 (0x0200) | |
161 | #define ASC_IS_BIG_ENDIAN (0x8000) | |
95c9f162 | 162 | |
1da177e4 LT |
163 | #define ASC_CHIP_MIN_VER_VL (0x01) |
164 | #define ASC_CHIP_MAX_VER_VL (0x07) | |
165 | #define ASC_CHIP_MIN_VER_PCI (0x09) | |
166 | #define ASC_CHIP_MAX_VER_PCI (0x0F) | |
167 | #define ASC_CHIP_VER_PCI_BIT (0x08) | |
168 | #define ASC_CHIP_MIN_VER_ISA (0x11) | |
169 | #define ASC_CHIP_MIN_VER_ISA_PNP (0x21) | |
170 | #define ASC_CHIP_MAX_VER_ISA (0x27) | |
171 | #define ASC_CHIP_VER_ISA_BIT (0x30) | |
172 | #define ASC_CHIP_VER_ISAPNP_BIT (0x20) | |
173 | #define ASC_CHIP_VER_ASYN_BUG (0x21) | |
174 | #define ASC_CHIP_VER_PCI 0x08 | |
175 | #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02) | |
176 | #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03) | |
177 | #define ASC_CHIP_MIN_VER_EISA (0x41) | |
178 | #define ASC_CHIP_MAX_VER_EISA (0x47) | |
179 | #define ASC_CHIP_VER_EISA_BIT (0x40) | |
180 | #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3) | |
1da177e4 | 181 | #define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL) |
1da177e4 | 182 | #define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL) |
1da177e4 | 183 | #define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL) |
1da177e4 LT |
184 | |
185 | #define ASC_SCSI_ID_BITS 3 | |
186 | #define ASC_SCSI_TIX_TYPE uchar | |
187 | #define ASC_ALL_DEVICE_BIT_SET 0xFF | |
188 | #define ASC_SCSI_BIT_ID_TYPE uchar | |
189 | #define ASC_MAX_TID 7 | |
190 | #define ASC_MAX_LUN 7 | |
191 | #define ASC_SCSI_WIDTH_BIT_SET 0xFF | |
192 | #define ASC_MAX_SENSE_LEN 32 | |
193 | #define ASC_MIN_SENSE_LEN 14 | |
1da177e4 LT |
194 | #define ASC_SCSI_RESET_HOLD_TIME_US 60 |
195 | ||
f05ec594 MW |
196 | /* |
197 | * Narrow boards only support 12-byte commands, while wide boards | |
198 | * extend to 16-byte commands. | |
199 | */ | |
200 | #define ASC_MAX_CDB_LEN 12 | |
201 | #define ADV_MAX_CDB_LEN 16 | |
202 | ||
1da177e4 | 203 | #define MS_SDTR_LEN 0x03 |
1da177e4 | 204 | #define MS_WDTR_LEN 0x02 |
1da177e4 LT |
205 | |
206 | #define ASC_SG_LIST_PER_Q 7 | |
207 | #define QS_FREE 0x00 | |
208 | #define QS_READY 0x01 | |
209 | #define QS_DISC1 0x02 | |
210 | #define QS_DISC2 0x04 | |
211 | #define QS_BUSY 0x08 | |
212 | #define QS_ABORTED 0x40 | |
213 | #define QS_DONE 0x80 | |
214 | #define QC_NO_CALLBACK 0x01 | |
215 | #define QC_SG_SWAP_QUEUE 0x02 | |
216 | #define QC_SG_HEAD 0x04 | |
217 | #define QC_DATA_IN 0x08 | |
218 | #define QC_DATA_OUT 0x10 | |
219 | #define QC_URGENT 0x20 | |
220 | #define QC_MSG_OUT 0x40 | |
221 | #define QC_REQ_SENSE 0x80 | |
222 | #define QCSG_SG_XFER_LIST 0x02 | |
223 | #define QCSG_SG_XFER_MORE 0x04 | |
224 | #define QCSG_SG_XFER_END 0x08 | |
225 | #define QD_IN_PROGRESS 0x00 | |
226 | #define QD_NO_ERROR 0x01 | |
227 | #define QD_ABORTED_BY_HOST 0x02 | |
228 | #define QD_WITH_ERROR 0x04 | |
229 | #define QD_INVALID_REQUEST 0x80 | |
230 | #define QD_INVALID_HOST_NUM 0x81 | |
231 | #define QD_INVALID_DEVICE 0x82 | |
232 | #define QD_ERR_INTERNAL 0xFF | |
233 | #define QHSTA_NO_ERROR 0x00 | |
234 | #define QHSTA_M_SEL_TIMEOUT 0x11 | |
235 | #define QHSTA_M_DATA_OVER_RUN 0x12 | |
236 | #define QHSTA_M_DATA_UNDER_RUN 0x12 | |
237 | #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13 | |
238 | #define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14 | |
239 | #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21 | |
240 | #define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22 | |
241 | #define QHSTA_D_HOST_ABORT_FAILED 0x23 | |
242 | #define QHSTA_D_EXE_SCSI_Q_FAILED 0x24 | |
243 | #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25 | |
244 | #define QHSTA_D_ASPI_NO_BUF_POOL 0x26 | |
245 | #define QHSTA_M_WTM_TIMEOUT 0x41 | |
246 | #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42 | |
247 | #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43 | |
248 | #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44 | |
249 | #define QHSTA_M_TARGET_STATUS_BUSY 0x45 | |
250 | #define QHSTA_M_BAD_TAG_CODE 0x46 | |
251 | #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47 | |
252 | #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48 | |
253 | #define QHSTA_D_LRAM_CMP_ERROR 0x81 | |
254 | #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1 | |
255 | #define ASC_FLAG_SCSIQ_REQ 0x01 | |
256 | #define ASC_FLAG_BIOS_SCSIQ_REQ 0x02 | |
257 | #define ASC_FLAG_BIOS_ASYNC_IO 0x04 | |
258 | #define ASC_FLAG_SRB_LINEAR_ADDR 0x08 | |
259 | #define ASC_FLAG_WIN16 0x10 | |
260 | #define ASC_FLAG_WIN32 0x20 | |
261 | #define ASC_FLAG_ISA_OVER_16MB 0x40 | |
262 | #define ASC_FLAG_DOS_VM_CALLBACK 0x80 | |
263 | #define ASC_TAG_FLAG_EXTRA_BYTES 0x10 | |
264 | #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04 | |
265 | #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08 | |
266 | #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40 | |
267 | #define ASC_SCSIQ_CPY_BEG 4 | |
268 | #define ASC_SCSIQ_SGHD_CPY_BEG 2 | |
269 | #define ASC_SCSIQ_B_FWD 0 | |
270 | #define ASC_SCSIQ_B_BWD 1 | |
271 | #define ASC_SCSIQ_B_STATUS 2 | |
272 | #define ASC_SCSIQ_B_QNO 3 | |
273 | #define ASC_SCSIQ_B_CNTL 4 | |
274 | #define ASC_SCSIQ_B_SG_QUEUE_CNT 5 | |
275 | #define ASC_SCSIQ_D_DATA_ADDR 8 | |
276 | #define ASC_SCSIQ_D_DATA_CNT 12 | |
277 | #define ASC_SCSIQ_B_SENSE_LEN 20 | |
278 | #define ASC_SCSIQ_DONE_INFO_BEG 22 | |
279 | #define ASC_SCSIQ_D_SRBPTR 22 | |
280 | #define ASC_SCSIQ_B_TARGET_IX 26 | |
281 | #define ASC_SCSIQ_B_CDB_LEN 28 | |
282 | #define ASC_SCSIQ_B_TAG_CODE 29 | |
283 | #define ASC_SCSIQ_W_VM_ID 30 | |
284 | #define ASC_SCSIQ_DONE_STATUS 32 | |
285 | #define ASC_SCSIQ_HOST_STATUS 33 | |
286 | #define ASC_SCSIQ_SCSI_STATUS 34 | |
287 | #define ASC_SCSIQ_CDB_BEG 36 | |
288 | #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56 | |
289 | #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60 | |
290 | #define ASC_SCSIQ_B_FIRST_SG_WK_QP 48 | |
291 | #define ASC_SCSIQ_B_SG_WK_QP 49 | |
292 | #define ASC_SCSIQ_B_SG_WK_IX 50 | |
293 | #define ASC_SCSIQ_W_ALT_DC1 52 | |
294 | #define ASC_SCSIQ_B_LIST_CNT 6 | |
295 | #define ASC_SCSIQ_B_CUR_LIST_CNT 7 | |
296 | #define ASC_SGQ_B_SG_CNTL 4 | |
297 | #define ASC_SGQ_B_SG_HEAD_QP 5 | |
298 | #define ASC_SGQ_B_SG_LIST_CNT 6 | |
299 | #define ASC_SGQ_B_SG_CUR_LIST_CNT 7 | |
300 | #define ASC_SGQ_LIST_BEG 8 | |
301 | #define ASC_DEF_SCSI1_QNG 4 | |
302 | #define ASC_MAX_SCSI1_QNG 4 | |
303 | #define ASC_DEF_SCSI2_QNG 16 | |
304 | #define ASC_MAX_SCSI2_QNG 32 | |
305 | #define ASC_TAG_CODE_MASK 0x23 | |
306 | #define ASC_STOP_REQ_RISC_STOP 0x01 | |
307 | #define ASC_STOP_ACK_RISC_STOP 0x03 | |
308 | #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10 | |
309 | #define ASC_STOP_CLEAN_UP_DISC_Q 0x20 | |
310 | #define ASC_STOP_HOST_REQ_RISC_HALT 0x40 | |
311 | #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS)) | |
312 | #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid)) | |
313 | #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID)) | |
314 | #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID) | |
315 | #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID) | |
316 | #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN) | |
317 | #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6)) | |
318 | ||
319 | typedef struct asc_scsiq_1 { | |
27c868c2 MW |
320 | uchar status; |
321 | uchar q_no; | |
322 | uchar cntl; | |
323 | uchar sg_queue_cnt; | |
324 | uchar target_id; | |
325 | uchar target_lun; | |
326 | ASC_PADDR data_addr; | |
327 | ASC_DCNT data_cnt; | |
328 | ASC_PADDR sense_addr; | |
329 | uchar sense_len; | |
330 | uchar extra_bytes; | |
1da177e4 LT |
331 | } ASC_SCSIQ_1; |
332 | ||
333 | typedef struct asc_scsiq_2 { | |
27c868c2 MW |
334 | ASC_VADDR srb_ptr; |
335 | uchar target_ix; | |
336 | uchar flag; | |
337 | uchar cdb_len; | |
338 | uchar tag_code; | |
339 | ushort vm_id; | |
1da177e4 LT |
340 | } ASC_SCSIQ_2; |
341 | ||
342 | typedef struct asc_scsiq_3 { | |
27c868c2 MW |
343 | uchar done_stat; |
344 | uchar host_stat; | |
345 | uchar scsi_stat; | |
346 | uchar scsi_msg; | |
1da177e4 LT |
347 | } ASC_SCSIQ_3; |
348 | ||
349 | typedef struct asc_scsiq_4 { | |
27c868c2 MW |
350 | uchar cdb[ASC_MAX_CDB_LEN]; |
351 | uchar y_first_sg_list_qp; | |
352 | uchar y_working_sg_qp; | |
353 | uchar y_working_sg_ix; | |
354 | uchar y_res; | |
355 | ushort x_req_count; | |
356 | ushort x_reconnect_rtn; | |
357 | ASC_PADDR x_saved_data_addr; | |
358 | ASC_DCNT x_saved_data_cnt; | |
1da177e4 LT |
359 | } ASC_SCSIQ_4; |
360 | ||
361 | typedef struct asc_q_done_info { | |
27c868c2 MW |
362 | ASC_SCSIQ_2 d2; |
363 | ASC_SCSIQ_3 d3; | |
364 | uchar q_status; | |
365 | uchar q_no; | |
366 | uchar cntl; | |
367 | uchar sense_len; | |
368 | uchar extra_bytes; | |
369 | uchar res; | |
370 | ASC_DCNT remain_bytes; | |
1da177e4 LT |
371 | } ASC_QDONE_INFO; |
372 | ||
373 | typedef struct asc_sg_list { | |
27c868c2 MW |
374 | ASC_PADDR addr; |
375 | ASC_DCNT bytes; | |
1da177e4 LT |
376 | } ASC_SG_LIST; |
377 | ||
378 | typedef struct asc_sg_head { | |
27c868c2 MW |
379 | ushort entry_cnt; |
380 | ushort queue_cnt; | |
381 | ushort entry_to_copy; | |
382 | ushort res; | |
05848b6e | 383 | ASC_SG_LIST sg_list[0]; |
1da177e4 LT |
384 | } ASC_SG_HEAD; |
385 | ||
1da177e4 | 386 | typedef struct asc_scsi_q { |
27c868c2 MW |
387 | ASC_SCSIQ_1 q1; |
388 | ASC_SCSIQ_2 q2; | |
389 | uchar *cdbptr; | |
390 | ASC_SG_HEAD *sg_head; | |
391 | ushort remain_sg_entry_cnt; | |
392 | ushort next_sg_index; | |
1da177e4 LT |
393 | } ASC_SCSI_Q; |
394 | ||
395 | typedef struct asc_scsi_req_q { | |
27c868c2 MW |
396 | ASC_SCSIQ_1 r1; |
397 | ASC_SCSIQ_2 r2; | |
398 | uchar *cdbptr; | |
399 | ASC_SG_HEAD *sg_head; | |
400 | uchar *sense_ptr; | |
401 | ASC_SCSIQ_3 r3; | |
402 | uchar cdb[ASC_MAX_CDB_LEN]; | |
403 | uchar sense[ASC_MIN_SENSE_LEN]; | |
1da177e4 LT |
404 | } ASC_SCSI_REQ_Q; |
405 | ||
406 | typedef struct asc_scsi_bios_req_q { | |
27c868c2 MW |
407 | ASC_SCSIQ_1 r1; |
408 | ASC_SCSIQ_2 r2; | |
409 | uchar *cdbptr; | |
410 | ASC_SG_HEAD *sg_head; | |
411 | uchar *sense_ptr; | |
412 | ASC_SCSIQ_3 r3; | |
413 | uchar cdb[ASC_MAX_CDB_LEN]; | |
414 | uchar sense[ASC_MIN_SENSE_LEN]; | |
1da177e4 LT |
415 | } ASC_SCSI_BIOS_REQ_Q; |
416 | ||
417 | typedef struct asc_risc_q { | |
27c868c2 MW |
418 | uchar fwd; |
419 | uchar bwd; | |
420 | ASC_SCSIQ_1 i1; | |
421 | ASC_SCSIQ_2 i2; | |
422 | ASC_SCSIQ_3 i3; | |
423 | ASC_SCSIQ_4 i4; | |
1da177e4 LT |
424 | } ASC_RISC_Q; |
425 | ||
426 | typedef struct asc_sg_list_q { | |
27c868c2 MW |
427 | uchar seq_no; |
428 | uchar q_no; | |
429 | uchar cntl; | |
430 | uchar sg_head_qp; | |
431 | uchar sg_list_cnt; | |
432 | uchar sg_cur_list_cnt; | |
1da177e4 LT |
433 | } ASC_SG_LIST_Q; |
434 | ||
435 | typedef struct asc_risc_sg_list_q { | |
27c868c2 MW |
436 | uchar fwd; |
437 | uchar bwd; | |
438 | ASC_SG_LIST_Q sg; | |
439 | ASC_SG_LIST sg_list[7]; | |
1da177e4 LT |
440 | } ASC_RISC_SG_LIST_Q; |
441 | ||
1da177e4 | 442 | #define ASCQ_ERR_Q_STATUS 0x0D |
1da177e4 LT |
443 | #define ASCQ_ERR_CUR_QNG 0x17 |
444 | #define ASCQ_ERR_SG_Q_LINKS 0x18 | |
1da177e4 LT |
445 | #define ASCQ_ERR_ISR_RE_ENTRY 0x1A |
446 | #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B | |
447 | #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C | |
1da177e4 LT |
448 | |
449 | /* | |
450 | * Warning code values are set in ASC_DVC_VAR 'warn_code'. | |
451 | */ | |
452 | #define ASC_WARN_NO_ERROR 0x0000 | |
453 | #define ASC_WARN_IO_PORT_ROTATE 0x0001 | |
454 | #define ASC_WARN_EEPROM_CHKSUM 0x0002 | |
455 | #define ASC_WARN_IRQ_MODIFIED 0x0004 | |
456 | #define ASC_WARN_AUTO_CONFIG 0x0008 | |
457 | #define ASC_WARN_CMD_QNG_CONFLICT 0x0010 | |
458 | #define ASC_WARN_EEPROM_RECOVER 0x0020 | |
459 | #define ASC_WARN_CFG_MSW_RECOVER 0x0040 | |
1da177e4 LT |
460 | |
461 | /* | |
462 | * Error code values are set in ASC_DVC_VAR 'err_code'. | |
463 | */ | |
464 | #define ASC_IERR_WRITE_EEPROM 0x0001 | |
465 | #define ASC_IERR_MCODE_CHKSUM 0x0002 | |
466 | #define ASC_IERR_SET_PC_ADDR 0x0004 | |
467 | #define ASC_IERR_START_STOP_CHIP 0x0008 | |
468 | #define ASC_IERR_IRQ_NO 0x0010 | |
469 | #define ASC_IERR_SET_IRQ_NO 0x0020 | |
470 | #define ASC_IERR_CHIP_VERSION 0x0040 | |
471 | #define ASC_IERR_SET_SCSI_ID 0x0080 | |
472 | #define ASC_IERR_GET_PHY_ADDR 0x0100 | |
473 | #define ASC_IERR_BAD_SIGNATURE 0x0200 | |
474 | #define ASC_IERR_NO_BUS_TYPE 0x0400 | |
475 | #define ASC_IERR_SCAM 0x0800 | |
476 | #define ASC_IERR_SET_SDTR 0x1000 | |
477 | #define ASC_IERR_RW_LRAM 0x8000 | |
478 | ||
1da177e4 LT |
479 | #define ASC_MAX_IRQ_NO 15 |
480 | #define ASC_MIN_IRQ_NO 10 | |
1da177e4 LT |
481 | #define ASC_DEF_MAX_TOTAL_QNG (0xF0) |
482 | #define ASC_MIN_TAG_Q_PER_DVC (0x04) | |
95c9f162 | 483 | #define ASC_MIN_FREE_Q (0x02) |
1da177e4 LT |
484 | #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q)) |
485 | #define ASC_MAX_TOTAL_QNG 240 | |
486 | #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16 | |
487 | #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8 | |
488 | #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20 | |
489 | #define ASC_MAX_INRAM_TAG_QNG 16 | |
1da177e4 | 490 | #define ASC_IOADR_GAP 0x10 |
1da177e4 LT |
491 | #define ASC_MAX_SYN_XFER_NO 16 |
492 | #define ASC_SYN_MAX_OFFSET 0x0F | |
493 | #define ASC_DEF_SDTR_OFFSET 0x0F | |
1da177e4 LT |
494 | #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02 |
495 | #define SYN_XFER_NS_0 25 | |
496 | #define SYN_XFER_NS_1 30 | |
497 | #define SYN_XFER_NS_2 35 | |
498 | #define SYN_XFER_NS_3 40 | |
499 | #define SYN_XFER_NS_4 50 | |
500 | #define SYN_XFER_NS_5 60 | |
501 | #define SYN_XFER_NS_6 70 | |
502 | #define SYN_XFER_NS_7 85 | |
503 | #define SYN_ULTRA_XFER_NS_0 12 | |
504 | #define SYN_ULTRA_XFER_NS_1 19 | |
505 | #define SYN_ULTRA_XFER_NS_2 25 | |
506 | #define SYN_ULTRA_XFER_NS_3 32 | |
507 | #define SYN_ULTRA_XFER_NS_4 38 | |
508 | #define SYN_ULTRA_XFER_NS_5 44 | |
509 | #define SYN_ULTRA_XFER_NS_6 50 | |
510 | #define SYN_ULTRA_XFER_NS_7 57 | |
511 | #define SYN_ULTRA_XFER_NS_8 63 | |
512 | #define SYN_ULTRA_XFER_NS_9 69 | |
513 | #define SYN_ULTRA_XFER_NS_10 75 | |
514 | #define SYN_ULTRA_XFER_NS_11 82 | |
515 | #define SYN_ULTRA_XFER_NS_12 88 | |
516 | #define SYN_ULTRA_XFER_NS_13 94 | |
517 | #define SYN_ULTRA_XFER_NS_14 100 | |
518 | #define SYN_ULTRA_XFER_NS_15 107 | |
519 | ||
520 | typedef struct ext_msg { | |
27c868c2 MW |
521 | uchar msg_type; |
522 | uchar msg_len; | |
523 | uchar msg_req; | |
524 | union { | |
525 | struct { | |
526 | uchar sdtr_xfer_period; | |
527 | uchar sdtr_req_ack_offset; | |
528 | } sdtr; | |
529 | struct { | |
530 | uchar wdtr_width; | |
531 | } wdtr; | |
532 | struct { | |
533 | uchar mdp_b3; | |
534 | uchar mdp_b2; | |
535 | uchar mdp_b1; | |
536 | uchar mdp_b0; | |
537 | } mdp; | |
538 | } u_ext_msg; | |
539 | uchar res; | |
1da177e4 LT |
540 | } EXT_MSG; |
541 | ||
542 | #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period | |
543 | #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset | |
544 | #define wdtr_width u_ext_msg.wdtr.wdtr_width | |
545 | #define mdp_b3 u_ext_msg.mdp_b3 | |
546 | #define mdp_b2 u_ext_msg.mdp_b2 | |
547 | #define mdp_b1 u_ext_msg.mdp_b1 | |
548 | #define mdp_b0 u_ext_msg.mdp_b0 | |
549 | ||
550 | typedef struct asc_dvc_cfg { | |
27c868c2 MW |
551 | ASC_SCSI_BIT_ID_TYPE can_tagged_qng; |
552 | ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled; | |
553 | ASC_SCSI_BIT_ID_TYPE disc_enable; | |
554 | ASC_SCSI_BIT_ID_TYPE sdtr_enable; | |
555 | uchar chip_scsi_id; | |
556 | uchar isa_dma_speed; | |
557 | uchar isa_dma_channel; | |
558 | uchar chip_version; | |
559 | ushort lib_serial_no; | |
560 | ushort lib_version; | |
561 | ushort mcode_date; | |
562 | ushort mcode_version; | |
563 | uchar max_tag_qng[ASC_MAX_TID + 1]; | |
564 | uchar *overrun_buf; | |
565 | uchar sdtr_period_offset[ASC_MAX_TID + 1]; | |
27c868c2 | 566 | uchar adapter_info[6]; |
1da177e4 LT |
567 | } ASC_DVC_CFG; |
568 | ||
569 | #define ASC_DEF_DVC_CNTL 0xFFFF | |
570 | #define ASC_DEF_CHIP_SCSI_ID 7 | |
571 | #define ASC_DEF_ISA_DMA_SPEED 4 | |
1da177e4 LT |
572 | #define ASC_INIT_STATE_BEG_GET_CFG 0x0001 |
573 | #define ASC_INIT_STATE_END_GET_CFG 0x0002 | |
574 | #define ASC_INIT_STATE_BEG_SET_CFG 0x0004 | |
575 | #define ASC_INIT_STATE_END_SET_CFG 0x0008 | |
576 | #define ASC_INIT_STATE_BEG_LOAD_MC 0x0010 | |
577 | #define ASC_INIT_STATE_END_LOAD_MC 0x0020 | |
578 | #define ASC_INIT_STATE_BEG_INQUIRY 0x0040 | |
579 | #define ASC_INIT_STATE_END_INQUIRY 0x0080 | |
580 | #define ASC_INIT_RESET_SCSI_DONE 0x0100 | |
581 | #define ASC_INIT_STATE_WITHOUT_EEP 0x8000 | |
1da177e4 LT |
582 | #define ASC_BUG_FIX_IF_NOT_DWB 0x0001 |
583 | #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002 | |
584 | #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41 | |
585 | #define ASC_MIN_TAGGED_CMD 7 | |
586 | #define ASC_MAX_SCSI_RESET_WAIT 30 | |
587 | ||
27c868c2 | 588 | struct asc_dvc_var; /* Forward Declaration. */ |
1da177e4 | 589 | |
1da177e4 | 590 | typedef struct asc_dvc_var { |
27c868c2 MW |
591 | PortAddr iop_base; |
592 | ushort err_code; | |
593 | ushort dvc_cntl; | |
594 | ushort bug_fix_cntl; | |
595 | ushort bus_type; | |
27c868c2 MW |
596 | ASC_SCSI_BIT_ID_TYPE init_sdtr; |
597 | ASC_SCSI_BIT_ID_TYPE sdtr_done; | |
598 | ASC_SCSI_BIT_ID_TYPE use_tagged_qng; | |
599 | ASC_SCSI_BIT_ID_TYPE unit_not_ready; | |
600 | ASC_SCSI_BIT_ID_TYPE queue_full_or_busy; | |
601 | ASC_SCSI_BIT_ID_TYPE start_motor; | |
602 | uchar scsi_reset_wait; | |
603 | uchar chip_no; | |
604 | char is_in_int; | |
605 | uchar max_total_qng; | |
606 | uchar cur_total_qng; | |
607 | uchar in_critical_cnt; | |
608 | uchar irq_no; | |
609 | uchar last_q_shortage; | |
610 | ushort init_state; | |
611 | uchar cur_dvc_qng[ASC_MAX_TID + 1]; | |
612 | uchar max_dvc_qng[ASC_MAX_TID + 1]; | |
613 | ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1]; | |
614 | ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1]; | |
615 | uchar sdtr_period_tbl[ASC_MAX_SYN_XFER_NO]; | |
616 | ASC_DVC_CFG *cfg; | |
617 | ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always; | |
618 | char redo_scam; | |
619 | ushort res2; | |
620 | uchar dos_int13_table[ASC_MAX_TID + 1]; | |
621 | ASC_DCNT max_dma_count; | |
622 | ASC_SCSI_BIT_ID_TYPE no_scam; | |
623 | ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer; | |
624 | uchar max_sdtr_index; | |
625 | uchar host_init_sdtr_index; | |
626 | struct asc_board *drv_ptr; | |
627 | ASC_DCNT uc_break; | |
1da177e4 LT |
628 | } ASC_DVC_VAR; |
629 | ||
630 | typedef struct asc_dvc_inq_info { | |
27c868c2 | 631 | uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1]; |
1da177e4 LT |
632 | } ASC_DVC_INQ_INFO; |
633 | ||
634 | typedef struct asc_cap_info { | |
27c868c2 MW |
635 | ASC_DCNT lba; |
636 | ASC_DCNT blk_size; | |
1da177e4 LT |
637 | } ASC_CAP_INFO; |
638 | ||
639 | typedef struct asc_cap_info_array { | |
27c868c2 | 640 | ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1]; |
1da177e4 LT |
641 | } ASC_CAP_INFO_ARRAY; |
642 | ||
643 | #define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001 | |
644 | #define ASC_MCNTL_NULL_TARGET (ushort)0x0002 | |
645 | #define ASC_CNTL_INITIATOR (ushort)0x0001 | |
646 | #define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002 | |
647 | #define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004 | |
648 | #define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008 | |
649 | #define ASC_CNTL_NO_SCAM (ushort)0x0010 | |
650 | #define ASC_CNTL_INT_MULTI_Q (ushort)0x0080 | |
651 | #define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040 | |
652 | #define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100 | |
653 | #define ASC_CNTL_RESET_SCSI (ushort)0x0200 | |
654 | #define ASC_CNTL_INIT_INQUIRY (ushort)0x0400 | |
655 | #define ASC_CNTL_INIT_VERBOSE (ushort)0x0800 | |
656 | #define ASC_CNTL_SCSI_PARITY (ushort)0x1000 | |
657 | #define ASC_CNTL_BURST_MODE (ushort)0x2000 | |
658 | #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000 | |
659 | #define ASC_EEP_DVC_CFG_BEG_VL 2 | |
660 | #define ASC_EEP_MAX_DVC_ADDR_VL 15 | |
661 | #define ASC_EEP_DVC_CFG_BEG 32 | |
662 | #define ASC_EEP_MAX_DVC_ADDR 45 | |
1da177e4 | 663 | #define ASC_EEP_MAX_RETRY 20 |
1da177e4 LT |
664 | |
665 | /* | |
666 | * These macros keep the chip SCSI id and ISA DMA speed | |
667 | * bitfields in board order. C bitfields aren't portable | |
668 | * between big and little-endian platforms so they are | |
669 | * not used. | |
670 | */ | |
671 | ||
672 | #define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f) | |
673 | #define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4) | |
674 | #define ASC_EEP_SET_CHIP_ID(cfg, sid) \ | |
675 | ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID)) | |
676 | #define ASC_EEP_SET_DMA_SPD(cfg, spd) \ | |
677 | ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4) | |
678 | ||
679 | typedef struct asceep_config { | |
27c868c2 MW |
680 | ushort cfg_lsw; |
681 | ushort cfg_msw; | |
682 | uchar init_sdtr; | |
683 | uchar disc_enable; | |
684 | uchar use_cmd_qng; | |
685 | uchar start_motor; | |
686 | uchar max_total_qng; | |
687 | uchar max_tag_qng; | |
688 | uchar bios_scan; | |
689 | uchar power_up_wait; | |
690 | uchar no_scam; | |
691 | uchar id_speed; /* low order 4 bits is chip scsi id */ | |
692 | /* high order 4 bits is isa dma speed */ | |
693 | uchar dos_int13_table[ASC_MAX_TID + 1]; | |
694 | uchar adapter_info[6]; | |
695 | ushort cntl; | |
696 | ushort chksum; | |
1da177e4 LT |
697 | } ASCEEP_CONFIG; |
698 | ||
1da177e4 LT |
699 | #define ASC_EEP_CMD_READ 0x80 |
700 | #define ASC_EEP_CMD_WRITE 0x40 | |
701 | #define ASC_EEP_CMD_WRITE_ABLE 0x30 | |
702 | #define ASC_EEP_CMD_WRITE_DISABLE 0x00 | |
703 | #define ASC_OVERRUN_BSIZE 0x00000048UL | |
1da177e4 LT |
704 | #define ASCV_MSGOUT_BEG 0x0000 |
705 | #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3) | |
706 | #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4) | |
707 | #define ASCV_BREAK_SAVED_CODE (ushort)0x0006 | |
708 | #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8) | |
709 | #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3) | |
710 | #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4) | |
711 | #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8) | |
712 | #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8) | |
713 | #define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020 | |
714 | #define ASCV_BREAK_ADDR (ushort)0x0028 | |
715 | #define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A | |
716 | #define ASCV_BREAK_CONTROL (ushort)0x002C | |
717 | #define ASCV_BREAK_HIT_COUNT (ushort)0x002E | |
718 | ||
719 | #define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030 | |
720 | #define ASCV_MCODE_CHKSUM_W (ushort)0x0032 | |
721 | #define ASCV_MCODE_SIZE_W (ushort)0x0034 | |
722 | #define ASCV_STOP_CODE_B (ushort)0x0036 | |
723 | #define ASCV_DVC_ERR_CODE_B (ushort)0x0037 | |
724 | #define ASCV_OVERRUN_PADDR_D (ushort)0x0038 | |
725 | #define ASCV_OVERRUN_BSIZE_D (ushort)0x003C | |
726 | #define ASCV_HALTCODE_W (ushort)0x0040 | |
727 | #define ASCV_CHKSUM_W (ushort)0x0042 | |
728 | #define ASCV_MC_DATE_W (ushort)0x0044 | |
729 | #define ASCV_MC_VER_W (ushort)0x0046 | |
730 | #define ASCV_NEXTRDY_B (ushort)0x0048 | |
731 | #define ASCV_DONENEXT_B (ushort)0x0049 | |
732 | #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A | |
733 | #define ASCV_SCSIBUSY_B (ushort)0x004B | |
734 | #define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C | |
735 | #define ASCV_CURCDB_B (ushort)0x004D | |
736 | #define ASCV_RCLUN_B (ushort)0x004E | |
737 | #define ASCV_BUSY_QHEAD_B (ushort)0x004F | |
738 | #define ASCV_DISC1_QHEAD_B (ushort)0x0050 | |
739 | #define ASCV_DISC_ENABLE_B (ushort)0x0052 | |
740 | #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053 | |
741 | #define ASCV_HOSTSCSI_ID_B (ushort)0x0055 | |
742 | #define ASCV_MCODE_CNTL_B (ushort)0x0056 | |
743 | #define ASCV_NULL_TARGET_B (ushort)0x0057 | |
744 | #define ASCV_FREE_Q_HEAD_W (ushort)0x0058 | |
745 | #define ASCV_DONE_Q_TAIL_W (ushort)0x005A | |
746 | #define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1) | |
747 | #define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1) | |
748 | #define ASCV_HOST_FLAG_B (ushort)0x005D | |
749 | #define ASCV_TOTAL_READY_Q_B (ushort)0x0064 | |
750 | #define ASCV_VER_SERIAL_B (ushort)0x0065 | |
751 | #define ASCV_HALTCODE_SAVED_W (ushort)0x0066 | |
752 | #define ASCV_WTM_FLAG_B (ushort)0x0068 | |
753 | #define ASCV_RISC_FLAG_B (ushort)0x006A | |
754 | #define ASCV_REQ_SG_LIST_QP (ushort)0x006B | |
755 | #define ASC_HOST_FLAG_IN_ISR 0x01 | |
756 | #define ASC_HOST_FLAG_ACK_INT 0x02 | |
757 | #define ASC_RISC_FLAG_GEN_INT 0x01 | |
758 | #define ASC_RISC_FLAG_REQ_SG_LIST 0x02 | |
759 | #define IOP_CTRL (0x0F) | |
760 | #define IOP_STATUS (0x0E) | |
761 | #define IOP_INT_ACK IOP_STATUS | |
762 | #define IOP_REG_IFC (0x0D) | |
763 | #define IOP_SYN_OFFSET (0x0B) | |
764 | #define IOP_EXTRA_CONTROL (0x0D) | |
765 | #define IOP_REG_PC (0x0C) | |
766 | #define IOP_RAM_ADDR (0x0A) | |
767 | #define IOP_RAM_DATA (0x08) | |
768 | #define IOP_EEP_DATA (0x06) | |
769 | #define IOP_EEP_CMD (0x07) | |
770 | #define IOP_VERSION (0x03) | |
771 | #define IOP_CONFIG_HIGH (0x04) | |
772 | #define IOP_CONFIG_LOW (0x02) | |
773 | #define IOP_SIG_BYTE (0x01) | |
774 | #define IOP_SIG_WORD (0x00) | |
775 | #define IOP_REG_DC1 (0x0E) | |
776 | #define IOP_REG_DC0 (0x0C) | |
777 | #define IOP_REG_SB (0x0B) | |
778 | #define IOP_REG_DA1 (0x0A) | |
779 | #define IOP_REG_DA0 (0x08) | |
780 | #define IOP_REG_SC (0x09) | |
781 | #define IOP_DMA_SPEED (0x07) | |
782 | #define IOP_REG_FLAG (0x07) | |
783 | #define IOP_FIFO_H (0x06) | |
784 | #define IOP_FIFO_L (0x04) | |
785 | #define IOP_REG_ID (0x05) | |
786 | #define IOP_REG_QP (0x03) | |
787 | #define IOP_REG_IH (0x02) | |
788 | #define IOP_REG_IX (0x01) | |
789 | #define IOP_REG_AX (0x00) | |
790 | #define IFC_REG_LOCK (0x00) | |
791 | #define IFC_REG_UNLOCK (0x09) | |
792 | #define IFC_WR_EN_FILTER (0x10) | |
793 | #define IFC_RD_NO_EEPROM (0x10) | |
794 | #define IFC_SLEW_RATE (0x20) | |
795 | #define IFC_ACT_NEG (0x40) | |
796 | #define IFC_INP_FILTER (0x80) | |
797 | #define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK) | |
798 | #define SC_SEL (uchar)(0x80) | |
799 | #define SC_BSY (uchar)(0x40) | |
800 | #define SC_ACK (uchar)(0x20) | |
801 | #define SC_REQ (uchar)(0x10) | |
802 | #define SC_ATN (uchar)(0x08) | |
803 | #define SC_IO (uchar)(0x04) | |
804 | #define SC_CD (uchar)(0x02) | |
805 | #define SC_MSG (uchar)(0x01) | |
806 | #define SEC_SCSI_CTL (uchar)(0x80) | |
807 | #define SEC_ACTIVE_NEGATE (uchar)(0x40) | |
808 | #define SEC_SLEW_RATE (uchar)(0x20) | |
809 | #define SEC_ENABLE_FILTER (uchar)(0x10) | |
810 | #define ASC_HALT_EXTMSG_IN (ushort)0x8000 | |
811 | #define ASC_HALT_CHK_CONDITION (ushort)0x8100 | |
812 | #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200 | |
813 | #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300 | |
814 | #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400 | |
815 | #define ASC_HALT_SDTR_REJECTED (ushort)0x4000 | |
816 | #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000 | |
817 | #define ASC_MAX_QNO 0xF8 | |
818 | #define ASC_DATA_SEC_BEG (ushort)0x0080 | |
819 | #define ASC_DATA_SEC_END (ushort)0x0080 | |
820 | #define ASC_CODE_SEC_BEG (ushort)0x0080 | |
821 | #define ASC_CODE_SEC_END (ushort)0x0080 | |
822 | #define ASC_QADR_BEG (0x4000) | |
823 | #define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64) | |
824 | #define ASC_QADR_END (ushort)0x7FFF | |
825 | #define ASC_QLAST_ADR (ushort)0x7FC0 | |
826 | #define ASC_QBLK_SIZE 0x40 | |
827 | #define ASC_BIOS_DATA_QBEG 0xF8 | |
828 | #define ASC_MIN_ACTIVE_QNO 0x01 | |
829 | #define ASC_QLINK_END 0xFF | |
830 | #define ASC_EEPROM_WORDS 0x10 | |
831 | #define ASC_MAX_MGS_LEN 0x10 | |
832 | #define ASC_BIOS_ADDR_DEF 0xDC00 | |
833 | #define ASC_BIOS_SIZE 0x3800 | |
834 | #define ASC_BIOS_RAM_OFF 0x3800 | |
835 | #define ASC_BIOS_RAM_SIZE 0x800 | |
836 | #define ASC_BIOS_MIN_ADDR 0xC000 | |
837 | #define ASC_BIOS_MAX_ADDR 0xEC00 | |
838 | #define ASC_BIOS_BANK_SIZE 0x0400 | |
839 | #define ASC_MCODE_START_ADDR 0x0080 | |
840 | #define ASC_CFG0_HOST_INT_ON 0x0020 | |
841 | #define ASC_CFG0_BIOS_ON 0x0040 | |
842 | #define ASC_CFG0_VERA_BURST_ON 0x0080 | |
843 | #define ASC_CFG0_SCSI_PARITY_ON 0x0800 | |
844 | #define ASC_CFG1_SCSI_TARGET_ON 0x0080 | |
845 | #define ASC_CFG1_LRAM_8BITS_ON 0x0800 | |
846 | #define ASC_CFG_MSW_CLR_MASK 0x3080 | |
847 | #define CSW_TEST1 (ASC_CS_TYPE)0x8000 | |
848 | #define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000 | |
849 | #define CSW_RESERVED1 (ASC_CS_TYPE)0x2000 | |
850 | #define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000 | |
851 | #define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800 | |
852 | #define CSW_TEST2 (ASC_CS_TYPE)0x0400 | |
853 | #define CSW_TEST3 (ASC_CS_TYPE)0x0200 | |
854 | #define CSW_RESERVED2 (ASC_CS_TYPE)0x0100 | |
855 | #define CSW_DMA_DONE (ASC_CS_TYPE)0x0080 | |
856 | #define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040 | |
857 | #define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020 | |
858 | #define CSW_HALTED (ASC_CS_TYPE)0x0010 | |
859 | #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008 | |
860 | #define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004 | |
861 | #define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002 | |
862 | #define CSW_INT_PENDING (ASC_CS_TYPE)0x0001 | |
863 | #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000 | |
864 | #define CIW_INT_ACK (ASC_CS_TYPE)0x0100 | |
865 | #define CIW_TEST1 (ASC_CS_TYPE)0x0200 | |
866 | #define CIW_TEST2 (ASC_CS_TYPE)0x0400 | |
867 | #define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800 | |
868 | #define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000 | |
869 | #define CC_CHIP_RESET (uchar)0x80 | |
870 | #define CC_SCSI_RESET (uchar)0x40 | |
871 | #define CC_HALT (uchar)0x20 | |
872 | #define CC_SINGLE_STEP (uchar)0x10 | |
873 | #define CC_DMA_ABLE (uchar)0x08 | |
874 | #define CC_TEST (uchar)0x04 | |
875 | #define CC_BANK_ONE (uchar)0x02 | |
876 | #define CC_DIAG (uchar)0x01 | |
877 | #define ASC_1000_ID0W 0x04C1 | |
878 | #define ASC_1000_ID0W_FIX 0x00C1 | |
879 | #define ASC_1000_ID1B 0x25 | |
1da177e4 | 880 | #define ASC_EISA_REV_IOP_MASK (0x0C83) |
1da177e4 LT |
881 | #define ASC_EISA_CFG_IOP_MASK (0x0C86) |
882 | #define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000) | |
1da177e4 LT |
883 | #define INS_HALTINT (ushort)0x6281 |
884 | #define INS_HALT (ushort)0x6280 | |
885 | #define INS_SINT (ushort)0x6200 | |
886 | #define INS_RFLAG_WTM (ushort)0x7380 | |
887 | #define ASC_MC_SAVE_CODE_WSIZE 0x500 | |
888 | #define ASC_MC_SAVE_DATA_WSIZE 0x40 | |
889 | ||
890 | typedef struct asc_mc_saved { | |
27c868c2 MW |
891 | ushort data[ASC_MC_SAVE_DATA_WSIZE]; |
892 | ushort code[ASC_MC_SAVE_CODE_WSIZE]; | |
1da177e4 LT |
893 | } ASC_MC_SAVED; |
894 | ||
895 | #define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B) | |
896 | #define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val) | |
897 | #define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W) | |
898 | #define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W) | |
899 | #define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val) | |
900 | #define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val) | |
901 | #define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B) | |
902 | #define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B) | |
903 | #define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val) | |
904 | #define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val) | |
51219358 MW |
905 | #define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data)) |
906 | #define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id)) | |
907 | #define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data) | |
908 | #define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id)) | |
1da177e4 LT |
909 | #define AscSynIndexToPeriod(index) (uchar)(asc_dvc->sdtr_period_tbl[ (index) ]) |
910 | #define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE) | |
911 | #define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD) | |
912 | #define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION) | |
913 | #define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW) | |
914 | #define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH) | |
915 | #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data) | |
916 | #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data) | |
917 | #define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD) | |
918 | #define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data) | |
919 | #define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA) | |
920 | #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data) | |
921 | #define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR)) | |
922 | #define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr) | |
923 | #define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA) | |
924 | #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data) | |
925 | #define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC) | |
926 | #define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data) | |
927 | #define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS) | |
928 | #define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val) | |
929 | #define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL) | |
930 | #define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val) | |
931 | #define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET) | |
932 | #define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data) | |
933 | #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data) | |
934 | #define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC) | |
935 | #define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH)) | |
936 | #define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID) | |
937 | #define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL) | |
938 | #define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data) | |
939 | #define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX) | |
940 | #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data) | |
941 | #define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX) | |
942 | #define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data) | |
943 | #define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH) | |
944 | #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data) | |
945 | #define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP) | |
946 | #define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data) | |
947 | #define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L) | |
948 | #define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data) | |
949 | #define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H) | |
950 | #define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data) | |
951 | #define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED) | |
952 | #define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data) | |
953 | #define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0) | |
954 | #define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data) | |
955 | #define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1) | |
956 | #define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data) | |
957 | #define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0) | |
958 | #define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data) | |
959 | #define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1) | |
960 | #define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data) | |
961 | #define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID) | |
962 | #define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data) | |
963 | ||
1da177e4 LT |
964 | #define ADV_LIB_VERSION_MAJOR 5 |
965 | #define ADV_LIB_VERSION_MINOR 14 | |
966 | ||
967 | /* | |
968 | * Define Adv Library required special types. | |
969 | */ | |
970 | ||
971 | /* | |
972 | * Portable Data Types | |
973 | * | |
974 | * Any instance where a 32-bit long or pointer type is assumed | |
975 | * for precision or HW defined structures, the following define | |
976 | * types must be used. In Linux the char, short, and int types | |
977 | * are all consistent at 8, 16, and 32 bits respectively. Pointers | |
978 | * and long types are 64 bits on Alpha and UltraSPARC. | |
979 | */ | |
27c868c2 MW |
980 | #define ADV_PADDR __u32 /* Physical address data type. */ |
981 | #define ADV_VADDR __u32 /* Virtual address data type. */ | |
982 | #define ADV_DCNT __u32 /* Unsigned Data count type. */ | |
983 | #define ADV_SDCNT __s32 /* Signed Data count type. */ | |
1da177e4 LT |
984 | |
985 | /* | |
986 | * These macros are used to convert a virtual address to a | |
987 | * 32-bit value. This currently can be used on Linux Alpha | |
988 | * which uses 64-bit virtual address but a 32-bit bus address. | |
989 | * This is likely to break in the future, but doing this now | |
990 | * will give us time to change the HW and FW to handle 64-bit | |
991 | * addresses. | |
992 | */ | |
993 | #define ADV_VADDR_TO_U32 virt_to_bus | |
994 | #define ADV_U32_TO_VADDR bus_to_virt | |
995 | ||
27c868c2 | 996 | #define AdvPortAddr void __iomem * /* Virtual memory address size */ |
1da177e4 LT |
997 | |
998 | /* | |
999 | * Define Adv Library required memory access macros. | |
1000 | */ | |
1001 | #define ADV_MEM_READB(addr) readb(addr) | |
1002 | #define ADV_MEM_READW(addr) readw(addr) | |
1003 | #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr) | |
1004 | #define ADV_MEM_WRITEW(addr, word) writew(word, addr) | |
1005 | #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr) | |
1006 | ||
1007 | #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 15) | |
1008 | ||
1da177e4 LT |
1009 | /* |
1010 | * Define total number of simultaneous maximum element scatter-gather | |
1011 | * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the | |
1012 | * maximum number of outstanding commands per wide host adapter. Each | |
1013 | * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather | |
1014 | * elements. Allow each command to have at least one ADV_SG_BLOCK structure. | |
1015 | * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK | |
1016 | * structures or 255 scatter-gather elements. | |
1017 | * | |
1018 | */ | |
1019 | #define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG | |
1020 | ||
1021 | /* | |
1022 | * Define Adv Library required maximum number of scatter-gather | |
1023 | * elements per request. | |
1024 | */ | |
1025 | #define ADV_MAX_SG_LIST 255 | |
1026 | ||
1027 | /* Number of SG blocks needed. */ | |
1028 | #define ADV_NUM_SG_BLOCK \ | |
1029 | ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK) | |
1030 | ||
1031 | /* Total contiguous memory needed for SG blocks. */ | |
1032 | #define ADV_SG_TOTAL_MEM_SIZE \ | |
1033 | (sizeof(ADV_SG_BLOCK) * ADV_NUM_SG_BLOCK) | |
1034 | ||
1035 | #define ADV_PAGE_SIZE PAGE_SIZE | |
1036 | ||
1037 | #define ADV_NUM_PAGE_CROSSING \ | |
1038 | ((ADV_SG_TOTAL_MEM_SIZE + (ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE) | |
1039 | ||
1da177e4 LT |
1040 | #define ADV_EEP_DVC_CFG_BEGIN (0x00) |
1041 | #define ADV_EEP_DVC_CFG_END (0x15) | |
27c868c2 | 1042 | #define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */ |
1da177e4 LT |
1043 | #define ADV_EEP_MAX_WORD_ADDR (0x1E) |
1044 | ||
1045 | #define ADV_EEP_DELAY_MS 100 | |
1046 | ||
27c868c2 MW |
1047 | #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */ |
1048 | #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */ | |
1da177e4 LT |
1049 | /* |
1050 | * For the ASC3550 Bit 13 is Termination Polarity control bit. | |
1051 | * For later ICs Bit 13 controls whether the CIS (Card Information | |
1052 | * Service Section) is loaded from EEPROM. | |
1053 | */ | |
27c868c2 MW |
1054 | #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */ |
1055 | #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */ | |
1da177e4 LT |
1056 | /* |
1057 | * ASC38C1600 Bit 11 | |
1058 | * | |
1059 | * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify | |
1060 | * INT A in the PCI Configuration Space Int Pin field. If it is 1, then | |
1061 | * Function 0 will specify INT B. | |
1062 | * | |
1063 | * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify | |
1064 | * INT B in the PCI Configuration Space Int Pin field. If it is 1, then | |
1065 | * Function 1 will specify INT A. | |
1066 | */ | |
27c868c2 MW |
1067 | #define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */ |
1068 | ||
1069 | typedef struct adveep_3550_config { | |
1070 | /* Word Offset, Description */ | |
1071 | ||
1072 | ushort cfg_lsw; /* 00 power up initialization */ | |
1073 | /* bit 13 set - Term Polarity Control */ | |
1074 | /* bit 14 set - BIOS Enable */ | |
1075 | /* bit 15 set - Big Endian Mode */ | |
1076 | ushort cfg_msw; /* 01 unused */ | |
1077 | ushort disc_enable; /* 02 disconnect enable */ | |
1078 | ushort wdtr_able; /* 03 Wide DTR able */ | |
1079 | ushort sdtr_able; /* 04 Synchronous DTR able */ | |
1080 | ushort start_motor; /* 05 send start up motor */ | |
1081 | ushort tagqng_able; /* 06 tag queuing able */ | |
1082 | ushort bios_scan; /* 07 BIOS device control */ | |
1083 | ushort scam_tolerant; /* 08 no scam */ | |
1084 | ||
1085 | uchar adapter_scsi_id; /* 09 Host Adapter ID */ | |
1086 | uchar bios_boot_delay; /* power up wait */ | |
1087 | ||
1088 | uchar scsi_reset_delay; /* 10 reset delay */ | |
1089 | uchar bios_id_lun; /* first boot device scsi id & lun */ | |
1090 | /* high nibble is lun */ | |
1091 | /* low nibble is scsi id */ | |
1092 | ||
1093 | uchar termination; /* 11 0 - automatic */ | |
1094 | /* 1 - low off / high off */ | |
1095 | /* 2 - low off / high on */ | |
1096 | /* 3 - low on / high on */ | |
1097 | /* There is no low on / high off */ | |
1098 | ||
1099 | uchar reserved1; /* reserved byte (not used) */ | |
1100 | ||
1101 | ushort bios_ctrl; /* 12 BIOS control bits */ | |
1102 | /* bit 0 BIOS don't act as initiator. */ | |
1103 | /* bit 1 BIOS > 1 GB support */ | |
1104 | /* bit 2 BIOS > 2 Disk Support */ | |
1105 | /* bit 3 BIOS don't support removables */ | |
1106 | /* bit 4 BIOS support bootable CD */ | |
1107 | /* bit 5 BIOS scan enabled */ | |
1108 | /* bit 6 BIOS support multiple LUNs */ | |
1109 | /* bit 7 BIOS display of message */ | |
1110 | /* bit 8 SCAM disabled */ | |
1111 | /* bit 9 Reset SCSI bus during init. */ | |
1112 | /* bit 10 */ | |
1113 | /* bit 11 No verbose initialization. */ | |
1114 | /* bit 12 SCSI parity enabled */ | |
1115 | /* bit 13 */ | |
1116 | /* bit 14 */ | |
1117 | /* bit 15 */ | |
1118 | ushort ultra_able; /* 13 ULTRA speed able */ | |
1119 | ushort reserved2; /* 14 reserved */ | |
1120 | uchar max_host_qng; /* 15 maximum host queuing */ | |
1121 | uchar max_dvc_qng; /* maximum per device queuing */ | |
1122 | ushort dvc_cntl; /* 16 control bit for driver */ | |
1123 | ushort bug_fix; /* 17 control bit for bug fix */ | |
1124 | ushort serial_number_word1; /* 18 Board serial number word 1 */ | |
1125 | ushort serial_number_word2; /* 19 Board serial number word 2 */ | |
1126 | ushort serial_number_word3; /* 20 Board serial number word 3 */ | |
1127 | ushort check_sum; /* 21 EEP check sum */ | |
1128 | uchar oem_name[16]; /* 22 OEM name */ | |
1129 | ushort dvc_err_code; /* 30 last device driver error code */ | |
1130 | ushort adv_err_code; /* 31 last uc and Adv Lib error code */ | |
1131 | ushort adv_err_addr; /* 32 last uc error address */ | |
1132 | ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */ | |
1133 | ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */ | |
1134 | ushort saved_adv_err_addr; /* 35 saved last uc error address */ | |
1135 | ushort num_of_err; /* 36 number of error */ | |
1da177e4 LT |
1136 | } ADVEEP_3550_CONFIG; |
1137 | ||
27c868c2 MW |
1138 | typedef struct adveep_38C0800_config { |
1139 | /* Word Offset, Description */ | |
1140 | ||
1141 | ushort cfg_lsw; /* 00 power up initialization */ | |
1142 | /* bit 13 set - Load CIS */ | |
1143 | /* bit 14 set - BIOS Enable */ | |
1144 | /* bit 15 set - Big Endian Mode */ | |
1145 | ushort cfg_msw; /* 01 unused */ | |
1146 | ushort disc_enable; /* 02 disconnect enable */ | |
1147 | ushort wdtr_able; /* 03 Wide DTR able */ | |
1148 | ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */ | |
1149 | ushort start_motor; /* 05 send start up motor */ | |
1150 | ushort tagqng_able; /* 06 tag queuing able */ | |
1151 | ushort bios_scan; /* 07 BIOS device control */ | |
1152 | ushort scam_tolerant; /* 08 no scam */ | |
1153 | ||
1154 | uchar adapter_scsi_id; /* 09 Host Adapter ID */ | |
1155 | uchar bios_boot_delay; /* power up wait */ | |
1156 | ||
1157 | uchar scsi_reset_delay; /* 10 reset delay */ | |
1158 | uchar bios_id_lun; /* first boot device scsi id & lun */ | |
1159 | /* high nibble is lun */ | |
1160 | /* low nibble is scsi id */ | |
1161 | ||
1162 | uchar termination_se; /* 11 0 - automatic */ | |
1163 | /* 1 - low off / high off */ | |
1164 | /* 2 - low off / high on */ | |
1165 | /* 3 - low on / high on */ | |
1166 | /* There is no low on / high off */ | |
1167 | ||
1168 | uchar termination_lvd; /* 11 0 - automatic */ | |
1169 | /* 1 - low off / high off */ | |
1170 | /* 2 - low off / high on */ | |
1171 | /* 3 - low on / high on */ | |
1172 | /* There is no low on / high off */ | |
1173 | ||
1174 | ushort bios_ctrl; /* 12 BIOS control bits */ | |
1175 | /* bit 0 BIOS don't act as initiator. */ | |
1176 | /* bit 1 BIOS > 1 GB support */ | |
1177 | /* bit 2 BIOS > 2 Disk Support */ | |
1178 | /* bit 3 BIOS don't support removables */ | |
1179 | /* bit 4 BIOS support bootable CD */ | |
1180 | /* bit 5 BIOS scan enabled */ | |
1181 | /* bit 6 BIOS support multiple LUNs */ | |
1182 | /* bit 7 BIOS display of message */ | |
1183 | /* bit 8 SCAM disabled */ | |
1184 | /* bit 9 Reset SCSI bus during init. */ | |
1185 | /* bit 10 */ | |
1186 | /* bit 11 No verbose initialization. */ | |
1187 | /* bit 12 SCSI parity enabled */ | |
1188 | /* bit 13 */ | |
1189 | /* bit 14 */ | |
1190 | /* bit 15 */ | |
1191 | ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */ | |
1192 | ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */ | |
1193 | uchar max_host_qng; /* 15 maximum host queueing */ | |
1194 | uchar max_dvc_qng; /* maximum per device queuing */ | |
1195 | ushort dvc_cntl; /* 16 control bit for driver */ | |
1196 | ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */ | |
1197 | ushort serial_number_word1; /* 18 Board serial number word 1 */ | |
1198 | ushort serial_number_word2; /* 19 Board serial number word 2 */ | |
1199 | ushort serial_number_word3; /* 20 Board serial number word 3 */ | |
1200 | ushort check_sum; /* 21 EEP check sum */ | |
1201 | uchar oem_name[16]; /* 22 OEM name */ | |
1202 | ushort dvc_err_code; /* 30 last device driver error code */ | |
1203 | ushort adv_err_code; /* 31 last uc and Adv Lib error code */ | |
1204 | ushort adv_err_addr; /* 32 last uc error address */ | |
1205 | ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */ | |
1206 | ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */ | |
1207 | ushort saved_adv_err_addr; /* 35 saved last uc error address */ | |
1208 | ushort reserved36; /* 36 reserved */ | |
1209 | ushort reserved37; /* 37 reserved */ | |
1210 | ushort reserved38; /* 38 reserved */ | |
1211 | ushort reserved39; /* 39 reserved */ | |
1212 | ushort reserved40; /* 40 reserved */ | |
1213 | ushort reserved41; /* 41 reserved */ | |
1214 | ushort reserved42; /* 42 reserved */ | |
1215 | ushort reserved43; /* 43 reserved */ | |
1216 | ushort reserved44; /* 44 reserved */ | |
1217 | ushort reserved45; /* 45 reserved */ | |
1218 | ushort reserved46; /* 46 reserved */ | |
1219 | ushort reserved47; /* 47 reserved */ | |
1220 | ushort reserved48; /* 48 reserved */ | |
1221 | ushort reserved49; /* 49 reserved */ | |
1222 | ushort reserved50; /* 50 reserved */ | |
1223 | ushort reserved51; /* 51 reserved */ | |
1224 | ushort reserved52; /* 52 reserved */ | |
1225 | ushort reserved53; /* 53 reserved */ | |
1226 | ushort reserved54; /* 54 reserved */ | |
1227 | ushort reserved55; /* 55 reserved */ | |
1228 | ushort cisptr_lsw; /* 56 CIS PTR LSW */ | |
1229 | ushort cisprt_msw; /* 57 CIS PTR MSW */ | |
1230 | ushort subsysvid; /* 58 SubSystem Vendor ID */ | |
1231 | ushort subsysid; /* 59 SubSystem ID */ | |
1232 | ushort reserved60; /* 60 reserved */ | |
1233 | ushort reserved61; /* 61 reserved */ | |
1234 | ushort reserved62; /* 62 reserved */ | |
1235 | ushort reserved63; /* 63 reserved */ | |
1da177e4 LT |
1236 | } ADVEEP_38C0800_CONFIG; |
1237 | ||
27c868c2 MW |
1238 | typedef struct adveep_38C1600_config { |
1239 | /* Word Offset, Description */ | |
1240 | ||
1241 | ushort cfg_lsw; /* 00 power up initialization */ | |
1242 | /* bit 11 set - Func. 0 INTB, Func. 1 INTA */ | |
1243 | /* clear - Func. 0 INTA, Func. 1 INTB */ | |
1244 | /* bit 13 set - Load CIS */ | |
1245 | /* bit 14 set - BIOS Enable */ | |
1246 | /* bit 15 set - Big Endian Mode */ | |
1247 | ushort cfg_msw; /* 01 unused */ | |
1248 | ushort disc_enable; /* 02 disconnect enable */ | |
1249 | ushort wdtr_able; /* 03 Wide DTR able */ | |
1250 | ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */ | |
1251 | ushort start_motor; /* 05 send start up motor */ | |
1252 | ushort tagqng_able; /* 06 tag queuing able */ | |
1253 | ushort bios_scan; /* 07 BIOS device control */ | |
1254 | ushort scam_tolerant; /* 08 no scam */ | |
1255 | ||
1256 | uchar adapter_scsi_id; /* 09 Host Adapter ID */ | |
1257 | uchar bios_boot_delay; /* power up wait */ | |
1258 | ||
1259 | uchar scsi_reset_delay; /* 10 reset delay */ | |
1260 | uchar bios_id_lun; /* first boot device scsi id & lun */ | |
1261 | /* high nibble is lun */ | |
1262 | /* low nibble is scsi id */ | |
1263 | ||
1264 | uchar termination_se; /* 11 0 - automatic */ | |
1265 | /* 1 - low off / high off */ | |
1266 | /* 2 - low off / high on */ | |
1267 | /* 3 - low on / high on */ | |
1268 | /* There is no low on / high off */ | |
1269 | ||
1270 | uchar termination_lvd; /* 11 0 - automatic */ | |
1271 | /* 1 - low off / high off */ | |
1272 | /* 2 - low off / high on */ | |
1273 | /* 3 - low on / high on */ | |
1274 | /* There is no low on / high off */ | |
1275 | ||
1276 | ushort bios_ctrl; /* 12 BIOS control bits */ | |
1277 | /* bit 0 BIOS don't act as initiator. */ | |
1278 | /* bit 1 BIOS > 1 GB support */ | |
1279 | /* bit 2 BIOS > 2 Disk Support */ | |
1280 | /* bit 3 BIOS don't support removables */ | |
1281 | /* bit 4 BIOS support bootable CD */ | |
1282 | /* bit 5 BIOS scan enabled */ | |
1283 | /* bit 6 BIOS support multiple LUNs */ | |
1284 | /* bit 7 BIOS display of message */ | |
1285 | /* bit 8 SCAM disabled */ | |
1286 | /* bit 9 Reset SCSI bus during init. */ | |
1287 | /* bit 10 Basic Integrity Checking disabled */ | |
1288 | /* bit 11 No verbose initialization. */ | |
1289 | /* bit 12 SCSI parity enabled */ | |
1290 | /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */ | |
1291 | /* bit 14 */ | |
1292 | /* bit 15 */ | |
1293 | ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */ | |
1294 | ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */ | |
1295 | uchar max_host_qng; /* 15 maximum host queueing */ | |
1296 | uchar max_dvc_qng; /* maximum per device queuing */ | |
1297 | ushort dvc_cntl; /* 16 control bit for driver */ | |
1298 | ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */ | |
1299 | ushort serial_number_word1; /* 18 Board serial number word 1 */ | |
1300 | ushort serial_number_word2; /* 19 Board serial number word 2 */ | |
1301 | ushort serial_number_word3; /* 20 Board serial number word 3 */ | |
1302 | ushort check_sum; /* 21 EEP check sum */ | |
1303 | uchar oem_name[16]; /* 22 OEM name */ | |
1304 | ushort dvc_err_code; /* 30 last device driver error code */ | |
1305 | ushort adv_err_code; /* 31 last uc and Adv Lib error code */ | |
1306 | ushort adv_err_addr; /* 32 last uc error address */ | |
1307 | ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */ | |
1308 | ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */ | |
1309 | ushort saved_adv_err_addr; /* 35 saved last uc error address */ | |
1310 | ushort reserved36; /* 36 reserved */ | |
1311 | ushort reserved37; /* 37 reserved */ | |
1312 | ushort reserved38; /* 38 reserved */ | |
1313 | ushort reserved39; /* 39 reserved */ | |
1314 | ushort reserved40; /* 40 reserved */ | |
1315 | ushort reserved41; /* 41 reserved */ | |
1316 | ushort reserved42; /* 42 reserved */ | |
1317 | ushort reserved43; /* 43 reserved */ | |
1318 | ushort reserved44; /* 44 reserved */ | |
1319 | ushort reserved45; /* 45 reserved */ | |
1320 | ushort reserved46; /* 46 reserved */ | |
1321 | ushort reserved47; /* 47 reserved */ | |
1322 | ushort reserved48; /* 48 reserved */ | |
1323 | ushort reserved49; /* 49 reserved */ | |
1324 | ushort reserved50; /* 50 reserved */ | |
1325 | ushort reserved51; /* 51 reserved */ | |
1326 | ushort reserved52; /* 52 reserved */ | |
1327 | ushort reserved53; /* 53 reserved */ | |
1328 | ushort reserved54; /* 54 reserved */ | |
1329 | ushort reserved55; /* 55 reserved */ | |
1330 | ushort cisptr_lsw; /* 56 CIS PTR LSW */ | |
1331 | ushort cisprt_msw; /* 57 CIS PTR MSW */ | |
1332 | ushort subsysvid; /* 58 SubSystem Vendor ID */ | |
1333 | ushort subsysid; /* 59 SubSystem ID */ | |
1334 | ushort reserved60; /* 60 reserved */ | |
1335 | ushort reserved61; /* 61 reserved */ | |
1336 | ushort reserved62; /* 62 reserved */ | |
1337 | ushort reserved63; /* 63 reserved */ | |
1da177e4 LT |
1338 | } ADVEEP_38C1600_CONFIG; |
1339 | ||
1340 | /* | |
1341 | * EEPROM Commands | |
1342 | */ | |
1343 | #define ASC_EEP_CMD_DONE 0x0200 | |
1da177e4 LT |
1344 | |
1345 | /* bios_ctrl */ | |
1346 | #define BIOS_CTRL_BIOS 0x0001 | |
1347 | #define BIOS_CTRL_EXTENDED_XLAT 0x0002 | |
1348 | #define BIOS_CTRL_GT_2_DISK 0x0004 | |
1349 | #define BIOS_CTRL_BIOS_REMOVABLE 0x0008 | |
1350 | #define BIOS_CTRL_BOOTABLE_CD 0x0010 | |
1351 | #define BIOS_CTRL_MULTIPLE_LUN 0x0040 | |
1352 | #define BIOS_CTRL_DISPLAY_MSG 0x0080 | |
1353 | #define BIOS_CTRL_NO_SCAM 0x0100 | |
1354 | #define BIOS_CTRL_RESET_SCSI_BUS 0x0200 | |
1355 | #define BIOS_CTRL_INIT_VERBOSE 0x0800 | |
1356 | #define BIOS_CTRL_SCSI_PARITY 0x1000 | |
1357 | #define BIOS_CTRL_AIPP_DIS 0x2000 | |
1358 | ||
27c868c2 | 1359 | #define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */ |
1da177e4 | 1360 | |
27c868c2 | 1361 | #define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */ |
1da177e4 LT |
1362 | |
1363 | /* | |
1364 | * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is | |
1365 | * a special 16K Adv Library and Microcode version. After the issue is | |
1366 | * resolved, should restore 32K support. | |
1367 | * | |
1368 | * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory * | |
1369 | */ | |
27c868c2 | 1370 | #define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */ |
1da177e4 LT |
1371 | |
1372 | /* | |
1373 | * Byte I/O register address from base of 'iop_base'. | |
1374 | */ | |
1375 | #define IOPB_INTR_STATUS_REG 0x00 | |
1376 | #define IOPB_CHIP_ID_1 0x01 | |
1377 | #define IOPB_INTR_ENABLES 0x02 | |
1378 | #define IOPB_CHIP_TYPE_REV 0x03 | |
1379 | #define IOPB_RES_ADDR_4 0x04 | |
1380 | #define IOPB_RES_ADDR_5 0x05 | |
1381 | #define IOPB_RAM_DATA 0x06 | |
1382 | #define IOPB_RES_ADDR_7 0x07 | |
1383 | #define IOPB_FLAG_REG 0x08 | |
1384 | #define IOPB_RES_ADDR_9 0x09 | |
1385 | #define IOPB_RISC_CSR 0x0A | |
1386 | #define IOPB_RES_ADDR_B 0x0B | |
1387 | #define IOPB_RES_ADDR_C 0x0C | |
1388 | #define IOPB_RES_ADDR_D 0x0D | |
1389 | #define IOPB_SOFT_OVER_WR 0x0E | |
1390 | #define IOPB_RES_ADDR_F 0x0F | |
1391 | #define IOPB_MEM_CFG 0x10 | |
1392 | #define IOPB_RES_ADDR_11 0x11 | |
1393 | #define IOPB_GPIO_DATA 0x12 | |
1394 | #define IOPB_RES_ADDR_13 0x13 | |
1395 | #define IOPB_FLASH_PAGE 0x14 | |
1396 | #define IOPB_RES_ADDR_15 0x15 | |
1397 | #define IOPB_GPIO_CNTL 0x16 | |
1398 | #define IOPB_RES_ADDR_17 0x17 | |
1399 | #define IOPB_FLASH_DATA 0x18 | |
1400 | #define IOPB_RES_ADDR_19 0x19 | |
1401 | #define IOPB_RES_ADDR_1A 0x1A | |
1402 | #define IOPB_RES_ADDR_1B 0x1B | |
1403 | #define IOPB_RES_ADDR_1C 0x1C | |
1404 | #define IOPB_RES_ADDR_1D 0x1D | |
1405 | #define IOPB_RES_ADDR_1E 0x1E | |
1406 | #define IOPB_RES_ADDR_1F 0x1F | |
1407 | #define IOPB_DMA_CFG0 0x20 | |
1408 | #define IOPB_DMA_CFG1 0x21 | |
1409 | #define IOPB_TICKLE 0x22 | |
1410 | #define IOPB_DMA_REG_WR 0x23 | |
1411 | #define IOPB_SDMA_STATUS 0x24 | |
1412 | #define IOPB_SCSI_BYTE_CNT 0x25 | |
1413 | #define IOPB_HOST_BYTE_CNT 0x26 | |
1414 | #define IOPB_BYTE_LEFT_TO_XFER 0x27 | |
1415 | #define IOPB_BYTE_TO_XFER_0 0x28 | |
1416 | #define IOPB_BYTE_TO_XFER_1 0x29 | |
1417 | #define IOPB_BYTE_TO_XFER_2 0x2A | |
1418 | #define IOPB_BYTE_TO_XFER_3 0x2B | |
1419 | #define IOPB_ACC_GRP 0x2C | |
1420 | #define IOPB_RES_ADDR_2D 0x2D | |
1421 | #define IOPB_DEV_ID 0x2E | |
1422 | #define IOPB_RES_ADDR_2F 0x2F | |
1423 | #define IOPB_SCSI_DATA 0x30 | |
1424 | #define IOPB_RES_ADDR_31 0x31 | |
1425 | #define IOPB_RES_ADDR_32 0x32 | |
1426 | #define IOPB_SCSI_DATA_HSHK 0x33 | |
1427 | #define IOPB_SCSI_CTRL 0x34 | |
1428 | #define IOPB_RES_ADDR_35 0x35 | |
1429 | #define IOPB_RES_ADDR_36 0x36 | |
1430 | #define IOPB_RES_ADDR_37 0x37 | |
1431 | #define IOPB_RAM_BIST 0x38 | |
1432 | #define IOPB_PLL_TEST 0x39 | |
1433 | #define IOPB_PCI_INT_CFG 0x3A | |
1434 | #define IOPB_RES_ADDR_3B 0x3B | |
1435 | #define IOPB_RFIFO_CNT 0x3C | |
1436 | #define IOPB_RES_ADDR_3D 0x3D | |
1437 | #define IOPB_RES_ADDR_3E 0x3E | |
1438 | #define IOPB_RES_ADDR_3F 0x3F | |
1439 | ||
1440 | /* | |
1441 | * Word I/O register address from base of 'iop_base'. | |
1442 | */ | |
27c868c2 MW |
1443 | #define IOPW_CHIP_ID_0 0x00 /* CID0 */ |
1444 | #define IOPW_CTRL_REG 0x02 /* CC */ | |
1445 | #define IOPW_RAM_ADDR 0x04 /* LA */ | |
1446 | #define IOPW_RAM_DATA 0x06 /* LD */ | |
1da177e4 | 1447 | #define IOPW_RES_ADDR_08 0x08 |
27c868c2 MW |
1448 | #define IOPW_RISC_CSR 0x0A /* CSR */ |
1449 | #define IOPW_SCSI_CFG0 0x0C /* CFG0 */ | |
1450 | #define IOPW_SCSI_CFG1 0x0E /* CFG1 */ | |
1da177e4 | 1451 | #define IOPW_RES_ADDR_10 0x10 |
27c868c2 | 1452 | #define IOPW_SEL_MASK 0x12 /* SM */ |
1da177e4 | 1453 | #define IOPW_RES_ADDR_14 0x14 |
27c868c2 | 1454 | #define IOPW_FLASH_ADDR 0x16 /* FA */ |
1da177e4 | 1455 | #define IOPW_RES_ADDR_18 0x18 |
27c868c2 MW |
1456 | #define IOPW_EE_CMD 0x1A /* EC */ |
1457 | #define IOPW_EE_DATA 0x1C /* ED */ | |
1458 | #define IOPW_SFIFO_CNT 0x1E /* SFC */ | |
1da177e4 | 1459 | #define IOPW_RES_ADDR_20 0x20 |
27c868c2 MW |
1460 | #define IOPW_Q_BASE 0x22 /* QB */ |
1461 | #define IOPW_QP 0x24 /* QP */ | |
1462 | #define IOPW_IX 0x26 /* IX */ | |
1463 | #define IOPW_SP 0x28 /* SP */ | |
1464 | #define IOPW_PC 0x2A /* PC */ | |
1da177e4 LT |
1465 | #define IOPW_RES_ADDR_2C 0x2C |
1466 | #define IOPW_RES_ADDR_2E 0x2E | |
27c868c2 MW |
1467 | #define IOPW_SCSI_DATA 0x30 /* SD */ |
1468 | #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */ | |
1469 | #define IOPW_SCSI_CTRL 0x34 /* SC */ | |
1470 | #define IOPW_HSHK_CFG 0x36 /* HCFG */ | |
1471 | #define IOPW_SXFR_STATUS 0x36 /* SXS */ | |
1472 | #define IOPW_SXFR_CNTL 0x38 /* SXL */ | |
1473 | #define IOPW_SXFR_CNTH 0x3A /* SXH */ | |
1da177e4 | 1474 | #define IOPW_RES_ADDR_3C 0x3C |
27c868c2 | 1475 | #define IOPW_RFIFO_DATA 0x3E /* RFD */ |
1da177e4 LT |
1476 | |
1477 | /* | |
1478 | * Doubleword I/O register address from base of 'iop_base'. | |
1479 | */ | |
1480 | #define IOPDW_RES_ADDR_0 0x00 | |
1481 | #define IOPDW_RAM_DATA 0x04 | |
1482 | #define IOPDW_RES_ADDR_8 0x08 | |
1483 | #define IOPDW_RES_ADDR_C 0x0C | |
1484 | #define IOPDW_RES_ADDR_10 0x10 | |
1485 | #define IOPDW_COMMA 0x14 | |
1486 | #define IOPDW_COMMB 0x18 | |
1487 | #define IOPDW_RES_ADDR_1C 0x1C | |
1488 | #define IOPDW_SDMA_ADDR0 0x20 | |
1489 | #define IOPDW_SDMA_ADDR1 0x24 | |
1490 | #define IOPDW_SDMA_COUNT 0x28 | |
1491 | #define IOPDW_SDMA_ERROR 0x2C | |
1492 | #define IOPDW_RDMA_ADDR0 0x30 | |
1493 | #define IOPDW_RDMA_ADDR1 0x34 | |
1494 | #define IOPDW_RDMA_COUNT 0x38 | |
1495 | #define IOPDW_RDMA_ERROR 0x3C | |
1496 | ||
1497 | #define ADV_CHIP_ID_BYTE 0x25 | |
1498 | #define ADV_CHIP_ID_WORD 0x04C1 | |
1499 | ||
1da177e4 LT |
1500 | #define ADV_INTR_ENABLE_HOST_INTR 0x01 |
1501 | #define ADV_INTR_ENABLE_SEL_INTR 0x02 | |
1502 | #define ADV_INTR_ENABLE_DPR_INTR 0x04 | |
1503 | #define ADV_INTR_ENABLE_RTA_INTR 0x08 | |
1504 | #define ADV_INTR_ENABLE_RMA_INTR 0x10 | |
1505 | #define ADV_INTR_ENABLE_RST_INTR 0x20 | |
1506 | #define ADV_INTR_ENABLE_DPE_INTR 0x40 | |
1507 | #define ADV_INTR_ENABLE_GLOBAL_INTR 0x80 | |
1508 | ||
1509 | #define ADV_INTR_STATUS_INTRA 0x01 | |
1510 | #define ADV_INTR_STATUS_INTRB 0x02 | |
1511 | #define ADV_INTR_STATUS_INTRC 0x04 | |
1512 | ||
1513 | #define ADV_RISC_CSR_STOP (0x0000) | |
1514 | #define ADV_RISC_TEST_COND (0x2000) | |
1515 | #define ADV_RISC_CSR_RUN (0x4000) | |
1516 | #define ADV_RISC_CSR_SINGLE_STEP (0x8000) | |
1517 | ||
1518 | #define ADV_CTRL_REG_HOST_INTR 0x0100 | |
1519 | #define ADV_CTRL_REG_SEL_INTR 0x0200 | |
1520 | #define ADV_CTRL_REG_DPR_INTR 0x0400 | |
1521 | #define ADV_CTRL_REG_RTA_INTR 0x0800 | |
1522 | #define ADV_CTRL_REG_RMA_INTR 0x1000 | |
1523 | #define ADV_CTRL_REG_RES_BIT14 0x2000 | |
1524 | #define ADV_CTRL_REG_DPE_INTR 0x4000 | |
1525 | #define ADV_CTRL_REG_POWER_DONE 0x8000 | |
1526 | #define ADV_CTRL_REG_ANY_INTR 0xFF00 | |
1527 | ||
1528 | #define ADV_CTRL_REG_CMD_RESET 0x00C6 | |
1529 | #define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5 | |
1530 | #define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4 | |
1531 | #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3 | |
1532 | #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2 | |
1533 | ||
1534 | #define ADV_TICKLE_NOP 0x00 | |
1535 | #define ADV_TICKLE_A 0x01 | |
1536 | #define ADV_TICKLE_B 0x02 | |
1537 | #define ADV_TICKLE_C 0x03 | |
1538 | ||
1da177e4 LT |
1539 | #define AdvIsIntPending(port) \ |
1540 | (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR) | |
1541 | ||
1542 | /* | |
1543 | * SCSI_CFG0 Register bit definitions | |
1544 | */ | |
27c868c2 MW |
1545 | #define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */ |
1546 | #define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */ | |
1547 | #define EVEN_PARITY 0x1000 /* Select Even Parity */ | |
1548 | #define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */ | |
1549 | #define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */ | |
1550 | #define PRIM_MODE 0x0100 /* Primitive SCSI mode */ | |
1551 | #define SCAM_EN 0x0080 /* Enable SCAM selection */ | |
1552 | #define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */ | |
1553 | #define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */ | |
1554 | #define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */ | |
1555 | #define OUR_ID 0x000F /* SCSI ID */ | |
1da177e4 LT |
1556 | |
1557 | /* | |
1558 | * SCSI_CFG1 Register bit definitions | |
1559 | */ | |
27c868c2 MW |
1560 | #define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */ |
1561 | #define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */ | |
1562 | #define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */ | |
1563 | #define FILTER_SEL 0x0C00 /* Filter Period Selection */ | |
1564 | #define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */ | |
1565 | #define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */ | |
1566 | #define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */ | |
1567 | #define ACTIVE_DBL 0x0200 /* Disable Active Negation */ | |
1568 | #define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */ | |
1569 | #define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */ | |
1570 | #define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */ | |
1571 | #define TERM_CTL 0x0030 /* External SCSI Termination Bits */ | |
1572 | #define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */ | |
1573 | #define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */ | |
1574 | #define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */ | |
1da177e4 LT |
1575 | |
1576 | /* | |
1577 | * Addendum for ASC-38C0800 Chip | |
1578 | * | |
1579 | * The ASC-38C1600 Chip uses the same definitions except that the | |
1580 | * bus mode override bits [12:10] have been moved to byte register | |
1581 | * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in | |
1582 | * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV) | |
1583 | * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only. | |
1584 | * Also each ASC-38C1600 function or channel uses only cable bits [5:4] | |
1585 | * and [1:0]. Bits [14], [7:6], [3:2] are unused. | |
1586 | */ | |
27c868c2 MW |
1587 | #define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */ |
1588 | #define HVD_LVD_SE 0x1C00 /* Device Detect Bits */ | |
1589 | #define HVD 0x1000 /* HVD Device Detect */ | |
1590 | #define LVD 0x0800 /* LVD Device Detect */ | |
1591 | #define SE 0x0400 /* SE Device Detect */ | |
1592 | #define TERM_LVD 0x00C0 /* LVD Termination Bits */ | |
1593 | #define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */ | |
1594 | #define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */ | |
1595 | #define TERM_SE 0x0030 /* SE Termination Bits */ | |
1596 | #define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */ | |
1597 | #define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */ | |
1598 | #define C_DET_LVD 0x000C /* LVD Cable Detect Bits */ | |
1599 | #define C_DET3 0x0008 /* Cable Detect for LVD External Wide */ | |
1600 | #define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */ | |
1601 | #define C_DET_SE 0x0003 /* SE Cable Detect Bits */ | |
1602 | #define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */ | |
1603 | #define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */ | |
1da177e4 LT |
1604 | |
1605 | #define CABLE_ILLEGAL_A 0x7 | |
1606 | /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */ | |
1607 | ||
1608 | #define CABLE_ILLEGAL_B 0xB | |
1609 | /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */ | |
1610 | ||
1611 | /* | |
1612 | * MEM_CFG Register bit definitions | |
1613 | */ | |
27c868c2 MW |
1614 | #define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */ |
1615 | #define FAST_EE_CLK 0x20 /* Diagnostic Bit */ | |
1616 | #define RAM_SZ 0x1C /* Specify size of RAM to RISC */ | |
1617 | #define RAM_SZ_2KB 0x00 /* 2 KB */ | |
1618 | #define RAM_SZ_4KB 0x04 /* 4 KB */ | |
1619 | #define RAM_SZ_8KB 0x08 /* 8 KB */ | |
1620 | #define RAM_SZ_16KB 0x0C /* 16 KB */ | |
1621 | #define RAM_SZ_32KB 0x10 /* 32 KB */ | |
1622 | #define RAM_SZ_64KB 0x14 /* 64 KB */ | |
1da177e4 LT |
1623 | |
1624 | /* | |
1625 | * DMA_CFG0 Register bit definitions | |
1626 | * | |
1627 | * This register is only accessible to the host. | |
1628 | */ | |
27c868c2 MW |
1629 | #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */ |
1630 | #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */ | |
1631 | #define FIFO_THRESH_16B 0x00 /* 16 bytes */ | |
1632 | #define FIFO_THRESH_32B 0x20 /* 32 bytes */ | |
1633 | #define FIFO_THRESH_48B 0x30 /* 48 bytes */ | |
1634 | #define FIFO_THRESH_64B 0x40 /* 64 bytes */ | |
1635 | #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */ | |
1636 | #define FIFO_THRESH_96B 0x60 /* 96 bytes */ | |
1637 | #define FIFO_THRESH_112B 0x70 /* 112 bytes */ | |
1638 | #define START_CTL 0x0C /* DMA start conditions */ | |
1639 | #define START_CTL_TH 0x00 /* Wait threshold level (default) */ | |
1640 | #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */ | |
1641 | #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */ | |
1642 | #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */ | |
1643 | #define READ_CMD 0x03 /* Memory Read Method */ | |
1644 | #define READ_CMD_MR 0x00 /* Memory Read */ | |
1645 | #define READ_CMD_MRL 0x02 /* Memory Read Long */ | |
1646 | #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */ | |
1da177e4 LT |
1647 | |
1648 | /* | |
1649 | * ASC-38C0800 RAM BIST Register bit definitions | |
1650 | */ | |
1651 | #define RAM_TEST_MODE 0x80 | |
1652 | #define PRE_TEST_MODE 0x40 | |
1653 | #define NORMAL_MODE 0x00 | |
1654 | #define RAM_TEST_DONE 0x10 | |
1655 | #define RAM_TEST_STATUS 0x0F | |
1656 | #define RAM_TEST_HOST_ERROR 0x08 | |
1657 | #define RAM_TEST_INTRAM_ERROR 0x04 | |
1658 | #define RAM_TEST_RISC_ERROR 0x02 | |
1659 | #define RAM_TEST_SCSI_ERROR 0x01 | |
1660 | #define RAM_TEST_SUCCESS 0x00 | |
1661 | #define PRE_TEST_VALUE 0x05 | |
1662 | #define NORMAL_VALUE 0x00 | |
1663 | ||
1664 | /* | |
1665 | * ASC38C1600 Definitions | |
1666 | * | |
1667 | * IOPB_PCI_INT_CFG Bit Field Definitions | |
1668 | */ | |
1669 | ||
27c868c2 | 1670 | #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */ |
1da177e4 LT |
1671 | |
1672 | /* | |
1673 | * Bit 1 can be set to change the interrupt for the Function to operate in | |
1674 | * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in | |
1675 | * Open Drain mode. Both functions of the ASC38C1600 must be set to the same | |
1676 | * mode, otherwise the operating mode is undefined. | |
1677 | */ | |
1678 | #define TOTEMPOLE 0x02 | |
1679 | ||
1680 | /* | |
1681 | * Bit 0 can be used to change the Int Pin for the Function. The value is | |
1682 | * 0 by default for both Functions with Function 0 using INT A and Function | |
1683 | * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set, | |
1684 | * INT A is used. | |
1685 | * | |
1686 | * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin | |
1687 | * value specified in the PCI Configuration Space. | |
1688 | */ | |
1689 | #define INTAB 0x01 | |
1690 | ||
1da177e4 LT |
1691 | /* |
1692 | * Adv Library Status Definitions | |
1693 | */ | |
1694 | #define ADV_TRUE 1 | |
1695 | #define ADV_FALSE 0 | |
1da177e4 LT |
1696 | #define ADV_SUCCESS 1 |
1697 | #define ADV_BUSY 0 | |
1698 | #define ADV_ERROR (-1) | |
1699 | ||
1da177e4 LT |
1700 | /* |
1701 | * ADV_DVC_VAR 'warn_code' values | |
1702 | */ | |
27c868c2 MW |
1703 | #define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */ |
1704 | #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */ | |
1705 | #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */ | |
27c868c2 | 1706 | #define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */ |
1da177e4 | 1707 | |
27c868c2 MW |
1708 | #define ADV_MAX_TID 15 /* max. target identifier */ |
1709 | #define ADV_MAX_LUN 7 /* max. logical unit number */ | |
1da177e4 LT |
1710 | |
1711 | /* | |
1712 | * Error code values are set in ADV_DVC_VAR 'err_code'. | |
1713 | */ | |
27c868c2 MW |
1714 | #define ASC_IERR_WRITE_EEPROM 0x0001 /* write EEPROM error */ |
1715 | #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */ | |
1716 | #define ASC_IERR_NO_CARRIER 0x0004 /* No more carrier memory. */ | |
1717 | #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */ | |
1718 | #define ASC_IERR_CHIP_VERSION 0x0040 /* wrong chip version */ | |
1719 | #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */ | |
1720 | #define ASC_IERR_HVD_DEVICE 0x0100 /* HVD attached to LVD connector. */ | |
1721 | #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */ | |
1722 | #define ASC_IERR_ILLEGAL_CONNECTION 0x0400 /* Illegal cable connection */ | |
1723 | #define ASC_IERR_SINGLE_END_DEVICE 0x0800 /* Single-end used w/differential */ | |
1724 | #define ASC_IERR_REVERSED_CABLE 0x1000 /* Narrow flat cable reversed */ | |
1725 | #define ASC_IERR_BIST_PRE_TEST 0x2000 /* BIST pre-test error */ | |
1726 | #define ASC_IERR_BIST_RAM_TEST 0x4000 /* BIST RAM test error */ | |
1727 | #define ASC_IERR_BAD_CHIPTYPE 0x8000 /* Invalid 'chip_type' setting. */ | |
1da177e4 LT |
1728 | |
1729 | /* | |
1730 | * Fixed locations of microcode operating variables. | |
1731 | */ | |
27c868c2 MW |
1732 | #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */ |
1733 | #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */ | |
1734 | #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */ | |
1735 | #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */ | |
1736 | #define ASC_MC_VERSION_NUM 0x003A /* microcode number */ | |
1737 | #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */ | |
1738 | #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */ | |
1739 | #define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */ | |
1740 | #define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */ | |
1741 | #define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */ | |
1742 | #define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */ | |
1743 | #define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */ | |
1744 | #define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */ | |
1da177e4 LT |
1745 | #define ASC_MC_CHIP_TYPE 0x009A |
1746 | #define ASC_MC_INTRB_CODE 0x009B | |
1747 | #define ASC_MC_WDTR_ABLE 0x009C | |
1748 | #define ASC_MC_SDTR_ABLE 0x009E | |
1749 | #define ASC_MC_TAGQNG_ABLE 0x00A0 | |
1750 | #define ASC_MC_DISC_ENABLE 0x00A2 | |
1751 | #define ASC_MC_IDLE_CMD_STATUS 0x00A4 | |
1752 | #define ASC_MC_IDLE_CMD 0x00A6 | |
1753 | #define ASC_MC_IDLE_CMD_PARAMETER 0x00A8 | |
1754 | #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC | |
1755 | #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE | |
1756 | #define ASC_MC_DEFAULT_MEM_CFG 0x00B0 | |
1757 | #define ASC_MC_DEFAULT_SEL_MASK 0x00B2 | |
1758 | #define ASC_MC_SDTR_DONE 0x00B6 | |
1759 | #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0 | |
1760 | #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0 | |
1761 | #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100 | |
27c868c2 | 1762 | #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */ |
1da177e4 | 1763 | #define ASC_MC_WDTR_DONE 0x0124 |
27c868c2 | 1764 | #define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */ |
1da177e4 LT |
1765 | #define ASC_MC_ICQ 0x0160 |
1766 | #define ASC_MC_IRQ 0x0164 | |
1767 | #define ASC_MC_PPR_ABLE 0x017A | |
1768 | ||
1769 | /* | |
1770 | * BIOS LRAM variable absolute offsets. | |
1771 | */ | |
1772 | #define BIOS_CODESEG 0x54 | |
1773 | #define BIOS_CODELEN 0x56 | |
1774 | #define BIOS_SIGNATURE 0x58 | |
1775 | #define BIOS_VERSION 0x5A | |
1776 | ||
1777 | /* | |
1778 | * Microcode Control Flags | |
1779 | * | |
1780 | * Flags set by the Adv Library in RISC variable 'control_flag' (0x122) | |
1781 | * and handled by the microcode. | |
1782 | */ | |
27c868c2 MW |
1783 | #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */ |
1784 | #define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */ | |
1da177e4 LT |
1785 | |
1786 | /* | |
1787 | * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format | |
1788 | */ | |
1789 | #define HSHK_CFG_WIDE_XFR 0x8000 | |
1790 | #define HSHK_CFG_RATE 0x0F00 | |
1791 | #define HSHK_CFG_OFFSET 0x001F | |
1792 | ||
27c868c2 MW |
1793 | #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */ |
1794 | #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */ | |
1795 | #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */ | |
1796 | #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */ | |
1797 | ||
1798 | #define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */ | |
1799 | #define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */ | |
1800 | #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */ | |
1801 | #define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */ | |
1802 | #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */ | |
1803 | ||
1804 | #define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */ | |
1805 | #define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */ | |
1806 | #define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */ | |
1807 | #define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */ | |
1808 | #define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */ | |
1da177e4 LT |
1809 | /* |
1810 | * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or | |
1811 | * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used. | |
1812 | */ | |
27c868c2 MW |
1813 | #define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */ |
1814 | #define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */ | |
1da177e4 LT |
1815 | |
1816 | /* | |
1817 | * All fields here are accessed by the board microcode and need to be | |
1818 | * little-endian. | |
1819 | */ | |
27c868c2 MW |
1820 | typedef struct adv_carr_t { |
1821 | ADV_VADDR carr_va; /* Carrier Virtual Address */ | |
1822 | ADV_PADDR carr_pa; /* Carrier Physical Address */ | |
1823 | ADV_VADDR areq_vpa; /* ASC_SCSI_REQ_Q Virtual or Physical Address */ | |
1824 | /* | |
1825 | * next_vpa [31:4] Carrier Virtual or Physical Next Pointer | |
1826 | * | |
1827 | * next_vpa [3:1] Reserved Bits | |
1828 | * next_vpa [0] Done Flag set in Response Queue. | |
1829 | */ | |
1830 | ADV_VADDR next_vpa; | |
1da177e4 LT |
1831 | } ADV_CARR_T; |
1832 | ||
1833 | /* | |
1834 | * Mask used to eliminate low 4 bits of carrier 'next_vpa' field. | |
1835 | */ | |
1836 | #define ASC_NEXT_VPA_MASK 0xFFFFFFF0 | |
1837 | ||
1838 | #define ASC_RQ_DONE 0x00000001 | |
1839 | #define ASC_RQ_GOOD 0x00000002 | |
1840 | #define ASC_CQ_STOPPER 0x00000000 | |
1841 | ||
1842 | #define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK) | |
1843 | ||
1844 | #define ADV_CARRIER_NUM_PAGE_CROSSING \ | |
1845 | (((ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) + \ | |
1846 | (ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE) | |
1847 | ||
1848 | #define ADV_CARRIER_BUFSIZE \ | |
1849 | ((ADV_CARRIER_COUNT + ADV_CARRIER_NUM_PAGE_CROSSING) * sizeof(ADV_CARR_T)) | |
1850 | ||
1851 | /* | |
1852 | * ASC_SCSI_REQ_Q 'a_flag' definitions | |
1853 | * | |
1854 | * The Adv Library should limit use to the lower nibble (4 bits) of | |
1855 | * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag. | |
1856 | */ | |
27c868c2 MW |
1857 | #define ADV_POLL_REQUEST 0x01 /* poll for request completion */ |
1858 | #define ADV_SCSIQ_DONE 0x02 /* request done */ | |
1859 | #define ADV_DONT_RETRY 0x08 /* don't do retry */ | |
1da177e4 | 1860 | |
27c868c2 MW |
1861 | #define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */ |
1862 | #define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */ | |
1863 | #define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */ | |
1da177e4 LT |
1864 | |
1865 | /* | |
1866 | * Adapter temporary configuration structure | |
1867 | * | |
1868 | * This structure can be discarded after initialization. Don't add | |
1869 | * fields here needed after initialization. | |
1870 | * | |
1871 | * Field naming convention: | |
1872 | * | |
1873 | * *_enable indicates the field enables or disables a feature. The | |
1874 | * value of the field is never reset. | |
1875 | */ | |
1876 | typedef struct adv_dvc_cfg { | |
27c868c2 MW |
1877 | ushort disc_enable; /* enable disconnection */ |
1878 | uchar chip_version; /* chip version */ | |
1879 | uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */ | |
1880 | ushort lib_version; /* Adv Library version number */ | |
1881 | ushort control_flag; /* Microcode Control Flag */ | |
1882 | ushort mcode_date; /* Microcode date */ | |
1883 | ushort mcode_version; /* Microcode version */ | |
27c868c2 MW |
1884 | ushort serial1; /* EEPROM serial number word 1 */ |
1885 | ushort serial2; /* EEPROM serial number word 2 */ | |
1886 | ushort serial3; /* EEPROM serial number word 3 */ | |
1da177e4 LT |
1887 | } ADV_DVC_CFG; |
1888 | ||
1889 | struct adv_dvc_var; | |
1890 | struct adv_scsi_req_q; | |
1891 | ||
1da177e4 LT |
1892 | /* |
1893 | * Adapter operation variable structure. | |
1894 | * | |
1895 | * One structure is required per host adapter. | |
1896 | * | |
1897 | * Field naming convention: | |
1898 | * | |
1899 | * *_able indicates both whether a feature should be enabled or disabled | |
1900 | * and whether a device isi capable of the feature. At initialization | |
1901 | * this field may be set, but later if a device is found to be incapable | |
1902 | * of the feature, the field is cleared. | |
1903 | */ | |
1904 | typedef struct adv_dvc_var { | |
27c868c2 MW |
1905 | AdvPortAddr iop_base; /* I/O port address */ |
1906 | ushort err_code; /* fatal error code */ | |
1907 | ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */ | |
27c868c2 MW |
1908 | ushort wdtr_able; /* try WDTR for a device */ |
1909 | ushort sdtr_able; /* try SDTR for a device */ | |
1910 | ushort ultra_able; /* try SDTR Ultra speed for a device */ | |
1911 | ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */ | |
1912 | ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */ | |
1913 | ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */ | |
1914 | ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */ | |
1915 | ushort tagqng_able; /* try tagged queuing with a device */ | |
1916 | ushort ppr_able; /* PPR message capable per TID bitmask. */ | |
1917 | uchar max_dvc_qng; /* maximum number of tagged commands per device */ | |
1918 | ushort start_motor; /* start motor command allowed */ | |
1919 | uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */ | |
1920 | uchar chip_no; /* should be assigned by caller */ | |
1921 | uchar max_host_qng; /* maximum number of Q'ed command allowed */ | |
1922 | uchar irq_no; /* IRQ number */ | |
1923 | ushort no_scam; /* scam_tolerant of EEPROM */ | |
1924 | struct asc_board *drv_ptr; /* driver pointer to private structure */ | |
1925 | uchar chip_scsi_id; /* chip SCSI target ID */ | |
1926 | uchar chip_type; | |
1927 | uchar bist_err_code; | |
1928 | ADV_CARR_T *carrier_buf; | |
1929 | ADV_CARR_T *carr_freelist; /* Carrier free list. */ | |
1930 | ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */ | |
1931 | ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */ | |
1932 | ushort carr_pending_cnt; /* Count of pending carriers. */ | |
1933 | /* | |
1934 | * Note: The following fields will not be used after initialization. The | |
1935 | * driver may discard the buffer after initialization is done. | |
1936 | */ | |
1937 | ADV_DVC_CFG *cfg; /* temporary configuration structure */ | |
1da177e4 LT |
1938 | } ADV_DVC_VAR; |
1939 | ||
1940 | #define NO_OF_SG_PER_BLOCK 15 | |
1941 | ||
1942 | typedef struct asc_sg_block { | |
27c868c2 MW |
1943 | uchar reserved1; |
1944 | uchar reserved2; | |
1945 | uchar reserved3; | |
1946 | uchar sg_cnt; /* Valid entries in block. */ | |
1947 | ADV_PADDR sg_ptr; /* Pointer to next sg block. */ | |
1948 | struct { | |
1949 | ADV_PADDR sg_addr; /* SG element address. */ | |
1950 | ADV_DCNT sg_count; /* SG element count. */ | |
1951 | } sg_list[NO_OF_SG_PER_BLOCK]; | |
1da177e4 LT |
1952 | } ADV_SG_BLOCK; |
1953 | ||
1954 | /* | |
1955 | * ADV_SCSI_REQ_Q - microcode request structure | |
1956 | * | |
1957 | * All fields in this structure up to byte 60 are used by the microcode. | |
1958 | * The microcode makes assumptions about the size and ordering of fields | |
1959 | * in this structure. Do not change the structure definition here without | |
1960 | * coordinating the change with the microcode. | |
1961 | * | |
1962 | * All fields accessed by microcode must be maintained in little_endian | |
1963 | * order. | |
1964 | */ | |
1965 | typedef struct adv_scsi_req_q { | |
27c868c2 MW |
1966 | uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */ |
1967 | uchar target_cmd; | |
1968 | uchar target_id; /* Device target identifier. */ | |
1969 | uchar target_lun; /* Device target logical unit number. */ | |
1970 | ADV_PADDR data_addr; /* Data buffer physical address. */ | |
1971 | ADV_DCNT data_cnt; /* Data count. Ucode sets to residual. */ | |
1972 | ADV_PADDR sense_addr; | |
1973 | ADV_PADDR carr_pa; | |
1974 | uchar mflag; | |
1975 | uchar sense_len; | |
1976 | uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */ | |
1977 | uchar scsi_cntl; | |
1978 | uchar done_status; /* Completion status. */ | |
1979 | uchar scsi_status; /* SCSI status byte. */ | |
1980 | uchar host_status; /* Ucode host status. */ | |
1981 | uchar sg_working_ix; | |
1982 | uchar cdb[12]; /* SCSI CDB bytes 0-11. */ | |
1983 | ADV_PADDR sg_real_addr; /* SG list physical address. */ | |
1984 | ADV_PADDR scsiq_rptr; | |
1985 | uchar cdb16[4]; /* SCSI CDB bytes 12-15. */ | |
1986 | ADV_VADDR scsiq_ptr; | |
1987 | ADV_VADDR carr_va; | |
1988 | /* | |
1989 | * End of microcode structure - 60 bytes. The rest of the structure | |
1990 | * is used by the Adv Library and ignored by the microcode. | |
1991 | */ | |
1992 | ADV_VADDR srb_ptr; | |
1993 | ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */ | |
1994 | char *vdata_addr; /* Data buffer virtual address. */ | |
1995 | uchar a_flag; | |
1996 | uchar pad[2]; /* Pad out to a word boundary. */ | |
1da177e4 LT |
1997 | } ADV_SCSI_REQ_Q; |
1998 | ||
1999 | /* | |
2000 | * Microcode idle loop commands | |
2001 | */ | |
2002 | #define IDLE_CMD_COMPLETED 0 | |
2003 | #define IDLE_CMD_STOP_CHIP 0x0001 | |
2004 | #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002 | |
2005 | #define IDLE_CMD_SEND_INT 0x0004 | |
2006 | #define IDLE_CMD_ABORT 0x0008 | |
2007 | #define IDLE_CMD_DEVICE_RESET 0x0010 | |
27c868c2 MW |
2008 | #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */ |
2009 | #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */ | |
1da177e4 LT |
2010 | #define IDLE_CMD_SCSIREQ 0x0080 |
2011 | ||
2012 | #define IDLE_CMD_STATUS_SUCCESS 0x0001 | |
2013 | #define IDLE_CMD_STATUS_FAILURE 0x0002 | |
2014 | ||
2015 | /* | |
2016 | * AdvSendIdleCmd() flag definitions. | |
2017 | */ | |
2018 | #define ADV_NOWAIT 0x01 | |
2019 | ||
2020 | /* | |
2021 | * Wait loop time out values. | |
2022 | */ | |
27c868c2 MW |
2023 | #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */ |
2024 | #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */ | |
27c868c2 | 2025 | #define SCSI_MAX_RETRY 10 /* retry count */ |
1da177e4 | 2026 | |
27c868c2 MW |
2027 | #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */ |
2028 | #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */ | |
2029 | #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */ | |
2030 | #define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */ | |
1da177e4 | 2031 | |
27c868c2 | 2032 | #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */ |
1da177e4 | 2033 | |
1da177e4 LT |
2034 | /* Read byte from a register. */ |
2035 | #define AdvReadByteRegister(iop_base, reg_off) \ | |
2036 | (ADV_MEM_READB((iop_base) + (reg_off))) | |
2037 | ||
2038 | /* Write byte to a register. */ | |
2039 | #define AdvWriteByteRegister(iop_base, reg_off, byte) \ | |
2040 | (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte))) | |
2041 | ||
2042 | /* Read word (2 bytes) from a register. */ | |
2043 | #define AdvReadWordRegister(iop_base, reg_off) \ | |
2044 | (ADV_MEM_READW((iop_base) + (reg_off))) | |
2045 | ||
2046 | /* Write word (2 bytes) to a register. */ | |
2047 | #define AdvWriteWordRegister(iop_base, reg_off, word) \ | |
2048 | (ADV_MEM_WRITEW((iop_base) + (reg_off), (word))) | |
2049 | ||
2050 | /* Write dword (4 bytes) to a register. */ | |
2051 | #define AdvWriteDWordRegister(iop_base, reg_off, dword) \ | |
2052 | (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword))) | |
2053 | ||
2054 | /* Read byte from LRAM. */ | |
2055 | #define AdvReadByteLram(iop_base, addr, byte) \ | |
2056 | do { \ | |
2057 | ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \ | |
2058 | (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \ | |
2059 | } while (0) | |
2060 | ||
2061 | /* Write byte to LRAM. */ | |
2062 | #define AdvWriteByteLram(iop_base, addr, byte) \ | |
2063 | (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \ | |
2064 | ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte))) | |
2065 | ||
2066 | /* Read word (2 bytes) from LRAM. */ | |
2067 | #define AdvReadWordLram(iop_base, addr, word) \ | |
2068 | do { \ | |
2069 | ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \ | |
2070 | (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \ | |
2071 | } while (0) | |
2072 | ||
2073 | /* Write word (2 bytes) to LRAM. */ | |
2074 | #define AdvWriteWordLram(iop_base, addr, word) \ | |
2075 | (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \ | |
2076 | ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word))) | |
2077 | ||
2078 | /* Write little-endian double word (4 bytes) to LRAM */ | |
2079 | /* Because of unspecified C language ordering don't use auto-increment. */ | |
2080 | #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \ | |
2081 | ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \ | |
2082 | ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \ | |
2083 | cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \ | |
2084 | (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \ | |
2085 | ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \ | |
2086 | cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF))))) | |
2087 | ||
2088 | /* Read word (2 bytes) from LRAM assuming that the address is already set. */ | |
2089 | #define AdvReadWordAutoIncLram(iop_base) \ | |
2090 | (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)) | |
2091 | ||
2092 | /* Write word (2 bytes) to LRAM assuming that the address is already set. */ | |
2093 | #define AdvWriteWordAutoIncLram(iop_base, word) \ | |
2094 | (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word))) | |
2095 | ||
1da177e4 LT |
2096 | /* |
2097 | * Define macro to check for Condor signature. | |
2098 | * | |
2099 | * Evaluate to ADV_TRUE if a Condor chip is found the specified port | |
2100 | * address 'iop_base'. Otherwise evalue to ADV_FALSE. | |
2101 | */ | |
2102 | #define AdvFindSignature(iop_base) \ | |
2103 | (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \ | |
2104 | ADV_CHIP_ID_BYTE) && \ | |
2105 | (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \ | |
2106 | ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE) | |
2107 | ||
2108 | /* | |
2109 | * Define macro to Return the version number of the chip at 'iop_base'. | |
2110 | * | |
2111 | * The second parameter 'bus_type' is currently unused. | |
2112 | */ | |
2113 | #define AdvGetChipVersion(iop_base, bus_type) \ | |
2114 | AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV) | |
2115 | ||
2116 | /* | |
2117 | * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must | |
2118 | * match the ASC_SCSI_REQ_Q 'srb_ptr' field. | |
2119 | * | |
2120 | * If the request has not yet been sent to the device it will simply be | |
2121 | * aborted from RISC memory. If the request is disconnected it will be | |
2122 | * aborted on reselection by sending an Abort Message to the target ID. | |
2123 | * | |
2124 | * Return value: | |
2125 | * ADV_TRUE(1) - Queue was successfully aborted. | |
2126 | * ADV_FALSE(0) - Queue was not found on the active queue list. | |
2127 | */ | |
2128 | #define AdvAbortQueue(asc_dvc, scsiq) \ | |
2129 | AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \ | |
2130 | (ADV_DCNT) (scsiq)) | |
2131 | ||
2132 | /* | |
2133 | * Send a Bus Device Reset Message to the specified target ID. | |
2134 | * | |
2135 | * All outstanding commands will be purged if sending the | |
2136 | * Bus Device Reset Message is successful. | |
2137 | * | |
2138 | * Return Value: | |
2139 | * ADV_TRUE(1) - All requests on the target are purged. | |
2140 | * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests | |
2141 | * are not purged. | |
2142 | */ | |
2143 | #define AdvResetDevice(asc_dvc, target_id) \ | |
2144 | AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \ | |
2145 | (ADV_DCNT) (target_id)) | |
2146 | ||
2147 | /* | |
2148 | * SCSI Wide Type definition. | |
2149 | */ | |
2150 | #define ADV_SCSI_BIT_ID_TYPE ushort | |
2151 | ||
2152 | /* | |
2153 | * AdvInitScsiTarget() 'cntl_flag' options. | |
2154 | */ | |
2155 | #define ADV_SCAN_LUN 0x01 | |
2156 | #define ADV_CAPINFO_NOLUN 0x02 | |
2157 | ||
2158 | /* | |
2159 | * Convert target id to target id bit mask. | |
2160 | */ | |
2161 | #define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID)) | |
2162 | ||
2163 | /* | |
2164 | * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values. | |
2165 | */ | |
2166 | ||
27c868c2 | 2167 | #define QD_NO_STATUS 0x00 /* Request not completed yet. */ |
1da177e4 LT |
2168 | #define QD_NO_ERROR 0x01 |
2169 | #define QD_ABORTED_BY_HOST 0x02 | |
2170 | #define QD_WITH_ERROR 0x04 | |
2171 | ||
2172 | #define QHSTA_NO_ERROR 0x00 | |
2173 | #define QHSTA_M_SEL_TIMEOUT 0x11 | |
2174 | #define QHSTA_M_DATA_OVER_RUN 0x12 | |
2175 | #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13 | |
2176 | #define QHSTA_M_QUEUE_ABORTED 0x15 | |
27c868c2 MW |
2177 | #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */ |
2178 | #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */ | |
2179 | #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */ | |
2180 | #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */ | |
2181 | #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */ | |
2182 | #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */ | |
2183 | #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */ | |
1da177e4 | 2184 | /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */ |
27c868c2 MW |
2185 | #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */ |
2186 | #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */ | |
2187 | #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */ | |
2188 | #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */ | |
2189 | #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */ | |
2190 | #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */ | |
2191 | #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */ | |
2192 | #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */ | |
1da177e4 LT |
2193 | #define QHSTA_M_WTM_TIMEOUT 0x41 |
2194 | #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42 | |
2195 | #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43 | |
2196 | #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44 | |
27c868c2 MW |
2197 | #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */ |
2198 | #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */ | |
2199 | #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */ | |
1da177e4 | 2200 | |
1da177e4 LT |
2201 | /* |
2202 | * DvcGetPhyAddr() flag arguments | |
2203 | */ | |
27c868c2 MW |
2204 | #define ADV_IS_SCSIQ_FLAG 0x01 /* 'addr' is ASC_SCSI_REQ_Q pointer */ |
2205 | #define ADV_ASCGETSGLIST_VADDR 0x02 /* 'addr' is AscGetSGList() virtual addr */ | |
2206 | #define ADV_IS_SENSE_FLAG 0x04 /* 'addr' is sense virtual pointer */ | |
2207 | #define ADV_IS_DATA_FLAG 0x08 /* 'addr' is data virtual pointer */ | |
2208 | #define ADV_IS_SGLIST_FLAG 0x10 /* 'addr' is sglist virtual pointer */ | |
2209 | #define ADV_IS_CARRIER_FLAG 0x20 /* 'addr' is ADV_CARR_T pointer */ | |
1da177e4 LT |
2210 | |
2211 | /* Return the address that is aligned at the next doubleword >= to 'addr'. */ | |
2212 | #define ADV_8BALIGN(addr) (((ulong) (addr) + 0x7) & ~0x7) | |
2213 | #define ADV_16BALIGN(addr) (((ulong) (addr) + 0xF) & ~0xF) | |
2214 | #define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F) | |
2215 | ||
2216 | /* | |
2217 | * Total contiguous memory needed for driver SG blocks. | |
2218 | * | |
2219 | * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum | |
2220 | * number of scatter-gather elements the driver supports in a | |
2221 | * single request. | |
2222 | */ | |
2223 | ||
2224 | #define ADV_SG_LIST_MAX_BYTE_SIZE \ | |
2225 | (sizeof(ADV_SG_BLOCK) * \ | |
2226 | ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK)) | |
2227 | ||
1da177e4 LT |
2228 | /* Reference Scsi_Host hostdata */ |
2229 | #define ASC_BOARDP(host) ((asc_board_t *) &((host)->hostdata)) | |
2230 | ||
2231 | /* asc_board_t flags */ | |
2232 | #define ASC_HOST_IN_RESET 0x01 | |
27c868c2 | 2233 | #define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */ |
1da177e4 LT |
2234 | #define ASC_SELECT_QUEUE_DEPTHS 0x08 |
2235 | ||
2236 | #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0) | |
2237 | #define ASC_WIDE_BOARD(boardp) ((boardp)->flags & ASC_IS_WIDE_BOARD) | |
2238 | ||
27c868c2 | 2239 | #define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */ |
1da177e4 | 2240 | |
27c868c2 | 2241 | #define ASC_INFO_SIZE 128 /* advansys_info() line size */ |
1da177e4 LT |
2242 | |
2243 | #ifdef CONFIG_PROC_FS | |
2244 | /* /proc/scsi/advansys/[0...] related definitions */ | |
2245 | #define ASC_PRTBUF_SIZE 2048 | |
2246 | #define ASC_PRTLINE_SIZE 160 | |
2247 | ||
2248 | #define ASC_PRT_NEXT() \ | |
2249 | if (cp) { \ | |
2250 | totlen += len; \ | |
2251 | leftlen -= len; \ | |
2252 | if (leftlen == 0) { \ | |
2253 | return totlen; \ | |
2254 | } \ | |
2255 | cp += len; \ | |
2256 | } | |
2257 | #endif /* CONFIG_PROC_FS */ | |
2258 | ||
2259 | /* Asc Library return codes */ | |
2260 | #define ASC_TRUE 1 | |
2261 | #define ASC_FALSE 0 | |
2262 | #define ASC_NOERROR 1 | |
2263 | #define ASC_BUSY 0 | |
2264 | #define ASC_ERROR (-1) | |
2265 | ||
2266 | /* struct scsi_cmnd function return codes */ | |
2267 | #define STATUS_BYTE(byte) (byte) | |
2268 | #define MSG_BYTE(byte) ((byte) << 8) | |
2269 | #define HOST_BYTE(byte) ((byte) << 16) | |
2270 | #define DRIVER_BYTE(byte) ((byte) << 24) | |
2271 | ||
1da177e4 | 2272 | #ifndef ADVANSYS_STATS |
27c868c2 MW |
2273 | #define ASC_STATS(shost, counter) |
2274 | #define ASC_STATS_ADD(shost, counter, count) | |
1da177e4 | 2275 | #else /* ADVANSYS_STATS */ |
27c868c2 MW |
2276 | #define ASC_STATS(shost, counter) \ |
2277 | (ASC_BOARDP(shost)->asc_stats.counter++) | |
1da177e4 | 2278 | |
27c868c2 MW |
2279 | #define ASC_STATS_ADD(shost, counter, count) \ |
2280 | (ASC_BOARDP(shost)->asc_stats.counter += (count)) | |
1da177e4 LT |
2281 | #endif /* ADVANSYS_STATS */ |
2282 | ||
2283 | #define ASC_CEILING(val, unit) (((val) + ((unit) - 1))/(unit)) | |
2284 | ||
2285 | /* If the result wraps when calculating tenths, return 0. */ | |
2286 | #define ASC_TENTHS(num, den) \ | |
2287 | (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \ | |
2288 | 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den))))) | |
2289 | ||
2290 | /* | |
2291 | * Display a message to the console. | |
2292 | */ | |
2293 | #define ASC_PRINT(s) \ | |
2294 | { \ | |
2295 | printk("advansys: "); \ | |
2296 | printk(s); \ | |
2297 | } | |
2298 | ||
2299 | #define ASC_PRINT1(s, a1) \ | |
2300 | { \ | |
2301 | printk("advansys: "); \ | |
2302 | printk((s), (a1)); \ | |
2303 | } | |
2304 | ||
2305 | #define ASC_PRINT2(s, a1, a2) \ | |
2306 | { \ | |
2307 | printk("advansys: "); \ | |
2308 | printk((s), (a1), (a2)); \ | |
2309 | } | |
2310 | ||
2311 | #define ASC_PRINT3(s, a1, a2, a3) \ | |
2312 | { \ | |
2313 | printk("advansys: "); \ | |
2314 | printk((s), (a1), (a2), (a3)); \ | |
2315 | } | |
2316 | ||
2317 | #define ASC_PRINT4(s, a1, a2, a3, a4) \ | |
2318 | { \ | |
2319 | printk("advansys: "); \ | |
2320 | printk((s), (a1), (a2), (a3), (a4)); \ | |
2321 | } | |
2322 | ||
1da177e4 LT |
2323 | #ifndef ADVANSYS_DEBUG |
2324 | ||
2325 | #define ASC_DBG(lvl, s) | |
2326 | #define ASC_DBG1(lvl, s, a1) | |
2327 | #define ASC_DBG2(lvl, s, a1, a2) | |
2328 | #define ASC_DBG3(lvl, s, a1, a2, a3) | |
2329 | #define ASC_DBG4(lvl, s, a1, a2, a3, a4) | |
2330 | #define ASC_DBG_PRT_SCSI_HOST(lvl, s) | |
2331 | #define ASC_DBG_PRT_SCSI_CMND(lvl, s) | |
2332 | #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) | |
2333 | #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) | |
2334 | #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) | |
2335 | #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) | |
2336 | #define ASC_DBG_PRT_HEX(lvl, name, start, length) | |
2337 | #define ASC_DBG_PRT_CDB(lvl, cdb, len) | |
2338 | #define ASC_DBG_PRT_SENSE(lvl, sense, len) | |
2339 | #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) | |
2340 | ||
2341 | #else /* ADVANSYS_DEBUG */ | |
2342 | ||
2343 | /* | |
2344 | * Debugging Message Levels: | |
2345 | * 0: Errors Only | |
2346 | * 1: High-Level Tracing | |
2347 | * 2-N: Verbose Tracing | |
2348 | */ | |
2349 | ||
2350 | #define ASC_DBG(lvl, s) \ | |
2351 | { \ | |
2352 | if (asc_dbglvl >= (lvl)) { \ | |
2353 | printk(s); \ | |
2354 | } \ | |
2355 | } | |
2356 | ||
2357 | #define ASC_DBG1(lvl, s, a1) \ | |
2358 | { \ | |
2359 | if (asc_dbglvl >= (lvl)) { \ | |
2360 | printk((s), (a1)); \ | |
2361 | } \ | |
2362 | } | |
2363 | ||
2364 | #define ASC_DBG2(lvl, s, a1, a2) \ | |
2365 | { \ | |
2366 | if (asc_dbglvl >= (lvl)) { \ | |
2367 | printk((s), (a1), (a2)); \ | |
2368 | } \ | |
2369 | } | |
2370 | ||
2371 | #define ASC_DBG3(lvl, s, a1, a2, a3) \ | |
2372 | { \ | |
2373 | if (asc_dbglvl >= (lvl)) { \ | |
2374 | printk((s), (a1), (a2), (a3)); \ | |
2375 | } \ | |
2376 | } | |
2377 | ||
2378 | #define ASC_DBG4(lvl, s, a1, a2, a3, a4) \ | |
2379 | { \ | |
2380 | if (asc_dbglvl >= (lvl)) { \ | |
2381 | printk((s), (a1), (a2), (a3), (a4)); \ | |
2382 | } \ | |
2383 | } | |
2384 | ||
2385 | #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \ | |
2386 | { \ | |
2387 | if (asc_dbglvl >= (lvl)) { \ | |
2388 | asc_prt_scsi_host(s); \ | |
2389 | } \ | |
2390 | } | |
2391 | ||
2392 | #define ASC_DBG_PRT_SCSI_CMND(lvl, s) \ | |
2393 | { \ | |
2394 | if (asc_dbglvl >= (lvl)) { \ | |
2395 | asc_prt_scsi_cmnd(s); \ | |
2396 | } \ | |
2397 | } | |
2398 | ||
2399 | #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \ | |
2400 | { \ | |
2401 | if (asc_dbglvl >= (lvl)) { \ | |
2402 | asc_prt_asc_scsi_q(scsiqp); \ | |
2403 | } \ | |
2404 | } | |
2405 | ||
2406 | #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \ | |
2407 | { \ | |
2408 | if (asc_dbglvl >= (lvl)) { \ | |
2409 | asc_prt_asc_qdone_info(qdone); \ | |
2410 | } \ | |
2411 | } | |
2412 | ||
2413 | #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \ | |
2414 | { \ | |
2415 | if (asc_dbglvl >= (lvl)) { \ | |
2416 | asc_prt_adv_scsi_req_q(scsiqp); \ | |
2417 | } \ | |
2418 | } | |
2419 | ||
2420 | #define ASC_DBG_PRT_HEX(lvl, name, start, length) \ | |
2421 | { \ | |
2422 | if (asc_dbglvl >= (lvl)) { \ | |
2423 | asc_prt_hex((name), (start), (length)); \ | |
2424 | } \ | |
2425 | } | |
2426 | ||
2427 | #define ASC_DBG_PRT_CDB(lvl, cdb, len) \ | |
2428 | ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len)); | |
2429 | ||
2430 | #define ASC_DBG_PRT_SENSE(lvl, sense, len) \ | |
2431 | ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len)); | |
2432 | ||
2433 | #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \ | |
2434 | ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len)); | |
2435 | #endif /* ADVANSYS_DEBUG */ | |
2436 | ||
1da177e4 LT |
2437 | #ifdef ADVANSYS_STATS |
2438 | ||
2439 | /* Per board statistics structure */ | |
2440 | struct asc_stats { | |
27c868c2 MW |
2441 | /* Driver Entrypoint Statistics */ |
2442 | ADV_DCNT queuecommand; /* # calls to advansys_queuecommand() */ | |
2443 | ADV_DCNT reset; /* # calls to advansys_eh_bus_reset() */ | |
2444 | ADV_DCNT biosparam; /* # calls to advansys_biosparam() */ | |
2445 | ADV_DCNT interrupt; /* # advansys_interrupt() calls */ | |
2446 | ADV_DCNT callback; /* # calls to asc/adv_isr_callback() */ | |
2447 | ADV_DCNT done; /* # calls to request's scsi_done function */ | |
2448 | ADV_DCNT build_error; /* # asc/adv_build_req() ASC_ERROR returns. */ | |
2449 | ADV_DCNT adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */ | |
2450 | ADV_DCNT adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */ | |
2451 | /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */ | |
2452 | ADV_DCNT exe_noerror; /* # ASC_NOERROR returns. */ | |
2453 | ADV_DCNT exe_busy; /* # ASC_BUSY returns. */ | |
2454 | ADV_DCNT exe_error; /* # ASC_ERROR returns. */ | |
2455 | ADV_DCNT exe_unknown; /* # unknown returns. */ | |
2456 | /* Data Transfer Statistics */ | |
2457 | ADV_DCNT cont_cnt; /* # non-scatter-gather I/O requests received */ | |
2458 | ADV_DCNT cont_xfer; /* # contiguous transfer 512-bytes */ | |
2459 | ADV_DCNT sg_cnt; /* # scatter-gather I/O requests received */ | |
2460 | ADV_DCNT sg_elem; /* # scatter-gather elements */ | |
2461 | ADV_DCNT sg_xfer; /* # scatter-gather transfer 512-bytes */ | |
1da177e4 LT |
2462 | }; |
2463 | #endif /* ADVANSYS_STATS */ | |
2464 | ||
1da177e4 LT |
2465 | /* |
2466 | * Adv Library Request Structures | |
2467 | * | |
2468 | * The following two structures are used to process Wide Board requests. | |
2469 | * | |
2470 | * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library | |
2471 | * and microcode with the ADV_SCSI_REQ_Q field 'srb_ptr' pointing to the | |
2472 | * adv_req_t. The adv_req_t structure 'cmndp' field in turn points to the | |
2473 | * Mid-Level SCSI request structure. | |
2474 | * | |
2475 | * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each | |
2476 | * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux | |
2477 | * up to 255 scatter-gather elements may be used per request or | |
2478 | * ADV_SCSI_REQ_Q. | |
2479 | * | |
2480 | * Both structures must be 32 byte aligned. | |
2481 | */ | |
2482 | typedef struct adv_sgblk { | |
27c868c2 MW |
2483 | ADV_SG_BLOCK sg_block; /* Sgblock structure. */ |
2484 | uchar align[32]; /* Sgblock structure padding. */ | |
2485 | struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */ | |
1da177e4 LT |
2486 | } adv_sgblk_t; |
2487 | ||
2488 | typedef struct adv_req { | |
27c868c2 MW |
2489 | ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */ |
2490 | uchar align[32]; /* Request structure padding. */ | |
2491 | struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */ | |
2492 | adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */ | |
2493 | struct adv_req *next_reqp; /* Next Request Structure. */ | |
1da177e4 LT |
2494 | } adv_req_t; |
2495 | ||
2496 | /* | |
2497 | * Structure allocated for each board. | |
2498 | * | |
8dfb5379 | 2499 | * This structure is allocated by scsi_host_alloc() at the end |
1da177e4 LT |
2500 | * of the 'Scsi_Host' structure starting at the 'hostdata' |
2501 | * field. It is guaranteed to be allocated from DMA-able memory. | |
2502 | */ | |
2503 | typedef struct asc_board { | |
394dbf3f | 2504 | struct device *dev; |
27c868c2 MW |
2505 | int id; /* Board Id */ |
2506 | uint flags; /* Board flags */ | |
2507 | union { | |
2508 | ASC_DVC_VAR asc_dvc_var; /* Narrow board */ | |
2509 | ADV_DVC_VAR adv_dvc_var; /* Wide board */ | |
2510 | } dvc_var; | |
2511 | union { | |
2512 | ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */ | |
2513 | ADV_DVC_CFG adv_dvc_cfg; /* Wide board */ | |
2514 | } dvc_cfg; | |
2515 | ushort asc_n_io_port; /* Number I/O ports. */ | |
27c868c2 | 2516 | ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */ |
27c868c2 MW |
2517 | ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */ |
2518 | ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */ | |
2519 | ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */ | |
2520 | union { | |
2521 | ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */ | |
2522 | ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */ | |
2523 | ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */ | |
2524 | ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */ | |
2525 | } eep_config; | |
2526 | ulong last_reset; /* Saved last reset time */ | |
2527 | spinlock_t lock; /* Board spinlock */ | |
27c868c2 MW |
2528 | /* /proc/scsi/advansys/[0...] */ |
2529 | char *prtbuf; /* /proc print buffer */ | |
1da177e4 | 2530 | #ifdef ADVANSYS_STATS |
27c868c2 MW |
2531 | struct asc_stats asc_stats; /* Board statistics */ |
2532 | #endif /* ADVANSYS_STATS */ | |
2533 | /* | |
2534 | * The following fields are used only for Narrow Boards. | |
2535 | */ | |
27c868c2 MW |
2536 | uchar sdtr_data[ASC_MAX_TID + 1]; /* SDTR information */ |
2537 | /* | |
2538 | * The following fields are used only for Wide Boards. | |
2539 | */ | |
2540 | void __iomem *ioremap_addr; /* I/O Memory remap address. */ | |
2541 | ushort ioport; /* I/O Port address. */ | |
b2c16f58 | 2542 | ADV_CARR_T *carrp; /* ADV_CARR_T memory block. */ |
27c868c2 MW |
2543 | adv_req_t *orig_reqp; /* adv_req_t memory block. */ |
2544 | adv_req_t *adv_reqp; /* Request structures. */ | |
2545 | adv_sgblk_t *adv_sgblkp; /* Scatter-gather structures. */ | |
2546 | ushort bios_signature; /* BIOS Signature. */ | |
2547 | ushort bios_version; /* BIOS Version. */ | |
2548 | ushort bios_codeseg; /* BIOS Code Segment. */ | |
2549 | ushort bios_codelen; /* BIOS Code Segment Length. */ | |
1da177e4 LT |
2550 | } asc_board_t; |
2551 | ||
13ac2d9c MW |
2552 | #define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \ |
2553 | dvc_var.adv_dvc_var) | |
2554 | #define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev) | |
2555 | ||
1da177e4 | 2556 | /* Number of boards detected in system. */ |
78e77d8b MW |
2557 | static int asc_board_count; |
2558 | ||
1da177e4 | 2559 | /* Overrun buffer used by all narrow boards. */ |
27c868c2 | 2560 | static uchar overrun_buf[ASC_OVERRUN_BSIZE] = { 0 }; |
1da177e4 | 2561 | |
1da177e4 | 2562 | #ifdef ADVANSYS_DEBUG |
27c868c2 | 2563 | static int asc_dbglvl = 3; |
1da177e4 | 2564 | |
1da177e4 | 2565 | /* |
51219358 | 2566 | * asc_prt_scsi_host() |
1da177e4 | 2567 | */ |
51219358 | 2568 | static void asc_prt_scsi_host(struct Scsi_Host *s) |
1da177e4 | 2569 | { |
27c868c2 | 2570 | asc_board_t *boardp; |
1da177e4 | 2571 | |
51219358 | 2572 | boardp = ASC_BOARDP(s); |
1da177e4 | 2573 | |
51219358 MW |
2574 | printk("Scsi_Host at addr 0x%lx\n", (ulong)s); |
2575 | printk(" host_busy %u, host_no %d, last_reset %d,\n", | |
2576 | s->host_busy, s->host_no, (unsigned)s->last_reset); | |
1da177e4 | 2577 | |
51219358 MW |
2578 | printk(" base 0x%lx, io_port 0x%lx, irq 0x%x,\n", |
2579 | (ulong)s->base, (ulong)s->io_port, s->irq); | |
1da177e4 | 2580 | |
51219358 MW |
2581 | printk(" dma_channel %d, this_id %d, can_queue %d,\n", |
2582 | s->dma_channel, s->this_id, s->can_queue); | |
27c868c2 | 2583 | |
51219358 MW |
2584 | printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n", |
2585 | s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma); | |
27c868c2 | 2586 | |
51219358 MW |
2587 | if (ASC_NARROW_BOARD(boardp)) { |
2588 | asc_prt_asc_dvc_var(&ASC_BOARDP(s)->dvc_var.asc_dvc_var); | |
2589 | asc_prt_asc_dvc_cfg(&ASC_BOARDP(s)->dvc_cfg.asc_dvc_cfg); | |
2590 | } else { | |
2591 | asc_prt_adv_dvc_var(&ASC_BOARDP(s)->dvc_var.adv_dvc_var); | |
2592 | asc_prt_adv_dvc_cfg(&ASC_BOARDP(s)->dvc_cfg.adv_dvc_cfg); | |
27c868c2 | 2593 | } |
51219358 | 2594 | } |
27c868c2 | 2595 | |
51219358 MW |
2596 | /* |
2597 | * asc_prt_scsi_cmnd() | |
2598 | */ | |
2599 | static void asc_prt_scsi_cmnd(struct scsi_cmnd *s) | |
2600 | { | |
2601 | printk("struct scsi_cmnd at addr 0x%lx\n", (ulong)s); | |
1da177e4 | 2602 | |
51219358 MW |
2603 | printk(" host 0x%lx, device 0x%lx, target %u, lun %u, channel %u,\n", |
2604 | (ulong)s->device->host, (ulong)s->device, s->device->id, | |
2605 | s->device->lun, s->device->channel); | |
27c868c2 | 2606 | |
51219358 | 2607 | asc_prt_hex(" CDB", s->cmnd, s->cmd_len); |
27c868c2 | 2608 | |
51219358 MW |
2609 | printk("sc_data_direction %u, resid %d\n", |
2610 | s->sc_data_direction, s->resid); | |
1da177e4 | 2611 | |
51219358 | 2612 | printk(" use_sg %u, sglist_len %u\n", s->use_sg, s->sglist_len); |
1da177e4 | 2613 | |
51219358 MW |
2614 | printk(" serial_number 0x%x, retries %d, allowed %d\n", |
2615 | (unsigned)s->serial_number, s->retries, s->allowed); | |
1da177e4 | 2616 | |
51219358 | 2617 | printk(" timeout_per_command %d\n", s->timeout_per_command); |
1da177e4 | 2618 | |
51219358 MW |
2619 | printk(" scsi_done 0x%p, done 0x%p, host_scribble 0x%p, result 0x%x\n", |
2620 | s->scsi_done, s->done, s->host_scribble, s->result); | |
2621 | ||
2622 | printk(" tag %u, pid %u\n", (unsigned)s->tag, (unsigned)s->pid); | |
1da177e4 | 2623 | } |
1da177e4 LT |
2624 | |
2625 | /* | |
51219358 | 2626 | * asc_prt_asc_dvc_var() |
1da177e4 | 2627 | */ |
51219358 | 2628 | static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h) |
1da177e4 | 2629 | { |
51219358 | 2630 | printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h); |
27c868c2 | 2631 | |
51219358 MW |
2632 | printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl " |
2633 | "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl); | |
2634 | ||
2635 | printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type, | |
2636 | (unsigned)h->init_sdtr); | |
2637 | ||
2638 | printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, " | |
2639 | "chip_no 0x%x,\n", (unsigned)h->sdtr_done, | |
2640 | (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready, | |
2641 | (unsigned)h->chip_no); | |
2642 | ||
2643 | printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait " | |
2644 | "%u,\n", (unsigned)h->queue_full_or_busy, | |
2645 | (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait); | |
2646 | ||
2647 | printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, " | |
2648 | "in_critical_cnt %u,\n", (unsigned)h->is_in_int, | |
2649 | (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng, | |
2650 | (unsigned)h->in_critical_cnt); | |
2651 | ||
2652 | printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, " | |
2653 | "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage, | |
2654 | (unsigned)h->init_state, (unsigned)h->no_scam, | |
2655 | (unsigned)h->pci_fix_asyn_xfer); | |
2656 | ||
2657 | printk(" cfg 0x%lx, irq_no 0x%x\n", (ulong)h->cfg, (unsigned)h->irq_no); | |
1da177e4 LT |
2658 | } |
2659 | ||
51219358 MW |
2660 | /* |
2661 | * asc_prt_asc_dvc_cfg() | |
2662 | */ | |
2663 | static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h) | |
6ed1ef07 | 2664 | { |
51219358 | 2665 | printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h); |
6ed1ef07 | 2666 | |
51219358 MW |
2667 | printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n", |
2668 | h->can_tagged_qng, h->cmd_qng_enabled); | |
2669 | printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n", | |
2670 | h->disc_enable, h->sdtr_enable); | |
6ed1ef07 | 2671 | |
51219358 MW |
2672 | printk |
2673 | (" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, chip_version %d,\n", | |
2674 | h->chip_scsi_id, h->isa_dma_speed, h->isa_dma_channel, | |
2675 | h->chip_version); | |
6ed1ef07 | 2676 | |
51219358 MW |
2677 | printk |
2678 | (" pci_device_id %d, lib_serial_no %u, lib_version %u, mcode_date 0x%x,\n", | |
2679 | to_pci_dev(h->dev)->device, h->lib_serial_no, h->lib_version, | |
2680 | h->mcode_date); | |
2681 | ||
2682 | printk(" mcode_version %d, overrun_buf 0x%lx\n", | |
2683 | h->mcode_version, (ulong)h->overrun_buf); | |
6ed1ef07 MW |
2684 | } |
2685 | ||
1da177e4 | 2686 | /* |
51219358 | 2687 | * asc_prt_asc_scsi_q() |
1da177e4 | 2688 | */ |
51219358 | 2689 | static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q) |
1da177e4 | 2690 | { |
51219358 MW |
2691 | ASC_SG_HEAD *sgp; |
2692 | int i; | |
1da177e4 | 2693 | |
51219358 | 2694 | printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q); |
1da177e4 | 2695 | |
51219358 MW |
2696 | printk |
2697 | (" target_ix 0x%x, target_lun %u, srb_ptr 0x%lx, tag_code 0x%x,\n", | |
2698 | q->q2.target_ix, q->q1.target_lun, (ulong)q->q2.srb_ptr, | |
2699 | q->q2.tag_code); | |
2700 | ||
2701 | printk | |
2702 | (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n", | |
2703 | (ulong)le32_to_cpu(q->q1.data_addr), | |
2704 | (ulong)le32_to_cpu(q->q1.data_cnt), | |
2705 | (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len); | |
2706 | ||
2707 | printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n", | |
2708 | (ulong)q->cdbptr, q->q2.cdb_len, | |
2709 | (ulong)q->sg_head, q->q1.sg_queue_cnt); | |
2710 | ||
2711 | if (q->sg_head) { | |
2712 | sgp = q->sg_head; | |
2713 | printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp); | |
2714 | printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt, | |
2715 | sgp->queue_cnt); | |
2716 | for (i = 0; i < sgp->entry_cnt; i++) { | |
2717 | printk(" [%u]: addr 0x%lx, bytes %lu\n", | |
2718 | i, (ulong)le32_to_cpu(sgp->sg_list[i].addr), | |
2719 | (ulong)le32_to_cpu(sgp->sg_list[i].bytes)); | |
2720 | } | |
b2a7a4ba | 2721 | |
27c868c2 | 2722 | } |
51219358 | 2723 | } |
1da177e4 | 2724 | |
51219358 MW |
2725 | /* |
2726 | * asc_prt_asc_qdone_info() | |
2727 | */ | |
2728 | static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q) | |
2729 | { | |
2730 | printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q); | |
2731 | printk(" srb_ptr 0x%lx, target_ix %u, cdb_len %u, tag_code %u,\n", | |
2732 | (ulong)q->d2.srb_ptr, q->d2.target_ix, q->d2.cdb_len, | |
2733 | q->d2.tag_code); | |
2734 | printk | |
2735 | (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n", | |
2736 | q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg); | |
1da177e4 LT |
2737 | } |
2738 | ||
2739 | /* | |
51219358 | 2740 | * asc_prt_adv_dvc_var() |
1da177e4 | 2741 | * |
51219358 | 2742 | * Display an ADV_DVC_VAR structure. |
1da177e4 | 2743 | */ |
51219358 | 2744 | static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h) |
1da177e4 | 2745 | { |
51219358 | 2746 | printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h); |
27c868c2 | 2747 | |
51219358 MW |
2748 | printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n", |
2749 | (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able); | |
1da177e4 | 2750 | |
51219358 MW |
2751 | printk(" isr_callback 0x%lx, sdtr_able 0x%x, wdtr_able 0x%x\n", |
2752 | (ulong)h->isr_callback, (unsigned)h->sdtr_able, | |
2753 | (unsigned)h->wdtr_able); | |
1da177e4 | 2754 | |
51219358 MW |
2755 | printk(" start_motor 0x%x, scsi_reset_wait 0x%x, irq_no 0x%x,\n", |
2756 | (unsigned)h->start_motor, | |
2757 | (unsigned)h->scsi_reset_wait, (unsigned)h->irq_no); | |
1da177e4 | 2758 | |
51219358 MW |
2759 | printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%lxn\n", |
2760 | (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng, | |
2761 | (ulong)h->carr_freelist); | |
1da177e4 | 2762 | |
51219358 MW |
2763 | printk(" icq_sp 0x%lx, irq_sp 0x%lx\n", |
2764 | (ulong)h->icq_sp, (ulong)h->irq_sp); | |
1da177e4 | 2765 | |
51219358 MW |
2766 | printk(" no_scam 0x%x, tagqng_able 0x%x\n", |
2767 | (unsigned)h->no_scam, (unsigned)h->tagqng_able); | |
1da177e4 | 2768 | |
51219358 MW |
2769 | printk(" chip_scsi_id 0x%x, cfg 0x%lx\n", |
2770 | (unsigned)h->chip_scsi_id, (ulong)h->cfg); | |
2771 | } | |
1da177e4 | 2772 | |
51219358 MW |
2773 | /* |
2774 | * asc_prt_adv_dvc_cfg() | |
2775 | * | |
2776 | * Display an ADV_DVC_CFG structure. | |
2777 | */ | |
2778 | static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h) | |
2779 | { | |
2780 | printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h); | |
27c868c2 | 2781 | |
51219358 MW |
2782 | printk(" disc_enable 0x%x, termination 0x%x\n", |
2783 | h->disc_enable, h->termination); | |
1da177e4 | 2784 | |
51219358 MW |
2785 | printk(" chip_version 0x%x, mcode_date 0x%x\n", |
2786 | h->chip_version, h->mcode_date); | |
27c868c2 | 2787 | |
51219358 MW |
2788 | printk(" mcode_version 0x%x, pci_device_id 0x%x, lib_version %u\n", |
2789 | h->mcode_version, to_pci_dev(h->dev)->device, h->lib_version); | |
1da177e4 | 2790 | |
51219358 | 2791 | printk(" control_flag 0x%x\n", h->control_flag); |
1da177e4 LT |
2792 | } |
2793 | ||
2794 | /* | |
51219358 | 2795 | * asc_prt_adv_scsi_req_q() |
1da177e4 | 2796 | * |
51219358 | 2797 | * Display an ADV_SCSI_REQ_Q structure. |
1da177e4 | 2798 | */ |
51219358 | 2799 | static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q) |
1da177e4 | 2800 | { |
51219358 MW |
2801 | int sg_blk_cnt; |
2802 | struct asc_sg_block *sg_ptr; | |
27c868c2 | 2803 | |
51219358 MW |
2804 | printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q); |
2805 | ||
2806 | printk(" target_id %u, target_lun %u, srb_ptr 0x%lx, a_flag 0x%x\n", | |
2807 | q->target_id, q->target_lun, (ulong)q->srb_ptr, q->a_flag); | |
2808 | ||
2809 | printk(" cntl 0x%x, data_addr 0x%lx, vdata_addr 0x%lx\n", | |
2810 | q->cntl, (ulong)le32_to_cpu(q->data_addr), (ulong)q->vdata_addr); | |
2811 | ||
2812 | printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n", | |
2813 | (ulong)le32_to_cpu(q->data_cnt), | |
2814 | (ulong)le32_to_cpu(q->sense_addr), q->sense_len); | |
2815 | ||
2816 | printk | |
2817 | (" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n", | |
2818 | q->cdb_len, q->done_status, q->host_status, q->scsi_status); | |
2819 | ||
2820 | printk(" sg_working_ix 0x%x, target_cmd %u\n", | |
2821 | q->sg_working_ix, q->target_cmd); | |
2822 | ||
2823 | printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n", | |
2824 | (ulong)le32_to_cpu(q->scsiq_rptr), | |
2825 | (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr); | |
2826 | ||
2827 | /* Display the request's ADV_SG_BLOCK structures. */ | |
2828 | if (q->sg_list_ptr != NULL) { | |
2829 | sg_blk_cnt = 0; | |
2830 | while (1) { | |
2831 | /* | |
2832 | * 'sg_ptr' is a physical address. Convert it to a virtual | |
2833 | * address by indexing 'sg_blk_cnt' into the virtual address | |
2834 | * array 'sg_list_ptr'. | |
2835 | * | |
2836 | * XXX - Assumes all SG physical blocks are virtually contiguous. | |
2837 | */ | |
2838 | sg_ptr = | |
2839 | &(((ADV_SG_BLOCK *)(q->sg_list_ptr))[sg_blk_cnt]); | |
2840 | asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr); | |
2841 | if (sg_ptr->sg_ptr == 0) { | |
2842 | break; | |
2843 | } | |
2844 | sg_blk_cnt++; | |
27c868c2 MW |
2845 | } |
2846 | } | |
1da177e4 LT |
2847 | } |
2848 | ||
1da177e4 | 2849 | /* |
51219358 | 2850 | * asc_prt_adv_sgblock() |
1da177e4 | 2851 | * |
51219358 | 2852 | * Display an ADV_SG_BLOCK structure. |
1da177e4 | 2853 | */ |
51219358 | 2854 | static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b) |
1da177e4 | 2855 | { |
51219358 | 2856 | int i; |
27c868c2 | 2857 | |
51219358 MW |
2858 | printk(" ASC_SG_BLOCK at addr 0x%lx (sgblockno %d)\n", |
2859 | (ulong)b, sgblockno); | |
2860 | printk(" sg_cnt %u, sg_ptr 0x%lx\n", | |
2861 | b->sg_cnt, (ulong)le32_to_cpu(b->sg_ptr)); | |
2862 | BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK); | |
2863 | if (b->sg_ptr != 0) | |
2864 | BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK); | |
2865 | for (i = 0; i < b->sg_cnt; i++) { | |
2866 | printk(" [%u]: sg_addr 0x%lx, sg_count 0x%lx\n", | |
2867 | i, (ulong)b->sg_list[i].sg_addr, | |
2868 | (ulong)b->sg_list[i].sg_count); | |
074c8fe4 | 2869 | } |
1da177e4 LT |
2870 | } |
2871 | ||
51219358 MW |
2872 | /* |
2873 | * asc_prt_hex() | |
2874 | * | |
2875 | * Print hexadecimal output in 4 byte groupings 32 bytes | |
2876 | * or 8 double-words per line. | |
2877 | */ | |
2878 | static void asc_prt_hex(char *f, uchar *s, int l) | |
47d853cc | 2879 | { |
51219358 MW |
2880 | int i; |
2881 | int j; | |
2882 | int k; | |
2883 | int m; | |
47d853cc | 2884 | |
51219358 MW |
2885 | printk("%s: (%d bytes)\n", f, l); |
2886 | ||
2887 | for (i = 0; i < l; i += 32) { | |
2888 | ||
2889 | /* Display a maximum of 8 double-words per line. */ | |
2890 | if ((k = (l - i) / 4) >= 8) { | |
2891 | k = 8; | |
2892 | m = 0; | |
47d853cc | 2893 | } else { |
51219358 | 2894 | m = (l - i) % 4; |
47d853cc MW |
2895 | } |
2896 | ||
51219358 MW |
2897 | for (j = 0; j < k; j++) { |
2898 | printk(" %2.2X%2.2X%2.2X%2.2X", | |
2899 | (unsigned)s[i + (j * 4)], | |
2900 | (unsigned)s[i + (j * 4) + 1], | |
2901 | (unsigned)s[i + (j * 4) + 2], | |
2902 | (unsigned)s[i + (j * 4) + 3]); | |
47d853cc | 2903 | } |
47d853cc | 2904 | |
51219358 MW |
2905 | switch (m) { |
2906 | case 0: | |
2907 | default: | |
2908 | break; | |
2909 | case 1: | |
2910 | printk(" %2.2X", (unsigned)s[i + (j * 4)]); | |
2911 | break; | |
2912 | case 2: | |
2913 | printk(" %2.2X%2.2X", | |
2914 | (unsigned)s[i + (j * 4)], | |
2915 | (unsigned)s[i + (j * 4) + 1]); | |
2916 | break; | |
2917 | case 3: | |
2918 | printk(" %2.2X%2.2X%2.2X", | |
2919 | (unsigned)s[i + (j * 4) + 1], | |
2920 | (unsigned)s[i + (j * 4) + 2], | |
2921 | (unsigned)s[i + (j * 4) + 3]); | |
2922 | break; | |
2923 | } | |
47d853cc | 2924 | |
51219358 | 2925 | printk("\n"); |
47d853cc MW |
2926 | } |
2927 | } | |
51219358 | 2928 | #endif /* ADVANSYS_DEBUG */ |
47d853cc | 2929 | |
1da177e4 | 2930 | /* |
51219358 | 2931 | * advansys_info() |
47d853cc | 2932 | * |
51219358 MW |
2933 | * Return suitable for printing on the console with the argument |
2934 | * adapter's configuration information. | |
2935 | * | |
2936 | * Note: The information line should not exceed ASC_INFO_SIZE bytes, | |
2937 | * otherwise the static 'info' array will be overrun. | |
1da177e4 | 2938 | */ |
51219358 | 2939 | static const char *advansys_info(struct Scsi_Host *shost) |
1da177e4 | 2940 | { |
51219358 MW |
2941 | static char info[ASC_INFO_SIZE]; |
2942 | asc_board_t *boardp; | |
2943 | ASC_DVC_VAR *asc_dvc_varp; | |
2944 | ADV_DVC_VAR *adv_dvc_varp; | |
2945 | char *busname; | |
2946 | char *widename = NULL; | |
1da177e4 | 2947 | |
51219358 MW |
2948 | boardp = ASC_BOARDP(shost); |
2949 | if (ASC_NARROW_BOARD(boardp)) { | |
2950 | asc_dvc_varp = &boardp->dvc_var.asc_dvc_var; | |
2951 | ASC_DBG(1, "advansys_info: begin\n"); | |
2952 | if (asc_dvc_varp->bus_type & ASC_IS_ISA) { | |
2953 | if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) == | |
2954 | ASC_IS_ISAPNP) { | |
2955 | busname = "ISA PnP"; | |
2956 | } else { | |
2957 | busname = "ISA"; | |
2958 | } | |
2959 | sprintf(info, | |
2960 | "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X", | |
2961 | ASC_VERSION, busname, | |
2962 | (ulong)shost->io_port, | |
2963 | (ulong)shost->io_port + ASC_IOADR_GAP - 1, | |
2964 | shost->irq, shost->dma_channel); | |
2965 | } else { | |
2966 | if (asc_dvc_varp->bus_type & ASC_IS_VL) { | |
2967 | busname = "VL"; | |
2968 | } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) { | |
2969 | busname = "EISA"; | |
2970 | } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) { | |
2971 | if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA) | |
2972 | == ASC_IS_PCI_ULTRA) { | |
2973 | busname = "PCI Ultra"; | |
2974 | } else { | |
2975 | busname = "PCI"; | |
2976 | } | |
2977 | } else { | |
2978 | busname = "?"; | |
2979 | ASC_PRINT2("advansys_info: board %d: unknown " | |
2980 | "bus type %d\n", boardp->id, | |
2981 | asc_dvc_varp->bus_type); | |
2982 | } | |
2983 | sprintf(info, | |
2984 | "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X", | |
2985 | ASC_VERSION, busname, (ulong)shost->io_port, | |
2986 | (ulong)shost->io_port + ASC_IOADR_GAP - 1, | |
2987 | shost->irq); | |
2988 | } | |
2989 | } else { | |
2990 | /* | |
2991 | * Wide Adapter Information | |
2992 | * | |
2993 | * Memory-mapped I/O is used instead of I/O space to access | |
2994 | * the adapter, but display the I/O Port range. The Memory | |
2995 | * I/O address is displayed through the driver /proc file. | |
2996 | */ | |
2997 | adv_dvc_varp = &boardp->dvc_var.adv_dvc_var; | |
2998 | if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { | |
2999 | widename = "Ultra-Wide"; | |
3000 | } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { | |
3001 | widename = "Ultra2-Wide"; | |
3002 | } else { | |
3003 | widename = "Ultra3-Wide"; | |
3004 | } | |
3005 | sprintf(info, | |
3006 | "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X", | |
3007 | ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base, | |
3008 | (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, shost->irq); | |
3009 | } | |
3010 | BUG_ON(strlen(info) >= ASC_INFO_SIZE); | |
3011 | ASC_DBG(1, "advansys_info: end\n"); | |
3012 | return info; | |
47d853cc MW |
3013 | } |
3014 | ||
51219358 | 3015 | #ifdef CONFIG_PROC_FS |
47d853cc | 3016 | /* |
51219358 | 3017 | * asc_prt_line() |
47d853cc | 3018 | * |
51219358 MW |
3019 | * If 'cp' is NULL print to the console, otherwise print to a buffer. |
3020 | * | |
3021 | * Return 0 if printing to the console, otherwise return the number of | |
3022 | * bytes written to the buffer. | |
3023 | * | |
3024 | * Note: If any single line is greater than ASC_PRTLINE_SIZE bytes the stack | |
3025 | * will be corrupted. 's[]' is defined to be ASC_PRTLINE_SIZE bytes. | |
47d853cc | 3026 | */ |
51219358 | 3027 | static int asc_prt_line(char *buf, int buflen, char *fmt, ...) |
47d853cc | 3028 | { |
51219358 MW |
3029 | va_list args; |
3030 | int ret; | |
3031 | char s[ASC_PRTLINE_SIZE]; | |
47d853cc | 3032 | |
51219358 MW |
3033 | va_start(args, fmt); |
3034 | ret = vsprintf(s, fmt, args); | |
3035 | BUG_ON(ret >= ASC_PRTLINE_SIZE); | |
3036 | if (buf == NULL) { | |
3037 | (void)printk(s); | |
3038 | ret = 0; | |
3039 | } else { | |
3040 | ret = min(buflen, ret); | |
3041 | memcpy(buf, s, ret); | |
3042 | } | |
3043 | va_end(args); | |
3044 | return ret; | |
47d853cc MW |
3045 | } |
3046 | ||
3047 | /* | |
51219358 | 3048 | * asc_prt_board_devices() |
47d853cc | 3049 | * |
51219358 MW |
3050 | * Print driver information for devices attached to the board. |
3051 | * | |
3052 | * Note: no single line should be greater than ASC_PRTLINE_SIZE, | |
3053 | * cf. asc_prt_line(). | |
3054 | * | |
3055 | * Return the number of characters copied into 'cp'. No more than | |
3056 | * 'cplen' characters will be copied to 'cp'. | |
47d853cc | 3057 | */ |
51219358 | 3058 | static int asc_prt_board_devices(struct Scsi_Host *shost, char *cp, int cplen) |
47d853cc | 3059 | { |
51219358 MW |
3060 | asc_board_t *boardp; |
3061 | int leftlen; | |
3062 | int totlen; | |
3063 | int len; | |
3064 | int chip_scsi_id; | |
3065 | int i; | |
47d853cc | 3066 | |
51219358 MW |
3067 | boardp = ASC_BOARDP(shost); |
3068 | leftlen = cplen; | |
3069 | totlen = len = 0; | |
47d853cc | 3070 | |
51219358 MW |
3071 | len = asc_prt_line(cp, leftlen, |
3072 | "\nDevice Information for AdvanSys SCSI Host %d:\n", | |
3073 | shost->host_no); | |
3074 | ASC_PRT_NEXT(); | |
47d853cc | 3075 | |
51219358 MW |
3076 | if (ASC_NARROW_BOARD(boardp)) { |
3077 | chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id; | |
3078 | } else { | |
3079 | chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id; | |
47d853cc MW |
3080 | } |
3081 | ||
51219358 MW |
3082 | len = asc_prt_line(cp, leftlen, "Target IDs Detected:"); |
3083 | ASC_PRT_NEXT(); | |
3084 | for (i = 0; i <= ADV_MAX_TID; i++) { | |
3085 | if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) { | |
3086 | len = asc_prt_line(cp, leftlen, " %X,", i); | |
3087 | ASC_PRT_NEXT(); | |
3088 | } | |
27c868c2 | 3089 | } |
51219358 MW |
3090 | len = asc_prt_line(cp, leftlen, " (%X=Host Adapter)\n", chip_scsi_id); |
3091 | ASC_PRT_NEXT(); | |
3092 | ||
3093 | return totlen; | |
47d853cc MW |
3094 | } |
3095 | ||
3096 | /* | |
51219358 | 3097 | * Display Wide Board BIOS Information. |
47d853cc | 3098 | */ |
51219358 | 3099 | static int asc_prt_adv_bios(struct Scsi_Host *shost, char *cp, int cplen) |
47d853cc | 3100 | { |
51219358 MW |
3101 | asc_board_t *boardp; |
3102 | int leftlen; | |
3103 | int totlen; | |
3104 | int len; | |
3105 | ushort major, minor, letter; | |
3106 | ||
3107 | boardp = ASC_BOARDP(shost); | |
3108 | leftlen = cplen; | |
3109 | totlen = len = 0; | |
3110 | ||
3111 | len = asc_prt_line(cp, leftlen, "\nROM BIOS Version: "); | |
3112 | ASC_PRT_NEXT(); | |
47d853cc MW |
3113 | |
3114 | /* | |
51219358 MW |
3115 | * If the BIOS saved a valid signature, then fill in |
3116 | * the BIOS code segment base address. | |
47d853cc | 3117 | */ |
51219358 MW |
3118 | if (boardp->bios_signature != 0x55AA) { |
3119 | len = asc_prt_line(cp, leftlen, "Disabled or Pre-3.1\n"); | |
3120 | ASC_PRT_NEXT(); | |
3121 | len = asc_prt_line(cp, leftlen, | |
3122 | "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n"); | |
3123 | ASC_PRT_NEXT(); | |
3124 | len = asc_prt_line(cp, leftlen, | |
3125 | "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n"); | |
3126 | ASC_PRT_NEXT(); | |
3127 | } else { | |
3128 | major = (boardp->bios_version >> 12) & 0xF; | |
3129 | minor = (boardp->bios_version >> 8) & 0xF; | |
3130 | letter = (boardp->bios_version & 0xFF); | |
47d853cc | 3131 | |
51219358 MW |
3132 | len = asc_prt_line(cp, leftlen, "%d.%d%c\n", |
3133 | major, minor, | |
3134 | letter >= 26 ? '?' : letter + 'A'); | |
3135 | ASC_PRT_NEXT(); | |
47d853cc | 3136 | |
51219358 MW |
3137 | /* |
3138 | * Current available ROM BIOS release is 3.1I for UW | |
3139 | * and 3.2I for U2W. This code doesn't differentiate | |
3140 | * UW and U2W boards. | |
3141 | */ | |
3142 | if (major < 3 || (major <= 3 && minor < 1) || | |
3143 | (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) { | |
3144 | len = asc_prt_line(cp, leftlen, | |
3145 | "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n"); | |
3146 | ASC_PRT_NEXT(); | |
3147 | len = asc_prt_line(cp, leftlen, | |
3148 | "ftp://ftp.connectcom.net/pub\n"); | |
3149 | ASC_PRT_NEXT(); | |
3150 | } | |
3151 | } | |
3152 | ||
3153 | return totlen; | |
1da177e4 LT |
3154 | } |
3155 | ||
1da177e4 | 3156 | /* |
51219358 MW |
3157 | * Add serial number to information bar if signature AAh |
3158 | * is found in at bit 15-9 (7 bits) of word 1. | |
1da177e4 | 3159 | * |
51219358 | 3160 | * Serial Number consists fo 12 alpha-numeric digits. |
1da177e4 | 3161 | * |
51219358 MW |
3162 | * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits) |
3163 | * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits) | |
3164 | * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits) | |
3165 | * 5 - Product revision (A-J) Word0: " " | |
1da177e4 | 3166 | * |
51219358 MW |
3167 | * Signature Word1: 15-9 (7 bits) |
3168 | * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit) | |
3169 | * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits) | |
1da177e4 | 3170 | * |
51219358 | 3171 | * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits) |
1da177e4 | 3172 | * |
51219358 | 3173 | * Note 1: Only production cards will have a serial number. |
1da177e4 | 3174 | * |
51219358 | 3175 | * Note 2: Signature is most significant 7 bits (0xFE). |
1da177e4 | 3176 | * |
51219358 | 3177 | * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE. |
1da177e4 | 3178 | */ |
51219358 | 3179 | static int asc_get_eeprom_string(ushort *serialnum, uchar *cp) |
1da177e4 | 3180 | { |
51219358 | 3181 | ushort w, num; |
27c868c2 | 3182 | |
51219358 MW |
3183 | if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) { |
3184 | return ASC_FALSE; | |
3185 | } else { | |
3186 | /* | |
3187 | * First word - 6 digits. | |
3188 | */ | |
3189 | w = serialnum[0]; | |
27c868c2 | 3190 | |
51219358 MW |
3191 | /* Product type - 1st digit. */ |
3192 | if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') { | |
3193 | /* Product type is P=Prototype */ | |
3194 | *cp += 0x8; | |
3195 | } | |
3196 | cp++; | |
3197 | ||
3198 | /* Manufacturing location - 2nd digit. */ | |
3199 | *cp++ = 'A' + ((w & 0x1C00) >> 10); | |
3200 | ||
3201 | /* Product ID - 3rd, 4th digits. */ | |
3202 | num = w & 0x3FF; | |
3203 | *cp++ = '0' + (num / 100); | |
3204 | num %= 100; | |
3205 | *cp++ = '0' + (num / 10); | |
3206 | ||
3207 | /* Product revision - 5th digit. */ | |
3208 | *cp++ = 'A' + (num % 10); | |
27c868c2 | 3209 | |
27c868c2 | 3210 | /* |
51219358 | 3211 | * Second word |
27c868c2 | 3212 | */ |
51219358 | 3213 | w = serialnum[1]; |
27c868c2 MW |
3214 | |
3215 | /* | |
51219358 | 3216 | * Year - 6th digit. |
27c868c2 | 3217 | * |
51219358 MW |
3218 | * If bit 15 of third word is set, then the |
3219 | * last digit of the year is greater than 7. | |
27c868c2 | 3220 | */ |
51219358 MW |
3221 | if (serialnum[2] & 0x8000) { |
3222 | *cp++ = '8' + ((w & 0x1C0) >> 6); | |
3223 | } else { | |
3224 | *cp++ = '0' + ((w & 0x1C0) >> 6); | |
27c868c2 MW |
3225 | } |
3226 | ||
51219358 MW |
3227 | /* Week of year - 7th, 8th digits. */ |
3228 | num = w & 0x003F; | |
3229 | *cp++ = '0' + num / 10; | |
3230 | num %= 10; | |
3231 | *cp++ = '0' + num; | |
27c868c2 MW |
3232 | |
3233 | /* | |
51219358 | 3234 | * Third word |
27c868c2 | 3235 | */ |
51219358 | 3236 | w = serialnum[2] & 0x7FFF; |
1da177e4 | 3237 | |
51219358 MW |
3238 | /* Serial number - 9th digit. */ |
3239 | *cp++ = 'A' + (w / 1000); | |
27c868c2 | 3240 | |
51219358 MW |
3241 | /* 10th, 11th, 12th digits. */ |
3242 | num = w % 1000; | |
3243 | *cp++ = '0' + num / 100; | |
3244 | num %= 100; | |
3245 | *cp++ = '0' + num / 10; | |
3246 | num %= 10; | |
3247 | *cp++ = '0' + num; | |
3248 | ||
3249 | *cp = '\0'; /* Null Terminate the string. */ | |
3250 | return ASC_TRUE; | |
3251 | } | |
1da177e4 LT |
3252 | } |
3253 | ||
3254 | /* | |
51219358 | 3255 | * asc_prt_asc_board_eeprom() |
1da177e4 | 3256 | * |
51219358 | 3257 | * Print board EEPROM configuration. |
1da177e4 | 3258 | * |
51219358 MW |
3259 | * Note: no single line should be greater than ASC_PRTLINE_SIZE, |
3260 | * cf. asc_prt_line(). | |
3261 | * | |
3262 | * Return the number of characters copied into 'cp'. No more than | |
3263 | * 'cplen' characters will be copied to 'cp'. | |
1da177e4 | 3264 | */ |
51219358 | 3265 | static int asc_prt_asc_board_eeprom(struct Scsi_Host *shost, char *cp, int cplen) |
1da177e4 | 3266 | { |
51219358 MW |
3267 | asc_board_t *boardp; |
3268 | ASC_DVC_VAR *asc_dvc_varp; | |
3269 | int leftlen; | |
3270 | int totlen; | |
3271 | int len; | |
3272 | ASCEEP_CONFIG *ep; | |
3273 | int i; | |
3274 | #ifdef CONFIG_ISA | |
3275 | int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 }; | |
3276 | #endif /* CONFIG_ISA */ | |
3277 | uchar serialstr[13]; | |
27c868c2 | 3278 | |
51219358 MW |
3279 | boardp = ASC_BOARDP(shost); |
3280 | asc_dvc_varp = &boardp->dvc_var.asc_dvc_var; | |
3281 | ep = &boardp->eep_config.asc_eep; | |
27c868c2 | 3282 | |
51219358 MW |
3283 | leftlen = cplen; |
3284 | totlen = len = 0; | |
27c868c2 | 3285 | |
51219358 MW |
3286 | len = asc_prt_line(cp, leftlen, |
3287 | "\nEEPROM Settings for AdvanSys SCSI Host %d:\n", | |
3288 | shost->host_no); | |
3289 | ASC_PRT_NEXT(); | |
1da177e4 | 3290 | |
51219358 MW |
3291 | if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr) |
3292 | == ASC_TRUE) { | |
3293 | len = | |
3294 | asc_prt_line(cp, leftlen, " Serial Number: %s\n", | |
3295 | serialstr); | |
3296 | ASC_PRT_NEXT(); | |
27c868c2 | 3297 | } else { |
51219358 MW |
3298 | if (ep->adapter_info[5] == 0xBB) { |
3299 | len = asc_prt_line(cp, leftlen, | |
3300 | " Default Settings Used for EEPROM-less Adapter.\n"); | |
3301 | ASC_PRT_NEXT(); | |
3302 | } else { | |
3303 | len = asc_prt_line(cp, leftlen, | |
3304 | " Serial Number Signature Not Present.\n"); | |
3305 | ASC_PRT_NEXT(); | |
27c868c2 | 3306 | } |
51219358 | 3307 | } |
27c868c2 | 3308 | |
51219358 MW |
3309 | len = asc_prt_line(cp, leftlen, |
3310 | " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n", | |
3311 | ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng, | |
3312 | ep->max_tag_qng); | |
3313 | ASC_PRT_NEXT(); | |
1da177e4 | 3314 | |
51219358 MW |
3315 | len = asc_prt_line(cp, leftlen, |
3316 | " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam); | |
3317 | ASC_PRT_NEXT(); | |
27c868c2 | 3318 | |
51219358 MW |
3319 | len = asc_prt_line(cp, leftlen, " Target ID: "); |
3320 | ASC_PRT_NEXT(); | |
3321 | for (i = 0; i <= ASC_MAX_TID; i++) { | |
3322 | len = asc_prt_line(cp, leftlen, " %d", i); | |
3323 | ASC_PRT_NEXT(); | |
3324 | } | |
3325 | len = asc_prt_line(cp, leftlen, "\n"); | |
3326 | ASC_PRT_NEXT(); | |
1da177e4 | 3327 | |
51219358 MW |
3328 | len = asc_prt_line(cp, leftlen, " Disconnects: "); |
3329 | ASC_PRT_NEXT(); | |
3330 | for (i = 0; i <= ASC_MAX_TID; i++) { | |
3331 | len = asc_prt_line(cp, leftlen, " %c", | |
3332 | (ep-> | |
3333 | disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' : | |
3334 | 'N'); | |
3335 | ASC_PRT_NEXT(); | |
27c868c2 | 3336 | } |
51219358 MW |
3337 | len = asc_prt_line(cp, leftlen, "\n"); |
3338 | ASC_PRT_NEXT(); | |
1da177e4 | 3339 | |
51219358 MW |
3340 | len = asc_prt_line(cp, leftlen, " Command Queuing: "); |
3341 | ASC_PRT_NEXT(); | |
3342 | for (i = 0; i <= ASC_MAX_TID; i++) { | |
3343 | len = asc_prt_line(cp, leftlen, " %c", | |
3344 | (ep-> | |
3345 | use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : | |
3346 | 'N'); | |
3347 | ASC_PRT_NEXT(); | |
3348 | } | |
3349 | len = asc_prt_line(cp, leftlen, "\n"); | |
3350 | ASC_PRT_NEXT(); | |
1da177e4 | 3351 | |
51219358 MW |
3352 | len = asc_prt_line(cp, leftlen, " Start Motor: "); |
3353 | ASC_PRT_NEXT(); | |
3354 | for (i = 0; i <= ASC_MAX_TID; i++) { | |
3355 | len = asc_prt_line(cp, leftlen, " %c", | |
3356 | (ep-> | |
3357 | start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' : | |
3358 | 'N'); | |
3359 | ASC_PRT_NEXT(); | |
3360 | } | |
3361 | len = asc_prt_line(cp, leftlen, "\n"); | |
3362 | ASC_PRT_NEXT(); | |
3363 | ||
3364 | len = asc_prt_line(cp, leftlen, " Synchronous Transfer:"); | |
3365 | ASC_PRT_NEXT(); | |
3366 | for (i = 0; i <= ASC_MAX_TID; i++) { | |
3367 | len = asc_prt_line(cp, leftlen, " %c", | |
3368 | (ep-> | |
3369 | init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' : | |
3370 | 'N'); | |
3371 | ASC_PRT_NEXT(); | |
3372 | } | |
3373 | len = asc_prt_line(cp, leftlen, "\n"); | |
3374 | ASC_PRT_NEXT(); | |
3375 | ||
3376 | #ifdef CONFIG_ISA | |
3377 | if (asc_dvc_varp->bus_type & ASC_IS_ISA) { | |
3378 | len = asc_prt_line(cp, leftlen, | |
3379 | " Host ISA DMA speed: %d MB/S\n", | |
3380 | isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]); | |
3381 | ASC_PRT_NEXT(); | |
3382 | } | |
3383 | #endif /* CONFIG_ISA */ | |
3384 | ||
3385 | return totlen; | |
1da177e4 LT |
3386 | } |
3387 | ||
3388 | /* | |
51219358 | 3389 | * asc_prt_adv_board_eeprom() |
1da177e4 | 3390 | * |
51219358 | 3391 | * Print board EEPROM configuration. |
1da177e4 | 3392 | * |
51219358 MW |
3393 | * Note: no single line should be greater than ASC_PRTLINE_SIZE, |
3394 | * cf. asc_prt_line(). | |
3395 | * | |
3396 | * Return the number of characters copied into 'cp'. No more than | |
3397 | * 'cplen' characters will be copied to 'cp'. | |
1da177e4 | 3398 | */ |
51219358 | 3399 | static int asc_prt_adv_board_eeprom(struct Scsi_Host *shost, char *cp, int cplen) |
1da177e4 | 3400 | { |
51219358 MW |
3401 | asc_board_t *boardp; |
3402 | ADV_DVC_VAR *adv_dvc_varp; | |
3403 | int leftlen; | |
3404 | int totlen; | |
3405 | int len; | |
27c868c2 | 3406 | int i; |
51219358 MW |
3407 | char *termstr; |
3408 | uchar serialstr[13]; | |
3409 | ADVEEP_3550_CONFIG *ep_3550 = NULL; | |
3410 | ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL; | |
3411 | ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL; | |
3412 | ushort word; | |
3413 | ushort *wordp; | |
3414 | ushort sdtr_speed = 0; | |
27c868c2 | 3415 | |
51219358 MW |
3416 | boardp = ASC_BOARDP(shost); |
3417 | adv_dvc_varp = &boardp->dvc_var.adv_dvc_var; | |
3418 | if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { | |
3419 | ep_3550 = &boardp->eep_config.adv_3550_eep; | |
3420 | } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { | |
3421 | ep_38C0800 = &boardp->eep_config.adv_38C0800_eep; | |
27c868c2 | 3422 | } else { |
51219358 | 3423 | ep_38C1600 = &boardp->eep_config.adv_38C1600_eep; |
27c868c2 | 3424 | } |
1da177e4 | 3425 | |
51219358 MW |
3426 | leftlen = cplen; |
3427 | totlen = len = 0; | |
27c868c2 | 3428 | |
51219358 MW |
3429 | len = asc_prt_line(cp, leftlen, |
3430 | "\nEEPROM Settings for AdvanSys SCSI Host %d:\n", | |
3431 | shost->host_no); | |
3432 | ASC_PRT_NEXT(); | |
27c868c2 | 3433 | |
51219358 MW |
3434 | if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { |
3435 | wordp = &ep_3550->serial_number_word1; | |
3436 | } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { | |
3437 | wordp = &ep_38C0800->serial_number_word1; | |
3438 | } else { | |
3439 | wordp = &ep_38C1600->serial_number_word1; | |
3440 | } | |
27c868c2 | 3441 | |
51219358 MW |
3442 | if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE) { |
3443 | len = | |
3444 | asc_prt_line(cp, leftlen, " Serial Number: %s\n", | |
3445 | serialstr); | |
3446 | ASC_PRT_NEXT(); | |
3447 | } else { | |
3448 | len = asc_prt_line(cp, leftlen, | |
3449 | " Serial Number Signature Not Present.\n"); | |
3450 | ASC_PRT_NEXT(); | |
3451 | } | |
27c868c2 | 3452 | |
51219358 MW |
3453 | if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { |
3454 | len = asc_prt_line(cp, leftlen, | |
3455 | " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n", | |
3456 | ep_3550->adapter_scsi_id, | |
3457 | ep_3550->max_host_qng, ep_3550->max_dvc_qng); | |
3458 | ASC_PRT_NEXT(); | |
3459 | } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { | |
3460 | len = asc_prt_line(cp, leftlen, | |
3461 | " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n", | |
3462 | ep_38C0800->adapter_scsi_id, | |
3463 | ep_38C0800->max_host_qng, | |
3464 | ep_38C0800->max_dvc_qng); | |
3465 | ASC_PRT_NEXT(); | |
3466 | } else { | |
3467 | len = asc_prt_line(cp, leftlen, | |
3468 | " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n", | |
3469 | ep_38C1600->adapter_scsi_id, | |
3470 | ep_38C1600->max_host_qng, | |
3471 | ep_38C1600->max_dvc_qng); | |
3472 | ASC_PRT_NEXT(); | |
27c868c2 | 3473 | } |
51219358 MW |
3474 | if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { |
3475 | word = ep_3550->termination; | |
3476 | } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { | |
3477 | word = ep_38C0800->termination_lvd; | |
3478 | } else { | |
3479 | word = ep_38C1600->termination_lvd; | |
3480 | } | |
3481 | switch (word) { | |
3482 | case 1: | |
3483 | termstr = "Low Off/High Off"; | |
3484 | break; | |
3485 | case 2: | |
3486 | termstr = "Low Off/High On"; | |
3487 | break; | |
3488 | case 3: | |
3489 | termstr = "Low On/High On"; | |
3490 | break; | |
3491 | default: | |
3492 | case 0: | |
3493 | termstr = "Automatic"; | |
3494 | break; | |
27c868c2 | 3495 | } |
1da177e4 | 3496 | |
51219358 MW |
3497 | if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { |
3498 | len = asc_prt_line(cp, leftlen, | |
3499 | " termination: %u (%s), bios_ctrl: 0x%x\n", | |
3500 | ep_3550->termination, termstr, | |
3501 | ep_3550->bios_ctrl); | |
3502 | ASC_PRT_NEXT(); | |
3503 | } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { | |
3504 | len = asc_prt_line(cp, leftlen, | |
3505 | " termination: %u (%s), bios_ctrl: 0x%x\n", | |
3506 | ep_38C0800->termination_lvd, termstr, | |
3507 | ep_38C0800->bios_ctrl); | |
3508 | ASC_PRT_NEXT(); | |
3509 | } else { | |
3510 | len = asc_prt_line(cp, leftlen, | |
3511 | " termination: %u (%s), bios_ctrl: 0x%x\n", | |
3512 | ep_38C1600->termination_lvd, termstr, | |
3513 | ep_38C1600->bios_ctrl); | |
3514 | ASC_PRT_NEXT(); | |
3515 | } | |
1da177e4 | 3516 | |
51219358 MW |
3517 | len = asc_prt_line(cp, leftlen, " Target ID: "); |
3518 | ASC_PRT_NEXT(); | |
3519 | for (i = 0; i <= ADV_MAX_TID; i++) { | |
3520 | len = asc_prt_line(cp, leftlen, " %X", i); | |
3521 | ASC_PRT_NEXT(); | |
3522 | } | |
3523 | len = asc_prt_line(cp, leftlen, "\n"); | |
3524 | ASC_PRT_NEXT(); | |
1da177e4 | 3525 | |
51219358 MW |
3526 | if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { |
3527 | word = ep_3550->disc_enable; | |
3528 | } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { | |
3529 | word = ep_38C0800->disc_enable; | |
3530 | } else { | |
3531 | word = ep_38C1600->disc_enable; | |
3532 | } | |
3533 | len = asc_prt_line(cp, leftlen, " Disconnects: "); | |
3534 | ASC_PRT_NEXT(); | |
3535 | for (i = 0; i <= ADV_MAX_TID; i++) { | |
3536 | len = asc_prt_line(cp, leftlen, " %c", | |
3537 | (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); | |
3538 | ASC_PRT_NEXT(); | |
3539 | } | |
3540 | len = asc_prt_line(cp, leftlen, "\n"); | |
3541 | ASC_PRT_NEXT(); | |
1da177e4 | 3542 | |
51219358 MW |
3543 | if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { |
3544 | word = ep_3550->tagqng_able; | |
3545 | } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { | |
3546 | word = ep_38C0800->tagqng_able; | |
3547 | } else { | |
3548 | word = ep_38C1600->tagqng_able; | |
3549 | } | |
3550 | len = asc_prt_line(cp, leftlen, " Command Queuing: "); | |
3551 | ASC_PRT_NEXT(); | |
3552 | for (i = 0; i <= ADV_MAX_TID; i++) { | |
3553 | len = asc_prt_line(cp, leftlen, " %c", | |
3554 | (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); | |
3555 | ASC_PRT_NEXT(); | |
3556 | } | |
3557 | len = asc_prt_line(cp, leftlen, "\n"); | |
3558 | ASC_PRT_NEXT(); | |
1da177e4 | 3559 | |
51219358 MW |
3560 | if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { |
3561 | word = ep_3550->start_motor; | |
3562 | } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { | |
3563 | word = ep_38C0800->start_motor; | |
27c868c2 | 3564 | } else { |
51219358 MW |
3565 | word = ep_38C1600->start_motor; |
3566 | } | |
3567 | len = asc_prt_line(cp, leftlen, " Start Motor: "); | |
3568 | ASC_PRT_NEXT(); | |
3569 | for (i = 0; i <= ADV_MAX_TID; i++) { | |
3570 | len = asc_prt_line(cp, leftlen, " %c", | |
3571 | (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); | |
3572 | ASC_PRT_NEXT(); | |
3573 | } | |
3574 | len = asc_prt_line(cp, leftlen, "\n"); | |
3575 | ASC_PRT_NEXT(); | |
27c868c2 | 3576 | |
51219358 MW |
3577 | if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { |
3578 | len = asc_prt_line(cp, leftlen, " Synchronous Transfer:"); | |
3579 | ASC_PRT_NEXT(); | |
3580 | for (i = 0; i <= ADV_MAX_TID; i++) { | |
3581 | len = asc_prt_line(cp, leftlen, " %c", | |
3582 | (ep_3550-> | |
3583 | sdtr_able & ADV_TID_TO_TIDMASK(i)) ? | |
3584 | 'Y' : 'N'); | |
3585 | ASC_PRT_NEXT(); | |
27c868c2 | 3586 | } |
51219358 MW |
3587 | len = asc_prt_line(cp, leftlen, "\n"); |
3588 | ASC_PRT_NEXT(); | |
3589 | } | |
27c868c2 | 3590 | |
51219358 MW |
3591 | if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { |
3592 | len = asc_prt_line(cp, leftlen, " Ultra Transfer: "); | |
3593 | ASC_PRT_NEXT(); | |
3594 | for (i = 0; i <= ADV_MAX_TID; i++) { | |
3595 | len = asc_prt_line(cp, leftlen, " %c", | |
3596 | (ep_3550-> | |
3597 | ultra_able & ADV_TID_TO_TIDMASK(i)) | |
3598 | ? 'Y' : 'N'); | |
3599 | ASC_PRT_NEXT(); | |
27c868c2 | 3600 | } |
51219358 MW |
3601 | len = asc_prt_line(cp, leftlen, "\n"); |
3602 | ASC_PRT_NEXT(); | |
3603 | } | |
27c868c2 | 3604 | |
51219358 MW |
3605 | if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { |
3606 | word = ep_3550->wdtr_able; | |
3607 | } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { | |
3608 | word = ep_38C0800->wdtr_able; | |
3609 | } else { | |
3610 | word = ep_38C1600->wdtr_able; | |
3611 | } | |
3612 | len = asc_prt_line(cp, leftlen, " Wide Transfer: "); | |
3613 | ASC_PRT_NEXT(); | |
3614 | for (i = 0; i <= ADV_MAX_TID; i++) { | |
3615 | len = asc_prt_line(cp, leftlen, " %c", | |
3616 | (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); | |
3617 | ASC_PRT_NEXT(); | |
27c868c2 | 3618 | } |
51219358 MW |
3619 | len = asc_prt_line(cp, leftlen, "\n"); |
3620 | ASC_PRT_NEXT(); | |
1da177e4 | 3621 | |
51219358 MW |
3622 | if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 || |
3623 | adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) { | |
3624 | len = asc_prt_line(cp, leftlen, | |
3625 | " Synchronous Transfer Speed (Mhz):\n "); | |
3626 | ASC_PRT_NEXT(); | |
3627 | for (i = 0; i <= ADV_MAX_TID; i++) { | |
3628 | char *speed_str; | |
1da177e4 | 3629 | |
51219358 MW |
3630 | if (i == 0) { |
3631 | sdtr_speed = adv_dvc_varp->sdtr_speed1; | |
3632 | } else if (i == 4) { | |
3633 | sdtr_speed = adv_dvc_varp->sdtr_speed2; | |
3634 | } else if (i == 8) { | |
3635 | sdtr_speed = adv_dvc_varp->sdtr_speed3; | |
3636 | } else if (i == 12) { | |
3637 | sdtr_speed = adv_dvc_varp->sdtr_speed4; | |
3638 | } | |
3639 | switch (sdtr_speed & ADV_MAX_TID) { | |
3640 | case 0: | |
3641 | speed_str = "Off"; | |
3642 | break; | |
3643 | case 1: | |
3644 | speed_str = " 5"; | |
3645 | break; | |
3646 | case 2: | |
3647 | speed_str = " 10"; | |
3648 | break; | |
3649 | case 3: | |
3650 | speed_str = " 20"; | |
3651 | break; | |
3652 | case 4: | |
3653 | speed_str = " 40"; | |
3654 | break; | |
3655 | case 5: | |
3656 | speed_str = " 80"; | |
3657 | break; | |
3658 | default: | |
3659 | speed_str = "Unk"; | |
3660 | break; | |
3661 | } | |
3662 | len = asc_prt_line(cp, leftlen, "%X:%s ", i, speed_str); | |
3663 | ASC_PRT_NEXT(); | |
3664 | if (i == 7) { | |
3665 | len = asc_prt_line(cp, leftlen, "\n "); | |
3666 | ASC_PRT_NEXT(); | |
3667 | } | |
3668 | sdtr_speed >>= 4; | |
3669 | } | |
3670 | len = asc_prt_line(cp, leftlen, "\n"); | |
3671 | ASC_PRT_NEXT(); | |
3672 | } | |
1da177e4 | 3673 | |
51219358 | 3674 | return totlen; |
1da177e4 LT |
3675 | } |
3676 | ||
3677 | /* | |
51219358 | 3678 | * asc_prt_driver_conf() |
1da177e4 | 3679 | * |
51219358 MW |
3680 | * Note: no single line should be greater than ASC_PRTLINE_SIZE, |
3681 | * cf. asc_prt_line(). | |
1da177e4 | 3682 | * |
51219358 MW |
3683 | * Return the number of characters copied into 'cp'. No more than |
3684 | * 'cplen' characters will be copied to 'cp'. | |
1da177e4 | 3685 | */ |
51219358 | 3686 | static int asc_prt_driver_conf(struct Scsi_Host *shost, char *cp, int cplen) |
1da177e4 | 3687 | { |
51219358 MW |
3688 | asc_board_t *boardp; |
3689 | int leftlen; | |
3690 | int totlen; | |
3691 | int len; | |
3692 | int chip_scsi_id; | |
27c868c2 | 3693 | |
51219358 | 3694 | boardp = ASC_BOARDP(shost); |
27c868c2 | 3695 | |
51219358 MW |
3696 | leftlen = cplen; |
3697 | totlen = len = 0; | |
27c868c2 | 3698 | |
51219358 MW |
3699 | len = asc_prt_line(cp, leftlen, |
3700 | "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n", | |
3701 | shost->host_no); | |
3702 | ASC_PRT_NEXT(); | |
95c9f162 | 3703 | |
51219358 MW |
3704 | len = asc_prt_line(cp, leftlen, |
3705 | " host_busy %u, last_reset %u, max_id %u, max_lun %u, max_channel %u\n", | |
3706 | shost->host_busy, shost->last_reset, shost->max_id, | |
3707 | shost->max_lun, shost->max_channel); | |
3708 | ASC_PRT_NEXT(); | |
95c9f162 | 3709 | |
51219358 MW |
3710 | len = asc_prt_line(cp, leftlen, |
3711 | " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n", | |
3712 | shost->unique_id, shost->can_queue, shost->this_id, | |
3713 | shost->sg_tablesize, shost->cmd_per_lun); | |
3714 | ASC_PRT_NEXT(); | |
95c9f162 | 3715 | |
51219358 MW |
3716 | len = asc_prt_line(cp, leftlen, |
3717 | " unchecked_isa_dma %d, use_clustering %d\n", | |
3718 | shost->unchecked_isa_dma, shost->use_clustering); | |
3719 | ASC_PRT_NEXT(); | |
27c868c2 | 3720 | |
51219358 MW |
3721 | len = asc_prt_line(cp, leftlen, |
3722 | " flags 0x%x, last_reset 0x%x, jiffies 0x%x, asc_n_io_port 0x%x\n", | |
3723 | boardp->flags, boardp->last_reset, jiffies, | |
3724 | boardp->asc_n_io_port); | |
3725 | ASC_PRT_NEXT(); | |
27c868c2 | 3726 | |
51219358 MW |
3727 | len = asc_prt_line(cp, leftlen, " io_port 0x%x\n", shost->io_port); |
3728 | ASC_PRT_NEXT(); | |
27c868c2 | 3729 | |
51219358 MW |
3730 | if (ASC_NARROW_BOARD(boardp)) { |
3731 | chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id; | |
3732 | } else { | |
3733 | chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id; | |
27c868c2 | 3734 | } |
51219358 MW |
3735 | |
3736 | return totlen; | |
1da177e4 LT |
3737 | } |
3738 | ||
3739 | /* | |
51219358 | 3740 | * asc_prt_asc_board_info() |
1da177e4 | 3741 | * |
51219358 MW |
3742 | * Print dynamic board configuration information. |
3743 | * | |
3744 | * Note: no single line should be greater than ASC_PRTLINE_SIZE, | |
3745 | * cf. asc_prt_line(). | |
3746 | * | |
3747 | * Return the number of characters copied into 'cp'. No more than | |
3748 | * 'cplen' characters will be copied to 'cp'. | |
1da177e4 | 3749 | */ |
51219358 | 3750 | static int asc_prt_asc_board_info(struct Scsi_Host *shost, char *cp, int cplen) |
1da177e4 | 3751 | { |
27c868c2 | 3752 | asc_board_t *boardp; |
51219358 MW |
3753 | int chip_scsi_id; |
3754 | int leftlen; | |
3755 | int totlen; | |
3756 | int len; | |
3757 | ASC_DVC_VAR *v; | |
3758 | ASC_DVC_CFG *c; | |
3759 | int i; | |
3760 | int renegotiate = 0; | |
27c868c2 | 3761 | |
51219358 MW |
3762 | boardp = ASC_BOARDP(shost); |
3763 | v = &boardp->dvc_var.asc_dvc_var; | |
3764 | c = &boardp->dvc_cfg.asc_dvc_cfg; | |
3765 | chip_scsi_id = c->chip_scsi_id; | |
27c868c2 | 3766 | |
51219358 MW |
3767 | leftlen = cplen; |
3768 | totlen = len = 0; | |
27c868c2 | 3769 | |
51219358 MW |
3770 | len = asc_prt_line(cp, leftlen, |
3771 | "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n", | |
3772 | shost->host_no); | |
3773 | ASC_PRT_NEXT(); | |
27c868c2 | 3774 | |
51219358 MW |
3775 | len = asc_prt_line(cp, leftlen, |
3776 | " chip_version %u, lib_version 0x%x, lib_serial_no %u, mcode_date 0x%x\n", | |
3777 | c->chip_version, c->lib_version, c->lib_serial_no, | |
3778 | c->mcode_date); | |
3779 | ASC_PRT_NEXT(); | |
27c868c2 | 3780 | |
51219358 MW |
3781 | len = asc_prt_line(cp, leftlen, |
3782 | " mcode_version 0x%x, err_code %u\n", | |
3783 | c->mcode_version, v->err_code); | |
3784 | ASC_PRT_NEXT(); | |
1da177e4 | 3785 | |
51219358 MW |
3786 | /* Current number of commands waiting for the host. */ |
3787 | len = asc_prt_line(cp, leftlen, | |
3788 | " Total Command Pending: %d\n", v->cur_total_qng); | |
3789 | ASC_PRT_NEXT(); | |
1da177e4 | 3790 | |
51219358 MW |
3791 | len = asc_prt_line(cp, leftlen, " Command Queuing:"); |
3792 | ASC_PRT_NEXT(); | |
3793 | for (i = 0; i <= ASC_MAX_TID; i++) { | |
3794 | if ((chip_scsi_id == i) || | |
3795 | ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { | |
3796 | continue; | |
27c868c2 | 3797 | } |
51219358 MW |
3798 | len = asc_prt_line(cp, leftlen, " %X:%c", |
3799 | i, | |
3800 | (v-> | |
3801 | use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? | |
3802 | 'Y' : 'N'); | |
3803 | ASC_PRT_NEXT(); | |
3804 | } | |
3805 | len = asc_prt_line(cp, leftlen, "\n"); | |
3806 | ASC_PRT_NEXT(); | |
27c868c2 | 3807 | |
51219358 MW |
3808 | /* Current number of commands waiting for a device. */ |
3809 | len = asc_prt_line(cp, leftlen, " Command Queue Pending:"); | |
3810 | ASC_PRT_NEXT(); | |
3811 | for (i = 0; i <= ASC_MAX_TID; i++) { | |
3812 | if ((chip_scsi_id == i) || | |
3813 | ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { | |
3814 | continue; | |
27c868c2 | 3815 | } |
51219358 MW |
3816 | len = asc_prt_line(cp, leftlen, " %X:%u", i, v->cur_dvc_qng[i]); |
3817 | ASC_PRT_NEXT(); | |
27c868c2 | 3818 | } |
51219358 MW |
3819 | len = asc_prt_line(cp, leftlen, "\n"); |
3820 | ASC_PRT_NEXT(); | |
1da177e4 | 3821 | |
51219358 MW |
3822 | /* Current limit on number of commands that can be sent to a device. */ |
3823 | len = asc_prt_line(cp, leftlen, " Command Queue Limit:"); | |
3824 | ASC_PRT_NEXT(); | |
3825 | for (i = 0; i <= ASC_MAX_TID; i++) { | |
3826 | if ((chip_scsi_id == i) || | |
3827 | ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { | |
3828 | continue; | |
3829 | } | |
3830 | len = asc_prt_line(cp, leftlen, " %X:%u", i, v->max_dvc_qng[i]); | |
3831 | ASC_PRT_NEXT(); | |
27c868c2 | 3832 | } |
51219358 MW |
3833 | len = asc_prt_line(cp, leftlen, "\n"); |
3834 | ASC_PRT_NEXT(); | |
1da177e4 | 3835 | |
51219358 MW |
3836 | /* Indicate whether the device has returned queue full status. */ |
3837 | len = asc_prt_line(cp, leftlen, " Command Queue Full:"); | |
3838 | ASC_PRT_NEXT(); | |
3839 | for (i = 0; i <= ASC_MAX_TID; i++) { | |
3840 | if ((chip_scsi_id == i) || | |
3841 | ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { | |
3842 | continue; | |
3843 | } | |
3844 | if (boardp->queue_full & ADV_TID_TO_TIDMASK(i)) { | |
3845 | len = asc_prt_line(cp, leftlen, " %X:Y-%d", | |
3846 | i, boardp->queue_full_cnt[i]); | |
3847 | } else { | |
3848 | len = asc_prt_line(cp, leftlen, " %X:N", i); | |
3849 | } | |
3850 | ASC_PRT_NEXT(); | |
3851 | } | |
3852 | len = asc_prt_line(cp, leftlen, "\n"); | |
3853 | ASC_PRT_NEXT(); | |
1da177e4 | 3854 | |
51219358 MW |
3855 | len = asc_prt_line(cp, leftlen, " Synchronous Transfer:"); |
3856 | ASC_PRT_NEXT(); | |
3857 | for (i = 0; i <= ASC_MAX_TID; i++) { | |
3858 | if ((chip_scsi_id == i) || | |
3859 | ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { | |
3860 | continue; | |
3861 | } | |
3862 | len = asc_prt_line(cp, leftlen, " %X:%c", | |
3863 | i, | |
3864 | (v-> | |
3865 | sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : | |
3866 | 'N'); | |
3867 | ASC_PRT_NEXT(); | |
27c868c2 | 3868 | } |
51219358 MW |
3869 | len = asc_prt_line(cp, leftlen, "\n"); |
3870 | ASC_PRT_NEXT(); | |
1da177e4 | 3871 | |
51219358 MW |
3872 | for (i = 0; i <= ASC_MAX_TID; i++) { |
3873 | uchar syn_period_ix; | |
1da177e4 | 3874 | |
51219358 MW |
3875 | if ((chip_scsi_id == i) || |
3876 | ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) || | |
3877 | ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) { | |
3878 | continue; | |
27c868c2 | 3879 | } |
27c868c2 | 3880 | |
51219358 MW |
3881 | len = asc_prt_line(cp, leftlen, " %X:", i); |
3882 | ASC_PRT_NEXT(); | |
27c868c2 | 3883 | |
51219358 MW |
3884 | if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) { |
3885 | len = asc_prt_line(cp, leftlen, " Asynchronous"); | |
3886 | ASC_PRT_NEXT(); | |
3887 | } else { | |
3888 | syn_period_ix = | |
3889 | (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index - | |
3890 | 1); | |
27c868c2 | 3891 | |
51219358 MW |
3892 | len = asc_prt_line(cp, leftlen, |
3893 | " Transfer Period Factor: %d (%d.%d Mhz),", | |
3894 | v->sdtr_period_tbl[syn_period_ix], | |
3895 | 250 / | |
3896 | v->sdtr_period_tbl[syn_period_ix], | |
3897 | ASC_TENTHS(250, | |
3898 | v-> | |
3899 | sdtr_period_tbl | |
3900 | [syn_period_ix])); | |
3901 | ASC_PRT_NEXT(); | |
27c868c2 | 3902 | |
51219358 MW |
3903 | len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d", |
3904 | boardp-> | |
3905 | sdtr_data[i] & ASC_SYN_MAX_OFFSET); | |
3906 | ASC_PRT_NEXT(); | |
3907 | } | |
1da177e4 | 3908 | |
51219358 MW |
3909 | if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) { |
3910 | len = asc_prt_line(cp, leftlen, "*\n"); | |
3911 | renegotiate = 1; | |
3912 | } else { | |
3913 | len = asc_prt_line(cp, leftlen, "\n"); | |
3914 | } | |
3915 | ASC_PRT_NEXT(); | |
27c868c2 | 3916 | } |
1da177e4 | 3917 | |
51219358 MW |
3918 | if (renegotiate) { |
3919 | len = asc_prt_line(cp, leftlen, | |
3920 | " * = Re-negotiation pending before next command.\n"); | |
3921 | ASC_PRT_NEXT(); | |
27c868c2 | 3922 | } |
1da177e4 | 3923 | |
51219358 | 3924 | return totlen; |
1da177e4 LT |
3925 | } |
3926 | ||
1da177e4 | 3927 | /* |
51219358 | 3928 | * asc_prt_adv_board_info() |
1da177e4 | 3929 | * |
51219358 | 3930 | * Print dynamic board configuration information. |
1da177e4 LT |
3931 | * |
3932 | * Note: no single line should be greater than ASC_PRTLINE_SIZE, | |
3933 | * cf. asc_prt_line(). | |
3934 | * | |
3935 | * Return the number of characters copied into 'cp'. No more than | |
3936 | * 'cplen' characters will be copied to 'cp'. | |
3937 | */ | |
51219358 | 3938 | static int asc_prt_adv_board_info(struct Scsi_Host *shost, char *cp, int cplen) |
1da177e4 | 3939 | { |
27c868c2 MW |
3940 | asc_board_t *boardp; |
3941 | int leftlen; | |
3942 | int totlen; | |
3943 | int len; | |
27c868c2 | 3944 | int i; |
51219358 MW |
3945 | ADV_DVC_VAR *v; |
3946 | ADV_DVC_CFG *c; | |
3947 | AdvPortAddr iop_base; | |
3948 | ushort chip_scsi_id; | |
3949 | ushort lramword; | |
3950 | uchar lrambyte; | |
3951 | ushort tagqng_able; | |
3952 | ushort sdtr_able, wdtr_able; | |
3953 | ushort wdtr_done, sdtr_done; | |
3954 | ushort period = 0; | |
3955 | int renegotiate = 0; | |
27c868c2 MW |
3956 | |
3957 | boardp = ASC_BOARDP(shost); | |
51219358 MW |
3958 | v = &boardp->dvc_var.adv_dvc_var; |
3959 | c = &boardp->dvc_cfg.adv_dvc_cfg; | |
3960 | iop_base = v->iop_base; | |
3961 | chip_scsi_id = v->chip_scsi_id; | |
3962 | ||
27c868c2 MW |
3963 | leftlen = cplen; |
3964 | totlen = len = 0; | |
3965 | ||
3966 | len = asc_prt_line(cp, leftlen, | |
51219358 | 3967 | "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n", |
27c868c2 MW |
3968 | shost->host_no); |
3969 | ASC_PRT_NEXT(); | |
3970 | ||
51219358 MW |
3971 | len = asc_prt_line(cp, leftlen, |
3972 | " iop_base 0x%lx, cable_detect: %X, err_code %u\n", | |
3973 | v->iop_base, | |
3974 | AdvReadWordRegister(iop_base, | |
3975 | IOPW_SCSI_CFG1) & CABLE_DETECT, | |
3976 | v->err_code); | |
3977 | ASC_PRT_NEXT(); | |
1da177e4 | 3978 | |
51219358 MW |
3979 | len = asc_prt_line(cp, leftlen, |
3980 | " chip_version %u, lib_version 0x%x, mcode_date 0x%x, mcode_version 0x%x\n", | |
3981 | c->chip_version, c->lib_version, c->mcode_date, | |
3982 | c->mcode_version); | |
3983 | ASC_PRT_NEXT(); | |
3984 | ||
3985 | AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able); | |
3986 | len = asc_prt_line(cp, leftlen, " Queuing Enabled:"); | |
27c868c2 MW |
3987 | ASC_PRT_NEXT(); |
3988 | for (i = 0; i <= ADV_MAX_TID; i++) { | |
51219358 MW |
3989 | if ((chip_scsi_id == i) || |
3990 | ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { | |
3991 | continue; | |
27c868c2 | 3992 | } |
51219358 MW |
3993 | |
3994 | len = asc_prt_line(cp, leftlen, " %X:%c", | |
3995 | i, | |
3996 | (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : | |
3997 | 'N'); | |
3998 | ASC_PRT_NEXT(); | |
27c868c2 | 3999 | } |
51219358 | 4000 | len = asc_prt_line(cp, leftlen, "\n"); |
27c868c2 | 4001 | ASC_PRT_NEXT(); |
1da177e4 | 4002 | |
51219358 MW |
4003 | len = asc_prt_line(cp, leftlen, " Queue Limit:"); |
4004 | ASC_PRT_NEXT(); | |
4005 | for (i = 0; i <= ADV_MAX_TID; i++) { | |
4006 | if ((chip_scsi_id == i) || | |
4007 | ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { | |
4008 | continue; | |
4009 | } | |
1da177e4 | 4010 | |
51219358 MW |
4011 | AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i, |
4012 | lrambyte); | |
27c868c2 | 4013 | |
51219358 MW |
4014 | len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte); |
4015 | ASC_PRT_NEXT(); | |
4016 | } | |
4017 | len = asc_prt_line(cp, leftlen, "\n"); | |
4018 | ASC_PRT_NEXT(); | |
27c868c2 | 4019 | |
51219358 | 4020 | len = asc_prt_line(cp, leftlen, " Command Pending:"); |
27c868c2 | 4021 | ASC_PRT_NEXT(); |
51219358 MW |
4022 | for (i = 0; i <= ADV_MAX_TID; i++) { |
4023 | if ((chip_scsi_id == i) || | |
4024 | ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { | |
4025 | continue; | |
4026 | } | |
27c868c2 | 4027 | |
51219358 MW |
4028 | AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i, |
4029 | lrambyte); | |
1da177e4 | 4030 | |
51219358 | 4031 | len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte); |
27c868c2 | 4032 | ASC_PRT_NEXT(); |
51219358 MW |
4033 | } |
4034 | len = asc_prt_line(cp, leftlen, "\n"); | |
4035 | ASC_PRT_NEXT(); | |
1da177e4 | 4036 | |
51219358 MW |
4037 | AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); |
4038 | len = asc_prt_line(cp, leftlen, " Wide Enabled:"); | |
4039 | ASC_PRT_NEXT(); | |
4040 | for (i = 0; i <= ADV_MAX_TID; i++) { | |
4041 | if ((chip_scsi_id == i) || | |
4042 | ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { | |
4043 | continue; | |
27c868c2 | 4044 | } |
51219358 MW |
4045 | |
4046 | len = asc_prt_line(cp, leftlen, " %X:%c", | |
4047 | i, | |
4048 | (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : | |
4049 | 'N'); | |
4050 | ASC_PRT_NEXT(); | |
27c868c2 | 4051 | } |
51219358 MW |
4052 | len = asc_prt_line(cp, leftlen, "\n"); |
4053 | ASC_PRT_NEXT(); | |
1da177e4 | 4054 | |
51219358 MW |
4055 | AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done); |
4056 | len = asc_prt_line(cp, leftlen, " Transfer Bit Width:"); | |
4057 | ASC_PRT_NEXT(); | |
4058 | for (i = 0; i <= ADV_MAX_TID; i++) { | |
4059 | if ((chip_scsi_id == i) || | |
4060 | ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { | |
4061 | continue; | |
4062 | } | |
1da177e4 | 4063 | |
51219358 MW |
4064 | AdvReadWordLram(iop_base, |
4065 | ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i), | |
4066 | lramword); | |
27c868c2 | 4067 | |
51219358 MW |
4068 | len = asc_prt_line(cp, leftlen, " %X:%d", |
4069 | i, (lramword & 0x8000) ? 16 : 8); | |
4070 | ASC_PRT_NEXT(); | |
27c868c2 | 4071 | |
51219358 MW |
4072 | if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) && |
4073 | (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) { | |
4074 | len = asc_prt_line(cp, leftlen, "*"); | |
4075 | ASC_PRT_NEXT(); | |
4076 | renegotiate = 1; | |
27c868c2 | 4077 | } |
51219358 MW |
4078 | } |
4079 | len = asc_prt_line(cp, leftlen, "\n"); | |
4080 | ASC_PRT_NEXT(); | |
27c868c2 | 4081 | |
51219358 MW |
4082 | AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); |
4083 | len = asc_prt_line(cp, leftlen, " Synchronous Enabled:"); | |
4084 | ASC_PRT_NEXT(); | |
4085 | for (i = 0; i <= ADV_MAX_TID; i++) { | |
4086 | if ((chip_scsi_id == i) || | |
4087 | ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { | |
4088 | continue; | |
4089 | } | |
27c868c2 | 4090 | |
51219358 MW |
4091 | len = asc_prt_line(cp, leftlen, " %X:%c", |
4092 | i, | |
4093 | (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : | |
4094 | 'N'); | |
4095 | ASC_PRT_NEXT(); | |
4096 | } | |
4097 | len = asc_prt_line(cp, leftlen, "\n"); | |
4098 | ASC_PRT_NEXT(); | |
27c868c2 | 4099 | |
51219358 MW |
4100 | AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done); |
4101 | for (i = 0; i <= ADV_MAX_TID; i++) { | |
27c868c2 | 4102 | |
51219358 MW |
4103 | AdvReadWordLram(iop_base, |
4104 | ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i), | |
4105 | lramword); | |
4106 | lramword &= ~0x8000; | |
27c868c2 | 4107 | |
51219358 MW |
4108 | if ((chip_scsi_id == i) || |
4109 | ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) || | |
4110 | ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) { | |
4111 | continue; | |
27c868c2 MW |
4112 | } |
4113 | ||
51219358 MW |
4114 | len = asc_prt_line(cp, leftlen, " %X:", i); |
4115 | ASC_PRT_NEXT(); | |
27c868c2 | 4116 | |
51219358 MW |
4117 | if ((lramword & 0x1F) == 0) { /* Check for REQ/ACK Offset 0. */ |
4118 | len = asc_prt_line(cp, leftlen, " Asynchronous"); | |
4119 | ASC_PRT_NEXT(); | |
4120 | } else { | |
4121 | len = | |
4122 | asc_prt_line(cp, leftlen, | |
4123 | " Transfer Period Factor: "); | |
4124 | ASC_PRT_NEXT(); | |
27c868c2 | 4125 | |
51219358 MW |
4126 | if ((lramword & 0x1F00) == 0x1100) { /* 80 Mhz */ |
4127 | len = | |
4128 | asc_prt_line(cp, leftlen, "9 (80.0 Mhz),"); | |
4129 | ASC_PRT_NEXT(); | |
4130 | } else if ((lramword & 0x1F00) == 0x1000) { /* 40 Mhz */ | |
4131 | len = | |
4132 | asc_prt_line(cp, leftlen, "10 (40.0 Mhz),"); | |
4133 | ASC_PRT_NEXT(); | |
4134 | } else { /* 20 Mhz or below. */ | |
27c868c2 | 4135 | |
51219358 MW |
4136 | period = (((lramword >> 8) * 25) + 50) / 4; |
4137 | ||
4138 | if (period == 0) { /* Should never happen. */ | |
4139 | len = | |
4140 | asc_prt_line(cp, leftlen, | |
4141 | "%d (? Mhz), "); | |
4142 | ASC_PRT_NEXT(); | |
4143 | } else { | |
4144 | len = asc_prt_line(cp, leftlen, | |
4145 | "%d (%d.%d Mhz),", | |
4146 | period, 250 / period, | |
4147 | ASC_TENTHS(250, | |
4148 | period)); | |
4149 | ASC_PRT_NEXT(); | |
4150 | } | |
4151 | } | |
4152 | ||
4153 | len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d", | |
4154 | lramword & 0x1F); | |
4155 | ASC_PRT_NEXT(); | |
4156 | } | |
4157 | ||
4158 | if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) { | |
4159 | len = asc_prt_line(cp, leftlen, "*\n"); | |
4160 | renegotiate = 1; | |
4161 | } else { | |
4162 | len = asc_prt_line(cp, leftlen, "\n"); | |
4163 | } | |
4164 | ASC_PRT_NEXT(); | |
27c868c2 | 4165 | } |
51219358 MW |
4166 | |
4167 | if (renegotiate) { | |
4168 | len = asc_prt_line(cp, leftlen, | |
4169 | " * = Re-negotiation pending before next command.\n"); | |
4170 | ASC_PRT_NEXT(); | |
4171 | } | |
4172 | ||
4173 | return totlen; | |
1da177e4 LT |
4174 | } |
4175 | ||
4176 | /* | |
51219358 | 4177 | * asc_proc_copy() |
1da177e4 | 4178 | * |
51219358 MW |
4179 | * Copy proc information to a read buffer taking into account the current |
4180 | * read offset in the file and the remaining space in the read buffer. | |
4181 | */ | |
4182 | static int | |
4183 | asc_proc_copy(off_t advoffset, off_t offset, char *curbuf, int leftlen, | |
4184 | char *cp, int cplen) | |
4185 | { | |
4186 | int cnt = 0; | |
4187 | ||
4188 | ASC_DBG3(2, "asc_proc_copy: offset %d, advoffset %d, cplen %d\n", | |
4189 | (unsigned)offset, (unsigned)advoffset, cplen); | |
4190 | if (offset <= advoffset) { | |
4191 | /* Read offset below current offset, copy everything. */ | |
4192 | cnt = min(cplen, leftlen); | |
4193 | ASC_DBG3(2, "asc_proc_copy: curbuf 0x%lx, cp 0x%lx, cnt %d\n", | |
4194 | (ulong)curbuf, (ulong)cp, cnt); | |
4195 | memcpy(curbuf, cp, cnt); | |
4196 | } else if (offset < advoffset + cplen) { | |
4197 | /* Read offset within current range, partial copy. */ | |
4198 | cnt = (advoffset + cplen) - offset; | |
4199 | cp = (cp + cplen) - cnt; | |
4200 | cnt = min(cnt, leftlen); | |
4201 | ASC_DBG3(2, "asc_proc_copy: curbuf 0x%lx, cp 0x%lx, cnt %d\n", | |
4202 | (ulong)curbuf, (ulong)cp, cnt); | |
4203 | memcpy(curbuf, cp, cnt); | |
4204 | } | |
4205 | return cnt; | |
4206 | } | |
4207 | ||
4208 | #ifdef ADVANSYS_STATS | |
4209 | /* | |
4210 | * asc_prt_board_stats() | |
1da177e4 LT |
4211 | * |
4212 | * Note: no single line should be greater than ASC_PRTLINE_SIZE, | |
4213 | * cf. asc_prt_line(). | |
4214 | * | |
4215 | * Return the number of characters copied into 'cp'. No more than | |
4216 | * 'cplen' characters will be copied to 'cp'. | |
4217 | */ | |
51219358 | 4218 | static int asc_prt_board_stats(struct Scsi_Host *shost, char *cp, int cplen) |
1da177e4 | 4219 | { |
27c868c2 MW |
4220 | int leftlen; |
4221 | int totlen; | |
4222 | int len; | |
51219358 MW |
4223 | struct asc_stats *s; |
4224 | asc_board_t *boardp; | |
27c868c2 MW |
4225 | |
4226 | leftlen = cplen; | |
4227 | totlen = len = 0; | |
4228 | ||
51219358 MW |
4229 | boardp = ASC_BOARDP(shost); |
4230 | s = &boardp->asc_stats; | |
4231 | ||
27c868c2 | 4232 | len = asc_prt_line(cp, leftlen, |
51219358 | 4233 | "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n", |
27c868c2 MW |
4234 | shost->host_no); |
4235 | ASC_PRT_NEXT(); | |
4236 | ||
27c868c2 | 4237 | len = asc_prt_line(cp, leftlen, |
51219358 MW |
4238 | " queuecommand %lu, reset %lu, biosparam %lu, interrupt %lu\n", |
4239 | s->queuecommand, s->reset, s->biosparam, | |
4240 | s->interrupt); | |
27c868c2 MW |
4241 | ASC_PRT_NEXT(); |
4242 | ||
4243 | len = asc_prt_line(cp, leftlen, | |
51219358 MW |
4244 | " callback %lu, done %lu, build_error %lu, build_noreq %lu, build_nosg %lu\n", |
4245 | s->callback, s->done, s->build_error, | |
4246 | s->adv_build_noreq, s->adv_build_nosg); | |
27c868c2 MW |
4247 | ASC_PRT_NEXT(); |
4248 | ||
51219358 MW |
4249 | len = asc_prt_line(cp, leftlen, |
4250 | " exe_noerror %lu, exe_busy %lu, exe_error %lu, exe_unknown %lu\n", | |
4251 | s->exe_noerror, s->exe_busy, s->exe_error, | |
4252 | s->exe_unknown); | |
27c868c2 | 4253 | ASC_PRT_NEXT(); |
51219358 MW |
4254 | |
4255 | /* | |
4256 | * Display data transfer statistics. | |
4257 | */ | |
4258 | if (s->cont_cnt > 0) { | |
4259 | len = asc_prt_line(cp, leftlen, " cont_cnt %lu, ", s->cont_cnt); | |
27c868c2 | 4260 | ASC_PRT_NEXT(); |
27c868c2 | 4261 | |
51219358 MW |
4262 | len = asc_prt_line(cp, leftlen, "cont_xfer %lu.%01lu kb ", |
4263 | s->cont_xfer / 2, | |
4264 | ASC_TENTHS(s->cont_xfer, 2)); | |
27c868c2 | 4265 | ASC_PRT_NEXT(); |
27c868c2 | 4266 | |
51219358 MW |
4267 | /* Contiguous transfer average size */ |
4268 | len = asc_prt_line(cp, leftlen, "avg_xfer %lu.%01lu kb\n", | |
4269 | (s->cont_xfer / 2) / s->cont_cnt, | |
4270 | ASC_TENTHS((s->cont_xfer / 2), s->cont_cnt)); | |
27c868c2 MW |
4271 | ASC_PRT_NEXT(); |
4272 | } | |
27c868c2 | 4273 | |
51219358 MW |
4274 | if (s->sg_cnt > 0) { |
4275 | ||
4276 | len = asc_prt_line(cp, leftlen, " sg_cnt %lu, sg_elem %lu, ", | |
4277 | s->sg_cnt, s->sg_elem); | |
27c868c2 | 4278 | ASC_PRT_NEXT(); |
27c868c2 | 4279 | |
51219358 MW |
4280 | len = asc_prt_line(cp, leftlen, "sg_xfer %lu.%01lu kb\n", |
4281 | s->sg_xfer / 2, ASC_TENTHS(s->sg_xfer, 2)); | |
27c868c2 | 4282 | ASC_PRT_NEXT(); |
1da177e4 | 4283 | |
51219358 MW |
4284 | /* Scatter gather transfer statistics */ |
4285 | len = asc_prt_line(cp, leftlen, " avg_num_elem %lu.%01lu, ", | |
4286 | s->sg_elem / s->sg_cnt, | |
4287 | ASC_TENTHS(s->sg_elem, s->sg_cnt)); | |
4288 | ASC_PRT_NEXT(); | |
4289 | ||
4290 | len = asc_prt_line(cp, leftlen, "avg_elem_size %lu.%01lu kb, ", | |
4291 | (s->sg_xfer / 2) / s->sg_elem, | |
4292 | ASC_TENTHS((s->sg_xfer / 2), s->sg_elem)); | |
4293 | ASC_PRT_NEXT(); | |
4294 | ||
4295 | len = asc_prt_line(cp, leftlen, "avg_xfer_size %lu.%01lu kb\n", | |
4296 | (s->sg_xfer / 2) / s->sg_cnt, | |
4297 | ASC_TENTHS((s->sg_xfer / 2), s->sg_cnt)); | |
27c868c2 MW |
4298 | ASC_PRT_NEXT(); |
4299 | } | |
51219358 MW |
4300 | |
4301 | /* | |
4302 | * Display request queuing statistics. | |
4303 | */ | |
4304 | len = asc_prt_line(cp, leftlen, | |
4305 | " Active and Waiting Request Queues (Time Unit: %d HZ):\n", | |
4306 | HZ); | |
4307 | ASC_PRT_NEXT(); | |
1da177e4 | 4308 | |
27c868c2 | 4309 | return totlen; |
1da177e4 | 4310 | } |
51219358 | 4311 | #endif /* ADVANSYS_STATS */ |
1da177e4 LT |
4312 | |
4313 | /* | |
51219358 | 4314 | * advansys_proc_info() - /proc/scsi/advansys/{0,1,2,3,...} |
1da177e4 | 4315 | * |
51219358 MW |
4316 | * *buffer: I/O buffer |
4317 | * **start: if inout == FALSE pointer into buffer where user read should start | |
4318 | * offset: current offset into a /proc/scsi/advansys/[0...] file | |
4319 | * length: length of buffer | |
4320 | * hostno: Scsi_Host host_no | |
4321 | * inout: TRUE - user is writing; FALSE - user is reading | |
1da177e4 | 4322 | * |
51219358 MW |
4323 | * Return the number of bytes read from or written to a |
4324 | * /proc/scsi/advansys/[0...] file. | |
1da177e4 | 4325 | * |
51219358 MW |
4326 | * Note: This function uses the per board buffer 'prtbuf' which is |
4327 | * allocated when the board is initialized in advansys_detect(). The | |
4328 | * buffer is ASC_PRTBUF_SIZE bytes. The function asc_proc_copy() is | |
4329 | * used to write to the buffer. The way asc_proc_copy() is written | |
4330 | * if 'prtbuf' is too small it will not be overwritten. Instead the | |
4331 | * user just won't get all the available statistics. | |
1da177e4 | 4332 | */ |
51219358 MW |
4333 | static int |
4334 | advansys_proc_info(struct Scsi_Host *shost, char *buffer, char **start, | |
4335 | off_t offset, int length, int inout) | |
1da177e4 | 4336 | { |
27c868c2 | 4337 | asc_board_t *boardp; |
51219358 MW |
4338 | char *cp; |
4339 | int cplen; | |
4340 | int cnt; | |
4341 | int totcnt; | |
27c868c2 | 4342 | int leftlen; |
51219358 MW |
4343 | char *curbuf; |
4344 | off_t advoffset; | |
27c868c2 | 4345 | |
51219358 MW |
4346 | ASC_DBG(1, "advansys_proc_info: begin\n"); |
4347 | ||
4348 | /* | |
4349 | * User write not supported. | |
4350 | */ | |
4351 | if (inout == TRUE) { | |
4352 | return (-ENOSYS); | |
27c868c2 | 4353 | } |
1da177e4 | 4354 | |
51219358 MW |
4355 | /* |
4356 | * User read of /proc/scsi/advansys/[0...] file. | |
4357 | */ | |
1da177e4 | 4358 | |
51219358 | 4359 | boardp = ASC_BOARDP(shost); |
1da177e4 | 4360 | |
51219358 MW |
4361 | /* Copy read data starting at the beginning of the buffer. */ |
4362 | *start = buffer; | |
4363 | curbuf = buffer; | |
4364 | advoffset = 0; | |
4365 | totcnt = 0; | |
4366 | leftlen = length; | |
4367 | ||
4368 | /* | |
4369 | * Get board configuration information. | |
4370 | * | |
4371 | * advansys_info() returns the board string from its own static buffer. | |
4372 | */ | |
4373 | cp = (char *)advansys_info(shost); | |
4374 | strcat(cp, "\n"); | |
4375 | cplen = strlen(cp); | |
4376 | /* Copy board information. */ | |
4377 | cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen); | |
4378 | totcnt += cnt; | |
4379 | leftlen -= cnt; | |
4380 | if (leftlen == 0) { | |
4381 | ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt); | |
4382 | return totcnt; | |
27c868c2 | 4383 | } |
51219358 MW |
4384 | advoffset += cplen; |
4385 | curbuf += cnt; | |
1da177e4 | 4386 | |
51219358 MW |
4387 | /* |
4388 | * Display Wide Board BIOS Information. | |
4389 | */ | |
4390 | if (ASC_WIDE_BOARD(boardp)) { | |
4391 | cp = boardp->prtbuf; | |
4392 | cplen = asc_prt_adv_bios(shost, cp, ASC_PRTBUF_SIZE); | |
4393 | BUG_ON(cplen >= ASC_PRTBUF_SIZE); | |
4394 | cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, | |
4395 | cplen); | |
4396 | totcnt += cnt; | |
4397 | leftlen -= cnt; | |
4398 | if (leftlen == 0) { | |
4399 | ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt); | |
4400 | return totcnt; | |
4401 | } | |
4402 | advoffset += cplen; | |
4403 | curbuf += cnt; | |
27c868c2 | 4404 | } |
1da177e4 | 4405 | |
51219358 MW |
4406 | /* |
4407 | * Display driver information for each device attached to the board. | |
4408 | */ | |
4409 | cp = boardp->prtbuf; | |
4410 | cplen = asc_prt_board_devices(shost, cp, ASC_PRTBUF_SIZE); | |
4411 | BUG_ON(cplen >= ASC_PRTBUF_SIZE); | |
4412 | cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen); | |
4413 | totcnt += cnt; | |
4414 | leftlen -= cnt; | |
4415 | if (leftlen == 0) { | |
4416 | ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt); | |
4417 | return totcnt; | |
27c868c2 | 4418 | } |
51219358 MW |
4419 | advoffset += cplen; |
4420 | curbuf += cnt; | |
4421 | ||
4422 | /* | |
4423 | * Display EEPROM configuration for the board. | |
4424 | */ | |
4425 | cp = boardp->prtbuf; | |
4426 | if (ASC_NARROW_BOARD(boardp)) { | |
4427 | cplen = asc_prt_asc_board_eeprom(shost, cp, ASC_PRTBUF_SIZE); | |
27c868c2 | 4428 | } else { |
51219358 | 4429 | cplen = asc_prt_adv_board_eeprom(shost, cp, ASC_PRTBUF_SIZE); |
27c868c2 | 4430 | } |
51219358 MW |
4431 | BUG_ON(cplen >= ASC_PRTBUF_SIZE); |
4432 | cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen); | |
4433 | totcnt += cnt; | |
4434 | leftlen -= cnt; | |
4435 | if (leftlen == 0) { | |
4436 | ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt); | |
4437 | return totcnt; | |
27c868c2 | 4438 | } |
51219358 MW |
4439 | advoffset += cplen; |
4440 | curbuf += cnt; | |
1da177e4 | 4441 | |
51219358 MW |
4442 | /* |
4443 | * Display driver configuration and information for the board. | |
4444 | */ | |
4445 | cp = boardp->prtbuf; | |
4446 | cplen = asc_prt_driver_conf(shost, cp, ASC_PRTBUF_SIZE); | |
4447 | BUG_ON(cplen >= ASC_PRTBUF_SIZE); | |
4448 | cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen); | |
4449 | totcnt += cnt; | |
4450 | leftlen -= cnt; | |
4451 | if (leftlen == 0) { | |
4452 | ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt); | |
4453 | return totcnt; | |
27c868c2 | 4454 | } |
51219358 MW |
4455 | advoffset += cplen; |
4456 | curbuf += cnt; | |
1da177e4 | 4457 | |
51219358 MW |
4458 | #ifdef ADVANSYS_STATS |
4459 | /* | |
4460 | * Display driver statistics for the board. | |
4461 | */ | |
4462 | cp = boardp->prtbuf; | |
4463 | cplen = asc_prt_board_stats(shost, cp, ASC_PRTBUF_SIZE); | |
4464 | BUG_ON(cplen >= ASC_PRTBUF_SIZE); | |
4465 | cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen); | |
4466 | totcnt += cnt; | |
4467 | leftlen -= cnt; | |
4468 | if (leftlen == 0) { | |
4469 | ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt); | |
4470 | return totcnt; | |
27c868c2 | 4471 | } |
51219358 MW |
4472 | advoffset += cplen; |
4473 | curbuf += cnt; | |
4474 | #endif /* ADVANSYS_STATS */ | |
1da177e4 | 4475 | |
51219358 MW |
4476 | /* |
4477 | * Display Asc Library dynamic configuration information | |
4478 | * for the board. | |
4479 | */ | |
4480 | cp = boardp->prtbuf; | |
4481 | if (ASC_NARROW_BOARD(boardp)) { | |
4482 | cplen = asc_prt_asc_board_info(shost, cp, ASC_PRTBUF_SIZE); | |
27c868c2 | 4483 | } else { |
51219358 | 4484 | cplen = asc_prt_adv_board_info(shost, cp, ASC_PRTBUF_SIZE); |
27c868c2 | 4485 | } |
51219358 MW |
4486 | BUG_ON(cplen >= ASC_PRTBUF_SIZE); |
4487 | cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen); | |
4488 | totcnt += cnt; | |
4489 | leftlen -= cnt; | |
4490 | if (leftlen == 0) { | |
4491 | ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt); | |
4492 | return totcnt; | |
27c868c2 | 4493 | } |
51219358 MW |
4494 | advoffset += cplen; |
4495 | curbuf += cnt; | |
1da177e4 | 4496 | |
51219358 | 4497 | ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt); |
27c868c2 | 4498 | |
51219358 MW |
4499 | return totcnt; |
4500 | } | |
4501 | #endif /* CONFIG_PROC_FS */ | |
4502 | ||
4503 | static void asc_scsi_done(struct scsi_cmnd *scp) | |
4504 | { | |
4505 | struct asc_board *boardp = ASC_BOARDP(scp->device->host); | |
4506 | ||
4507 | if (scp->use_sg) | |
4508 | dma_unmap_sg(boardp->dev, | |
4509 | (struct scatterlist *)scp->request_buffer, | |
4510 | scp->use_sg, scp->sc_data_direction); | |
4511 | else if (scp->request_bufflen) | |
4512 | dma_unmap_single(boardp->dev, scp->SCp.dma_handle, | |
4513 | scp->request_bufflen, scp->sc_data_direction); | |
4514 | ||
4515 | ASC_STATS(scp->device->host, done); | |
4516 | ||
4517 | scp->scsi_done(scp); | |
4518 | } | |
4519 | ||
4520 | static void AscSetBank(PortAddr iop_base, uchar bank) | |
4521 | { | |
4522 | uchar val; | |
4523 | ||
4524 | val = AscGetChipControl(iop_base) & | |
4525 | (~ | |
4526 | (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET | | |
4527 | CC_CHIP_RESET)); | |
4528 | if (bank == 1) { | |
4529 | val |= CC_BANK_ONE; | |
4530 | } else if (bank == 2) { | |
4531 | val |= CC_DIAG | CC_BANK_ONE; | |
27c868c2 | 4532 | } else { |
51219358 | 4533 | val &= ~CC_BANK_ONE; |
27c868c2 | 4534 | } |
51219358 MW |
4535 | AscSetChipControl(iop_base, val); |
4536 | return; | |
4537 | } | |
4538 | ||
4539 | static void AscSetChipIH(PortAddr iop_base, ushort ins_code) | |
4540 | { | |
4541 | AscSetBank(iop_base, 1); | |
4542 | AscWriteChipIH(iop_base, ins_code); | |
4543 | AscSetBank(iop_base, 0); | |
4544 | return; | |
4545 | } | |
4546 | ||
4547 | static int AscStartChip(PortAddr iop_base) | |
4548 | { | |
4549 | AscSetChipControl(iop_base, 0); | |
4550 | if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) { | |
4551 | return (0); | |
27c868c2 | 4552 | } |
51219358 MW |
4553 | return (1); |
4554 | } | |
27c868c2 | 4555 | |
51219358 MW |
4556 | static int AscStopChip(PortAddr iop_base) |
4557 | { | |
4558 | uchar cc_val; | |
4559 | ||
4560 | cc_val = | |
4561 | AscGetChipControl(iop_base) & | |
4562 | (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG)); | |
4563 | AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT)); | |
4564 | AscSetChipIH(iop_base, INS_HALT); | |
4565 | AscSetChipIH(iop_base, INS_RFLAG_WTM); | |
4566 | if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) { | |
4567 | return (0); | |
27c868c2 | 4568 | } |
51219358 MW |
4569 | return (1); |
4570 | } | |
27c868c2 | 4571 | |
51219358 MW |
4572 | static int AscIsChipHalted(PortAddr iop_base) |
4573 | { | |
4574 | if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) { | |
4575 | if ((AscGetChipControl(iop_base) & CC_HALT) != 0) { | |
4576 | return (1); | |
27c868c2 | 4577 | } |
27c868c2 | 4578 | } |
51219358 MW |
4579 | return (0); |
4580 | } | |
27c868c2 | 4581 | |
51219358 MW |
4582 | static int AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc) |
4583 | { | |
4584 | PortAddr iop_base; | |
4585 | int i = 10; | |
4586 | ||
4587 | iop_base = asc_dvc->iop_base; | |
4588 | while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE) | |
4589 | && (i-- > 0)) { | |
4590 | mdelay(100); | |
27c868c2 | 4591 | } |
51219358 MW |
4592 | AscStopChip(iop_base); |
4593 | AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT); | |
4594 | udelay(60); | |
4595 | AscSetChipIH(iop_base, INS_RFLAG_WTM); | |
4596 | AscSetChipIH(iop_base, INS_HALT); | |
4597 | AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT); | |
4598 | AscSetChipControl(iop_base, CC_HALT); | |
4599 | mdelay(200); | |
4600 | AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT); | |
4601 | AscSetChipStatus(iop_base, 0); | |
4602 | return (AscIsChipHalted(iop_base)); | |
4603 | } | |
27c868c2 | 4604 | |
51219358 MW |
4605 | static int AscFindSignature(PortAddr iop_base) |
4606 | { | |
4607 | ushort sig_word; | |
27c868c2 | 4608 | |
51219358 MW |
4609 | ASC_DBG2(1, "AscFindSignature: AscGetChipSignatureByte(0x%x) 0x%x\n", |
4610 | iop_base, AscGetChipSignatureByte(iop_base)); | |
4611 | if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) { | |
4612 | ASC_DBG2(1, | |
4613 | "AscFindSignature: AscGetChipSignatureWord(0x%x) 0x%x\n", | |
4614 | iop_base, AscGetChipSignatureWord(iop_base)); | |
4615 | sig_word = AscGetChipSignatureWord(iop_base); | |
4616 | if ((sig_word == (ushort)ASC_1000_ID0W) || | |
4617 | (sig_word == (ushort)ASC_1000_ID0W_FIX)) { | |
4618 | return (1); | |
27c868c2 | 4619 | } |
27c868c2 | 4620 | } |
51219358 | 4621 | return (0); |
27c868c2 MW |
4622 | } |
4623 | ||
51219358 | 4624 | static void AscEnableInterrupt(PortAddr iop_base) |
1da177e4 | 4625 | { |
51219358 | 4626 | ushort cfg; |
27c868c2 | 4627 | |
51219358 MW |
4628 | cfg = AscGetChipCfgLsw(iop_base); |
4629 | AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON); | |
4630 | return; | |
4631 | } | |
27c868c2 | 4632 | |
51219358 MW |
4633 | static void AscDisableInterrupt(PortAddr iop_base) |
4634 | { | |
4635 | ushort cfg; | |
27c868c2 | 4636 | |
51219358 MW |
4637 | cfg = AscGetChipCfgLsw(iop_base); |
4638 | AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON)); | |
4639 | return; | |
4640 | } | |
27c868c2 | 4641 | |
51219358 MW |
4642 | static uchar AscReadLramByte(PortAddr iop_base, ushort addr) |
4643 | { | |
4644 | unsigned char byte_data; | |
4645 | unsigned short word_data; | |
27c868c2 | 4646 | |
51219358 MW |
4647 | if (isodd_word(addr)) { |
4648 | AscSetChipLramAddr(iop_base, addr - 1); | |
4649 | word_data = AscGetChipLramData(iop_base); | |
4650 | byte_data = (word_data >> 8) & 0xFF; | |
4651 | } else { | |
4652 | AscSetChipLramAddr(iop_base, addr); | |
4653 | word_data = AscGetChipLramData(iop_base); | |
4654 | byte_data = word_data & 0xFF; | |
4655 | } | |
4656 | return byte_data; | |
4657 | } | |
27c868c2 | 4658 | |
51219358 MW |
4659 | static ushort AscReadLramWord(PortAddr iop_base, ushort addr) |
4660 | { | |
4661 | ushort word_data; | |
27c868c2 | 4662 | |
51219358 MW |
4663 | AscSetChipLramAddr(iop_base, addr); |
4664 | word_data = AscGetChipLramData(iop_base); | |
4665 | return (word_data); | |
4666 | } | |
27c868c2 | 4667 | |
51219358 MW |
4668 | #if CC_VERY_LONG_SG_LIST |
4669 | static ASC_DCNT AscReadLramDWord(PortAddr iop_base, ushort addr) | |
4670 | { | |
4671 | ushort val_low, val_high; | |
4672 | ASC_DCNT dword_data; | |
27c868c2 | 4673 | |
51219358 MW |
4674 | AscSetChipLramAddr(iop_base, addr); |
4675 | val_low = AscGetChipLramData(iop_base); | |
4676 | val_high = AscGetChipLramData(iop_base); | |
4677 | dword_data = ((ASC_DCNT) val_high << 16) | (ASC_DCNT) val_low; | |
4678 | return (dword_data); | |
4679 | } | |
4680 | #endif /* CC_VERY_LONG_SG_LIST */ | |
4681 | ||
4682 | static void | |
4683 | AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words) | |
4684 | { | |
4685 | int i; | |
4686 | ||
4687 | AscSetChipLramAddr(iop_base, s_addr); | |
4688 | for (i = 0; i < words; i++) { | |
4689 | AscSetChipLramData(iop_base, set_wval); | |
27c868c2 | 4690 | } |
51219358 | 4691 | } |
1da177e4 | 4692 | |
51219358 MW |
4693 | static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val) |
4694 | { | |
4695 | AscSetChipLramAddr(iop_base, addr); | |
4696 | AscSetChipLramData(iop_base, word_val); | |
4697 | return; | |
4698 | } | |
4699 | ||
4700 | static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val) | |
4701 | { | |
4702 | ushort word_data; | |
4703 | ||
4704 | if (isodd_word(addr)) { | |
4705 | addr--; | |
4706 | word_data = AscReadLramWord(iop_base, addr); | |
4707 | word_data &= 0x00FF; | |
4708 | word_data |= (((ushort)byte_val << 8) & 0xFF00); | |
4709 | } else { | |
4710 | word_data = AscReadLramWord(iop_base, addr); | |
4711 | word_data &= 0xFF00; | |
4712 | word_data |= ((ushort)byte_val & 0x00FF); | |
4713 | } | |
4714 | AscWriteLramWord(iop_base, addr, word_data); | |
4715 | return; | |
1da177e4 LT |
4716 | } |
4717 | ||
4718 | /* | |
51219358 | 4719 | * Copy 2 bytes to LRAM. |
1da177e4 | 4720 | * |
51219358 MW |
4721 | * The source data is assumed to be in little-endian order in memory |
4722 | * and is maintained in little-endian order when written to LRAM. | |
1da177e4 | 4723 | */ |
51219358 MW |
4724 | static void |
4725 | AscMemWordCopyPtrToLram(PortAddr iop_base, | |
4726 | ushort s_addr, uchar *s_buffer, int words) | |
1da177e4 | 4727 | { |
27c868c2 | 4728 | int i; |
27c868c2 | 4729 | |
51219358 MW |
4730 | AscSetChipLramAddr(iop_base, s_addr); |
4731 | for (i = 0; i < 2 * words; i += 2) { | |
4732 | /* | |
4733 | * On a little-endian system the second argument below | |
4734 | * produces a little-endian ushort which is written to | |
4735 | * LRAM in little-endian order. On a big-endian system | |
4736 | * the second argument produces a big-endian ushort which | |
4737 | * is "transparently" byte-swapped by outpw() and written | |
4738 | * in little-endian order to LRAM. | |
4739 | */ | |
4740 | outpw(iop_base + IOP_RAM_DATA, | |
4741 | ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); | |
4742 | } | |
4743 | return; | |
4744 | } | |
27c868c2 | 4745 | |
51219358 MW |
4746 | /* |
4747 | * Copy 4 bytes to LRAM. | |
4748 | * | |
4749 | * The source data is assumed to be in little-endian order in memory | |
4750 | * and is maintained in little-endian order when writen to LRAM. | |
4751 | */ | |
4752 | static void | |
4753 | AscMemDWordCopyPtrToLram(PortAddr iop_base, | |
4754 | ushort s_addr, uchar *s_buffer, int dwords) | |
4755 | { | |
4756 | int i; | |
27c868c2 | 4757 | |
51219358 MW |
4758 | AscSetChipLramAddr(iop_base, s_addr); |
4759 | for (i = 0; i < 4 * dwords; i += 4) { | |
4760 | outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */ | |
4761 | outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */ | |
4762 | } | |
4763 | return; | |
4764 | } | |
27c868c2 | 4765 | |
51219358 MW |
4766 | /* |
4767 | * Copy 2 bytes from LRAM. | |
4768 | * | |
4769 | * The source data is assumed to be in little-endian order in LRAM | |
4770 | * and is maintained in little-endian order when written to memory. | |
4771 | */ | |
4772 | static void | |
4773 | AscMemWordCopyPtrFromLram(PortAddr iop_base, | |
4774 | ushort s_addr, uchar *d_buffer, int words) | |
4775 | { | |
4776 | int i; | |
4777 | ushort word; | |
27c868c2 | 4778 | |
51219358 MW |
4779 | AscSetChipLramAddr(iop_base, s_addr); |
4780 | for (i = 0; i < 2 * words; i += 2) { | |
4781 | word = inpw(iop_base + IOP_RAM_DATA); | |
4782 | d_buffer[i] = word & 0xff; | |
4783 | d_buffer[i + 1] = (word >> 8) & 0xff; | |
27c868c2 | 4784 | } |
51219358 MW |
4785 | return; |
4786 | } | |
27c868c2 | 4787 | |
51219358 MW |
4788 | static ASC_DCNT AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words) |
4789 | { | |
4790 | ASC_DCNT sum; | |
4791 | int i; | |
27c868c2 | 4792 | |
51219358 MW |
4793 | sum = 0L; |
4794 | for (i = 0; i < words; i++, s_addr += 2) { | |
4795 | sum += AscReadLramWord(iop_base, s_addr); | |
27c868c2 | 4796 | } |
51219358 MW |
4797 | return (sum); |
4798 | } | |
27c868c2 | 4799 | |
51219358 MW |
4800 | static ushort AscInitLram(ASC_DVC_VAR *asc_dvc) |
4801 | { | |
4802 | uchar i; | |
4803 | ushort s_addr; | |
4804 | PortAddr iop_base; | |
4805 | ushort warn_code; | |
27c868c2 | 4806 | |
51219358 MW |
4807 | iop_base = asc_dvc->iop_base; |
4808 | warn_code = 0; | |
4809 | AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0, | |
4810 | (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) * | |
4811 | 64) >> 1)); | |
4812 | i = ASC_MIN_ACTIVE_QNO; | |
4813 | s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE; | |
4814 | AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD), | |
4815 | (uchar)(i + 1)); | |
4816 | AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD), | |
4817 | (uchar)(asc_dvc->max_total_qng)); | |
4818 | AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO), | |
4819 | (uchar)i); | |
4820 | i++; | |
4821 | s_addr += ASC_QBLK_SIZE; | |
4822 | for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) { | |
4823 | AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD), | |
4824 | (uchar)(i + 1)); | |
4825 | AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD), | |
4826 | (uchar)(i - 1)); | |
4827 | AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO), | |
4828 | (uchar)i); | |
27c868c2 | 4829 | } |
51219358 MW |
4830 | AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD), |
4831 | (uchar)ASC_QLINK_END); | |
4832 | AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD), | |
4833 | (uchar)(asc_dvc->max_total_qng - 1)); | |
4834 | AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO), | |
4835 | (uchar)asc_dvc->max_total_qng); | |
4836 | i++; | |
4837 | s_addr += ASC_QBLK_SIZE; | |
4838 | for (; i <= (uchar)(asc_dvc->max_total_qng + 3); | |
4839 | i++, s_addr += ASC_QBLK_SIZE) { | |
4840 | AscWriteLramByte(iop_base, | |
4841 | (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i); | |
4842 | AscWriteLramByte(iop_base, | |
4843 | (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i); | |
4844 | AscWriteLramByte(iop_base, | |
4845 | (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i); | |
27c868c2 | 4846 | } |
51219358 | 4847 | return warn_code; |
1da177e4 LT |
4848 | } |
4849 | ||
51219358 MW |
4850 | static ASC_DCNT |
4851 | AscLoadMicroCode(PortAddr iop_base, | |
4852 | ushort s_addr, uchar *mcode_buf, ushort mcode_size) | |
1da177e4 | 4853 | { |
51219358 MW |
4854 | ASC_DCNT chksum; |
4855 | ushort mcode_word_size; | |
4856 | ushort mcode_chksum; | |
27c868c2 | 4857 | |
51219358 MW |
4858 | /* Write the microcode buffer starting at LRAM address 0. */ |
4859 | mcode_word_size = (ushort)(mcode_size >> 1); | |
4860 | AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size); | |
4861 | AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size); | |
27c868c2 | 4862 | |
51219358 MW |
4863 | chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size); |
4864 | ASC_DBG1(1, "AscLoadMicroCode: chksum 0x%lx\n", (ulong)chksum); | |
4865 | mcode_chksum = (ushort)AscMemSumLramWord(iop_base, | |
4866 | (ushort)ASC_CODE_SEC_BEG, | |
4867 | (ushort)((mcode_size - | |
4868 | s_addr - (ushort) | |
4869 | ASC_CODE_SEC_BEG) / | |
4870 | 2)); | |
4871 | ASC_DBG1(1, "AscLoadMicroCode: mcode_chksum 0x%lx\n", | |
4872 | (ulong)mcode_chksum); | |
4873 | AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum); | |
4874 | AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size); | |
4875 | return (chksum); | |
4876 | } | |
27c868c2 | 4877 | |
51219358 MW |
4878 | /* Microcode buffer is kept after initialization for error recovery. */ |
4879 | static uchar _asc_mcode_buf[] = { | |
4880 | 0x01, 0x03, 0x01, 0x19, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
4881 | 0x00, 0x00, 0x00, 0x00, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, | |
4882 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
4883 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
4884 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
4885 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC3, 0x12, 0x0D, 0x05, | |
4886 | 0x01, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
4887 | 0xFF, 0x80, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
4888 | 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0xFF, | |
4889 | 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, | |
4890 | 0x00, 0x00, 0xE4, 0x88, 0x00, 0x00, 0x00, 0x00, 0x80, 0x73, 0x48, 0x04, | |
4891 | 0x36, 0x00, 0x00, 0xA2, 0xC2, 0x00, 0x80, 0x73, 0x03, 0x23, 0x36, 0x40, | |
4892 | 0xB6, 0x00, 0x36, 0x00, 0x05, 0xD6, 0x0C, 0xD2, 0x12, 0xDA, 0x00, 0xA2, | |
4893 | 0xC2, 0x00, 0x92, 0x80, 0x1E, 0x98, 0x50, 0x00, 0xF5, 0x00, 0x48, 0x98, | |
4894 | 0xDF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80, 0x4F, 0x00, 0xF5, 0x00, | |
4895 | 0x48, 0x98, 0xEF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80, 0x80, 0x62, | |
4896 | 0x92, 0x80, 0x00, 0x46, 0x15, 0xEE, 0x13, 0xEA, 0x02, 0x01, 0x09, 0xD8, | |
4897 | 0xCD, 0x04, 0x4D, 0x00, 0x00, 0xA3, 0xD6, 0x00, 0xA6, 0x97, 0x7F, 0x23, | |
4898 | 0x04, 0x61, 0x84, 0x01, 0xE6, 0x84, 0xD2, 0xC1, 0x80, 0x73, 0xCD, 0x04, | |
4899 | 0x4D, 0x00, 0x00, 0xA3, 0xDA, 0x01, 0xA6, 0x97, 0xC6, 0x81, 0xC2, 0x88, | |
4900 | 0x80, 0x73, 0x80, 0x77, 0x00, 0x01, 0x01, 0xA1, 0xFE, 0x00, 0x4F, 0x00, | |
4901 | 0x84, 0x97, 0x07, 0xA6, 0x08, 0x01, 0x00, 0x33, 0x03, 0x00, 0xC2, 0x88, | |
4902 | 0x03, 0x03, 0x01, 0xDE, 0xC2, 0x88, 0xCE, 0x00, 0x69, 0x60, 0xCE, 0x00, | |
4903 | 0x02, 0x03, 0x4A, 0x60, 0x00, 0xA2, 0x78, 0x01, 0x80, 0x63, 0x07, 0xA6, | |
4904 | 0x24, 0x01, 0x78, 0x81, 0x03, 0x03, 0x80, 0x63, 0xE2, 0x00, 0x07, 0xA6, | |
4905 | 0x34, 0x01, 0x00, 0x33, 0x04, 0x00, 0xC2, 0x88, 0x03, 0x07, 0x02, 0x01, | |
4906 | 0x04, 0xCA, 0x0D, 0x23, 0x68, 0x98, 0x4D, 0x04, 0x04, 0x85, 0x05, 0xD8, | |
4907 | 0x0D, 0x23, 0x68, 0x98, 0xCD, 0x04, 0x15, 0x23, 0xF8, 0x88, 0xFB, 0x23, | |
4908 | 0x02, 0x61, 0x82, 0x01, 0x80, 0x63, 0x02, 0x03, 0x06, 0xA3, 0x62, 0x01, | |
4909 | 0x00, 0x33, 0x0A, 0x00, 0xC2, 0x88, 0x4E, 0x00, 0x07, 0xA3, 0x6E, 0x01, | |
4910 | 0x00, 0x33, 0x0B, 0x00, 0xC2, 0x88, 0xCD, 0x04, 0x36, 0x2D, 0x00, 0x33, | |
4911 | 0x1A, 0x00, 0xC2, 0x88, 0x50, 0x04, 0x88, 0x81, 0x06, 0xAB, 0x82, 0x01, | |
4912 | 0x88, 0x81, 0x4E, 0x00, 0x07, 0xA3, 0x92, 0x01, 0x50, 0x00, 0x00, 0xA3, | |
4913 | 0x3C, 0x01, 0x00, 0x05, 0x7C, 0x81, 0x46, 0x97, 0x02, 0x01, 0x05, 0xC6, | |
4914 | 0x04, 0x23, 0xA0, 0x01, 0x15, 0x23, 0xA1, 0x01, 0xBE, 0x81, 0xFD, 0x23, | |
4915 | 0x02, 0x61, 0x82, 0x01, 0x0A, 0xDA, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA0, | |
4916 | 0xB4, 0x01, 0x80, 0x63, 0xCD, 0x04, 0x36, 0x2D, 0x00, 0x33, 0x1B, 0x00, | |
4917 | 0xC2, 0x88, 0x06, 0x23, 0x68, 0x98, 0xCD, 0x04, 0xE6, 0x84, 0x06, 0x01, | |
4918 | 0x00, 0xA2, 0xD4, 0x01, 0x57, 0x60, 0x00, 0xA0, 0xDA, 0x01, 0xE6, 0x84, | |
4919 | 0x80, 0x23, 0xA0, 0x01, 0xE6, 0x84, 0x80, 0x73, 0x4B, 0x00, 0x06, 0x61, | |
4920 | 0x00, 0xA2, 0x00, 0x02, 0x04, 0x01, 0x0C, 0xDE, 0x02, 0x01, 0x03, 0xCC, | |
4921 | 0x4F, 0x00, 0x84, 0x97, 0xFC, 0x81, 0x08, 0x23, 0x02, 0x41, 0x82, 0x01, | |
4922 | 0x4F, 0x00, 0x62, 0x97, 0x48, 0x04, 0x84, 0x80, 0xF0, 0x97, 0x00, 0x46, | |
4923 | 0x56, 0x00, 0x03, 0xC0, 0x01, 0x23, 0xE8, 0x00, 0x81, 0x73, 0x06, 0x29, | |
4924 | 0x03, 0x42, 0x06, 0xE2, 0x03, 0xEE, 0x6B, 0xEB, 0x11, 0x23, 0xF8, 0x88, | |
4925 | 0x04, 0x98, 0xF0, 0x80, 0x80, 0x73, 0x80, 0x77, 0x07, 0xA4, 0x2A, 0x02, | |
4926 | 0x7C, 0x95, 0x06, 0xA6, 0x34, 0x02, 0x03, 0xA6, 0x4C, 0x04, 0x46, 0x82, | |
4927 | 0x04, 0x01, 0x03, 0xD8, 0xB4, 0x98, 0x6A, 0x96, 0x46, 0x82, 0xFE, 0x95, | |
4928 | 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0xB6, 0x2D, 0x02, 0xA6, 0x6C, 0x02, | |
4929 | 0x07, 0xA6, 0x5A, 0x02, 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x62, 0x02, | |
4930 | 0xC2, 0x88, 0x7C, 0x95, 0x48, 0x82, 0x60, 0x96, 0x48, 0x82, 0x04, 0x23, | |
4931 | 0xA0, 0x01, 0x14, 0x23, 0xA1, 0x01, 0x3C, 0x84, 0x04, 0x01, 0x0C, 0xDC, | |
4932 | 0xE0, 0x23, 0x25, 0x61, 0xEF, 0x00, 0x14, 0x01, 0x4F, 0x04, 0xA8, 0x01, | |
4933 | 0x6F, 0x00, 0xA5, 0x01, 0x03, 0x23, 0xA4, 0x01, 0x06, 0x23, 0x9C, 0x01, | |
4934 | 0x24, 0x2B, 0x1C, 0x01, 0x02, 0xA6, 0xAA, 0x02, 0x07, 0xA6, 0x5A, 0x02, | |
4935 | 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x20, 0x04, 0x01, 0xA6, 0xB4, 0x02, | |
4936 | 0x00, 0xA6, 0xB4, 0x02, 0x00, 0x33, 0x12, 0x00, 0xC2, 0x88, 0x00, 0x0E, | |
4937 | 0x80, 0x63, 0x00, 0x43, 0x00, 0xA0, 0x8C, 0x02, 0x4D, 0x04, 0x04, 0x01, | |
4938 | 0x0B, 0xDC, 0xE7, 0x23, 0x04, 0x61, 0x84, 0x01, 0x10, 0x31, 0x12, 0x35, | |
4939 | 0x14, 0x01, 0xEC, 0x00, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0xEA, 0x82, | |
4940 | 0x18, 0x23, 0x04, 0x61, 0x18, 0xA0, 0xE2, 0x02, 0x04, 0x01, 0xA2, 0xC8, | |
4941 | 0x00, 0x33, 0x1F, 0x00, 0xC2, 0x88, 0x08, 0x31, 0x0A, 0x35, 0x0C, 0x39, | |
4942 | 0x0E, 0x3D, 0x7E, 0x98, 0xB6, 0x2D, 0x01, 0xA6, 0x14, 0x03, 0x00, 0xA6, | |
4943 | 0x14, 0x03, 0x07, 0xA6, 0x0C, 0x03, 0x06, 0xA6, 0x10, 0x03, 0x03, 0xA6, | |
4944 | 0x20, 0x04, 0x02, 0xA6, 0x6C, 0x02, 0x00, 0x33, 0x33, 0x00, 0xC2, 0x88, | |
4945 | 0x7C, 0x95, 0xEE, 0x82, 0x60, 0x96, 0xEE, 0x82, 0x82, 0x98, 0x80, 0x42, | |
4946 | 0x7E, 0x98, 0x64, 0xE4, 0x04, 0x01, 0x2D, 0xC8, 0x31, 0x05, 0x07, 0x01, | |
4947 | 0x00, 0xA2, 0x54, 0x03, 0x00, 0x43, 0x87, 0x01, 0x05, 0x05, 0x86, 0x98, | |
4948 | 0x7E, 0x98, 0x00, 0xA6, 0x16, 0x03, 0x07, 0xA6, 0x4C, 0x03, 0x03, 0xA6, | |
4949 | 0x3C, 0x04, 0x06, 0xA6, 0x50, 0x03, 0x01, 0xA6, 0x16, 0x03, 0x00, 0x33, | |
4950 | 0x25, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x32, 0x83, 0x60, 0x96, 0x32, 0x83, | |
4951 | 0x04, 0x01, 0x10, 0xCE, 0x07, 0xC8, 0x05, 0x05, 0xEB, 0x04, 0x00, 0x33, | |
4952 | 0x00, 0x20, 0xC0, 0x20, 0x81, 0x62, 0x72, 0x83, 0x00, 0x01, 0x05, 0x05, | |
4953 | 0xFF, 0xA2, 0x7A, 0x03, 0xB1, 0x01, 0x08, 0x23, 0xB2, 0x01, 0x2E, 0x83, | |
4954 | 0x05, 0x05, 0x15, 0x01, 0x00, 0xA2, 0x9A, 0x03, 0xEC, 0x00, 0x6E, 0x00, | |
4955 | 0x95, 0x01, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0x01, 0xA6, 0x96, 0x03, | |
4956 | 0x00, 0xA6, 0x96, 0x03, 0x10, 0x84, 0x80, 0x42, 0x7E, 0x98, 0x01, 0xA6, | |
4957 | 0xA4, 0x03, 0x00, 0xA6, 0xBC, 0x03, 0x10, 0x84, 0xA8, 0x98, 0x80, 0x42, | |
4958 | 0x01, 0xA6, 0xA4, 0x03, 0x07, 0xA6, 0xB2, 0x03, 0xD4, 0x83, 0x7C, 0x95, | |
4959 | 0xA8, 0x83, 0x00, 0x33, 0x2F, 0x00, 0xC2, 0x88, 0xA8, 0x98, 0x80, 0x42, | |
4960 | 0x00, 0xA6, 0xBC, 0x03, 0x07, 0xA6, 0xCA, 0x03, 0xD4, 0x83, 0x7C, 0x95, | |
4961 | 0xC0, 0x83, 0x00, 0x33, 0x26, 0x00, 0xC2, 0x88, 0x38, 0x2B, 0x80, 0x32, | |
4962 | 0x80, 0x36, 0x04, 0x23, 0xA0, 0x01, 0x12, 0x23, 0xA1, 0x01, 0x10, 0x84, | |
4963 | 0x07, 0xF0, 0x06, 0xA4, 0xF4, 0x03, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23, | |
4964 | 0x83, 0x03, 0x80, 0x63, 0x03, 0xA6, 0x0E, 0x04, 0x07, 0xA6, 0x06, 0x04, | |
4965 | 0x06, 0xA6, 0x0A, 0x04, 0x00, 0x33, 0x17, 0x00, 0xC2, 0x88, 0x7C, 0x95, | |
4966 | 0xF4, 0x83, 0x60, 0x96, 0xF4, 0x83, 0x20, 0x84, 0x07, 0xF0, 0x06, 0xA4, | |
4967 | 0x20, 0x04, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23, 0x83, 0x03, 0x80, 0x63, | |
4968 | 0xB6, 0x2D, 0x03, 0xA6, 0x3C, 0x04, 0x07, 0xA6, 0x34, 0x04, 0x06, 0xA6, | |
4969 | 0x38, 0x04, 0x00, 0x33, 0x30, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x20, 0x84, | |
4970 | 0x60, 0x96, 0x20, 0x84, 0x1D, 0x01, 0x06, 0xCC, 0x00, 0x33, 0x00, 0x84, | |
4971 | 0xC0, 0x20, 0x00, 0x23, 0xEA, 0x00, 0x81, 0x62, 0xA2, 0x0D, 0x80, 0x63, | |
4972 | 0x07, 0xA6, 0x5A, 0x04, 0x00, 0x33, 0x18, 0x00, 0xC2, 0x88, 0x03, 0x03, | |
4973 | 0x80, 0x63, 0xA3, 0x01, 0x07, 0xA4, 0x64, 0x04, 0x23, 0x01, 0x00, 0xA2, | |
4974 | 0x86, 0x04, 0x0A, 0xA0, 0x76, 0x04, 0xE0, 0x00, 0x00, 0x33, 0x1D, 0x00, | |
4975 | 0xC2, 0x88, 0x0B, 0xA0, 0x82, 0x04, 0xE0, 0x00, 0x00, 0x33, 0x1E, 0x00, | |
4976 | 0xC2, 0x88, 0x42, 0x23, 0xF8, 0x88, 0x00, 0x23, 0x22, 0xA3, 0xE6, 0x04, | |
4977 | 0x08, 0x23, 0x22, 0xA3, 0xA2, 0x04, 0x28, 0x23, 0x22, 0xA3, 0xAE, 0x04, | |
4978 | 0x02, 0x23, 0x22, 0xA3, 0xC4, 0x04, 0x42, 0x23, 0xF8, 0x88, 0x4A, 0x00, | |
4979 | 0x06, 0x61, 0x00, 0xA0, 0xAE, 0x04, 0x45, 0x23, 0xF8, 0x88, 0x04, 0x98, | |
4980 | 0x00, 0xA2, 0xC0, 0x04, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x82, 0xC0, 0x20, | |
4981 | 0x81, 0x62, 0xE8, 0x81, 0x47, 0x23, 0xF8, 0x88, 0x04, 0x01, 0x0B, 0xDE, | |
4982 | 0x04, 0x98, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x81, 0xC0, 0x20, 0x81, 0x62, | |
4983 | 0x14, 0x01, 0x00, 0xA0, 0x00, 0x02, 0x43, 0x23, 0xF8, 0x88, 0x04, 0x23, | |
4984 | 0xA0, 0x01, 0x44, 0x23, 0xA1, 0x01, 0x80, 0x73, 0x4D, 0x00, 0x03, 0xA3, | |
4985 | 0xF4, 0x04, 0x00, 0x33, 0x27, 0x00, 0xC2, 0x88, 0x04, 0x01, 0x04, 0xDC, | |
4986 | 0x02, 0x23, 0xA2, 0x01, 0x04, 0x23, 0xA0, 0x01, 0x04, 0x98, 0x26, 0x95, | |
4987 | 0x4B, 0x00, 0xF6, 0x00, 0x4F, 0x04, 0x4F, 0x00, 0x00, 0xA3, 0x22, 0x05, | |
4988 | 0x00, 0x05, 0x76, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x1C, 0x05, 0x0A, 0x85, | |
4989 | 0x46, 0x97, 0xCD, 0x04, 0x24, 0x85, 0x48, 0x04, 0x84, 0x80, 0x02, 0x01, | |
4990 | 0x03, 0xDA, 0x80, 0x23, 0x82, 0x01, 0x34, 0x85, 0x02, 0x23, 0xA0, 0x01, | |
4991 | 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x40, 0x05, 0x1D, 0x01, 0x04, 0xD6, | |
4992 | 0xFF, 0x23, 0x86, 0x41, 0x4B, 0x60, 0xCB, 0x00, 0xFF, 0x23, 0x80, 0x01, | |
4993 | 0x49, 0x00, 0x81, 0x01, 0x04, 0x01, 0x02, 0xC8, 0x30, 0x01, 0x80, 0x01, | |
4994 | 0xF7, 0x04, 0x03, 0x01, 0x49, 0x04, 0x80, 0x01, 0xC9, 0x00, 0x00, 0x05, | |
4995 | 0x00, 0x01, 0xFF, 0xA0, 0x60, 0x05, 0x77, 0x04, 0x01, 0x23, 0xEA, 0x00, | |
4996 | 0x5D, 0x00, 0xFE, 0xC7, 0x00, 0x62, 0x00, 0x23, 0xEA, 0x00, 0x00, 0x63, | |
4997 | 0x07, 0xA4, 0xF8, 0x05, 0x03, 0x03, 0x02, 0xA0, 0x8E, 0x05, 0xF4, 0x85, | |
4998 | 0x00, 0x33, 0x2D, 0x00, 0xC2, 0x88, 0x04, 0xA0, 0xB8, 0x05, 0x80, 0x63, | |
4999 | 0x00, 0x23, 0xDF, 0x00, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0xA4, 0x05, | |
5000 | 0x1D, 0x01, 0x06, 0xD6, 0x02, 0x23, 0x02, 0x41, 0x82, 0x01, 0x50, 0x00, | |
5001 | 0x62, 0x97, 0x04, 0x85, 0x04, 0x23, 0x02, 0x41, 0x82, 0x01, 0x04, 0x85, | |
5002 | 0x08, 0xA0, 0xBE, 0x05, 0xF4, 0x85, 0x03, 0xA0, 0xC4, 0x05, 0xF4, 0x85, | |
5003 | 0x01, 0xA0, 0xCE, 0x05, 0x88, 0x00, 0x80, 0x63, 0xCC, 0x86, 0x07, 0xA0, | |
5004 | 0xEE, 0x05, 0x5F, 0x00, 0x00, 0x2B, 0xDF, 0x08, 0x00, 0xA2, 0xE6, 0x05, | |
5005 | 0x80, 0x67, 0x80, 0x63, 0x01, 0xA2, 0x7A, 0x06, 0x7C, 0x85, 0x06, 0x23, | |
5006 | 0x68, 0x98, 0x48, 0x23, 0xF8, 0x88, 0x07, 0x23, 0x80, 0x00, 0x06, 0x87, | |
5007 | 0x80, 0x63, 0x7C, 0x85, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63, 0x4A, 0x00, | |
5008 | 0x06, 0x61, 0x00, 0xA2, 0x36, 0x06, 0x1D, 0x01, 0x16, 0xD4, 0xC0, 0x23, | |
5009 | 0x07, 0x41, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, 0x1C, 0x06, 0x00, 0x33, | |
5010 | 0x37, 0x00, 0xC2, 0x88, 0x1D, 0x01, 0x01, 0xD6, 0x20, 0x23, 0x63, 0x60, | |
5011 | 0x83, 0x03, 0x80, 0x63, 0x02, 0x23, 0xDF, 0x00, 0x07, 0xA6, 0x7C, 0x05, | |
5012 | 0xEF, 0x04, 0x6F, 0x00, 0x00, 0x63, 0x4B, 0x00, 0x06, 0x41, 0xCB, 0x00, | |
5013 | 0x52, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x4E, 0x06, 0x1D, 0x01, 0x03, 0xCA, | |
5014 | 0xC0, 0x23, 0x07, 0x41, 0x00, 0x63, 0x1D, 0x01, 0x04, 0xCC, 0x00, 0x33, | |
5015 | 0x00, 0x83, 0xC0, 0x20, 0x81, 0x62, 0x80, 0x23, 0x07, 0x41, 0x00, 0x63, | |
5016 | 0x80, 0x67, 0x08, 0x23, 0x83, 0x03, 0x80, 0x63, 0x00, 0x63, 0x01, 0x23, | |
5017 | 0xDF, 0x00, 0x06, 0xA6, 0x84, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67, | |
5018 | 0x80, 0x63, 0x00, 0x33, 0x00, 0x40, 0xC0, 0x20, 0x81, 0x62, 0x00, 0x63, | |
5019 | 0x00, 0x00, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, 0x94, 0x06, | |
5020 | 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x00, 0x01, 0xA0, 0x14, 0x07, 0x00, 0x2B, | |
5021 | 0x40, 0x0E, 0x80, 0x63, 0x01, 0x00, 0x06, 0xA6, 0xAA, 0x06, 0x07, 0xA6, | |
5022 | 0x7C, 0x05, 0x40, 0x0E, 0x80, 0x63, 0x00, 0x43, 0x00, 0xA0, 0xA2, 0x06, | |
5023 | 0x06, 0xA6, 0xBC, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67, 0x40, 0x0E, | |
5024 | 0x80, 0x63, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63, | |
5025 | 0x07, 0xA6, 0xD6, 0x06, 0x00, 0x33, 0x2A, 0x00, 0xC2, 0x88, 0x03, 0x03, | |
5026 | 0x80, 0x63, 0x89, 0x00, 0x0A, 0x2B, 0x07, 0xA6, 0xE8, 0x06, 0x00, 0x33, | |
5027 | 0x29, 0x00, 0xC2, 0x88, 0x00, 0x43, 0x00, 0xA2, 0xF4, 0x06, 0xC0, 0x0E, | |
5028 | 0x80, 0x63, 0xDE, 0x86, 0xC0, 0x0E, 0x00, 0x33, 0x00, 0x80, 0xC0, 0x20, | |
5029 | 0x81, 0x62, 0x04, 0x01, 0x02, 0xDA, 0x80, 0x63, 0x7C, 0x85, 0x80, 0x7B, | |
5030 | 0x80, 0x63, 0x06, 0xA6, 0x8C, 0x06, 0x00, 0x33, 0x2C, 0x00, 0xC2, 0x88, | |
5031 | 0x0C, 0xA2, 0x2E, 0x07, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, | |
5032 | 0x2C, 0x07, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x33, 0x3D, 0x00, 0xC2, 0x88, | |
5033 | 0x00, 0x00, 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0x0C, 0xA0, 0x44, 0x07, | |
5034 | 0x07, 0xA6, 0x7C, 0x05, 0xBF, 0x23, 0x04, 0x61, 0x84, 0x01, 0xE6, 0x84, | |
5035 | 0x00, 0x63, 0xF0, 0x04, 0x01, 0x01, 0xF1, 0x00, 0x00, 0x01, 0xF2, 0x00, | |
5036 | 0x01, 0x05, 0x80, 0x01, 0x72, 0x04, 0x71, 0x00, 0x81, 0x01, 0x70, 0x04, | |
5037 | 0x80, 0x05, 0x81, 0x05, 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04, | |
5038 | 0x01, 0x01, 0xF1, 0x00, 0x70, 0x00, 0x81, 0x01, 0x70, 0x04, 0x71, 0x00, | |
5039 | 0x81, 0x01, 0x72, 0x00, 0x80, 0x01, 0x71, 0x04, 0x70, 0x00, 0x80, 0x01, | |
5040 | 0x70, 0x04, 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04, 0x00, 0x01, | |
5041 | 0xF1, 0x00, 0x70, 0x00, 0x80, 0x01, 0x70, 0x04, 0x71, 0x00, 0x80, 0x01, | |
5042 | 0x72, 0x00, 0x81, 0x01, 0x71, 0x04, 0x70, 0x00, 0x81, 0x01, 0x70, 0x04, | |
5043 | 0x00, 0x63, 0x00, 0x23, 0xB3, 0x01, 0x83, 0x05, 0xA3, 0x01, 0xA2, 0x01, | |
5044 | 0xA1, 0x01, 0x01, 0x23, 0xA0, 0x01, 0x00, 0x01, 0xC8, 0x00, 0x03, 0xA1, | |
5045 | 0xC4, 0x07, 0x00, 0x33, 0x07, 0x00, 0xC2, 0x88, 0x80, 0x05, 0x81, 0x05, | |
5046 | 0x04, 0x01, 0x11, 0xC8, 0x48, 0x00, 0xB0, 0x01, 0xB1, 0x01, 0x08, 0x23, | |
5047 | 0xB2, 0x01, 0x05, 0x01, 0x48, 0x04, 0x00, 0x43, 0x00, 0xA2, 0xE4, 0x07, | |
5048 | 0x00, 0x05, 0xDA, 0x87, 0x00, 0x01, 0xC8, 0x00, 0xFF, 0x23, 0x80, 0x01, | |
5049 | 0x05, 0x05, 0x00, 0x63, 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04, | |
5050 | 0x00, 0x02, 0x80, 0x43, 0x76, 0x08, 0x80, 0x02, 0x77, 0x04, 0x00, 0x63, | |
5051 | 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04, 0x00, 0x02, 0x00, 0xA0, | |
5052 | 0x14, 0x08, 0x16, 0x88, 0x00, 0x43, 0x76, 0x08, 0x80, 0x02, 0x77, 0x04, | |
5053 | 0x00, 0x63, 0xF3, 0x04, 0x00, 0x23, 0xF4, 0x00, 0x74, 0x00, 0x80, 0x43, | |
5054 | 0xF4, 0x00, 0xCF, 0x40, 0x00, 0xA2, 0x44, 0x08, 0x74, 0x04, 0x02, 0x01, | |
5055 | 0xF7, 0xC9, 0xF6, 0xD9, 0x00, 0x01, 0x01, 0xA1, 0x24, 0x08, 0x04, 0x98, | |
5056 | 0x26, 0x95, 0x24, 0x88, 0x73, 0x04, 0x00, 0x63, 0xF3, 0x04, 0x75, 0x04, | |
5057 | 0x5A, 0x88, 0x02, 0x01, 0x04, 0xD8, 0x46, 0x97, 0x04, 0x98, 0x26, 0x95, | |
5058 | 0x4A, 0x88, 0x75, 0x00, 0x00, 0xA3, 0x64, 0x08, 0x00, 0x05, 0x4E, 0x88, | |
5059 | 0x73, 0x04, 0x00, 0x63, 0x80, 0x7B, 0x80, 0x63, 0x06, 0xA6, 0x76, 0x08, | |
5060 | 0x00, 0x33, 0x3E, 0x00, 0xC2, 0x88, 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, | |
5061 | 0x00, 0x63, 0x38, 0x2B, 0x9C, 0x88, 0x38, 0x2B, 0x92, 0x88, 0x32, 0x09, | |
5062 | 0x31, 0x05, 0x92, 0x98, 0x05, 0x05, 0xB2, 0x09, 0x00, 0x63, 0x00, 0x32, | |
5063 | 0x00, 0x36, 0x00, 0x3A, 0x00, 0x3E, 0x00, 0x63, 0x80, 0x32, 0x80, 0x36, | |
5064 | 0x80, 0x3A, 0x80, 0x3E, 0xB4, 0x3D, 0x00, 0x63, 0x38, 0x2B, 0x40, 0x32, | |
5065 | 0x40, 0x36, 0x40, 0x3A, 0x40, 0x3E, 0x00, 0x63, 0x5A, 0x20, 0xC9, 0x40, | |
5066 | 0x00, 0xA0, 0xB4, 0x08, 0x5D, 0x00, 0xFE, 0xC3, 0x00, 0x63, 0x80, 0x73, | |
5067 | 0xE6, 0x20, 0x02, 0x23, 0xE8, 0x00, 0x82, 0x73, 0xFF, 0xFD, 0x80, 0x73, | |
5068 | 0x13, 0x23, 0xF8, 0x88, 0x66, 0x20, 0xC0, 0x20, 0x04, 0x23, 0xA0, 0x01, | |
5069 | 0xA1, 0x23, 0xA1, 0x01, 0x81, 0x62, 0xE2, 0x88, 0x80, 0x73, 0x80, 0x77, | |
5070 | 0x68, 0x00, 0x00, 0xA2, 0x80, 0x00, 0x03, 0xC2, 0xF1, 0xC7, 0x41, 0x23, | |
5071 | 0xF8, 0x88, 0x11, 0x23, 0xA1, 0x01, 0x04, 0x23, 0xA0, 0x01, 0xE6, 0x84, | |
5072 | }; | |
27c868c2 | 5073 | |
51219358 MW |
5074 | static unsigned short _asc_mcode_size = sizeof(_asc_mcode_buf); |
5075 | static ADV_DCNT _asc_mcode_chksum = 0x012C453FUL; | |
1da177e4 | 5076 | |
1da177e4 | 5077 | /* Microcode buffer is kept after initialization for error recovery. */ |
27c868c2 MW |
5078 | static unsigned char _adv_asc3550_buf[] = { |
5079 | 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0x16, 0x18, 0xe4, 0x00, 0xfc, | |
629d688d MW |
5080 | 0x01, 0x00, 0x48, 0xe4, 0xbe, 0x18, 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00, |
5081 | 0x00, 0xfa, 0xff, 0xff, 0x28, 0x0e, 0x9e, 0xe7, 0xff, 0x00, 0x82, 0xe7, | |
5082 | 0x00, 0xea, 0x00, 0xf6, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0, 0x01, 0xf6, | |
27c868c2 | 5083 | 0x01, 0xfa, 0x08, 0x00, 0x03, 0x00, 0x04, 0x00, 0x18, 0xf4, 0x10, 0x00, |
629d688d MW |
5084 | 0x00, 0xec, 0x85, 0xf0, 0xbc, 0x00, 0xd5, 0xf0, 0x8e, 0x0c, 0x38, 0x54, |
5085 | 0x00, 0xe6, 0x1e, 0xf0, 0x86, 0xf0, 0xb4, 0x00, 0x98, 0x57, 0xd0, 0x01, | |
5086 | 0x0c, 0x1c, 0x3e, 0x1c, 0x0c, 0x00, 0xbb, 0x00, 0xaa, 0x18, 0x02, 0x80, | |
27c868c2 | 5087 | 0x32, 0xf0, 0x01, 0xfc, 0x88, 0x0c, 0xc6, 0x12, 0x02, 0x13, 0x18, 0x40, |
629d688d MW |
5088 | 0x00, 0x57, 0x01, 0xea, 0x3c, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12, |
5089 | 0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00, 0xc0, 0x00, 0x01, 0x01, | |
5090 | 0x3e, 0x01, 0xda, 0x0f, 0x22, 0x10, 0x08, 0x12, 0x02, 0x4a, 0xb9, 0x54, | |
27c868c2 | 5091 | 0x03, 0x58, 0x1b, 0x80, 0x30, 0xe4, 0x4b, 0xe4, 0x20, 0x00, 0x32, 0x00, |
629d688d MW |
5092 | 0x3e, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01, |
5093 | 0x70, 0x01, 0x72, 0x01, 0x74, 0x01, 0x76, 0x01, 0x78, 0x01, 0x62, 0x0a, | |
5094 | 0x92, 0x0c, 0x2c, 0x10, 0x2e, 0x10, 0x06, 0x13, 0x4c, 0x1c, 0xbb, 0x55, | |
27c868c2 | 5095 | 0x3c, 0x56, 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0, 0xb1, 0xf0, |
629d688d MW |
5096 | 0x03, 0xf7, 0x06, 0xf7, 0x03, 0xfc, 0x0f, 0x00, 0x40, 0x00, 0xbe, 0x00, |
5097 | 0x00, 0x01, 0xb0, 0x08, 0x30, 0x13, 0x64, 0x15, 0x32, 0x1c, 0x38, 0x1c, | |
5098 | 0x4e, 0x1c, 0x10, 0x44, 0x02, 0x48, 0x00, 0x4c, 0x04, 0xea, 0x5d, 0xf0, | |
27c868c2 | 5099 | 0x04, 0xf6, 0x02, 0xfc, 0x05, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00, |
629d688d MW |
5100 | 0xcc, 0x00, 0x20, 0x01, 0x4e, 0x01, 0x4e, 0x0b, 0x1e, 0x0e, 0x0c, 0x10, |
5101 | 0x0a, 0x12, 0x04, 0x13, 0x40, 0x13, 0x30, 0x1c, 0x00, 0x4e, 0xbd, 0x56, | |
5102 | 0x06, 0x83, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0, 0x59, 0xf0, 0xa7, 0xf0, | |
27c868c2 | 5103 | 0xb8, 0xf0, 0x0e, 0xf7, 0x06, 0x00, 0x19, 0x00, 0x33, 0x00, 0x9b, 0x00, |
629d688d MW |
5104 | 0xa4, 0x00, 0xb5, 0x00, 0xba, 0x00, 0xd0, 0x00, 0xe1, 0x00, 0xe7, 0x00, |
5105 | 0xde, 0x03, 0x56, 0x0a, 0x14, 0x0e, 0x02, 0x10, 0x04, 0x10, 0x0a, 0x10, | |
5106 | 0x36, 0x10, 0x0a, 0x13, 0x12, 0x13, 0x52, 0x13, 0x10, 0x15, 0x14, 0x15, | |
27c868c2 | 5107 | 0xac, 0x16, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c, 0x08, 0x44, 0x38, 0x44, |
629d688d MW |
5108 | 0x91, 0x44, 0x0a, 0x45, 0x48, 0x46, 0x01, 0x48, 0x68, 0x54, 0x83, 0x55, |
5109 | 0xb0, 0x57, 0x01, 0x58, 0x83, 0x59, 0x05, 0xe6, 0x0b, 0xf0, 0x0c, 0xf0, | |
5110 | 0x5c, 0xf0, 0x4b, 0xf4, 0x04, 0xf8, 0x05, 0xf8, 0x02, 0xfa, 0x03, 0xfa, | |
27c868c2 | 5111 | 0x04, 0xfc, 0x05, 0xfc, 0x07, 0x00, 0x0a, 0x00, 0x0d, 0x00, 0x1c, 0x00, |
629d688d MW |
5112 | 0x9e, 0x00, 0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00, 0x22, 0x01, |
5113 | 0x26, 0x01, 0x79, 0x01, 0x7a, 0x01, 0xc0, 0x01, 0xc2, 0x01, 0x7c, 0x02, | |
5114 | 0x5a, 0x03, 0xea, 0x04, 0xe8, 0x07, 0x68, 0x08, 0x69, 0x08, 0xba, 0x08, | |
27c868c2 | 5115 | 0xe9, 0x09, 0x06, 0x0b, 0x3a, 0x0e, 0x00, 0x10, 0x1a, 0x10, 0xed, 0x10, |
629d688d MW |
5116 | 0xf1, 0x10, 0x06, 0x12, 0x0c, 0x13, 0x16, 0x13, 0x1e, 0x13, 0x82, 0x13, |
5117 | 0x42, 0x14, 0xd6, 0x14, 0x8a, 0x15, 0xc6, 0x17, 0xd2, 0x17, 0x6b, 0x18, | |
5118 | 0x12, 0x1c, 0x46, 0x1c, 0x9c, 0x32, 0x00, 0x40, 0x0e, 0x47, 0x48, 0x47, | |
27c868c2 | 5119 | 0x41, 0x48, 0x89, 0x48, 0x80, 0x4c, 0x00, 0x54, 0x44, 0x55, 0xe5, 0x55, |
629d688d MW |
5120 | 0x14, 0x56, 0x77, 0x57, 0xbf, 0x57, 0x40, 0x5c, 0x06, 0x80, 0x08, 0x90, |
5121 | 0x03, 0xa1, 0xfe, 0x9c, 0xf0, 0x29, 0x02, 0xfe, 0xb8, 0x0c, 0xff, 0x10, | |
5122 | 0x00, 0x00, 0xd0, 0xfe, 0xcc, 0x18, 0x00, 0xcf, 0xfe, 0x80, 0x01, 0xff, | |
27c868c2 | 5123 | 0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00, |
629d688d MW |
5124 | 0x00, 0xfe, 0x57, 0x24, 0x00, 0xfe, 0x48, 0x00, 0x4f, 0xff, 0x04, 0x00, |
5125 | 0x00, 0x10, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08, 0x01, 0x01, 0xff, 0x08, | |
5126 | 0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x0f, | |
27c868c2 | 5127 | 0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00, |
629d688d MW |
5128 | 0xfe, 0x04, 0xf7, 0xcf, 0x2a, 0x67, 0x0b, 0x01, 0xfe, 0xce, 0x0e, 0xfe, |
5129 | 0x04, 0xf7, 0xcf, 0x67, 0x0b, 0x3c, 0x2a, 0xfe, 0x3d, 0xf0, 0xfe, 0x02, | |
5130 | 0x02, 0xfe, 0x20, 0xf0, 0x9c, 0xfe, 0x91, 0xf0, 0xfe, 0xf0, 0x01, 0xfe, | |
27c868c2 | 5131 | 0x90, 0xf0, 0xfe, 0xf0, 0x01, 0xfe, 0x8f, 0xf0, 0x9c, 0x05, 0x51, 0x3b, |
629d688d MW |
5132 | 0x02, 0xfe, 0xd4, 0x0c, 0x01, 0xfe, 0x44, 0x0d, 0xfe, 0xdd, 0x12, 0xfe, |
5133 | 0xfc, 0x10, 0xfe, 0x28, 0x1c, 0x05, 0xfe, 0xa6, 0x00, 0xfe, 0xd3, 0x12, | |
5134 | 0x47, 0x18, 0xfe, 0xa6, 0x00, 0xb5, 0xfe, 0x48, 0xf0, 0xfe, 0x86, 0x02, | |
27c868c2 | 5135 | 0xfe, 0x49, 0xf0, 0xfe, 0xa0, 0x02, 0xfe, 0x4a, 0xf0, 0xfe, 0xbe, 0x02, |
629d688d MW |
5136 | 0xfe, 0x46, 0xf0, 0xfe, 0x50, 0x02, 0xfe, 0x47, 0xf0, 0xfe, 0x56, 0x02, |
5137 | 0xfe, 0x43, 0xf0, 0xfe, 0x44, 0x02, 0xfe, 0x44, 0xf0, 0xfe, 0x48, 0x02, | |
5138 | 0xfe, 0x45, 0xf0, 0xfe, 0x4c, 0x02, 0x17, 0x0b, 0xa0, 0x17, 0x06, 0x18, | |
27c868c2 | 5139 | 0x96, 0x02, 0x29, 0xfe, 0x00, 0x1c, 0xde, 0xfe, 0x02, 0x1c, 0xdd, 0xfe, |
629d688d MW |
5140 | 0x1e, 0x1c, 0xfe, 0xe9, 0x10, 0x01, 0xfe, 0x20, 0x17, 0xfe, 0xe7, 0x10, |
5141 | 0xfe, 0x06, 0xfc, 0xc7, 0x0a, 0x6b, 0x01, 0x9e, 0x02, 0x29, 0x14, 0x4d, | |
5142 | 0x37, 0x97, 0x01, 0xfe, 0x64, 0x0f, 0x0a, 0x6b, 0x01, 0x82, 0xfe, 0xbd, | |
27c868c2 | 5143 | 0x10, 0x0a, 0x6b, 0x01, 0x82, 0xfe, 0xad, 0x10, 0xfe, 0x16, 0x1c, 0xfe, |
629d688d MW |
5144 | 0x58, 0x1c, 0x17, 0x06, 0x18, 0x96, 0x2a, 0x25, 0x29, 0xfe, 0x3d, 0xf0, |
5145 | 0xfe, 0x02, 0x02, 0x21, 0xfe, 0x94, 0x02, 0xfe, 0x5a, 0x1c, 0xea, 0xfe, | |
5146 | 0x14, 0x1c, 0x14, 0xfe, 0x30, 0x00, 0x37, 0x97, 0x01, 0xfe, 0x54, 0x0f, | |
27c868c2 | 5147 | 0x17, 0x06, 0x18, 0x96, 0x02, 0xd0, 0x1e, 0x20, 0x07, 0x10, 0x34, 0xfe, |
629d688d MW |
5148 | 0x69, 0x10, 0x17, 0x06, 0x18, 0x96, 0xfe, 0x04, 0xec, 0x20, 0x46, 0x3d, |
5149 | 0x12, 0x20, 0xfe, 0x05, 0xf6, 0xc7, 0x01, 0xfe, 0x52, 0x16, 0x09, 0x4a, | |
5150 | 0x4c, 0x35, 0x11, 0x2d, 0x3c, 0x8a, 0x01, 0xe6, 0x02, 0x29, 0x0a, 0x40, | |
27c868c2 | 5151 | 0x01, 0x0e, 0x07, 0x00, 0x5d, 0x01, 0x6f, 0xfe, 0x18, 0x10, 0xfe, 0x41, |
629d688d MW |
5152 | 0x58, 0x0a, 0x99, 0x01, 0x0e, 0xfe, 0xc8, 0x54, 0x64, 0xfe, 0x0c, 0x03, |
5153 | 0x01, 0xe6, 0x02, 0x29, 0x2a, 0x46, 0xfe, 0x02, 0xe8, 0x27, 0xf8, 0xfe, | |
5154 | 0x9e, 0x43, 0xf7, 0xfe, 0x27, 0xf0, 0xfe, 0xdc, 0x01, 0xfe, 0x07, 0x4b, | |
27c868c2 | 5155 | 0xfe, 0x20, 0xf0, 0x9c, 0xfe, 0x40, 0x1c, 0x25, 0xd2, 0xfe, 0x26, 0xf0, |
629d688d MW |
5156 | 0xfe, 0x56, 0x03, 0xfe, 0xa0, 0xf0, 0xfe, 0x44, 0x03, 0xfe, 0x11, 0xf0, |
5157 | 0x9c, 0xfe, 0xef, 0x10, 0xfe, 0x9f, 0xf0, 0xfe, 0x64, 0x03, 0xeb, 0x0f, | |
5158 | 0xfe, 0x11, 0x00, 0x02, 0x5a, 0x2a, 0xfe, 0x48, 0x1c, 0xeb, 0x09, 0x04, | |
27c868c2 | 5159 | 0x1d, 0xfe, 0x18, 0x13, 0x23, 0x1e, 0x98, 0xac, 0x12, 0x98, 0x0a, 0x40, |
629d688d MW |
5160 | 0x01, 0x0e, 0xac, 0x75, 0x01, 0xfe, 0xbc, 0x15, 0x11, 0xca, 0x25, 0xd2, |
5161 | 0xfe, 0x01, 0xf0, 0xd2, 0xfe, 0x82, 0xf0, 0xfe, 0x92, 0x03, 0xec, 0x11, | |
5162 | 0xfe, 0xe4, 0x00, 0x65, 0xfe, 0xa4, 0x03, 0x25, 0x32, 0x1f, 0xfe, 0xb4, | |
27c868c2 | 5163 | 0x03, 0x01, 0x43, 0xfe, 0x06, 0xf0, 0xfe, 0xc4, 0x03, 0x8d, 0x81, 0xfe, |
629d688d MW |
5164 | 0x0a, 0xf0, 0xfe, 0x7a, 0x06, 0x02, 0x22, 0x05, 0x6b, 0x28, 0x16, 0xfe, |
5165 | 0xf6, 0x04, 0x14, 0x2c, 0x01, 0x33, 0x8f, 0xfe, 0x66, 0x02, 0x02, 0xd1, | |
5166 | 0xeb, 0x2a, 0x67, 0x1a, 0xfe, 0x67, 0x1b, 0xf8, 0xf7, 0xfe, 0x48, 0x1c, | |
27c868c2 | 5167 | 0x70, 0x01, 0x6e, 0x87, 0x0a, 0x40, 0x01, 0x0e, 0x07, 0x00, 0x16, 0xd3, |
629d688d MW |
5168 | 0x0a, 0xca, 0x01, 0x0e, 0x74, 0x60, 0x59, 0x76, 0x27, 0x05, 0x6b, 0x28, |
5169 | 0xfe, 0x10, 0x12, 0x14, 0x2c, 0x01, 0x33, 0x8f, 0xfe, 0x66, 0x02, 0x02, | |
5170 | 0xd1, 0xbc, 0x7d, 0xbd, 0x7f, 0x25, 0x22, 0x65, 0xfe, 0x3c, 0x04, 0x1f, | |
27c868c2 | 5171 | 0xfe, 0x38, 0x04, 0x68, 0xfe, 0xa0, 0x00, 0xfe, 0x9b, 0x57, 0xfe, 0x4e, |
629d688d MW |
5172 | 0x12, 0x2b, 0xff, 0x02, 0x00, 0x10, 0x01, 0x08, 0x1f, 0xfe, 0xe0, 0x04, |
5173 | 0x2b, 0x01, 0x08, 0x1f, 0x22, 0x30, 0x2e, 0xd5, 0xfe, 0x4c, 0x44, 0xfe, | |
5174 | 0x4c, 0x12, 0x60, 0xfe, 0x44, 0x48, 0x13, 0x2c, 0xfe, 0x4c, 0x54, 0x64, | |
27c868c2 | 5175 | 0xd3, 0x46, 0x76, 0x27, 0xfa, 0xef, 0xfe, 0x62, 0x13, 0x09, 0x04, 0x1d, |
629d688d MW |
5176 | 0xfe, 0x2a, 0x13, 0x2f, 0x07, 0x7e, 0xa5, 0xfe, 0x20, 0x10, 0x13, 0x2c, |
5177 | 0xfe, 0x4c, 0x54, 0x64, 0xd3, 0xfa, 0xef, 0x86, 0x09, 0x04, 0x1d, 0xfe, | |
5178 | 0x08, 0x13, 0x2f, 0x07, 0x7e, 0x6e, 0x09, 0x04, 0x1d, 0xfe, 0x1c, 0x12, | |
27c868c2 | 5179 | 0x14, 0x92, 0x09, 0x04, 0x06, 0x3b, 0x14, 0xc4, 0x01, 0x33, 0x8f, 0xfe, |
629d688d MW |
5180 | 0x70, 0x0c, 0x02, 0x22, 0x2b, 0x11, 0xfe, 0xe6, 0x00, 0xfe, 0x1c, 0x90, |
5181 | 0xf9, 0x03, 0x14, 0x92, 0x01, 0x33, 0x02, 0x29, 0xfe, 0x42, 0x5b, 0x67, | |
5182 | 0x1a, 0xfe, 0x46, 0x59, 0xf8, 0xf7, 0xfe, 0x87, 0x80, 0xfe, 0x31, 0xe4, | |
27c868c2 | 5183 | 0x4f, 0x09, 0x04, 0x0b, 0xfe, 0x78, 0x13, 0xfe, 0x20, 0x80, 0x07, 0x1a, |
629d688d MW |
5184 | 0xfe, 0x70, 0x12, 0x49, 0x04, 0x06, 0xfe, 0x60, 0x13, 0x05, 0xfe, 0xa2, |
5185 | 0x00, 0x28, 0x16, 0xfe, 0x80, 0x05, 0xfe, 0x31, 0xe4, 0x6a, 0x49, 0x04, | |
5186 | 0x0b, 0xfe, 0x4a, 0x13, 0x05, 0xfe, 0xa0, 0x00, 0x28, 0xfe, 0x42, 0x12, | |
27c868c2 | 5187 | 0x5e, 0x01, 0x08, 0x25, 0x32, 0xf1, 0x01, 0x08, 0x26, 0xfe, 0x98, 0x05, |
629d688d MW |
5188 | 0x11, 0xfe, 0xe3, 0x00, 0x23, 0x49, 0xfe, 0x4a, 0xf0, 0xfe, 0x6a, 0x05, |
5189 | 0xfe, 0x49, 0xf0, 0xfe, 0x64, 0x05, 0x83, 0x24, 0xfe, 0x21, 0x00, 0xa1, | |
5190 | 0x24, 0xfe, 0x22, 0x00, 0xa0, 0x24, 0x4c, 0xfe, 0x09, 0x48, 0x01, 0x08, | |
27c868c2 | 5191 | 0x26, 0xfe, 0x98, 0x05, 0xfe, 0xe2, 0x08, 0x49, 0x04, 0xc5, 0x3b, 0x01, |
629d688d MW |
5192 | 0x86, 0x24, 0x06, 0x12, 0xcc, 0x37, 0xfe, 0x27, 0x01, 0x09, 0x04, 0x1d, |
5193 | 0xfe, 0x22, 0x12, 0x47, 0x01, 0xa7, 0x14, 0x92, 0x09, 0x04, 0x06, 0x3b, | |
5194 | 0x14, 0xc4, 0x01, 0x33, 0x8f, 0xfe, 0x70, 0x0c, 0x02, 0x22, 0x05, 0xfe, | |
27c868c2 | 5195 | 0x9c, 0x00, 0x28, 0xfe, 0x3e, 0x12, 0x05, 0x50, 0x28, 0xfe, 0x36, 0x13, |
629d688d MW |
5196 | 0x47, 0x01, 0xa7, 0x26, 0xfe, 0x08, 0x06, 0x0a, 0x06, 0x49, 0x04, 0x19, |
5197 | 0xfe, 0x02, 0x12, 0x5f, 0x01, 0xfe, 0xaa, 0x14, 0x1f, 0xfe, 0xfe, 0x05, | |
5198 | 0x11, 0x9a, 0x01, 0x43, 0x11, 0xfe, 0xe5, 0x00, 0x05, 0x50, 0xb4, 0x0c, | |
27c868c2 | 5199 | 0x50, 0x05, 0xc6, 0x28, 0xfe, 0x62, 0x12, 0x05, 0x3f, 0x28, 0xfe, 0x5a, |
629d688d MW |
5200 | 0x13, 0x01, 0xfe, 0x14, 0x18, 0x01, 0xfe, 0x66, 0x18, 0xfe, 0x43, 0x48, |
5201 | 0xb7, 0x19, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0x1c, 0x3d, | |
5202 | 0x85, 0xb7, 0x69, 0x47, 0x01, 0xa7, 0x26, 0xfe, 0x72, 0x06, 0x49, 0x04, | |
27c868c2 | 5203 | 0x1b, 0xdf, 0x89, 0x0a, 0x4d, 0x01, 0xfe, 0xd8, 0x14, 0x1f, 0xfe, 0x68, |
629d688d MW |
5204 | 0x06, 0x11, 0x9a, 0x01, 0x43, 0x11, 0xfe, 0xe5, 0x00, 0x05, 0x3f, 0xb4, |
5205 | 0x0c, 0x3f, 0x17, 0x06, 0x01, 0xa7, 0xec, 0x72, 0x70, 0x01, 0x6e, 0x87, | |
5206 | 0x11, 0xfe, 0xe2, 0x00, 0x01, 0x08, 0x25, 0x32, 0xfe, 0x0a, 0xf0, 0xfe, | |
27c868c2 | 5207 | 0xa6, 0x06, 0x8c, 0xfe, 0x5c, 0x07, 0xfe, 0x06, 0xf0, 0xfe, 0x64, 0x07, |
629d688d MW |
5208 | 0x8d, 0x81, 0x02, 0x22, 0x09, 0x04, 0x0b, 0xfe, 0x2e, 0x12, 0x15, 0x1a, |
5209 | 0x01, 0x08, 0x15, 0x00, 0x01, 0x08, 0x15, 0x00, 0x01, 0x08, 0x15, 0x00, | |
5210 | 0x01, 0x08, 0xfe, 0x99, 0xa4, 0x01, 0x08, 0x15, 0x00, 0x02, 0xfe, 0x32, | |
27c868c2 | 5211 | 0x08, 0x61, 0x04, 0x1b, 0xfe, 0x38, 0x12, 0x09, 0x04, 0x1b, 0x6e, 0x15, |
629d688d MW |
5212 | 0xfe, 0x1b, 0x00, 0x01, 0x08, 0x15, 0x00, 0x01, 0x08, 0x15, 0x00, 0x01, |
5213 | 0x08, 0x15, 0x00, 0x01, 0x08, 0x15, 0x06, 0x01, 0x08, 0x15, 0x00, 0x02, | |
5214 | 0xd9, 0x66, 0x4c, 0xfe, 0x3a, 0x55, 0x5f, 0xfe, 0x9a, 0x81, 0x4b, 0x1d, | |
27c868c2 | 5215 | 0xba, 0xfe, 0x32, 0x07, 0x0a, 0x1d, 0xfe, 0x09, 0x6f, 0xaf, 0xfe, 0xca, |
629d688d MW |
5216 | 0x45, 0xfe, 0x32, 0x12, 0x62, 0x2c, 0x85, 0x66, 0x7b, 0x01, 0x08, 0x25, |
5217 | 0x32, 0xfe, 0x0a, 0xf0, 0xfe, 0x32, 0x07, 0x8d, 0x81, 0x8c, 0xfe, 0x5c, | |
5218 | 0x07, 0x02, 0x22, 0x01, 0x43, 0x02, 0xfe, 0x8a, 0x06, 0x15, 0x19, 0x02, | |
27c868c2 | 5219 | 0xfe, 0x8a, 0x06, 0xfe, 0x9c, 0xf7, 0xd4, 0xfe, 0x2c, 0x90, 0xfe, 0xae, |
629d688d MW |
5220 | 0x90, 0x77, 0xfe, 0xca, 0x07, 0x0c, 0x54, 0x18, 0x55, 0x09, 0x4a, 0x6a, |
5221 | 0x35, 0x1e, 0x20, 0x07, 0x10, 0xfe, 0x0e, 0x12, 0x74, 0xfe, 0x80, 0x80, | |
5222 | 0x37, 0x20, 0x63, 0x27, 0xfe, 0x06, 0x10, 0xfe, 0x83, 0xe7, 0xc4, 0xa1, | |
27c868c2 | 5223 | 0xfe, 0x03, 0x40, 0x09, 0x4a, 0x4f, 0x35, 0x01, 0xa8, 0xad, 0xfe, 0x1f, |
629d688d MW |
5224 | 0x40, 0x12, 0x58, 0x01, 0xa5, 0xfe, 0x08, 0x50, 0xfe, 0x8a, 0x50, 0xfe, |
5225 | 0x44, 0x51, 0xfe, 0xc6, 0x51, 0x83, 0xfb, 0xfe, 0x8a, 0x90, 0x0c, 0x52, | |
5226 | 0x18, 0x53, 0xfe, 0x0c, 0x90, 0xfe, 0x8e, 0x90, 0xfe, 0x40, 0x50, 0xfe, | |
27c868c2 | 5227 | 0xc2, 0x50, 0x0c, 0x39, 0x18, 0x3a, 0xfe, 0x4a, 0x10, 0x09, 0x04, 0x6a, |
629d688d MW |
5228 | 0xfe, 0x2a, 0x12, 0xfe, 0x2c, 0x90, 0xfe, 0xae, 0x90, 0x0c, 0x54, 0x18, |
5229 | 0x55, 0x09, 0x04, 0x4f, 0x85, 0x01, 0xa8, 0xfe, 0x1f, 0x80, 0x12, 0x58, | |
5230 | 0xfe, 0x44, 0x90, 0xfe, 0xc6, 0x90, 0x0c, 0x56, 0x18, 0x57, 0xfb, 0xfe, | |
27c868c2 | 5231 | 0x8a, 0x90, 0x0c, 0x52, 0x18, 0x53, 0xfe, 0x40, 0x90, 0xfe, 0xc2, 0x90, |
629d688d MW |
5232 | 0x0c, 0x39, 0x18, 0x3a, 0x0c, 0x38, 0x18, 0x4e, 0x09, 0x4a, 0x19, 0x35, |
5233 | 0x2a, 0x13, 0xfe, 0x4e, 0x11, 0x65, 0xfe, 0x48, 0x08, 0xfe, 0x9e, 0xf0, | |
5234 | 0xfe, 0x5c, 0x08, 0xb1, 0x16, 0x32, 0x2a, 0x73, 0xdd, 0xb8, 0xfe, 0x80, | |
27c868c2 | 5235 | 0x08, 0xb9, 0xfe, 0x9e, 0x08, 0x8c, 0xfe, 0x74, 0x08, 0xfe, 0x06, 0xf0, |
629d688d MW |
5236 | 0xfe, 0x7a, 0x08, 0x8d, 0x81, 0x02, 0x22, 0x01, 0x43, 0xfe, 0xc9, 0x10, |
5237 | 0x15, 0x19, 0xfe, 0xc9, 0x10, 0x61, 0x04, 0x06, 0xfe, 0x10, 0x12, 0x61, | |
5238 | 0x04, 0x0b, 0x45, 0x09, 0x04, 0x0b, 0xfe, 0x68, 0x12, 0xfe, 0x2e, 0x1c, | |
27c868c2 | 5239 | 0x02, 0xfe, 0x24, 0x0a, 0x61, 0x04, 0x06, 0x45, 0x61, 0x04, 0x0b, 0xfe, |
629d688d MW |
5240 | 0x52, 0x12, 0xfe, 0x2c, 0x1c, 0xfe, 0xaa, 0xf0, 0xfe, 0x1e, 0x09, 0xfe, |
5241 | 0xac, 0xf0, 0xfe, 0xbe, 0x08, 0xfe, 0x8a, 0x10, 0xaa, 0xfe, 0xf3, 0x10, | |
5242 | 0xfe, 0xad, 0xf0, 0xfe, 0xca, 0x08, 0x02, 0xfe, 0x24, 0x0a, 0xab, 0xfe, | |
27c868c2 | 5243 | 0xe7, 0x10, 0xfe, 0x2b, 0xf0, 0x9d, 0xe9, 0x1c, 0xfe, 0x00, 0xfe, 0xfe, |
629d688d MW |
5244 | 0x1c, 0x12, 0xb5, 0xfe, 0xd2, 0xf0, 0x9d, 0xfe, 0x76, 0x18, 0x1c, 0x1a, |
5245 | 0x16, 0x9d, 0x05, 0xcb, 0x1c, 0x06, 0x16, 0x9d, 0xb8, 0x6d, 0xb9, 0x6d, | |
5246 | 0xaa, 0xab, 0xfe, 0xb1, 0x10, 0x70, 0x5e, 0x2b, 0x14, 0x92, 0x01, 0x33, | |
27c868c2 | 5247 | 0x0f, 0xfe, 0x35, 0x00, 0xfe, 0x01, 0xf0, 0x5a, 0x0f, 0x7c, 0x02, 0x5a, |
629d688d MW |
5248 | 0xfe, 0x74, 0x18, 0x1c, 0xfe, 0x00, 0xf8, 0x16, 0x6d, 0x67, 0x1b, 0x01, |
5249 | 0xfe, 0x44, 0x0d, 0x3b, 0x01, 0xe6, 0x1e, 0x27, 0x74, 0x67, 0x1a, 0x02, | |
5250 | 0x6d, 0x09, 0x04, 0x0b, 0x21, 0xfe, 0x06, 0x0a, 0x09, 0x04, 0x6a, 0xfe, | |
27c868c2 | 5251 | 0x82, 0x12, 0x09, 0x04, 0x19, 0xfe, 0x66, 0x13, 0x1e, 0x58, 0xac, 0xfc, |
629d688d MW |
5252 | 0xfe, 0x83, 0x80, 0xfe, 0xc8, 0x44, 0xfe, 0x2e, 0x13, 0xfe, 0x04, 0x91, |
5253 | 0xfe, 0x86, 0x91, 0x63, 0x27, 0xfe, 0x40, 0x59, 0xfe, 0xc1, 0x59, 0x77, | |
5254 | 0xd7, 0x05, 0x54, 0x31, 0x55, 0x0c, 0x7b, 0x18, 0x7c, 0xbe, 0x54, 0xbf, | |
27c868c2 | 5255 | 0x55, 0x01, 0xa8, 0xad, 0x63, 0x27, 0x12, 0x58, 0xc0, 0x38, 0xc1, 0x4e, |
629d688d MW |
5256 | 0x79, 0x56, 0x68, 0x57, 0xf4, 0xf5, 0xfe, 0x04, 0xfa, 0x38, 0xfe, 0x05, |
5257 | 0xfa, 0x4e, 0x01, 0xa5, 0xa2, 0x23, 0x0c, 0x7b, 0x0c, 0x7c, 0x79, 0x56, | |
5258 | 0x68, 0x57, 0xfe, 0x12, 0x10, 0x09, 0x04, 0x19, 0x16, 0xd7, 0x79, 0x39, | |
27c868c2 | 5259 | 0x68, 0x3a, 0x09, 0x04, 0xfe, 0xf7, 0x00, 0x35, 0x05, 0x52, 0x31, 0x53, |
629d688d MW |
5260 | 0xfe, 0x10, 0x58, 0xfe, 0x91, 0x58, 0xfe, 0x14, 0x59, 0xfe, 0x95, 0x59, |
5261 | 0x02, 0x6d, 0x09, 0x04, 0x19, 0x16, 0xd7, 0x09, 0x04, 0xfe, 0xf7, 0x00, | |
5262 | 0x35, 0xfe, 0x3a, 0x55, 0xfe, 0x19, 0x81, 0x5f, 0xfe, 0x10, 0x90, 0xfe, | |
27c868c2 | 5263 | 0x92, 0x90, 0xfe, 0xd7, 0x10, 0x2f, 0x07, 0x9b, 0x16, 0xfe, 0xc6, 0x08, |
629d688d MW |
5264 | 0x11, 0x9b, 0x09, 0x04, 0x0b, 0xfe, 0x14, 0x13, 0x05, 0x39, 0x31, 0x3a, |
5265 | 0x77, 0xfe, 0xc6, 0x08, 0xfe, 0x0c, 0x58, 0xfe, 0x8d, 0x58, 0x02, 0x6d, | |
5266 | 0x23, 0x47, 0xfe, 0x19, 0x80, 0xde, 0x09, 0x04, 0x0b, 0xfe, 0x1a, 0x12, | |
27c868c2 | 5267 | 0xfe, 0x6c, 0x19, 0xfe, 0x19, 0x41, 0xe9, 0xb5, 0xfe, 0xd1, 0xf0, 0xd9, |
629d688d MW |
5268 | 0x14, 0x7a, 0x01, 0x33, 0x0f, 0xfe, 0x44, 0x00, 0xfe, 0x8e, 0x10, 0xfe, |
5269 | 0x6c, 0x19, 0xbe, 0x39, 0xfe, 0xed, 0x19, 0xbf, 0x3a, 0xfe, 0x0c, 0x51, | |
5270 | 0xfe, 0x8e, 0x51, 0xe9, 0x1c, 0xfe, 0x00, 0xff, 0x34, 0xfe, 0x74, 0x10, | |
27c868c2 | 5271 | 0xb5, 0xfe, 0xd2, 0xf0, 0xfe, 0xb2, 0x0a, 0xfe, 0x76, 0x18, 0x1c, 0x1a, |
629d688d MW |
5272 | 0x84, 0x05, 0xcb, 0x1c, 0x06, 0xfe, 0x08, 0x13, 0x0f, 0xfe, 0x16, 0x00, |
5273 | 0x02, 0x5a, 0xfe, 0xd1, 0xf0, 0xfe, 0xc4, 0x0a, 0x14, 0x7a, 0x01, 0x33, | |
5274 | 0x0f, 0xfe, 0x17, 0x00, 0xfe, 0x42, 0x10, 0xfe, 0xce, 0xf0, 0xfe, 0xca, | |
27c868c2 | 5275 | 0x0a, 0xfe, 0x3c, 0x10, 0xfe, 0xcd, 0xf0, 0xfe, 0xd6, 0x0a, 0x0f, 0xfe, |
629d688d MW |
5276 | 0x22, 0x00, 0x02, 0x5a, 0xfe, 0xcb, 0xf0, 0xfe, 0xe2, 0x0a, 0x0f, 0xfe, |
5277 | 0x24, 0x00, 0x02, 0x5a, 0xfe, 0xd0, 0xf0, 0xfe, 0xec, 0x0a, 0x0f, 0x93, | |
5278 | 0xdc, 0xfe, 0xcf, 0xf0, 0xfe, 0xf6, 0x0a, 0x0f, 0x4c, 0xfe, 0x10, 0x10, | |
27c868c2 | 5279 | 0xfe, 0xcc, 0xf0, 0xd9, 0x61, 0x04, 0x19, 0x3b, 0x0f, 0xfe, 0x12, 0x00, |
629d688d MW |
5280 | 0x2a, 0x13, 0xfe, 0x4e, 0x11, 0x65, 0xfe, 0x0c, 0x0b, 0xfe, 0x9e, 0xf0, |
5281 | 0xfe, 0x20, 0x0b, 0xb1, 0x16, 0x32, 0x2a, 0x73, 0xdd, 0xb8, 0x22, 0xb9, | |
5282 | 0x22, 0x2a, 0xec, 0x65, 0xfe, 0x2c, 0x0b, 0x25, 0x32, 0x8c, 0xfe, 0x48, | |
27c868c2 | 5283 | 0x0b, 0x8d, 0x81, 0xb8, 0xd4, 0xb9, 0xd4, 0x02, 0x22, 0x01, 0x43, 0xfe, |
629d688d MW |
5284 | 0xdb, 0x10, 0x11, 0xfe, 0xe8, 0x00, 0xaa, 0xab, 0x70, 0xbc, 0x7d, 0xbd, |
5285 | 0x7f, 0xfe, 0x89, 0xf0, 0x22, 0x30, 0x2e, 0xd8, 0xbc, 0x7d, 0xbd, 0x7f, | |
5286 | 0x01, 0x08, 0x1f, 0x22, 0x30, 0x2e, 0xd6, 0xb1, 0x45, 0x0f, 0xfe, 0x42, | |
27c868c2 | 5287 | 0x00, 0x02, 0x5a, 0x78, 0x06, 0xfe, 0x81, 0x49, 0x16, 0xfe, 0x38, 0x0c, |
629d688d MW |
5288 | 0x09, 0x04, 0x0b, 0xfe, 0x44, 0x13, 0x0f, 0x00, 0x4b, 0x0b, 0xfe, 0x54, |
5289 | 0x12, 0x4b, 0xfe, 0x28, 0x00, 0x21, 0xfe, 0xa6, 0x0c, 0x0a, 0x40, 0x01, | |
5290 | 0x0e, 0x07, 0x00, 0x5d, 0x3e, 0xfe, 0x28, 0x00, 0xfe, 0xe2, 0x10, 0x01, | |
27c868c2 | 5291 | 0xe7, 0x01, 0xe8, 0x0a, 0x99, 0x01, 0xfe, 0x32, 0x0e, 0x59, 0x11, 0x2d, |
629d688d MW |
5292 | 0x01, 0x6f, 0x02, 0x29, 0x0f, 0xfe, 0x44, 0x00, 0x4b, 0x0b, 0xdf, 0x3e, |
5293 | 0x0b, 0xfe, 0xb4, 0x10, 0x01, 0x86, 0x3e, 0x0b, 0xfe, 0xaa, 0x10, 0x01, | |
5294 | 0x86, 0xfe, 0x19, 0x82, 0xfe, 0x34, 0x46, 0xa3, 0x3e, 0x0b, 0x0f, 0xfe, | |
27c868c2 | 5295 | 0x43, 0x00, 0xfe, 0x96, 0x10, 0x09, 0x4a, 0x0b, 0x35, 0x01, 0xe7, 0x01, |
629d688d MW |
5296 | 0xe8, 0x59, 0x11, 0x2d, 0x01, 0x6f, 0x67, 0x0b, 0x59, 0x3c, 0x8a, 0x02, |
5297 | 0xfe, 0x2a, 0x03, 0x09, 0x04, 0x0b, 0x84, 0x3e, 0x0b, 0x0f, 0x00, 0xfe, | |
5298 | 0x5c, 0x10, 0x61, 0x04, 0x1b, 0xfe, 0x58, 0x12, 0x09, 0x04, 0x1b, 0xfe, | |
27c868c2 | 5299 | 0x50, 0x13, 0xfe, 0x1c, 0x1c, 0xfe, 0x9d, 0xf0, 0xfe, 0x5c, 0x0c, 0xfe, |
629d688d MW |
5300 | 0x1c, 0x1c, 0xfe, 0x9d, 0xf0, 0xfe, 0x62, 0x0c, 0x09, 0x4a, 0x1b, 0x35, |
5301 | 0xfe, 0xa9, 0x10, 0x0f, 0xfe, 0x15, 0x00, 0xfe, 0x04, 0xe6, 0x0b, 0x5f, | |
5302 | 0x5c, 0x0f, 0xfe, 0x13, 0x00, 0xfe, 0x10, 0x10, 0x0f, 0xfe, 0x47, 0x00, | |
27c868c2 | 5303 | 0xa1, 0x0f, 0xfe, 0x41, 0x00, 0xa0, 0x0f, 0xfe, 0x24, 0x00, 0x87, 0xaa, |
629d688d MW |
5304 | 0xab, 0x70, 0x05, 0x6b, 0x28, 0x21, 0xd1, 0x5f, 0xfe, 0x04, 0xe6, 0x1b, |
5305 | 0xfe, 0x9d, 0x41, 0xfe, 0x1c, 0x42, 0x59, 0x01, 0xda, 0x02, 0x29, 0xea, | |
5306 | 0x14, 0x0b, 0x37, 0x95, 0xa9, 0x14, 0xfe, 0x31, 0x00, 0x37, 0x97, 0x01, | |
27c868c2 | 5307 | 0xfe, 0x54, 0x0f, 0x02, 0xd0, 0x3c, 0xfe, 0x06, 0xec, 0xc9, 0xee, 0x3e, |
629d688d MW |
5308 | 0x1d, 0xfe, 0xce, 0x45, 0x34, 0x3c, 0xfe, 0x06, 0xea, 0xc9, 0xfe, 0x47, |
5309 | 0x4b, 0x89, 0xfe, 0x75, 0x57, 0x05, 0x51, 0xfe, 0x98, 0x56, 0xfe, 0x38, | |
5310 | 0x12, 0x0a, 0x42, 0x01, 0x0e, 0xfe, 0x44, 0x48, 0x46, 0x09, 0x04, 0x1d, | |
27c868c2 | 5311 | 0xfe, 0x1a, 0x13, 0x0a, 0x40, 0x01, 0x0e, 0x47, 0xfe, 0x41, 0x58, 0x0a, |
629d688d MW |
5312 | 0x99, 0x01, 0x0e, 0xfe, 0x49, 0x54, 0x8e, 0xfe, 0x2a, 0x0d, 0x02, 0xfe, |
5313 | 0x2a, 0x03, 0x0a, 0x51, 0xfe, 0xee, 0x14, 0xee, 0x3e, 0x1d, 0xfe, 0xce, | |
5314 | 0x45, 0x34, 0x3c, 0xfe, 0xce, 0x47, 0xfe, 0xad, 0x13, 0x02, 0x29, 0x1e, | |
27c868c2 | 5315 | 0x20, 0x07, 0x10, 0xfe, 0x9e, 0x12, 0x23, 0x12, 0x4d, 0x12, 0x94, 0x12, |
629d688d MW |
5316 | 0xce, 0x1e, 0x2d, 0x47, 0x37, 0x2d, 0xb1, 0xe0, 0xfe, 0xbc, 0xf0, 0xfe, |
5317 | 0xec, 0x0d, 0x13, 0x06, 0x12, 0x4d, 0x01, 0xfe, 0xe2, 0x15, 0x05, 0xfe, | |
5318 | 0x38, 0x01, 0x31, 0xfe, 0x3a, 0x01, 0x77, 0xfe, 0xf0, 0x0d, 0xfe, 0x02, | |
27c868c2 | 5319 | 0xec, 0xce, 0x62, 0x00, 0x5d, 0xfe, 0x04, 0xec, 0x20, 0x46, 0xfe, 0x05, |
629d688d MW |
5320 | 0xf6, 0xfe, 0x34, 0x01, 0x01, 0xfe, 0x52, 0x16, 0xfb, 0xfe, 0x48, 0xf4, |
5321 | 0x0d, 0xfe, 0x18, 0x13, 0xaf, 0xfe, 0x02, 0xea, 0xce, 0x62, 0x7a, 0xfe, | |
5322 | 0xc5, 0x13, 0x14, 0x1b, 0x37, 0x95, 0xa9, 0x5c, 0x05, 0xfe, 0x38, 0x01, | |
27c868c2 | 5323 | 0x1c, 0xfe, 0xf0, 0xff, 0x0c, 0xfe, 0x60, 0x01, 0x05, 0xfe, 0x3a, 0x01, |
629d688d MW |
5324 | 0x0c, 0xfe, 0x62, 0x01, 0x3d, 0x12, 0x20, 0x24, 0x06, 0x12, 0x2d, 0x11, |
5325 | 0x2d, 0x8a, 0x13, 0x06, 0x03, 0x23, 0x03, 0x1e, 0x4d, 0xfe, 0xf7, 0x12, | |
5326 | 0x1e, 0x94, 0xac, 0x12, 0x94, 0x07, 0x7a, 0xfe, 0x71, 0x13, 0xfe, 0x24, | |
27c868c2 | 5327 | 0x1c, 0x14, 0x1a, 0x37, 0x95, 0xa9, 0xfe, 0xd9, 0x10, 0xb6, 0xfe, 0x03, |
629d688d MW |
5328 | 0xdc, 0xfe, 0x73, 0x57, 0xfe, 0x80, 0x5d, 0x03, 0xb6, 0xfe, 0x03, 0xdc, |
5329 | 0xfe, 0x5b, 0x57, 0xfe, 0x80, 0x5d, 0x03, 0xfe, 0x03, 0x57, 0xb6, 0x23, | |
5330 | 0xfe, 0x00, 0xcc, 0x03, 0xfe, 0x03, 0x57, 0xb6, 0x75, 0x03, 0x09, 0x04, | |
27c868c2 | 5331 | 0x4c, 0xfe, 0x22, 0x13, 0xfe, 0x1c, 0x80, 0x07, 0x06, 0xfe, 0x1a, 0x13, |
629d688d MW |
5332 | 0xfe, 0x1e, 0x80, 0xe1, 0xfe, 0x1d, 0x80, 0xa4, 0xfe, 0x0c, 0x90, 0xfe, |
5333 | 0x0e, 0x13, 0xfe, 0x0e, 0x90, 0xa3, 0xfe, 0x3c, 0x90, 0xfe, 0x30, 0xf4, | |
5334 | 0x0b, 0xfe, 0x3c, 0x50, 0xa0, 0x01, 0xfe, 0x82, 0x16, 0x2f, 0x07, 0x2d, | |
27c868c2 | 5335 | 0xe0, 0x01, 0xfe, 0xbc, 0x15, 0x09, 0x04, 0x1d, 0x45, 0x01, 0xe7, 0x01, |
629d688d MW |
5336 | 0xe8, 0x11, 0xfe, 0xe9, 0x00, 0x09, 0x04, 0x4c, 0xfe, 0x2c, 0x13, 0x01, |
5337 | 0xfe, 0x14, 0x16, 0xfe, 0x1e, 0x1c, 0xfe, 0x14, 0x90, 0xfe, 0x96, 0x90, | |
5338 | 0x0c, 0xfe, 0x64, 0x01, 0x18, 0xfe, 0x66, 0x01, 0x09, 0x04, 0x4f, 0xfe, | |
27c868c2 | 5339 | 0x12, 0x12, 0xfe, 0x03, 0x80, 0x74, 0xfe, 0x01, 0xec, 0x20, 0xfe, 0x80, |
629d688d MW |
5340 | 0x40, 0x12, 0x20, 0x63, 0x27, 0x11, 0xc8, 0x59, 0x1e, 0x20, 0xed, 0x76, |
5341 | 0x20, 0x03, 0xfe, 0x08, 0x1c, 0x05, 0xfe, 0xac, 0x00, 0xfe, 0x06, 0x58, | |
5342 | 0x05, 0xfe, 0xae, 0x00, 0xfe, 0x07, 0x58, 0x05, 0xfe, 0xb0, 0x00, 0xfe, | |
27c868c2 | 5343 | 0x08, 0x58, 0x05, 0xfe, 0xb2, 0x00, 0xfe, 0x09, 0x58, 0xfe, 0x0a, 0x1c, |
629d688d MW |
5344 | 0x24, 0x69, 0x12, 0xc9, 0x23, 0x0c, 0x50, 0x0c, 0x3f, 0x13, 0x40, 0x48, |
5345 | 0x5f, 0x17, 0x1d, 0xfe, 0x90, 0x4d, 0xfe, 0x91, 0x54, 0x21, 0xfe, 0x08, | |
5346 | 0x0f, 0x3e, 0x10, 0x13, 0x42, 0x48, 0x17, 0x4c, 0xfe, 0x90, 0x4d, 0xfe, | |
27c868c2 | 5347 | 0x91, 0x54, 0x21, 0xfe, 0x1e, 0x0f, 0x24, 0x10, 0x12, 0x20, 0x78, 0x2c, |
629d688d MW |
5348 | 0x46, 0x1e, 0x20, 0xed, 0x76, 0x20, 0x11, 0xc8, 0xf6, 0xfe, 0xd6, 0xf0, |
5349 | 0xfe, 0x32, 0x0f, 0xea, 0x70, 0xfe, 0x14, 0x1c, 0xfe, 0x10, 0x1c, 0xfe, | |
5350 | 0x18, 0x1c, 0x03, 0x3c, 0xfe, 0x0c, 0x14, 0xee, 0xfe, 0x07, 0xe6, 0x1d, | |
27c868c2 | 5351 | 0xfe, 0xce, 0x47, 0xfe, 0xf5, 0x13, 0x03, 0x01, 0x86, 0x78, 0x2c, 0x46, |
629d688d MW |
5352 | 0xfa, 0xef, 0xfe, 0x42, 0x13, 0x2f, 0x07, 0x2d, 0xfe, 0x34, 0x13, 0x0a, |
5353 | 0x42, 0x01, 0x0e, 0xb0, 0xfe, 0x36, 0x12, 0xf0, 0xfe, 0x45, 0x48, 0x01, | |
5354 | 0xe3, 0xfe, 0x00, 0xcc, 0xb0, 0xfe, 0xf3, 0x13, 0x3d, 0x75, 0x07, 0x10, | |
27c868c2 | 5355 | 0xa3, 0x0a, 0x80, 0x01, 0x0e, 0xfe, 0x80, 0x5c, 0x01, 0x6f, 0xfe, 0x0e, |
629d688d MW |
5356 | 0x10, 0x07, 0x7e, 0x45, 0xf6, 0xfe, 0xd6, 0xf0, 0xfe, 0x6c, 0x0f, 0x03, |
5357 | 0xfe, 0x44, 0x58, 0x74, 0xfe, 0x01, 0xec, 0x97, 0xfe, 0x9e, 0x40, 0xfe, | |
5358 | 0x9d, 0xe7, 0x00, 0xfe, 0x9c, 0xe7, 0x1b, 0x76, 0x27, 0x01, 0xda, 0xfe, | |
27c868c2 | 5359 | 0xdd, 0x10, 0x2a, 0xbc, 0x7d, 0xbd, 0x7f, 0x30, 0x2e, 0xd5, 0x07, 0x1b, |
629d688d MW |
5360 | 0xfe, 0x48, 0x12, 0x07, 0x0b, 0xfe, 0x56, 0x12, 0x07, 0x1a, 0xfe, 0x30, |
5361 | 0x12, 0x07, 0xc2, 0x16, 0xfe, 0x3e, 0x11, 0x07, 0xfe, 0x23, 0x00, 0x16, | |
5362 | 0xfe, 0x4a, 0x11, 0x07, 0x06, 0x16, 0xfe, 0xa8, 0x11, 0x07, 0x19, 0xfe, | |
27c868c2 | 5363 | 0x12, 0x12, 0x07, 0x00, 0x16, 0x22, 0x14, 0xc2, 0x01, 0x33, 0x9f, 0x2b, |
629d688d MW |
5364 | 0x01, 0x08, 0x8c, 0x43, 0x03, 0x2b, 0xfe, 0x62, 0x08, 0x0a, 0xca, 0x01, |
5365 | 0xfe, 0x32, 0x0e, 0x11, 0x7e, 0x02, 0x29, 0x2b, 0x2f, 0x07, 0x9b, 0xfe, | |
5366 | 0xd9, 0x13, 0x79, 0x39, 0x68, 0x3a, 0x77, 0xfe, 0xfc, 0x10, 0x09, 0x04, | |
27c868c2 | 5367 | 0x6a, 0xfe, 0x72, 0x12, 0xc0, 0x38, 0xc1, 0x4e, 0xf4, 0xf5, 0x8e, 0xfe, |
629d688d MW |
5368 | 0xc6, 0x10, 0x1e, 0x58, 0xfe, 0x26, 0x13, 0x05, 0x7b, 0x31, 0x7c, 0x77, |
5369 | 0xfe, 0x82, 0x0c, 0x0c, 0x54, 0x18, 0x55, 0x23, 0x0c, 0x7b, 0x0c, 0x7c, | |
5370 | 0x01, 0xa8, 0x24, 0x69, 0x73, 0x12, 0x58, 0x01, 0xa5, 0xc0, 0x38, 0xc1, | |
27c868c2 | 5371 | 0x4e, 0xfe, 0x04, 0x55, 0xfe, 0xa5, 0x55, 0xfe, 0x04, 0xfa, 0x38, 0xfe, |
629d688d MW |
5372 | 0x05, 0xfa, 0x4e, 0xfe, 0x91, 0x10, 0x05, 0x56, 0x31, 0x57, 0xfe, 0x40, |
5373 | 0x56, 0xfe, 0xe1, 0x56, 0x0c, 0x56, 0x18, 0x57, 0x83, 0xc0, 0x38, 0xc1, | |
5374 | 0x4e, 0xf4, 0xf5, 0x05, 0x52, 0x31, 0x53, 0xfe, 0x00, 0x56, 0xfe, 0xa1, | |
27c868c2 | 5375 | 0x56, 0x0c, 0x52, 0x18, 0x53, 0x09, 0x04, 0x6a, 0xfe, 0x1e, 0x12, 0x1e, |
629d688d MW |
5376 | 0x58, 0xfe, 0x1f, 0x40, 0x05, 0x54, 0x31, 0x55, 0xfe, 0x2c, 0x50, 0xfe, |
5377 | 0xae, 0x50, 0x05, 0x56, 0x31, 0x57, 0xfe, 0x44, 0x50, 0xfe, 0xc6, 0x50, | |
5378 | 0x05, 0x52, 0x31, 0x53, 0xfe, 0x08, 0x50, 0xfe, 0x8a, 0x50, 0x05, 0x39, | |
27c868c2 | 5379 | 0x31, 0x3a, 0xfe, 0x40, 0x50, 0xfe, 0xc2, 0x50, 0x02, 0x5c, 0x24, 0x06, |
629d688d MW |
5380 | 0x12, 0xcd, 0x02, 0x5b, 0x2b, 0x01, 0x08, 0x1f, 0x44, 0x30, 0x2e, 0xd5, |
5381 | 0x07, 0x06, 0x21, 0x44, 0x2f, 0x07, 0x9b, 0x21, 0x5b, 0x01, 0x6e, 0x1c, | |
5382 | 0x3d, 0x16, 0x44, 0x09, 0x04, 0x0b, 0xe2, 0x79, 0x39, 0x68, 0x3a, 0xfe, | |
27c868c2 | 5383 | 0x0a, 0x55, 0x34, 0xfe, 0x8b, 0x55, 0xbe, 0x39, 0xbf, 0x3a, 0xfe, 0x0c, |
629d688d MW |
5384 | 0x51, 0xfe, 0x8e, 0x51, 0x02, 0x5b, 0xfe, 0x19, 0x81, 0xaf, 0xfe, 0x19, |
5385 | 0x41, 0x02, 0x5b, 0x2b, 0x01, 0x08, 0x25, 0x32, 0x1f, 0xa2, 0x30, 0x2e, | |
5386 | 0xd8, 0x4b, 0x1a, 0xfe, 0xa6, 0x12, 0x4b, 0x0b, 0x3b, 0x02, 0x44, 0x01, | |
27c868c2 | 5387 | 0x08, 0x25, 0x32, 0x1f, 0xa2, 0x30, 0x2e, 0xd6, 0x07, 0x1a, 0x21, 0x44, |
629d688d MW |
5388 | 0x01, 0x08, 0x1f, 0xa2, 0x30, 0x2e, 0xfe, 0xe8, 0x09, 0xfe, 0xc2, 0x49, |
5389 | 0x60, 0x05, 0xfe, 0x9c, 0x00, 0x28, 0x84, 0x49, 0x04, 0x19, 0x34, 0x9f, | |
5390 | 0xfe, 0xbb, 0x45, 0x4b, 0x00, 0x45, 0x3e, 0x06, 0x78, 0x3d, 0xfe, 0xda, | |
27c868c2 | 5391 | 0x14, 0x01, 0x6e, 0x87, 0xfe, 0x4b, 0x45, 0xe2, 0x2f, 0x07, 0x9a, 0xe1, |
629d688d MW |
5392 | 0x05, 0xc6, 0x28, 0x84, 0x05, 0x3f, 0x28, 0x34, 0x5e, 0x02, 0x5b, 0xfe, |
5393 | 0xc0, 0x5d, 0xfe, 0xf8, 0x14, 0xfe, 0x03, 0x17, 0x05, 0x50, 0xb4, 0x0c, | |
5394 | 0x50, 0x5e, 0x2b, 0x01, 0x08, 0x26, 0x5c, 0x01, 0xfe, 0xaa, 0x14, 0x02, | |
27c868c2 | 5395 | 0x5c, 0x01, 0x08, 0x25, 0x32, 0x1f, 0x44, 0x30, 0x2e, 0xd6, 0x07, 0x06, |
629d688d MW |
5396 | 0x21, 0x44, 0x01, 0xfe, 0x8e, 0x13, 0xfe, 0x42, 0x58, 0xfe, 0x82, 0x14, |
5397 | 0xfe, 0xa4, 0x14, 0x87, 0xfe, 0x4a, 0xf4, 0x0b, 0x16, 0x44, 0xfe, 0x4a, | |
5398 | 0xf4, 0x06, 0xfe, 0x0c, 0x12, 0x2f, 0x07, 0x9a, 0x85, 0x02, 0x5b, 0x05, | |
27c868c2 | 5399 | 0x3f, 0xb4, 0x0c, 0x3f, 0x5e, 0x2b, 0x01, 0x08, 0x26, 0x5c, 0x01, 0xfe, |
629d688d MW |
5400 | 0xd8, 0x14, 0x02, 0x5c, 0x13, 0x06, 0x65, 0xfe, 0xca, 0x12, 0x26, 0xfe, |
5401 | 0xe0, 0x12, 0x72, 0xf1, 0x01, 0x08, 0x23, 0x72, 0x03, 0x8f, 0xfe, 0xdc, | |
5402 | 0x12, 0x25, 0xfe, 0xdc, 0x12, 0x1f, 0xfe, 0xca, 0x12, 0x5e, 0x2b, 0x01, | |
27c868c2 | 5403 | 0x08, 0xfe, 0xd5, 0x10, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, |
629d688d MW |
5404 | 0x1c, 0xfe, 0xff, 0x7f, 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x03, 0x13, |
5405 | 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0x1c, 0x3d, 0xfe, 0x30, 0x56, | |
5406 | 0xfe, 0x00, 0x5c, 0x03, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, | |
27c868c2 | 5407 | 0x03, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0xfe, 0x0b, 0x58, |
629d688d MW |
5408 | 0x03, 0x0a, 0x50, 0x01, 0x82, 0x0a, 0x3f, 0x01, 0x82, 0x03, 0xfc, 0x1c, |
5409 | 0x10, 0xff, 0x03, 0x00, 0x54, 0xfe, 0x00, 0xf4, 0x19, 0x48, 0xfe, 0x00, | |
5410 | 0x7d, 0xfe, 0x01, 0x7d, 0xfe, 0x02, 0x7d, 0xfe, 0x03, 0x7c, 0x63, 0x27, | |
27c868c2 | 5411 | 0x0c, 0x52, 0x18, 0x53, 0xbe, 0x56, 0xbf, 0x57, 0x03, 0xfe, 0x62, 0x08, |
629d688d MW |
5412 | 0xfe, 0x82, 0x4a, 0xfe, 0xe1, 0x1a, 0xfe, 0x83, 0x5a, 0x74, 0x03, 0x01, |
5413 | 0xfe, 0x14, 0x18, 0xfe, 0x42, 0x48, 0x5f, 0x60, 0x89, 0x01, 0x08, 0x1f, | |
5414 | 0xfe, 0xa2, 0x14, 0x30, 0x2e, 0xd8, 0x01, 0x08, 0x1f, 0xfe, 0xa2, 0x14, | |
27c868c2 | 5415 | 0x30, 0x2e, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59, 0x05, 0xc6, 0x28, 0xfe, |
629d688d MW |
5416 | 0xcc, 0x12, 0x49, 0x04, 0x1b, 0xfe, 0xc4, 0x13, 0x23, 0x62, 0x1b, 0xe2, |
5417 | 0x4b, 0xc3, 0x64, 0xfe, 0xe8, 0x13, 0x3b, 0x13, 0x06, 0x17, 0xc3, 0x78, | |
5418 | 0xdb, 0xfe, 0x78, 0x10, 0xff, 0x02, 0x83, 0x55, 0xa1, 0xff, 0x02, 0x83, | |
27c868c2 | 5419 | 0x55, 0x62, 0x1a, 0xa4, 0xbb, 0xfe, 0x30, 0x00, 0x8e, 0xe4, 0x17, 0x2c, |
629d688d MW |
5420 | 0x13, 0x06, 0xfe, 0x56, 0x10, 0x62, 0x0b, 0xe1, 0xbb, 0xfe, 0x64, 0x00, |
5421 | 0x8e, 0xe4, 0x0a, 0xfe, 0x64, 0x00, 0x17, 0x93, 0x13, 0x06, 0xfe, 0x28, | |
5422 | 0x10, 0x62, 0x06, 0xfe, 0x60, 0x13, 0xbb, 0xfe, 0xc8, 0x00, 0x8e, 0xe4, | |
27c868c2 | 5423 | 0x0a, 0xfe, 0xc8, 0x00, 0x17, 0x4d, 0x13, 0x06, 0x83, 0xbb, 0xfe, 0x90, |
629d688d MW |
5424 | 0x01, 0xba, 0xfe, 0x4e, 0x14, 0x89, 0xfe, 0x12, 0x10, 0xfe, 0x43, 0xf4, |
5425 | 0x94, 0xfe, 0x56, 0xf0, 0xfe, 0x60, 0x14, 0xfe, 0x04, 0xf4, 0x6c, 0xfe, | |
5426 | 0x43, 0xf4, 0x93, 0xfe, 0xf3, 0x10, 0xf9, 0x01, 0xfe, 0x22, 0x13, 0x1c, | |
27c868c2 | 5427 | 0x3d, 0xfe, 0x10, 0x13, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4, 0x69, 0xba, |
629d688d MW |
5428 | 0xfe, 0x9c, 0x14, 0xb7, 0x69, 0xfe, 0x1c, 0x10, 0xfe, 0x00, 0x17, 0xfe, |
5429 | 0x4d, 0xe4, 0x19, 0xba, 0xfe, 0x9c, 0x14, 0xb7, 0x19, 0x83, 0x60, 0x23, | |
5430 | 0xfe, 0x4d, 0xf4, 0x00, 0xdf, 0x89, 0x13, 0x06, 0xfe, 0xb4, 0x56, 0xfe, | |
27c868c2 | 5431 | 0xc3, 0x58, 0x03, 0x60, 0x13, 0x0b, 0x03, 0x15, 0x06, 0x01, 0x08, 0x26, |
629d688d MW |
5432 | 0xe5, 0x15, 0x0b, 0x01, 0x08, 0x26, 0xe5, 0x15, 0x1a, 0x01, 0x08, 0x26, |
5433 | 0xe5, 0x72, 0xfe, 0x89, 0x49, 0x01, 0x08, 0x03, 0x15, 0x06, 0x01, 0x08, | |
5434 | 0x26, 0xa6, 0x15, 0x1a, 0x01, 0x08, 0x26, 0xa6, 0x15, 0x06, 0x01, 0x08, | |
27c868c2 | 5435 | 0x26, 0xa6, 0xfe, 0x89, 0x49, 0x01, 0x08, 0x26, 0xa6, 0x72, 0xfe, 0x89, |
629d688d MW |
5436 | 0x4a, 0x01, 0x08, 0x03, 0x60, 0x03, 0x1e, 0xcc, 0x07, 0x06, 0xfe, 0x44, |
5437 | 0x13, 0xad, 0x12, 0xcc, 0xfe, 0x49, 0xf4, 0x00, 0x3b, 0x72, 0x9f, 0x5e, | |
5438 | 0xfe, 0x01, 0xec, 0xfe, 0x27, 0x01, 0xf1, 0x01, 0x08, 0x2f, 0x07, 0xfe, | |
27c868c2 | 5439 | 0xe3, 0x00, 0xfe, 0x20, 0x13, 0x1f, 0xfe, 0x5a, 0x15, 0x23, 0x12, 0xcd, |
629d688d MW |
5440 | 0x01, 0x43, 0x1e, 0xcd, 0x07, 0x06, 0x45, 0x09, 0x4a, 0x06, 0x35, 0x03, |
5441 | 0x0a, 0x42, 0x01, 0x0e, 0xed, 0x88, 0x07, 0x10, 0xa4, 0x0a, 0x80, 0x01, | |
5442 | 0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03, 0x0a, 0x80, 0x01, 0x0e, 0x88, | |
27c868c2 | 5443 | 0xfe, 0x80, 0xe7, 0x10, 0x07, 0x10, 0x84, 0xfe, 0x45, 0x58, 0x01, 0xe3, |
629d688d MW |
5444 | 0x88, 0x03, 0x0a, 0x42, 0x01, 0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03, |
5445 | 0x0a, 0x42, 0x01, 0x0e, 0xfe, 0x80, 0x80, 0xf2, 0xfe, 0x49, 0xe4, 0x10, | |
5446 | 0xa4, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x0a, 0x51, 0x01, 0x82, 0x03, 0x17, | |
27c868c2 | 5447 | 0x10, 0x71, 0x66, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, |
629d688d MW |
5448 | 0xfe, 0x24, 0x1c, 0xfe, 0x1d, 0xf7, 0x1d, 0x90, 0xfe, 0xf6, 0x15, 0x01, |
5449 | 0xfe, 0xfc, 0x16, 0xe0, 0x91, 0x1d, 0x66, 0xfe, 0x2c, 0x01, 0xfe, 0x2f, | |
5450 | 0x19, 0x03, 0xae, 0x21, 0xfe, 0xe6, 0x15, 0xfe, 0xda, 0x10, 0x17, 0x10, | |
27c868c2 | 5451 | 0x71, 0x05, 0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x19, 0xfe, 0x18, 0x58, |
629d688d MW |
5452 | 0x05, 0xfe, 0x66, 0x01, 0xfe, 0x19, 0x58, 0x91, 0x19, 0xfe, 0x3c, 0x90, |
5453 | 0xfe, 0x30, 0xf4, 0x06, 0xfe, 0x3c, 0x50, 0x66, 0xfe, 0x38, 0x00, 0xfe, | |
5454 | 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0x19, 0x90, 0xfe, 0x40, 0x16, 0xfe, 0xb6, | |
27c868c2 | 5455 | 0x14, 0x34, 0x03, 0xae, 0x21, 0xfe, 0x18, 0x16, 0xfe, 0x9c, 0x10, 0x17, |
629d688d MW |
5456 | 0x10, 0x71, 0xfe, 0x83, 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, |
5457 | 0x1d, 0xf7, 0x38, 0x90, 0xfe, 0x62, 0x16, 0xfe, 0x94, 0x14, 0xfe, 0x10, | |
5458 | 0x13, 0x91, 0x38, 0x66, 0x1b, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00, | |
27c868c2 | 5459 | 0x03, 0xae, 0x21, 0xfe, 0x56, 0x16, 0xfe, 0x6c, 0x10, 0x17, 0x10, 0x71, |
629d688d MW |
5460 | 0xfe, 0x30, 0xbc, 0xfe, 0xb2, 0xbc, 0x91, 0xc5, 0x66, 0x1b, 0xfe, 0x0f, |
5461 | 0x79, 0xfe, 0x1c, 0xf7, 0xc5, 0x90, 0xfe, 0x9a, 0x16, 0xfe, 0x5c, 0x14, | |
5462 | 0x34, 0x03, 0xae, 0x21, 0xfe, 0x86, 0x16, 0xfe, 0x42, 0x10, 0xfe, 0x02, | |
27c868c2 | 5463 | 0xf6, 0x10, 0x71, 0xfe, 0x18, 0xfe, 0x54, 0xfe, 0x19, 0xfe, 0x55, 0xfc, |
629d688d MW |
5464 | 0xfe, 0x1d, 0xf7, 0x4f, 0x90, 0xfe, 0xc0, 0x16, 0xfe, 0x36, 0x14, 0xfe, |
5465 | 0x1c, 0x13, 0x91, 0x4f, 0x47, 0xfe, 0x83, 0x58, 0xfe, 0xaf, 0x19, 0xfe, | |
5466 | 0x80, 0xe7, 0x10, 0xfe, 0x81, 0xe7, 0x10, 0x11, 0xfe, 0xdd, 0x00, 0x63, | |
27c868c2 | 5467 | 0x27, 0x03, 0x63, 0x27, 0xfe, 0x12, 0x45, 0x21, 0xfe, 0xb0, 0x16, 0x14, |
629d688d MW |
5468 | 0x06, 0x37, 0x95, 0xa9, 0x02, 0x29, 0xfe, 0x39, 0xf0, 0xfe, 0x04, 0x17, |
5469 | 0x23, 0x03, 0xfe, 0x7e, 0x18, 0x1c, 0x1a, 0x5d, 0x13, 0x0d, 0x03, 0x71, | |
5470 | 0x05, 0xcb, 0x1c, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10, 0x78, 0x2c, | |
27c868c2 | 5471 | 0x46, 0x2f, 0x07, 0x2d, 0xfe, 0x3c, 0x13, 0xfe, 0x82, 0x14, 0xfe, 0x42, |
629d688d MW |
5472 | 0x13, 0x3c, 0x8a, 0x0a, 0x42, 0x01, 0x0e, 0xb0, 0xfe, 0x3e, 0x12, 0xf0, |
5473 | 0xfe, 0x45, 0x48, 0x01, 0xe3, 0xfe, 0x00, 0xcc, 0xb0, 0xfe, 0xf3, 0x13, | |
5474 | 0x3d, 0x75, 0x07, 0x10, 0xa3, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x01, 0x6f, | |
27c868c2 | 5475 | 0xfe, 0x16, 0x10, 0x07, 0x7e, 0x85, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12, |
629d688d MW |
5476 | 0xf6, 0xfe, 0xd6, 0xf0, 0xfe, 0x24, 0x17, 0x17, 0x0b, 0x03, 0xfe, 0x9c, |
5477 | 0xe7, 0x0b, 0x0f, 0xfe, 0x15, 0x00, 0x59, 0x76, 0x27, 0x01, 0xda, 0x17, | |
5478 | 0x06, 0x03, 0x3c, 0x8a, 0x09, 0x4a, 0x1d, 0x35, 0x11, 0x2d, 0x01, 0x6f, | |
27c868c2 | 5479 | 0x17, 0x06, 0x03, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x79, 0xc7, 0x68, |
629d688d MW |
5480 | 0xc8, 0xfe, 0x48, 0x55, 0x34, 0xfe, 0xc9, 0x55, 0x03, 0x1e, 0x98, 0x73, |
5481 | 0x12, 0x98, 0x03, 0x0a, 0x99, 0x01, 0x0e, 0xf0, 0x0a, 0x40, 0x01, 0x0e, | |
5482 | 0xfe, 0x49, 0x44, 0x16, 0xfe, 0xf0, 0x17, 0x73, 0x75, 0x03, 0x0a, 0x42, | |
27c868c2 | 5483 | 0x01, 0x0e, 0x07, 0x10, 0x45, 0x0a, 0x51, 0x01, 0x9e, 0x0a, 0x40, 0x01, |
629d688d MW |
5484 | 0x0e, 0x73, 0x75, 0x03, 0xfe, 0x4e, 0xe4, 0x1a, 0x64, 0xfe, 0x24, 0x18, |
5485 | 0x05, 0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0x5b, 0xfe, 0x4e, 0xe4, 0xc2, | |
5486 | 0x64, 0xfe, 0x36, 0x18, 0x05, 0xfe, 0x92, 0x00, 0xfe, 0x02, 0xe6, 0x1b, | |
27c868c2 | 5487 | 0xdc, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x64, 0xfe, 0x48, 0x18, 0x05, |
629d688d MW |
5488 | 0xfe, 0x94, 0x00, 0xfe, 0x02, 0xe6, 0x19, 0xfe, 0x08, 0x10, 0x05, 0xfe, |
5489 | 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x2c, 0xfe, 0x4e, 0x45, 0xfe, 0x0c, 0x12, | |
5490 | 0xaf, 0xff, 0x04, 0x68, 0x54, 0xde, 0x1c, 0x69, 0x03, 0x07, 0x7a, 0xfe, | |
27c868c2 | 5491 | 0x5a, 0xf0, 0xfe, 0x74, 0x18, 0x24, 0xfe, 0x09, 0x00, 0xfe, 0x34, 0x10, |
629d688d MW |
5492 | 0x07, 0x1b, 0xfe, 0x5a, 0xf0, 0xfe, 0x82, 0x18, 0x24, 0xc3, 0xfe, 0x26, |
5493 | 0x10, 0x07, 0x1a, 0x5d, 0x24, 0x2c, 0xdc, 0x07, 0x0b, 0x5d, 0x24, 0x93, | |
5494 | 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x5d, 0x24, 0x4d, 0x9f, 0xad, 0x03, 0x14, | |
27c868c2 | 5495 | 0xfe, 0x09, 0x00, 0x01, 0x33, 0xfe, 0x04, 0xfe, 0x7d, 0x05, 0x7f, 0xf9, |
629d688d MW |
5496 | 0x03, 0x25, 0xfe, 0xca, 0x18, 0xfe, 0x14, 0xf0, 0x08, 0x65, 0xfe, 0xc6, |
5497 | 0x18, 0x03, 0xff, 0x1a, 0x00, 0x00, | |
1da177e4 LT |
5498 | }; |
5499 | ||
27c868c2 MW |
5500 | static unsigned short _adv_asc3550_size = sizeof(_adv_asc3550_buf); /* 0x13AD */ |
5501 | static ADV_DCNT _adv_asc3550_chksum = 0x04D52DDDUL; /* Expanded little-endian checksum. */ | |
1da177e4 LT |
5502 | |
5503 | /* Microcode buffer is kept after initialization for error recovery. */ | |
27c868c2 MW |
5504 | static unsigned char _adv_asc38C0800_buf[] = { |
5505 | 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0xfc, 0x00, 0x16, 0x18, 0xe4, | |
629d688d MW |
5506 | 0x01, 0x00, 0x48, 0xe4, 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00, 0xce, 0x19, |
5507 | 0x00, 0xfa, 0xff, 0xff, 0x1c, 0x0f, 0x00, 0xf6, 0x9e, 0xe7, 0xff, 0x00, | |
5508 | 0x82, 0xe7, 0x00, 0xea, 0x01, 0xfa, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0, | |
27c868c2 | 5509 | 0x01, 0xf6, 0x03, 0x00, 0x04, 0x00, 0x10, 0x00, 0x1e, 0xf0, 0x85, 0xf0, |
629d688d MW |
5510 | 0x18, 0xf4, 0x08, 0x00, 0xbc, 0x00, 0x38, 0x54, 0x00, 0xec, 0xd5, 0xf0, |
5511 | 0x82, 0x0d, 0x00, 0xe6, 0x86, 0xf0, 0xb1, 0xf0, 0x98, 0x57, 0x01, 0xfc, | |
5512 | 0xb4, 0x00, 0xd4, 0x01, 0x0c, 0x1c, 0x3e, 0x1c, 0x3c, 0x00, 0xbb, 0x00, | |
27c868c2 | 5513 | 0x00, 0x10, 0xba, 0x19, 0x02, 0x80, 0x32, 0xf0, 0x7c, 0x0d, 0x02, 0x13, |
629d688d MW |
5514 | 0xba, 0x13, 0x18, 0x40, 0x00, 0x57, 0x01, 0xea, 0x02, 0xfc, 0x03, 0xfc, |
5515 | 0x3e, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x74, 0x01, 0x76, 0x01, 0xb9, 0x54, | |
5516 | 0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00, 0xc0, 0x00, 0x01, 0x01, | |
27c868c2 | 5517 | 0x3e, 0x01, 0x7a, 0x01, 0xca, 0x08, 0xce, 0x10, 0x16, 0x11, 0x04, 0x12, |
629d688d MW |
5518 | 0x08, 0x12, 0x02, 0x4a, 0xbb, 0x55, 0x3c, 0x56, 0x03, 0x58, 0x1b, 0x80, |
5519 | 0x30, 0xe4, 0x4b, 0xe4, 0x5d, 0xf0, 0x02, 0xfa, 0x20, 0x00, 0x32, 0x00, | |
5520 | 0x40, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01, | |
27c868c2 | 5521 | 0x70, 0x01, 0x72, 0x01, 0x78, 0x01, 0x7c, 0x01, 0x62, 0x0a, 0x86, 0x0d, |
629d688d MW |
5522 | 0x06, 0x13, 0x4c, 0x1c, 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0, |
5523 | 0x03, 0xf7, 0x0c, 0x00, 0x0f, 0x00, 0x47, 0x00, 0xbe, 0x00, 0x00, 0x01, | |
5524 | 0x20, 0x11, 0x5c, 0x16, 0x32, 0x1c, 0x38, 0x1c, 0x4e, 0x1c, 0x10, 0x44, | |
27c868c2 | 5525 | 0x00, 0x4c, 0x04, 0xea, 0x5c, 0xf0, 0xa7, 0xf0, 0x04, 0xf6, 0x03, 0xfa, |
629d688d MW |
5526 | 0x05, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00, 0xcc, 0x00, 0x20, 0x01, |
5527 | 0x4e, 0x01, 0x4a, 0x0b, 0x42, 0x0c, 0x12, 0x0f, 0x0c, 0x10, 0x22, 0x11, | |
5528 | 0x0a, 0x12, 0x04, 0x13, 0x30, 0x1c, 0x02, 0x48, 0x00, 0x4e, 0x42, 0x54, | |
27c868c2 | 5529 | 0x44, 0x55, 0xbd, 0x56, 0x06, 0x83, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0, |
629d688d MW |
5530 | 0x59, 0xf0, 0xb8, 0xf0, 0x4b, 0xf4, 0x06, 0xf7, 0x0e, 0xf7, 0x04, 0xfc, |
5531 | 0x05, 0xfc, 0x06, 0x00, 0x19, 0x00, 0x33, 0x00, 0x9b, 0x00, 0xa4, 0x00, | |
5532 | 0xb5, 0x00, 0xba, 0x00, 0xd0, 0x00, 0xe1, 0x00, 0xe7, 0x00, 0xe2, 0x03, | |
27c868c2 | 5533 | 0x08, 0x0f, 0x02, 0x10, 0x04, 0x10, 0x0a, 0x10, 0x0a, 0x13, 0x0c, 0x13, |
629d688d MW |
5534 | 0x12, 0x13, 0x24, 0x14, 0x34, 0x14, 0x04, 0x16, 0x08, 0x16, 0xa4, 0x17, |
5535 | 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c, 0x08, 0x44, 0x38, 0x44, 0x91, 0x44, | |
5536 | 0x0a, 0x45, 0x48, 0x46, 0x01, 0x48, 0x68, 0x54, 0x3a, 0x55, 0x83, 0x55, | |
27c868c2 | 5537 | 0xe5, 0x55, 0xb0, 0x57, 0x01, 0x58, 0x83, 0x59, 0x05, 0xe6, 0x0b, 0xf0, |
629d688d MW |
5538 | 0x0c, 0xf0, 0x04, 0xf8, 0x05, 0xf8, 0x07, 0x00, 0x0a, 0x00, 0x1c, 0x00, |
5539 | 0x1e, 0x00, 0x9e, 0x00, 0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00, | |
5540 | 0x22, 0x01, 0x26, 0x01, 0x79, 0x01, 0x7e, 0x01, 0xc4, 0x01, 0xc6, 0x01, | |
27c868c2 | 5541 | 0x80, 0x02, 0x5e, 0x03, 0xee, 0x04, 0x9a, 0x06, 0xf8, 0x07, 0x62, 0x08, |
629d688d MW |
5542 | 0x68, 0x08, 0x69, 0x08, 0xd6, 0x08, 0xe9, 0x09, 0xfa, 0x0b, 0x2e, 0x0f, |
5543 | 0x12, 0x10, 0x1a, 0x10, 0xed, 0x10, 0xf1, 0x10, 0x2a, 0x11, 0x06, 0x12, | |
5544 | 0x0c, 0x12, 0x3e, 0x12, 0x10, 0x13, 0x16, 0x13, 0x1e, 0x13, 0x46, 0x14, | |
27c868c2 | 5545 | 0x76, 0x14, 0x82, 0x14, 0x36, 0x15, 0xca, 0x15, 0x6b, 0x18, 0xbe, 0x18, |
629d688d MW |
5546 | 0xca, 0x18, 0xe6, 0x19, 0x12, 0x1c, 0x46, 0x1c, 0x9c, 0x32, 0x00, 0x40, |
5547 | 0x0e, 0x47, 0xfe, 0x9c, 0xf0, 0x2b, 0x02, 0xfe, 0xac, 0x0d, 0xff, 0x10, | |
5548 | 0x00, 0x00, 0xd7, 0xfe, 0xe8, 0x19, 0x00, 0xd6, 0xfe, 0x84, 0x01, 0xff, | |
27c868c2 | 5549 | 0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00, |
629d688d MW |
5550 | 0x00, 0xfe, 0x57, 0x24, 0x00, 0xfe, 0x4c, 0x00, 0x5b, 0xff, 0x04, 0x00, |
5551 | 0x00, 0x11, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08, 0x01, 0x01, 0xff, 0x08, | |
5552 | 0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x11, | |
27c868c2 | 5553 | 0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00, |
629d688d MW |
5554 | 0xfe, 0x04, 0xf7, 0xd6, 0x2c, 0x99, 0x0a, 0x01, 0xfe, 0xc2, 0x0f, 0xfe, |
5555 | 0x04, 0xf7, 0xd6, 0x99, 0x0a, 0x42, 0x2c, 0xfe, 0x3d, 0xf0, 0xfe, 0x06, | |
5556 | 0x02, 0xfe, 0x20, 0xf0, 0xa7, 0xfe, 0x91, 0xf0, 0xfe, 0xf4, 0x01, 0xfe, | |
27c868c2 | 5557 | 0x90, 0xf0, 0xfe, 0xf4, 0x01, 0xfe, 0x8f, 0xf0, 0xa7, 0x03, 0x5d, 0x4d, |
629d688d MW |
5558 | 0x02, 0xfe, 0xc8, 0x0d, 0x01, 0xfe, 0x38, 0x0e, 0xfe, 0xdd, 0x12, 0xfe, |
5559 | 0xfc, 0x10, 0xfe, 0x28, 0x1c, 0x03, 0xfe, 0xa6, 0x00, 0xfe, 0xd3, 0x12, | |
5560 | 0x41, 0x14, 0xfe, 0xa6, 0x00, 0xc2, 0xfe, 0x48, 0xf0, 0xfe, 0x8a, 0x02, | |
27c868c2 | 5561 | 0xfe, 0x49, 0xf0, 0xfe, 0xa4, 0x02, 0xfe, 0x4a, 0xf0, 0xfe, 0xc2, 0x02, |
629d688d MW |
5562 | 0xfe, 0x46, 0xf0, 0xfe, 0x54, 0x02, 0xfe, 0x47, 0xf0, 0xfe, 0x5a, 0x02, |
5563 | 0xfe, 0x43, 0xf0, 0xfe, 0x48, 0x02, 0xfe, 0x44, 0xf0, 0xfe, 0x4c, 0x02, | |
5564 | 0xfe, 0x45, 0xf0, 0xfe, 0x50, 0x02, 0x18, 0x0a, 0xaa, 0x18, 0x06, 0x14, | |
27c868c2 | 5565 | 0xa1, 0x02, 0x2b, 0xfe, 0x00, 0x1c, 0xe7, 0xfe, 0x02, 0x1c, 0xe6, 0xfe, |
629d688d MW |
5566 | 0x1e, 0x1c, 0xfe, 0xe9, 0x10, 0x01, 0xfe, 0x18, 0x18, 0xfe, 0xe7, 0x10, |
5567 | 0xfe, 0x06, 0xfc, 0xce, 0x09, 0x70, 0x01, 0xa8, 0x02, 0x2b, 0x15, 0x59, | |
5568 | 0x39, 0xa2, 0x01, 0xfe, 0x58, 0x10, 0x09, 0x70, 0x01, 0x87, 0xfe, 0xbd, | |
27c868c2 | 5569 | 0x10, 0x09, 0x70, 0x01, 0x87, 0xfe, 0xad, 0x10, 0xfe, 0x16, 0x1c, 0xfe, |
629d688d MW |
5570 | 0x58, 0x1c, 0x18, 0x06, 0x14, 0xa1, 0x2c, 0x1c, 0x2b, 0xfe, 0x3d, 0xf0, |
5571 | 0xfe, 0x06, 0x02, 0x23, 0xfe, 0x98, 0x02, 0xfe, 0x5a, 0x1c, 0xf8, 0xfe, | |
5572 | 0x14, 0x1c, 0x15, 0xfe, 0x30, 0x00, 0x39, 0xa2, 0x01, 0xfe, 0x48, 0x10, | |
27c868c2 | 5573 | 0x18, 0x06, 0x14, 0xa1, 0x02, 0xd7, 0x22, 0x20, 0x07, 0x11, 0x35, 0xfe, |
629d688d MW |
5574 | 0x69, 0x10, 0x18, 0x06, 0x14, 0xa1, 0xfe, 0x04, 0xec, 0x20, 0x4f, 0x43, |
5575 | 0x13, 0x20, 0xfe, 0x05, 0xf6, 0xce, 0x01, 0xfe, 0x4a, 0x17, 0x08, 0x54, | |
5576 | 0x58, 0x37, 0x12, 0x2f, 0x42, 0x92, 0x01, 0xfe, 0x82, 0x16, 0x02, 0x2b, | |
27c868c2 | 5577 | 0x09, 0x46, 0x01, 0x0e, 0x07, 0x00, 0x66, 0x01, 0x73, 0xfe, 0x18, 0x10, |
629d688d MW |
5578 | 0xfe, 0x41, 0x58, 0x09, 0xa4, 0x01, 0x0e, 0xfe, 0xc8, 0x54, 0x6b, 0xfe, |
5579 | 0x10, 0x03, 0x01, 0xfe, 0x82, 0x16, 0x02, 0x2b, 0x2c, 0x4f, 0xfe, 0x02, | |
5580 | 0xe8, 0x2a, 0xfe, 0xbf, 0x57, 0xfe, 0x9e, 0x43, 0xfe, 0x77, 0x57, 0xfe, | |
27c868c2 | 5581 | 0x27, 0xf0, 0xfe, 0xe0, 0x01, 0xfe, 0x07, 0x4b, 0xfe, 0x20, 0xf0, 0xa7, |
629d688d MW |
5582 | 0xfe, 0x40, 0x1c, 0x1c, 0xd9, 0xfe, 0x26, 0xf0, 0xfe, 0x5a, 0x03, 0xfe, |
5583 | 0xa0, 0xf0, 0xfe, 0x48, 0x03, 0xfe, 0x11, 0xf0, 0xa7, 0xfe, 0xef, 0x10, | |
5584 | 0xfe, 0x9f, 0xf0, 0xfe, 0x68, 0x03, 0xf9, 0x10, 0xfe, 0x11, 0x00, 0x02, | |
27c868c2 | 5585 | 0x65, 0x2c, 0xfe, 0x48, 0x1c, 0xf9, 0x08, 0x05, 0x1b, 0xfe, 0x18, 0x13, |
629d688d MW |
5586 | 0x21, 0x22, 0xa3, 0xb7, 0x13, 0xa3, 0x09, 0x46, 0x01, 0x0e, 0xb7, 0x78, |
5587 | 0x01, 0xfe, 0xb4, 0x16, 0x12, 0xd1, 0x1c, 0xd9, 0xfe, 0x01, 0xf0, 0xd9, | |
5588 | 0xfe, 0x82, 0xf0, 0xfe, 0x96, 0x03, 0xfa, 0x12, 0xfe, 0xe4, 0x00, 0x27, | |
27c868c2 | 5589 | 0xfe, 0xa8, 0x03, 0x1c, 0x34, 0x1d, 0xfe, 0xb8, 0x03, 0x01, 0x4b, 0xfe, |
629d688d MW |
5590 | 0x06, 0xf0, 0xfe, 0xc8, 0x03, 0x95, 0x86, 0xfe, 0x0a, 0xf0, 0xfe, 0x8a, |
5591 | 0x06, 0x02, 0x24, 0x03, 0x70, 0x28, 0x17, 0xfe, 0xfa, 0x04, 0x15, 0x6d, | |
5592 | 0x01, 0x36, 0x7b, 0xfe, 0x6a, 0x02, 0x02, 0xd8, 0xf9, 0x2c, 0x99, 0x19, | |
27c868c2 | 5593 | 0xfe, 0x67, 0x1b, 0xfe, 0xbf, 0x57, 0xfe, 0x77, 0x57, 0xfe, 0x48, 0x1c, |
629d688d MW |
5594 | 0x74, 0x01, 0xaf, 0x8c, 0x09, 0x46, 0x01, 0x0e, 0x07, 0x00, 0x17, 0xda, |
5595 | 0x09, 0xd1, 0x01, 0x0e, 0x8d, 0x51, 0x64, 0x79, 0x2a, 0x03, 0x70, 0x28, | |
5596 | 0xfe, 0x10, 0x12, 0x15, 0x6d, 0x01, 0x36, 0x7b, 0xfe, 0x6a, 0x02, 0x02, | |
27c868c2 | 5597 | 0xd8, 0xc7, 0x81, 0xc8, 0x83, 0x1c, 0x24, 0x27, 0xfe, 0x40, 0x04, 0x1d, |
629d688d MW |
5598 | 0xfe, 0x3c, 0x04, 0x3b, 0xfe, 0xa0, 0x00, 0xfe, 0x9b, 0x57, 0xfe, 0x4e, |
5599 | 0x12, 0x2d, 0xff, 0x02, 0x00, 0x10, 0x01, 0x0b, 0x1d, 0xfe, 0xe4, 0x04, | |
5600 | 0x2d, 0x01, 0x0b, 0x1d, 0x24, 0x33, 0x31, 0xde, 0xfe, 0x4c, 0x44, 0xfe, | |
27c868c2 | 5601 | 0x4c, 0x12, 0x51, 0xfe, 0x44, 0x48, 0x0f, 0x6f, 0xfe, 0x4c, 0x54, 0x6b, |
629d688d MW |
5602 | 0xda, 0x4f, 0x79, 0x2a, 0xfe, 0x06, 0x80, 0xfe, 0x48, 0x47, 0xfe, 0x62, |
5603 | 0x13, 0x08, 0x05, 0x1b, 0xfe, 0x2a, 0x13, 0x32, 0x07, 0x82, 0xfe, 0x52, | |
5604 | 0x13, 0xfe, 0x20, 0x10, 0x0f, 0x6f, 0xfe, 0x4c, 0x54, 0x6b, 0xda, 0xfe, | |
27c868c2 | 5605 | 0x06, 0x80, 0xfe, 0x48, 0x47, 0xfe, 0x40, 0x13, 0x08, 0x05, 0x1b, 0xfe, |
629d688d MW |
5606 | 0x08, 0x13, 0x32, 0x07, 0x82, 0xfe, 0x30, 0x13, 0x08, 0x05, 0x1b, 0xfe, |
5607 | 0x1c, 0x12, 0x15, 0x9d, 0x08, 0x05, 0x06, 0x4d, 0x15, 0xfe, 0x0d, 0x00, | |
5608 | 0x01, 0x36, 0x7b, 0xfe, 0x64, 0x0d, 0x02, 0x24, 0x2d, 0x12, 0xfe, 0xe6, | |
27c868c2 | 5609 | 0x00, 0xfe, 0x1c, 0x90, 0xfe, 0x40, 0x5c, 0x04, 0x15, 0x9d, 0x01, 0x36, |
629d688d MW |
5610 | 0x02, 0x2b, 0xfe, 0x42, 0x5b, 0x99, 0x19, 0xfe, 0x46, 0x59, 0xfe, 0xbf, |
5611 | 0x57, 0xfe, 0x77, 0x57, 0xfe, 0x87, 0x80, 0xfe, 0x31, 0xe4, 0x5b, 0x08, | |
5612 | 0x05, 0x0a, 0xfe, 0x84, 0x13, 0xfe, 0x20, 0x80, 0x07, 0x19, 0xfe, 0x7c, | |
27c868c2 | 5613 | 0x12, 0x53, 0x05, 0x06, 0xfe, 0x6c, 0x13, 0x03, 0xfe, 0xa2, 0x00, 0x28, |
629d688d MW |
5614 | 0x17, 0xfe, 0x90, 0x05, 0xfe, 0x31, 0xe4, 0x5a, 0x53, 0x05, 0x0a, 0xfe, |
5615 | 0x56, 0x13, 0x03, 0xfe, 0xa0, 0x00, 0x28, 0xfe, 0x4e, 0x12, 0x67, 0xff, | |
5616 | 0x02, 0x00, 0x10, 0x27, 0xfe, 0x48, 0x05, 0x1c, 0x34, 0xfe, 0x89, 0x48, | |
27c868c2 | 5617 | 0xff, 0x02, 0x00, 0x10, 0x27, 0xfe, 0x56, 0x05, 0x26, 0xfe, 0xa8, 0x05, |
629d688d MW |
5618 | 0x12, 0xfe, 0xe3, 0x00, 0x21, 0x53, 0xfe, 0x4a, 0xf0, 0xfe, 0x76, 0x05, |
5619 | 0xfe, 0x49, 0xf0, 0xfe, 0x70, 0x05, 0x88, 0x25, 0xfe, 0x21, 0x00, 0xab, | |
5620 | 0x25, 0xfe, 0x22, 0x00, 0xaa, 0x25, 0x58, 0xfe, 0x09, 0x48, 0xff, 0x02, | |
27c868c2 | 5621 | 0x00, 0x10, 0x27, 0xfe, 0x86, 0x05, 0x26, 0xfe, 0xa8, 0x05, 0xfe, 0xe2, |
629d688d MW |
5622 | 0x08, 0x53, 0x05, 0xcb, 0x4d, 0x01, 0xb0, 0x25, 0x06, 0x13, 0xd3, 0x39, |
5623 | 0xfe, 0x27, 0x01, 0x08, 0x05, 0x1b, 0xfe, 0x22, 0x12, 0x41, 0x01, 0xb2, | |
5624 | 0x15, 0x9d, 0x08, 0x05, 0x06, 0x4d, 0x15, 0xfe, 0x0d, 0x00, 0x01, 0x36, | |
27c868c2 | 5625 | 0x7b, 0xfe, 0x64, 0x0d, 0x02, 0x24, 0x03, 0xfe, 0x9c, 0x00, 0x28, 0xeb, |
629d688d MW |
5626 | 0x03, 0x5c, 0x28, 0xfe, 0x36, 0x13, 0x41, 0x01, 0xb2, 0x26, 0xfe, 0x18, |
5627 | 0x06, 0x09, 0x06, 0x53, 0x05, 0x1f, 0xfe, 0x02, 0x12, 0x50, 0x01, 0xfe, | |
5628 | 0x9e, 0x15, 0x1d, 0xfe, 0x0e, 0x06, 0x12, 0xa5, 0x01, 0x4b, 0x12, 0xfe, | |
27c868c2 | 5629 | 0xe5, 0x00, 0x03, 0x5c, 0xc1, 0x0c, 0x5c, 0x03, 0xcd, 0x28, 0xfe, 0x62, |
629d688d MW |
5630 | 0x12, 0x03, 0x45, 0x28, 0xfe, 0x5a, 0x13, 0x01, 0xfe, 0x0c, 0x19, 0x01, |
5631 | 0xfe, 0x76, 0x19, 0xfe, 0x43, 0x48, 0xc4, 0xcc, 0x0f, 0x71, 0xff, 0x02, | |
5632 | 0x00, 0x57, 0x52, 0x93, 0x1e, 0x43, 0x8b, 0xc4, 0x6e, 0x41, 0x01, 0xb2, | |
27c868c2 | 5633 | 0x26, 0xfe, 0x82, 0x06, 0x53, 0x05, 0x1a, 0xe9, 0x91, 0x09, 0x59, 0x01, |
629d688d MW |
5634 | 0xfe, 0xcc, 0x15, 0x1d, 0xfe, 0x78, 0x06, 0x12, 0xa5, 0x01, 0x4b, 0x12, |
5635 | 0xfe, 0xe5, 0x00, 0x03, 0x45, 0xc1, 0x0c, 0x45, 0x18, 0x06, 0x01, 0xb2, | |
5636 | 0xfa, 0x76, 0x74, 0x01, 0xaf, 0x8c, 0x12, 0xfe, 0xe2, 0x00, 0x27, 0xdb, | |
27c868c2 | 5637 | 0x1c, 0x34, 0xfe, 0x0a, 0xf0, 0xfe, 0xb6, 0x06, 0x94, 0xfe, 0x6c, 0x07, |
629d688d MW |
5638 | 0xfe, 0x06, 0xf0, 0xfe, 0x74, 0x07, 0x95, 0x86, 0x02, 0x24, 0x08, 0x05, |
5639 | 0x0a, 0xfe, 0x2e, 0x12, 0x16, 0x19, 0x01, 0x0b, 0x16, 0x00, 0x01, 0x0b, | |
5640 | 0x16, 0x00, 0x01, 0x0b, 0x16, 0x00, 0x01, 0x0b, 0xfe, 0x99, 0xa4, 0x01, | |
27c868c2 | 5641 | 0x0b, 0x16, 0x00, 0x02, 0xfe, 0x42, 0x08, 0x68, 0x05, 0x1a, 0xfe, 0x38, |
629d688d MW |
5642 | 0x12, 0x08, 0x05, 0x1a, 0xfe, 0x30, 0x13, 0x16, 0xfe, 0x1b, 0x00, 0x01, |
5643 | 0x0b, 0x16, 0x00, 0x01, 0x0b, 0x16, 0x00, 0x01, 0x0b, 0x16, 0x00, 0x01, | |
5644 | 0x0b, 0x16, 0x06, 0x01, 0x0b, 0x16, 0x00, 0x02, 0xe2, 0x6c, 0x58, 0xbe, | |
27c868c2 | 5645 | 0x50, 0xfe, 0x9a, 0x81, 0x55, 0x1b, 0x7a, 0xfe, 0x42, 0x07, 0x09, 0x1b, |
629d688d MW |
5646 | 0xfe, 0x09, 0x6f, 0xba, 0xfe, 0xca, 0x45, 0xfe, 0x32, 0x12, 0x69, 0x6d, |
5647 | 0x8b, 0x6c, 0x7f, 0x27, 0xfe, 0x54, 0x07, 0x1c, 0x34, 0xfe, 0x0a, 0xf0, | |
5648 | 0xfe, 0x42, 0x07, 0x95, 0x86, 0x94, 0xfe, 0x6c, 0x07, 0x02, 0x24, 0x01, | |
27c868c2 | 5649 | 0x4b, 0x02, 0xdb, 0x16, 0x1f, 0x02, 0xdb, 0xfe, 0x9c, 0xf7, 0xdc, 0xfe, |
629d688d MW |
5650 | 0x2c, 0x90, 0xfe, 0xae, 0x90, 0x56, 0xfe, 0xda, 0x07, 0x0c, 0x60, 0x14, |
5651 | 0x61, 0x08, 0x54, 0x5a, 0x37, 0x22, 0x20, 0x07, 0x11, 0xfe, 0x0e, 0x12, | |
5652 | 0x8d, 0xfe, 0x80, 0x80, 0x39, 0x20, 0x6a, 0x2a, 0xfe, 0x06, 0x10, 0xfe, | |
27c868c2 | 5653 | 0x83, 0xe7, 0xfe, 0x48, 0x00, 0xab, 0xfe, 0x03, 0x40, 0x08, 0x54, 0x5b, |
629d688d MW |
5654 | 0x37, 0x01, 0xb3, 0xb8, 0xfe, 0x1f, 0x40, 0x13, 0x62, 0x01, 0xef, 0xfe, |
5655 | 0x08, 0x50, 0xfe, 0x8a, 0x50, 0xfe, 0x44, 0x51, 0xfe, 0xc6, 0x51, 0x88, | |
5656 | 0xfe, 0x08, 0x90, 0xfe, 0x8a, 0x90, 0x0c, 0x5e, 0x14, 0x5f, 0xfe, 0x0c, | |
27c868c2 | 5657 | 0x90, 0xfe, 0x8e, 0x90, 0xfe, 0x40, 0x50, 0xfe, 0xc2, 0x50, 0x0c, 0x3d, |
629d688d MW |
5658 | 0x14, 0x3e, 0xfe, 0x4a, 0x10, 0x08, 0x05, 0x5a, 0xfe, 0x2a, 0x12, 0xfe, |
5659 | 0x2c, 0x90, 0xfe, 0xae, 0x90, 0x0c, 0x60, 0x14, 0x61, 0x08, 0x05, 0x5b, | |
5660 | 0x8b, 0x01, 0xb3, 0xfe, 0x1f, 0x80, 0x13, 0x62, 0xfe, 0x44, 0x90, 0xfe, | |
27c868c2 | 5661 | 0xc6, 0x90, 0x0c, 0x3f, 0x14, 0x40, 0xfe, 0x08, 0x90, 0xfe, 0x8a, 0x90, |
629d688d MW |
5662 | 0x0c, 0x5e, 0x14, 0x5f, 0xfe, 0x40, 0x90, 0xfe, 0xc2, 0x90, 0x0c, 0x3d, |
5663 | 0x14, 0x3e, 0x0c, 0x2e, 0x14, 0x3c, 0x21, 0x0c, 0x49, 0x0c, 0x63, 0x08, | |
5664 | 0x54, 0x1f, 0x37, 0x2c, 0x0f, 0xfe, 0x4e, 0x11, 0x27, 0xdd, 0xfe, 0x9e, | |
27c868c2 | 5665 | 0xf0, 0xfe, 0x76, 0x08, 0xbc, 0x17, 0x34, 0x2c, 0x77, 0xe6, 0xc5, 0xfe, |
629d688d MW |
5666 | 0x9a, 0x08, 0xc6, 0xfe, 0xb8, 0x08, 0x94, 0xfe, 0x8e, 0x08, 0xfe, 0x06, |
5667 | 0xf0, 0xfe, 0x94, 0x08, 0x95, 0x86, 0x02, 0x24, 0x01, 0x4b, 0xfe, 0xc9, | |
5668 | 0x10, 0x16, 0x1f, 0xfe, 0xc9, 0x10, 0x68, 0x05, 0x06, 0xfe, 0x10, 0x12, | |
27c868c2 | 5669 | 0x68, 0x05, 0x0a, 0x4e, 0x08, 0x05, 0x0a, 0xfe, 0x90, 0x12, 0xfe, 0x2e, |
629d688d MW |
5670 | 0x1c, 0x02, 0xfe, 0x18, 0x0b, 0x68, 0x05, 0x06, 0x4e, 0x68, 0x05, 0x0a, |
5671 | 0xfe, 0x7a, 0x12, 0xfe, 0x2c, 0x1c, 0xfe, 0xaa, 0xf0, 0xfe, 0xd2, 0x09, | |
5672 | 0xfe, 0xac, 0xf0, 0xfe, 0x00, 0x09, 0x02, 0xfe, 0xde, 0x09, 0xfe, 0xb7, | |
27c868c2 | 5673 | 0xf0, 0xfe, 0xfc, 0x08, 0xfe, 0x02, 0xf6, 0x1a, 0x50, 0xfe, 0x70, 0x18, |
629d688d MW |
5674 | 0xfe, 0xf1, 0x18, 0xfe, 0x40, 0x55, 0xfe, 0xe1, 0x55, 0xfe, 0x10, 0x58, |
5675 | 0xfe, 0x91, 0x58, 0xfe, 0x14, 0x59, 0xfe, 0x95, 0x59, 0x1c, 0x85, 0xfe, | |
5676 | 0x8c, 0xf0, 0xfe, 0xfc, 0x08, 0xfe, 0xac, 0xf0, 0xfe, 0xf0, 0x08, 0xb5, | |
27c868c2 | 5677 | 0xfe, 0xcb, 0x10, 0xfe, 0xad, 0xf0, 0xfe, 0x0c, 0x09, 0x02, 0xfe, 0x18, |
629d688d MW |
5678 | 0x0b, 0xb6, 0xfe, 0xbf, 0x10, 0xfe, 0x2b, 0xf0, 0x85, 0xf4, 0x1e, 0xfe, |
5679 | 0x00, 0xfe, 0xfe, 0x1c, 0x12, 0xc2, 0xfe, 0xd2, 0xf0, 0x85, 0xfe, 0x76, | |
5680 | 0x18, 0x1e, 0x19, 0x17, 0x85, 0x03, 0xd2, 0x1e, 0x06, 0x17, 0x85, 0xc5, | |
27c868c2 | 5681 | 0x4a, 0xc6, 0x4a, 0xb5, 0xb6, 0xfe, 0x89, 0x10, 0x74, 0x67, 0x2d, 0x15, |
629d688d MW |
5682 | 0x9d, 0x01, 0x36, 0x10, 0xfe, 0x35, 0x00, 0xfe, 0x01, 0xf0, 0x65, 0x10, |
5683 | 0x80, 0x02, 0x65, 0xfe, 0x98, 0x80, 0xfe, 0x19, 0xe4, 0x0a, 0xfe, 0x1a, | |
5684 | 0x12, 0x51, 0xfe, 0x19, 0x82, 0xfe, 0x6c, 0x18, 0xfe, 0x44, 0x54, 0xbe, | |
27c868c2 | 5685 | 0xfe, 0x19, 0x81, 0xfe, 0x74, 0x18, 0x8f, 0x90, 0x17, 0xfe, 0xce, 0x08, |
629d688d MW |
5686 | 0x02, 0x4a, 0x08, 0x05, 0x5a, 0xec, 0x03, 0x2e, 0x29, 0x3c, 0x0c, 0x3f, |
5687 | 0x14, 0x40, 0x9b, 0x2e, 0x9c, 0x3c, 0xfe, 0x6c, 0x18, 0xfe, 0xed, 0x18, | |
5688 | 0xfe, 0x44, 0x54, 0xfe, 0xe5, 0x54, 0x3a, 0x3f, 0x3b, 0x40, 0x03, 0x49, | |
27c868c2 | 5689 | 0x29, 0x63, 0x8f, 0xfe, 0xe3, 0x54, 0xfe, 0x74, 0x18, 0xfe, 0xf5, 0x18, |
629d688d MW |
5690 | 0x8f, 0xfe, 0xe3, 0x54, 0x90, 0xc0, 0x56, 0xfe, 0xce, 0x08, 0x02, 0x4a, |
5691 | 0xfe, 0x37, 0xf0, 0xfe, 0xda, 0x09, 0xfe, 0x8b, 0xf0, 0xfe, 0x60, 0x09, | |
5692 | 0x02, 0x4a, 0x08, 0x05, 0x0a, 0x23, 0xfe, 0xfa, 0x0a, 0x3a, 0x49, 0x3b, | |
27c868c2 | 5693 | 0x63, 0x56, 0xfe, 0x3e, 0x0a, 0x0f, 0xfe, 0xc0, 0x07, 0x41, 0x98, 0x00, |
629d688d MW |
5694 | 0xad, 0xfe, 0x01, 0x59, 0xfe, 0x52, 0xf0, 0xfe, 0x0c, 0x0a, 0x8f, 0x7a, |
5695 | 0xfe, 0x24, 0x0a, 0x3a, 0x49, 0x8f, 0xfe, 0xe3, 0x54, 0x57, 0x49, 0x7d, | |
5696 | 0x63, 0xfe, 0x14, 0x58, 0xfe, 0x95, 0x58, 0x02, 0x4a, 0x3a, 0x49, 0x3b, | |
27c868c2 | 5697 | 0x63, 0xfe, 0x14, 0x59, 0xfe, 0x95, 0x59, 0xbe, 0x57, 0x49, 0x57, 0x63, |
629d688d MW |
5698 | 0x02, 0x4a, 0x08, 0x05, 0x5a, 0xfe, 0x82, 0x12, 0x08, 0x05, 0x1f, 0xfe, |
5699 | 0x66, 0x13, 0x22, 0x62, 0xb7, 0xfe, 0x03, 0xa1, 0xfe, 0x83, 0x80, 0xfe, | |
5700 | 0xc8, 0x44, 0xfe, 0x2e, 0x13, 0xfe, 0x04, 0x91, 0xfe, 0x86, 0x91, 0x6a, | |
27c868c2 | 5701 | 0x2a, 0xfe, 0x40, 0x59, 0xfe, 0xc1, 0x59, 0x56, 0xe0, 0x03, 0x60, 0x29, |
629d688d MW |
5702 | 0x61, 0x0c, 0x7f, 0x14, 0x80, 0x57, 0x60, 0x7d, 0x61, 0x01, 0xb3, 0xb8, |
5703 | 0x6a, 0x2a, 0x13, 0x62, 0x9b, 0x2e, 0x9c, 0x3c, 0x3a, 0x3f, 0x3b, 0x40, | |
5704 | 0x90, 0xc0, 0xfe, 0x04, 0xfa, 0x2e, 0xfe, 0x05, 0xfa, 0x3c, 0x01, 0xef, | |
27c868c2 | 5705 | 0xfe, 0x36, 0x10, 0x21, 0x0c, 0x7f, 0x0c, 0x80, 0x3a, 0x3f, 0x3b, 0x40, |
629d688d MW |
5706 | 0xe4, 0x08, 0x05, 0x1f, 0x17, 0xe0, 0x3a, 0x3d, 0x3b, 0x3e, 0x08, 0x05, |
5707 | 0xfe, 0xf7, 0x00, 0x37, 0x03, 0x5e, 0x29, 0x5f, 0xfe, 0x10, 0x58, 0xfe, | |
5708 | 0x91, 0x58, 0x57, 0x49, 0x7d, 0x63, 0x02, 0xfe, 0xf4, 0x09, 0x08, 0x05, | |
27c868c2 | 5709 | 0x1f, 0x17, 0xe0, 0x08, 0x05, 0xfe, 0xf7, 0x00, 0x37, 0xbe, 0xfe, 0x19, |
629d688d MW |
5710 | 0x81, 0x50, 0xfe, 0x10, 0x90, 0xfe, 0x92, 0x90, 0xfe, 0xd3, 0x10, 0x32, |
5711 | 0x07, 0xa6, 0x17, 0xfe, 0x08, 0x09, 0x12, 0xa6, 0x08, 0x05, 0x0a, 0xfe, | |
5712 | 0x14, 0x13, 0x03, 0x3d, 0x29, 0x3e, 0x56, 0xfe, 0x08, 0x09, 0xfe, 0x0c, | |
27c868c2 | 5713 | 0x58, 0xfe, 0x8d, 0x58, 0x02, 0x4a, 0x21, 0x41, 0xfe, 0x19, 0x80, 0xe7, |
629d688d MW |
5714 | 0x08, 0x05, 0x0a, 0xfe, 0x1a, 0x12, 0xfe, 0x6c, 0x19, 0xfe, 0x19, 0x41, |
5715 | 0xf4, 0xc2, 0xfe, 0xd1, 0xf0, 0xe2, 0x15, 0x7e, 0x01, 0x36, 0x10, 0xfe, | |
5716 | 0x44, 0x00, 0xfe, 0x8e, 0x10, 0xfe, 0x6c, 0x19, 0x57, 0x3d, 0xfe, 0xed, | |
27c868c2 | 5717 | 0x19, 0x7d, 0x3e, 0xfe, 0x0c, 0x51, 0xfe, 0x8e, 0x51, 0xf4, 0x1e, 0xfe, |
629d688d MW |
5718 | 0x00, 0xff, 0x35, 0xfe, 0x74, 0x10, 0xc2, 0xfe, 0xd2, 0xf0, 0xfe, 0xa6, |
5719 | 0x0b, 0xfe, 0x76, 0x18, 0x1e, 0x19, 0x8a, 0x03, 0xd2, 0x1e, 0x06, 0xfe, | |
5720 | 0x08, 0x13, 0x10, 0xfe, 0x16, 0x00, 0x02, 0x65, 0xfe, 0xd1, 0xf0, 0xfe, | |
27c868c2 | 5721 | 0xb8, 0x0b, 0x15, 0x7e, 0x01, 0x36, 0x10, 0xfe, 0x17, 0x00, 0xfe, 0x42, |
629d688d MW |
5722 | 0x10, 0xfe, 0xce, 0xf0, 0xfe, 0xbe, 0x0b, 0xfe, 0x3c, 0x10, 0xfe, 0xcd, |
5723 | 0xf0, 0xfe, 0xca, 0x0b, 0x10, 0xfe, 0x22, 0x00, 0x02, 0x65, 0xfe, 0xcb, | |
5724 | 0xf0, 0xfe, 0xd6, 0x0b, 0x10, 0xfe, 0x24, 0x00, 0x02, 0x65, 0xfe, 0xd0, | |
27c868c2 | 5725 | 0xf0, 0xfe, 0xe0, 0x0b, 0x10, 0x9e, 0xe5, 0xfe, 0xcf, 0xf0, 0xfe, 0xea, |
629d688d MW |
5726 | 0x0b, 0x10, 0x58, 0xfe, 0x10, 0x10, 0xfe, 0xcc, 0xf0, 0xe2, 0x68, 0x05, |
5727 | 0x1f, 0x4d, 0x10, 0xfe, 0x12, 0x00, 0x2c, 0x0f, 0xfe, 0x4e, 0x11, 0x27, | |
5728 | 0xfe, 0x00, 0x0c, 0xfe, 0x9e, 0xf0, 0xfe, 0x14, 0x0c, 0xbc, 0x17, 0x34, | |
27c868c2 | 5729 | 0x2c, 0x77, 0xe6, 0xc5, 0x24, 0xc6, 0x24, 0x2c, 0xfa, 0x27, 0xfe, 0x20, |
629d688d MW |
5730 | 0x0c, 0x1c, 0x34, 0x94, 0xfe, 0x3c, 0x0c, 0x95, 0x86, 0xc5, 0xdc, 0xc6, |
5731 | 0xdc, 0x02, 0x24, 0x01, 0x4b, 0xfe, 0xdb, 0x10, 0x12, 0xfe, 0xe8, 0x00, | |
5732 | 0xb5, 0xb6, 0x74, 0xc7, 0x81, 0xc8, 0x83, 0xfe, 0x89, 0xf0, 0x24, 0x33, | |
27c868c2 | 5733 | 0x31, 0xe1, 0xc7, 0x81, 0xc8, 0x83, 0x27, 0xfe, 0x66, 0x0c, 0x1d, 0x24, |
629d688d MW |
5734 | 0x33, 0x31, 0xdf, 0xbc, 0x4e, 0x10, 0xfe, 0x42, 0x00, 0x02, 0x65, 0x7c, |
5735 | 0x06, 0xfe, 0x81, 0x49, 0x17, 0xfe, 0x2c, 0x0d, 0x08, 0x05, 0x0a, 0xfe, | |
5736 | 0x44, 0x13, 0x10, 0x00, 0x55, 0x0a, 0xfe, 0x54, 0x12, 0x55, 0xfe, 0x28, | |
27c868c2 | 5737 | 0x00, 0x23, 0xfe, 0x9a, 0x0d, 0x09, 0x46, 0x01, 0x0e, 0x07, 0x00, 0x66, |
629d688d MW |
5738 | 0x44, 0xfe, 0x28, 0x00, 0xfe, 0xe2, 0x10, 0x01, 0xf5, 0x01, 0xf6, 0x09, |
5739 | 0xa4, 0x01, 0xfe, 0x26, 0x0f, 0x64, 0x12, 0x2f, 0x01, 0x73, 0x02, 0x2b, | |
5740 | 0x10, 0xfe, 0x44, 0x00, 0x55, 0x0a, 0xe9, 0x44, 0x0a, 0xfe, 0xb4, 0x10, | |
27c868c2 | 5741 | 0x01, 0xb0, 0x44, 0x0a, 0xfe, 0xaa, 0x10, 0x01, 0xb0, 0xfe, 0x19, 0x82, |
629d688d MW |
5742 | 0xfe, 0x34, 0x46, 0xac, 0x44, 0x0a, 0x10, 0xfe, 0x43, 0x00, 0xfe, 0x96, |
5743 | 0x10, 0x08, 0x54, 0x0a, 0x37, 0x01, 0xf5, 0x01, 0xf6, 0x64, 0x12, 0x2f, | |
5744 | 0x01, 0x73, 0x99, 0x0a, 0x64, 0x42, 0x92, 0x02, 0xfe, 0x2e, 0x03, 0x08, | |
27c868c2 | 5745 | 0x05, 0x0a, 0x8a, 0x44, 0x0a, 0x10, 0x00, 0xfe, 0x5c, 0x10, 0x68, 0x05, |
629d688d MW |
5746 | 0x1a, 0xfe, 0x58, 0x12, 0x08, 0x05, 0x1a, 0xfe, 0x50, 0x13, 0xfe, 0x1c, |
5747 | 0x1c, 0xfe, 0x9d, 0xf0, 0xfe, 0x50, 0x0d, 0xfe, 0x1c, 0x1c, 0xfe, 0x9d, | |
5748 | 0xf0, 0xfe, 0x56, 0x0d, 0x08, 0x54, 0x1a, 0x37, 0xfe, 0xa9, 0x10, 0x10, | |
27c868c2 | 5749 | 0xfe, 0x15, 0x00, 0xfe, 0x04, 0xe6, 0x0a, 0x50, 0xfe, 0x2e, 0x10, 0x10, |
629d688d MW |
5750 | 0xfe, 0x13, 0x00, 0xfe, 0x10, 0x10, 0x10, 0x6f, 0xab, 0x10, 0xfe, 0x41, |
5751 | 0x00, 0xaa, 0x10, 0xfe, 0x24, 0x00, 0x8c, 0xb5, 0xb6, 0x74, 0x03, 0x70, | |
5752 | 0x28, 0x23, 0xd8, 0x50, 0xfe, 0x04, 0xe6, 0x1a, 0xfe, 0x9d, 0x41, 0xfe, | |
27c868c2 | 5753 | 0x1c, 0x42, 0x64, 0x01, 0xe3, 0x02, 0x2b, 0xf8, 0x15, 0x0a, 0x39, 0xa0, |
629d688d MW |
5754 | 0xb4, 0x15, 0xfe, 0x31, 0x00, 0x39, 0xa2, 0x01, 0xfe, 0x48, 0x10, 0x02, |
5755 | 0xd7, 0x42, 0xfe, 0x06, 0xec, 0xd0, 0xfc, 0x44, 0x1b, 0xfe, 0xce, 0x45, | |
5756 | 0x35, 0x42, 0xfe, 0x06, 0xea, 0xd0, 0xfe, 0x47, 0x4b, 0x91, 0xfe, 0x75, | |
27c868c2 | 5757 | 0x57, 0x03, 0x5d, 0xfe, 0x98, 0x56, 0xfe, 0x38, 0x12, 0x09, 0x48, 0x01, |
629d688d MW |
5758 | 0x0e, 0xfe, 0x44, 0x48, 0x4f, 0x08, 0x05, 0x1b, 0xfe, 0x1a, 0x13, 0x09, |
5759 | 0x46, 0x01, 0x0e, 0x41, 0xfe, 0x41, 0x58, 0x09, 0xa4, 0x01, 0x0e, 0xfe, | |
5760 | 0x49, 0x54, 0x96, 0xfe, 0x1e, 0x0e, 0x02, 0xfe, 0x2e, 0x03, 0x09, 0x5d, | |
27c868c2 | 5761 | 0xfe, 0xee, 0x14, 0xfc, 0x44, 0x1b, 0xfe, 0xce, 0x45, 0x35, 0x42, 0xfe, |
629d688d MW |
5762 | 0xce, 0x47, 0xfe, 0xad, 0x13, 0x02, 0x2b, 0x22, 0x20, 0x07, 0x11, 0xfe, |
5763 | 0x9e, 0x12, 0x21, 0x13, 0x59, 0x13, 0x9f, 0x13, 0xd5, 0x22, 0x2f, 0x41, | |
5764 | 0x39, 0x2f, 0xbc, 0xad, 0xfe, 0xbc, 0xf0, 0xfe, 0xe0, 0x0e, 0x0f, 0x06, | |
27c868c2 | 5765 | 0x13, 0x59, 0x01, 0xfe, 0xda, 0x16, 0x03, 0xfe, 0x38, 0x01, 0x29, 0xfe, |
629d688d MW |
5766 | 0x3a, 0x01, 0x56, 0xfe, 0xe4, 0x0e, 0xfe, 0x02, 0xec, 0xd5, 0x69, 0x00, |
5767 | 0x66, 0xfe, 0x04, 0xec, 0x20, 0x4f, 0xfe, 0x05, 0xf6, 0xfe, 0x34, 0x01, | |
5768 | 0x01, 0xfe, 0x4a, 0x17, 0xfe, 0x08, 0x90, 0xfe, 0x48, 0xf4, 0x0d, 0xfe, | |
27c868c2 | 5769 | 0x18, 0x13, 0xba, 0xfe, 0x02, 0xea, 0xd5, 0x69, 0x7e, 0xfe, 0xc5, 0x13, |
629d688d MW |
5770 | 0x15, 0x1a, 0x39, 0xa0, 0xb4, 0xfe, 0x2e, 0x10, 0x03, 0xfe, 0x38, 0x01, |
5771 | 0x1e, 0xfe, 0xf0, 0xff, 0x0c, 0xfe, 0x60, 0x01, 0x03, 0xfe, 0x3a, 0x01, | |
5772 | 0x0c, 0xfe, 0x62, 0x01, 0x43, 0x13, 0x20, 0x25, 0x06, 0x13, 0x2f, 0x12, | |
27c868c2 | 5773 | 0x2f, 0x92, 0x0f, 0x06, 0x04, 0x21, 0x04, 0x22, 0x59, 0xfe, 0xf7, 0x12, |
629d688d MW |
5774 | 0x22, 0x9f, 0xb7, 0x13, 0x9f, 0x07, 0x7e, 0xfe, 0x71, 0x13, 0xfe, 0x24, |
5775 | 0x1c, 0x15, 0x19, 0x39, 0xa0, 0xb4, 0xfe, 0xd9, 0x10, 0xc3, 0xfe, 0x03, | |
5776 | 0xdc, 0xfe, 0x73, 0x57, 0xfe, 0x80, 0x5d, 0x04, 0xc3, 0xfe, 0x03, 0xdc, | |
27c868c2 | 5777 | 0xfe, 0x5b, 0x57, 0xfe, 0x80, 0x5d, 0x04, 0xfe, 0x03, 0x57, 0xc3, 0x21, |
629d688d MW |
5778 | 0xfe, 0x00, 0xcc, 0x04, 0xfe, 0x03, 0x57, 0xc3, 0x78, 0x04, 0x08, 0x05, |
5779 | 0x58, 0xfe, 0x22, 0x13, 0xfe, 0x1c, 0x80, 0x07, 0x06, 0xfe, 0x1a, 0x13, | |
5780 | 0xfe, 0x1e, 0x80, 0xed, 0xfe, 0x1d, 0x80, 0xae, 0xfe, 0x0c, 0x90, 0xfe, | |
27c868c2 | 5781 | 0x0e, 0x13, 0xfe, 0x0e, 0x90, 0xac, 0xfe, 0x3c, 0x90, 0xfe, 0x30, 0xf4, |
629d688d MW |
5782 | 0x0a, 0xfe, 0x3c, 0x50, 0xaa, 0x01, 0xfe, 0x7a, 0x17, 0x32, 0x07, 0x2f, |
5783 | 0xad, 0x01, 0xfe, 0xb4, 0x16, 0x08, 0x05, 0x1b, 0x4e, 0x01, 0xf5, 0x01, | |
5784 | 0xf6, 0x12, 0xfe, 0xe9, 0x00, 0x08, 0x05, 0x58, 0xfe, 0x2c, 0x13, 0x01, | |
27c868c2 | 5785 | 0xfe, 0x0c, 0x17, 0xfe, 0x1e, 0x1c, 0xfe, 0x14, 0x90, 0xfe, 0x96, 0x90, |
629d688d MW |
5786 | 0x0c, 0xfe, 0x64, 0x01, 0x14, 0xfe, 0x66, 0x01, 0x08, 0x05, 0x5b, 0xfe, |
5787 | 0x12, 0x12, 0xfe, 0x03, 0x80, 0x8d, 0xfe, 0x01, 0xec, 0x20, 0xfe, 0x80, | |
5788 | 0x40, 0x13, 0x20, 0x6a, 0x2a, 0x12, 0xcf, 0x64, 0x22, 0x20, 0xfb, 0x79, | |
27c868c2 | 5789 | 0x20, 0x04, 0xfe, 0x08, 0x1c, 0x03, 0xfe, 0xac, 0x00, 0xfe, 0x06, 0x58, |
629d688d MW |
5790 | 0x03, 0xfe, 0xae, 0x00, 0xfe, 0x07, 0x58, 0x03, 0xfe, 0xb0, 0x00, 0xfe, |
5791 | 0x08, 0x58, 0x03, 0xfe, 0xb2, 0x00, 0xfe, 0x09, 0x58, 0xfe, 0x0a, 0x1c, | |
5792 | 0x25, 0x6e, 0x13, 0xd0, 0x21, 0x0c, 0x5c, 0x0c, 0x45, 0x0f, 0x46, 0x52, | |
27c868c2 | 5793 | 0x50, 0x18, 0x1b, 0xfe, 0x90, 0x4d, 0xfe, 0x91, 0x54, 0x23, 0xfe, 0xfc, |
629d688d MW |
5794 | 0x0f, 0x44, 0x11, 0x0f, 0x48, 0x52, 0x18, 0x58, 0xfe, 0x90, 0x4d, 0xfe, |
5795 | 0x91, 0x54, 0x23, 0xe4, 0x25, 0x11, 0x13, 0x20, 0x7c, 0x6f, 0x4f, 0x22, | |
5796 | 0x20, 0xfb, 0x79, 0x20, 0x12, 0xcf, 0xfe, 0x14, 0x56, 0xfe, 0xd6, 0xf0, | |
27c868c2 | 5797 | 0xfe, 0x26, 0x10, 0xf8, 0x74, 0xfe, 0x14, 0x1c, 0xfe, 0x10, 0x1c, 0xfe, |
629d688d MW |
5798 | 0x18, 0x1c, 0x04, 0x42, 0xfe, 0x0c, 0x14, 0xfc, 0xfe, 0x07, 0xe6, 0x1b, |
5799 | 0xfe, 0xce, 0x47, 0xfe, 0xf5, 0x13, 0x04, 0x01, 0xb0, 0x7c, 0x6f, 0x4f, | |
5800 | 0xfe, 0x06, 0x80, 0xfe, 0x48, 0x47, 0xfe, 0x42, 0x13, 0x32, 0x07, 0x2f, | |
27c868c2 | 5801 | 0xfe, 0x34, 0x13, 0x09, 0x48, 0x01, 0x0e, 0xbb, 0xfe, 0x36, 0x12, 0xfe, |
629d688d MW |
5802 | 0x41, 0x48, 0xfe, 0x45, 0x48, 0x01, 0xf0, 0xfe, 0x00, 0xcc, 0xbb, 0xfe, |
5803 | 0xf3, 0x13, 0x43, 0x78, 0x07, 0x11, 0xac, 0x09, 0x84, 0x01, 0x0e, 0xfe, | |
5804 | 0x80, 0x5c, 0x01, 0x73, 0xfe, 0x0e, 0x10, 0x07, 0x82, 0x4e, 0xfe, 0x14, | |
27c868c2 | 5805 | 0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0x60, 0x10, 0x04, 0xfe, 0x44, 0x58, 0x8d, |
629d688d MW |
5806 | 0xfe, 0x01, 0xec, 0xa2, 0xfe, 0x9e, 0x40, 0xfe, 0x9d, 0xe7, 0x00, 0xfe, |
5807 | 0x9c, 0xe7, 0x1a, 0x79, 0x2a, 0x01, 0xe3, 0xfe, 0xdd, 0x10, 0x2c, 0xc7, | |
5808 | 0x81, 0xc8, 0x83, 0x33, 0x31, 0xde, 0x07, 0x1a, 0xfe, 0x48, 0x12, 0x07, | |
27c868c2 | 5809 | 0x0a, 0xfe, 0x56, 0x12, 0x07, 0x19, 0xfe, 0x30, 0x12, 0x07, 0xc9, 0x17, |
629d688d MW |
5810 | 0xfe, 0x32, 0x12, 0x07, 0xfe, 0x23, 0x00, 0x17, 0xeb, 0x07, 0x06, 0x17, |
5811 | 0xfe, 0x9c, 0x12, 0x07, 0x1f, 0xfe, 0x12, 0x12, 0x07, 0x00, 0x17, 0x24, | |
5812 | 0x15, 0xc9, 0x01, 0x36, 0xa9, 0x2d, 0x01, 0x0b, 0x94, 0x4b, 0x04, 0x2d, | |
27c868c2 | 5813 | 0xdd, 0x09, 0xd1, 0x01, 0xfe, 0x26, 0x0f, 0x12, 0x82, 0x02, 0x2b, 0x2d, |
629d688d MW |
5814 | 0x32, 0x07, 0xa6, 0xfe, 0xd9, 0x13, 0x3a, 0x3d, 0x3b, 0x3e, 0x56, 0xfe, |
5815 | 0xf0, 0x11, 0x08, 0x05, 0x5a, 0xfe, 0x72, 0x12, 0x9b, 0x2e, 0x9c, 0x3c, | |
5816 | 0x90, 0xc0, 0x96, 0xfe, 0xba, 0x11, 0x22, 0x62, 0xfe, 0x26, 0x13, 0x03, | |
27c868c2 | 5817 | 0x7f, 0x29, 0x80, 0x56, 0xfe, 0x76, 0x0d, 0x0c, 0x60, 0x14, 0x61, 0x21, |
629d688d MW |
5818 | 0x0c, 0x7f, 0x0c, 0x80, 0x01, 0xb3, 0x25, 0x6e, 0x77, 0x13, 0x62, 0x01, |
5819 | 0xef, 0x9b, 0x2e, 0x9c, 0x3c, 0xfe, 0x04, 0x55, 0xfe, 0xa5, 0x55, 0xfe, | |
5820 | 0x04, 0xfa, 0x2e, 0xfe, 0x05, 0xfa, 0x3c, 0xfe, 0x91, 0x10, 0x03, 0x3f, | |
27c868c2 | 5821 | 0x29, 0x40, 0xfe, 0x40, 0x56, 0xfe, 0xe1, 0x56, 0x0c, 0x3f, 0x14, 0x40, |
629d688d MW |
5822 | 0x88, 0x9b, 0x2e, 0x9c, 0x3c, 0x90, 0xc0, 0x03, 0x5e, 0x29, 0x5f, 0xfe, |
5823 | 0x00, 0x56, 0xfe, 0xa1, 0x56, 0x0c, 0x5e, 0x14, 0x5f, 0x08, 0x05, 0x5a, | |
5824 | 0xfe, 0x1e, 0x12, 0x22, 0x62, 0xfe, 0x1f, 0x40, 0x03, 0x60, 0x29, 0x61, | |
27c868c2 | 5825 | 0xfe, 0x2c, 0x50, 0xfe, 0xae, 0x50, 0x03, 0x3f, 0x29, 0x40, 0xfe, 0x44, |
629d688d MW |
5826 | 0x50, 0xfe, 0xc6, 0x50, 0x03, 0x5e, 0x29, 0x5f, 0xfe, 0x08, 0x50, 0xfe, |
5827 | 0x8a, 0x50, 0x03, 0x3d, 0x29, 0x3e, 0xfe, 0x40, 0x50, 0xfe, 0xc2, 0x50, | |
5828 | 0x02, 0x89, 0x25, 0x06, 0x13, 0xd4, 0x02, 0x72, 0x2d, 0x01, 0x0b, 0x1d, | |
27c868c2 | 5829 | 0x4c, 0x33, 0x31, 0xde, 0x07, 0x06, 0x23, 0x4c, 0x32, 0x07, 0xa6, 0x23, |
629d688d MW |
5830 | 0x72, 0x01, 0xaf, 0x1e, 0x43, 0x17, 0x4c, 0x08, 0x05, 0x0a, 0xee, 0x3a, |
5831 | 0x3d, 0x3b, 0x3e, 0xfe, 0x0a, 0x55, 0x35, 0xfe, 0x8b, 0x55, 0x57, 0x3d, | |
5832 | 0x7d, 0x3e, 0xfe, 0x0c, 0x51, 0xfe, 0x8e, 0x51, 0x02, 0x72, 0xfe, 0x19, | |
27c868c2 | 5833 | 0x81, 0xba, 0xfe, 0x19, 0x41, 0x02, 0x72, 0x2d, 0x01, 0x0b, 0x1c, 0x34, |
629d688d MW |
5834 | 0x1d, 0xe8, 0x33, 0x31, 0xe1, 0x55, 0x19, 0xfe, 0xa6, 0x12, 0x55, 0x0a, |
5835 | 0x4d, 0x02, 0x4c, 0x01, 0x0b, 0x1c, 0x34, 0x1d, 0xe8, 0x33, 0x31, 0xdf, | |
5836 | 0x07, 0x19, 0x23, 0x4c, 0x01, 0x0b, 0x1d, 0xe8, 0x33, 0x31, 0xfe, 0xe8, | |
27c868c2 | 5837 | 0x09, 0xfe, 0xc2, 0x49, 0x51, 0x03, 0xfe, 0x9c, 0x00, 0x28, 0x8a, 0x53, |
629d688d MW |
5838 | 0x05, 0x1f, 0x35, 0xa9, 0xfe, 0xbb, 0x45, 0x55, 0x00, 0x4e, 0x44, 0x06, |
5839 | 0x7c, 0x43, 0xfe, 0xda, 0x14, 0x01, 0xaf, 0x8c, 0xfe, 0x4b, 0x45, 0xee, | |
5840 | 0x32, 0x07, 0xa5, 0xed, 0x03, 0xcd, 0x28, 0x8a, 0x03, 0x45, 0x28, 0x35, | |
27c868c2 | 5841 | 0x67, 0x02, 0x72, 0xfe, 0xc0, 0x5d, 0xfe, 0xf8, 0x14, 0xfe, 0x03, 0x17, |
629d688d MW |
5842 | 0x03, 0x5c, 0xc1, 0x0c, 0x5c, 0x67, 0x2d, 0x01, 0x0b, 0x26, 0x89, 0x01, |
5843 | 0xfe, 0x9e, 0x15, 0x02, 0x89, 0x01, 0x0b, 0x1c, 0x34, 0x1d, 0x4c, 0x33, | |
5844 | 0x31, 0xdf, 0x07, 0x06, 0x23, 0x4c, 0x01, 0xf1, 0xfe, 0x42, 0x58, 0xf1, | |
27c868c2 | 5845 | 0xfe, 0xa4, 0x14, 0x8c, 0xfe, 0x4a, 0xf4, 0x0a, 0x17, 0x4c, 0xfe, 0x4a, |
629d688d MW |
5846 | 0xf4, 0x06, 0xea, 0x32, 0x07, 0xa5, 0x8b, 0x02, 0x72, 0x03, 0x45, 0xc1, |
5847 | 0x0c, 0x45, 0x67, 0x2d, 0x01, 0x0b, 0x26, 0x89, 0x01, 0xfe, 0xcc, 0x15, | |
5848 | 0x02, 0x89, 0x0f, 0x06, 0x27, 0xfe, 0xbe, 0x13, 0x26, 0xfe, 0xd4, 0x13, | |
27c868c2 | 5849 | 0x76, 0xfe, 0x89, 0x48, 0x01, 0x0b, 0x21, 0x76, 0x04, 0x7b, 0xfe, 0xd0, |
629d688d MW |
5850 | 0x13, 0x1c, 0xfe, 0xd0, 0x13, 0x1d, 0xfe, 0xbe, 0x13, 0x67, 0x2d, 0x01, |
5851 | 0x0b, 0xfe, 0xd5, 0x10, 0x0f, 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93, | |
5852 | 0x1e, 0xfe, 0xff, 0x7f, 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x04, 0x0f, | |
27c868c2 | 5853 | 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93, 0x1e, 0x43, 0xfe, 0x30, 0x56, |
629d688d MW |
5854 | 0xfe, 0x00, 0x5c, 0x04, 0x0f, 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93, |
5855 | 0x04, 0x0f, 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93, 0xfe, 0x0b, 0x58, | |
5856 | 0x04, 0x09, 0x5c, 0x01, 0x87, 0x09, 0x45, 0x01, 0x87, 0x04, 0xfe, 0x03, | |
27c868c2 | 5857 | 0xa1, 0x1e, 0x11, 0xff, 0x03, 0x00, 0x54, 0xfe, 0x00, 0xf4, 0x1f, 0x52, |
629d688d MW |
5858 | 0xfe, 0x00, 0x7d, 0xfe, 0x01, 0x7d, 0xfe, 0x02, 0x7d, 0xfe, 0x03, 0x7c, |
5859 | 0x6a, 0x2a, 0x0c, 0x5e, 0x14, 0x5f, 0x57, 0x3f, 0x7d, 0x40, 0x04, 0xdd, | |
5860 | 0xfe, 0x82, 0x4a, 0xfe, 0xe1, 0x1a, 0xfe, 0x83, 0x5a, 0x8d, 0x04, 0x01, | |
27c868c2 | 5861 | 0xfe, 0x0c, 0x19, 0xfe, 0x42, 0x48, 0x50, 0x51, 0x91, 0x01, 0x0b, 0x1d, |
629d688d MW |
5862 | 0xfe, 0x96, 0x15, 0x33, 0x31, 0xe1, 0x01, 0x0b, 0x1d, 0xfe, 0x96, 0x15, |
5863 | 0x33, 0x31, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59, 0x03, 0xcd, 0x28, 0xfe, | |
5864 | 0xcc, 0x12, 0x53, 0x05, 0x1a, 0xfe, 0xc4, 0x13, 0x21, 0x69, 0x1a, 0xee, | |
27c868c2 | 5865 | 0x55, 0xca, 0x6b, 0xfe, 0xdc, 0x14, 0x4d, 0x0f, 0x06, 0x18, 0xca, 0x7c, |
629d688d MW |
5866 | 0x30, 0xfe, 0x78, 0x10, 0xff, 0x02, 0x83, 0x55, 0xab, 0xff, 0x02, 0x83, |
5867 | 0x55, 0x69, 0x19, 0xae, 0x98, 0xfe, 0x30, 0x00, 0x96, 0xf2, 0x18, 0x6d, | |
5868 | 0x0f, 0x06, 0xfe, 0x56, 0x10, 0x69, 0x0a, 0xed, 0x98, 0xfe, 0x64, 0x00, | |
27c868c2 | 5869 | 0x96, 0xf2, 0x09, 0xfe, 0x64, 0x00, 0x18, 0x9e, 0x0f, 0x06, 0xfe, 0x28, |
629d688d MW |
5870 | 0x10, 0x69, 0x06, 0xfe, 0x60, 0x13, 0x98, 0xfe, 0xc8, 0x00, 0x96, 0xf2, |
5871 | 0x09, 0xfe, 0xc8, 0x00, 0x18, 0x59, 0x0f, 0x06, 0x88, 0x98, 0xfe, 0x90, | |
5872 | 0x01, 0x7a, 0xfe, 0x42, 0x15, 0x91, 0xe4, 0xfe, 0x43, 0xf4, 0x9f, 0xfe, | |
27c868c2 | 5873 | 0x56, 0xf0, 0xfe, 0x54, 0x15, 0xfe, 0x04, 0xf4, 0x71, 0xfe, 0x43, 0xf4, |
629d688d MW |
5874 | 0x9e, 0xfe, 0xf3, 0x10, 0xfe, 0x40, 0x5c, 0x01, 0xfe, 0x16, 0x14, 0x1e, |
5875 | 0x43, 0xec, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4, 0x6e, 0x7a, 0xfe, 0x90, | |
5876 | 0x15, 0xc4, 0x6e, 0xfe, 0x1c, 0x10, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4, | |
27c868c2 | 5877 | 0xcc, 0x7a, 0xfe, 0x90, 0x15, 0xc4, 0xcc, 0x88, 0x51, 0x21, 0xfe, 0x4d, |
629d688d MW |
5878 | 0xf4, 0x00, 0xe9, 0x91, 0x0f, 0x06, 0xfe, 0xb4, 0x56, 0xfe, 0xc3, 0x58, |
5879 | 0x04, 0x51, 0x0f, 0x0a, 0x04, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xf3, 0x16, | |
5880 | 0x0a, 0x01, 0x0b, 0x26, 0xf3, 0x16, 0x19, 0x01, 0x0b, 0x26, 0xf3, 0x76, | |
27c868c2 | 5881 | 0xfe, 0x89, 0x49, 0x01, 0x0b, 0x04, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xb1, |
629d688d MW |
5882 | 0x16, 0x19, 0x01, 0x0b, 0x26, 0xb1, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xb1, |
5883 | 0xfe, 0x89, 0x49, 0x01, 0x0b, 0x26, 0xb1, 0x76, 0xfe, 0x89, 0x4a, 0x01, | |
5884 | 0x0b, 0x04, 0x51, 0x04, 0x22, 0xd3, 0x07, 0x06, 0xfe, 0x48, 0x13, 0xb8, | |
27c868c2 | 5885 | 0x13, 0xd3, 0xfe, 0x49, 0xf4, 0x00, 0x4d, 0x76, 0xa9, 0x67, 0xfe, 0x01, |
629d688d MW |
5886 | 0xec, 0xfe, 0x27, 0x01, 0xfe, 0x89, 0x48, 0xff, 0x02, 0x00, 0x10, 0x27, |
5887 | 0xfe, 0x2e, 0x16, 0x32, 0x07, 0xfe, 0xe3, 0x00, 0xfe, 0x20, 0x13, 0x1d, | |
5888 | 0xfe, 0x52, 0x16, 0x21, 0x13, 0xd4, 0x01, 0x4b, 0x22, 0xd4, 0x07, 0x06, | |
27c868c2 | 5889 | 0x4e, 0x08, 0x54, 0x06, 0x37, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfb, 0x8e, |
629d688d MW |
5890 | 0x07, 0x11, 0xae, 0x09, 0x84, 0x01, 0x0e, 0x8e, 0x09, 0x5d, 0x01, 0xa8, |
5891 | 0x04, 0x09, 0x84, 0x01, 0x0e, 0x8e, 0xfe, 0x80, 0xe7, 0x11, 0x07, 0x11, | |
5892 | 0x8a, 0xfe, 0x45, 0x58, 0x01, 0xf0, 0x8e, 0x04, 0x09, 0x48, 0x01, 0x0e, | |
27c868c2 | 5893 | 0x8e, 0x09, 0x5d, 0x01, 0xa8, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfe, 0x80, |
629d688d MW |
5894 | 0x80, 0xfe, 0x80, 0x4c, 0xfe, 0x49, 0xe4, 0x11, 0xae, 0x09, 0x84, 0x01, |
5895 | 0x0e, 0xfe, 0x80, 0x4c, 0x09, 0x5d, 0x01, 0x87, 0x04, 0x18, 0x11, 0x75, | |
5896 | 0x6c, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x24, | |
27c868c2 | 5897 | 0x1c, 0xfe, 0x1d, 0xf7, 0x1b, 0x97, 0xfe, 0xee, 0x16, 0x01, 0xfe, 0xf4, |
629d688d MW |
5898 | 0x17, 0xad, 0x9a, 0x1b, 0x6c, 0xfe, 0x2c, 0x01, 0xfe, 0x2f, 0x19, 0x04, |
5899 | 0xb9, 0x23, 0xfe, 0xde, 0x16, 0xfe, 0xda, 0x10, 0x18, 0x11, 0x75, 0x03, | |
5900 | 0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x1f, 0xfe, 0x18, 0x58, 0x03, 0xfe, | |
27c868c2 | 5901 | 0x66, 0x01, 0xfe, 0x19, 0x58, 0x9a, 0x1f, 0xfe, 0x3c, 0x90, 0xfe, 0x30, |
629d688d MW |
5902 | 0xf4, 0x06, 0xfe, 0x3c, 0x50, 0x6c, 0xfe, 0x38, 0x00, 0xfe, 0x0f, 0x79, |
5903 | 0xfe, 0x1c, 0xf7, 0x1f, 0x97, 0xfe, 0x38, 0x17, 0xfe, 0xb6, 0x14, 0x35, | |
5904 | 0x04, 0xb9, 0x23, 0xfe, 0x10, 0x17, 0xfe, 0x9c, 0x10, 0x18, 0x11, 0x75, | |
27c868c2 | 5905 | 0xfe, 0x83, 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x1d, 0xf7, |
629d688d MW |
5906 | 0x2e, 0x97, 0xfe, 0x5a, 0x17, 0xfe, 0x94, 0x14, 0xec, 0x9a, 0x2e, 0x6c, |
5907 | 0x1a, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00, 0x04, 0xb9, 0x23, 0xfe, | |
5908 | 0x4e, 0x17, 0xfe, 0x6c, 0x10, 0x18, 0x11, 0x75, 0xfe, 0x30, 0xbc, 0xfe, | |
27c868c2 | 5909 | 0xb2, 0xbc, 0x9a, 0xcb, 0x6c, 0x1a, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7, |
629d688d MW |
5910 | 0xcb, 0x97, 0xfe, 0x92, 0x17, 0xfe, 0x5c, 0x14, 0x35, 0x04, 0xb9, 0x23, |
5911 | 0xfe, 0x7e, 0x17, 0xfe, 0x42, 0x10, 0xfe, 0x02, 0xf6, 0x11, 0x75, 0xfe, | |
5912 | 0x18, 0xfe, 0x60, 0xfe, 0x19, 0xfe, 0x61, 0xfe, 0x03, 0xa1, 0xfe, 0x1d, | |
27c868c2 | 5913 | 0xf7, 0x5b, 0x97, 0xfe, 0xb8, 0x17, 0xfe, 0x36, 0x14, 0xfe, 0x1c, 0x13, |
629d688d MW |
5914 | 0x9a, 0x5b, 0x41, 0xfe, 0x83, 0x58, 0xfe, 0xaf, 0x19, 0xfe, 0x80, 0xe7, |
5915 | 0x11, 0xfe, 0x81, 0xe7, 0x11, 0x12, 0xfe, 0xdd, 0x00, 0x6a, 0x2a, 0x04, | |
5916 | 0x6a, 0x2a, 0xfe, 0x12, 0x45, 0x23, 0xfe, 0xa8, 0x17, 0x15, 0x06, 0x39, | |
27c868c2 | 5917 | 0xa0, 0xb4, 0x02, 0x2b, 0xfe, 0x39, 0xf0, 0xfe, 0xfc, 0x17, 0x21, 0x04, |
629d688d MW |
5918 | 0xfe, 0x7e, 0x18, 0x1e, 0x19, 0x66, 0x0f, 0x0d, 0x04, 0x75, 0x03, 0xd2, |
5919 | 0x1e, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10, 0x7c, 0x6f, 0x4f, 0x32, | |
5920 | 0x07, 0x2f, 0xfe, 0x3c, 0x13, 0xf1, 0xfe, 0x42, 0x13, 0x42, 0x92, 0x09, | |
27c868c2 | 5921 | 0x48, 0x01, 0x0e, 0xbb, 0xeb, 0xfe, 0x41, 0x48, 0xfe, 0x45, 0x48, 0x01, |
629d688d MW |
5922 | 0xf0, 0xfe, 0x00, 0xcc, 0xbb, 0xfe, 0xf3, 0x13, 0x43, 0x78, 0x07, 0x11, |
5923 | 0xac, 0x09, 0x84, 0x01, 0x0e, 0xfe, 0x80, 0x4c, 0x01, 0x73, 0xfe, 0x16, | |
5924 | 0x10, 0x07, 0x82, 0x8b, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12, 0xfe, 0x14, | |
27c868c2 | 5925 | 0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0x1c, 0x18, 0x18, 0x0a, 0x04, 0xfe, 0x9c, |
629d688d MW |
5926 | 0xe7, 0x0a, 0x10, 0xfe, 0x15, 0x00, 0x64, 0x79, 0x2a, 0x01, 0xe3, 0x18, |
5927 | 0x06, 0x04, 0x42, 0x92, 0x08, 0x54, 0x1b, 0x37, 0x12, 0x2f, 0x01, 0x73, | |
5928 | 0x18, 0x06, 0x04, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x3a, 0xce, 0x3b, | |
27c868c2 | 5929 | 0xcf, 0xfe, 0x48, 0x55, 0x35, 0xfe, 0xc9, 0x55, 0x04, 0x22, 0xa3, 0x77, |
629d688d MW |
5930 | 0x13, 0xa3, 0x04, 0x09, 0xa4, 0x01, 0x0e, 0xfe, 0x41, 0x48, 0x09, 0x46, |
5931 | 0x01, 0x0e, 0xfe, 0x49, 0x44, 0x17, 0xfe, 0xe8, 0x18, 0x77, 0x78, 0x04, | |
5932 | 0x09, 0x48, 0x01, 0x0e, 0x07, 0x11, 0x4e, 0x09, 0x5d, 0x01, 0xa8, 0x09, | |
27c868c2 | 5933 | 0x46, 0x01, 0x0e, 0x77, 0x78, 0x04, 0xfe, 0x4e, 0xe4, 0x19, 0x6b, 0xfe, |
629d688d MW |
5934 | 0x1c, 0x19, 0x03, 0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10, |
5935 | 0xfe, 0x4e, 0xe4, 0xc9, 0x6b, 0xfe, 0x2e, 0x19, 0x03, 0xfe, 0x92, 0x00, | |
5936 | 0xfe, 0x02, 0xe6, 0x1a, 0xe5, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x6b, | |
27c868c2 | 5937 | 0xfe, 0x40, 0x19, 0x03, 0xfe, 0x94, 0x00, 0xfe, 0x02, 0xe6, 0x1f, 0xfe, |
629d688d MW |
5938 | 0x08, 0x10, 0x03, 0xfe, 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x6d, 0xfe, 0x4e, |
5939 | 0x45, 0xea, 0xba, 0xff, 0x04, 0x68, 0x54, 0xe7, 0x1e, 0x6e, 0xfe, 0x08, | |
5940 | 0x1c, 0xfe, 0x67, 0x19, 0xfe, 0x0a, 0x1c, 0xfe, 0x1a, 0xf4, 0xfe, 0x00, | |
27c868c2 | 5941 | 0x04, 0xea, 0xfe, 0x48, 0xf4, 0x19, 0x7a, 0xfe, 0x74, 0x19, 0x0f, 0x19, |
629d688d MW |
5942 | 0x04, 0x07, 0x7e, 0xfe, 0x5a, 0xf0, 0xfe, 0x84, 0x19, 0x25, 0xfe, 0x09, |
5943 | 0x00, 0xfe, 0x34, 0x10, 0x07, 0x1a, 0xfe, 0x5a, 0xf0, 0xfe, 0x92, 0x19, | |
5944 | 0x25, 0xca, 0xfe, 0x26, 0x10, 0x07, 0x19, 0x66, 0x25, 0x6d, 0xe5, 0x07, | |
27c868c2 | 5945 | 0x0a, 0x66, 0x25, 0x9e, 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x66, 0x25, 0x59, |
629d688d MW |
5946 | 0xa9, 0xb8, 0x04, 0x15, 0xfe, 0x09, 0x00, 0x01, 0x36, 0xfe, 0x04, 0xfe, |
5947 | 0x81, 0x03, 0x83, 0xfe, 0x40, 0x5c, 0x04, 0x1c, 0xf7, 0xfe, 0x14, 0xf0, | |
5948 | 0x0b, 0x27, 0xfe, 0xd6, 0x19, 0x1c, 0xf7, 0x7b, 0xf7, 0xfe, 0x82, 0xf0, | |
27c868c2 | 5949 | 0xfe, 0xda, 0x19, 0x04, 0xff, 0xcc, 0x00, 0x00, |
1da177e4 LT |
5950 | }; |
5951 | ||
27c868c2 MW |
5952 | static unsigned short _adv_asc38C0800_size = sizeof(_adv_asc38C0800_buf); /* 0x14E1 */ |
5953 | static ADV_DCNT _adv_asc38C0800_chksum = 0x050D3FD8UL; /* Expanded little-endian checksum. */ | |
1da177e4 LT |
5954 | |
5955 | /* Microcode buffer is kept after initialization for error recovery. */ | |
27c868c2 MW |
5956 | static unsigned char _adv_asc38C1600_buf[] = { |
5957 | 0x00, 0x00, 0x00, 0xf2, 0x00, 0x16, 0x00, 0xfc, 0x00, 0x10, 0x00, 0xf0, | |
629d688d MW |
5958 | 0x18, 0xe4, 0x01, 0x00, 0x04, 0x1e, 0x48, 0xe4, 0x03, 0xf6, 0xf7, 0x13, |
5959 | 0x2e, 0x1e, 0x02, 0x00, 0x07, 0x17, 0xc0, 0x5f, 0x00, 0xfa, 0xff, 0xff, | |
5960 | 0x04, 0x00, 0x00, 0xf6, 0x09, 0xe7, 0x82, 0xe7, 0x85, 0xf0, 0x86, 0xf0, | |
27c868c2 | 5961 | 0x4e, 0x10, 0x9e, 0xe7, 0xff, 0x00, 0x55, 0xf0, 0x01, 0xf6, 0x03, 0x00, |
629d688d MW |
5962 | 0x98, 0x57, 0x01, 0xe6, 0x00, 0xea, 0x00, 0xec, 0x01, 0xfa, 0x18, 0xf4, |
5963 | 0x08, 0x00, 0xf0, 0x1d, 0x38, 0x54, 0x32, 0xf0, 0x10, 0x00, 0xc2, 0x0e, | |
5964 | 0x1e, 0xf0, 0xd5, 0xf0, 0xbc, 0x00, 0x4b, 0xe4, 0x00, 0xe6, 0xb1, 0xf0, | |
27c868c2 | 5965 | 0xb4, 0x00, 0x02, 0x13, 0x3e, 0x1c, 0xc8, 0x47, 0x3e, 0x00, 0xd8, 0x01, |
629d688d MW |
5966 | 0x06, 0x13, 0x0c, 0x1c, 0x5e, 0x1e, 0x00, 0x57, 0xc8, 0x57, 0x01, 0xfc, |
5967 | 0xbc, 0x0e, 0xa2, 0x12, 0xb9, 0x54, 0x00, 0x80, 0x62, 0x0a, 0x5a, 0x12, | |
5968 | 0xc8, 0x15, 0x3e, 0x1e, 0x18, 0x40, 0xbd, 0x56, 0x03, 0xe6, 0x01, 0xea, | |
27c868c2 | 5969 | 0x5c, 0xf0, 0x0f, 0x00, 0x20, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12, |
629d688d MW |
5970 | 0x04, 0x13, 0xbb, 0x55, 0x3c, 0x56, 0x3e, 0x57, 0x03, 0x58, 0x4a, 0xe4, |
5971 | 0x40, 0x00, 0xb6, 0x00, 0xbb, 0x00, 0xc0, 0x00, 0x00, 0x01, 0x01, 0x01, | |
5972 | 0x3e, 0x01, 0x58, 0x0a, 0x44, 0x10, 0x0a, 0x12, 0x4c, 0x1c, 0x4e, 0x1c, | |
27c868c2 | 5973 | 0x02, 0x4a, 0x30, 0xe4, 0x05, 0xe6, 0x0c, 0x00, 0x3c, 0x00, 0x80, 0x00, |
629d688d MW |
5974 | 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01, 0x70, 0x01, 0x72, 0x01, |
5975 | 0x74, 0x01, 0x76, 0x01, 0x78, 0x01, 0x7c, 0x01, 0xc6, 0x0e, 0x0c, 0x10, | |
5976 | 0xac, 0x12, 0xae, 0x12, 0x16, 0x1a, 0x32, 0x1c, 0x6e, 0x1e, 0x02, 0x48, | |
27c868c2 | 5977 | 0x3a, 0x55, 0xc9, 0x57, 0x02, 0xee, 0x5b, 0xf0, 0x03, 0xf7, 0x06, 0xf7, |
629d688d MW |
5978 | 0x03, 0xfc, 0x06, 0x00, 0x1e, 0x00, 0xbe, 0x00, 0xe1, 0x00, 0x0c, 0x12, |
5979 | 0x18, 0x1a, 0x70, 0x1a, 0x30, 0x1c, 0x38, 0x1c, 0x10, 0x44, 0x00, 0x4c, | |
5980 | 0xb0, 0x57, 0x40, 0x5c, 0x4d, 0xe4, 0x04, 0xea, 0x5d, 0xf0, 0xa7, 0xf0, | |
27c868c2 | 5981 | 0x04, 0xf6, 0x02, 0xfc, 0x05, 0x00, 0x09, 0x00, 0x19, 0x00, 0x32, 0x00, |
629d688d MW |
5982 | 0x33, 0x00, 0x34, 0x00, 0x36, 0x00, 0x98, 0x00, 0x9e, 0x00, 0xcc, 0x00, |
5983 | 0x20, 0x01, 0x4e, 0x01, 0x79, 0x01, 0x3c, 0x09, 0x68, 0x0d, 0x02, 0x10, | |
5984 | 0x04, 0x10, 0x3a, 0x10, 0x08, 0x12, 0x0a, 0x13, 0x40, 0x16, 0x50, 0x16, | |
27c868c2 | 5985 | 0x00, 0x17, 0x4a, 0x19, 0x00, 0x4e, 0x00, 0x54, 0x01, 0x58, 0x00, 0xdc, |
629d688d MW |
5986 | 0x05, 0xf0, 0x09, 0xf0, 0x59, 0xf0, 0xb8, 0xf0, 0x48, 0xf4, 0x0e, 0xf7, |
5987 | 0x0a, 0x00, 0x9b, 0x00, 0x9c, 0x00, 0xa4, 0x00, 0xb5, 0x00, 0xba, 0x00, | |
5988 | 0xd0, 0x00, 0xe7, 0x00, 0xf0, 0x03, 0x69, 0x08, 0xe9, 0x09, 0x5c, 0x0c, | |
27c868c2 | 5989 | 0xb6, 0x12, 0xbc, 0x19, 0xd8, 0x1b, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c, |
629d688d MW |
5990 | 0x42, 0x1d, 0x08, 0x44, 0x38, 0x44, 0x91, 0x44, 0x0a, 0x45, 0x48, 0x46, |
5991 | 0x89, 0x48, 0x68, 0x54, 0x83, 0x55, 0x83, 0x59, 0x31, 0xe4, 0x02, 0xe6, | |
5992 | 0x07, 0xf0, 0x08, 0xf0, 0x0b, 0xf0, 0x0c, 0xf0, 0x4b, 0xf4, 0x04, 0xf8, | |
27c868c2 | 5993 | 0x05, 0xf8, 0x02, 0xfa, 0x03, 0xfa, 0x04, 0xfc, 0x05, 0xfc, 0x07, 0x00, |
629d688d MW |
5994 | 0xa8, 0x00, 0xaa, 0x00, 0xb9, 0x00, 0xe0, 0x00, 0xe5, 0x00, 0x22, 0x01, |
5995 | 0x26, 0x01, 0x60, 0x01, 0x7a, 0x01, 0x82, 0x01, 0xc8, 0x01, 0xca, 0x01, | |
5996 | 0x86, 0x02, 0x6a, 0x03, 0x18, 0x05, 0xb2, 0x07, 0x68, 0x08, 0x10, 0x0d, | |
27c868c2 | 5997 | 0x06, 0x10, 0x0a, 0x10, 0x0e, 0x10, 0x12, 0x10, 0x60, 0x10, 0xed, 0x10, |
629d688d MW |
5998 | 0xf3, 0x10, 0x06, 0x12, 0x10, 0x12, 0x1e, 0x12, 0x0c, 0x13, 0x0e, 0x13, |
5999 | 0x10, 0x13, 0xfe, 0x9c, 0xf0, 0x35, 0x05, 0xfe, 0xec, 0x0e, 0xff, 0x10, | |
6000 | 0x00, 0x00, 0xe9, 0xfe, 0x34, 0x1f, 0x00, 0xe8, 0xfe, 0x88, 0x01, 0xff, | |
27c868c2 | 6001 | 0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00, |
629d688d MW |
6002 | 0x00, 0xfe, 0x57, 0x24, 0x00, 0xfe, 0x4c, 0x00, 0x65, 0xff, 0x04, 0x00, |
6003 | 0x00, 0x1a, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08, 0x01, 0x01, 0xff, 0x08, | |
6004 | 0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x13, | |
27c868c2 | 6005 | 0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00, |
629d688d MW |
6006 | 0xfe, 0x04, 0xf7, 0xe8, 0x37, 0x7d, 0x0d, 0x01, 0xfe, 0x4a, 0x11, 0xfe, |
6007 | 0x04, 0xf7, 0xe8, 0x7d, 0x0d, 0x51, 0x37, 0xfe, 0x3d, 0xf0, 0xfe, 0x0c, | |
6008 | 0x02, 0xfe, 0x20, 0xf0, 0xbc, 0xfe, 0x91, 0xf0, 0xfe, 0xf8, 0x01, 0xfe, | |
27c868c2 | 6009 | 0x90, 0xf0, 0xfe, 0xf8, 0x01, 0xfe, 0x8f, 0xf0, 0xbc, 0x03, 0x67, 0x4d, |
629d688d MW |
6010 | 0x05, 0xfe, 0x08, 0x0f, 0x01, 0xfe, 0x78, 0x0f, 0xfe, 0xdd, 0x12, 0x05, |
6011 | 0xfe, 0x0e, 0x03, 0xfe, 0x28, 0x1c, 0x03, 0xfe, 0xa6, 0x00, 0xfe, 0xd1, | |
6012 | 0x12, 0x3e, 0x22, 0xfe, 0xa6, 0x00, 0xac, 0xfe, 0x48, 0xf0, 0xfe, 0x90, | |
27c868c2 | 6013 | 0x02, 0xfe, 0x49, 0xf0, 0xfe, 0xaa, 0x02, 0xfe, 0x4a, 0xf0, 0xfe, 0xc8, |
629d688d MW |
6014 | 0x02, 0xfe, 0x46, 0xf0, 0xfe, 0x5a, 0x02, 0xfe, 0x47, 0xf0, 0xfe, 0x60, |
6015 | 0x02, 0xfe, 0x43, 0xf0, 0xfe, 0x4e, 0x02, 0xfe, 0x44, 0xf0, 0xfe, 0x52, | |
6016 | 0x02, 0xfe, 0x45, 0xf0, 0xfe, 0x56, 0x02, 0x1c, 0x0d, 0xa2, 0x1c, 0x07, | |
27c868c2 | 6017 | 0x22, 0xb7, 0x05, 0x35, 0xfe, 0x00, 0x1c, 0xfe, 0xf1, 0x10, 0xfe, 0x02, |
629d688d MW |
6018 | 0x1c, 0xf5, 0xfe, 0x1e, 0x1c, 0xfe, 0xe9, 0x10, 0x01, 0x5f, 0xfe, 0xe7, |
6019 | 0x10, 0xfe, 0x06, 0xfc, 0xde, 0x0a, 0x81, 0x01, 0xa3, 0x05, 0x35, 0x1f, | |
6020 | 0x95, 0x47, 0xb8, 0x01, 0xfe, 0xe4, 0x11, 0x0a, 0x81, 0x01, 0x5c, 0xfe, | |
27c868c2 | 6021 | 0xbd, 0x10, 0x0a, 0x81, 0x01, 0x5c, 0xfe, 0xad, 0x10, 0xfe, 0x16, 0x1c, |
629d688d MW |
6022 | 0xfe, 0x58, 0x1c, 0x1c, 0x07, 0x22, 0xb7, 0x37, 0x2a, 0x35, 0xfe, 0x3d, |
6023 | 0xf0, 0xfe, 0x0c, 0x02, 0x2b, 0xfe, 0x9e, 0x02, 0xfe, 0x5a, 0x1c, 0xfe, | |
6024 | 0x12, 0x1c, 0xfe, 0x14, 0x1c, 0x1f, 0xfe, 0x30, 0x00, 0x47, 0xb8, 0x01, | |
27c868c2 | 6025 | 0xfe, 0xd4, 0x11, 0x1c, 0x07, 0x22, 0xb7, 0x05, 0xe9, 0x21, 0x2c, 0x09, |
629d688d MW |
6026 | 0x1a, 0x31, 0xfe, 0x69, 0x10, 0x1c, 0x07, 0x22, 0xb7, 0xfe, 0x04, 0xec, |
6027 | 0x2c, 0x60, 0x01, 0xfe, 0x1e, 0x1e, 0x20, 0x2c, 0xfe, 0x05, 0xf6, 0xde, | |
6028 | 0x01, 0xfe, 0x62, 0x1b, 0x01, 0x0c, 0x61, 0x4a, 0x44, 0x15, 0x56, 0x51, | |
27c868c2 | 6029 | 0x01, 0xfe, 0x9e, 0x1e, 0x01, 0xfe, 0x96, 0x1a, 0x05, 0x35, 0x0a, 0x57, |
629d688d MW |
6030 | 0x01, 0x18, 0x09, 0x00, 0x36, 0x01, 0x85, 0xfe, 0x18, 0x10, 0xfe, 0x41, |
6031 | 0x58, 0x0a, 0xba, 0x01, 0x18, 0xfe, 0xc8, 0x54, 0x7b, 0xfe, 0x1c, 0x03, | |
6032 | 0x01, 0xfe, 0x96, 0x1a, 0x05, 0x35, 0x37, 0x60, 0xfe, 0x02, 0xe8, 0x30, | |
27c868c2 | 6033 | 0xfe, 0xbf, 0x57, 0xfe, 0x9e, 0x43, 0xfe, 0x77, 0x57, 0xfe, 0x27, 0xf0, |
629d688d MW |
6034 | 0xfe, 0xe4, 0x01, 0xfe, 0x07, 0x4b, 0xfe, 0x20, 0xf0, 0xbc, 0xfe, 0x40, |
6035 | 0x1c, 0x2a, 0xeb, 0xfe, 0x26, 0xf0, 0xfe, 0x66, 0x03, 0xfe, 0xa0, 0xf0, | |
6036 | 0xfe, 0x54, 0x03, 0xfe, 0x11, 0xf0, 0xbc, 0xfe, 0xef, 0x10, 0xfe, 0x9f, | |
27c868c2 | 6037 | 0xf0, 0xfe, 0x74, 0x03, 0xfe, 0x46, 0x1c, 0x19, 0xfe, 0x11, 0x00, 0x05, |
629d688d MW |
6038 | 0x70, 0x37, 0xfe, 0x48, 0x1c, 0xfe, 0x46, 0x1c, 0x01, 0x0c, 0x06, 0x28, |
6039 | 0xfe, 0x18, 0x13, 0x26, 0x21, 0xb9, 0xc7, 0x20, 0xb9, 0x0a, 0x57, 0x01, | |
6040 | 0x18, 0xc7, 0x89, 0x01, 0xfe, 0xc8, 0x1a, 0x15, 0xe1, 0x2a, 0xeb, 0xfe, | |
27c868c2 | 6041 | 0x01, 0xf0, 0xeb, 0xfe, 0x82, 0xf0, 0xfe, 0xa4, 0x03, 0xfe, 0x9c, 0x32, |
629d688d MW |
6042 | 0x15, 0xfe, 0xe4, 0x00, 0x2f, 0xfe, 0xb6, 0x03, 0x2a, 0x3c, 0x16, 0xfe, |
6043 | 0xc6, 0x03, 0x01, 0x41, 0xfe, 0x06, 0xf0, 0xfe, 0xd6, 0x03, 0xaf, 0xa0, | |
6044 | 0xfe, 0x0a, 0xf0, 0xfe, 0xa2, 0x07, 0x05, 0x29, 0x03, 0x81, 0x1e, 0x1b, | |
27c868c2 | 6045 | 0xfe, 0x24, 0x05, 0x1f, 0x63, 0x01, 0x42, 0x8f, 0xfe, 0x70, 0x02, 0x05, |
629d688d MW |
6046 | 0xea, 0xfe, 0x46, 0x1c, 0x37, 0x7d, 0x1d, 0xfe, 0x67, 0x1b, 0xfe, 0xbf, |
6047 | 0x57, 0xfe, 0x77, 0x57, 0xfe, 0x48, 0x1c, 0x75, 0x01, 0xa6, 0x86, 0x0a, | |
6048 | 0x57, 0x01, 0x18, 0x09, 0x00, 0x1b, 0xec, 0x0a, 0xe1, 0x01, 0x18, 0x77, | |
27c868c2 | 6049 | 0x50, 0x40, 0x8d, 0x30, 0x03, 0x81, 0x1e, 0xf8, 0x1f, 0x63, 0x01, 0x42, |
629d688d MW |
6050 | 0x8f, 0xfe, 0x70, 0x02, 0x05, 0xea, 0xd7, 0x99, 0xd8, 0x9c, 0x2a, 0x29, |
6051 | 0x2f, 0xfe, 0x4e, 0x04, 0x16, 0xfe, 0x4a, 0x04, 0x7e, 0xfe, 0xa0, 0x00, | |
6052 | 0xfe, 0x9b, 0x57, 0xfe, 0x54, 0x12, 0x32, 0xff, 0x02, 0x00, 0x10, 0x01, | |
27c868c2 | 6053 | 0x08, 0x16, 0xfe, 0x02, 0x05, 0x32, 0x01, 0x08, 0x16, 0x29, 0x27, 0x25, |
629d688d MW |
6054 | 0xee, 0xfe, 0x4c, 0x44, 0xfe, 0x58, 0x12, 0x50, 0xfe, 0x44, 0x48, 0x13, |
6055 | 0x34, 0xfe, 0x4c, 0x54, 0x7b, 0xec, 0x60, 0x8d, 0x30, 0x01, 0xfe, 0x4e, | |
6056 | 0x1e, 0xfe, 0x48, 0x47, 0xfe, 0x7c, 0x13, 0x01, 0x0c, 0x06, 0x28, 0xfe, | |
27c868c2 | 6057 | 0x32, 0x13, 0x01, 0x43, 0x09, 0x9b, 0xfe, 0x68, 0x13, 0xfe, 0x26, 0x10, |
629d688d MW |
6058 | 0x13, 0x34, 0xfe, 0x4c, 0x54, 0x7b, 0xec, 0x01, 0xfe, 0x4e, 0x1e, 0xfe, |
6059 | 0x48, 0x47, 0xfe, 0x54, 0x13, 0x01, 0x0c, 0x06, 0x28, 0xa5, 0x01, 0x43, | |
6060 | 0x09, 0x9b, 0xfe, 0x40, 0x13, 0x01, 0x0c, 0x06, 0x28, 0xf9, 0x1f, 0x7f, | |
27c868c2 | 6061 | 0x01, 0x0c, 0x06, 0x07, 0x4d, 0x1f, 0xfe, 0x0d, 0x00, 0x01, 0x42, 0x8f, |
629d688d MW |
6062 | 0xfe, 0xa4, 0x0e, 0x05, 0x29, 0x32, 0x15, 0xfe, 0xe6, 0x00, 0x0f, 0xfe, |
6063 | 0x1c, 0x90, 0x04, 0xfe, 0x9c, 0x93, 0x3a, 0x0b, 0x0e, 0x8b, 0x02, 0x1f, | |
6064 | 0x7f, 0x01, 0x42, 0x05, 0x35, 0xfe, 0x42, 0x5b, 0x7d, 0x1d, 0xfe, 0x46, | |
27c868c2 | 6065 | 0x59, 0xfe, 0xbf, 0x57, 0xfe, 0x77, 0x57, 0x0f, 0xfe, 0x87, 0x80, 0x04, |
629d688d MW |
6066 | 0xfe, 0x87, 0x83, 0xfe, 0xc9, 0x47, 0x0b, 0x0e, 0xd0, 0x65, 0x01, 0x0c, |
6067 | 0x06, 0x0d, 0xfe, 0x98, 0x13, 0x0f, 0xfe, 0x20, 0x80, 0x04, 0xfe, 0xa0, | |
6068 | 0x83, 0x33, 0x0b, 0x0e, 0x09, 0x1d, 0xfe, 0x84, 0x12, 0x01, 0x38, 0x06, | |
27c868c2 | 6069 | 0x07, 0xfe, 0x70, 0x13, 0x03, 0xfe, 0xa2, 0x00, 0x1e, 0x1b, 0xfe, 0xda, |
629d688d MW |
6070 | 0x05, 0xd0, 0x54, 0x01, 0x38, 0x06, 0x0d, 0xfe, 0x58, 0x13, 0x03, 0xfe, |
6071 | 0xa0, 0x00, 0x1e, 0xfe, 0x50, 0x12, 0x5e, 0xff, 0x02, 0x00, 0x10, 0x2f, | |
6072 | 0xfe, 0x90, 0x05, 0x2a, 0x3c, 0xcc, 0xff, 0x02, 0x00, 0x10, 0x2f, 0xfe, | |
27c868c2 | 6073 | 0x9e, 0x05, 0x17, 0xfe, 0xf4, 0x05, 0x15, 0xfe, 0xe3, 0x00, 0x26, 0x01, |
629d688d MW |
6074 | 0x38, 0xfe, 0x4a, 0xf0, 0xfe, 0xc0, 0x05, 0xfe, 0x49, 0xf0, 0xfe, 0xba, |
6075 | 0x05, 0x71, 0x2e, 0xfe, 0x21, 0x00, 0xf1, 0x2e, 0xfe, 0x22, 0x00, 0xa2, | |
6076 | 0x2e, 0x4a, 0xfe, 0x09, 0x48, 0xff, 0x02, 0x00, 0x10, 0x2f, 0xfe, 0xd0, | |
27c868c2 | 6077 | 0x05, 0x17, 0xfe, 0xf4, 0x05, 0xfe, 0xe2, 0x08, 0x01, 0x38, 0x06, 0xfe, |
629d688d MW |
6078 | 0x1c, 0x00, 0x4d, 0x01, 0xa7, 0x2e, 0x07, 0x20, 0xe4, 0x47, 0xfe, 0x27, |
6079 | 0x01, 0x01, 0x0c, 0x06, 0x28, 0xfe, 0x24, 0x12, 0x3e, 0x01, 0x84, 0x1f, | |
6080 | 0x7f, 0x01, 0x0c, 0x06, 0x07, 0x4d, 0x1f, 0xfe, 0x0d, 0x00, 0x01, 0x42, | |
27c868c2 | 6081 | 0x8f, 0xfe, 0xa4, 0x0e, 0x05, 0x29, 0x03, 0xe6, 0x1e, 0xfe, 0xca, 0x13, |
629d688d MW |
6082 | 0x03, 0xb6, 0x1e, 0xfe, 0x40, 0x12, 0x03, 0x66, 0x1e, 0xfe, 0x38, 0x13, |
6083 | 0x3e, 0x01, 0x84, 0x17, 0xfe, 0x72, 0x06, 0x0a, 0x07, 0x01, 0x38, 0x06, | |
6084 | 0x24, 0xfe, 0x02, 0x12, 0x4f, 0x01, 0xfe, 0x56, 0x19, 0x16, 0xfe, 0x68, | |
27c868c2 | 6085 | 0x06, 0x15, 0x82, 0x01, 0x41, 0x15, 0xe2, 0x03, 0x66, 0x8a, 0x10, 0x66, |
629d688d MW |
6086 | 0x03, 0x9a, 0x1e, 0xfe, 0x70, 0x12, 0x03, 0x55, 0x1e, 0xfe, 0x68, 0x13, |
6087 | 0x01, 0xc6, 0x09, 0x12, 0x48, 0xfe, 0x92, 0x06, 0x2e, 0x12, 0x01, 0xfe, | |
6088 | 0xac, 0x1d, 0xfe, 0x43, 0x48, 0x62, 0x80, 0x13, 0x58, 0xff, 0x02, 0x00, | |
27c868c2 | 6089 | 0x57, 0x52, 0xad, 0x23, 0x3f, 0x4e, 0x62, 0x49, 0x3e, 0x01, 0x84, 0x17, |
629d688d MW |
6090 | 0xfe, 0xea, 0x06, 0x01, 0x38, 0x06, 0x12, 0xf7, 0x45, 0x0a, 0x95, 0x01, |
6091 | 0xfe, 0x84, 0x19, 0x16, 0xfe, 0xe0, 0x06, 0x15, 0x82, 0x01, 0x41, 0x15, | |
6092 | 0xe2, 0x03, 0x55, 0x8a, 0x10, 0x55, 0x1c, 0x07, 0x01, 0x84, 0xfe, 0xae, | |
27c868c2 | 6093 | 0x10, 0x03, 0x6f, 0x1e, 0xfe, 0x9e, 0x13, 0x3e, 0x01, 0x84, 0x03, 0x9a, |
629d688d MW |
6094 | 0x1e, 0xfe, 0x1a, 0x12, 0x01, 0x38, 0x06, 0x12, 0xfc, 0x01, 0xc6, 0x01, |
6095 | 0xfe, 0xac, 0x1d, 0xfe, 0x43, 0x48, 0x62, 0x80, 0xf0, 0x45, 0x0a, 0x95, | |
6096 | 0x03, 0xb6, 0x1e, 0xf8, 0x01, 0x38, 0x06, 0x24, 0x36, 0xfe, 0x02, 0xf6, | |
27c868c2 | 6097 | 0x07, 0x71, 0x78, 0x8c, 0x00, 0x4d, 0x62, 0x49, 0x3e, 0x2d, 0x93, 0x4e, |
629d688d MW |
6098 | 0xd0, 0x0d, 0x17, 0xfe, 0x9a, 0x07, 0x01, 0xfe, 0xc0, 0x19, 0x16, 0xfe, |
6099 | 0x90, 0x07, 0x26, 0x20, 0x9e, 0x15, 0x82, 0x01, 0x41, 0x15, 0xe2, 0x21, | |
6100 | 0x9e, 0x09, 0x07, 0xfb, 0x03, 0xe6, 0xfe, 0x58, 0x57, 0x10, 0xe6, 0x05, | |
27c868c2 | 6101 | 0xfe, 0x2a, 0x06, 0x03, 0x6f, 0x8a, 0x10, 0x6f, 0x1c, 0x07, 0x01, 0x84, |
629d688d MW |
6102 | 0xfe, 0x9c, 0x32, 0x5f, 0x75, 0x01, 0xa6, 0x86, 0x15, 0xfe, 0xe2, 0x00, |
6103 | 0x2f, 0xed, 0x2a, 0x3c, 0xfe, 0x0a, 0xf0, 0xfe, 0xce, 0x07, 0xae, 0xfe, | |
6104 | 0x96, 0x08, 0xfe, 0x06, 0xf0, 0xfe, 0x9e, 0x08, 0xaf, 0xa0, 0x05, 0x29, | |
27c868c2 | 6105 | 0x01, 0x0c, 0x06, 0x0d, 0xfe, 0x2e, 0x12, 0x14, 0x1d, 0x01, 0x08, 0x14, |
629d688d MW |
6106 | 0x00, 0x01, 0x08, 0x14, 0x00, 0x01, 0x08, 0x14, 0x00, 0x01, 0x08, 0xfe, |
6107 | 0x99, 0xa4, 0x01, 0x08, 0x14, 0x00, 0x05, 0xfe, 0xc6, 0x09, 0x01, 0x76, | |
6108 | 0x06, 0x12, 0xfe, 0x3a, 0x12, 0x01, 0x0c, 0x06, 0x12, 0xfe, 0x30, 0x13, | |
27c868c2 | 6109 | 0x14, 0xfe, 0x1b, 0x00, 0x01, 0x08, 0x14, 0x00, 0x01, 0x08, 0x14, 0x00, |
629d688d MW |
6110 | 0x01, 0x08, 0x14, 0x00, 0x01, 0x08, 0x14, 0x07, 0x01, 0x08, 0x14, 0x00, |
6111 | 0x05, 0xef, 0x7c, 0x4a, 0x78, 0x4f, 0x0f, 0xfe, 0x9a, 0x81, 0x04, 0xfe, | |
6112 | 0x9a, 0x83, 0xfe, 0xcb, 0x47, 0x0b, 0x0e, 0x2d, 0x28, 0x48, 0xfe, 0x6c, | |
27c868c2 | 6113 | 0x08, 0x0a, 0x28, 0xfe, 0x09, 0x6f, 0xca, 0xfe, 0xca, 0x45, 0xfe, 0x32, |
629d688d MW |
6114 | 0x12, 0x53, 0x63, 0x4e, 0x7c, 0x97, 0x2f, 0xfe, 0x7e, 0x08, 0x2a, 0x3c, |
6115 | 0xfe, 0x0a, 0xf0, 0xfe, 0x6c, 0x08, 0xaf, 0xa0, 0xae, 0xfe, 0x96, 0x08, | |
6116 | 0x05, 0x29, 0x01, 0x41, 0x05, 0xed, 0x14, 0x24, 0x05, 0xed, 0xfe, 0x9c, | |
27c868c2 | 6117 | 0xf7, 0x9f, 0x01, 0xfe, 0xae, 0x1e, 0xfe, 0x18, 0x58, 0x01, 0xfe, 0xbe, |
629d688d MW |
6118 | 0x1e, 0xfe, 0x99, 0x58, 0xfe, 0x78, 0x18, 0xfe, 0xf9, 0x18, 0x8e, 0xfe, |
6119 | 0x16, 0x09, 0x10, 0x6a, 0x22, 0x6b, 0x01, 0x0c, 0x61, 0x54, 0x44, 0x21, | |
6120 | 0x2c, 0x09, 0x1a, 0xf8, 0x77, 0x01, 0xfe, 0x7e, 0x1e, 0x47, 0x2c, 0x7a, | |
27c868c2 | 6121 | 0x30, 0xf0, 0xfe, 0x83, 0xe7, 0xfe, 0x3f, 0x00, 0x71, 0xfe, 0x03, 0x40, |
629d688d MW |
6122 | 0x01, 0x0c, 0x61, 0x65, 0x44, 0x01, 0xc2, 0xc8, 0xfe, 0x1f, 0x40, 0x20, |
6123 | 0x6e, 0x01, 0xfe, 0x6a, 0x16, 0xfe, 0x08, 0x50, 0xfe, 0x8a, 0x50, 0xfe, | |
6124 | 0x44, 0x51, 0xfe, 0xc6, 0x51, 0xfe, 0x10, 0x10, 0x01, 0xfe, 0xce, 0x1e, | |
27c868c2 | 6125 | 0x01, 0xfe, 0xde, 0x1e, 0x10, 0x68, 0x22, 0x69, 0x01, 0xfe, 0xee, 0x1e, |
629d688d MW |
6126 | 0x01, 0xfe, 0xfe, 0x1e, 0xfe, 0x40, 0x50, 0xfe, 0xc2, 0x50, 0x10, 0x4b, |
6127 | 0x22, 0x4c, 0xfe, 0x8a, 0x10, 0x01, 0x0c, 0x06, 0x54, 0xfe, 0x50, 0x12, | |
6128 | 0x01, 0xfe, 0xae, 0x1e, 0x01, 0xfe, 0xbe, 0x1e, 0x10, 0x6a, 0x22, 0x6b, | |
27c868c2 | 6129 | 0x01, 0x0c, 0x06, 0x65, 0x4e, 0x01, 0xc2, 0x0f, 0xfe, 0x1f, 0x80, 0x04, |
629d688d MW |
6130 | 0xfe, 0x9f, 0x83, 0x33, 0x0b, 0x0e, 0x20, 0x6e, 0x0f, 0xfe, 0x44, 0x90, |
6131 | 0x04, 0xfe, 0xc4, 0x93, 0x3a, 0x0b, 0xfe, 0xc6, 0x90, 0x04, 0xfe, 0xc6, | |
6132 | 0x93, 0x79, 0x0b, 0x0e, 0x10, 0x6c, 0x22, 0x6d, 0x01, 0xfe, 0xce, 0x1e, | |
27c868c2 | 6133 | 0x01, 0xfe, 0xde, 0x1e, 0x10, 0x68, 0x22, 0x69, 0x0f, 0xfe, 0x40, 0x90, |
629d688d MW |
6134 | 0x04, 0xfe, 0xc0, 0x93, 0x3a, 0x0b, 0xfe, 0xc2, 0x90, 0x04, 0xfe, 0xc2, |
6135 | 0x93, 0x79, 0x0b, 0x0e, 0x10, 0x4b, 0x22, 0x4c, 0x10, 0x64, 0x22, 0x34, | |
6136 | 0x01, 0x0c, 0x61, 0x24, 0x44, 0x37, 0x13, 0xfe, 0x4e, 0x11, 0x2f, 0xfe, | |
27c868c2 | 6137 | 0xde, 0x09, 0xfe, 0x9e, 0xf0, 0xfe, 0xf2, 0x09, 0xfe, 0x01, 0x48, 0x1b, |
629d688d MW |
6138 | 0x3c, 0x37, 0x88, 0xf5, 0xd4, 0xfe, 0x1e, 0x0a, 0xd5, 0xfe, 0x42, 0x0a, |
6139 | 0xd2, 0xfe, 0x1e, 0x0a, 0xd3, 0xfe, 0x42, 0x0a, 0xae, 0xfe, 0x12, 0x0a, | |
6140 | 0xfe, 0x06, 0xf0, 0xfe, 0x18, 0x0a, 0xaf, 0xa0, 0x05, 0x29, 0x01, 0x41, | |
27c868c2 | 6141 | 0xfe, 0xc1, 0x10, 0x14, 0x24, 0xfe, 0xc1, 0x10, 0x01, 0x76, 0x06, 0x07, |
629d688d MW |
6142 | 0xfe, 0x14, 0x12, 0x01, 0x76, 0x06, 0x0d, 0x5d, 0x01, 0x0c, 0x06, 0x0d, |
6143 | 0xfe, 0x74, 0x12, 0xfe, 0x2e, 0x1c, 0x05, 0xfe, 0x1a, 0x0c, 0x01, 0x76, | |
6144 | 0x06, 0x07, 0x5d, 0x01, 0x76, 0x06, 0x0d, 0x41, 0xfe, 0x2c, 0x1c, 0xfe, | |
27c868c2 | 6145 | 0xaa, 0xf0, 0xfe, 0xce, 0x0a, 0xfe, 0xac, 0xf0, 0xfe, 0x66, 0x0a, 0xfe, |
629d688d MW |
6146 | 0x92, 0x10, 0xc4, 0xf6, 0xfe, 0xad, 0xf0, 0xfe, 0x72, 0x0a, 0x05, 0xfe, |
6147 | 0x1a, 0x0c, 0xc5, 0xfe, 0xe7, 0x10, 0xfe, 0x2b, 0xf0, 0xbf, 0xfe, 0x6b, | |
6148 | 0x18, 0x23, 0xfe, 0x00, 0xfe, 0xfe, 0x1c, 0x12, 0xac, 0xfe, 0xd2, 0xf0, | |
27c868c2 | 6149 | 0xbf, 0xfe, 0x76, 0x18, 0x23, 0x1d, 0x1b, 0xbf, 0x03, 0xe3, 0x23, 0x07, |
629d688d MW |
6150 | 0x1b, 0xbf, 0xd4, 0x5b, 0xd5, 0x5b, 0xd2, 0x5b, 0xd3, 0x5b, 0xc4, 0xc5, |
6151 | 0xfe, 0xa9, 0x10, 0x75, 0x5e, 0x32, 0x1f, 0x7f, 0x01, 0x42, 0x19, 0xfe, | |
6152 | 0x35, 0x00, 0xfe, 0x01, 0xf0, 0x70, 0x19, 0x98, 0x05, 0x70, 0xfe, 0x74, | |
27c868c2 | 6153 | 0x18, 0x23, 0xfe, 0x00, 0xf8, 0x1b, 0x5b, 0x7d, 0x12, 0x01, 0xfe, 0x78, |
629d688d MW |
6154 | 0x0f, 0x4d, 0x01, 0xfe, 0x96, 0x1a, 0x21, 0x30, 0x77, 0x7d, 0x1d, 0x05, |
6155 | 0x5b, 0x01, 0x0c, 0x06, 0x0d, 0x2b, 0xfe, 0xe2, 0x0b, 0x01, 0x0c, 0x06, | |
6156 | 0x54, 0xfe, 0xa6, 0x12, 0x01, 0x0c, 0x06, 0x24, 0xfe, 0x88, 0x13, 0x21, | |
27c868c2 | 6157 | 0x6e, 0xc7, 0x01, 0xfe, 0x1e, 0x1f, 0x0f, 0xfe, 0x83, 0x80, 0x04, 0xfe, |
629d688d MW |
6158 | 0x83, 0x83, 0xfe, 0xc9, 0x47, 0x0b, 0x0e, 0xfe, 0xc8, 0x44, 0xfe, 0x42, |
6159 | 0x13, 0x0f, 0xfe, 0x04, 0x91, 0x04, 0xfe, 0x84, 0x93, 0xfe, 0xca, 0x57, | |
6160 | 0x0b, 0xfe, 0x86, 0x91, 0x04, 0xfe, 0x86, 0x93, 0xfe, 0xcb, 0x57, 0x0b, | |
27c868c2 | 6161 | 0x0e, 0x7a, 0x30, 0xfe, 0x40, 0x59, 0xfe, 0xc1, 0x59, 0x8e, 0x40, 0x03, |
629d688d MW |
6162 | 0x6a, 0x3b, 0x6b, 0x10, 0x97, 0x22, 0x98, 0xd9, 0x6a, 0xda, 0x6b, 0x01, |
6163 | 0xc2, 0xc8, 0x7a, 0x30, 0x20, 0x6e, 0xdb, 0x64, 0xdc, 0x34, 0x91, 0x6c, | |
6164 | 0x7e, 0x6d, 0xfe, 0x44, 0x55, 0xfe, 0xe5, 0x55, 0xfe, 0x04, 0xfa, 0x64, | |
27c868c2 | 6165 | 0xfe, 0x05, 0xfa, 0x34, 0x01, 0xfe, 0x6a, 0x16, 0xa3, 0x26, 0x10, 0x97, |
629d688d MW |
6166 | 0x10, 0x98, 0x91, 0x6c, 0x7e, 0x6d, 0xfe, 0x14, 0x10, 0x01, 0x0c, 0x06, |
6167 | 0x24, 0x1b, 0x40, 0x91, 0x4b, 0x7e, 0x4c, 0x01, 0x0c, 0x06, 0xfe, 0xf7, | |
6168 | 0x00, 0x44, 0x03, 0x68, 0x3b, 0x69, 0xfe, 0x10, 0x58, 0xfe, 0x91, 0x58, | |
27c868c2 | 6169 | 0xfe, 0x14, 0x59, 0xfe, 0x95, 0x59, 0x05, 0x5b, 0x01, 0x0c, 0x06, 0x24, |
629d688d MW |
6170 | 0x1b, 0x40, 0x01, 0x0c, 0x06, 0xfe, 0xf7, 0x00, 0x44, 0x78, 0x01, 0xfe, |
6171 | 0x8e, 0x1e, 0x4f, 0x0f, 0xfe, 0x10, 0x90, 0x04, 0xfe, 0x90, 0x93, 0x3a, | |
6172 | 0x0b, 0xfe, 0x92, 0x90, 0x04, 0xfe, 0x92, 0x93, 0x79, 0x0b, 0x0e, 0xfe, | |
27c868c2 | 6173 | 0xbd, 0x10, 0x01, 0x43, 0x09, 0xbb, 0x1b, 0xfe, 0x6e, 0x0a, 0x15, 0xbb, |
629d688d MW |
6174 | 0x01, 0x0c, 0x06, 0x0d, 0xfe, 0x14, 0x13, 0x03, 0x4b, 0x3b, 0x4c, 0x8e, |
6175 | 0xfe, 0x6e, 0x0a, 0xfe, 0x0c, 0x58, 0xfe, 0x8d, 0x58, 0x05, 0x5b, 0x26, | |
6176 | 0x3e, 0x0f, 0xfe, 0x19, 0x80, 0x04, 0xfe, 0x99, 0x83, 0x33, 0x0b, 0x0e, | |
27c868c2 | 6177 | 0xfe, 0xe5, 0x10, 0x01, 0x0c, 0x06, 0x0d, 0xfe, 0x1a, 0x12, 0xfe, 0x6c, |
629d688d MW |
6178 | 0x19, 0xfe, 0x19, 0x41, 0xfe, 0x6b, 0x18, 0xac, 0xfe, 0xd1, 0xf0, 0xef, |
6179 | 0x1f, 0x92, 0x01, 0x42, 0x19, 0xfe, 0x44, 0x00, 0xfe, 0x90, 0x10, 0xfe, | |
6180 | 0x6c, 0x19, 0xd9, 0x4b, 0xfe, 0xed, 0x19, 0xda, 0x4c, 0xfe, 0x0c, 0x51, | |
27c868c2 | 6181 | 0xfe, 0x8e, 0x51, 0xfe, 0x6b, 0x18, 0x23, 0xfe, 0x00, 0xff, 0x31, 0xfe, |
629d688d MW |
6182 | 0x76, 0x10, 0xac, 0xfe, 0xd2, 0xf0, 0xfe, 0xba, 0x0c, 0xfe, 0x76, 0x18, |
6183 | 0x23, 0x1d, 0x5d, 0x03, 0xe3, 0x23, 0x07, 0xfe, 0x08, 0x13, 0x19, 0xfe, | |
6184 | 0x16, 0x00, 0x05, 0x70, 0xfe, 0xd1, 0xf0, 0xfe, 0xcc, 0x0c, 0x1f, 0x92, | |
27c868c2 | 6185 | 0x01, 0x42, 0x19, 0xfe, 0x17, 0x00, 0x5c, 0xfe, 0xce, 0xf0, 0xfe, 0xd2, |
629d688d MW |
6186 | 0x0c, 0xfe, 0x3e, 0x10, 0xfe, 0xcd, 0xf0, 0xfe, 0xde, 0x0c, 0x19, 0xfe, |
6187 | 0x22, 0x00, 0x05, 0x70, 0xfe, 0xcb, 0xf0, 0xfe, 0xea, 0x0c, 0x19, 0xfe, | |
6188 | 0x24, 0x00, 0x05, 0x70, 0xfe, 0xd0, 0xf0, 0xfe, 0xf4, 0x0c, 0x19, 0x94, | |
27c868c2 | 6189 | 0xfe, 0x1c, 0x10, 0xfe, 0xcf, 0xf0, 0xfe, 0xfe, 0x0c, 0x19, 0x4a, 0xf3, |
629d688d MW |
6190 | 0xfe, 0xcc, 0xf0, 0xef, 0x01, 0x76, 0x06, 0x24, 0x4d, 0x19, 0xfe, 0x12, |
6191 | 0x00, 0x37, 0x13, 0xfe, 0x4e, 0x11, 0x2f, 0xfe, 0x16, 0x0d, 0xfe, 0x9e, | |
6192 | 0xf0, 0xfe, 0x2a, 0x0d, 0xfe, 0x01, 0x48, 0x1b, 0x3c, 0x37, 0x88, 0xf5, | |
27c868c2 | 6193 | 0xd4, 0x29, 0xd5, 0x29, 0xd2, 0x29, 0xd3, 0x29, 0x37, 0xfe, 0x9c, 0x32, |
629d688d MW |
6194 | 0x2f, 0xfe, 0x3e, 0x0d, 0x2a, 0x3c, 0xae, 0xfe, 0x62, 0x0d, 0xaf, 0xa0, |
6195 | 0xd4, 0x9f, 0xd5, 0x9f, 0xd2, 0x9f, 0xd3, 0x9f, 0x05, 0x29, 0x01, 0x41, | |
6196 | 0xfe, 0xd3, 0x10, 0x15, 0xfe, 0xe8, 0x00, 0xc4, 0xc5, 0x75, 0xd7, 0x99, | |
27c868c2 | 6197 | 0xd8, 0x9c, 0xfe, 0x89, 0xf0, 0x29, 0x27, 0x25, 0xbe, 0xd7, 0x99, 0xd8, |
629d688d MW |
6198 | 0x9c, 0x2f, 0xfe, 0x8c, 0x0d, 0x16, 0x29, 0x27, 0x25, 0xbd, 0xfe, 0x01, |
6199 | 0x48, 0xa4, 0x19, 0xfe, 0x42, 0x00, 0x05, 0x70, 0x90, 0x07, 0xfe, 0x81, | |
6200 | 0x49, 0x1b, 0xfe, 0x64, 0x0e, 0x01, 0x0c, 0x06, 0x0d, 0xfe, 0x44, 0x13, | |
27c868c2 | 6201 | 0x19, 0x00, 0x2d, 0x0d, 0xfe, 0x54, 0x12, 0x2d, 0xfe, 0x28, 0x00, 0x2b, |
629d688d MW |
6202 | 0xfe, 0xda, 0x0e, 0x0a, 0x57, 0x01, 0x18, 0x09, 0x00, 0x36, 0x46, 0xfe, |
6203 | 0x28, 0x00, 0xfe, 0xfa, 0x10, 0x01, 0xfe, 0xf4, 0x1c, 0x01, 0xfe, 0x00, | |
6204 | 0x1d, 0x0a, 0xba, 0x01, 0xfe, 0x58, 0x10, 0x40, 0x15, 0x56, 0x01, 0x85, | |
27c868c2 | 6205 | 0x05, 0x35, 0x19, 0xfe, 0x44, 0x00, 0x2d, 0x0d, 0xf7, 0x46, 0x0d, 0xfe, |
629d688d MW |
6206 | 0xcc, 0x10, 0x01, 0xa7, 0x46, 0x0d, 0xfe, 0xc2, 0x10, 0x01, 0xa7, 0x0f, |
6207 | 0xfe, 0x19, 0x82, 0x04, 0xfe, 0x99, 0x83, 0xfe, 0xcc, 0x47, 0x0b, 0x0e, | |
6208 | 0xfe, 0x34, 0x46, 0xa5, 0x46, 0x0d, 0x19, 0xfe, 0x43, 0x00, 0xfe, 0xa2, | |
27c868c2 | 6209 | 0x10, 0x01, 0x0c, 0x61, 0x0d, 0x44, 0x01, 0xfe, 0xf4, 0x1c, 0x01, 0xfe, |
629d688d MW |
6210 | 0x00, 0x1d, 0x40, 0x15, 0x56, 0x01, 0x85, 0x7d, 0x0d, 0x40, 0x51, 0x01, |
6211 | 0xfe, 0x9e, 0x1e, 0x05, 0xfe, 0x3a, 0x03, 0x01, 0x0c, 0x06, 0x0d, 0x5d, | |
6212 | 0x46, 0x0d, 0x19, 0x00, 0xfe, 0x62, 0x10, 0x01, 0x76, 0x06, 0x12, 0xfe, | |
27c868c2 | 6213 | 0x5c, 0x12, 0x01, 0x0c, 0x06, 0x12, 0xfe, 0x52, 0x13, 0xfe, 0x1c, 0x1c, |
629d688d MW |
6214 | 0xfe, 0x9d, 0xf0, 0xfe, 0x8e, 0x0e, 0xfe, 0x1c, 0x1c, 0xfe, 0x9d, 0xf0, |
6215 | 0xfe, 0x94, 0x0e, 0x01, 0x0c, 0x61, 0x12, 0x44, 0xfe, 0x9f, 0x10, 0x19, | |
6216 | 0xfe, 0x15, 0x00, 0xfe, 0x04, 0xe6, 0x0d, 0x4f, 0xfe, 0x2e, 0x10, 0x19, | |
27c868c2 | 6217 | 0xfe, 0x13, 0x00, 0xfe, 0x10, 0x10, 0x19, 0xfe, 0x47, 0x00, 0xf1, 0x19, |
629d688d MW |
6218 | 0xfe, 0x41, 0x00, 0xa2, 0x19, 0xfe, 0x24, 0x00, 0x86, 0xc4, 0xc5, 0x75, |
6219 | 0x03, 0x81, 0x1e, 0x2b, 0xea, 0x4f, 0xfe, 0x04, 0xe6, 0x12, 0xfe, 0x9d, | |
6220 | 0x41, 0xfe, 0x1c, 0x42, 0x40, 0x01, 0xf4, 0x05, 0x35, 0xfe, 0x12, 0x1c, | |
27c868c2 | 6221 | 0x1f, 0x0d, 0x47, 0xb5, 0xc3, 0x1f, 0xfe, 0x31, 0x00, 0x47, 0xb8, 0x01, |
629d688d MW |
6222 | 0xfe, 0xd4, 0x11, 0x05, 0xe9, 0x51, 0xfe, 0x06, 0xec, 0xe0, 0xfe, 0x0e, |
6223 | 0x47, 0x46, 0x28, 0xfe, 0xce, 0x45, 0x31, 0x51, 0xfe, 0x06, 0xea, 0xe0, | |
6224 | 0xfe, 0x47, 0x4b, 0x45, 0xfe, 0x75, 0x57, 0x03, 0x67, 0xfe, 0x98, 0x56, | |
27c868c2 | 6225 | 0xfe, 0x38, 0x12, 0x0a, 0x5a, 0x01, 0x18, 0xfe, 0x44, 0x48, 0x60, 0x01, |
629d688d MW |
6226 | 0x0c, 0x06, 0x28, 0xfe, 0x18, 0x13, 0x0a, 0x57, 0x01, 0x18, 0x3e, 0xfe, |
6227 | 0x41, 0x58, 0x0a, 0xba, 0xfe, 0xfa, 0x14, 0xfe, 0x49, 0x54, 0xb0, 0xfe, | |
6228 | 0x5e, 0x0f, 0x05, 0xfe, 0x3a, 0x03, 0x0a, 0x67, 0xfe, 0xe0, 0x14, 0xfe, | |
27c868c2 | 6229 | 0x0e, 0x47, 0x46, 0x28, 0xfe, 0xce, 0x45, 0x31, 0x51, 0xfe, 0xce, 0x47, |
629d688d MW |
6230 | 0xfe, 0xad, 0x13, 0x05, 0x35, 0x21, 0x2c, 0x09, 0x1a, 0xfe, 0x98, 0x12, |
6231 | 0x26, 0x20, 0x96, 0x20, 0xe7, 0xfe, 0x08, 0x1c, 0xfe, 0x7c, 0x19, 0xfe, | |
6232 | 0xfd, 0x19, 0xfe, 0x0a, 0x1c, 0x03, 0xe5, 0xfe, 0x48, 0x55, 0xa5, 0x3b, | |
27c868c2 | 6233 | 0xfe, 0x62, 0x01, 0xfe, 0xc9, 0x55, 0x31, 0xfe, 0x74, 0x10, 0x01, 0xfe, |
629d688d MW |
6234 | 0xf0, 0x1a, 0x03, 0xfe, 0x38, 0x01, 0x3b, 0xfe, 0x3a, 0x01, 0x8e, 0xfe, |
6235 | 0x1e, 0x10, 0xfe, 0x02, 0xec, 0xe7, 0x53, 0x00, 0x36, 0xfe, 0x04, 0xec, | |
6236 | 0x2c, 0x60, 0xfe, 0x05, 0xf6, 0xfe, 0x34, 0x01, 0x01, 0xfe, 0x62, 0x1b, | |
27c868c2 | 6237 | 0x01, 0xfe, 0xce, 0x1e, 0xb2, 0x11, 0xfe, 0x18, 0x13, 0xca, 0xfe, 0x02, |
629d688d MW |
6238 | 0xea, 0xe7, 0x53, 0x92, 0xfe, 0xc3, 0x13, 0x1f, 0x12, 0x47, 0xb5, 0xc3, |
6239 | 0xfe, 0x2a, 0x10, 0x03, 0xfe, 0x38, 0x01, 0x23, 0xfe, 0xf0, 0xff, 0x10, | |
6240 | 0xe5, 0x03, 0xfe, 0x3a, 0x01, 0x10, 0xfe, 0x62, 0x01, 0x01, 0xfe, 0x1e, | |
27c868c2 | 6241 | 0x1e, 0x20, 0x2c, 0x15, 0x56, 0x01, 0xfe, 0x9e, 0x1e, 0x13, 0x07, 0x02, |
629d688d MW |
6242 | 0x26, 0x02, 0x21, 0x96, 0xc7, 0x20, 0x96, 0x09, 0x92, 0xfe, 0x79, 0x13, |
6243 | 0x1f, 0x1d, 0x47, 0xb5, 0xc3, 0xfe, 0xe1, 0x10, 0xcf, 0xfe, 0x03, 0xdc, | |
6244 | 0xfe, 0x73, 0x57, 0xfe, 0x80, 0x5d, 0x02, 0xcf, 0xfe, 0x03, 0xdc, 0xfe, | |
27c868c2 | 6245 | 0x5b, 0x57, 0xfe, 0x80, 0x5d, 0x02, 0xfe, 0x03, 0x57, 0xcf, 0x26, 0xfe, |
629d688d MW |
6246 | 0x00, 0xcc, 0x02, 0xfe, 0x03, 0x57, 0xcf, 0x89, 0x02, 0x01, 0x0c, 0x06, |
6247 | 0x4a, 0xfe, 0x4e, 0x13, 0x0f, 0xfe, 0x1c, 0x80, 0x04, 0xfe, 0x9c, 0x83, | |
6248 | 0x33, 0x0b, 0x0e, 0x09, 0x07, 0xfe, 0x3a, 0x13, 0x0f, 0xfe, 0x1e, 0x80, | |
27c868c2 | 6249 | 0x04, 0xfe, 0x9e, 0x83, 0x33, 0x0b, 0x0e, 0xfe, 0x2a, 0x13, 0x0f, 0xfe, |
629d688d MW |
6250 | 0x1d, 0x80, 0x04, 0xfe, 0x9d, 0x83, 0xfe, 0xf9, 0x13, 0x0e, 0xfe, 0x1c, |
6251 | 0x13, 0x01, 0xfe, 0xee, 0x1e, 0xac, 0xfe, 0x14, 0x13, 0x01, 0xfe, 0xfe, | |
6252 | 0x1e, 0xfe, 0x81, 0x58, 0xfa, 0x01, 0xfe, 0x0e, 0x1f, 0xfe, 0x30, 0xf4, | |
27c868c2 | 6253 | 0x0d, 0xfe, 0x3c, 0x50, 0xa2, 0x01, 0xfe, 0x92, 0x1b, 0x01, 0x43, 0x09, |
629d688d MW |
6254 | 0x56, 0xfb, 0x01, 0xfe, 0xc8, 0x1a, 0x01, 0x0c, 0x06, 0x28, 0xa4, 0x01, |
6255 | 0xfe, 0xf4, 0x1c, 0x01, 0xfe, 0x00, 0x1d, 0x15, 0xfe, 0xe9, 0x00, 0x01, | |
6256 | 0x0c, 0x06, 0x4a, 0xfe, 0x4e, 0x13, 0x01, 0xfe, 0x22, 0x1b, 0xfe, 0x1e, | |
27c868c2 | 6257 | 0x1c, 0x0f, 0xfe, 0x14, 0x90, 0x04, 0xfe, 0x94, 0x93, 0x3a, 0x0b, 0xfe, |
629d688d MW |
6258 | 0x96, 0x90, 0x04, 0xfe, 0x96, 0x93, 0x79, 0x0b, 0x0e, 0x10, 0xfe, 0x64, |
6259 | 0x01, 0x22, 0xfe, 0x66, 0x01, 0x01, 0x0c, 0x06, 0x65, 0xf9, 0x0f, 0xfe, | |
6260 | 0x03, 0x80, 0x04, 0xfe, 0x83, 0x83, 0x33, 0x0b, 0x0e, 0x77, 0xfe, 0x01, | |
27c868c2 | 6261 | 0xec, 0x2c, 0xfe, 0x80, 0x40, 0x20, 0x2c, 0x7a, 0x30, 0x15, 0xdf, 0x40, |
629d688d MW |
6262 | 0x21, 0x2c, 0xfe, 0x00, 0x40, 0x8d, 0x2c, 0x02, 0xfe, 0x08, 0x1c, 0x03, |
6263 | 0xfe, 0xac, 0x00, 0xfe, 0x06, 0x58, 0x03, 0xfe, 0xae, 0x00, 0xfe, 0x07, | |
6264 | 0x58, 0x03, 0xfe, 0xb0, 0x00, 0xfe, 0x08, 0x58, 0x03, 0xfe, 0xb2, 0x00, | |
27c868c2 | 6265 | 0xfe, 0x09, 0x58, 0xfe, 0x0a, 0x1c, 0x2e, 0x49, 0x20, 0xe0, 0x26, 0x10, |
629d688d MW |
6266 | 0x66, 0x10, 0x55, 0x10, 0x6f, 0x13, 0x57, 0x52, 0x4f, 0x1c, 0x28, 0xfe, |
6267 | 0x90, 0x4d, 0xfe, 0x91, 0x54, 0x2b, 0xfe, 0x88, 0x11, 0x46, 0x1a, 0x13, | |
6268 | 0x5a, 0x52, 0x1c, 0x4a, 0xfe, 0x90, 0x4d, 0xfe, 0x91, 0x54, 0x2b, 0xfe, | |
27c868c2 | 6269 | 0x9e, 0x11, 0x2e, 0x1a, 0x20, 0x2c, 0x90, 0x34, 0x60, 0x21, 0x2c, 0xfe, |
629d688d MW |
6270 | 0x00, 0x40, 0x8d, 0x2c, 0x15, 0xdf, 0xfe, 0x14, 0x56, 0xfe, 0xd6, 0xf0, |
6271 | 0xfe, 0xb2, 0x11, 0xfe, 0x12, 0x1c, 0x75, 0xfe, 0x14, 0x1c, 0xfe, 0x10, | |
6272 | 0x1c, 0xfe, 0x18, 0x1c, 0x02, 0x51, 0xfe, 0x0c, 0x14, 0xfe, 0x0e, 0x47, | |
27c868c2 | 6273 | 0xfe, 0x07, 0xe6, 0x28, 0xfe, 0xce, 0x47, 0xfe, 0xf5, 0x13, 0x02, 0x01, |
629d688d MW |
6274 | 0xa7, 0x90, 0x34, 0x60, 0xfe, 0x06, 0x80, 0xfe, 0x48, 0x47, 0xfe, 0x42, |
6275 | 0x13, 0xfe, 0x02, 0x80, 0x09, 0x56, 0xfe, 0x34, 0x13, 0x0a, 0x5a, 0x01, | |
6276 | 0x18, 0xcb, 0xfe, 0x36, 0x12, 0xfe, 0x41, 0x48, 0xfe, 0x45, 0x48, 0x01, | |
27c868c2 | 6277 | 0xfe, 0xb2, 0x16, 0xfe, 0x00, 0xcc, 0xcb, 0xfe, 0xf3, 0x13, 0x3f, 0x89, |
629d688d MW |
6278 | 0x09, 0x1a, 0xa5, 0x0a, 0x9d, 0x01, 0x18, 0xfe, 0x80, 0x5c, 0x01, 0x85, |
6279 | 0xf2, 0x09, 0x9b, 0xa4, 0xfe, 0x14, 0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0xec, | |
6280 | 0x11, 0x02, 0xfe, 0x44, 0x58, 0x77, 0xfe, 0x01, 0xec, 0xb8, 0xfe, 0x9e, | |
27c868c2 | 6281 | 0x40, 0xfe, 0x9d, 0xe7, 0x00, 0xfe, 0x9c, 0xe7, 0x12, 0x8d, 0x30, 0x01, |
629d688d MW |
6282 | 0xf4, 0xfe, 0xdd, 0x10, 0x37, 0xd7, 0x99, 0xd8, 0x9c, 0x27, 0x25, 0xee, |
6283 | 0x09, 0x12, 0xfe, 0x48, 0x12, 0x09, 0x0d, 0xfe, 0x56, 0x12, 0x09, 0x1d, | |
6284 | 0xfe, 0x30, 0x12, 0x09, 0xdd, 0x1b, 0xfe, 0xc4, 0x13, 0x09, 0xfe, 0x23, | |
27c868c2 | 6285 | 0x00, 0x1b, 0xfe, 0xd0, 0x13, 0x09, 0x07, 0x1b, 0xfe, 0x34, 0x14, 0x09, |
629d688d MW |
6286 | 0x24, 0xfe, 0x12, 0x12, 0x09, 0x00, 0x1b, 0x29, 0x1f, 0xdd, 0x01, 0x42, |
6287 | 0xa1, 0x32, 0x01, 0x08, 0xae, 0x41, 0x02, 0x32, 0xfe, 0x62, 0x08, 0x0a, | |
6288 | 0xe1, 0x01, 0xfe, 0x58, 0x10, 0x15, 0x9b, 0x05, 0x35, 0x32, 0x01, 0x43, | |
27c868c2 | 6289 | 0x09, 0xbb, 0xfe, 0xd7, 0x13, 0x91, 0x4b, 0x7e, 0x4c, 0x8e, 0xfe, 0x80, |
629d688d MW |
6290 | 0x13, 0x01, 0x0c, 0x06, 0x54, 0xfe, 0x72, 0x12, 0xdb, 0x64, 0xdc, 0x34, |
6291 | 0xfe, 0x44, 0x55, 0xfe, 0xe5, 0x55, 0xb0, 0xfe, 0x4a, 0x13, 0x21, 0x6e, | |
6292 | 0xfe, 0x26, 0x13, 0x03, 0x97, 0x3b, 0x98, 0x8e, 0xfe, 0xb6, 0x0e, 0x10, | |
27c868c2 | 6293 | 0x6a, 0x22, 0x6b, 0x26, 0x10, 0x97, 0x10, 0x98, 0x01, 0xc2, 0x2e, 0x49, |
629d688d MW |
6294 | 0x88, 0x20, 0x6e, 0x01, 0xfe, 0x6a, 0x16, 0xdb, 0x64, 0xdc, 0x34, 0xfe, |
6295 | 0x04, 0x55, 0xfe, 0xa5, 0x55, 0xfe, 0x04, 0xfa, 0x64, 0xfe, 0x05, 0xfa, | |
6296 | 0x34, 0xfe, 0x8f, 0x10, 0x03, 0x6c, 0x3b, 0x6d, 0xfe, 0x40, 0x56, 0xfe, | |
27c868c2 | 6297 | 0xe1, 0x56, 0x10, 0x6c, 0x22, 0x6d, 0x71, 0xdb, 0x64, 0xdc, 0x34, 0xfe, |
629d688d MW |
6298 | 0x44, 0x55, 0xfe, 0xe5, 0x55, 0x03, 0x68, 0x3b, 0x69, 0xfe, 0x00, 0x56, |
6299 | 0xfe, 0xa1, 0x56, 0x10, 0x68, 0x22, 0x69, 0x01, 0x0c, 0x06, 0x54, 0xf9, | |
6300 | 0x21, 0x6e, 0xfe, 0x1f, 0x40, 0x03, 0x6a, 0x3b, 0x6b, 0xfe, 0x2c, 0x50, | |
27c868c2 | 6301 | 0xfe, 0xae, 0x50, 0x03, 0x6c, 0x3b, 0x6d, 0xfe, 0x44, 0x50, 0xfe, 0xc6, |
629d688d MW |
6302 | 0x50, 0x03, 0x68, 0x3b, 0x69, 0xfe, 0x08, 0x50, 0xfe, 0x8a, 0x50, 0x03, |
6303 | 0x4b, 0x3b, 0x4c, 0xfe, 0x40, 0x50, 0xfe, 0xc2, 0x50, 0x05, 0x73, 0x2e, | |
6304 | 0x07, 0x20, 0x9e, 0x05, 0x72, 0x32, 0x01, 0x08, 0x16, 0x3d, 0x27, 0x25, | |
27c868c2 | 6305 | 0xee, 0x09, 0x07, 0x2b, 0x3d, 0x01, 0x43, 0x09, 0xbb, 0x2b, 0x72, 0x01, |
629d688d MW |
6306 | 0xa6, 0x23, 0x3f, 0x1b, 0x3d, 0x01, 0x0c, 0x06, 0x0d, 0xfe, 0x1e, 0x13, |
6307 | 0x91, 0x4b, 0x7e, 0x4c, 0xfe, 0x0a, 0x55, 0x31, 0xfe, 0x8b, 0x55, 0xd9, | |
6308 | 0x4b, 0xda, 0x4c, 0xfe, 0x0c, 0x51, 0xfe, 0x8e, 0x51, 0x05, 0x72, 0x01, | |
27c868c2 | 6309 | 0xfe, 0x8e, 0x1e, 0xca, 0xfe, 0x19, 0x41, 0x05, 0x72, 0x32, 0x01, 0x08, |
629d688d MW |
6310 | 0x2a, 0x3c, 0x16, 0xc0, 0x27, 0x25, 0xbe, 0x2d, 0x1d, 0xc0, 0x2d, 0x0d, |
6311 | 0x83, 0x2d, 0x7f, 0x1b, 0xfe, 0x66, 0x15, 0x05, 0x3d, 0x01, 0x08, 0x2a, | |
6312 | 0x3c, 0x16, 0xc0, 0x27, 0x25, 0xbd, 0x09, 0x1d, 0x2b, 0x3d, 0x01, 0x08, | |
27c868c2 | 6313 | 0x16, 0xc0, 0x27, 0x25, 0xfe, 0xe8, 0x09, 0xfe, 0xc2, 0x49, 0x50, 0x03, |
629d688d MW |
6314 | 0xb6, 0x1e, 0x83, 0x01, 0x38, 0x06, 0x24, 0x31, 0xa1, 0xfe, 0xbb, 0x45, |
6315 | 0x2d, 0x00, 0xa4, 0x46, 0x07, 0x90, 0x3f, 0x01, 0xfe, 0xf8, 0x15, 0x01, | |
6316 | 0xa6, 0x86, 0xfe, 0x4b, 0x45, 0xfe, 0x20, 0x13, 0x01, 0x43, 0x09, 0x82, | |
27c868c2 | 6317 | 0xfe, 0x16, 0x13, 0x03, 0x9a, 0x1e, 0x5d, 0x03, 0x55, 0x1e, 0x31, 0x5e, |
629d688d MW |
6318 | 0x05, 0x72, 0xfe, 0xc0, 0x5d, 0x01, 0xa7, 0xfe, 0x03, 0x17, 0x03, 0x66, |
6319 | 0x8a, 0x10, 0x66, 0x5e, 0x32, 0x01, 0x08, 0x17, 0x73, 0x01, 0xfe, 0x56, | |
6320 | 0x19, 0x05, 0x73, 0x01, 0x08, 0x2a, 0x3c, 0x16, 0x3d, 0x27, 0x25, 0xbd, | |
27c868c2 | 6321 | 0x09, 0x07, 0x2b, 0x3d, 0x01, 0xfe, 0xbe, 0x16, 0xfe, 0x42, 0x58, 0xfe, |
629d688d MW |
6322 | 0xe8, 0x14, 0x01, 0xa6, 0x86, 0xfe, 0x4a, 0xf4, 0x0d, 0x1b, 0x3d, 0xfe, |
6323 | 0x4a, 0xf4, 0x07, 0xfe, 0x0e, 0x12, 0x01, 0x43, 0x09, 0x82, 0x4e, 0x05, | |
6324 | 0x72, 0x03, 0x55, 0x8a, 0x10, 0x55, 0x5e, 0x32, 0x01, 0x08, 0x17, 0x73, | |
27c868c2 | 6325 | 0x01, 0xfe, 0x84, 0x19, 0x05, 0x73, 0x01, 0x08, 0x2a, 0x3c, 0x16, 0x3d, |
629d688d MW |
6326 | 0x27, 0x25, 0xbd, 0x09, 0x12, 0x2b, 0x3d, 0x01, 0xfe, 0xe8, 0x17, 0x8b, |
6327 | 0xfe, 0xaa, 0x14, 0xfe, 0xb6, 0x14, 0x86, 0xa8, 0xb2, 0x0d, 0x1b, 0x3d, | |
6328 | 0xb2, 0x07, 0xfe, 0x0e, 0x12, 0x01, 0x43, 0x09, 0x82, 0x4e, 0x05, 0x72, | |
27c868c2 | 6329 | 0x03, 0x6f, 0x8a, 0x10, 0x6f, 0x5e, 0x32, 0x01, 0x08, 0x17, 0x73, 0x01, |
629d688d MW |
6330 | 0xfe, 0xc0, 0x19, 0x05, 0x73, 0x13, 0x07, 0x2f, 0xfe, 0xcc, 0x15, 0x17, |
6331 | 0xfe, 0xe2, 0x15, 0x5f, 0xcc, 0x01, 0x08, 0x26, 0x5f, 0x02, 0x8f, 0xfe, | |
6332 | 0xde, 0x15, 0x2a, 0xfe, 0xde, 0x15, 0x16, 0xfe, 0xcc, 0x15, 0x5e, 0x32, | |
27c868c2 | 6333 | 0x01, 0x08, 0xfe, 0xd5, 0x10, 0x13, 0x58, 0xff, 0x02, 0x00, 0x57, 0x52, |
629d688d MW |
6334 | 0xad, 0x23, 0xfe, 0xff, 0x7f, 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x02, |
6335 | 0x13, 0x58, 0xff, 0x02, 0x00, 0x57, 0x52, 0xad, 0x23, 0x3f, 0xfe, 0x30, | |
6336 | 0x56, 0xfe, 0x00, 0x5c, 0x02, 0x13, 0x58, 0xff, 0x02, 0x00, 0x57, 0x52, | |
27c868c2 | 6337 | 0xad, 0x02, 0x13, 0x58, 0xff, 0x02, 0x00, 0x57, 0x52, 0xfe, 0x00, 0x5e, |
629d688d MW |
6338 | 0x02, 0x13, 0x58, 0xff, 0x02, 0x00, 0x57, 0x52, 0xad, 0xfe, 0x0b, 0x58, |
6339 | 0x02, 0x0a, 0x66, 0x01, 0x5c, 0x0a, 0x55, 0x01, 0x5c, 0x0a, 0x6f, 0x01, | |
6340 | 0x5c, 0x02, 0x01, 0xfe, 0x1e, 0x1f, 0x23, 0x1a, 0xff, 0x03, 0x00, 0x54, | |
27c868c2 | 6341 | 0xfe, 0x00, 0xf4, 0x24, 0x52, 0x0f, 0xfe, 0x00, 0x7c, 0x04, 0xfe, 0x07, |
629d688d MW |
6342 | 0x7c, 0x3a, 0x0b, 0x0e, 0xfe, 0x00, 0x71, 0xfe, 0xf9, 0x18, 0xfe, 0x7a, |
6343 | 0x19, 0xfe, 0xfb, 0x19, 0xfe, 0x1a, 0xf7, 0x00, 0xfe, 0x1b, 0xf7, 0x00, | |
6344 | 0x7a, 0x30, 0x10, 0x68, 0x22, 0x69, 0xd9, 0x6c, 0xda, 0x6d, 0x02, 0xfe, | |
27c868c2 | 6345 | 0x62, 0x08, 0xfe, 0x82, 0x4a, 0xfe, 0xe1, 0x1a, 0xfe, 0x83, 0x5a, 0x77, |
629d688d MW |
6346 | 0x02, 0x01, 0xc6, 0xfe, 0x42, 0x48, 0x4f, 0x50, 0x45, 0x01, 0x08, 0x16, |
6347 | 0xfe, 0xe0, 0x17, 0x27, 0x25, 0xbe, 0x01, 0x08, 0x16, 0xfe, 0xe0, 0x17, | |
6348 | 0x27, 0x25, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59, 0x03, 0x9a, 0x1e, 0xfe, | |
27c868c2 | 6349 | 0xda, 0x12, 0x01, 0x38, 0x06, 0x12, 0xfe, 0xd0, 0x13, 0x26, 0x53, 0x12, |
629d688d MW |
6350 | 0x48, 0xfe, 0x08, 0x17, 0xd1, 0x12, 0x53, 0x12, 0xfe, 0x1e, 0x13, 0x2d, |
6351 | 0xb4, 0x7b, 0xfe, 0x26, 0x17, 0x4d, 0x13, 0x07, 0x1c, 0xb4, 0x90, 0x04, | |
6352 | 0xfe, 0x78, 0x10, 0xff, 0x02, 0x83, 0x55, 0xf1, 0xff, 0x02, 0x83, 0x55, | |
27c868c2 | 6353 | 0x53, 0x1d, 0xfe, 0x12, 0x13, 0xd6, 0xfe, 0x30, 0x00, 0xb0, 0xfe, 0x80, |
629d688d MW |
6354 | 0x17, 0x1c, 0x63, 0x13, 0x07, 0xfe, 0x56, 0x10, 0x53, 0x0d, 0xfe, 0x16, |
6355 | 0x13, 0xd6, 0xfe, 0x64, 0x00, 0xb0, 0xfe, 0x80, 0x17, 0x0a, 0xfe, 0x64, | |
6356 | 0x00, 0x1c, 0x94, 0x13, 0x07, 0xfe, 0x28, 0x10, 0x53, 0x07, 0xfe, 0x60, | |
27c868c2 | 6357 | 0x13, 0xd6, 0xfe, 0xc8, 0x00, 0xb0, 0xfe, 0x80, 0x17, 0x0a, 0xfe, 0xc8, |
629d688d MW |
6358 | 0x00, 0x1c, 0x95, 0x13, 0x07, 0x71, 0xd6, 0xfe, 0x90, 0x01, 0x48, 0xfe, |
6359 | 0x8c, 0x17, 0x45, 0xf3, 0xfe, 0x43, 0xf4, 0x96, 0xfe, 0x56, 0xf0, 0xfe, | |
6360 | 0x9e, 0x17, 0xfe, 0x04, 0xf4, 0x58, 0xfe, 0x43, 0xf4, 0x94, 0xf6, 0x8b, | |
27c868c2 | 6361 | 0x01, 0xfe, 0x24, 0x16, 0x23, 0x3f, 0xfc, 0xa8, 0x8c, 0x49, 0x48, 0xfe, |
629d688d MW |
6362 | 0xda, 0x17, 0x62, 0x49, 0xfe, 0x1c, 0x10, 0xa8, 0x8c, 0x80, 0x48, 0xfe, |
6363 | 0xda, 0x17, 0x62, 0x80, 0x71, 0x50, 0x26, 0xfe, 0x4d, 0xf4, 0x00, 0xf7, | |
6364 | 0x45, 0x13, 0x07, 0xfe, 0xb4, 0x56, 0xfe, 0xc3, 0x58, 0x02, 0x50, 0x13, | |
27c868c2 | 6365 | 0x0d, 0x02, 0x50, 0x3e, 0x78, 0x4f, 0x45, 0x01, 0x08, 0x16, 0xa9, 0x27, |
629d688d MW |
6366 | 0x25, 0xbe, 0xfe, 0x03, 0xea, 0xfe, 0x7e, 0x01, 0x01, 0x08, 0x16, 0xa9, |
6367 | 0x27, 0x25, 0xfe, 0xe9, 0x0a, 0x01, 0x08, 0x16, 0xa9, 0x27, 0x25, 0xfe, | |
6368 | 0xe9, 0x0a, 0xfe, 0x05, 0xea, 0xfe, 0x7f, 0x01, 0x01, 0x08, 0x16, 0xa9, | |
27c868c2 | 6369 | 0x27, 0x25, 0xfe, 0x69, 0x09, 0xfe, 0x02, 0xea, 0xfe, 0x80, 0x01, 0x01, |
629d688d MW |
6370 | 0x08, 0x16, 0xa9, 0x27, 0x25, 0xfe, 0xe8, 0x08, 0x47, 0xfe, 0x81, 0x01, |
6371 | 0x03, 0xb6, 0x1e, 0x83, 0x01, 0x38, 0x06, 0x24, 0x31, 0xa2, 0x78, 0xf2, | |
6372 | 0x53, 0x07, 0x36, 0xfe, 0x34, 0xf4, 0x3f, 0xa1, 0x78, 0x03, 0x9a, 0x1e, | |
27c868c2 | 6373 | 0x83, 0x01, 0x38, 0x06, 0x12, 0x31, 0xf0, 0x4f, 0x45, 0xfe, 0x90, 0x10, |
629d688d MW |
6374 | 0xfe, 0x40, 0x5a, 0x23, 0x3f, 0xfb, 0x8c, 0x49, 0x48, 0xfe, 0xaa, 0x18, |
6375 | 0x62, 0x49, 0x71, 0x8c, 0x80, 0x48, 0xfe, 0xaa, 0x18, 0x62, 0x80, 0xfe, | |
6376 | 0xb4, 0x56, 0xfe, 0x40, 0x5d, 0x01, 0xc6, 0x01, 0xfe, 0xac, 0x1d, 0xfe, | |
27c868c2 | 6377 | 0x02, 0x17, 0xfe, 0xc8, 0x45, 0xfe, 0x5a, 0xf0, 0xfe, 0xc0, 0x18, 0xfe, |
629d688d MW |
6378 | 0x43, 0x48, 0x2d, 0x93, 0x36, 0xfe, 0x34, 0xf4, 0xfe, 0x00, 0x11, 0xfe, |
6379 | 0x40, 0x10, 0x2d, 0xb4, 0x36, 0xfe, 0x34, 0xf4, 0x04, 0xfe, 0x34, 0x10, | |
6380 | 0x2d, 0xfe, 0x0b, 0x00, 0x36, 0x46, 0x63, 0xfe, 0x28, 0x10, 0xfe, 0xc0, | |
27c868c2 | 6381 | 0x49, 0xff, 0x02, 0x00, 0x54, 0xb2, 0xfe, 0x90, 0x01, 0x48, 0xfe, 0xfa, |
629d688d MW |
6382 | 0x18, 0x45, 0xfe, 0x1c, 0xf4, 0x3f, 0xf3, 0xfe, 0x40, 0xf4, 0x96, 0xfe, |
6383 | 0x56, 0xf0, 0xfe, 0x0c, 0x19, 0xfe, 0x04, 0xf4, 0x58, 0xfe, 0x40, 0xf4, | |
6384 | 0x94, 0xf6, 0x3e, 0x2d, 0x93, 0x4e, 0xd0, 0x0d, 0x21, 0xfe, 0x7f, 0x01, | |
27c868c2 | 6385 | 0xfe, 0xc8, 0x46, 0xfe, 0x24, 0x13, 0x8c, 0x00, 0x5d, 0x26, 0x21, 0xfe, |
629d688d MW |
6386 | 0x7e, 0x01, 0xfe, 0xc8, 0x45, 0xfe, 0x14, 0x13, 0x21, 0xfe, 0x80, 0x01, |
6387 | 0xfe, 0x48, 0x45, 0xfa, 0x21, 0xfe, 0x81, 0x01, 0xfe, 0xc8, 0x44, 0x4e, | |
6388 | 0x26, 0x02, 0x13, 0x07, 0x02, 0x78, 0x45, 0x50, 0x13, 0x0d, 0x02, 0x14, | |
27c868c2 | 6389 | 0x07, 0x01, 0x08, 0x17, 0xfe, 0x82, 0x19, 0x14, 0x0d, 0x01, 0x08, 0x17, |
629d688d MW |
6390 | 0xfe, 0x82, 0x19, 0x14, 0x1d, 0x01, 0x08, 0x17, 0xfe, 0x82, 0x19, 0x5f, |
6391 | 0xfe, 0x89, 0x49, 0x01, 0x08, 0x02, 0x14, 0x07, 0x01, 0x08, 0x17, 0xc1, | |
6392 | 0x14, 0x1d, 0x01, 0x08, 0x17, 0xc1, 0x14, 0x07, 0x01, 0x08, 0x17, 0xc1, | |
27c868c2 | 6393 | 0xfe, 0x89, 0x49, 0x01, 0x08, 0x17, 0xc1, 0x5f, 0xfe, 0x89, 0x4a, 0x01, |
629d688d MW |
6394 | 0x08, 0x02, 0x50, 0x02, 0x14, 0x07, 0x01, 0x08, 0x17, 0x74, 0x14, 0x7f, |
6395 | 0x01, 0x08, 0x17, 0x74, 0x14, 0x12, 0x01, 0x08, 0x17, 0x74, 0xfe, 0x89, | |
6396 | 0x49, 0x01, 0x08, 0x17, 0x74, 0x14, 0x00, 0x01, 0x08, 0x17, 0x74, 0xfe, | |
27c868c2 | 6397 | 0x89, 0x4a, 0x01, 0x08, 0x17, 0x74, 0xfe, 0x09, 0x49, 0x01, 0x08, 0x17, |
629d688d MW |
6398 | 0x74, 0x5f, 0xcc, 0x01, 0x08, 0x02, 0x21, 0xe4, 0x09, 0x07, 0xfe, 0x4c, |
6399 | 0x13, 0xc8, 0x20, 0xe4, 0xfe, 0x49, 0xf4, 0x00, 0x4d, 0x5f, 0xa1, 0x5e, | |
6400 | 0xfe, 0x01, 0xec, 0xfe, 0x27, 0x01, 0xcc, 0xff, 0x02, 0x00, 0x10, 0x2f, | |
27c868c2 | 6401 | 0xfe, 0x3e, 0x1a, 0x01, 0x43, 0x09, 0xfe, 0xe3, 0x00, 0xfe, 0x22, 0x13, |
629d688d MW |
6402 | 0x16, 0xfe, 0x64, 0x1a, 0x26, 0x20, 0x9e, 0x01, 0x41, 0x21, 0x9e, 0x09, |
6403 | 0x07, 0x5d, 0x01, 0x0c, 0x61, 0x07, 0x44, 0x02, 0x0a, 0x5a, 0x01, 0x18, | |
6404 | 0xfe, 0x00, 0x40, 0xaa, 0x09, 0x1a, 0xfe, 0x12, 0x13, 0x0a, 0x9d, 0x01, | |
27c868c2 | 6405 | 0x18, 0xaa, 0x0a, 0x67, 0x01, 0xa3, 0x02, 0x0a, 0x9d, 0x01, 0x18, 0xaa, |
629d688d MW |
6406 | 0xfe, 0x80, 0xe7, 0x1a, 0x09, 0x1a, 0x5d, 0xfe, 0x45, 0x58, 0x01, 0xfe, |
6407 | 0xb2, 0x16, 0xaa, 0x02, 0x0a, 0x5a, 0x01, 0x18, 0xaa, 0x0a, 0x67, 0x01, | |
6408 | 0xa3, 0x02, 0x0a, 0x5a, 0x01, 0x18, 0x01, 0xfe, 0x7e, 0x1e, 0xfe, 0x80, | |
27c868c2 | 6409 | 0x4c, 0xfe, 0x49, 0xe4, 0x1a, 0xfe, 0x12, 0x13, 0x0a, 0x9d, 0x01, 0x18, |
629d688d MW |
6410 | 0xfe, 0x80, 0x4c, 0x0a, 0x67, 0x01, 0x5c, 0x02, 0x1c, 0x1a, 0x87, 0x7c, |
6411 | 0xe5, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x24, 0x1c, 0xfe, 0x1d, | |
6412 | 0xf7, 0x28, 0xb1, 0xfe, 0x04, 0x1b, 0x01, 0xfe, 0x2a, 0x1c, 0xfa, 0xb3, | |
27c868c2 | 6413 | 0x28, 0x7c, 0xfe, 0x2c, 0x01, 0xfe, 0x2f, 0x19, 0x02, 0xc9, 0x2b, 0xfe, |
629d688d MW |
6414 | 0xf4, 0x1a, 0xfe, 0xfa, 0x10, 0x1c, 0x1a, 0x87, 0x03, 0xfe, 0x64, 0x01, |
6415 | 0xfe, 0x00, 0xf4, 0x24, 0xfe, 0x18, 0x58, 0x03, 0xfe, 0x66, 0x01, 0xfe, | |
6416 | 0x19, 0x58, 0xb3, 0x24, 0x01, 0xfe, 0x0e, 0x1f, 0xfe, 0x30, 0xf4, 0x07, | |
27c868c2 | 6417 | 0xfe, 0x3c, 0x50, 0x7c, 0xfe, 0x38, 0x00, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, |
629d688d MW |
6418 | 0xf7, 0x24, 0xb1, 0xfe, 0x50, 0x1b, 0xfe, 0xd4, 0x14, 0x31, 0x02, 0xc9, |
6419 | 0x2b, 0xfe, 0x26, 0x1b, 0xfe, 0xba, 0x10, 0x1c, 0x1a, 0x87, 0xfe, 0x83, | |
6420 | 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x1d, 0xf7, 0x54, 0xb1, | |
27c868c2 | 6421 | 0xfe, 0x72, 0x1b, 0xfe, 0xb2, 0x14, 0xfc, 0xb3, 0x54, 0x7c, 0x12, 0xfe, |
629d688d MW |
6422 | 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00, 0x02, 0xc9, 0x2b, 0xfe, 0x66, 0x1b, |
6423 | 0xfe, 0x8a, 0x10, 0x1c, 0x1a, 0x87, 0x8b, 0x0f, 0xfe, 0x30, 0x90, 0x04, | |
6424 | 0xfe, 0xb0, 0x93, 0x3a, 0x0b, 0xfe, 0x18, 0x58, 0xfe, 0x32, 0x90, 0x04, | |
27c868c2 | 6425 | 0xfe, 0xb2, 0x93, 0x3a, 0x0b, 0xfe, 0x19, 0x58, 0x0e, 0xa8, 0xb3, 0x4a, |
629d688d MW |
6426 | 0x7c, 0x12, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0x4a, 0xb1, 0xfe, 0xc6, |
6427 | 0x1b, 0xfe, 0x5e, 0x14, 0x31, 0x02, 0xc9, 0x2b, 0xfe, 0x96, 0x1b, 0x5c, | |
6428 | 0xfe, 0x02, 0xf6, 0x1a, 0x87, 0xfe, 0x18, 0xfe, 0x6a, 0xfe, 0x19, 0xfe, | |
27c868c2 | 6429 | 0x6b, 0x01, 0xfe, 0x1e, 0x1f, 0xfe, 0x1d, 0xf7, 0x65, 0xb1, 0xfe, 0xee, |
629d688d MW |
6430 | 0x1b, 0xfe, 0x36, 0x14, 0xfe, 0x1c, 0x13, 0xb3, 0x65, 0x3e, 0xfe, 0x83, |
6431 | 0x58, 0xfe, 0xaf, 0x19, 0xfe, 0x80, 0xe7, 0x1a, 0xfe, 0x81, 0xe7, 0x1a, | |
6432 | 0x15, 0xfe, 0xdd, 0x00, 0x7a, 0x30, 0x02, 0x7a, 0x30, 0xfe, 0x12, 0x45, | |
27c868c2 | 6433 | 0x2b, 0xfe, 0xdc, 0x1b, 0x1f, 0x07, 0x47, 0xb5, 0xc3, 0x05, 0x35, 0xfe, |
629d688d MW |
6434 | 0x39, 0xf0, 0x75, 0x26, 0x02, 0xfe, 0x7e, 0x18, 0x23, 0x1d, 0x36, 0x13, |
6435 | 0x11, 0x02, 0x87, 0x03, 0xe3, 0x23, 0x07, 0xfe, 0xef, 0x12, 0xfe, 0xe1, | |
6436 | 0x10, 0x90, 0x34, 0x60, 0xfe, 0x02, 0x80, 0x09, 0x56, 0xfe, 0x3c, 0x13, | |
27c868c2 | 6437 | 0xfe, 0x82, 0x14, 0xfe, 0x42, 0x13, 0x51, 0xfe, 0x06, 0x83, 0x0a, 0x5a, |
629d688d MW |
6438 | 0x01, 0x18, 0xcb, 0xfe, 0x3e, 0x12, 0xfe, 0x41, 0x48, 0xfe, 0x45, 0x48, |
6439 | 0x01, 0xfe, 0xb2, 0x16, 0xfe, 0x00, 0xcc, 0xcb, 0xfe, 0xf3, 0x13, 0x3f, | |
6440 | 0x89, 0x09, 0x1a, 0xa5, 0x0a, 0x9d, 0x01, 0x18, 0xfe, 0x80, 0x4c, 0x01, | |
27c868c2 | 6441 | 0x85, 0xfe, 0x16, 0x10, 0x09, 0x9b, 0x4e, 0xfe, 0x40, 0x14, 0xfe, 0x24, |
629d688d MW |
6442 | 0x12, 0xfe, 0x14, 0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0x52, 0x1c, 0x1c, 0x0d, |
6443 | 0x02, 0xfe, 0x9c, 0xe7, 0x0d, 0x19, 0xfe, 0x15, 0x00, 0x40, 0x8d, 0x30, | |
6444 | 0x01, 0xf4, 0x1c, 0x07, 0x02, 0x51, 0xfe, 0x06, 0x83, 0xfe, 0x18, 0x80, | |
27c868c2 | 6445 | 0x61, 0x28, 0x44, 0x15, 0x56, 0x01, 0x85, 0x1c, 0x07, 0x02, 0xfe, 0x38, |
629d688d MW |
6446 | 0x90, 0xfe, 0xba, 0x90, 0x91, 0xde, 0x7e, 0xdf, 0xfe, 0x48, 0x55, 0x31, |
6447 | 0xfe, 0xc9, 0x55, 0x02, 0x21, 0xb9, 0x88, 0x20, 0xb9, 0x02, 0x0a, 0xba, | |
6448 | 0x01, 0x18, 0xfe, 0x41, 0x48, 0x0a, 0x57, 0x01, 0x18, 0xfe, 0x49, 0x44, | |
27c868c2 | 6449 | 0x1b, 0xfe, 0x1e, 0x1d, 0x88, 0x89, 0x02, 0x0a, 0x5a, 0x01, 0x18, 0x09, |
629d688d MW |
6450 | 0x1a, 0xa4, 0x0a, 0x67, 0x01, 0xa3, 0x0a, 0x57, 0x01, 0x18, 0x88, 0x89, |
6451 | 0x02, 0xfe, 0x4e, 0xe4, 0x1d, 0x7b, 0xfe, 0x52, 0x1d, 0x03, 0xfe, 0x90, | |
6452 | 0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10, 0xfe, 0x4e, 0xe4, 0xdd, 0x7b, | |
27c868c2 | 6453 | 0xfe, 0x64, 0x1d, 0x03, 0xfe, 0x92, 0x00, 0xd1, 0x12, 0xfe, 0x1a, 0x10, |
629d688d MW |
6454 | 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x7b, 0xfe, 0x76, 0x1d, 0x03, 0xfe, |
6455 | 0x94, 0x00, 0xd1, 0x24, 0xfe, 0x08, 0x10, 0x03, 0xfe, 0x96, 0x00, 0xd1, | |
6456 | 0x63, 0xfe, 0x4e, 0x45, 0x83, 0xca, 0xff, 0x04, 0x68, 0x54, 0xfe, 0xf1, | |
27c868c2 | 6457 | 0x10, 0x23, 0x49, 0xfe, 0x08, 0x1c, 0xfe, 0x67, 0x19, 0xfe, 0x0a, 0x1c, |
629d688d MW |
6458 | 0xfe, 0x1a, 0xf4, 0xfe, 0x00, 0x04, 0x83, 0xb2, 0x1d, 0x48, 0xfe, 0xaa, |
6459 | 0x1d, 0x13, 0x1d, 0x02, 0x09, 0x92, 0xfe, 0x5a, 0xf0, 0xfe, 0xba, 0x1d, | |
6460 | 0x2e, 0x93, 0xfe, 0x34, 0x10, 0x09, 0x12, 0xfe, 0x5a, 0xf0, 0xfe, 0xc8, | |
27c868c2 | 6461 | 0x1d, 0x2e, 0xb4, 0xfe, 0x26, 0x10, 0x09, 0x1d, 0x36, 0x2e, 0x63, 0xfe, |
629d688d MW |
6462 | 0x1a, 0x10, 0x09, 0x0d, 0x36, 0x2e, 0x94, 0xf2, 0x09, 0x07, 0x36, 0x2e, |
6463 | 0x95, 0xa1, 0xc8, 0x02, 0x1f, 0x93, 0x01, 0x42, 0xfe, 0x04, 0xfe, 0x99, | |
6464 | 0x03, 0x9c, 0x8b, 0x02, 0x2a, 0xfe, 0x1c, 0x1e, 0xfe, 0x14, 0xf0, 0x08, | |
27c868c2 | 6465 | 0x2f, 0xfe, 0x0c, 0x1e, 0x2a, 0xfe, 0x1c, 0x1e, 0x8f, 0xfe, 0x1c, 0x1e, |
629d688d MW |
6466 | 0xfe, 0x82, 0xf0, 0xfe, 0x10, 0x1e, 0x02, 0x0f, 0x3f, 0x04, 0xfe, 0x80, |
6467 | 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x18, 0x80, 0x04, 0xfe, 0x98, | |
6468 | 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x02, 0x80, 0x04, 0xfe, 0x82, | |
27c868c2 | 6469 | 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06, 0x80, 0x04, 0xfe, 0x86, |
629d688d MW |
6470 | 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x1b, 0x80, 0x04, 0xfe, 0x9b, |
6471 | 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x04, 0x80, 0x04, 0xfe, 0x84, | |
6472 | 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x80, 0x80, 0x04, 0xfe, 0x80, | |
27c868c2 | 6473 | 0x83, 0xfe, 0xc9, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x19, 0x81, 0x04, |
629d688d MW |
6474 | 0xfe, 0x99, 0x83, 0xfe, 0xca, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06, |
6475 | 0x83, 0x04, 0xfe, 0x86, 0x83, 0xfe, 0xce, 0x47, 0x0b, 0x0e, 0x02, 0x0f, | |
6476 | 0xfe, 0x2c, 0x90, 0x04, 0xfe, 0xac, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f, | |
27c868c2 | 6477 | 0xfe, 0xae, 0x90, 0x04, 0xfe, 0xae, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f, |
629d688d MW |
6478 | 0xfe, 0x08, 0x90, 0x04, 0xfe, 0x88, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f, |
6479 | 0xfe, 0x8a, 0x90, 0x04, 0xfe, 0x8a, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f, | |
6480 | 0xfe, 0x0c, 0x90, 0x04, 0xfe, 0x8c, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f, | |
27c868c2 | 6481 | 0xfe, 0x8e, 0x90, 0x04, 0xfe, 0x8e, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f, |
629d688d MW |
6482 | 0xfe, 0x3c, 0x90, 0x04, 0xfe, 0xbc, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x8b, |
6483 | 0x0f, 0xfe, 0x03, 0x80, 0x04, 0xfe, 0x83, 0x83, 0x33, 0x0b, 0x77, 0x0e, | |
6484 | 0xa8, 0x02, 0xff, 0x66, 0x00, 0x00, | |
1da177e4 LT |
6485 | }; |
6486 | ||
51219358 MW |
6487 | static unsigned short _adv_asc38C1600_size = sizeof(_adv_asc38C1600_buf); /* 0x1673 */ |
6488 | static ADV_DCNT _adv_asc38C1600_chksum = 0x0604EF77UL; /* Expanded little-endian checksum. */ | |
6489 | ||
6490 | static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc) | |
6491 | { | |
6492 | PortAddr iop_base; | |
6493 | int i; | |
6494 | ushort lram_addr; | |
6495 | ||
6496 | iop_base = asc_dvc->iop_base; | |
6497 | AscPutRiscVarFreeQHead(iop_base, 1); | |
6498 | AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng); | |
6499 | AscPutVarFreeQHead(iop_base, 1); | |
6500 | AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng); | |
6501 | AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B, | |
6502 | (uchar)((int)asc_dvc->max_total_qng + 1)); | |
6503 | AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B, | |
6504 | (uchar)((int)asc_dvc->max_total_qng + 2)); | |
6505 | AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B, | |
6506 | asc_dvc->max_total_qng); | |
6507 | AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0); | |
6508 | AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); | |
6509 | AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0); | |
6510 | AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0); | |
6511 | AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0); | |
6512 | AscPutQDoneInProgress(iop_base, 0); | |
6513 | lram_addr = ASC_QADR_BEG; | |
6514 | for (i = 0; i < 32; i++, lram_addr += 2) { | |
6515 | AscWriteLramWord(iop_base, lram_addr, 0); | |
6516 | } | |
6517 | } | |
6518 | ||
6519 | static ushort AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc) | |
6520 | { | |
6521 | int i; | |
6522 | ushort warn_code; | |
6523 | PortAddr iop_base; | |
6524 | ASC_PADDR phy_addr; | |
6525 | ASC_DCNT phy_size; | |
6526 | ||
6527 | iop_base = asc_dvc->iop_base; | |
6528 | warn_code = 0; | |
6529 | for (i = 0; i <= ASC_MAX_TID; i++) { | |
6530 | AscPutMCodeInitSDTRAtID(iop_base, i, | |
6531 | asc_dvc->cfg->sdtr_period_offset[i]); | |
6532 | } | |
6533 | ||
6534 | AscInitQLinkVar(asc_dvc); | |
6535 | AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B, | |
6536 | asc_dvc->cfg->disc_enable); | |
6537 | AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B, | |
6538 | ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id)); | |
6539 | ||
6540 | /* Align overrun buffer on an 8 byte boundary. */ | |
6541 | phy_addr = virt_to_bus(asc_dvc->cfg->overrun_buf); | |
6542 | phy_addr = cpu_to_le32((phy_addr + 7) & ~0x7); | |
6543 | AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D, | |
6544 | (uchar *)&phy_addr, 1); | |
6545 | phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE - 8); | |
6546 | AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D, | |
6547 | (uchar *)&phy_size, 1); | |
6548 | ||
6549 | asc_dvc->cfg->mcode_date = | |
6550 | AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W); | |
6551 | asc_dvc->cfg->mcode_version = | |
6552 | AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W); | |
6553 | ||
6554 | AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR); | |
6555 | if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) { | |
6556 | asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR; | |
6557 | return warn_code; | |
6558 | } | |
6559 | if (AscStartChip(iop_base) != 1) { | |
6560 | asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP; | |
6561 | return warn_code; | |
6562 | } | |
6563 | ||
6564 | return warn_code; | |
6565 | } | |
6566 | ||
6567 | static ushort AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc) | |
6568 | { | |
6569 | ushort warn_code; | |
6570 | PortAddr iop_base; | |
6571 | ||
6572 | iop_base = asc_dvc->iop_base; | |
6573 | warn_code = 0; | |
6574 | if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) && | |
6575 | !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) { | |
6576 | AscResetChipAndScsiBus(asc_dvc); | |
6577 | mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */ | |
6578 | } | |
6579 | asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC; | |
6580 | if (asc_dvc->err_code != 0) | |
6581 | return UW_ERR; | |
6582 | if (!AscFindSignature(asc_dvc->iop_base)) { | |
6583 | asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE; | |
6584 | return warn_code; | |
6585 | } | |
6586 | AscDisableInterrupt(iop_base); | |
6587 | warn_code |= AscInitLram(asc_dvc); | |
6588 | if (asc_dvc->err_code != 0) | |
6589 | return UW_ERR; | |
6590 | ASC_DBG1(1, "AscInitAsc1000Driver: _asc_mcode_chksum 0x%lx\n", | |
6591 | (ulong)_asc_mcode_chksum); | |
6592 | if (AscLoadMicroCode(iop_base, 0, _asc_mcode_buf, | |
6593 | _asc_mcode_size) != _asc_mcode_chksum) { | |
6594 | asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM; | |
6595 | return warn_code; | |
6596 | } | |
6597 | warn_code |= AscInitMicroCodeVar(asc_dvc); | |
6598 | asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC; | |
6599 | AscEnableInterrupt(iop_base); | |
6600 | return warn_code; | |
6601 | } | |
6602 | ||
6603 | /* | |
6604 | * Load the Microcode | |
6605 | * | |
6606 | * Write the microcode image to RISC memory starting at address 0. | |
6607 | * | |
6608 | * The microcode is stored compressed in the following format: | |
6609 | * | |
6610 | * 254 word (508 byte) table indexed by byte code followed | |
6611 | * by the following byte codes: | |
6612 | * | |
6613 | * 1-Byte Code: | |
6614 | * 00: Emit word 0 in table. | |
6615 | * 01: Emit word 1 in table. | |
6616 | * . | |
6617 | * FD: Emit word 253 in table. | |
6618 | * | |
6619 | * Multi-Byte Code: | |
6620 | * FE WW WW: (3 byte code) Word to emit is the next word WW WW. | |
6621 | * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW. | |
6622 | * | |
6623 | * Returns 0 or an error if the checksum doesn't match | |
6624 | */ | |
6625 | static int AdvLoadMicrocode(AdvPortAddr iop_base, unsigned char *buf, int size, | |
6626 | int memsize, int chksum) | |
6627 | { | |
6628 | int i, j, end, len = 0; | |
6629 | ADV_DCNT sum; | |
6630 | ||
6631 | AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0); | |
6632 | ||
6633 | for (i = 253 * 2; i < size; i++) { | |
6634 | if (buf[i] == 0xff) { | |
6635 | unsigned short word = (buf[i + 3] << 8) | buf[i + 2]; | |
6636 | for (j = 0; j < buf[i + 1]; j++) { | |
6637 | AdvWriteWordAutoIncLram(iop_base, word); | |
6638 | len += 2; | |
6639 | } | |
6640 | i += 3; | |
6641 | } else if (buf[i] == 0xfe) { | |
6642 | unsigned short word = (buf[i + 2] << 8) | buf[i + 1]; | |
6643 | AdvWriteWordAutoIncLram(iop_base, word); | |
6644 | i += 2; | |
6645 | len += 2; | |
6646 | } else { | |
6647 | unsigned char off = buf[i] * 2; | |
6648 | unsigned short word = (buf[off + 1] << 8) | buf[off]; | |
6649 | AdvWriteWordAutoIncLram(iop_base, word); | |
6650 | len += 2; | |
6651 | } | |
6652 | } | |
6653 | ||
6654 | end = len; | |
6655 | ||
6656 | while (len < memsize) { | |
6657 | AdvWriteWordAutoIncLram(iop_base, 0); | |
6658 | len += 2; | |
6659 | } | |
6660 | ||
6661 | /* Verify the microcode checksum. */ | |
6662 | sum = 0; | |
6663 | AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0); | |
6664 | ||
6665 | for (len = 0; len < end; len += 2) { | |
6666 | sum += AdvReadWordAutoIncLram(iop_base); | |
6667 | } | |
6668 | ||
6669 | if (sum != chksum) | |
6670 | return ASC_IERR_MCODE_CHKSUM; | |
6671 | ||
6672 | return 0; | |
6673 | } | |
6674 | ||
6675 | /* | |
6676 | * DvcGetPhyAddr() | |
6677 | * | |
6678 | * Return the physical address of 'vaddr' and set '*lenp' to the | |
6679 | * number of physically contiguous bytes that follow 'vaddr'. | |
6680 | * 'flag' indicates the type of structure whose physical address | |
6681 | * is being translated. | |
6682 | * | |
6683 | * Note: Because Linux currently doesn't page the kernel and all | |
6684 | * kernel buffers are physically contiguous, leave '*lenp' unchanged. | |
6685 | */ | |
6686 | ADV_PADDR | |
6687 | DvcGetPhyAddr(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq, | |
6688 | uchar *vaddr, ADV_SDCNT *lenp, int flag) | |
6689 | { | |
6690 | ADV_PADDR paddr = virt_to_bus(vaddr); | |
6691 | ||
6692 | ASC_DBG4(4, "DvcGetPhyAddr: vaddr 0x%p, lenp 0x%p *lenp %lu, paddr 0x%lx\n", | |
6693 | vaddr, lenp, (ulong)*((ulong *)lenp), (ulong)paddr); | |
6694 | ||
6695 | return paddr; | |
6696 | } | |
6697 | ||
6698 | static void AdvBuildCarrierFreelist(struct adv_dvc_var *asc_dvc) | |
6699 | { | |
6700 | ADV_CARR_T *carrp; | |
6701 | ADV_SDCNT buf_size; | |
6702 | ADV_PADDR carr_paddr; | |
6703 | ||
6704 | BUG_ON(!asc_dvc->carrier_buf); | |
6705 | ||
6706 | carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf); | |
6707 | asc_dvc->carr_freelist = NULL; | |
6708 | if (carrp == asc_dvc->carrier_buf) { | |
6709 | buf_size = ADV_CARRIER_BUFSIZE; | |
6710 | } else { | |
6711 | buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T); | |
6712 | } | |
6713 | ||
6714 | do { | |
6715 | /* Get physical address of the carrier 'carrp'. */ | |
6716 | ADV_DCNT contig_len = sizeof(ADV_CARR_T); | |
6717 | carr_paddr = cpu_to_le32(DvcGetPhyAddr(asc_dvc, NULL, | |
6718 | (uchar *)carrp, | |
6719 | (ADV_SDCNT *)&contig_len, | |
6720 | ADV_IS_CARRIER_FLAG)); | |
6721 | ||
6722 | buf_size -= sizeof(ADV_CARR_T); | |
6723 | ||
6724 | /* | |
6725 | * If the current carrier is not physically contiguous, then | |
6726 | * maybe there was a page crossing. Try the next carrier | |
6727 | * aligned start address. | |
6728 | */ | |
6729 | if (contig_len < sizeof(ADV_CARR_T)) { | |
6730 | carrp++; | |
6731 | continue; | |
6732 | } | |
6733 | ||
6734 | carrp->carr_pa = carr_paddr; | |
6735 | carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp)); | |
6736 | ||
6737 | /* | |
6738 | * Insert the carrier at the beginning of the freelist. | |
6739 | */ | |
6740 | carrp->next_vpa = | |
6741 | cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist)); | |
6742 | asc_dvc->carr_freelist = carrp; | |
6743 | ||
6744 | carrp++; | |
6745 | } while (buf_size > 0); | |
6746 | } | |
6747 | ||
6748 | /* | |
6749 | * Send an idle command to the chip and wait for completion. | |
6750 | * | |
6751 | * Command completion is polled for once per microsecond. | |
6752 | * | |
6753 | * The function can be called from anywhere including an interrupt handler. | |
6754 | * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical() | |
6755 | * functions to prevent reentrancy. | |
6756 | * | |
6757 | * Return Values: | |
6758 | * ADV_TRUE - command completed successfully | |
6759 | * ADV_FALSE - command failed | |
6760 | * ADV_ERROR - command timed out | |
6761 | */ | |
6762 | static int | |
6763 | AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc, | |
6764 | ushort idle_cmd, ADV_DCNT idle_cmd_parameter) | |
6765 | { | |
6766 | int result; | |
6767 | ADV_DCNT i, j; | |
6768 | AdvPortAddr iop_base; | |
6769 | ||
6770 | iop_base = asc_dvc->iop_base; | |
6771 | ||
6772 | /* | |
6773 | * Clear the idle command status which is set by the microcode | |
6774 | * to a non-zero value to indicate when the command is completed. | |
6775 | * The non-zero result is one of the IDLE_CMD_STATUS_* values | |
6776 | */ | |
6777 | AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0); | |
6778 | ||
6779 | /* | |
6780 | * Write the idle command value after the idle command parameter | |
6781 | * has been written to avoid a race condition. If the order is not | |
6782 | * followed, the microcode may process the idle command before the | |
6783 | * parameters have been written to LRAM. | |
6784 | */ | |
6785 | AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER, | |
6786 | cpu_to_le32(idle_cmd_parameter)); | |
6787 | AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd); | |
6788 | ||
6789 | /* | |
6790 | * Tickle the RISC to tell it to process the idle command. | |
6791 | */ | |
6792 | AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B); | |
6793 | if (asc_dvc->chip_type == ADV_CHIP_ASC3550) { | |
6794 | /* | |
6795 | * Clear the tickle value. In the ASC-3550 the RISC flag | |
6796 | * command 'clr_tickle_b' does not work unless the host | |
6797 | * value is cleared. | |
6798 | */ | |
6799 | AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP); | |
6800 | } | |
6801 | ||
6802 | /* Wait for up to 100 millisecond for the idle command to timeout. */ | |
6803 | for (i = 0; i < SCSI_WAIT_100_MSEC; i++) { | |
6804 | /* Poll once each microsecond for command completion. */ | |
6805 | for (j = 0; j < SCSI_US_PER_MSEC; j++) { | |
6806 | AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, | |
6807 | result); | |
6808 | if (result != 0) | |
6809 | return result; | |
6810 | udelay(1); | |
6811 | } | |
6812 | } | |
6813 | ||
6814 | BUG(); /* The idle command should never timeout. */ | |
6815 | return ADV_ERROR; | |
6816 | } | |
6817 | ||
6818 | /* | |
6819 | * Reset SCSI Bus and purge all outstanding requests. | |
6820 | * | |
6821 | * Return Value: | |
6822 | * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset. | |
6823 | * ADV_FALSE(0) - Microcode command failed. | |
6824 | * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC | |
6825 | * may be hung which requires driver recovery. | |
6826 | */ | |
6827 | static int AdvResetSB(ADV_DVC_VAR *asc_dvc) | |
6828 | { | |
6829 | int status; | |
6830 | ||
6831 | /* | |
6832 | * Send the SCSI Bus Reset idle start idle command which asserts | |
6833 | * the SCSI Bus Reset signal. | |
6834 | */ | |
6835 | status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L); | |
6836 | if (status != ADV_TRUE) { | |
6837 | return status; | |
6838 | } | |
6839 | ||
6840 | /* | |
6841 | * Delay for the specified SCSI Bus Reset hold time. | |
6842 | * | |
6843 | * The hold time delay is done on the host because the RISC has no | |
6844 | * microsecond accurate timer. | |
6845 | */ | |
6846 | udelay(ASC_SCSI_RESET_HOLD_TIME_US); | |
6847 | ||
6848 | /* | |
6849 | * Send the SCSI Bus Reset end idle command which de-asserts | |
6850 | * the SCSI Bus Reset signal and purges any pending requests. | |
6851 | */ | |
6852 | status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L); | |
6853 | if (status != ADV_TRUE) { | |
6854 | return status; | |
6855 | } | |
6856 | ||
6857 | mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */ | |
6858 | ||
6859 | return status; | |
6860 | } | |
6861 | ||
6862 | /* | |
6863 | * Initialize the ASC-3550. | |
6864 | * | |
6865 | * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR. | |
6866 | * | |
6867 | * For a non-fatal error return a warning code. If there are no warnings | |
6868 | * then 0 is returned. | |
6869 | * | |
6870 | * Needed after initialization for error recovery. | |
6871 | */ | |
6872 | static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc) | |
6873 | { | |
6874 | AdvPortAddr iop_base; | |
6875 | ushort warn_code; | |
6876 | int begin_addr; | |
6877 | int end_addr; | |
6878 | ushort code_sum; | |
6879 | int word; | |
6880 | int i; | |
6881 | ushort scsi_cfg1; | |
6882 | uchar tid; | |
6883 | ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */ | |
6884 | ushort wdtr_able = 0, sdtr_able, tagqng_able; | |
6885 | uchar max_cmd[ADV_MAX_TID + 1]; | |
6886 | ||
6887 | /* If there is already an error, don't continue. */ | |
6888 | if (asc_dvc->err_code != 0) | |
6889 | return ADV_ERROR; | |
6890 | ||
6891 | /* | |
6892 | * The caller must set 'chip_type' to ADV_CHIP_ASC3550. | |
6893 | */ | |
6894 | if (asc_dvc->chip_type != ADV_CHIP_ASC3550) { | |
6895 | asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE; | |
6896 | return ADV_ERROR; | |
6897 | } | |
6898 | ||
6899 | warn_code = 0; | |
6900 | iop_base = asc_dvc->iop_base; | |
6901 | ||
6902 | /* | |
6903 | * Save the RISC memory BIOS region before writing the microcode. | |
6904 | * The BIOS may already be loaded and using its RISC LRAM region | |
6905 | * so its region must be saved and restored. | |
6906 | * | |
6907 | * Note: This code makes the assumption, which is currently true, | |
6908 | * that a chip reset does not clear RISC LRAM. | |
6909 | */ | |
6910 | for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) { | |
6911 | AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), | |
6912 | bios_mem[i]); | |
6913 | } | |
6914 | ||
6915 | /* | |
6916 | * Save current per TID negotiated values. | |
6917 | */ | |
6918 | if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) { | |
6919 | ushort bios_version, major, minor; | |
6920 | ||
6921 | bios_version = | |
6922 | bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2]; | |
6923 | major = (bios_version >> 12) & 0xF; | |
6924 | minor = (bios_version >> 8) & 0xF; | |
6925 | if (major < 3 || (major == 3 && minor == 1)) { | |
6926 | /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */ | |
6927 | AdvReadWordLram(iop_base, 0x120, wdtr_able); | |
6928 | } else { | |
6929 | AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); | |
6930 | } | |
6931 | } | |
6932 | AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); | |
6933 | AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able); | |
6934 | for (tid = 0; tid <= ADV_MAX_TID; tid++) { | |
6935 | AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid, | |
6936 | max_cmd[tid]); | |
6937 | } | |
6938 | ||
6939 | asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc3550_buf, | |
6940 | _adv_asc3550_size, ADV_3550_MEMSIZE, | |
6941 | _adv_asc3550_chksum); | |
6942 | if (asc_dvc->err_code) | |
6943 | return ADV_ERROR; | |
6944 | ||
6945 | /* | |
6946 | * Restore the RISC memory BIOS region. | |
6947 | */ | |
6948 | for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) { | |
6949 | AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), | |
6950 | bios_mem[i]); | |
6951 | } | |
6952 | ||
6953 | /* | |
6954 | * Calculate and write the microcode code checksum to the microcode | |
6955 | * code checksum location ASC_MC_CODE_CHK_SUM (0x2C). | |
6956 | */ | |
6957 | AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr); | |
6958 | AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr); | |
6959 | code_sum = 0; | |
6960 | AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr); | |
6961 | for (word = begin_addr; word < end_addr; word += 2) { | |
6962 | code_sum += AdvReadWordAutoIncLram(iop_base); | |
6963 | } | |
6964 | AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum); | |
6965 | ||
6966 | /* | |
6967 | * Read and save microcode version and date. | |
6968 | */ | |
6969 | AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, | |
6970 | asc_dvc->cfg->mcode_date); | |
6971 | AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, | |
6972 | asc_dvc->cfg->mcode_version); | |
6973 | ||
6974 | /* | |
6975 | * Set the chip type to indicate the ASC3550. | |
6976 | */ | |
6977 | AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550); | |
6978 | ||
6979 | /* | |
6980 | * If the PCI Configuration Command Register "Parity Error Response | |
6981 | * Control" Bit was clear (0), then set the microcode variable | |
6982 | * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode | |
6983 | * to ignore DMA parity errors. | |
6984 | */ | |
6985 | if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) { | |
6986 | AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); | |
6987 | word |= CONTROL_FLAG_IGNORE_PERR; | |
6988 | AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); | |
6989 | } | |
6990 | ||
6991 | /* | |
6992 | * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO | |
6993 | * threshold of 128 bytes. This register is only accessible to the host. | |
6994 | */ | |
6995 | AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0, | |
6996 | START_CTL_EMFU | READ_CMD_MRM); | |
6997 | ||
6998 | /* | |
6999 | * Microcode operating variables for WDTR, SDTR, and command tag | |
7000 | * queuing will be set in slave_configure() based on what a | |
7001 | * device reports it is capable of in Inquiry byte 7. | |
7002 | * | |
7003 | * If SCSI Bus Resets have been disabled, then directly set | |
7004 | * SDTR and WDTR from the EEPROM configuration. This will allow | |
7005 | * the BIOS and warm boot to work without a SCSI bus hang on | |
7006 | * the Inquiry caused by host and target mismatched DTR values. | |
7007 | * Without the SCSI Bus Reset, before an Inquiry a device can't | |
7008 | * be assumed to be in Asynchronous, Narrow mode. | |
7009 | */ | |
7010 | if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { | |
7011 | AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, | |
7012 | asc_dvc->wdtr_able); | |
7013 | AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, | |
7014 | asc_dvc->sdtr_able); | |
7015 | } | |
7016 | ||
7017 | /* | |
7018 | * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2, | |
7019 | * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID | |
7020 | * bitmask. These values determine the maximum SDTR speed negotiated | |
7021 | * with a device. | |
7022 | * | |
7023 | * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, | |
7024 | * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them | |
7025 | * without determining here whether the device supports SDTR. | |
7026 | * | |
7027 | * 4-bit speed SDTR speed name | |
7028 | * =========== =============== | |
7029 | * 0000b (0x0) SDTR disabled | |
7030 | * 0001b (0x1) 5 Mhz | |
7031 | * 0010b (0x2) 10 Mhz | |
7032 | * 0011b (0x3) 20 Mhz (Ultra) | |
7033 | * 0100b (0x4) 40 Mhz (LVD/Ultra2) | |
7034 | * 0101b (0x5) 80 Mhz (LVD2/Ultra3) | |
7035 | * 0110b (0x6) Undefined | |
7036 | * . | |
7037 | * 1111b (0xF) Undefined | |
7038 | */ | |
7039 | word = 0; | |
7040 | for (tid = 0; tid <= ADV_MAX_TID; tid++) { | |
7041 | if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) { | |
7042 | /* Set Ultra speed for TID 'tid'. */ | |
7043 | word |= (0x3 << (4 * (tid % 4))); | |
7044 | } else { | |
7045 | /* Set Fast speed for TID 'tid'. */ | |
7046 | word |= (0x2 << (4 * (tid % 4))); | |
7047 | } | |
7048 | if (tid == 3) { /* Check if done with sdtr_speed1. */ | |
7049 | AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word); | |
7050 | word = 0; | |
7051 | } else if (tid == 7) { /* Check if done with sdtr_speed2. */ | |
7052 | AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word); | |
7053 | word = 0; | |
7054 | } else if (tid == 11) { /* Check if done with sdtr_speed3. */ | |
7055 | AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word); | |
7056 | word = 0; | |
7057 | } else if (tid == 15) { /* Check if done with sdtr_speed4. */ | |
7058 | AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word); | |
7059 | /* End of loop. */ | |
7060 | } | |
7061 | } | |
7062 | ||
7063 | /* | |
7064 | * Set microcode operating variable for the disconnect per TID bitmask. | |
7065 | */ | |
7066 | AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, | |
7067 | asc_dvc->cfg->disc_enable); | |
7068 | ||
7069 | /* | |
7070 | * Set SCSI_CFG0 Microcode Default Value. | |
7071 | * | |
7072 | * The microcode will set the SCSI_CFG0 register using this value | |
7073 | * after it is started below. | |
7074 | */ | |
7075 | AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0, | |
7076 | PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN | | |
7077 | asc_dvc->chip_scsi_id); | |
7078 | ||
7079 | /* | |
7080 | * Determine SCSI_CFG1 Microcode Default Value. | |
7081 | * | |
7082 | * The microcode will set the SCSI_CFG1 register using this value | |
7083 | * after it is started below. | |
7084 | */ | |
7085 | ||
7086 | /* Read current SCSI_CFG1 Register value. */ | |
7087 | scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1); | |
7088 | ||
7089 | /* | |
7090 | * If all three connectors are in use, return an error. | |
7091 | */ | |
7092 | if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 || | |
7093 | (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) { | |
7094 | asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION; | |
7095 | return ADV_ERROR; | |
7096 | } | |
7097 | ||
7098 | /* | |
7099 | * If the internal narrow cable is reversed all of the SCSI_CTRL | |
7100 | * register signals will be set. Check for and return an error if | |
7101 | * this condition is found. | |
7102 | */ | |
7103 | if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) { | |
7104 | asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE; | |
7105 | return ADV_ERROR; | |
7106 | } | |
7107 | ||
7108 | /* | |
7109 | * If this is a differential board and a single-ended device | |
7110 | * is attached to one of the connectors, return an error. | |
7111 | */ | |
7112 | if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) { | |
7113 | asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE; | |
7114 | return ADV_ERROR; | |
7115 | } | |
7116 | ||
7117 | /* | |
7118 | * If automatic termination control is enabled, then set the | |
7119 | * termination value based on a table listed in a_condor.h. | |
7120 | * | |
7121 | * If manual termination was specified with an EEPROM setting | |
7122 | * then 'termination' was set-up in AdvInitFrom3550EEPROM() and | |
7123 | * is ready to be 'ored' into SCSI_CFG1. | |
7124 | */ | |
7125 | if (asc_dvc->cfg->termination == 0) { | |
7126 | /* | |
7127 | * The software always controls termination by setting TERM_CTL_SEL. | |
7128 | * If TERM_CTL_SEL were set to 0, the hardware would set termination. | |
7129 | */ | |
7130 | asc_dvc->cfg->termination |= TERM_CTL_SEL; | |
7131 | ||
7132 | switch (scsi_cfg1 & CABLE_DETECT) { | |
7133 | /* TERM_CTL_H: on, TERM_CTL_L: on */ | |
7134 | case 0x3: | |
7135 | case 0x7: | |
7136 | case 0xB: | |
7137 | case 0xD: | |
7138 | case 0xE: | |
7139 | case 0xF: | |
7140 | asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L); | |
7141 | break; | |
7142 | ||
7143 | /* TERM_CTL_H: on, TERM_CTL_L: off */ | |
7144 | case 0x1: | |
7145 | case 0x5: | |
7146 | case 0x9: | |
7147 | case 0xA: | |
7148 | case 0xC: | |
7149 | asc_dvc->cfg->termination |= TERM_CTL_H; | |
7150 | break; | |
7151 | ||
7152 | /* TERM_CTL_H: off, TERM_CTL_L: off */ | |
7153 | case 0x2: | |
7154 | case 0x6: | |
7155 | break; | |
7156 | } | |
7157 | } | |
7158 | ||
7159 | /* | |
7160 | * Clear any set TERM_CTL_H and TERM_CTL_L bits. | |
7161 | */ | |
7162 | scsi_cfg1 &= ~TERM_CTL; | |
7163 | ||
7164 | /* | |
7165 | * Invert the TERM_CTL_H and TERM_CTL_L bits and then | |
7166 | * set 'scsi_cfg1'. The TERM_POL bit does not need to be | |
7167 | * referenced, because the hardware internally inverts | |
7168 | * the Termination High and Low bits if TERM_POL is set. | |
7169 | */ | |
7170 | scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL)); | |
7171 | ||
7172 | /* | |
7173 | * Set SCSI_CFG1 Microcode Default Value | |
7174 | * | |
7175 | * Set filter value and possibly modified termination control | |
7176 | * bits in the Microcode SCSI_CFG1 Register Value. | |
7177 | * | |
7178 | * The microcode will set the SCSI_CFG1 register using this value | |
7179 | * after it is started below. | |
7180 | */ | |
7181 | AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, | |
7182 | FLTR_DISABLE | scsi_cfg1); | |
7183 | ||
7184 | /* | |
7185 | * Set MEM_CFG Microcode Default Value | |
7186 | * | |
7187 | * The microcode will set the MEM_CFG register using this value | |
7188 | * after it is started below. | |
7189 | * | |
7190 | * MEM_CFG may be accessed as a word or byte, but only bits 0-7 | |
7191 | * are defined. | |
7192 | * | |
7193 | * ASC-3550 has 8KB internal memory. | |
7194 | */ | |
7195 | AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG, | |
7196 | BIOS_EN | RAM_SZ_8KB); | |
7197 | ||
7198 | /* | |
7199 | * Set SEL_MASK Microcode Default Value | |
7200 | * | |
7201 | * The microcode will set the SEL_MASK register using this value | |
7202 | * after it is started below. | |
7203 | */ | |
7204 | AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK, | |
7205 | ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id)); | |
7206 | ||
7207 | AdvBuildCarrierFreelist(asc_dvc); | |
7208 | ||
7209 | /* | |
7210 | * Set-up the Host->RISC Initiator Command Queue (ICQ). | |
7211 | */ | |
7212 | ||
7213 | if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) { | |
7214 | asc_dvc->err_code |= ASC_IERR_NO_CARRIER; | |
7215 | return ADV_ERROR; | |
7216 | } | |
7217 | asc_dvc->carr_freelist = (ADV_CARR_T *) | |
7218 | ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa)); | |
7219 | ||
7220 | /* | |
7221 | * The first command issued will be placed in the stopper carrier. | |
7222 | */ | |
7223 | asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER); | |
7224 | ||
7225 | /* | |
7226 | * Set RISC ICQ physical address start value. | |
7227 | */ | |
7228 | AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa); | |
7229 | ||
7230 | /* | |
7231 | * Set-up the RISC->Host Initiator Response Queue (IRQ). | |
7232 | */ | |
7233 | if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) { | |
7234 | asc_dvc->err_code |= ASC_IERR_NO_CARRIER; | |
7235 | return ADV_ERROR; | |
7236 | } | |
7237 | asc_dvc->carr_freelist = (ADV_CARR_T *) | |
7238 | ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa)); | |
7239 | ||
7240 | /* | |
7241 | * The first command completed by the RISC will be placed in | |
7242 | * the stopper. | |
7243 | * | |
7244 | * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is | |
7245 | * completed the RISC will set the ASC_RQ_STOPPER bit. | |
7246 | */ | |
7247 | asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER); | |
7248 | ||
7249 | /* | |
7250 | * Set RISC IRQ physical address start value. | |
7251 | */ | |
7252 | AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa); | |
7253 | asc_dvc->carr_pending_cnt = 0; | |
7254 | ||
7255 | AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES, | |
7256 | (ADV_INTR_ENABLE_HOST_INTR | | |
7257 | ADV_INTR_ENABLE_GLOBAL_INTR)); | |
7258 | ||
7259 | AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word); | |
7260 | AdvWriteWordRegister(iop_base, IOPW_PC, word); | |
7261 | ||
7262 | /* finally, finally, gentlemen, start your engine */ | |
7263 | AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN); | |
7264 | ||
7265 | /* | |
7266 | * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus | |
7267 | * Resets should be performed. The RISC has to be running | |
7268 | * to issue a SCSI Bus Reset. | |
7269 | */ | |
7270 | if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) { | |
7271 | /* | |
7272 | * If the BIOS Signature is present in memory, restore the | |
7273 | * BIOS Handshake Configuration Table and do not perform | |
7274 | * a SCSI Bus Reset. | |
7275 | */ | |
7276 | if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == | |
7277 | 0x55AA) { | |
7278 | /* | |
7279 | * Restore per TID negotiated values. | |
7280 | */ | |
7281 | AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); | |
7282 | AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); | |
7283 | AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, | |
7284 | tagqng_able); | |
7285 | for (tid = 0; tid <= ADV_MAX_TID; tid++) { | |
7286 | AdvWriteByteLram(iop_base, | |
7287 | ASC_MC_NUMBER_OF_MAX_CMD + tid, | |
7288 | max_cmd[tid]); | |
7289 | } | |
7290 | } else { | |
7291 | if (AdvResetSB(asc_dvc) != ADV_TRUE) { | |
7292 | warn_code = ASC_WARN_BUSRESET_ERROR; | |
7293 | } | |
7294 | } | |
7295 | } | |
7296 | ||
7297 | return warn_code; | |
7298 | } | |
7299 | ||
7300 | /* | |
7301 | * Initialize the ASC-38C0800. | |
7302 | * | |
7303 | * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR. | |
7304 | * | |
7305 | * For a non-fatal error return a warning code. If there are no warnings | |
7306 | * then 0 is returned. | |
7307 | * | |
7308 | * Needed after initialization for error recovery. | |
7309 | */ | |
7310 | static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc) | |
7311 | { | |
7312 | AdvPortAddr iop_base; | |
7313 | ushort warn_code; | |
7314 | int begin_addr; | |
7315 | int end_addr; | |
7316 | ushort code_sum; | |
7317 | int word; | |
7318 | int i; | |
7319 | ushort scsi_cfg1; | |
7320 | uchar byte; | |
7321 | uchar tid; | |
7322 | ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */ | |
7323 | ushort wdtr_able, sdtr_able, tagqng_able; | |
7324 | uchar max_cmd[ADV_MAX_TID + 1]; | |
7325 | ||
7326 | /* If there is already an error, don't continue. */ | |
7327 | if (asc_dvc->err_code != 0) | |
7328 | return ADV_ERROR; | |
7329 | ||
7330 | /* | |
7331 | * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800. | |
7332 | */ | |
7333 | if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) { | |
7334 | asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE; | |
7335 | return ADV_ERROR; | |
7336 | } | |
7337 | ||
7338 | warn_code = 0; | |
7339 | iop_base = asc_dvc->iop_base; | |
7340 | ||
7341 | /* | |
7342 | * Save the RISC memory BIOS region before writing the microcode. | |
7343 | * The BIOS may already be loaded and using its RISC LRAM region | |
7344 | * so its region must be saved and restored. | |
7345 | * | |
7346 | * Note: This code makes the assumption, which is currently true, | |
7347 | * that a chip reset does not clear RISC LRAM. | |
7348 | */ | |
7349 | for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) { | |
7350 | AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), | |
7351 | bios_mem[i]); | |
7352 | } | |
7353 | ||
7354 | /* | |
7355 | * Save current per TID negotiated values. | |
7356 | */ | |
7357 | AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); | |
7358 | AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); | |
7359 | AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able); | |
7360 | for (tid = 0; tid <= ADV_MAX_TID; tid++) { | |
7361 | AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid, | |
7362 | max_cmd[tid]); | |
7363 | } | |
7364 | ||
7365 | /* | |
7366 | * RAM BIST (RAM Built-In Self Test) | |
7367 | * | |
7368 | * Address : I/O base + offset 0x38h register (byte). | |
7369 | * Function: Bit 7-6(RW) : RAM mode | |
7370 | * Normal Mode : 0x00 | |
7371 | * Pre-test Mode : 0x40 | |
7372 | * RAM Test Mode : 0x80 | |
7373 | * Bit 5 : unused | |
7374 | * Bit 4(RO) : Done bit | |
7375 | * Bit 3-0(RO) : Status | |
7376 | * Host Error : 0x08 | |
7377 | * Int_RAM Error : 0x04 | |
7378 | * RISC Error : 0x02 | |
7379 | * SCSI Error : 0x01 | |
7380 | * No Error : 0x00 | |
7381 | * | |
7382 | * Note: RAM BIST code should be put right here, before loading the | |
7383 | * microcode and after saving the RISC memory BIOS region. | |
7384 | */ | |
7385 | ||
7386 | /* | |
7387 | * LRAM Pre-test | |
7388 | * | |
7389 | * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds. | |
7390 | * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return | |
7391 | * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset | |
7392 | * to NORMAL_MODE, return an error too. | |
7393 | */ | |
7394 | for (i = 0; i < 2; i++) { | |
7395 | AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE); | |
7396 | mdelay(10); /* Wait for 10ms before reading back. */ | |
7397 | byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST); | |
7398 | if ((byte & RAM_TEST_DONE) == 0 | |
7399 | || (byte & 0x0F) != PRE_TEST_VALUE) { | |
7400 | asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST; | |
7401 | return ADV_ERROR; | |
7402 | } | |
7403 | ||
7404 | AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE); | |
7405 | mdelay(10); /* Wait for 10ms before reading back. */ | |
7406 | if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST) | |
7407 | != NORMAL_VALUE) { | |
7408 | asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST; | |
7409 | return ADV_ERROR; | |
7410 | } | |
7411 | } | |
7412 | ||
7413 | /* | |
7414 | * LRAM Test - It takes about 1.5 ms to run through the test. | |
7415 | * | |
7416 | * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds. | |
7417 | * If Done bit not set or Status not 0, save register byte, set the | |
7418 | * err_code, and return an error. | |
7419 | */ | |
7420 | AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE); | |
7421 | mdelay(10); /* Wait for 10ms before checking status. */ | |
7422 | ||
7423 | byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST); | |
7424 | if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) { | |
7425 | /* Get here if Done bit not set or Status not 0. */ | |
7426 | asc_dvc->bist_err_code = byte; /* for BIOS display message */ | |
7427 | asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST; | |
7428 | return ADV_ERROR; | |
7429 | } | |
7430 | ||
7431 | /* We need to reset back to normal mode after LRAM test passes. */ | |
7432 | AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE); | |
7433 | ||
7434 | asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc38C0800_buf, | |
7435 | _adv_asc38C0800_size, ADV_38C0800_MEMSIZE, | |
7436 | _adv_asc38C0800_chksum); | |
7437 | if (asc_dvc->err_code) | |
7438 | return ADV_ERROR; | |
7439 | ||
7440 | /* | |
7441 | * Restore the RISC memory BIOS region. | |
7442 | */ | |
7443 | for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) { | |
7444 | AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), | |
7445 | bios_mem[i]); | |
7446 | } | |
7447 | ||
7448 | /* | |
7449 | * Calculate and write the microcode code checksum to the microcode | |
7450 | * code checksum location ASC_MC_CODE_CHK_SUM (0x2C). | |
7451 | */ | |
7452 | AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr); | |
7453 | AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr); | |
7454 | code_sum = 0; | |
7455 | AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr); | |
7456 | for (word = begin_addr; word < end_addr; word += 2) { | |
7457 | code_sum += AdvReadWordAutoIncLram(iop_base); | |
7458 | } | |
7459 | AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum); | |
7460 | ||
7461 | /* | |
7462 | * Read microcode version and date. | |
7463 | */ | |
7464 | AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, | |
7465 | asc_dvc->cfg->mcode_date); | |
7466 | AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, | |
7467 | asc_dvc->cfg->mcode_version); | |
7468 | ||
7469 | /* | |
7470 | * Set the chip type to indicate the ASC38C0800. | |
7471 | */ | |
7472 | AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800); | |
7473 | ||
7474 | /* | |
7475 | * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. | |
7476 | * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current | |
7477 | * cable detection and then we are able to read C_DET[3:0]. | |
7478 | * | |
7479 | * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 | |
7480 | * Microcode Default Value' section below. | |
7481 | */ | |
7482 | scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1); | |
7483 | AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1, | |
7484 | scsi_cfg1 | DIS_TERM_DRV); | |
7485 | ||
7486 | /* | |
7487 | * If the PCI Configuration Command Register "Parity Error Response | |
7488 | * Control" Bit was clear (0), then set the microcode variable | |
7489 | * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode | |
7490 | * to ignore DMA parity errors. | |
7491 | */ | |
7492 | if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) { | |
7493 | AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); | |
7494 | word |= CONTROL_FLAG_IGNORE_PERR; | |
7495 | AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); | |
7496 | } | |
7497 | ||
7498 | /* | |
7499 | * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2] | |
7500 | * bits for the default FIFO threshold. | |
7501 | * | |
7502 | * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes. | |
7503 | * | |
7504 | * For DMA Errata #4 set the BC_THRESH_ENB bit. | |
7505 | */ | |
7506 | AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0, | |
7507 | BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH | | |
7508 | READ_CMD_MRM); | |
7509 | ||
7510 | /* | |
7511 | * Microcode operating variables for WDTR, SDTR, and command tag | |
7512 | * queuing will be set in slave_configure() based on what a | |
7513 | * device reports it is capable of in Inquiry byte 7. | |
7514 | * | |
7515 | * If SCSI Bus Resets have been disabled, then directly set | |
7516 | * SDTR and WDTR from the EEPROM configuration. This will allow | |
7517 | * the BIOS and warm boot to work without a SCSI bus hang on | |
7518 | * the Inquiry caused by host and target mismatched DTR values. | |
7519 | * Without the SCSI Bus Reset, before an Inquiry a device can't | |
7520 | * be assumed to be in Asynchronous, Narrow mode. | |
7521 | */ | |
7522 | if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { | |
7523 | AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, | |
7524 | asc_dvc->wdtr_able); | |
7525 | AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, | |
7526 | asc_dvc->sdtr_able); | |
7527 | } | |
7528 | ||
7529 | /* | |
7530 | * Set microcode operating variables for DISC and SDTR_SPEED1, | |
7531 | * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM | |
7532 | * configuration values. | |
7533 | * | |
7534 | * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, | |
7535 | * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them | |
7536 | * without determining here whether the device supports SDTR. | |
7537 | */ | |
7538 | AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, | |
7539 | asc_dvc->cfg->disc_enable); | |
7540 | AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1); | |
7541 | AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2); | |
7542 | AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3); | |
7543 | AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4); | |
7544 | ||
7545 | /* | |
7546 | * Set SCSI_CFG0 Microcode Default Value. | |
7547 | * | |
7548 | * The microcode will set the SCSI_CFG0 register using this value | |
7549 | * after it is started below. | |
7550 | */ | |
7551 | AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0, | |
7552 | PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN | | |
7553 | asc_dvc->chip_scsi_id); | |
7554 | ||
7555 | /* | |
7556 | * Determine SCSI_CFG1 Microcode Default Value. | |
7557 | * | |
7558 | * The microcode will set the SCSI_CFG1 register using this value | |
7559 | * after it is started below. | |
7560 | */ | |
7561 | ||
7562 | /* Read current SCSI_CFG1 Register value. */ | |
7563 | scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1); | |
7564 | ||
7565 | /* | |
7566 | * If the internal narrow cable is reversed all of the SCSI_CTRL | |
7567 | * register signals will be set. Check for and return an error if | |
7568 | * this condition is found. | |
7569 | */ | |
7570 | if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) { | |
7571 | asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE; | |
7572 | return ADV_ERROR; | |
7573 | } | |
7574 | ||
7575 | /* | |
7576 | * All kind of combinations of devices attached to one of four | |
7577 | * connectors are acceptable except HVD device attached. For example, | |
7578 | * LVD device can be attached to SE connector while SE device attached | |
7579 | * to LVD connector. If LVD device attached to SE connector, it only | |
7580 | * runs up to Ultra speed. | |
7581 | * | |
7582 | * If an HVD device is attached to one of LVD connectors, return an | |
7583 | * error. However, there is no way to detect HVD device attached to | |
7584 | * SE connectors. | |
7585 | */ | |
7586 | if (scsi_cfg1 & HVD) { | |
7587 | asc_dvc->err_code = ASC_IERR_HVD_DEVICE; | |
7588 | return ADV_ERROR; | |
7589 | } | |
7590 | ||
7591 | /* | |
7592 | * If either SE or LVD automatic termination control is enabled, then | |
7593 | * set the termination value based on a table listed in a_condor.h. | |
7594 | * | |
7595 | * If manual termination was specified with an EEPROM setting then | |
7596 | * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready | |
7597 | * to be 'ored' into SCSI_CFG1. | |
7598 | */ | |
7599 | if ((asc_dvc->cfg->termination & TERM_SE) == 0) { | |
7600 | /* SE automatic termination control is enabled. */ | |
7601 | switch (scsi_cfg1 & C_DET_SE) { | |
7602 | /* TERM_SE_HI: on, TERM_SE_LO: on */ | |
7603 | case 0x1: | |
7604 | case 0x2: | |
7605 | case 0x3: | |
7606 | asc_dvc->cfg->termination |= TERM_SE; | |
7607 | break; | |
7608 | ||
7609 | /* TERM_SE_HI: on, TERM_SE_LO: off */ | |
7610 | case 0x0: | |
7611 | asc_dvc->cfg->termination |= TERM_SE_HI; | |
7612 | break; | |
7613 | } | |
7614 | } | |
7615 | ||
7616 | if ((asc_dvc->cfg->termination & TERM_LVD) == 0) { | |
7617 | /* LVD automatic termination control is enabled. */ | |
7618 | switch (scsi_cfg1 & C_DET_LVD) { | |
7619 | /* TERM_LVD_HI: on, TERM_LVD_LO: on */ | |
7620 | case 0x4: | |
7621 | case 0x8: | |
7622 | case 0xC: | |
7623 | asc_dvc->cfg->termination |= TERM_LVD; | |
7624 | break; | |
7625 | ||
7626 | /* TERM_LVD_HI: off, TERM_LVD_LO: off */ | |
7627 | case 0x0: | |
7628 | break; | |
7629 | } | |
7630 | } | |
7631 | ||
7632 | /* | |
7633 | * Clear any set TERM_SE and TERM_LVD bits. | |
7634 | */ | |
7635 | scsi_cfg1 &= (~TERM_SE & ~TERM_LVD); | |
7636 | ||
7637 | /* | |
7638 | * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'. | |
7639 | */ | |
7640 | scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0); | |
7641 | ||
7642 | /* | |
7643 | * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE | |
7644 | * bits and set possibly modified termination control bits in the | |
7645 | * Microcode SCSI_CFG1 Register Value. | |
7646 | */ | |
7647 | scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE); | |
7648 | ||
7649 | /* | |
7650 | * Set SCSI_CFG1 Microcode Default Value | |
7651 | * | |
7652 | * Set possibly modified termination control and reset DIS_TERM_DRV | |
7653 | * bits in the Microcode SCSI_CFG1 Register Value. | |
7654 | * | |
7655 | * The microcode will set the SCSI_CFG1 register using this value | |
7656 | * after it is started below. | |
7657 | */ | |
7658 | AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); | |
7659 | ||
7660 | /* | |
7661 | * Set MEM_CFG Microcode Default Value | |
7662 | * | |
7663 | * The microcode will set the MEM_CFG register using this value | |
7664 | * after it is started below. | |
7665 | * | |
7666 | * MEM_CFG may be accessed as a word or byte, but only bits 0-7 | |
7667 | * are defined. | |
7668 | * | |
7669 | * ASC-38C0800 has 16KB internal memory. | |
7670 | */ | |
7671 | AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG, | |
7672 | BIOS_EN | RAM_SZ_16KB); | |
7673 | ||
7674 | /* | |
7675 | * Set SEL_MASK Microcode Default Value | |
7676 | * | |
7677 | * The microcode will set the SEL_MASK register using this value | |
7678 | * after it is started below. | |
7679 | */ | |
7680 | AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK, | |
7681 | ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id)); | |
7682 | ||
7683 | AdvBuildCarrierFreelist(asc_dvc); | |
7684 | ||
7685 | /* | |
7686 | * Set-up the Host->RISC Initiator Command Queue (ICQ). | |
7687 | */ | |
7688 | ||
7689 | if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) { | |
7690 | asc_dvc->err_code |= ASC_IERR_NO_CARRIER; | |
7691 | return ADV_ERROR; | |
7692 | } | |
7693 | asc_dvc->carr_freelist = (ADV_CARR_T *) | |
7694 | ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa)); | |
7695 | ||
7696 | /* | |
7697 | * The first command issued will be placed in the stopper carrier. | |
7698 | */ | |
7699 | asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER); | |
7700 | ||
7701 | /* | |
7702 | * Set RISC ICQ physical address start value. | |
7703 | * carr_pa is LE, must be native before write | |
7704 | */ | |
7705 | AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa); | |
7706 | ||
7707 | /* | |
7708 | * Set-up the RISC->Host Initiator Response Queue (IRQ). | |
7709 | */ | |
7710 | if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) { | |
7711 | asc_dvc->err_code |= ASC_IERR_NO_CARRIER; | |
7712 | return ADV_ERROR; | |
7713 | } | |
7714 | asc_dvc->carr_freelist = (ADV_CARR_T *) | |
7715 | ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa)); | |
7716 | ||
7717 | /* | |
7718 | * The first command completed by the RISC will be placed in | |
7719 | * the stopper. | |
7720 | * | |
7721 | * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is | |
7722 | * completed the RISC will set the ASC_RQ_STOPPER bit. | |
7723 | */ | |
7724 | asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER); | |
7725 | ||
7726 | /* | |
7727 | * Set RISC IRQ physical address start value. | |
7728 | * | |
7729 | * carr_pa is LE, must be native before write * | |
7730 | */ | |
7731 | AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa); | |
7732 | asc_dvc->carr_pending_cnt = 0; | |
7733 | ||
7734 | AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES, | |
7735 | (ADV_INTR_ENABLE_HOST_INTR | | |
7736 | ADV_INTR_ENABLE_GLOBAL_INTR)); | |
7737 | ||
7738 | AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word); | |
7739 | AdvWriteWordRegister(iop_base, IOPW_PC, word); | |
7740 | ||
7741 | /* finally, finally, gentlemen, start your engine */ | |
7742 | AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN); | |
7743 | ||
7744 | /* | |
7745 | * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus | |
7746 | * Resets should be performed. The RISC has to be running | |
7747 | * to issue a SCSI Bus Reset. | |
7748 | */ | |
7749 | if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) { | |
7750 | /* | |
7751 | * If the BIOS Signature is present in memory, restore the | |
7752 | * BIOS Handshake Configuration Table and do not perform | |
7753 | * a SCSI Bus Reset. | |
7754 | */ | |
7755 | if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == | |
7756 | 0x55AA) { | |
7757 | /* | |
7758 | * Restore per TID negotiated values. | |
7759 | */ | |
7760 | AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); | |
7761 | AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); | |
7762 | AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, | |
7763 | tagqng_able); | |
7764 | for (tid = 0; tid <= ADV_MAX_TID; tid++) { | |
7765 | AdvWriteByteLram(iop_base, | |
7766 | ASC_MC_NUMBER_OF_MAX_CMD + tid, | |
7767 | max_cmd[tid]); | |
7768 | } | |
7769 | } else { | |
7770 | if (AdvResetSB(asc_dvc) != ADV_TRUE) { | |
7771 | warn_code = ASC_WARN_BUSRESET_ERROR; | |
7772 | } | |
7773 | } | |
7774 | } | |
7775 | ||
7776 | return warn_code; | |
7777 | } | |
7778 | ||
7779 | /* | |
7780 | * Initialize the ASC-38C1600. | |
7781 | * | |
7782 | * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR. | |
7783 | * | |
7784 | * For a non-fatal error return a warning code. If there are no warnings | |
7785 | * then 0 is returned. | |
7786 | * | |
7787 | * Needed after initialization for error recovery. | |
7788 | */ | |
7789 | static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc) | |
7790 | { | |
7791 | AdvPortAddr iop_base; | |
7792 | ushort warn_code; | |
7793 | int begin_addr; | |
7794 | int end_addr; | |
7795 | ushort code_sum; | |
7796 | long word; | |
7797 | int i; | |
7798 | ushort scsi_cfg1; | |
7799 | uchar byte; | |
7800 | uchar tid; | |
7801 | ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */ | |
7802 | ushort wdtr_able, sdtr_able, ppr_able, tagqng_able; | |
7803 | uchar max_cmd[ASC_MAX_TID + 1]; | |
7804 | ||
7805 | /* If there is already an error, don't continue. */ | |
7806 | if (asc_dvc->err_code != 0) { | |
7807 | return ADV_ERROR; | |
7808 | } | |
7809 | ||
7810 | /* | |
7811 | * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600. | |
7812 | */ | |
7813 | if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) { | |
7814 | asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE; | |
7815 | return ADV_ERROR; | |
7816 | } | |
7817 | ||
7818 | warn_code = 0; | |
7819 | iop_base = asc_dvc->iop_base; | |
7820 | ||
7821 | /* | |
7822 | * Save the RISC memory BIOS region before writing the microcode. | |
7823 | * The BIOS may already be loaded and using its RISC LRAM region | |
7824 | * so its region must be saved and restored. | |
7825 | * | |
7826 | * Note: This code makes the assumption, which is currently true, | |
7827 | * that a chip reset does not clear RISC LRAM. | |
7828 | */ | |
7829 | for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) { | |
7830 | AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), | |
7831 | bios_mem[i]); | |
7832 | } | |
7833 | ||
7834 | /* | |
7835 | * Save current per TID negotiated values. | |
7836 | */ | |
7837 | AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); | |
7838 | AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); | |
7839 | AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able); | |
7840 | AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able); | |
7841 | for (tid = 0; tid <= ASC_MAX_TID; tid++) { | |
7842 | AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid, | |
7843 | max_cmd[tid]); | |
7844 | } | |
7845 | ||
7846 | /* | |
7847 | * RAM BIST (Built-In Self Test) | |
7848 | * | |
7849 | * Address : I/O base + offset 0x38h register (byte). | |
7850 | * Function: Bit 7-6(RW) : RAM mode | |
7851 | * Normal Mode : 0x00 | |
7852 | * Pre-test Mode : 0x40 | |
7853 | * RAM Test Mode : 0x80 | |
7854 | * Bit 5 : unused | |
7855 | * Bit 4(RO) : Done bit | |
7856 | * Bit 3-0(RO) : Status | |
7857 | * Host Error : 0x08 | |
7858 | * Int_RAM Error : 0x04 | |
7859 | * RISC Error : 0x02 | |
7860 | * SCSI Error : 0x01 | |
7861 | * No Error : 0x00 | |
7862 | * | |
7863 | * Note: RAM BIST code should be put right here, before loading the | |
7864 | * microcode and after saving the RISC memory BIOS region. | |
7865 | */ | |
7866 | ||
7867 | /* | |
7868 | * LRAM Pre-test | |
7869 | * | |
7870 | * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds. | |
7871 | * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return | |
7872 | * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset | |
7873 | * to NORMAL_MODE, return an error too. | |
7874 | */ | |
7875 | for (i = 0; i < 2; i++) { | |
7876 | AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE); | |
7877 | mdelay(10); /* Wait for 10ms before reading back. */ | |
7878 | byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST); | |
7879 | if ((byte & RAM_TEST_DONE) == 0 | |
7880 | || (byte & 0x0F) != PRE_TEST_VALUE) { | |
7881 | asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST; | |
7882 | return ADV_ERROR; | |
7883 | } | |
7884 | ||
7885 | AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE); | |
7886 | mdelay(10); /* Wait for 10ms before reading back. */ | |
7887 | if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST) | |
7888 | != NORMAL_VALUE) { | |
7889 | asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST; | |
7890 | return ADV_ERROR; | |
7891 | } | |
7892 | } | |
7893 | ||
7894 | /* | |
7895 | * LRAM Test - It takes about 1.5 ms to run through the test. | |
7896 | * | |
7897 | * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds. | |
7898 | * If Done bit not set or Status not 0, save register byte, set the | |
7899 | * err_code, and return an error. | |
7900 | */ | |
7901 | AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE); | |
7902 | mdelay(10); /* Wait for 10ms before checking status. */ | |
7903 | ||
7904 | byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST); | |
7905 | if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) { | |
7906 | /* Get here if Done bit not set or Status not 0. */ | |
7907 | asc_dvc->bist_err_code = byte; /* for BIOS display message */ | |
7908 | asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST; | |
7909 | return ADV_ERROR; | |
7910 | } | |
7911 | ||
7912 | /* We need to reset back to normal mode after LRAM test passes. */ | |
7913 | AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE); | |
7914 | ||
7915 | asc_dvc->err_code = AdvLoadMicrocode(iop_base, _adv_asc38C1600_buf, | |
7916 | _adv_asc38C1600_size, ADV_38C1600_MEMSIZE, | |
7917 | _adv_asc38C1600_chksum); | |
7918 | if (asc_dvc->err_code) | |
7919 | return ADV_ERROR; | |
7920 | ||
7921 | /* | |
7922 | * Restore the RISC memory BIOS region. | |
7923 | */ | |
7924 | for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) { | |
7925 | AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), | |
7926 | bios_mem[i]); | |
7927 | } | |
7928 | ||
7929 | /* | |
7930 | * Calculate and write the microcode code checksum to the microcode | |
7931 | * code checksum location ASC_MC_CODE_CHK_SUM (0x2C). | |
7932 | */ | |
7933 | AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr); | |
7934 | AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr); | |
7935 | code_sum = 0; | |
7936 | AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr); | |
7937 | for (word = begin_addr; word < end_addr; word += 2) { | |
7938 | code_sum += AdvReadWordAutoIncLram(iop_base); | |
7939 | } | |
7940 | AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum); | |
7941 | ||
7942 | /* | |
7943 | * Read microcode version and date. | |
7944 | */ | |
7945 | AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, | |
7946 | asc_dvc->cfg->mcode_date); | |
7947 | AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, | |
7948 | asc_dvc->cfg->mcode_version); | |
7949 | ||
7950 | /* | |
7951 | * Set the chip type to indicate the ASC38C1600. | |
7952 | */ | |
7953 | AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600); | |
7954 | ||
7955 | /* | |
7956 | * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. | |
7957 | * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current | |
7958 | * cable detection and then we are able to read C_DET[3:0]. | |
7959 | * | |
7960 | * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 | |
7961 | * Microcode Default Value' section below. | |
7962 | */ | |
7963 | scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1); | |
7964 | AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1, | |
7965 | scsi_cfg1 | DIS_TERM_DRV); | |
7966 | ||
7967 | /* | |
7968 | * If the PCI Configuration Command Register "Parity Error Response | |
7969 | * Control" Bit was clear (0), then set the microcode variable | |
7970 | * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode | |
7971 | * to ignore DMA parity errors. | |
7972 | */ | |
7973 | if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) { | |
7974 | AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); | |
7975 | word |= CONTROL_FLAG_IGNORE_PERR; | |
7976 | AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); | |
7977 | } | |
7978 | ||
7979 | /* | |
7980 | * If the BIOS control flag AIPP (Asynchronous Information | |
7981 | * Phase Protection) disable bit is not set, then set the firmware | |
7982 | * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable | |
7983 | * AIPP checking and encoding. | |
7984 | */ | |
7985 | if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) { | |
7986 | AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); | |
7987 | word |= CONTROL_FLAG_ENABLE_AIPP; | |
7988 | AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); | |
7989 | } | |
7990 | ||
7991 | /* | |
7992 | * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4], | |
7993 | * and START_CTL_TH [3:2]. | |
7994 | */ | |
7995 | AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0, | |
7996 | FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM); | |
7997 | ||
7998 | /* | |
7999 | * Microcode operating variables for WDTR, SDTR, and command tag | |
8000 | * queuing will be set in slave_configure() based on what a | |
8001 | * device reports it is capable of in Inquiry byte 7. | |
8002 | * | |
8003 | * If SCSI Bus Resets have been disabled, then directly set | |
8004 | * SDTR and WDTR from the EEPROM configuration. This will allow | |
8005 | * the BIOS and warm boot to work without a SCSI bus hang on | |
8006 | * the Inquiry caused by host and target mismatched DTR values. | |
8007 | * Without the SCSI Bus Reset, before an Inquiry a device can't | |
8008 | * be assumed to be in Asynchronous, Narrow mode. | |
8009 | */ | |
8010 | if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { | |
8011 | AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, | |
8012 | asc_dvc->wdtr_able); | |
8013 | AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, | |
8014 | asc_dvc->sdtr_able); | |
8015 | } | |
8016 | ||
8017 | /* | |
8018 | * Set microcode operating variables for DISC and SDTR_SPEED1, | |
8019 | * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM | |
8020 | * configuration values. | |
8021 | * | |
8022 | * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, | |
8023 | * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them | |
8024 | * without determining here whether the device supports SDTR. | |
8025 | */ | |
8026 | AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, | |
8027 | asc_dvc->cfg->disc_enable); | |
8028 | AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1); | |
8029 | AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2); | |
8030 | AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3); | |
8031 | AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4); | |
8032 | ||
8033 | /* | |
8034 | * Set SCSI_CFG0 Microcode Default Value. | |
8035 | * | |
8036 | * The microcode will set the SCSI_CFG0 register using this value | |
8037 | * after it is started below. | |
8038 | */ | |
8039 | AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0, | |
8040 | PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN | | |
8041 | asc_dvc->chip_scsi_id); | |
8042 | ||
8043 | /* | |
8044 | * Calculate SCSI_CFG1 Microcode Default Value. | |
8045 | * | |
8046 | * The microcode will set the SCSI_CFG1 register using this value | |
8047 | * after it is started below. | |
8048 | * | |
8049 | * Each ASC-38C1600 function has only two cable detect bits. | |
8050 | * The bus mode override bits are in IOPB_SOFT_OVER_WR. | |
8051 | */ | |
8052 | scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1); | |
8053 | ||
8054 | /* | |
8055 | * If the cable is reversed all of the SCSI_CTRL register signals | |
8056 | * will be set. Check for and return an error if this condition is | |
8057 | * found. | |
8058 | */ | |
8059 | if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) { | |
8060 | asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE; | |
8061 | return ADV_ERROR; | |
8062 | } | |
8063 | ||
8064 | /* | |
8065 | * Each ASC-38C1600 function has two connectors. Only an HVD device | |
8066 | * can not be connected to either connector. An LVD device or SE device | |
8067 | * may be connected to either connecor. If an SE device is connected, | |
8068 | * then at most Ultra speed (20 Mhz) can be used on both connectors. | |
8069 | * | |
8070 | * If an HVD device is attached, return an error. | |
8071 | */ | |
8072 | if (scsi_cfg1 & HVD) { | |
8073 | asc_dvc->err_code |= ASC_IERR_HVD_DEVICE; | |
8074 | return ADV_ERROR; | |
8075 | } | |
8076 | ||
8077 | /* | |
8078 | * Each function in the ASC-38C1600 uses only the SE cable detect and | |
8079 | * termination because there are two connectors for each function. Each | |
8080 | * function may use either LVD or SE mode. Corresponding the SE automatic | |
8081 | * termination control EEPROM bits are used for each function. Each | |
8082 | * function has its own EEPROM. If SE automatic control is enabled for | |
8083 | * the function, then set the termination value based on a table listed | |
8084 | * in a_condor.h. | |
8085 | * | |
8086 | * If manual termination is specified in the EEPROM for the function, | |
8087 | * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is | |
8088 | * ready to be 'ored' into SCSI_CFG1. | |
8089 | */ | |
8090 | if ((asc_dvc->cfg->termination & TERM_SE) == 0) { | |
8091 | struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc); | |
8092 | /* SE automatic termination control is enabled. */ | |
8093 | switch (scsi_cfg1 & C_DET_SE) { | |
8094 | /* TERM_SE_HI: on, TERM_SE_LO: on */ | |
8095 | case 0x1: | |
8096 | case 0x2: | |
8097 | case 0x3: | |
8098 | asc_dvc->cfg->termination |= TERM_SE; | |
8099 | break; | |
8100 | ||
8101 | case 0x0: | |
8102 | if (PCI_FUNC(pdev->devfn) == 0) { | |
8103 | /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */ | |
8104 | } else { | |
8105 | /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */ | |
8106 | asc_dvc->cfg->termination |= TERM_SE_HI; | |
8107 | } | |
8108 | break; | |
8109 | } | |
8110 | } | |
8111 | ||
8112 | /* | |
8113 | * Clear any set TERM_SE bits. | |
8114 | */ | |
8115 | scsi_cfg1 &= ~TERM_SE; | |
8116 | ||
8117 | /* | |
8118 | * Invert the TERM_SE bits and then set 'scsi_cfg1'. | |
8119 | */ | |
8120 | scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE); | |
8121 | ||
8122 | /* | |
8123 | * Clear Big Endian and Terminator Polarity bits and set possibly | |
8124 | * modified termination control bits in the Microcode SCSI_CFG1 | |
8125 | * Register Value. | |
8126 | * | |
8127 | * Big Endian bit is not used even on big endian machines. | |
8128 | */ | |
8129 | scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL); | |
8130 | ||
8131 | /* | |
8132 | * Set SCSI_CFG1 Microcode Default Value | |
8133 | * | |
8134 | * Set possibly modified termination control bits in the Microcode | |
8135 | * SCSI_CFG1 Register Value. | |
8136 | * | |
8137 | * The microcode will set the SCSI_CFG1 register using this value | |
8138 | * after it is started below. | |
8139 | */ | |
8140 | AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); | |
8141 | ||
8142 | /* | |
8143 | * Set MEM_CFG Microcode Default Value | |
8144 | * | |
8145 | * The microcode will set the MEM_CFG register using this value | |
8146 | * after it is started below. | |
8147 | * | |
8148 | * MEM_CFG may be accessed as a word or byte, but only bits 0-7 | |
8149 | * are defined. | |
8150 | * | |
8151 | * ASC-38C1600 has 32KB internal memory. | |
8152 | * | |
8153 | * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come | |
8154 | * out a special 16K Adv Library and Microcode version. After the issue | |
8155 | * resolved, we should turn back to the 32K support. Both a_condor.h and | |
8156 | * mcode.sas files also need to be updated. | |
8157 | * | |
8158 | * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG, | |
8159 | * BIOS_EN | RAM_SZ_32KB); | |
8160 | */ | |
8161 | AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG, | |
8162 | BIOS_EN | RAM_SZ_16KB); | |
8163 | ||
8164 | /* | |
8165 | * Set SEL_MASK Microcode Default Value | |
8166 | * | |
8167 | * The microcode will set the SEL_MASK register using this value | |
8168 | * after it is started below. | |
8169 | */ | |
8170 | AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK, | |
8171 | ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id)); | |
8172 | ||
8173 | AdvBuildCarrierFreelist(asc_dvc); | |
8174 | ||
8175 | /* | |
8176 | * Set-up the Host->RISC Initiator Command Queue (ICQ). | |
8177 | */ | |
8178 | if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) { | |
8179 | asc_dvc->err_code |= ASC_IERR_NO_CARRIER; | |
8180 | return ADV_ERROR; | |
8181 | } | |
8182 | asc_dvc->carr_freelist = (ADV_CARR_T *) | |
8183 | ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa)); | |
8184 | ||
8185 | /* | |
8186 | * The first command issued will be placed in the stopper carrier. | |
8187 | */ | |
8188 | asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER); | |
8189 | ||
8190 | /* | |
8191 | * Set RISC ICQ physical address start value. Initialize the | |
8192 | * COMMA register to the same value otherwise the RISC will | |
8193 | * prematurely detect a command is available. | |
8194 | */ | |
8195 | AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa); | |
8196 | AdvWriteDWordRegister(iop_base, IOPDW_COMMA, | |
8197 | le32_to_cpu(asc_dvc->icq_sp->carr_pa)); | |
8198 | ||
8199 | /* | |
8200 | * Set-up the RISC->Host Initiator Response Queue (IRQ). | |
8201 | */ | |
8202 | if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) { | |
8203 | asc_dvc->err_code |= ASC_IERR_NO_CARRIER; | |
8204 | return ADV_ERROR; | |
8205 | } | |
8206 | asc_dvc->carr_freelist = (ADV_CARR_T *) | |
8207 | ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa)); | |
8208 | ||
8209 | /* | |
8210 | * The first command completed by the RISC will be placed in | |
8211 | * the stopper. | |
8212 | * | |
8213 | * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is | |
8214 | * completed the RISC will set the ASC_RQ_STOPPER bit. | |
8215 | */ | |
8216 | asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER); | |
8217 | ||
8218 | /* | |
8219 | * Set RISC IRQ physical address start value. | |
8220 | */ | |
8221 | AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa); | |
8222 | asc_dvc->carr_pending_cnt = 0; | |
8223 | ||
8224 | AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES, | |
8225 | (ADV_INTR_ENABLE_HOST_INTR | | |
8226 | ADV_INTR_ENABLE_GLOBAL_INTR)); | |
8227 | AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word); | |
8228 | AdvWriteWordRegister(iop_base, IOPW_PC, word); | |
8229 | ||
8230 | /* finally, finally, gentlemen, start your engine */ | |
8231 | AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN); | |
8232 | ||
8233 | /* | |
8234 | * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus | |
8235 | * Resets should be performed. The RISC has to be running | |
8236 | * to issue a SCSI Bus Reset. | |
8237 | */ | |
8238 | if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) { | |
8239 | /* | |
8240 | * If the BIOS Signature is present in memory, restore the | |
8241 | * per TID microcode operating variables. | |
8242 | */ | |
8243 | if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == | |
8244 | 0x55AA) { | |
8245 | /* | |
8246 | * Restore per TID negotiated values. | |
8247 | */ | |
8248 | AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); | |
8249 | AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); | |
8250 | AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able); | |
8251 | AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, | |
8252 | tagqng_able); | |
8253 | for (tid = 0; tid <= ASC_MAX_TID; tid++) { | |
8254 | AdvWriteByteLram(iop_base, | |
8255 | ASC_MC_NUMBER_OF_MAX_CMD + tid, | |
8256 | max_cmd[tid]); | |
8257 | } | |
8258 | } else { | |
8259 | if (AdvResetSB(asc_dvc) != ADV_TRUE) { | |
8260 | warn_code = ASC_WARN_BUSRESET_ERROR; | |
8261 | } | |
8262 | } | |
8263 | } | |
8264 | ||
8265 | return warn_code; | |
8266 | } | |
8267 | ||
8268 | /* | |
8269 | * Reset chip and SCSI Bus. | |
8270 | * | |
8271 | * Return Value: | |
8272 | * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful. | |
8273 | * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure. | |
8274 | */ | |
8275 | static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc) | |
8276 | { | |
8277 | int status; | |
8278 | ushort wdtr_able, sdtr_able, tagqng_able; | |
8279 | ushort ppr_able = 0; | |
8280 | uchar tid, max_cmd[ADV_MAX_TID + 1]; | |
8281 | AdvPortAddr iop_base; | |
8282 | ushort bios_sig; | |
8283 | ||
8284 | iop_base = asc_dvc->iop_base; | |
8285 | ||
8286 | /* | |
8287 | * Save current per TID negotiated values. | |
8288 | */ | |
8289 | AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); | |
8290 | AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); | |
8291 | if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) { | |
8292 | AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able); | |
8293 | } | |
8294 | AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able); | |
8295 | for (tid = 0; tid <= ADV_MAX_TID; tid++) { | |
8296 | AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid, | |
8297 | max_cmd[tid]); | |
8298 | } | |
8299 | ||
8300 | /* | |
8301 | * Force the AdvInitAsc3550/38C0800Driver() function to | |
8302 | * perform a SCSI Bus Reset by clearing the BIOS signature word. | |
8303 | * The initialization functions assumes a SCSI Bus Reset is not | |
8304 | * needed if the BIOS signature word is present. | |
8305 | */ | |
8306 | AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig); | |
8307 | AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0); | |
8308 | ||
8309 | /* | |
8310 | * Stop chip and reset it. | |
8311 | */ | |
8312 | AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP); | |
8313 | AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET); | |
8314 | mdelay(100); | |
8315 | AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, | |
8316 | ADV_CTRL_REG_CMD_WR_IO_REG); | |
8317 | ||
8318 | /* | |
8319 | * Reset Adv Library error code, if any, and try | |
8320 | * re-initializing the chip. | |
8321 | */ | |
8322 | asc_dvc->err_code = 0; | |
8323 | if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) { | |
8324 | status = AdvInitAsc38C1600Driver(asc_dvc); | |
8325 | } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) { | |
8326 | status = AdvInitAsc38C0800Driver(asc_dvc); | |
8327 | } else { | |
8328 | status = AdvInitAsc3550Driver(asc_dvc); | |
8329 | } | |
8330 | ||
8331 | /* Translate initialization return value to status value. */ | |
8332 | if (status == 0) { | |
8333 | status = ADV_TRUE; | |
8334 | } else { | |
8335 | status = ADV_FALSE; | |
8336 | } | |
8337 | ||
8338 | /* | |
8339 | * Restore the BIOS signature word. | |
8340 | */ | |
8341 | AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig); | |
8342 | ||
8343 | /* | |
8344 | * Restore per TID negotiated values. | |
8345 | */ | |
8346 | AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); | |
8347 | AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); | |
8348 | if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) { | |
8349 | AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able); | |
8350 | } | |
8351 | AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able); | |
8352 | for (tid = 0; tid <= ADV_MAX_TID; tid++) { | |
8353 | AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid, | |
8354 | max_cmd[tid]); | |
8355 | } | |
8356 | ||
8357 | return status; | |
8358 | } | |
8359 | ||
8360 | /* | |
8361 | * adv_async_callback() - Adv Library asynchronous event callback function. | |
8362 | */ | |
8363 | static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code) | |
8364 | { | |
8365 | switch (code) { | |
8366 | case ADV_ASYNC_SCSI_BUS_RESET_DET: | |
8367 | /* | |
8368 | * The firmware detected a SCSI Bus reset. | |
8369 | */ | |
8370 | ASC_DBG(0, | |
8371 | "adv_async_callback: ADV_ASYNC_SCSI_BUS_RESET_DET\n"); | |
8372 | break; | |
8373 | ||
8374 | case ADV_ASYNC_RDMA_FAILURE: | |
8375 | /* | |
8376 | * Handle RDMA failure by resetting the SCSI Bus and | |
8377 | * possibly the chip if it is unresponsive. Log the error | |
8378 | * with a unique code. | |
8379 | */ | |
8380 | ASC_DBG(0, "adv_async_callback: ADV_ASYNC_RDMA_FAILURE\n"); | |
8381 | AdvResetChipAndSB(adv_dvc_varp); | |
8382 | break; | |
8383 | ||
8384 | case ADV_HOST_SCSI_BUS_RESET: | |
8385 | /* | |
8386 | * Host generated SCSI bus reset occurred. | |
8387 | */ | |
8388 | ASC_DBG(0, "adv_async_callback: ADV_HOST_SCSI_BUS_RESET\n"); | |
8389 | break; | |
8390 | ||
8391 | default: | |
8392 | ASC_DBG1(0, "DvcAsyncCallBack: unknown code 0x%x\n", code); | |
8393 | break; | |
8394 | } | |
8395 | } | |
8396 | ||
8397 | /* | |
8398 | * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR(). | |
8399 | * | |
8400 | * Callback function for the Wide SCSI Adv Library. | |
8401 | */ | |
8402 | static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp) | |
8403 | { | |
8404 | asc_board_t *boardp; | |
8405 | adv_req_t *reqp; | |
8406 | adv_sgblk_t *sgblkp; | |
8407 | struct scsi_cmnd *scp; | |
8408 | struct Scsi_Host *shost; | |
8409 | ADV_DCNT resid_cnt; | |
8410 | ||
8411 | ASC_DBG2(1, "adv_isr_callback: adv_dvc_varp 0x%lx, scsiqp 0x%lx\n", | |
8412 | (ulong)adv_dvc_varp, (ulong)scsiqp); | |
8413 | ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp); | |
8414 | ||
8415 | /* | |
8416 | * Get the adv_req_t structure for the command that has been | |
8417 | * completed. The adv_req_t structure actually contains the | |
8418 | * completed ADV_SCSI_REQ_Q structure. | |
8419 | */ | |
8420 | reqp = (adv_req_t *)ADV_U32_TO_VADDR(scsiqp->srb_ptr); | |
8421 | ASC_DBG1(1, "adv_isr_callback: reqp 0x%lx\n", (ulong)reqp); | |
8422 | if (reqp == NULL) { | |
8423 | ASC_PRINT("adv_isr_callback: reqp is NULL\n"); | |
8424 | return; | |
8425 | } | |
8426 | ||
8427 | /* | |
8428 | * Get the struct scsi_cmnd structure and Scsi_Host structure for the | |
8429 | * command that has been completed. | |
8430 | * | |
8431 | * Note: The adv_req_t request structure and adv_sgblk_t structure, | |
8432 | * if any, are dropped, because a board structure pointer can not be | |
8433 | * determined. | |
8434 | */ | |
8435 | scp = reqp->cmndp; | |
8436 | ASC_DBG1(1, "adv_isr_callback: scp 0x%lx\n", (ulong)scp); | |
8437 | if (scp == NULL) { | |
8438 | ASC_PRINT | |
8439 | ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n"); | |
8440 | return; | |
8441 | } | |
8442 | ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len); | |
8443 | ||
8444 | shost = scp->device->host; | |
8445 | ASC_STATS(shost, callback); | |
8446 | ASC_DBG1(1, "adv_isr_callback: shost 0x%lx\n", (ulong)shost); | |
8447 | ||
8448 | boardp = ASC_BOARDP(shost); | |
8449 | BUG_ON(adv_dvc_varp != &boardp->dvc_var.adv_dvc_var); | |
8450 | ||
8451 | /* | |
8452 | * 'done_status' contains the command's ending status. | |
8453 | */ | |
8454 | switch (scsiqp->done_status) { | |
8455 | case QD_NO_ERROR: | |
8456 | ASC_DBG(2, "adv_isr_callback: QD_NO_ERROR\n"); | |
8457 | scp->result = 0; | |
8458 | ||
8459 | /* | |
8460 | * Check for an underrun condition. | |
8461 | * | |
8462 | * If there was no error and an underrun condition, then | |
8463 | * then return the number of underrun bytes. | |
8464 | */ | |
8465 | resid_cnt = le32_to_cpu(scsiqp->data_cnt); | |
8466 | if (scp->request_bufflen != 0 && resid_cnt != 0 && | |
8467 | resid_cnt <= scp->request_bufflen) { | |
8468 | ASC_DBG1(1, | |
8469 | "adv_isr_callback: underrun condition %lu bytes\n", | |
8470 | (ulong)resid_cnt); | |
8471 | scp->resid = resid_cnt; | |
8472 | } | |
8473 | break; | |
8474 | ||
8475 | case QD_WITH_ERROR: | |
8476 | ASC_DBG(2, "adv_isr_callback: QD_WITH_ERROR\n"); | |
8477 | switch (scsiqp->host_status) { | |
8478 | case QHSTA_NO_ERROR: | |
8479 | if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) { | |
8480 | ASC_DBG(2, | |
8481 | "adv_isr_callback: SAM_STAT_CHECK_CONDITION\n"); | |
8482 | ASC_DBG_PRT_SENSE(2, scp->sense_buffer, | |
8483 | sizeof(scp->sense_buffer)); | |
8484 | /* | |
8485 | * Note: The 'status_byte()' macro used by | |
8486 | * target drivers defined in scsi.h shifts the | |
8487 | * status byte returned by host drivers right | |
8488 | * by 1 bit. This is why target drivers also | |
8489 | * use right shifted status byte definitions. | |
8490 | * For instance target drivers use | |
8491 | * CHECK_CONDITION, defined to 0x1, instead of | |
8492 | * the SCSI defined check condition value of | |
8493 | * 0x2. Host drivers are supposed to return | |
8494 | * the status byte as it is defined by SCSI. | |
8495 | */ | |
8496 | scp->result = DRIVER_BYTE(DRIVER_SENSE) | | |
8497 | STATUS_BYTE(scsiqp->scsi_status); | |
8498 | } else { | |
8499 | scp->result = STATUS_BYTE(scsiqp->scsi_status); | |
8500 | } | |
8501 | break; | |
8502 | ||
8503 | default: | |
8504 | /* Some other QHSTA error occurred. */ | |
8505 | ASC_DBG1(1, "adv_isr_callback: host_status 0x%x\n", | |
8506 | scsiqp->host_status); | |
8507 | scp->result = HOST_BYTE(DID_BAD_TARGET); | |
8508 | break; | |
8509 | } | |
8510 | break; | |
8511 | ||
8512 | case QD_ABORTED_BY_HOST: | |
8513 | ASC_DBG(1, "adv_isr_callback: QD_ABORTED_BY_HOST\n"); | |
8514 | scp->result = | |
8515 | HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status); | |
8516 | break; | |
8517 | ||
8518 | default: | |
8519 | ASC_DBG1(1, "adv_isr_callback: done_status 0x%x\n", | |
8520 | scsiqp->done_status); | |
8521 | scp->result = | |
8522 | HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status); | |
8523 | break; | |
8524 | } | |
8525 | ||
8526 | /* | |
8527 | * If the 'init_tidmask' bit isn't already set for the target and the | |
8528 | * current request finished normally, then set the bit for the target | |
8529 | * to indicate that a device is present. | |
8530 | */ | |
8531 | if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 && | |
8532 | scsiqp->done_status == QD_NO_ERROR && | |
8533 | scsiqp->host_status == QHSTA_NO_ERROR) { | |
8534 | boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id); | |
8535 | } | |
8536 | ||
8537 | asc_scsi_done(scp); | |
8538 | ||
8539 | /* | |
8540 | * Free all 'adv_sgblk_t' structures allocated for the request. | |
8541 | */ | |
8542 | while ((sgblkp = reqp->sgblkp) != NULL) { | |
8543 | /* Remove 'sgblkp' from the request list. */ | |
8544 | reqp->sgblkp = sgblkp->next_sgblkp; | |
8545 | ||
8546 | /* Add 'sgblkp' to the board free list. */ | |
8547 | sgblkp->next_sgblkp = boardp->adv_sgblkp; | |
8548 | boardp->adv_sgblkp = sgblkp; | |
8549 | } | |
8550 | ||
8551 | /* | |
8552 | * Free the adv_req_t structure used with the command by adding | |
8553 | * it back to the board free list. | |
8554 | */ | |
8555 | reqp->next_reqp = boardp->adv_reqp; | |
8556 | boardp->adv_reqp = reqp; | |
8557 | ||
8558 | ASC_DBG(1, "adv_isr_callback: done\n"); | |
8559 | ||
8560 | return; | |
8561 | } | |
8562 | ||
8563 | /* | |
8564 | * Adv Library Interrupt Service Routine | |
8565 | * | |
8566 | * This function is called by a driver's interrupt service routine. | |
8567 | * The function disables and re-enables interrupts. | |
8568 | * | |
8569 | * When a microcode idle command is completed, the ADV_DVC_VAR | |
8570 | * 'idle_cmd_done' field is set to ADV_TRUE. | |
8571 | * | |
8572 | * Note: AdvISR() can be called when interrupts are disabled or even | |
8573 | * when there is no hardware interrupt condition present. It will | |
8574 | * always check for completed idle commands and microcode requests. | |
8575 | * This is an important feature that shouldn't be changed because it | |
8576 | * allows commands to be completed from polling mode loops. | |
8577 | * | |
8578 | * Return: | |
8579 | * ADV_TRUE(1) - interrupt was pending | |
8580 | * ADV_FALSE(0) - no interrupt was pending | |
8581 | */ | |
8582 | static int AdvISR(ADV_DVC_VAR *asc_dvc) | |
8583 | { | |
8584 | AdvPortAddr iop_base; | |
8585 | uchar int_stat; | |
8586 | ushort target_bit; | |
8587 | ADV_CARR_T *free_carrp; | |
8588 | ADV_VADDR irq_next_vpa; | |
8589 | ADV_SCSI_REQ_Q *scsiq; | |
8590 | ||
8591 | iop_base = asc_dvc->iop_base; | |
8592 | ||
8593 | /* Reading the register clears the interrupt. */ | |
8594 | int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG); | |
8595 | ||
8596 | if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB | | |
8597 | ADV_INTR_STATUS_INTRC)) == 0) { | |
8598 | return ADV_FALSE; | |
8599 | } | |
8600 | ||
8601 | /* | |
8602 | * Notify the driver of an asynchronous microcode condition by | |
8603 | * calling the adv_async_callback function. The function | |
8604 | * is passed the microcode ASC_MC_INTRB_CODE byte value. | |
8605 | */ | |
8606 | if (int_stat & ADV_INTR_STATUS_INTRB) { | |
8607 | uchar intrb_code; | |
8608 | ||
8609 | AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code); | |
8610 | ||
8611 | if (asc_dvc->chip_type == ADV_CHIP_ASC3550 || | |
8612 | asc_dvc->chip_type == ADV_CHIP_ASC38C0800) { | |
8613 | if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE && | |
8614 | asc_dvc->carr_pending_cnt != 0) { | |
8615 | AdvWriteByteRegister(iop_base, IOPB_TICKLE, | |
8616 | ADV_TICKLE_A); | |
8617 | if (asc_dvc->chip_type == ADV_CHIP_ASC3550) { | |
8618 | AdvWriteByteRegister(iop_base, | |
8619 | IOPB_TICKLE, | |
8620 | ADV_TICKLE_NOP); | |
8621 | } | |
8622 | } | |
8623 | } | |
8624 | ||
8625 | adv_async_callback(asc_dvc, intrb_code); | |
8626 | } | |
8627 | ||
8628 | /* | |
8629 | * Check if the IRQ stopper carrier contains a completed request. | |
8630 | */ | |
8631 | while (((irq_next_vpa = | |
8632 | le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0) { | |
8633 | /* | |
8634 | * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure. | |
8635 | * The RISC will have set 'areq_vpa' to a virtual address. | |
8636 | * | |
8637 | * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr | |
8638 | * field to the carrier ADV_CARR_T.areq_vpa field. The conversion | |
8639 | * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr' | |
8640 | * in AdvExeScsiQueue(). | |
8641 | */ | |
8642 | scsiq = (ADV_SCSI_REQ_Q *) | |
8643 | ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->areq_vpa)); | |
8644 | ||
8645 | /* | |
8646 | * Request finished with good status and the queue was not | |
8647 | * DMAed to host memory by the firmware. Set all status fields | |
8648 | * to indicate good status. | |
8649 | */ | |
8650 | if ((irq_next_vpa & ASC_RQ_GOOD) != 0) { | |
8651 | scsiq->done_status = QD_NO_ERROR; | |
8652 | scsiq->host_status = scsiq->scsi_status = 0; | |
8653 | scsiq->data_cnt = 0L; | |
8654 | } | |
8655 | ||
8656 | /* | |
8657 | * Advance the stopper pointer to the next carrier | |
8658 | * ignoring the lower four bits. Free the previous | |
8659 | * stopper carrier. | |
8660 | */ | |
8661 | free_carrp = asc_dvc->irq_sp; | |
8662 | asc_dvc->irq_sp = (ADV_CARR_T *) | |
8663 | ADV_U32_TO_VADDR(ASC_GET_CARRP(irq_next_vpa)); | |
8664 | ||
8665 | free_carrp->next_vpa = | |
8666 | cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist)); | |
8667 | asc_dvc->carr_freelist = free_carrp; | |
8668 | asc_dvc->carr_pending_cnt--; | |
8669 | ||
8670 | target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id); | |
8671 | ||
8672 | /* | |
8673 | * Clear request microcode control flag. | |
8674 | */ | |
8675 | scsiq->cntl = 0; | |
8676 | ||
8677 | /* | |
8678 | * Notify the driver of the completed request by passing | |
8679 | * the ADV_SCSI_REQ_Q pointer to its callback function. | |
8680 | */ | |
8681 | scsiq->a_flag |= ADV_SCSIQ_DONE; | |
8682 | adv_isr_callback(asc_dvc, scsiq); | |
8683 | /* | |
8684 | * Note: After the driver callback function is called, 'scsiq' | |
8685 | * can no longer be referenced. | |
8686 | * | |
8687 | * Fall through and continue processing other completed | |
8688 | * requests... | |
8689 | */ | |
8690 | } | |
8691 | return ADV_TRUE; | |
8692 | } | |
8693 | ||
8694 | static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code) | |
8695 | { | |
8696 | if (asc_dvc->err_code == 0) { | |
8697 | asc_dvc->err_code = err_code; | |
8698 | AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W, | |
8699 | err_code); | |
8700 | } | |
8701 | return err_code; | |
8702 | } | |
8703 | ||
8704 | static void AscAckInterrupt(PortAddr iop_base) | |
8705 | { | |
8706 | uchar host_flag; | |
8707 | uchar risc_flag; | |
8708 | ushort loop; | |
8709 | ||
8710 | loop = 0; | |
8711 | do { | |
8712 | risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B); | |
8713 | if (loop++ > 0x7FFF) { | |
8714 | break; | |
8715 | } | |
8716 | } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0); | |
8717 | host_flag = | |
8718 | AscReadLramByte(iop_base, | |
8719 | ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT); | |
8720 | AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, | |
8721 | (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT)); | |
8722 | AscSetChipStatus(iop_base, CIW_INT_ACK); | |
8723 | loop = 0; | |
8724 | while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) { | |
8725 | AscSetChipStatus(iop_base, CIW_INT_ACK); | |
8726 | if (loop++ > 3) { | |
8727 | break; | |
8728 | } | |
8729 | } | |
8730 | AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag); | |
8731 | return; | |
8732 | } | |
8733 | ||
8734 | static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time) | |
8735 | { | |
8736 | uchar *period_table; | |
8737 | int max_index; | |
8738 | int min_index; | |
8739 | int i; | |
8740 | ||
8741 | period_table = asc_dvc->sdtr_period_tbl; | |
8742 | max_index = (int)asc_dvc->max_sdtr_index; | |
8743 | min_index = (int)asc_dvc->host_init_sdtr_index; | |
8744 | if ((syn_time <= period_table[max_index])) { | |
8745 | for (i = min_index; i < (max_index - 1); i++) { | |
8746 | if (syn_time <= period_table[i]) { | |
8747 | return (uchar)i; | |
8748 | } | |
8749 | } | |
8750 | return (uchar)max_index; | |
8751 | } else { | |
8752 | return (uchar)(max_index + 1); | |
8753 | } | |
8754 | } | |
8755 | ||
8756 | static uchar | |
8757 | AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset) | |
8758 | { | |
8759 | EXT_MSG sdtr_buf; | |
8760 | uchar sdtr_period_index; | |
8761 | PortAddr iop_base; | |
8762 | ||
8763 | iop_base = asc_dvc->iop_base; | |
8764 | sdtr_buf.msg_type = EXTENDED_MESSAGE; | |
8765 | sdtr_buf.msg_len = MS_SDTR_LEN; | |
8766 | sdtr_buf.msg_req = EXTENDED_SDTR; | |
8767 | sdtr_buf.xfer_period = sdtr_period; | |
8768 | sdtr_offset &= ASC_SYN_MAX_OFFSET; | |
8769 | sdtr_buf.req_ack_offset = sdtr_offset; | |
8770 | sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period); | |
8771 | if (sdtr_period_index <= asc_dvc->max_sdtr_index) { | |
8772 | AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG, | |
8773 | (uchar *)&sdtr_buf, | |
8774 | sizeof(EXT_MSG) >> 1); | |
8775 | return ((sdtr_period_index << 4) | sdtr_offset); | |
8776 | } else { | |
8777 | sdtr_buf.req_ack_offset = 0; | |
8778 | AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG, | |
8779 | (uchar *)&sdtr_buf, | |
8780 | sizeof(EXT_MSG) >> 1); | |
8781 | return 0; | |
8782 | } | |
8783 | } | |
8784 | ||
8785 | static uchar | |
8786 | AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset) | |
8787 | { | |
8788 | uchar byte; | |
8789 | uchar sdtr_period_ix; | |
8790 | ||
8791 | sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period); | |
8792 | if (sdtr_period_ix > asc_dvc->max_sdtr_index) { | |
8793 | return 0xFF; | |
8794 | } | |
8795 | byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET); | |
8796 | return byte; | |
8797 | } | |
8798 | ||
8799 | static int AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data) | |
8800 | { | |
8801 | ASC_SCSI_BIT_ID_TYPE org_id; | |
8802 | int i; | |
8803 | int sta = TRUE; | |
8804 | ||
8805 | AscSetBank(iop_base, 1); | |
8806 | org_id = AscReadChipDvcID(iop_base); | |
8807 | for (i = 0; i <= ASC_MAX_TID; i++) { | |
8808 | if (org_id == (0x01 << i)) | |
8809 | break; | |
8810 | } | |
8811 | org_id = (ASC_SCSI_BIT_ID_TYPE) i; | |
8812 | AscWriteChipDvcID(iop_base, id); | |
8813 | if (AscReadChipDvcID(iop_base) == (0x01 << id)) { | |
8814 | AscSetBank(iop_base, 0); | |
8815 | AscSetChipSyn(iop_base, sdtr_data); | |
8816 | if (AscGetChipSyn(iop_base) != sdtr_data) { | |
8817 | sta = FALSE; | |
8818 | } | |
8819 | } else { | |
8820 | sta = FALSE; | |
8821 | } | |
8822 | AscSetBank(iop_base, 1); | |
8823 | AscWriteChipDvcID(iop_base, org_id); | |
8824 | AscSetBank(iop_base, 0); | |
8825 | return (sta); | |
8826 | } | |
8827 | ||
8828 | static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no) | |
8829 | { | |
8830 | AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data); | |
8831 | AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data); | |
8832 | } | |
8833 | ||
8834 | static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc) | |
8835 | { | |
8836 | EXT_MSG ext_msg; | |
8837 | EXT_MSG out_msg; | |
8838 | ushort halt_q_addr; | |
8839 | int sdtr_accept; | |
8840 | ushort int_halt_code; | |
8841 | ASC_SCSI_BIT_ID_TYPE scsi_busy; | |
8842 | ASC_SCSI_BIT_ID_TYPE target_id; | |
8843 | PortAddr iop_base; | |
8844 | uchar tag_code; | |
8845 | uchar q_status; | |
8846 | uchar halt_qp; | |
8847 | uchar sdtr_data; | |
8848 | uchar target_ix; | |
8849 | uchar q_cntl, tid_no; | |
8850 | uchar cur_dvc_qng; | |
8851 | uchar asyn_sdtr; | |
8852 | uchar scsi_status; | |
8853 | asc_board_t *boardp; | |
8854 | ||
8855 | BUG_ON(!asc_dvc->drv_ptr); | |
8856 | boardp = asc_dvc->drv_ptr; | |
8857 | ||
8858 | iop_base = asc_dvc->iop_base; | |
8859 | int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W); | |
8860 | ||
8861 | halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B); | |
8862 | halt_q_addr = ASC_QNO_TO_QADDR(halt_qp); | |
8863 | target_ix = AscReadLramByte(iop_base, | |
8864 | (ushort)(halt_q_addr + | |
8865 | (ushort)ASC_SCSIQ_B_TARGET_IX)); | |
8866 | q_cntl = AscReadLramByte(iop_base, | |
8867 | (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL)); | |
8868 | tid_no = ASC_TIX_TO_TID(target_ix); | |
8869 | target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no); | |
8870 | if (asc_dvc->pci_fix_asyn_xfer & target_id) { | |
8871 | asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB; | |
8872 | } else { | |
8873 | asyn_sdtr = 0; | |
8874 | } | |
8875 | if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) { | |
8876 | if (asc_dvc->pci_fix_asyn_xfer & target_id) { | |
8877 | AscSetChipSDTR(iop_base, 0, tid_no); | |
8878 | boardp->sdtr_data[tid_no] = 0; | |
8879 | } | |
8880 | AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); | |
8881 | return (0); | |
8882 | } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) { | |
8883 | if (asc_dvc->pci_fix_asyn_xfer & target_id) { | |
8884 | AscSetChipSDTR(iop_base, asyn_sdtr, tid_no); | |
8885 | boardp->sdtr_data[tid_no] = asyn_sdtr; | |
8886 | } | |
8887 | AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); | |
8888 | return (0); | |
8889 | } else if (int_halt_code == ASC_HALT_EXTMSG_IN) { | |
8890 | AscMemWordCopyPtrFromLram(iop_base, | |
8891 | ASCV_MSGIN_BEG, | |
8892 | (uchar *)&ext_msg, | |
8893 | sizeof(EXT_MSG) >> 1); | |
8894 | ||
8895 | if (ext_msg.msg_type == EXTENDED_MESSAGE && | |
8896 | ext_msg.msg_req == EXTENDED_SDTR && | |
8897 | ext_msg.msg_len == MS_SDTR_LEN) { | |
8898 | sdtr_accept = TRUE; | |
8899 | if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) { | |
8900 | ||
8901 | sdtr_accept = FALSE; | |
8902 | ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET; | |
8903 | } | |
8904 | if ((ext_msg.xfer_period < | |
8905 | asc_dvc->sdtr_period_tbl[asc_dvc-> | |
8906 | host_init_sdtr_index]) | |
8907 | || (ext_msg.xfer_period > | |
8908 | asc_dvc->sdtr_period_tbl[asc_dvc-> | |
8909 | max_sdtr_index])) { | |
8910 | sdtr_accept = FALSE; | |
8911 | ext_msg.xfer_period = | |
8912 | asc_dvc->sdtr_period_tbl[asc_dvc-> | |
8913 | host_init_sdtr_index]; | |
8914 | } | |
8915 | if (sdtr_accept) { | |
8916 | sdtr_data = | |
8917 | AscCalSDTRData(asc_dvc, ext_msg.xfer_period, | |
8918 | ext_msg.req_ack_offset); | |
8919 | if ((sdtr_data == 0xFF)) { | |
8920 | ||
8921 | q_cntl |= QC_MSG_OUT; | |
8922 | asc_dvc->init_sdtr &= ~target_id; | |
8923 | asc_dvc->sdtr_done &= ~target_id; | |
8924 | AscSetChipSDTR(iop_base, asyn_sdtr, | |
8925 | tid_no); | |
8926 | boardp->sdtr_data[tid_no] = asyn_sdtr; | |
8927 | } | |
8928 | } | |
8929 | if (ext_msg.req_ack_offset == 0) { | |
8930 | ||
8931 | q_cntl &= ~QC_MSG_OUT; | |
8932 | asc_dvc->init_sdtr &= ~target_id; | |
8933 | asc_dvc->sdtr_done &= ~target_id; | |
8934 | AscSetChipSDTR(iop_base, asyn_sdtr, tid_no); | |
8935 | } else { | |
8936 | if (sdtr_accept && (q_cntl & QC_MSG_OUT)) { | |
8937 | ||
8938 | q_cntl &= ~QC_MSG_OUT; | |
8939 | asc_dvc->sdtr_done |= target_id; | |
8940 | asc_dvc->init_sdtr |= target_id; | |
8941 | asc_dvc->pci_fix_asyn_xfer &= | |
8942 | ~target_id; | |
8943 | sdtr_data = | |
8944 | AscCalSDTRData(asc_dvc, | |
8945 | ext_msg.xfer_period, | |
8946 | ext_msg. | |
8947 | req_ack_offset); | |
8948 | AscSetChipSDTR(iop_base, sdtr_data, | |
8949 | tid_no); | |
8950 | boardp->sdtr_data[tid_no] = sdtr_data; | |
8951 | } else { | |
8952 | ||
8953 | q_cntl |= QC_MSG_OUT; | |
8954 | AscMsgOutSDTR(asc_dvc, | |
8955 | ext_msg.xfer_period, | |
8956 | ext_msg.req_ack_offset); | |
8957 | asc_dvc->pci_fix_asyn_xfer &= | |
8958 | ~target_id; | |
8959 | sdtr_data = | |
8960 | AscCalSDTRData(asc_dvc, | |
8961 | ext_msg.xfer_period, | |
8962 | ext_msg. | |
8963 | req_ack_offset); | |
8964 | AscSetChipSDTR(iop_base, sdtr_data, | |
8965 | tid_no); | |
8966 | boardp->sdtr_data[tid_no] = sdtr_data; | |
8967 | asc_dvc->sdtr_done |= target_id; | |
8968 | asc_dvc->init_sdtr |= target_id; | |
8969 | } | |
8970 | } | |
8971 | ||
8972 | AscWriteLramByte(iop_base, | |
8973 | (ushort)(halt_q_addr + | |
8974 | (ushort)ASC_SCSIQ_B_CNTL), | |
8975 | q_cntl); | |
8976 | AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); | |
8977 | return (0); | |
8978 | } else if (ext_msg.msg_type == EXTENDED_MESSAGE && | |
8979 | ext_msg.msg_req == EXTENDED_WDTR && | |
8980 | ext_msg.msg_len == MS_WDTR_LEN) { | |
8981 | ||
8982 | ext_msg.wdtr_width = 0; | |
8983 | AscMemWordCopyPtrToLram(iop_base, | |
8984 | ASCV_MSGOUT_BEG, | |
8985 | (uchar *)&ext_msg, | |
8986 | sizeof(EXT_MSG) >> 1); | |
8987 | q_cntl |= QC_MSG_OUT; | |
8988 | AscWriteLramByte(iop_base, | |
8989 | (ushort)(halt_q_addr + | |
8990 | (ushort)ASC_SCSIQ_B_CNTL), | |
8991 | q_cntl); | |
8992 | AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); | |
8993 | return (0); | |
8994 | } else { | |
8995 | ||
8996 | ext_msg.msg_type = MESSAGE_REJECT; | |
8997 | AscMemWordCopyPtrToLram(iop_base, | |
8998 | ASCV_MSGOUT_BEG, | |
8999 | (uchar *)&ext_msg, | |
9000 | sizeof(EXT_MSG) >> 1); | |
9001 | q_cntl |= QC_MSG_OUT; | |
9002 | AscWriteLramByte(iop_base, | |
9003 | (ushort)(halt_q_addr + | |
9004 | (ushort)ASC_SCSIQ_B_CNTL), | |
9005 | q_cntl); | |
9006 | AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); | |
9007 | return (0); | |
9008 | } | |
9009 | } else if (int_halt_code == ASC_HALT_CHK_CONDITION) { | |
9010 | ||
9011 | q_cntl |= QC_REQ_SENSE; | |
9012 | ||
9013 | if ((asc_dvc->init_sdtr & target_id) != 0) { | |
9014 | ||
9015 | asc_dvc->sdtr_done &= ~target_id; | |
9016 | ||
9017 | sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no); | |
9018 | q_cntl |= QC_MSG_OUT; | |
9019 | AscMsgOutSDTR(asc_dvc, | |
9020 | asc_dvc-> | |
9021 | sdtr_period_tbl[(sdtr_data >> 4) & | |
9022 | (uchar)(asc_dvc-> | |
9023 | max_sdtr_index - | |
9024 | 1)], | |
9025 | (uchar)(sdtr_data & (uchar) | |
9026 | ASC_SYN_MAX_OFFSET)); | |
9027 | } | |
9028 | ||
9029 | AscWriteLramByte(iop_base, | |
9030 | (ushort)(halt_q_addr + | |
9031 | (ushort)ASC_SCSIQ_B_CNTL), q_cntl); | |
9032 | ||
9033 | tag_code = AscReadLramByte(iop_base, | |
9034 | (ushort)(halt_q_addr + (ushort) | |
9035 | ASC_SCSIQ_B_TAG_CODE)); | |
9036 | tag_code &= 0xDC; | |
9037 | if ((asc_dvc->pci_fix_asyn_xfer & target_id) | |
9038 | && !(asc_dvc->pci_fix_asyn_xfer_always & target_id) | |
9039 | ) { | |
9040 | ||
9041 | tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT | |
9042 | | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX); | |
9043 | ||
9044 | } | |
9045 | AscWriteLramByte(iop_base, | |
9046 | (ushort)(halt_q_addr + | |
9047 | (ushort)ASC_SCSIQ_B_TAG_CODE), | |
9048 | tag_code); | |
9049 | ||
9050 | q_status = AscReadLramByte(iop_base, | |
9051 | (ushort)(halt_q_addr + (ushort) | |
9052 | ASC_SCSIQ_B_STATUS)); | |
9053 | q_status |= (QS_READY | QS_BUSY); | |
9054 | AscWriteLramByte(iop_base, | |
9055 | (ushort)(halt_q_addr + | |
9056 | (ushort)ASC_SCSIQ_B_STATUS), | |
9057 | q_status); | |
9058 | ||
9059 | scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B); | |
9060 | scsi_busy &= ~target_id; | |
9061 | AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy); | |
9062 | ||
9063 | AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); | |
9064 | return (0); | |
9065 | } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) { | |
9066 | ||
9067 | AscMemWordCopyPtrFromLram(iop_base, | |
9068 | ASCV_MSGOUT_BEG, | |
9069 | (uchar *)&out_msg, | |
9070 | sizeof(EXT_MSG) >> 1); | |
9071 | ||
9072 | if ((out_msg.msg_type == EXTENDED_MESSAGE) && | |
9073 | (out_msg.msg_len == MS_SDTR_LEN) && | |
9074 | (out_msg.msg_req == EXTENDED_SDTR)) { | |
9075 | ||
9076 | asc_dvc->init_sdtr &= ~target_id; | |
9077 | asc_dvc->sdtr_done &= ~target_id; | |
9078 | AscSetChipSDTR(iop_base, asyn_sdtr, tid_no); | |
9079 | boardp->sdtr_data[tid_no] = asyn_sdtr; | |
9080 | } | |
9081 | q_cntl &= ~QC_MSG_OUT; | |
9082 | AscWriteLramByte(iop_base, | |
9083 | (ushort)(halt_q_addr + | |
9084 | (ushort)ASC_SCSIQ_B_CNTL), q_cntl); | |
9085 | AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); | |
9086 | return (0); | |
9087 | } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) { | |
9088 | ||
9089 | scsi_status = AscReadLramByte(iop_base, | |
9090 | (ushort)((ushort)halt_q_addr + | |
9091 | (ushort) | |
9092 | ASC_SCSIQ_SCSI_STATUS)); | |
9093 | cur_dvc_qng = | |
9094 | AscReadLramByte(iop_base, | |
9095 | (ushort)((ushort)ASC_QADR_BEG + | |
9096 | (ushort)target_ix)); | |
9097 | if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) { | |
9098 | ||
9099 | scsi_busy = AscReadLramByte(iop_base, | |
9100 | (ushort)ASCV_SCSIBUSY_B); | |
9101 | scsi_busy |= target_id; | |
9102 | AscWriteLramByte(iop_base, | |
9103 | (ushort)ASCV_SCSIBUSY_B, scsi_busy); | |
9104 | asc_dvc->queue_full_or_busy |= target_id; | |
9105 | ||
9106 | if (scsi_status == SAM_STAT_TASK_SET_FULL) { | |
9107 | if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) { | |
9108 | cur_dvc_qng -= 1; | |
9109 | asc_dvc->max_dvc_qng[tid_no] = | |
9110 | cur_dvc_qng; | |
9111 | ||
9112 | AscWriteLramByte(iop_base, | |
9113 | (ushort)((ushort) | |
9114 | ASCV_MAX_DVC_QNG_BEG | |
9115 | + (ushort) | |
9116 | tid_no), | |
9117 | cur_dvc_qng); | |
9118 | ||
9119 | /* | |
9120 | * Set the device queue depth to the | |
9121 | * number of active requests when the | |
9122 | * QUEUE FULL condition was encountered. | |
9123 | */ | |
9124 | boardp->queue_full |= target_id; | |
9125 | boardp->queue_full_cnt[tid_no] = | |
9126 | cur_dvc_qng; | |
9127 | } | |
9128 | } | |
9129 | } | |
9130 | AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); | |
9131 | return (0); | |
9132 | } | |
9133 | #if CC_VERY_LONG_SG_LIST | |
9134 | else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC) { | |
9135 | uchar q_no; | |
9136 | ushort q_addr; | |
9137 | uchar sg_wk_q_no; | |
9138 | uchar first_sg_wk_q_no; | |
9139 | ASC_SCSI_Q *scsiq; /* Ptr to driver request. */ | |
9140 | ASC_SG_HEAD *sg_head; /* Ptr to driver SG request. */ | |
9141 | ASC_SG_LIST_Q scsi_sg_q; /* Structure written to queue. */ | |
9142 | ushort sg_list_dwords; | |
9143 | ushort sg_entry_cnt; | |
9144 | uchar next_qp; | |
9145 | int i; | |
9146 | ||
9147 | q_no = AscReadLramByte(iop_base, (ushort)ASCV_REQ_SG_LIST_QP); | |
9148 | if (q_no == ASC_QLINK_END) | |
9149 | return 0; | |
9150 | ||
9151 | q_addr = ASC_QNO_TO_QADDR(q_no); | |
9152 | ||
9153 | /* | |
9154 | * Convert the request's SRB pointer to a host ASC_SCSI_REQ | |
9155 | * structure pointer using a macro provided by the driver. | |
9156 | * The ASC_SCSI_REQ pointer provides a pointer to the | |
9157 | * host ASC_SG_HEAD structure. | |
9158 | */ | |
9159 | /* Read request's SRB pointer. */ | |
9160 | scsiq = (ASC_SCSI_Q *) | |
9161 | ASC_SRB2SCSIQ(ASC_U32_TO_VADDR(AscReadLramDWord(iop_base, | |
9162 | (ushort) | |
9163 | (q_addr + | |
9164 | ASC_SCSIQ_D_SRBPTR)))); | |
9165 | ||
9166 | /* | |
9167 | * Get request's first and working SG queue. | |
9168 | */ | |
9169 | sg_wk_q_no = AscReadLramByte(iop_base, | |
9170 | (ushort)(q_addr + | |
9171 | ASC_SCSIQ_B_SG_WK_QP)); | |
9172 | ||
9173 | first_sg_wk_q_no = AscReadLramByte(iop_base, | |
9174 | (ushort)(q_addr + | |
9175 | ASC_SCSIQ_B_FIRST_SG_WK_QP)); | |
9176 | ||
9177 | /* | |
9178 | * Reset request's working SG queue back to the | |
9179 | * first SG queue. | |
9180 | */ | |
9181 | AscWriteLramByte(iop_base, | |
9182 | (ushort)(q_addr + | |
9183 | (ushort)ASC_SCSIQ_B_SG_WK_QP), | |
9184 | first_sg_wk_q_no); | |
9185 | ||
9186 | sg_head = scsiq->sg_head; | |
9187 | ||
9188 | /* | |
9189 | * Set sg_entry_cnt to the number of SG elements | |
9190 | * that will be completed on this interrupt. | |
9191 | * | |
9192 | * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1 | |
9193 | * SG elements. The data_cnt and data_addr fields which | |
9194 | * add 1 to the SG element capacity are not used when | |
9195 | * restarting SG handling after a halt. | |
9196 | */ | |
9197 | if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1)) { | |
9198 | sg_entry_cnt = ASC_MAX_SG_LIST - 1; | |
9199 | ||
9200 | /* | |
9201 | * Keep track of remaining number of SG elements that | |
9202 | * will need to be handled on the next interrupt. | |
9203 | */ | |
9204 | scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1); | |
9205 | } else { | |
9206 | sg_entry_cnt = scsiq->remain_sg_entry_cnt; | |
9207 | scsiq->remain_sg_entry_cnt = 0; | |
9208 | } | |
9209 | ||
9210 | /* | |
9211 | * Copy SG elements into the list of allocated SG queues. | |
9212 | * | |
9213 | * Last index completed is saved in scsiq->next_sg_index. | |
9214 | */ | |
9215 | next_qp = first_sg_wk_q_no; | |
9216 | q_addr = ASC_QNO_TO_QADDR(next_qp); | |
9217 | scsi_sg_q.sg_head_qp = q_no; | |
9218 | scsi_sg_q.cntl = QCSG_SG_XFER_LIST; | |
9219 | for (i = 0; i < sg_head->queue_cnt; i++) { | |
9220 | scsi_sg_q.seq_no = i + 1; | |
9221 | if (sg_entry_cnt > ASC_SG_LIST_PER_Q) { | |
9222 | sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2); | |
9223 | sg_entry_cnt -= ASC_SG_LIST_PER_Q; | |
9224 | /* | |
9225 | * After very first SG queue RISC FW uses next | |
9226 | * SG queue first element then checks sg_list_cnt | |
9227 | * against zero and then decrements, so set | |
9228 | * sg_list_cnt 1 less than number of SG elements | |
9229 | * in each SG queue. | |
9230 | */ | |
9231 | scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1; | |
9232 | scsi_sg_q.sg_cur_list_cnt = | |
9233 | ASC_SG_LIST_PER_Q - 1; | |
9234 | } else { | |
9235 | /* | |
9236 | * This is the last SG queue in the list of | |
9237 | * allocated SG queues. If there are more | |
9238 | * SG elements than will fit in the allocated | |
9239 | * queues, then set the QCSG_SG_XFER_MORE flag. | |
9240 | */ | |
9241 | if (scsiq->remain_sg_entry_cnt != 0) { | |
9242 | scsi_sg_q.cntl |= QCSG_SG_XFER_MORE; | |
9243 | } else { | |
9244 | scsi_sg_q.cntl |= QCSG_SG_XFER_END; | |
9245 | } | |
9246 | /* equals sg_entry_cnt * 2 */ | |
9247 | sg_list_dwords = sg_entry_cnt << 1; | |
9248 | scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1; | |
9249 | scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1; | |
9250 | sg_entry_cnt = 0; | |
9251 | } | |
9252 | ||
9253 | scsi_sg_q.q_no = next_qp; | |
9254 | AscMemWordCopyPtrToLram(iop_base, | |
9255 | q_addr + ASC_SCSIQ_SGHD_CPY_BEG, | |
9256 | (uchar *)&scsi_sg_q, | |
9257 | sizeof(ASC_SG_LIST_Q) >> 1); | |
9258 | ||
9259 | AscMemDWordCopyPtrToLram(iop_base, | |
9260 | q_addr + ASC_SGQ_LIST_BEG, | |
9261 | (uchar *)&sg_head-> | |
9262 | sg_list[scsiq->next_sg_index], | |
9263 | sg_list_dwords); | |
9264 | ||
9265 | scsiq->next_sg_index += ASC_SG_LIST_PER_Q; | |
9266 | ||
9267 | /* | |
9268 | * If the just completed SG queue contained the | |
9269 | * last SG element, then no more SG queues need | |
9270 | * to be written. | |
9271 | */ | |
9272 | if (scsi_sg_q.cntl & QCSG_SG_XFER_END) { | |
9273 | break; | |
9274 | } | |
9275 | ||
9276 | next_qp = AscReadLramByte(iop_base, | |
9277 | (ushort)(q_addr + | |
9278 | ASC_SCSIQ_B_FWD)); | |
9279 | q_addr = ASC_QNO_TO_QADDR(next_qp); | |
9280 | } | |
9281 | ||
9282 | /* | |
9283 | * Clear the halt condition so the RISC will be restarted | |
9284 | * after the return. | |
9285 | */ | |
9286 | AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); | |
9287 | return (0); | |
9288 | } | |
9289 | #endif /* CC_VERY_LONG_SG_LIST */ | |
9290 | return (0); | |
9291 | } | |
1da177e4 | 9292 | |
1da177e4 | 9293 | /* |
51219358 MW |
9294 | * void |
9295 | * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words) | |
1da177e4 | 9296 | * |
51219358 MW |
9297 | * Calling/Exit State: |
9298 | * none | |
1da177e4 | 9299 | * |
51219358 MW |
9300 | * Description: |
9301 | * Input an ASC_QDONE_INFO structure from the chip | |
1da177e4 | 9302 | */ |
51219358 MW |
9303 | static void |
9304 | DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words) | |
9305 | { | |
9306 | int i; | |
9307 | ushort word; | |
9308 | ||
9309 | AscSetChipLramAddr(iop_base, s_addr); | |
9310 | for (i = 0; i < 2 * words; i += 2) { | |
9311 | if (i == 10) { | |
9312 | continue; | |
9313 | } | |
9314 | word = inpw(iop_base + IOP_RAM_DATA); | |
9315 | inbuf[i] = word & 0xff; | |
9316 | inbuf[i + 1] = (word >> 8) & 0xff; | |
9317 | } | |
9318 | ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words); | |
9319 | } | |
9320 | ||
9321 | static uchar | |
9322 | _AscCopyLramScsiDoneQ(PortAddr iop_base, | |
9323 | ushort q_addr, | |
9324 | ASC_QDONE_INFO *scsiq, ASC_DCNT max_dma_count) | |
9325 | { | |
9326 | ushort _val; | |
9327 | uchar sg_queue_cnt; | |
9328 | ||
9329 | DvcGetQinfo(iop_base, | |
9330 | q_addr + ASC_SCSIQ_DONE_INFO_BEG, | |
9331 | (uchar *)scsiq, | |
9332 | (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2); | |
9333 | ||
9334 | _val = AscReadLramWord(iop_base, | |
9335 | (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS)); | |
9336 | scsiq->q_status = (uchar)_val; | |
9337 | scsiq->q_no = (uchar)(_val >> 8); | |
9338 | _val = AscReadLramWord(iop_base, | |
9339 | (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL)); | |
9340 | scsiq->cntl = (uchar)_val; | |
9341 | sg_queue_cnt = (uchar)(_val >> 8); | |
9342 | _val = AscReadLramWord(iop_base, | |
9343 | (ushort)(q_addr + | |
9344 | (ushort)ASC_SCSIQ_B_SENSE_LEN)); | |
9345 | scsiq->sense_len = (uchar)_val; | |
9346 | scsiq->extra_bytes = (uchar)(_val >> 8); | |
9347 | ||
9348 | /* | |
9349 | * Read high word of remain bytes from alternate location. | |
9350 | */ | |
9351 | scsiq->remain_bytes = (((ADV_DCNT)AscReadLramWord(iop_base, | |
9352 | (ushort)(q_addr + | |
9353 | (ushort) | |
9354 | ASC_SCSIQ_W_ALT_DC1))) | |
9355 | << 16); | |
9356 | /* | |
9357 | * Read low word of remain bytes from original location. | |
9358 | */ | |
9359 | scsiq->remain_bytes += AscReadLramWord(iop_base, | |
9360 | (ushort)(q_addr + (ushort) | |
9361 | ASC_SCSIQ_DW_REMAIN_XFER_CNT)); | |
9362 | ||
9363 | scsiq->remain_bytes &= max_dma_count; | |
9364 | return sg_queue_cnt; | |
9365 | } | |
9366 | ||
9367 | /* | |
9368 | * asc_isr_callback() - Second Level Interrupt Handler called by AscISR(). | |
9369 | * | |
9370 | * Interrupt callback function for the Narrow SCSI Asc Library. | |
9371 | */ | |
9372 | static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep) | |
9373 | { | |
9374 | asc_board_t *boardp; | |
9375 | struct scsi_cmnd *scp; | |
9376 | struct Scsi_Host *shost; | |
9377 | ||
9378 | ASC_DBG2(1, "asc_isr_callback: asc_dvc_varp 0x%lx, qdonep 0x%lx\n", | |
9379 | (ulong)asc_dvc_varp, (ulong)qdonep); | |
9380 | ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep); | |
9381 | ||
9382 | /* | |
9383 | * Get the struct scsi_cmnd structure and Scsi_Host structure for the | |
9384 | * command that has been completed. | |
9385 | */ | |
9386 | scp = (struct scsi_cmnd *)ASC_U32_TO_VADDR(qdonep->d2.srb_ptr); | |
9387 | ASC_DBG1(1, "asc_isr_callback: scp 0x%lx\n", (ulong)scp); | |
9388 | ||
9389 | if (scp == NULL) { | |
9390 | ASC_PRINT("asc_isr_callback: scp is NULL\n"); | |
9391 | return; | |
9392 | } | |
9393 | ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len); | |
9394 | ||
9395 | shost = scp->device->host; | |
9396 | ASC_STATS(shost, callback); | |
9397 | ASC_DBG1(1, "asc_isr_callback: shost 0x%lx\n", (ulong)shost); | |
9398 | ||
9399 | boardp = ASC_BOARDP(shost); | |
9400 | BUG_ON(asc_dvc_varp != &boardp->dvc_var.asc_dvc_var); | |
9401 | ||
9402 | /* | |
9403 | * 'qdonep' contains the command's ending status. | |
9404 | */ | |
9405 | switch (qdonep->d3.done_stat) { | |
9406 | case QD_NO_ERROR: | |
9407 | ASC_DBG(2, "asc_isr_callback: QD_NO_ERROR\n"); | |
9408 | scp->result = 0; | |
9409 | ||
9410 | /* | |
9411 | * Check for an underrun condition. | |
9412 | * | |
9413 | * If there was no error and an underrun condition, then | |
9414 | * return the number of underrun bytes. | |
9415 | */ | |
9416 | if (scp->request_bufflen != 0 && qdonep->remain_bytes != 0 && | |
9417 | qdonep->remain_bytes <= scp->request_bufflen) { | |
9418 | ASC_DBG1(1, | |
9419 | "asc_isr_callback: underrun condition %u bytes\n", | |
9420 | (unsigned)qdonep->remain_bytes); | |
9421 | scp->resid = qdonep->remain_bytes; | |
9422 | } | |
9423 | break; | |
9424 | ||
9425 | case QD_WITH_ERROR: | |
9426 | ASC_DBG(2, "asc_isr_callback: QD_WITH_ERROR\n"); | |
9427 | switch (qdonep->d3.host_stat) { | |
9428 | case QHSTA_NO_ERROR: | |
9429 | if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) { | |
9430 | ASC_DBG(2, | |
9431 | "asc_isr_callback: SAM_STAT_CHECK_CONDITION\n"); | |
9432 | ASC_DBG_PRT_SENSE(2, scp->sense_buffer, | |
9433 | sizeof(scp->sense_buffer)); | |
9434 | /* | |
9435 | * Note: The 'status_byte()' macro used by | |
9436 | * target drivers defined in scsi.h shifts the | |
9437 | * status byte returned by host drivers right | |
9438 | * by 1 bit. This is why target drivers also | |
9439 | * use right shifted status byte definitions. | |
9440 | * For instance target drivers use | |
9441 | * CHECK_CONDITION, defined to 0x1, instead of | |
9442 | * the SCSI defined check condition value of | |
9443 | * 0x2. Host drivers are supposed to return | |
9444 | * the status byte as it is defined by SCSI. | |
9445 | */ | |
9446 | scp->result = DRIVER_BYTE(DRIVER_SENSE) | | |
9447 | STATUS_BYTE(qdonep->d3.scsi_stat); | |
9448 | } else { | |
9449 | scp->result = STATUS_BYTE(qdonep->d3.scsi_stat); | |
9450 | } | |
9451 | break; | |
9452 | ||
9453 | default: | |
9454 | /* QHSTA error occurred */ | |
9455 | ASC_DBG1(1, "asc_isr_callback: host_stat 0x%x\n", | |
9456 | qdonep->d3.host_stat); | |
9457 | scp->result = HOST_BYTE(DID_BAD_TARGET); | |
9458 | break; | |
9459 | } | |
9460 | break; | |
9461 | ||
9462 | case QD_ABORTED_BY_HOST: | |
9463 | ASC_DBG(1, "asc_isr_callback: QD_ABORTED_BY_HOST\n"); | |
9464 | scp->result = | |
9465 | HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3. | |
9466 | scsi_msg) | | |
9467 | STATUS_BYTE(qdonep->d3.scsi_stat); | |
9468 | break; | |
9469 | ||
9470 | default: | |
9471 | ASC_DBG1(1, "asc_isr_callback: done_stat 0x%x\n", | |
9472 | qdonep->d3.done_stat); | |
9473 | scp->result = | |
9474 | HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3. | |
9475 | scsi_msg) | | |
9476 | STATUS_BYTE(qdonep->d3.scsi_stat); | |
9477 | break; | |
9478 | } | |
9479 | ||
9480 | /* | |
9481 | * If the 'init_tidmask' bit isn't already set for the target and the | |
9482 | * current request finished normally, then set the bit for the target | |
9483 | * to indicate that a device is present. | |
9484 | */ | |
9485 | if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 && | |
9486 | qdonep->d3.done_stat == QD_NO_ERROR && | |
9487 | qdonep->d3.host_stat == QHSTA_NO_ERROR) { | |
9488 | boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id); | |
9489 | } | |
1da177e4 | 9490 | |
51219358 | 9491 | asc_scsi_done(scp); |
1da177e4 | 9492 | |
51219358 MW |
9493 | return; |
9494 | } | |
9495 | ||
9496 | static int AscIsrQDone(ASC_DVC_VAR *asc_dvc) | |
9497 | { | |
9498 | uchar next_qp; | |
9499 | uchar n_q_used; | |
9500 | uchar sg_list_qp; | |
9501 | uchar sg_queue_cnt; | |
9502 | uchar q_cnt; | |
9503 | uchar done_q_tail; | |
9504 | uchar tid_no; | |
9505 | ASC_SCSI_BIT_ID_TYPE scsi_busy; | |
9506 | ASC_SCSI_BIT_ID_TYPE target_id; | |
9507 | PortAddr iop_base; | |
9508 | ushort q_addr; | |
9509 | ushort sg_q_addr; | |
9510 | uchar cur_target_qng; | |
9511 | ASC_QDONE_INFO scsiq_buf; | |
9512 | ASC_QDONE_INFO *scsiq; | |
9513 | int false_overrun; | |
9514 | ||
9515 | iop_base = asc_dvc->iop_base; | |
9516 | n_q_used = 1; | |
9517 | scsiq = (ASC_QDONE_INFO *)&scsiq_buf; | |
9518 | done_q_tail = (uchar)AscGetVarDoneQTail(iop_base); | |
9519 | q_addr = ASC_QNO_TO_QADDR(done_q_tail); | |
9520 | next_qp = AscReadLramByte(iop_base, | |
9521 | (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD)); | |
9522 | if (next_qp != ASC_QLINK_END) { | |
9523 | AscPutVarDoneQTail(iop_base, next_qp); | |
9524 | q_addr = ASC_QNO_TO_QADDR(next_qp); | |
9525 | sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq, | |
9526 | asc_dvc->max_dma_count); | |
9527 | AscWriteLramByte(iop_base, | |
9528 | (ushort)(q_addr + | |
9529 | (ushort)ASC_SCSIQ_B_STATUS), | |
9530 | (uchar)(scsiq-> | |
9531 | q_status & (uchar)~(QS_READY | | |
9532 | QS_ABORTED))); | |
9533 | tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix); | |
9534 | target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix); | |
9535 | if ((scsiq->cntl & QC_SG_HEAD) != 0) { | |
9536 | sg_q_addr = q_addr; | |
9537 | sg_list_qp = next_qp; | |
9538 | for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) { | |
9539 | sg_list_qp = AscReadLramByte(iop_base, | |
9540 | (ushort)(sg_q_addr | |
9541 | + (ushort) | |
9542 | ASC_SCSIQ_B_FWD)); | |
9543 | sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp); | |
9544 | if (sg_list_qp == ASC_QLINK_END) { | |
9545 | AscSetLibErrorCode(asc_dvc, | |
9546 | ASCQ_ERR_SG_Q_LINKS); | |
9547 | scsiq->d3.done_stat = QD_WITH_ERROR; | |
9548 | scsiq->d3.host_stat = | |
9549 | QHSTA_D_QDONE_SG_LIST_CORRUPTED; | |
9550 | goto FATAL_ERR_QDONE; | |
9551 | } | |
9552 | AscWriteLramByte(iop_base, | |
9553 | (ushort)(sg_q_addr + (ushort) | |
9554 | ASC_SCSIQ_B_STATUS), | |
9555 | QS_FREE); | |
9556 | } | |
9557 | n_q_used = sg_queue_cnt + 1; | |
9558 | AscPutVarDoneQTail(iop_base, sg_list_qp); | |
9559 | } | |
9560 | if (asc_dvc->queue_full_or_busy & target_id) { | |
9561 | cur_target_qng = AscReadLramByte(iop_base, | |
9562 | (ushort)((ushort) | |
9563 | ASC_QADR_BEG | |
9564 | + (ushort) | |
9565 | scsiq->d2. | |
9566 | target_ix)); | |
9567 | if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) { | |
9568 | scsi_busy = AscReadLramByte(iop_base, (ushort) | |
9569 | ASCV_SCSIBUSY_B); | |
9570 | scsi_busy &= ~target_id; | |
9571 | AscWriteLramByte(iop_base, | |
9572 | (ushort)ASCV_SCSIBUSY_B, | |
9573 | scsi_busy); | |
9574 | asc_dvc->queue_full_or_busy &= ~target_id; | |
9575 | } | |
9576 | } | |
9577 | if (asc_dvc->cur_total_qng >= n_q_used) { | |
9578 | asc_dvc->cur_total_qng -= n_q_used; | |
9579 | if (asc_dvc->cur_dvc_qng[tid_no] != 0) { | |
9580 | asc_dvc->cur_dvc_qng[tid_no]--; | |
9581 | } | |
9582 | } else { | |
9583 | AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG); | |
9584 | scsiq->d3.done_stat = QD_WITH_ERROR; | |
9585 | goto FATAL_ERR_QDONE; | |
9586 | } | |
9587 | if ((scsiq->d2.srb_ptr == 0UL) || | |
9588 | ((scsiq->q_status & QS_ABORTED) != 0)) { | |
9589 | return (0x11); | |
9590 | } else if (scsiq->q_status == QS_DONE) { | |
9591 | false_overrun = FALSE; | |
9592 | if (scsiq->extra_bytes != 0) { | |
9593 | scsiq->remain_bytes += | |
9594 | (ADV_DCNT)scsiq->extra_bytes; | |
9595 | } | |
9596 | if (scsiq->d3.done_stat == QD_WITH_ERROR) { | |
9597 | if (scsiq->d3.host_stat == | |
9598 | QHSTA_M_DATA_OVER_RUN) { | |
9599 | if ((scsiq-> | |
9600 | cntl & (QC_DATA_IN | QC_DATA_OUT)) | |
9601 | == 0) { | |
9602 | scsiq->d3.done_stat = | |
9603 | QD_NO_ERROR; | |
9604 | scsiq->d3.host_stat = | |
9605 | QHSTA_NO_ERROR; | |
9606 | } else if (false_overrun) { | |
9607 | scsiq->d3.done_stat = | |
9608 | QD_NO_ERROR; | |
9609 | scsiq->d3.host_stat = | |
9610 | QHSTA_NO_ERROR; | |
9611 | } | |
9612 | } else if (scsiq->d3.host_stat == | |
9613 | QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) { | |
9614 | AscStopChip(iop_base); | |
9615 | AscSetChipControl(iop_base, | |
9616 | (uchar)(CC_SCSI_RESET | |
9617 | | CC_HALT)); | |
9618 | udelay(60); | |
9619 | AscSetChipControl(iop_base, CC_HALT); | |
9620 | AscSetChipStatus(iop_base, | |
9621 | CIW_CLR_SCSI_RESET_INT); | |
9622 | AscSetChipStatus(iop_base, 0); | |
9623 | AscSetChipControl(iop_base, 0); | |
9624 | } | |
9625 | } | |
9626 | if ((scsiq->cntl & QC_NO_CALLBACK) == 0) { | |
9627 | asc_isr_callback(asc_dvc, scsiq); | |
9628 | } else { | |
9629 | if ((AscReadLramByte(iop_base, | |
9630 | (ushort)(q_addr + (ushort) | |
9631 | ASC_SCSIQ_CDB_BEG)) | |
9632 | == START_STOP)) { | |
9633 | asc_dvc->unit_not_ready &= ~target_id; | |
9634 | if (scsiq->d3.done_stat != QD_NO_ERROR) { | |
9635 | asc_dvc->start_motor &= | |
9636 | ~target_id; | |
9637 | } | |
9638 | } | |
9639 | } | |
9640 | return (1); | |
9641 | } else { | |
9642 | AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS); | |
9643 | FATAL_ERR_QDONE: | |
9644 | if ((scsiq->cntl & QC_NO_CALLBACK) == 0) { | |
9645 | asc_isr_callback(asc_dvc, scsiq); | |
9646 | } | |
9647 | return (0x80); | |
9648 | } | |
9649 | } | |
9650 | return (0); | |
9651 | } | |
1da177e4 | 9652 | |
51219358 MW |
9653 | static int AscISR(ASC_DVC_VAR *asc_dvc) |
9654 | { | |
9655 | ASC_CS_TYPE chipstat; | |
9656 | PortAddr iop_base; | |
9657 | ushort saved_ram_addr; | |
9658 | uchar ctrl_reg; | |
9659 | uchar saved_ctrl_reg; | |
9660 | int int_pending; | |
9661 | int status; | |
9662 | uchar host_flag; | |
1da177e4 | 9663 | |
51219358 MW |
9664 | iop_base = asc_dvc->iop_base; |
9665 | int_pending = FALSE; | |
1da177e4 | 9666 | |
51219358 MW |
9667 | if (AscIsIntPending(iop_base) == 0) |
9668 | return int_pending; | |
9669 | ||
9670 | if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) { | |
9671 | return ERR; | |
9672 | } | |
9673 | if (asc_dvc->in_critical_cnt != 0) { | |
9674 | AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL); | |
9675 | return ERR; | |
9676 | } | |
9677 | if (asc_dvc->is_in_int) { | |
9678 | AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY); | |
9679 | return ERR; | |
9680 | } | |
9681 | asc_dvc->is_in_int = TRUE; | |
9682 | ctrl_reg = AscGetChipControl(iop_base); | |
9683 | saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET | | |
9684 | CC_SINGLE_STEP | CC_DIAG | CC_TEST)); | |
9685 | chipstat = AscGetChipStatus(iop_base); | |
9686 | if (chipstat & CSW_SCSI_RESET_LATCH) { | |
9687 | if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) { | |
9688 | int i = 10; | |
9689 | int_pending = TRUE; | |
9690 | asc_dvc->sdtr_done = 0; | |
9691 | saved_ctrl_reg &= (uchar)(~CC_HALT); | |
9692 | while ((AscGetChipStatus(iop_base) & | |
9693 | CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) { | |
9694 | mdelay(100); | |
9695 | } | |
9696 | AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT)); | |
9697 | AscSetChipControl(iop_base, CC_HALT); | |
9698 | AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT); | |
9699 | AscSetChipStatus(iop_base, 0); | |
9700 | chipstat = AscGetChipStatus(iop_base); | |
9701 | } | |
9702 | } | |
9703 | saved_ram_addr = AscGetChipLramAddr(iop_base); | |
9704 | host_flag = AscReadLramByte(iop_base, | |
9705 | ASCV_HOST_FLAG_B) & | |
9706 | (uchar)(~ASC_HOST_FLAG_IN_ISR); | |
9707 | AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, | |
9708 | (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR)); | |
9709 | if ((chipstat & CSW_INT_PENDING) || (int_pending)) { | |
9710 | AscAckInterrupt(iop_base); | |
9711 | int_pending = TRUE; | |
9712 | if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) { | |
9713 | if (AscIsrChipHalted(asc_dvc) == ERR) { | |
9714 | goto ISR_REPORT_QDONE_FATAL_ERROR; | |
9715 | } else { | |
9716 | saved_ctrl_reg &= (uchar)(~CC_HALT); | |
9717 | } | |
9718 | } else { | |
9719 | ISR_REPORT_QDONE_FATAL_ERROR: | |
9720 | if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) { | |
9721 | while (((status = | |
9722 | AscIsrQDone(asc_dvc)) & 0x01) != 0) { | |
9723 | } | |
9724 | } else { | |
9725 | do { | |
9726 | if ((status = | |
9727 | AscIsrQDone(asc_dvc)) == 1) { | |
9728 | break; | |
9729 | } | |
9730 | } while (status == 0x11); | |
9731 | } | |
9732 | if ((status & 0x80) != 0) | |
9733 | int_pending = ERR; | |
9734 | } | |
9735 | } | |
9736 | AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag); | |
9737 | AscSetChipLramAddr(iop_base, saved_ram_addr); | |
9738 | AscSetChipControl(iop_base, saved_ctrl_reg); | |
9739 | asc_dvc->is_in_int = FALSE; | |
9740 | return int_pending; | |
9741 | } | |
1da177e4 LT |
9742 | |
9743 | /* | |
51219358 | 9744 | * advansys_reset() |
1da177e4 | 9745 | * |
51219358 | 9746 | * Reset the bus associated with the command 'scp'. |
1da177e4 | 9747 | * |
51219358 MW |
9748 | * This function runs its own thread. Interrupts must be blocked but |
9749 | * sleeping is allowed and no locking other than for host structures is | |
9750 | * required. Returns SUCCESS or FAILED. | |
1da177e4 | 9751 | */ |
51219358 | 9752 | static int advansys_reset(struct scsi_cmnd *scp) |
1da177e4 | 9753 | { |
51219358 MW |
9754 | struct Scsi_Host *shost; |
9755 | asc_board_t *boardp; | |
9756 | ASC_DVC_VAR *asc_dvc_varp; | |
9757 | ADV_DVC_VAR *adv_dvc_varp; | |
9758 | ulong flags; | |
27c868c2 | 9759 | int status; |
51219358 | 9760 | int ret = SUCCESS; |
27c868c2 | 9761 | |
51219358 | 9762 | ASC_DBG1(1, "advansys_reset: 0x%lx\n", (ulong)scp); |
1da177e4 | 9763 | |
51219358 MW |
9764 | #ifdef ADVANSYS_STATS |
9765 | if (scp->device->host != NULL) { | |
9766 | ASC_STATS(scp->device->host, reset); | |
9767 | } | |
9768 | #endif /* ADVANSYS_STATS */ | |
27c868c2 | 9769 | |
51219358 MW |
9770 | if ((shost = scp->device->host) == NULL) { |
9771 | scp->result = HOST_BYTE(DID_ERROR); | |
9772 | return FAILED; | |
9773 | } | |
27c868c2 | 9774 | |
51219358 | 9775 | boardp = ASC_BOARDP(shost); |
27c868c2 | 9776 | |
51219358 MW |
9777 | ASC_PRINT1("advansys_reset: board %d: SCSI bus reset started...\n", |
9778 | boardp->id); | |
27c868c2 | 9779 | /* |
51219358 | 9780 | * Check for re-entrancy. |
27c868c2 | 9781 | */ |
51219358 MW |
9782 | spin_lock_irqsave(&boardp->lock, flags); |
9783 | if (boardp->flags & ASC_HOST_IN_RESET) { | |
9784 | spin_unlock_irqrestore(&boardp->lock, flags); | |
9785 | return FAILED; | |
9786 | } | |
9787 | boardp->flags |= ASC_HOST_IN_RESET; | |
9788 | spin_unlock_irqrestore(&boardp->lock, flags); | |
9789 | ||
9790 | if (ASC_NARROW_BOARD(boardp)) { | |
27c868c2 | 9791 | /* |
51219358 | 9792 | * Narrow Board |
27c868c2 | 9793 | */ |
51219358 | 9794 | asc_dvc_varp = &boardp->dvc_var.asc_dvc_var; |
1da177e4 | 9795 | |
27c868c2 | 9796 | /* |
51219358 | 9797 | * Reset the chip and SCSI bus. |
27c868c2 | 9798 | */ |
51219358 MW |
9799 | ASC_DBG(1, "advansys_reset: before AscInitAsc1000Driver()\n"); |
9800 | status = AscInitAsc1000Driver(asc_dvc_varp); | |
27c868c2 | 9801 | |
51219358 MW |
9802 | /* Refer to ASC_IERR_* defintions for meaning of 'err_code'. */ |
9803 | if (asc_dvc_varp->err_code) { | |
9804 | ASC_PRINT2("advansys_reset: board %d: SCSI bus reset " | |
9805 | "error: 0x%x\n", boardp->id, | |
9806 | asc_dvc_varp->err_code); | |
9807 | ret = FAILED; | |
9808 | } else if (status) { | |
9809 | ASC_PRINT2("advansys_reset: board %d: SCSI bus reset " | |
9810 | "warning: 0x%x\n", boardp->id, status); | |
27c868c2 | 9811 | } else { |
51219358 MW |
9812 | ASC_PRINT1("advansys_reset: board %d: SCSI bus reset " |
9813 | "successful.\n", boardp->id); | |
27c868c2 | 9814 | } |
a9f4a59a | 9815 | |
51219358 MW |
9816 | ASC_DBG(1, "advansys_reset: after AscInitAsc1000Driver()\n"); |
9817 | spin_lock_irqsave(&boardp->lock, flags); | |
a9f4a59a | 9818 | |
a9f4a59a | 9819 | } else { |
a9f4a59a | 9820 | /* |
51219358 MW |
9821 | * Wide Board |
9822 | * | |
9823 | * If the suggest reset bus flags are set, then reset the bus. | |
9824 | * Otherwise only reset the device. | |
a9f4a59a | 9825 | */ |
51219358 | 9826 | adv_dvc_varp = &boardp->dvc_var.adv_dvc_var; |
a9f4a59a MW |
9827 | |
9828 | /* | |
51219358 | 9829 | * Reset the target's SCSI bus. |
a9f4a59a | 9830 | */ |
51219358 MW |
9831 | ASC_DBG(1, "advansys_reset: before AdvResetChipAndSB()\n"); |
9832 | switch (AdvResetChipAndSB(adv_dvc_varp)) { | |
9833 | case ASC_TRUE: | |
9834 | ASC_PRINT1("advansys_reset: board %d: SCSI bus reset " | |
9835 | "successful.\n", boardp->id); | |
9836 | break; | |
9837 | case ASC_FALSE: | |
9838 | default: | |
9839 | ASC_PRINT1("advansys_reset: board %d: SCSI bus reset " | |
9840 | "error.\n", boardp->id); | |
9841 | ret = FAILED; | |
9842 | break; | |
b9d96614 | 9843 | } |
51219358 MW |
9844 | spin_lock_irqsave(&boardp->lock, flags); |
9845 | AdvISR(adv_dvc_varp); | |
b9d96614 | 9846 | } |
51219358 | 9847 | /* Board lock is held. */ |
b9d96614 | 9848 | |
51219358 MW |
9849 | /* Save the time of the most recently completed reset. */ |
9850 | boardp->last_reset = jiffies; | |
b9d96614 | 9851 | |
51219358 MW |
9852 | /* Clear reset flag. */ |
9853 | boardp->flags &= ~ASC_HOST_IN_RESET; | |
9854 | spin_unlock_irqrestore(&boardp->lock, flags); | |
b9d96614 | 9855 | |
51219358 | 9856 | ASC_DBG1(1, "advansys_reset: ret %d\n", ret); |
b9d96614 | 9857 | |
51219358 | 9858 | return ret; |
b9d96614 MW |
9859 | } |
9860 | ||
1da177e4 | 9861 | /* |
51219358 | 9862 | * advansys_biosparam() |
1da177e4 | 9863 | * |
51219358 MW |
9864 | * Translate disk drive geometry if the "BIOS greater than 1 GB" |
9865 | * support is enabled for a drive. | |
1da177e4 | 9866 | * |
51219358 MW |
9867 | * ip (information pointer) is an int array with the following definition: |
9868 | * ip[0]: heads | |
9869 | * ip[1]: sectors | |
9870 | * ip[2]: cylinders | |
1da177e4 | 9871 | */ |
51219358 MW |
9872 | static int |
9873 | advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev, | |
9874 | sector_t capacity, int ip[]) | |
1da177e4 | 9875 | { |
51219358 | 9876 | asc_board_t *boardp; |
1da177e4 | 9877 | |
51219358 MW |
9878 | ASC_DBG(1, "advansys_biosparam: begin\n"); |
9879 | ASC_STATS(sdev->host, biosparam); | |
9880 | boardp = ASC_BOARDP(sdev->host); | |
9881 | if (ASC_NARROW_BOARD(boardp)) { | |
9882 | if ((boardp->dvc_var.asc_dvc_var.dvc_cntl & | |
9883 | ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) { | |
9884 | ip[0] = 255; | |
9885 | ip[1] = 63; | |
9886 | } else { | |
9887 | ip[0] = 64; | |
9888 | ip[1] = 32; | |
9889 | } | |
9890 | } else { | |
9891 | if ((boardp->dvc_var.adv_dvc_var.bios_ctrl & | |
9892 | BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) { | |
9893 | ip[0] = 255; | |
9894 | ip[1] = 63; | |
9895 | } else { | |
9896 | ip[0] = 64; | |
9897 | ip[1] = 32; | |
9898 | } | |
27c868c2 | 9899 | } |
51219358 MW |
9900 | ip[2] = (unsigned long)capacity / (ip[0] * ip[1]); |
9901 | ASC_DBG(1, "advansys_biosparam: end\n"); | |
9902 | return 0; | |
9903 | } | |
1da177e4 | 9904 | |
51219358 MW |
9905 | /* |
9906 | * First-level interrupt handler. | |
9907 | * | |
9908 | * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host. | |
9909 | */ | |
9910 | static irqreturn_t advansys_interrupt(int irq, void *dev_id) | |
9911 | { | |
9912 | unsigned long flags; | |
9913 | struct Scsi_Host *shost = dev_id; | |
9914 | asc_board_t *boardp = ASC_BOARDP(shost); | |
9915 | irqreturn_t result = IRQ_NONE; | |
27c868c2 | 9916 | |
51219358 MW |
9917 | ASC_DBG1(2, "advansys_interrupt: boardp 0x%p\n", boardp); |
9918 | spin_lock_irqsave(&boardp->lock, flags); | |
9919 | if (ASC_NARROW_BOARD(boardp)) { | |
9920 | if (AscIsIntPending(shost->io_port)) { | |
9921 | result = IRQ_HANDLED; | |
9922 | ASC_STATS(shost, interrupt); | |
9923 | ASC_DBG(1, "advansys_interrupt: before AscISR()\n"); | |
9924 | AscISR(&boardp->dvc_var.asc_dvc_var); | |
9925 | } | |
9926 | } else { | |
9927 | ASC_DBG(1, "advansys_interrupt: before AdvISR()\n"); | |
9928 | if (AdvISR(&boardp->dvc_var.adv_dvc_var)) { | |
9929 | result = IRQ_HANDLED; | |
9930 | ASC_STATS(shost, interrupt); | |
9931 | } | |
27c868c2 | 9932 | } |
51219358 | 9933 | spin_unlock_irqrestore(&boardp->lock, flags); |
1da177e4 | 9934 | |
51219358 MW |
9935 | ASC_DBG(1, "advansys_interrupt: end\n"); |
9936 | return result; | |
9937 | } | |
27c868c2 | 9938 | |
51219358 MW |
9939 | static int AscHostReqRiscHalt(PortAddr iop_base) |
9940 | { | |
9941 | int count = 0; | |
9942 | int sta = 0; | |
9943 | uchar saved_stop_code; | |
9944 | ||
9945 | if (AscIsChipHalted(iop_base)) | |
9946 | return (1); | |
9947 | saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B); | |
9948 | AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, | |
9949 | ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP); | |
9950 | do { | |
9951 | if (AscIsChipHalted(iop_base)) { | |
9952 | sta = 1; | |
9953 | break; | |
27c868c2 | 9954 | } |
51219358 MW |
9955 | mdelay(100); |
9956 | } while (count++ < 20); | |
9957 | AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code); | |
9958 | return (sta); | |
9959 | } | |
1da177e4 | 9960 | |
51219358 MW |
9961 | static int |
9962 | AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data) | |
9963 | { | |
9964 | int sta = FALSE; | |
1da177e4 | 9965 | |
51219358 MW |
9966 | if (AscHostReqRiscHalt(iop_base)) { |
9967 | sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data); | |
9968 | AscStartChip(iop_base); | |
27c868c2 | 9969 | } |
51219358 MW |
9970 | return sta; |
9971 | } | |
1da177e4 | 9972 | |
51219358 MW |
9973 | static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev) |
9974 | { | |
9975 | char type = sdev->type; | |
9976 | ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id; | |
27c868c2 | 9977 | |
51219358 MW |
9978 | if (!(asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN)) |
9979 | return; | |
9980 | if (asc_dvc->init_sdtr & tid_bits) | |
9981 | return; | |
27c868c2 | 9982 | |
51219358 MW |
9983 | if ((type == TYPE_ROM) && (strncmp(sdev->vendor, "HP ", 3) == 0)) |
9984 | asc_dvc->pci_fix_asyn_xfer_always |= tid_bits; | |
27c868c2 | 9985 | |
51219358 MW |
9986 | asc_dvc->pci_fix_asyn_xfer |= tid_bits; |
9987 | if ((type == TYPE_PROCESSOR) || (type == TYPE_SCANNER) || | |
9988 | (type == TYPE_ROM) || (type == TYPE_TAPE)) | |
9989 | asc_dvc->pci_fix_asyn_xfer &= ~tid_bits; | |
9990 | ||
9991 | if (asc_dvc->pci_fix_asyn_xfer & tid_bits) | |
9992 | AscSetRunChipSynRegAtID(asc_dvc->iop_base, sdev->id, | |
9993 | ASYN_SDTR_DATA_FIX_PCI_REV_AB); | |
9994 | } | |
1da177e4 | 9995 | |
51219358 MW |
9996 | static void |
9997 | advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc) | |
9998 | { | |
9999 | ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id; | |
10000 | ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng; | |
27c868c2 | 10001 | |
51219358 MW |
10002 | if (sdev->lun == 0) { |
10003 | ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr; | |
10004 | if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) { | |
10005 | asc_dvc->init_sdtr |= tid_bit; | |
10006 | } else { | |
10007 | asc_dvc->init_sdtr &= ~tid_bit; | |
10008 | } | |
10009 | ||
10010 | if (orig_init_sdtr != asc_dvc->init_sdtr) | |
10011 | AscAsyncFix(asc_dvc, sdev); | |
27c868c2 | 10012 | } |
1da177e4 | 10013 | |
51219358 MW |
10014 | if (sdev->tagged_supported) { |
10015 | if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) { | |
10016 | if (sdev->lun == 0) { | |
10017 | asc_dvc->cfg->can_tagged_qng |= tid_bit; | |
10018 | asc_dvc->use_tagged_qng |= tid_bit; | |
10019 | } | |
10020 | scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, | |
10021 | asc_dvc->max_dvc_qng[sdev->id]); | |
27c868c2 | 10022 | } |
51219358 MW |
10023 | } else { |
10024 | if (sdev->lun == 0) { | |
10025 | asc_dvc->cfg->can_tagged_qng &= ~tid_bit; | |
10026 | asc_dvc->use_tagged_qng &= ~tid_bit; | |
27c868c2 | 10027 | } |
51219358 | 10028 | scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun); |
27c868c2 | 10029 | } |
1da177e4 | 10030 | |
51219358 MW |
10031 | if ((sdev->lun == 0) && |
10032 | (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) { | |
10033 | AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B, | |
10034 | asc_dvc->cfg->disc_enable); | |
10035 | AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B, | |
10036 | asc_dvc->use_tagged_qng); | |
10037 | AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B, | |
10038 | asc_dvc->cfg->can_tagged_qng); | |
27c868c2 | 10039 | |
51219358 MW |
10040 | asc_dvc->max_dvc_qng[sdev->id] = |
10041 | asc_dvc->cfg->max_tag_qng[sdev->id]; | |
10042 | AscWriteLramByte(asc_dvc->iop_base, | |
10043 | (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id), | |
10044 | asc_dvc->max_dvc_qng[sdev->id]); | |
10045 | } | |
10046 | } | |
27c868c2 | 10047 | |
51219358 MW |
10048 | /* |
10049 | * Wide Transfers | |
10050 | * | |
10051 | * If the EEPROM enabled WDTR for the device and the device supports wide | |
10052 | * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and | |
10053 | * write the new value to the microcode. | |
10054 | */ | |
10055 | static void | |
10056 | advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask) | |
10057 | { | |
10058 | unsigned short cfg_word; | |
10059 | AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word); | |
10060 | if ((cfg_word & tidmask) != 0) | |
10061 | return; | |
27c868c2 | 10062 | |
51219358 MW |
10063 | cfg_word |= tidmask; |
10064 | AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word); | |
27c868c2 MW |
10065 | |
10066 | /* | |
51219358 MW |
10067 | * Clear the microcode SDTR and WDTR negotiation done indicators for |
10068 | * the target to cause it to negotiate with the new setting set above. | |
10069 | * WDTR when accepted causes the target to enter asynchronous mode, so | |
10070 | * SDTR must be negotiated. | |
27c868c2 | 10071 | */ |
51219358 MW |
10072 | AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word); |
10073 | cfg_word &= ~tidmask; | |
10074 | AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word); | |
10075 | AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word); | |
10076 | cfg_word &= ~tidmask; | |
10077 | AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word); | |
10078 | } | |
1da177e4 | 10079 | |
51219358 MW |
10080 | /* |
10081 | * Synchronous Transfers | |
10082 | * | |
10083 | * If the EEPROM enabled SDTR for the device and the device | |
10084 | * supports synchronous transfers, then turn on the device's | |
10085 | * 'sdtr_able' bit. Write the new value to the microcode. | |
10086 | */ | |
10087 | static void | |
10088 | advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask) | |
10089 | { | |
10090 | unsigned short cfg_word; | |
10091 | AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word); | |
10092 | if ((cfg_word & tidmask) != 0) | |
10093 | return; | |
1da177e4 | 10094 | |
51219358 MW |
10095 | cfg_word |= tidmask; |
10096 | AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word); | |
1da177e4 | 10097 | |
27c868c2 | 10098 | /* |
51219358 MW |
10099 | * Clear the microcode "SDTR negotiation" done indicator for the |
10100 | * target to cause it to negotiate with the new setting set above. | |
27c868c2 | 10101 | */ |
51219358 MW |
10102 | AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word); |
10103 | cfg_word &= ~tidmask; | |
10104 | AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word); | |
10105 | } | |
27c868c2 | 10106 | |
51219358 MW |
10107 | /* |
10108 | * PPR (Parallel Protocol Request) Capable | |
10109 | * | |
10110 | * If the device supports DT mode, then it must be PPR capable. | |
10111 | * The PPR message will be used in place of the SDTR and WDTR | |
10112 | * messages to negotiate synchronous speed and offset, transfer | |
10113 | * width, and protocol options. | |
10114 | */ | |
10115 | static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc, | |
10116 | AdvPortAddr iop_base, unsigned short tidmask) | |
10117 | { | |
10118 | AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able); | |
10119 | adv_dvc->ppr_able |= tidmask; | |
10120 | AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able); | |
10121 | } | |
27c868c2 | 10122 | |
51219358 MW |
10123 | static void |
10124 | advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc) | |
10125 | { | |
10126 | AdvPortAddr iop_base = adv_dvc->iop_base; | |
10127 | unsigned short tidmask = 1 << sdev->id; | |
10128 | ||
10129 | if (sdev->lun == 0) { | |
10130 | /* | |
10131 | * Handle WDTR, SDTR, and Tag Queuing. If the feature | |
10132 | * is enabled in the EEPROM and the device supports the | |
10133 | * feature, then enable it in the microcode. | |
10134 | */ | |
27c868c2 | 10135 | |
51219358 MW |
10136 | if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr) |
10137 | advansys_wide_enable_wdtr(iop_base, tidmask); | |
10138 | if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr) | |
10139 | advansys_wide_enable_sdtr(iop_base, tidmask); | |
10140 | if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr) | |
10141 | advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask); | |
10142 | ||
10143 | /* | |
10144 | * Tag Queuing is disabled for the BIOS which runs in polled | |
10145 | * mode and would see no benefit from Tag Queuing. Also by | |
10146 | * disabling Tag Queuing in the BIOS devices with Tag Queuing | |
10147 | * bugs will at least work with the BIOS. | |
10148 | */ | |
10149 | if ((adv_dvc->tagqng_able & tidmask) && | |
10150 | sdev->tagged_supported) { | |
10151 | unsigned short cfg_word; | |
10152 | AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word); | |
10153 | cfg_word |= tidmask; | |
10154 | AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, | |
10155 | cfg_word); | |
10156 | AdvWriteByteLram(iop_base, | |
10157 | ASC_MC_NUMBER_OF_MAX_CMD + sdev->id, | |
10158 | adv_dvc->max_dvc_qng); | |
27c868c2 MW |
10159 | } |
10160 | } | |
1da177e4 | 10161 | |
51219358 MW |
10162 | if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported) { |
10163 | scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, | |
10164 | adv_dvc->max_dvc_qng); | |
10165 | } else { | |
10166 | scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun); | |
10167 | } | |
10168 | } | |
27c868c2 | 10169 | |
51219358 MW |
10170 | /* |
10171 | * Set the number of commands to queue per device for the | |
10172 | * specified host adapter. | |
10173 | */ | |
10174 | static int advansys_slave_configure(struct scsi_device *sdev) | |
10175 | { | |
10176 | asc_board_t *boardp = ASC_BOARDP(sdev->host); | |
10177 | boardp->flags |= ASC_SELECT_QUEUE_DEPTHS; | |
27c868c2 | 10178 | |
51219358 MW |
10179 | if (ASC_NARROW_BOARD(boardp)) |
10180 | advansys_narrow_slave_configure(sdev, | |
10181 | &boardp->dvc_var.asc_dvc_var); | |
10182 | else | |
10183 | advansys_wide_slave_configure(sdev, | |
10184 | &boardp->dvc_var.adv_dvc_var); | |
1da177e4 | 10185 | |
51219358 MW |
10186 | return 0; |
10187 | } | |
27c868c2 | 10188 | |
05848b6e MW |
10189 | static int asc_build_req(asc_board_t *boardp, struct scsi_cmnd *scp, |
10190 | struct asc_scsi_q *asc_scsi_q) | |
51219358 | 10191 | { |
05848b6e | 10192 | memset(asc_scsi_q, 0, sizeof(*asc_scsi_q)); |
27c868c2 MW |
10193 | |
10194 | /* | |
51219358 | 10195 | * Point the ASC_SCSI_Q to the 'struct scsi_cmnd'. |
27c868c2 | 10196 | */ |
05848b6e | 10197 | asc_scsi_q->q2.srb_ptr = ASC_VADDR_TO_U32(scp); |
27c868c2 MW |
10198 | |
10199 | /* | |
51219358 | 10200 | * Build the ASC_SCSI_Q request. |
27c868c2 | 10201 | */ |
05848b6e MW |
10202 | asc_scsi_q->cdbptr = &scp->cmnd[0]; |
10203 | asc_scsi_q->q2.cdb_len = scp->cmd_len; | |
10204 | asc_scsi_q->q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id); | |
10205 | asc_scsi_q->q1.target_lun = scp->device->lun; | |
10206 | asc_scsi_q->q2.target_ix = | |
51219358 | 10207 | ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun); |
05848b6e | 10208 | asc_scsi_q->q1.sense_addr = |
51219358 | 10209 | cpu_to_le32(virt_to_bus(&scp->sense_buffer[0])); |
05848b6e | 10210 | asc_scsi_q->q1.sense_len = sizeof(scp->sense_buffer); |
27c868c2 MW |
10211 | |
10212 | /* | |
51219358 MW |
10213 | * If there are any outstanding requests for the current target, |
10214 | * then every 255th request send an ORDERED request. This heuristic | |
10215 | * tries to retain the benefit of request sorting while preventing | |
10216 | * request starvation. 255 is the max number of tags or pending commands | |
10217 | * a device may have outstanding. | |
10218 | * | |
10219 | * The request count is incremented below for every successfully | |
10220 | * started request. | |
27c868c2 | 10221 | * |
27c868c2 | 10222 | */ |
51219358 MW |
10223 | if ((boardp->dvc_var.asc_dvc_var.cur_dvc_qng[scp->device->id] > 0) && |
10224 | (boardp->reqcnt[scp->device->id] % 255) == 0) { | |
05848b6e | 10225 | asc_scsi_q->q2.tag_code = MSG_ORDERED_TAG; |
51219358 | 10226 | } else { |
05848b6e | 10227 | asc_scsi_q->q2.tag_code = MSG_SIMPLE_TAG; |
51219358 | 10228 | } |
27c868c2 MW |
10229 | |
10230 | /* | |
51219358 MW |
10231 | * Build ASC_SCSI_Q for a contiguous buffer or a scatter-gather |
10232 | * buffer command. | |
27c868c2 | 10233 | */ |
51219358 MW |
10234 | if (scp->use_sg == 0) { |
10235 | /* | |
10236 | * CDB request of single contiguous buffer. | |
10237 | */ | |
10238 | ASC_STATS(scp->device->host, cont_cnt); | |
10239 | scp->SCp.dma_handle = scp->request_bufflen ? | |
10240 | dma_map_single(boardp->dev, scp->request_buffer, | |
10241 | scp->request_bufflen, | |
10242 | scp->sc_data_direction) : 0; | |
05848b6e MW |
10243 | asc_scsi_q->q1.data_addr = cpu_to_le32(scp->SCp.dma_handle); |
10244 | asc_scsi_q->q1.data_cnt = cpu_to_le32(scp->request_bufflen); | |
51219358 MW |
10245 | ASC_STATS_ADD(scp->device->host, cont_xfer, |
10246 | ASC_CEILING(scp->request_bufflen, 512)); | |
05848b6e MW |
10247 | asc_scsi_q->q1.sg_queue_cnt = 0; |
10248 | asc_scsi_q->sg_head = NULL; | |
51219358 MW |
10249 | } else { |
10250 | /* | |
10251 | * CDB scatter-gather request list. | |
10252 | */ | |
10253 | int sgcnt; | |
10254 | int use_sg; | |
10255 | struct scatterlist *slp; | |
05848b6e | 10256 | struct asc_sg_head *asc_sg_head; |
27c868c2 | 10257 | |
51219358 MW |
10258 | slp = (struct scatterlist *)scp->request_buffer; |
10259 | use_sg = dma_map_sg(boardp->dev, slp, scp->use_sg, | |
10260 | scp->sc_data_direction); | |
27c868c2 | 10261 | |
51219358 MW |
10262 | if (use_sg > scp->device->host->sg_tablesize) { |
10263 | ASC_PRINT3("asc_build_req: board %d: use_sg %d > " | |
10264 | "sg_tablesize %d\n", boardp->id, use_sg, | |
10265 | scp->device->host->sg_tablesize); | |
10266 | dma_unmap_sg(boardp->dev, slp, scp->use_sg, | |
10267 | scp->sc_data_direction); | |
10268 | scp->result = HOST_BYTE(DID_ERROR); | |
10269 | return ASC_ERROR; | |
10270 | } | |
27c868c2 | 10271 | |
51219358 | 10272 | ASC_STATS(scp->device->host, sg_cnt); |
27c868c2 | 10273 | |
05848b6e MW |
10274 | asc_sg_head = kzalloc(sizeof(asc_scsi_q->sg_head) + |
10275 | use_sg * sizeof(struct asc_sg_list), GFP_ATOMIC); | |
10276 | if (!asc_sg_head) { | |
10277 | dma_unmap_sg(boardp->dev, slp, scp->use_sg, | |
10278 | scp->sc_data_direction); | |
10279 | scp->result = HOST_BYTE(DID_SOFT_ERROR); | |
10280 | return ASC_ERROR; | |
10281 | } | |
51219358 | 10282 | |
05848b6e MW |
10283 | asc_scsi_q->q1.cntl |= QC_SG_HEAD; |
10284 | asc_scsi_q->sg_head = asc_sg_head; | |
10285 | asc_scsi_q->q1.data_cnt = 0; | |
10286 | asc_scsi_q->q1.data_addr = 0; | |
51219358 | 10287 | /* This is a byte value, otherwise it would need to be swapped. */ |
05848b6e | 10288 | asc_sg_head->entry_cnt = asc_scsi_q->q1.sg_queue_cnt = use_sg; |
51219358 | 10289 | ASC_STATS_ADD(scp->device->host, sg_elem, |
05848b6e | 10290 | asc_sg_head->entry_cnt); |
51219358 MW |
10291 | |
10292 | /* | |
10293 | * Convert scatter-gather list into ASC_SG_HEAD list. | |
10294 | */ | |
10295 | for (sgcnt = 0; sgcnt < use_sg; sgcnt++, slp++) { | |
05848b6e | 10296 | asc_sg_head->sg_list[sgcnt].addr = |
51219358 | 10297 | cpu_to_le32(sg_dma_address(slp)); |
05848b6e | 10298 | asc_sg_head->sg_list[sgcnt].bytes = |
51219358 MW |
10299 | cpu_to_le32(sg_dma_len(slp)); |
10300 | ASC_STATS_ADD(scp->device->host, sg_xfer, | |
10301 | ASC_CEILING(sg_dma_len(slp), 512)); | |
27c868c2 MW |
10302 | } |
10303 | } | |
1da177e4 | 10304 | |
51219358 MW |
10305 | ASC_DBG_PRT_ASC_SCSI_Q(2, &asc_scsi_q); |
10306 | ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len); | |
10307 | ||
10308 | return ASC_NOERROR; | |
27c868c2 | 10309 | } |
1da177e4 | 10310 | |
27c868c2 | 10311 | /* |
51219358 | 10312 | * Build scatter-gather list for Adv Library (Wide Board). |
27c868c2 | 10313 | * |
51219358 MW |
10314 | * Additional ADV_SG_BLOCK structures will need to be allocated |
10315 | * if the total number of scatter-gather elements exceeds | |
10316 | * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are | |
10317 | * assumed to be physically contiguous. | |
27c868c2 | 10318 | * |
51219358 MW |
10319 | * Return: |
10320 | * ADV_SUCCESS(1) - SG List successfully created | |
10321 | * ADV_ERROR(-1) - SG List creation failed | |
27c868c2 | 10322 | */ |
51219358 MW |
10323 | static int |
10324 | adv_get_sglist(asc_board_t *boardp, adv_req_t *reqp, struct scsi_cmnd *scp, | |
10325 | int use_sg) | |
27c868c2 | 10326 | { |
51219358 MW |
10327 | adv_sgblk_t *sgblkp; |
10328 | ADV_SCSI_REQ_Q *scsiqp; | |
10329 | struct scatterlist *slp; | |
10330 | int sg_elem_cnt; | |
10331 | ADV_SG_BLOCK *sg_block, *prev_sg_block; | |
10332 | ADV_PADDR sg_block_paddr; | |
27c868c2 | 10333 | int i; |
27c868c2 | 10334 | |
51219358 MW |
10335 | scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q); |
10336 | slp = (struct scatterlist *)scp->request_buffer; | |
10337 | sg_elem_cnt = use_sg; | |
10338 | prev_sg_block = NULL; | |
10339 | reqp->sgblkp = NULL; | |
1da177e4 | 10340 | |
51219358 MW |
10341 | for (;;) { |
10342 | /* | |
10343 | * Allocate a 'adv_sgblk_t' structure from the board free | |
10344 | * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK | |
10345 | * (15) scatter-gather elements. | |
10346 | */ | |
10347 | if ((sgblkp = boardp->adv_sgblkp) == NULL) { | |
10348 | ASC_DBG(1, "adv_get_sglist: no free adv_sgblk_t\n"); | |
10349 | ASC_STATS(scp->device->host, adv_build_nosg); | |
1da177e4 | 10350 | |
51219358 MW |
10351 | /* |
10352 | * Allocation failed. Free 'adv_sgblk_t' structures | |
10353 | * already allocated for the request. | |
10354 | */ | |
10355 | while ((sgblkp = reqp->sgblkp) != NULL) { | |
10356 | /* Remove 'sgblkp' from the request list. */ | |
10357 | reqp->sgblkp = sgblkp->next_sgblkp; | |
27c868c2 | 10358 | |
51219358 MW |
10359 | /* Add 'sgblkp' to the board free list. */ |
10360 | sgblkp->next_sgblkp = boardp->adv_sgblkp; | |
10361 | boardp->adv_sgblkp = sgblkp; | |
10362 | } | |
10363 | return ASC_BUSY; | |
10364 | } | |
1da177e4 | 10365 | |
51219358 MW |
10366 | /* Complete 'adv_sgblk_t' board allocation. */ |
10367 | boardp->adv_sgblkp = sgblkp->next_sgblkp; | |
10368 | sgblkp->next_sgblkp = NULL; | |
1da177e4 | 10369 | |
51219358 MW |
10370 | /* |
10371 | * Get 8 byte aligned virtual and physical addresses | |
10372 | * for the allocated ADV_SG_BLOCK structure. | |
10373 | */ | |
10374 | sg_block = (ADV_SG_BLOCK *)ADV_8BALIGN(&sgblkp->sg_block); | |
10375 | sg_block_paddr = virt_to_bus(sg_block); | |
27c868c2 | 10376 | |
51219358 MW |
10377 | /* |
10378 | * Check if this is the first 'adv_sgblk_t' for the | |
10379 | * request. | |
10380 | */ | |
10381 | if (reqp->sgblkp == NULL) { | |
10382 | /* Request's first scatter-gather block. */ | |
10383 | reqp->sgblkp = sgblkp; | |
27c868c2 | 10384 | |
51219358 MW |
10385 | /* |
10386 | * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical | |
10387 | * address pointers. | |
10388 | */ | |
10389 | scsiqp->sg_list_ptr = sg_block; | |
10390 | scsiqp->sg_real_addr = cpu_to_le32(sg_block_paddr); | |
10391 | } else { | |
10392 | /* Request's second or later scatter-gather block. */ | |
10393 | sgblkp->next_sgblkp = reqp->sgblkp; | |
10394 | reqp->sgblkp = sgblkp; | |
10395 | ||
10396 | /* | |
10397 | * Point the previous ADV_SG_BLOCK structure to | |
10398 | * the newly allocated ADV_SG_BLOCK structure. | |
10399 | */ | |
10400 | prev_sg_block->sg_ptr = cpu_to_le32(sg_block_paddr); | |
27c868c2 | 10401 | } |
1da177e4 | 10402 | |
51219358 MW |
10403 | for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) { |
10404 | sg_block->sg_list[i].sg_addr = | |
10405 | cpu_to_le32(sg_dma_address(slp)); | |
10406 | sg_block->sg_list[i].sg_count = | |
10407 | cpu_to_le32(sg_dma_len(slp)); | |
10408 | ASC_STATS_ADD(scp->device->host, sg_xfer, | |
10409 | ASC_CEILING(sg_dma_len(slp), 512)); | |
27c868c2 | 10410 | |
51219358 MW |
10411 | if (--sg_elem_cnt == 0) { /* Last ADV_SG_BLOCK and scatter-gather entry. */ |
10412 | sg_block->sg_cnt = i + 1; | |
10413 | sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */ | |
10414 | return ADV_SUCCESS; | |
10415 | } | |
10416 | slp++; | |
10417 | } | |
10418 | sg_block->sg_cnt = NO_OF_SG_PER_BLOCK; | |
10419 | prev_sg_block = sg_block; | |
27c868c2 | 10420 | } |
51219358 | 10421 | } |
1da177e4 | 10422 | |
51219358 MW |
10423 | /* |
10424 | * Build a request structure for the Adv Library (Wide Board). | |
10425 | * | |
10426 | * If an adv_req_t can not be allocated to issue the request, | |
10427 | * then return ASC_BUSY. If an error occurs, then return ASC_ERROR. | |
10428 | * | |
10429 | * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the | |
10430 | * microcode for DMA addresses or math operations are byte swapped | |
10431 | * to little-endian order. | |
10432 | */ | |
10433 | static int | |
10434 | adv_build_req(asc_board_t *boardp, struct scsi_cmnd *scp, | |
10435 | ADV_SCSI_REQ_Q **adv_scsiqpp) | |
10436 | { | |
10437 | adv_req_t *reqp; | |
10438 | ADV_SCSI_REQ_Q *scsiqp; | |
10439 | int i; | |
10440 | int ret; | |
1da177e4 | 10441 | |
27c868c2 | 10442 | /* |
51219358 MW |
10443 | * Allocate an adv_req_t structure from the board to execute |
10444 | * the command. | |
27c868c2 | 10445 | */ |
51219358 MW |
10446 | if (boardp->adv_reqp == NULL) { |
10447 | ASC_DBG(1, "adv_build_req: no free adv_req_t\n"); | |
10448 | ASC_STATS(scp->device->host, adv_build_noreq); | |
10449 | return ASC_BUSY; | |
10450 | } else { | |
10451 | reqp = boardp->adv_reqp; | |
10452 | boardp->adv_reqp = reqp->next_reqp; | |
10453 | reqp->next_reqp = NULL; | |
27c868c2 | 10454 | } |
1da177e4 | 10455 | |
27c868c2 | 10456 | /* |
51219358 | 10457 | * Get 32-byte aligned ADV_SCSI_REQ_Q and ADV_SG_BLOCK pointers. |
27c868c2 | 10458 | */ |
51219358 | 10459 | scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q); |
27c868c2 MW |
10460 | |
10461 | /* | |
51219358 | 10462 | * Initialize the structure. |
27c868c2 | 10463 | */ |
51219358 | 10464 | scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0; |
27c868c2 MW |
10465 | |
10466 | /* | |
51219358 | 10467 | * Set the ADV_SCSI_REQ_Q 'srb_ptr' to point to the adv_req_t structure. |
27c868c2 | 10468 | */ |
51219358 | 10469 | scsiqp->srb_ptr = ASC_VADDR_TO_U32(reqp); |
27c868c2 MW |
10470 | |
10471 | /* | |
51219358 | 10472 | * Set the adv_req_t 'cmndp' to point to the struct scsi_cmnd structure. |
27c868c2 | 10473 | */ |
51219358 | 10474 | reqp->cmndp = scp; |
27c868c2 MW |
10475 | |
10476 | /* | |
51219358 | 10477 | * Build the ADV_SCSI_REQ_Q request. |
27c868c2 | 10478 | */ |
51219358 MW |
10479 | |
10480 | /* Set CDB length and copy it to the request structure. */ | |
10481 | scsiqp->cdb_len = scp->cmd_len; | |
10482 | /* Copy first 12 CDB bytes to cdb[]. */ | |
10483 | for (i = 0; i < scp->cmd_len && i < 12; i++) { | |
10484 | scsiqp->cdb[i] = scp->cmnd[i]; | |
10485 | } | |
10486 | /* Copy last 4 CDB bytes, if present, to cdb16[]. */ | |
10487 | for (; i < scp->cmd_len; i++) { | |
10488 | scsiqp->cdb16[i - 12] = scp->cmnd[i]; | |
27c868c2 | 10489 | } |
1da177e4 | 10490 | |
51219358 MW |
10491 | scsiqp->target_id = scp->device->id; |
10492 | scsiqp->target_lun = scp->device->lun; | |
10493 | ||
10494 | scsiqp->sense_addr = cpu_to_le32(virt_to_bus(&scp->sense_buffer[0])); | |
10495 | scsiqp->sense_len = sizeof(scp->sense_buffer); | |
27c868c2 MW |
10496 | |
10497 | /* | |
51219358 MW |
10498 | * Build ADV_SCSI_REQ_Q for a contiguous buffer or a scatter-gather |
10499 | * buffer command. | |
27c868c2 | 10500 | */ |
51219358 MW |
10501 | |
10502 | scsiqp->data_cnt = cpu_to_le32(scp->request_bufflen); | |
10503 | scsiqp->vdata_addr = scp->request_buffer; | |
10504 | scsiqp->data_addr = cpu_to_le32(virt_to_bus(scp->request_buffer)); | |
10505 | ||
10506 | if (scp->use_sg == 0) { | |
10507 | /* | |
10508 | * CDB request of single contiguous buffer. | |
10509 | */ | |
10510 | reqp->sgblkp = NULL; | |
10511 | scsiqp->data_cnt = cpu_to_le32(scp->request_bufflen); | |
10512 | if (scp->request_bufflen) { | |
10513 | scsiqp->vdata_addr = scp->request_buffer; | |
10514 | scp->SCp.dma_handle = | |
10515 | dma_map_single(boardp->dev, scp->request_buffer, | |
10516 | scp->request_bufflen, | |
10517 | scp->sc_data_direction); | |
10518 | } else { | |
10519 | scsiqp->vdata_addr = NULL; | |
10520 | scp->SCp.dma_handle = 0; | |
10521 | } | |
10522 | scsiqp->data_addr = cpu_to_le32(scp->SCp.dma_handle); | |
10523 | scsiqp->sg_list_ptr = NULL; | |
10524 | scsiqp->sg_real_addr = 0; | |
10525 | ASC_STATS(scp->device->host, cont_cnt); | |
10526 | ASC_STATS_ADD(scp->device->host, cont_xfer, | |
10527 | ASC_CEILING(scp->request_bufflen, 512)); | |
10528 | } else { | |
10529 | /* | |
10530 | * CDB scatter-gather request list. | |
10531 | */ | |
10532 | struct scatterlist *slp; | |
10533 | int use_sg; | |
10534 | ||
10535 | slp = (struct scatterlist *)scp->request_buffer; | |
10536 | use_sg = dma_map_sg(boardp->dev, slp, scp->use_sg, | |
10537 | scp->sc_data_direction); | |
10538 | ||
10539 | if (use_sg > ADV_MAX_SG_LIST) { | |
10540 | ASC_PRINT3("adv_build_req: board %d: use_sg %d > " | |
10541 | "ADV_MAX_SG_LIST %d\n", boardp->id, use_sg, | |
10542 | scp->device->host->sg_tablesize); | |
10543 | dma_unmap_sg(boardp->dev, slp, scp->use_sg, | |
10544 | scp->sc_data_direction); | |
10545 | scp->result = HOST_BYTE(DID_ERROR); | |
10546 | ||
10547 | /* | |
10548 | * Free the 'adv_req_t' structure by adding it back | |
10549 | * to the board free list. | |
10550 | */ | |
10551 | reqp->next_reqp = boardp->adv_reqp; | |
10552 | boardp->adv_reqp = reqp; | |
10553 | ||
10554 | return ASC_ERROR; | |
10555 | } | |
10556 | ||
10557 | ret = adv_get_sglist(boardp, reqp, scp, use_sg); | |
10558 | if (ret != ADV_SUCCESS) { | |
10559 | /* | |
10560 | * Free the adv_req_t structure by adding it back to | |
10561 | * the board free list. | |
10562 | */ | |
10563 | reqp->next_reqp = boardp->adv_reqp; | |
10564 | boardp->adv_reqp = reqp; | |
10565 | ||
10566 | return ret; | |
10567 | } | |
10568 | ||
10569 | ASC_STATS(scp->device->host, sg_cnt); | |
10570 | ASC_STATS_ADD(scp->device->host, sg_elem, use_sg); | |
27c868c2 | 10571 | } |
1da177e4 | 10572 | |
51219358 MW |
10573 | ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp); |
10574 | ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len); | |
27c868c2 | 10575 | |
51219358 | 10576 | *adv_scsiqpp = scsiqp; |
27c868c2 | 10577 | |
51219358 MW |
10578 | return ASC_NOERROR; |
10579 | } | |
10580 | ||
10581 | static int AscSgListToQueue(int sg_list) | |
10582 | { | |
10583 | int n_sg_list_qs; | |
10584 | ||
10585 | n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q); | |
10586 | if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0) | |
10587 | n_sg_list_qs++; | |
10588 | return n_sg_list_qs + 1; | |
10589 | } | |
10590 | ||
10591 | static uint | |
10592 | AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs) | |
10593 | { | |
10594 | uint cur_used_qs; | |
10595 | uint cur_free_qs; | |
10596 | ASC_SCSI_BIT_ID_TYPE target_id; | |
10597 | uchar tid_no; | |
10598 | ||
10599 | target_id = ASC_TIX_TO_TARGET_ID(target_ix); | |
10600 | tid_no = ASC_TIX_TO_TID(target_ix); | |
10601 | if ((asc_dvc->unit_not_ready & target_id) || | |
10602 | (asc_dvc->queue_full_or_busy & target_id)) { | |
10603 | return 0; | |
10604 | } | |
10605 | if (n_qs == 1) { | |
10606 | cur_used_qs = (uint) asc_dvc->cur_total_qng + | |
10607 | (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q; | |
10608 | } else { | |
10609 | cur_used_qs = (uint) asc_dvc->cur_total_qng + | |
10610 | (uint) ASC_MIN_FREE_Q; | |
10611 | } | |
10612 | if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) { | |
10613 | cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs; | |
10614 | if (asc_dvc->cur_dvc_qng[tid_no] >= | |
10615 | asc_dvc->max_dvc_qng[tid_no]) { | |
10616 | return 0; | |
10617 | } | |
10618 | return cur_free_qs; | |
10619 | } | |
10620 | if (n_qs > 1) { | |
10621 | if ((n_qs > asc_dvc->last_q_shortage) | |
10622 | && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) { | |
10623 | asc_dvc->last_q_shortage = n_qs; | |
10624 | } | |
10625 | } | |
10626 | return 0; | |
10627 | } | |
10628 | ||
10629 | static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head) | |
10630 | { | |
10631 | ushort q_addr; | |
10632 | uchar next_qp; | |
10633 | uchar q_status; | |
10634 | ||
10635 | q_addr = ASC_QNO_TO_QADDR(free_q_head); | |
10636 | q_status = (uchar)AscReadLramByte(iop_base, | |
10637 | (ushort)(q_addr + | |
10638 | ASC_SCSIQ_B_STATUS)); | |
10639 | next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD)); | |
10640 | if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END)) | |
10641 | return next_qp; | |
10642 | return ASC_QLINK_END; | |
10643 | } | |
10644 | ||
10645 | static uchar | |
10646 | AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q) | |
10647 | { | |
10648 | uchar i; | |
27c868c2 | 10649 | |
51219358 MW |
10650 | for (i = 0; i < n_free_q; i++) { |
10651 | free_q_head = AscAllocFreeQueue(iop_base, free_q_head); | |
10652 | if (free_q_head == ASC_QLINK_END) | |
10653 | break; | |
10654 | } | |
10655 | return free_q_head; | |
10656 | } | |
27c868c2 | 10657 | |
51219358 MW |
10658 | /* |
10659 | * void | |
10660 | * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words) | |
10661 | * | |
10662 | * Calling/Exit State: | |
10663 | * none | |
10664 | * | |
10665 | * Description: | |
10666 | * Output an ASC_SCSI_Q structure to the chip | |
10667 | */ | |
10668 | static void | |
10669 | DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words) | |
10670 | { | |
10671 | int i; | |
10672 | ||
10673 | ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words); | |
10674 | AscSetChipLramAddr(iop_base, s_addr); | |
10675 | for (i = 0; i < 2 * words; i += 2) { | |
10676 | if (i == 4 || i == 20) { | |
10677 | continue; | |
10678 | } | |
10679 | outpw(iop_base + IOP_RAM_DATA, | |
10680 | ((ushort)outbuf[i + 1] << 8) | outbuf[i]); | |
27c868c2 | 10681 | } |
51219358 | 10682 | } |
1da177e4 | 10683 | |
51219358 MW |
10684 | static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no) |
10685 | { | |
10686 | ushort q_addr; | |
10687 | uchar tid_no; | |
10688 | uchar sdtr_data; | |
10689 | uchar syn_period_ix; | |
10690 | uchar syn_offset; | |
10691 | PortAddr iop_base; | |
10692 | ||
10693 | iop_base = asc_dvc->iop_base; | |
10694 | if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) && | |
10695 | ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) { | |
10696 | tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix); | |
10697 | sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no); | |
10698 | syn_period_ix = | |
10699 | (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1); | |
10700 | syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET; | |
10701 | AscMsgOutSDTR(asc_dvc, | |
10702 | asc_dvc->sdtr_period_tbl[syn_period_ix], | |
10703 | syn_offset); | |
10704 | scsiq->q1.cntl |= QC_MSG_OUT; | |
10705 | } | |
10706 | q_addr = ASC_QNO_TO_QADDR(q_no); | |
10707 | if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) { | |
10708 | scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG; | |
27c868c2 | 10709 | } |
51219358 MW |
10710 | scsiq->q1.status = QS_FREE; |
10711 | AscMemWordCopyPtrToLram(iop_base, | |
10712 | q_addr + ASC_SCSIQ_CDB_BEG, | |
10713 | (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1); | |
10714 | ||
10715 | DvcPutScsiQ(iop_base, | |
10716 | q_addr + ASC_SCSIQ_CPY_BEG, | |
10717 | (uchar *)&scsiq->q1.cntl, | |
10718 | ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1); | |
10719 | AscWriteLramWord(iop_base, | |
10720 | (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS), | |
10721 | (ushort)(((ushort)scsiq->q1. | |
10722 | q_no << 8) | (ushort)QS_READY)); | |
10723 | return 1; | |
10724 | } | |
10725 | ||
10726 | static int | |
10727 | AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no) | |
10728 | { | |
10729 | int sta; | |
10730 | int i; | |
10731 | ASC_SG_HEAD *sg_head; | |
10732 | ASC_SG_LIST_Q scsi_sg_q; | |
10733 | ASC_DCNT saved_data_addr; | |
10734 | ASC_DCNT saved_data_cnt; | |
10735 | PortAddr iop_base; | |
10736 | ushort sg_list_dwords; | |
10737 | ushort sg_index; | |
10738 | ushort sg_entry_cnt; | |
10739 | ushort q_addr; | |
10740 | uchar next_qp; | |
1da177e4 | 10741 | |
51219358 MW |
10742 | iop_base = asc_dvc->iop_base; |
10743 | sg_head = scsiq->sg_head; | |
10744 | saved_data_addr = scsiq->q1.data_addr; | |
10745 | saved_data_cnt = scsiq->q1.data_cnt; | |
10746 | scsiq->q1.data_addr = (ASC_PADDR) sg_head->sg_list[0].addr; | |
10747 | scsiq->q1.data_cnt = (ASC_DCNT) sg_head->sg_list[0].bytes; | |
10748 | #if CC_VERY_LONG_SG_LIST | |
27c868c2 | 10749 | /* |
51219358 MW |
10750 | * If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST |
10751 | * then not all SG elements will fit in the allocated queues. | |
10752 | * The rest of the SG elements will be copied when the RISC | |
10753 | * completes the SG elements that fit and halts. | |
27c868c2 | 10754 | */ |
51219358 MW |
10755 | if (sg_head->entry_cnt > ASC_MAX_SG_LIST) { |
10756 | /* | |
10757 | * Set sg_entry_cnt to be the number of SG elements that | |
10758 | * will fit in the allocated SG queues. It is minus 1, because | |
10759 | * the first SG element is handled above. ASC_MAX_SG_LIST is | |
10760 | * already inflated by 1 to account for this. For example it | |
10761 | * may be 50 which is 1 + 7 queues * 7 SG elements. | |
10762 | */ | |
10763 | sg_entry_cnt = ASC_MAX_SG_LIST - 1; | |
27c868c2 | 10764 | |
51219358 MW |
10765 | /* |
10766 | * Keep track of remaining number of SG elements that will | |
10767 | * need to be handled from a_isr.c. | |
10768 | */ | |
10769 | scsiq->remain_sg_entry_cnt = | |
10770 | sg_head->entry_cnt - ASC_MAX_SG_LIST; | |
10771 | } else { | |
10772 | #endif /* CC_VERY_LONG_SG_LIST */ | |
10773 | /* | |
10774 | * Set sg_entry_cnt to be the number of SG elements that | |
10775 | * will fit in the allocated SG queues. It is minus 1, because | |
10776 | * the first SG element is handled above. | |
10777 | */ | |
10778 | sg_entry_cnt = sg_head->entry_cnt - 1; | |
10779 | #if CC_VERY_LONG_SG_LIST | |
10780 | } | |
10781 | #endif /* CC_VERY_LONG_SG_LIST */ | |
10782 | if (sg_entry_cnt != 0) { | |
10783 | scsiq->q1.cntl |= QC_SG_HEAD; | |
10784 | q_addr = ASC_QNO_TO_QADDR(q_no); | |
10785 | sg_index = 1; | |
10786 | scsiq->q1.sg_queue_cnt = sg_head->queue_cnt; | |
10787 | scsi_sg_q.sg_head_qp = q_no; | |
10788 | scsi_sg_q.cntl = QCSG_SG_XFER_LIST; | |
10789 | for (i = 0; i < sg_head->queue_cnt; i++) { | |
10790 | scsi_sg_q.seq_no = i + 1; | |
10791 | if (sg_entry_cnt > ASC_SG_LIST_PER_Q) { | |
10792 | sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2); | |
10793 | sg_entry_cnt -= ASC_SG_LIST_PER_Q; | |
10794 | if (i == 0) { | |
10795 | scsi_sg_q.sg_list_cnt = | |
10796 | ASC_SG_LIST_PER_Q; | |
10797 | scsi_sg_q.sg_cur_list_cnt = | |
10798 | ASC_SG_LIST_PER_Q; | |
10799 | } else { | |
10800 | scsi_sg_q.sg_list_cnt = | |
10801 | ASC_SG_LIST_PER_Q - 1; | |
10802 | scsi_sg_q.sg_cur_list_cnt = | |
10803 | ASC_SG_LIST_PER_Q - 1; | |
10804 | } | |
10805 | } else { | |
10806 | #if CC_VERY_LONG_SG_LIST | |
10807 | /* | |
10808 | * This is the last SG queue in the list of | |
10809 | * allocated SG queues. If there are more | |
10810 | * SG elements than will fit in the allocated | |
10811 | * queues, then set the QCSG_SG_XFER_MORE flag. | |
10812 | */ | |
10813 | if (sg_head->entry_cnt > ASC_MAX_SG_LIST) { | |
10814 | scsi_sg_q.cntl |= QCSG_SG_XFER_MORE; | |
10815 | } else { | |
10816 | #endif /* CC_VERY_LONG_SG_LIST */ | |
10817 | scsi_sg_q.cntl |= QCSG_SG_XFER_END; | |
10818 | #if CC_VERY_LONG_SG_LIST | |
10819 | } | |
10820 | #endif /* CC_VERY_LONG_SG_LIST */ | |
10821 | sg_list_dwords = sg_entry_cnt << 1; | |
10822 | if (i == 0) { | |
10823 | scsi_sg_q.sg_list_cnt = sg_entry_cnt; | |
10824 | scsi_sg_q.sg_cur_list_cnt = | |
10825 | sg_entry_cnt; | |
10826 | } else { | |
10827 | scsi_sg_q.sg_list_cnt = | |
10828 | sg_entry_cnt - 1; | |
10829 | scsi_sg_q.sg_cur_list_cnt = | |
10830 | sg_entry_cnt - 1; | |
10831 | } | |
10832 | sg_entry_cnt = 0; | |
10833 | } | |
10834 | next_qp = AscReadLramByte(iop_base, | |
10835 | (ushort)(q_addr + | |
10836 | ASC_SCSIQ_B_FWD)); | |
10837 | scsi_sg_q.q_no = next_qp; | |
10838 | q_addr = ASC_QNO_TO_QADDR(next_qp); | |
10839 | AscMemWordCopyPtrToLram(iop_base, | |
10840 | q_addr + ASC_SCSIQ_SGHD_CPY_BEG, | |
10841 | (uchar *)&scsi_sg_q, | |
10842 | sizeof(ASC_SG_LIST_Q) >> 1); | |
10843 | AscMemDWordCopyPtrToLram(iop_base, | |
10844 | q_addr + ASC_SGQ_LIST_BEG, | |
10845 | (uchar *)&sg_head-> | |
10846 | sg_list[sg_index], | |
10847 | sg_list_dwords); | |
10848 | sg_index += ASC_SG_LIST_PER_Q; | |
10849 | scsiq->next_sg_index = sg_index; | |
27c868c2 | 10850 | } |
51219358 MW |
10851 | } else { |
10852 | scsiq->q1.cntl &= ~QC_SG_HEAD; | |
27c868c2 | 10853 | } |
51219358 MW |
10854 | sta = AscPutReadyQueue(asc_dvc, scsiq, q_no); |
10855 | scsiq->q1.data_addr = saved_data_addr; | |
10856 | scsiq->q1.data_cnt = saved_data_cnt; | |
10857 | return (sta); | |
10858 | } | |
27c868c2 | 10859 | |
51219358 MW |
10860 | static int |
10861 | AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required) | |
10862 | { | |
10863 | PortAddr iop_base; | |
10864 | uchar free_q_head; | |
10865 | uchar next_qp; | |
10866 | uchar tid_no; | |
10867 | uchar target_ix; | |
10868 | int sta; | |
27c868c2 | 10869 | |
51219358 MW |
10870 | iop_base = asc_dvc->iop_base; |
10871 | target_ix = scsiq->q2.target_ix; | |
10872 | tid_no = ASC_TIX_TO_TID(target_ix); | |
10873 | sta = 0; | |
10874 | free_q_head = (uchar)AscGetVarFreeQHead(iop_base); | |
10875 | if (n_q_required > 1) { | |
10876 | next_qp = AscAllocMultipleFreeQueue(iop_base, free_q_head, | |
10877 | (uchar)n_q_required); | |
10878 | if (next_qp != ASC_QLINK_END) { | |
10879 | asc_dvc->last_q_shortage = 0; | |
10880 | scsiq->sg_head->queue_cnt = n_q_required - 1; | |
10881 | scsiq->q1.q_no = free_q_head; | |
10882 | sta = AscPutReadySgListQueue(asc_dvc, scsiq, | |
10883 | free_q_head); | |
10884 | } | |
10885 | } else if (n_q_required == 1) { | |
10886 | next_qp = AscAllocFreeQueue(iop_base, free_q_head); | |
10887 | if (next_qp != ASC_QLINK_END) { | |
10888 | scsiq->q1.q_no = free_q_head; | |
10889 | sta = AscPutReadyQueue(asc_dvc, scsiq, free_q_head); | |
27c868c2 MW |
10890 | } |
10891 | } | |
51219358 MW |
10892 | if (sta == 1) { |
10893 | AscPutVarFreeQHead(iop_base, next_qp); | |
10894 | asc_dvc->cur_total_qng += n_q_required; | |
10895 | asc_dvc->cur_dvc_qng[tid_no]++; | |
27c868c2 | 10896 | } |
51219358 MW |
10897 | return sta; |
10898 | } | |
27c868c2 | 10899 | |
51219358 MW |
10900 | #define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16 |
10901 | static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = { | |
10902 | INQUIRY, | |
10903 | REQUEST_SENSE, | |
10904 | READ_CAPACITY, | |
10905 | READ_TOC, | |
10906 | MODE_SELECT, | |
10907 | MODE_SENSE, | |
10908 | MODE_SELECT_10, | |
10909 | MODE_SENSE_10, | |
10910 | 0xFF, | |
10911 | 0xFF, | |
10912 | 0xFF, | |
10913 | 0xFF, | |
10914 | 0xFF, | |
10915 | 0xFF, | |
10916 | 0xFF, | |
10917 | 0xFF | |
10918 | }; | |
27c868c2 | 10919 | |
51219358 MW |
10920 | static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq) |
10921 | { | |
10922 | PortAddr iop_base; | |
10923 | int sta; | |
10924 | int n_q_required; | |
10925 | int disable_syn_offset_one_fix; | |
10926 | int i; | |
10927 | ASC_PADDR addr; | |
10928 | ushort sg_entry_cnt = 0; | |
10929 | ushort sg_entry_cnt_minus_one = 0; | |
10930 | uchar target_ix; | |
10931 | uchar tid_no; | |
10932 | uchar sdtr_data; | |
10933 | uchar extra_bytes; | |
10934 | uchar scsi_cmd; | |
10935 | uchar disable_cmd; | |
10936 | ASC_SG_HEAD *sg_head; | |
10937 | ASC_DCNT data_cnt; | |
27c868c2 | 10938 | |
51219358 MW |
10939 | iop_base = asc_dvc->iop_base; |
10940 | sg_head = scsiq->sg_head; | |
10941 | if (asc_dvc->err_code != 0) | |
10942 | return (ERR); | |
10943 | scsiq->q1.q_no = 0; | |
10944 | if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) { | |
10945 | scsiq->q1.extra_bytes = 0; | |
27c868c2 | 10946 | } |
51219358 MW |
10947 | sta = 0; |
10948 | target_ix = scsiq->q2.target_ix; | |
10949 | tid_no = ASC_TIX_TO_TID(target_ix); | |
10950 | n_q_required = 1; | |
10951 | if (scsiq->cdbptr[0] == REQUEST_SENSE) { | |
10952 | if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) { | |
10953 | asc_dvc->sdtr_done &= ~scsiq->q1.target_id; | |
10954 | sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no); | |
10955 | AscMsgOutSDTR(asc_dvc, | |
10956 | asc_dvc-> | |
10957 | sdtr_period_tbl[(sdtr_data >> 4) & | |
10958 | (uchar)(asc_dvc-> | |
10959 | max_sdtr_index - | |
10960 | 1)], | |
10961 | (uchar)(sdtr_data & (uchar) | |
10962 | ASC_SYN_MAX_OFFSET)); | |
10963 | scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT); | |
10964 | } | |
10965 | } | |
10966 | if (asc_dvc->in_critical_cnt != 0) { | |
10967 | AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY); | |
10968 | return (ERR); | |
10969 | } | |
10970 | asc_dvc->in_critical_cnt++; | |
10971 | if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) { | |
10972 | if ((sg_entry_cnt = sg_head->entry_cnt) == 0) { | |
10973 | asc_dvc->in_critical_cnt--; | |
10974 | return (ERR); | |
10975 | } | |
10976 | #if !CC_VERY_LONG_SG_LIST | |
10977 | if (sg_entry_cnt > ASC_MAX_SG_LIST) { | |
10978 | asc_dvc->in_critical_cnt--; | |
10979 | return (ERR); | |
10980 | } | |
10981 | #endif /* !CC_VERY_LONG_SG_LIST */ | |
10982 | if (sg_entry_cnt == 1) { | |
10983 | scsiq->q1.data_addr = | |
10984 | (ADV_PADDR)sg_head->sg_list[0].addr; | |
10985 | scsiq->q1.data_cnt = | |
10986 | (ADV_DCNT)sg_head->sg_list[0].bytes; | |
10987 | scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE); | |
10988 | } | |
10989 | sg_entry_cnt_minus_one = sg_entry_cnt - 1; | |
10990 | } | |
10991 | scsi_cmd = scsiq->cdbptr[0]; | |
10992 | disable_syn_offset_one_fix = FALSE; | |
10993 | if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) && | |
10994 | !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) { | |
10995 | if (scsiq->q1.cntl & QC_SG_HEAD) { | |
10996 | data_cnt = 0; | |
10997 | for (i = 0; i < sg_entry_cnt; i++) { | |
10998 | data_cnt += | |
10999 | (ADV_DCNT)le32_to_cpu(sg_head->sg_list[i]. | |
11000 | bytes); | |
11001 | } | |
11002 | } else { | |
11003 | data_cnt = le32_to_cpu(scsiq->q1.data_cnt); | |
11004 | } | |
11005 | if (data_cnt != 0UL) { | |
11006 | if (data_cnt < 512UL) { | |
11007 | disable_syn_offset_one_fix = TRUE; | |
11008 | } else { | |
11009 | for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST; | |
11010 | i++) { | |
11011 | disable_cmd = | |
11012 | _syn_offset_one_disable_cmd[i]; | |
11013 | if (disable_cmd == 0xFF) { | |
11014 | break; | |
11015 | } | |
11016 | if (scsi_cmd == disable_cmd) { | |
11017 | disable_syn_offset_one_fix = | |
11018 | TRUE; | |
11019 | break; | |
11020 | } | |
11021 | } | |
11022 | } | |
11023 | } | |
11024 | } | |
11025 | if (disable_syn_offset_one_fix) { | |
11026 | scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG; | |
11027 | scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX | | |
11028 | ASC_TAG_FLAG_DISABLE_DISCONNECT); | |
11029 | } else { | |
11030 | scsiq->q2.tag_code &= 0x27; | |
11031 | } | |
11032 | if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) { | |
11033 | if (asc_dvc->bug_fix_cntl) { | |
11034 | if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { | |
11035 | if ((scsi_cmd == READ_6) || | |
11036 | (scsi_cmd == READ_10)) { | |
11037 | addr = | |
11038 | (ADV_PADDR)le32_to_cpu(sg_head-> | |
11039 | sg_list | |
11040 | [sg_entry_cnt_minus_one]. | |
11041 | addr) + | |
11042 | (ADV_DCNT)le32_to_cpu(sg_head-> | |
11043 | sg_list | |
11044 | [sg_entry_cnt_minus_one]. | |
11045 | bytes); | |
11046 | extra_bytes = | |
11047 | (uchar)((ushort)addr & 0x0003); | |
11048 | if ((extra_bytes != 0) | |
11049 | && | |
11050 | ((scsiq->q2. | |
11051 | tag_code & | |
11052 | ASC_TAG_FLAG_EXTRA_BYTES) | |
11053 | == 0)) { | |
11054 | scsiq->q2.tag_code |= | |
11055 | ASC_TAG_FLAG_EXTRA_BYTES; | |
11056 | scsiq->q1.extra_bytes = | |
11057 | extra_bytes; | |
11058 | data_cnt = | |
11059 | le32_to_cpu(sg_head-> | |
11060 | sg_list | |
11061 | [sg_entry_cnt_minus_one]. | |
11062 | bytes); | |
11063 | data_cnt -= | |
11064 | (ASC_DCNT) extra_bytes; | |
11065 | sg_head-> | |
11066 | sg_list | |
11067 | [sg_entry_cnt_minus_one]. | |
11068 | bytes = | |
11069 | cpu_to_le32(data_cnt); | |
11070 | } | |
11071 | } | |
11072 | } | |
11073 | } | |
11074 | sg_head->entry_to_copy = sg_head->entry_cnt; | |
11075 | #if CC_VERY_LONG_SG_LIST | |
27c868c2 | 11076 | /* |
51219358 MW |
11077 | * Set the sg_entry_cnt to the maximum possible. The rest of |
11078 | * the SG elements will be copied when the RISC completes the | |
11079 | * SG elements that fit and halts. | |
27c868c2 | 11080 | */ |
51219358 MW |
11081 | if (sg_entry_cnt > ASC_MAX_SG_LIST) { |
11082 | sg_entry_cnt = ASC_MAX_SG_LIST; | |
11083 | } | |
11084 | #endif /* CC_VERY_LONG_SG_LIST */ | |
11085 | n_q_required = AscSgListToQueue(sg_entry_cnt); | |
11086 | if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >= | |
11087 | (uint) n_q_required) | |
11088 | || ((scsiq->q1.cntl & QC_URGENT) != 0)) { | |
11089 | if ((sta = | |
11090 | AscSendScsiQueue(asc_dvc, scsiq, | |
11091 | n_q_required)) == 1) { | |
11092 | asc_dvc->in_critical_cnt--; | |
11093 | return (sta); | |
27c868c2 | 11094 | } |
51219358 MW |
11095 | } |
11096 | } else { | |
11097 | if (asc_dvc->bug_fix_cntl) { | |
11098 | if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { | |
11099 | if ((scsi_cmd == READ_6) || | |
11100 | (scsi_cmd == READ_10)) { | |
11101 | addr = | |
11102 | le32_to_cpu(scsiq->q1.data_addr) + | |
11103 | le32_to_cpu(scsiq->q1.data_cnt); | |
11104 | extra_bytes = | |
11105 | (uchar)((ushort)addr & 0x0003); | |
11106 | if ((extra_bytes != 0) | |
11107 | && | |
11108 | ((scsiq->q2. | |
11109 | tag_code & | |
11110 | ASC_TAG_FLAG_EXTRA_BYTES) | |
11111 | == 0)) { | |
11112 | data_cnt = | |
11113 | le32_to_cpu(scsiq->q1. | |
11114 | data_cnt); | |
11115 | if (((ushort)data_cnt & 0x01FF) | |
11116 | == 0) { | |
11117 | scsiq->q2.tag_code |= | |
11118 | ASC_TAG_FLAG_EXTRA_BYTES; | |
11119 | data_cnt -= (ASC_DCNT) | |
11120 | extra_bytes; | |
11121 | scsiq->q1.data_cnt = | |
11122 | cpu_to_le32 | |
11123 | (data_cnt); | |
11124 | scsiq->q1.extra_bytes = | |
11125 | extra_bytes; | |
11126 | } | |
11127 | } | |
11128 | } | |
11129 | } | |
11130 | } | |
11131 | n_q_required = 1; | |
11132 | if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) || | |
11133 | ((scsiq->q1.cntl & QC_URGENT) != 0)) { | |
11134 | if ((sta = AscSendScsiQueue(asc_dvc, scsiq, | |
11135 | n_q_required)) == 1) { | |
11136 | asc_dvc->in_critical_cnt--; | |
11137 | return (sta); | |
27c868c2 MW |
11138 | } |
11139 | } | |
11140 | } | |
51219358 MW |
11141 | asc_dvc->in_critical_cnt--; |
11142 | return (sta); | |
1da177e4 LT |
11143 | } |
11144 | ||
11145 | /* | |
51219358 | 11146 | * AdvExeScsiQueue() - Send a request to the RISC microcode program. |
1da177e4 | 11147 | * |
51219358 MW |
11148 | * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q, |
11149 | * add the carrier to the ICQ (Initiator Command Queue), and tickle the | |
11150 | * RISC to notify it a new command is ready to be executed. | |
11151 | * | |
11152 | * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be | |
11153 | * set to SCSI_MAX_RETRY. | |
11154 | * | |
11155 | * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode | |
11156 | * for DMA addresses or math operations are byte swapped to little-endian | |
11157 | * order. | |
11158 | * | |
11159 | * Return: | |
11160 | * ADV_SUCCESS(1) - The request was successfully queued. | |
11161 | * ADV_BUSY(0) - Resource unavailable; Retry again after pending | |
11162 | * request completes. | |
11163 | * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure | |
11164 | * host IC error. | |
11165 | */ | |
11166 | static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq) | |
11167 | { | |
11168 | AdvPortAddr iop_base; | |
11169 | ADV_DCNT req_size; | |
11170 | ADV_PADDR req_paddr; | |
11171 | ADV_CARR_T *new_carrp; | |
1da177e4 | 11172 | |
27c868c2 | 11173 | /* |
51219358 | 11174 | * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID. |
27c868c2 | 11175 | */ |
51219358 MW |
11176 | if (scsiq->target_id > ADV_MAX_TID) { |
11177 | scsiq->host_status = QHSTA_M_INVALID_DEVICE; | |
11178 | scsiq->done_status = QD_WITH_ERROR; | |
27c868c2 MW |
11179 | return ADV_ERROR; |
11180 | } | |
1da177e4 | 11181 | |
51219358 | 11182 | iop_base = asc_dvc->iop_base; |
1da177e4 | 11183 | |
27c868c2 | 11184 | /* |
51219358 MW |
11185 | * Allocate a carrier ensuring at least one carrier always |
11186 | * remains on the freelist and initialize fields. | |
27c868c2 | 11187 | */ |
51219358 MW |
11188 | if ((new_carrp = asc_dvc->carr_freelist) == NULL) { |
11189 | return ADV_BUSY; | |
27c868c2 | 11190 | } |
51219358 MW |
11191 | asc_dvc->carr_freelist = (ADV_CARR_T *) |
11192 | ADV_U32_TO_VADDR(le32_to_cpu(new_carrp->next_vpa)); | |
11193 | asc_dvc->carr_pending_cnt++; | |
1da177e4 | 11194 | |
27c868c2 | 11195 | /* |
51219358 MW |
11196 | * Set the carrier to be a stopper by setting 'next_vpa' |
11197 | * to the stopper value. The current stopper will be changed | |
11198 | * below to point to the new stopper. | |
27c868c2 | 11199 | */ |
51219358 | 11200 | new_carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER); |
27c868c2 MW |
11201 | |
11202 | /* | |
51219358 | 11203 | * Clear the ADV_SCSI_REQ_Q done flag. |
27c868c2 | 11204 | */ |
51219358 | 11205 | scsiq->a_flag &= ~ADV_SCSIQ_DONE; |
27c868c2 | 11206 | |
51219358 MW |
11207 | req_size = sizeof(ADV_SCSI_REQ_Q); |
11208 | req_paddr = DvcGetPhyAddr(asc_dvc, scsiq, (uchar *)scsiq, | |
11209 | (ADV_SDCNT *)&req_size, ADV_IS_SCSIQ_FLAG); | |
27c868c2 | 11210 | |
51219358 MW |
11211 | BUG_ON(req_paddr & 31); |
11212 | BUG_ON(req_size < sizeof(ADV_SCSI_REQ_Q)); | |
11213 | ||
11214 | /* Wait for assertion before making little-endian */ | |
11215 | req_paddr = cpu_to_le32(req_paddr); | |
27c868c2 | 11216 | |
51219358 MW |
11217 | /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */ |
11218 | scsiq->scsiq_ptr = cpu_to_le32(ADV_VADDR_TO_U32(scsiq)); | |
11219 | scsiq->scsiq_rptr = req_paddr; | |
11220 | ||
11221 | scsiq->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->icq_sp)); | |
27c868c2 | 11222 | /* |
51219358 MW |
11223 | * Every ADV_CARR_T.carr_pa is byte swapped to little-endian |
11224 | * order during initialization. | |
27c868c2 | 11225 | */ |
51219358 | 11226 | scsiq->carr_pa = asc_dvc->icq_sp->carr_pa; |
1da177e4 | 11227 | |
27c868c2 | 11228 | /* |
51219358 MW |
11229 | * Use the current stopper to send the ADV_SCSI_REQ_Q command to |
11230 | * the microcode. The newly allocated stopper will become the new | |
11231 | * stopper. | |
27c868c2 | 11232 | */ |
51219358 | 11233 | asc_dvc->icq_sp->areq_vpa = req_paddr; |
1da177e4 | 11234 | |
27c868c2 | 11235 | /* |
51219358 MW |
11236 | * Set the 'next_vpa' pointer for the old stopper to be the |
11237 | * physical address of the new stopper. The RISC can only | |
11238 | * follow physical addresses. | |
27c868c2 | 11239 | */ |
51219358 | 11240 | asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa; |
27c868c2 MW |
11241 | |
11242 | /* | |
51219358 | 11243 | * Set the host adapter stopper pointer to point to the new carrier. |
27c868c2 | 11244 | */ |
51219358 MW |
11245 | asc_dvc->icq_sp = new_carrp; |
11246 | ||
11247 | if (asc_dvc->chip_type == ADV_CHIP_ASC3550 || | |
11248 | asc_dvc->chip_type == ADV_CHIP_ASC38C0800) { | |
11249 | /* | |
11250 | * Tickle the RISC to tell it to read its Command Queue Head pointer. | |
11251 | */ | |
11252 | AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A); | |
11253 | if (asc_dvc->chip_type == ADV_CHIP_ASC3550) { | |
11254 | /* | |
11255 | * Clear the tickle value. In the ASC-3550 the RISC flag | |
11256 | * command 'clr_tickle_a' does not work unless the host | |
11257 | * value is cleared. | |
11258 | */ | |
11259 | AdvWriteByteRegister(iop_base, IOPB_TICKLE, | |
11260 | ADV_TICKLE_NOP); | |
11261 | } | |
11262 | } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) { | |
11263 | /* | |
11264 | * Notify the RISC a carrier is ready by writing the physical | |
11265 | * address of the new carrier stopper to the COMMA register. | |
11266 | */ | |
11267 | AdvWriteDWordRegister(iop_base, IOPDW_COMMA, | |
11268 | le32_to_cpu(new_carrp->carr_pa)); | |
27c868c2 | 11269 | } |
1da177e4 | 11270 | |
51219358 MW |
11271 | return ADV_SUCCESS; |
11272 | } | |
11273 | ||
11274 | /* | |
11275 | * Execute a single 'Scsi_Cmnd'. | |
11276 | * | |
11277 | * The function 'done' is called when the request has been completed. | |
11278 | * | |
11279 | * Scsi_Cmnd: | |
11280 | * | |
11281 | * host - board controlling device | |
11282 | * device - device to send command | |
11283 | * target - target of device | |
11284 | * lun - lun of device | |
11285 | * cmd_len - length of SCSI CDB | |
11286 | * cmnd - buffer for SCSI 8, 10, or 12 byte CDB | |
11287 | * use_sg - if non-zero indicates scatter-gather request with use_sg elements | |
11288 | * | |
11289 | * if (use_sg == 0) { | |
11290 | * request_buffer - buffer address for request | |
11291 | * request_bufflen - length of request buffer | |
11292 | * } else { | |
11293 | * request_buffer - pointer to scatterlist structure | |
11294 | * } | |
11295 | * | |
11296 | * sense_buffer - sense command buffer | |
11297 | * | |
11298 | * result (4 bytes of an int): | |
11299 | * Byte Meaning | |
11300 | * 0 SCSI Status Byte Code | |
11301 | * 1 SCSI One Byte Message Code | |
11302 | * 2 Host Error Code | |
11303 | * 3 Mid-Level Error Code | |
11304 | * | |
11305 | * host driver fields: | |
11306 | * SCp - Scsi_Pointer used for command processing status | |
11307 | * scsi_done - used to save caller's done function | |
11308 | * host_scribble - used for pointer to another struct scsi_cmnd | |
11309 | * | |
11310 | * If this function returns ASC_NOERROR the request will be completed | |
11311 | * from the interrupt handler. | |
11312 | * | |
11313 | * If this function returns ASC_ERROR the host error code has been set, | |
11314 | * and the called must call asc_scsi_done. | |
11315 | * | |
11316 | * If ASC_BUSY is returned the request will be returned to the midlayer | |
11317 | * and re-tried later. | |
11318 | */ | |
11319 | static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp) | |
11320 | { | |
41d2493d MW |
11321 | int ret, err_code; |
11322 | asc_board_t *boardp = ASC_BOARDP(scp->device->host); | |
51219358 | 11323 | |
41d2493d | 11324 | ASC_DBG1(1, "asc_execute_scsi_cmnd: scp 0x%p\n", scp); |
27c868c2 | 11325 | |
51219358 | 11326 | if (ASC_NARROW_BOARD(boardp)) { |
41d2493d | 11327 | ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var; |
05848b6e | 11328 | struct asc_scsi_q asc_scsi_q; |
27c868c2 | 11329 | |
41d2493d | 11330 | /* asc_build_req() can not return ASC_BUSY. */ |
05848b6e MW |
11331 | ret = asc_build_req(boardp, scp, &asc_scsi_q); |
11332 | if (ret == ASC_ERROR) { | |
51219358 MW |
11333 | ASC_STATS(scp->device->host, build_error); |
11334 | return ASC_ERROR; | |
11335 | } | |
1da177e4 | 11336 | |
41d2493d | 11337 | ret = AscExeScsiQueue(asc_dvc, &asc_scsi_q); |
05848b6e | 11338 | kfree(asc_scsi_q.sg_head); |
41d2493d | 11339 | err_code = asc_dvc->err_code; |
51219358 | 11340 | } else { |
41d2493d MW |
11341 | ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var; |
11342 | ADV_SCSI_REQ_Q *adv_scsiqp; | |
27c868c2 | 11343 | |
51219358 MW |
11344 | switch (adv_build_req(boardp, scp, &adv_scsiqp)) { |
11345 | case ASC_NOERROR: | |
11346 | ASC_DBG(3, "asc_execute_scsi_cmnd: adv_build_req " | |
11347 | "ASC_NOERROR\n"); | |
11348 | break; | |
11349 | case ASC_BUSY: | |
11350 | ASC_DBG(1, "asc_execute_scsi_cmnd: adv_build_req " | |
11351 | "ASC_BUSY\n"); | |
11352 | /* | |
11353 | * The asc_stats fields 'adv_build_noreq' and | |
11354 | * 'adv_build_nosg' count wide board busy conditions. | |
11355 | * They are updated in adv_build_req and | |
11356 | * adv_get_sglist, respectively. | |
11357 | */ | |
11358 | return ASC_BUSY; | |
11359 | case ASC_ERROR: | |
11360 | default: | |
11361 | ASC_DBG(1, "asc_execute_scsi_cmnd: adv_build_req " | |
11362 | "ASC_ERROR\n"); | |
11363 | ASC_STATS(scp->device->host, build_error); | |
11364 | return ASC_ERROR; | |
11365 | } | |
11366 | ||
41d2493d MW |
11367 | ret = AdvExeScsiQueue(adv_dvc, adv_scsiqp); |
11368 | err_code = adv_dvc->err_code; | |
11369 | } | |
11370 | ||
11371 | switch (ret) { | |
11372 | case ASC_NOERROR: | |
11373 | ASC_STATS(scp->device->host, exe_noerror); | |
11374 | /* | |
11375 | * Increment monotonically increasing per device | |
11376 | * successful request counter. Wrapping doesn't matter. | |
11377 | */ | |
11378 | boardp->reqcnt[scp->device->id]++; | |
11379 | ASC_DBG(1, "asc_execute_scsi_cmnd: ExeScsiQueue(), " | |
11380 | "ASC_NOERROR\n"); | |
11381 | break; | |
11382 | case ASC_BUSY: | |
11383 | ASC_STATS(scp->device->host, exe_busy); | |
11384 | break; | |
11385 | case ASC_ERROR: | |
11386 | ASC_PRINT2("asc_execute_scsi_cmnd: board %d: ExeScsiQueue() " | |
11387 | "ASC_ERROR, err_code 0x%x\n", boardp->id, err_code); | |
11388 | ASC_STATS(scp->device->host, exe_error); | |
11389 | scp->result = HOST_BYTE(DID_ERROR); | |
11390 | break; | |
11391 | default: | |
11392 | ASC_PRINT2("asc_execute_scsi_cmnd: board %d: ExeScsiQueue() " | |
11393 | "unknown, err_code 0x%x\n", boardp->id, err_code); | |
11394 | ASC_STATS(scp->device->host, exe_unknown); | |
11395 | scp->result = HOST_BYTE(DID_ERROR); | |
11396 | break; | |
27c868c2 | 11397 | } |
1da177e4 | 11398 | |
51219358 MW |
11399 | ASC_DBG(1, "asc_execute_scsi_cmnd: end\n"); |
11400 | return ret; | |
11401 | } | |
27c868c2 | 11402 | |
51219358 MW |
11403 | /* |
11404 | * advansys_queuecommand() - interrupt-driven I/O entrypoint. | |
11405 | * | |
11406 | * This function always returns 0. Command return status is saved | |
11407 | * in the 'scp' result field. | |
11408 | */ | |
11409 | static int | |
11410 | advansys_queuecommand(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *)) | |
11411 | { | |
11412 | struct Scsi_Host *shost = scp->device->host; | |
11413 | asc_board_t *boardp = ASC_BOARDP(shost); | |
11414 | unsigned long flags; | |
11415 | int asc_res, result = 0; | |
27c868c2 | 11416 | |
51219358 MW |
11417 | ASC_STATS(shost, queuecommand); |
11418 | scp->scsi_done = done; | |
27c868c2 MW |
11419 | |
11420 | /* | |
51219358 MW |
11421 | * host_lock taken by mid-level prior to call, but need |
11422 | * to protect against own ISR | |
27c868c2 | 11423 | */ |
51219358 MW |
11424 | spin_lock_irqsave(&boardp->lock, flags); |
11425 | asc_res = asc_execute_scsi_cmnd(scp); | |
11426 | spin_unlock_irqrestore(&boardp->lock, flags); | |
11427 | ||
11428 | switch (asc_res) { | |
11429 | case ASC_NOERROR: | |
11430 | break; | |
11431 | case ASC_BUSY: | |
11432 | result = SCSI_MLQUEUE_HOST_BUSY; | |
11433 | break; | |
11434 | case ASC_ERROR: | |
11435 | default: | |
11436 | asc_scsi_done(scp); | |
11437 | break; | |
11438 | } | |
11439 | ||
11440 | return result; | |
11441 | } | |
11442 | ||
11443 | static ushort __devinit AscGetEisaChipCfg(PortAddr iop_base) | |
11444 | { | |
11445 | PortAddr eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) | | |
11446 | (PortAddr) (ASC_EISA_CFG_IOP_MASK); | |
11447 | return inpw(eisa_cfg_iop); | |
11448 | } | |
11449 | ||
11450 | /* | |
11451 | * Return the BIOS address of the adapter at the specified | |
11452 | * I/O port and with the specified bus type. | |
11453 | */ | |
11454 | static unsigned short __devinit | |
11455 | AscGetChipBiosAddress(PortAddr iop_base, unsigned short bus_type) | |
11456 | { | |
11457 | unsigned short cfg_lsw; | |
11458 | unsigned short bios_addr; | |
27c868c2 MW |
11459 | |
11460 | /* | |
51219358 MW |
11461 | * The PCI BIOS is re-located by the motherboard BIOS. Because |
11462 | * of this the driver can not determine where a PCI BIOS is | |
11463 | * loaded and executes. | |
27c868c2 | 11464 | */ |
51219358 MW |
11465 | if (bus_type & ASC_IS_PCI) |
11466 | return 0; | |
27c868c2 | 11467 | |
51219358 MW |
11468 | if ((bus_type & ASC_IS_EISA) != 0) { |
11469 | cfg_lsw = AscGetEisaChipCfg(iop_base); | |
11470 | cfg_lsw &= 0x000F; | |
11471 | bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE; | |
11472 | return bios_addr; | |
11473 | } | |
27c868c2 | 11474 | |
51219358 | 11475 | cfg_lsw = AscGetChipCfgLsw(iop_base); |
27c868c2 MW |
11476 | |
11477 | /* | |
51219358 | 11478 | * ISA PnP uses the top bit as the 32K BIOS flag |
27c868c2 | 11479 | */ |
51219358 MW |
11480 | if (bus_type == ASC_IS_ISAPNP) |
11481 | cfg_lsw &= 0x7FFF; | |
11482 | bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE; | |
11483 | return bios_addr; | |
11484 | } | |
11485 | ||
11486 | static uchar __devinit AscSetChipScsiID(PortAddr iop_base, uchar new_host_id) | |
11487 | { | |
11488 | ushort cfg_lsw; | |
11489 | ||
11490 | if (AscGetChipScsiID(iop_base) == new_host_id) { | |
11491 | return (new_host_id); | |
27c868c2 | 11492 | } |
51219358 MW |
11493 | cfg_lsw = AscGetChipCfgLsw(iop_base); |
11494 | cfg_lsw &= 0xF8FF; | |
11495 | cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8); | |
11496 | AscSetChipCfgLsw(iop_base, cfg_lsw); | |
11497 | return (AscGetChipScsiID(iop_base)); | |
11498 | } | |
27c868c2 | 11499 | |
51219358 MW |
11500 | static unsigned char __devinit AscGetChipScsiCtrl(PortAddr iop_base) |
11501 | { | |
11502 | unsigned char sc; | |
27c868c2 | 11503 | |
51219358 MW |
11504 | AscSetBank(iop_base, 1); |
11505 | sc = inp(iop_base + IOP_REG_SC); | |
11506 | AscSetBank(iop_base, 0); | |
11507 | return sc; | |
11508 | } | |
27c868c2 | 11509 | |
51219358 MW |
11510 | static unsigned char __devinit |
11511 | AscGetChipVersion(PortAddr iop_base, unsigned short bus_type) | |
11512 | { | |
11513 | if (bus_type & ASC_IS_EISA) { | |
11514 | PortAddr eisa_iop; | |
11515 | unsigned char revision; | |
11516 | eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) | | |
11517 | (PortAddr) ASC_EISA_REV_IOP_MASK; | |
11518 | revision = inp(eisa_iop); | |
11519 | return ASC_CHIP_MIN_VER_EISA - 1 + revision; | |
27c868c2 | 11520 | } |
51219358 MW |
11521 | return AscGetChipVerNo(iop_base); |
11522 | } | |
27c868c2 | 11523 | |
51219358 MW |
11524 | static void __devinit AscToggleIRQAct(PortAddr iop_base) |
11525 | { | |
11526 | AscSetChipStatus(iop_base, CIW_IRQ_ACT); | |
11527 | AscSetChipStatus(iop_base, 0); | |
11528 | return; | |
11529 | } | |
27c868c2 | 11530 | |
51219358 MW |
11531 | static uchar __devinit AscGetChipIRQ(PortAddr iop_base, ushort bus_type) |
11532 | { | |
11533 | ushort cfg_lsw; | |
11534 | uchar chip_irq; | |
27c868c2 | 11535 | |
51219358 MW |
11536 | if ((bus_type & ASC_IS_EISA) != 0) { |
11537 | cfg_lsw = AscGetEisaChipCfg(iop_base); | |
11538 | chip_irq = (uchar)(((cfg_lsw >> 8) & 0x07) + 10); | |
11539 | if ((chip_irq == 13) || (chip_irq > 15)) { | |
11540 | return (0); | |
11541 | } | |
11542 | return (chip_irq); | |
11543 | } | |
11544 | if ((bus_type & ASC_IS_VL) != 0) { | |
11545 | cfg_lsw = AscGetChipCfgLsw(iop_base); | |
11546 | chip_irq = (uchar)(((cfg_lsw >> 2) & 0x07)); | |
11547 | if ((chip_irq == 0) || (chip_irq == 4) || (chip_irq == 7)) { | |
11548 | return (0); | |
11549 | } | |
11550 | return ((uchar)(chip_irq + (ASC_MIN_IRQ_NO - 1))); | |
11551 | } | |
11552 | cfg_lsw = AscGetChipCfgLsw(iop_base); | |
11553 | chip_irq = (uchar)(((cfg_lsw >> 2) & 0x03)); | |
11554 | if (chip_irq == 3) | |
11555 | chip_irq += (uchar)2; | |
11556 | return ((uchar)(chip_irq + ASC_MIN_IRQ_NO)); | |
11557 | } | |
27c868c2 | 11558 | |
51219358 MW |
11559 | static uchar __devinit |
11560 | AscSetChipIRQ(PortAddr iop_base, uchar irq_no, ushort bus_type) | |
11561 | { | |
11562 | ushort cfg_lsw; | |
27c868c2 | 11563 | |
51219358 MW |
11564 | if ((bus_type & ASC_IS_VL) != 0) { |
11565 | if (irq_no != 0) { | |
11566 | if ((irq_no < ASC_MIN_IRQ_NO) | |
11567 | || (irq_no > ASC_MAX_IRQ_NO)) { | |
11568 | irq_no = 0; | |
11569 | } else { | |
11570 | irq_no -= (uchar)((ASC_MIN_IRQ_NO - 1)); | |
27c868c2 MW |
11571 | } |
11572 | } | |
51219358 MW |
11573 | cfg_lsw = (ushort)(AscGetChipCfgLsw(iop_base) & 0xFFE3); |
11574 | cfg_lsw |= (ushort)0x0010; | |
11575 | AscSetChipCfgLsw(iop_base, cfg_lsw); | |
11576 | AscToggleIRQAct(iop_base); | |
11577 | cfg_lsw = (ushort)(AscGetChipCfgLsw(iop_base) & 0xFFE0); | |
11578 | cfg_lsw |= (ushort)((irq_no & 0x07) << 2); | |
11579 | AscSetChipCfgLsw(iop_base, cfg_lsw); | |
11580 | AscToggleIRQAct(iop_base); | |
11581 | return (AscGetChipIRQ(iop_base, bus_type)); | |
11582 | } | |
11583 | if ((bus_type & (ASC_IS_ISA)) != 0) { | |
11584 | if (irq_no == 15) | |
11585 | irq_no -= (uchar)2; | |
11586 | irq_no -= (uchar)ASC_MIN_IRQ_NO; | |
11587 | cfg_lsw = (ushort)(AscGetChipCfgLsw(iop_base) & 0xFFF3); | |
11588 | cfg_lsw |= (ushort)((irq_no & 0x03) << 2); | |
11589 | AscSetChipCfgLsw(iop_base, cfg_lsw); | |
11590 | return (AscGetChipIRQ(iop_base, bus_type)); | |
27c868c2 | 11591 | } |
51219358 MW |
11592 | return (0); |
11593 | } | |
1da177e4 | 11594 | |
51219358 MW |
11595 | #ifdef CONFIG_ISA |
11596 | static void __devinit AscEnableIsaDma(uchar dma_channel) | |
11597 | { | |
11598 | if (dma_channel < 4) { | |
11599 | outp(0x000B, (ushort)(0xC0 | dma_channel)); | |
11600 | outp(0x000A, dma_channel); | |
11601 | } else if (dma_channel < 8) { | |
11602 | outp(0x00D6, (ushort)(0xC0 | (dma_channel - 4))); | |
11603 | outp(0x00D4, (ushort)(dma_channel - 4)); | |
11604 | } | |
11605 | return; | |
11606 | } | |
11607 | #endif /* CONFIG_ISA */ | |
11608 | ||
11609 | static int AscStopQueueExe(PortAddr iop_base) | |
11610 | { | |
11611 | int count = 0; | |
11612 | ||
11613 | if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) { | |
11614 | AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, | |
11615 | ASC_STOP_REQ_RISC_STOP); | |
11616 | do { | |
11617 | if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) & | |
11618 | ASC_STOP_ACK_RISC_STOP) { | |
11619 | return (1); | |
11620 | } | |
11621 | mdelay(100); | |
11622 | } while (count++ < 20); | |
11623 | } | |
11624 | return (0); | |
11625 | } | |
11626 | ||
11627 | static ASC_DCNT __devinit AscGetMaxDmaCount(ushort bus_type) | |
11628 | { | |
11629 | if (bus_type & ASC_IS_ISA) | |
11630 | return ASC_MAX_ISA_DMA_COUNT; | |
11631 | else if (bus_type & (ASC_IS_EISA | ASC_IS_VL)) | |
11632 | return ASC_MAX_VL_DMA_COUNT; | |
11633 | return ASC_MAX_PCI_DMA_COUNT; | |
27c868c2 | 11634 | } |
1da177e4 | 11635 | |
51219358 MW |
11636 | #ifdef CONFIG_ISA |
11637 | static ushort __devinit AscGetIsaDmaChannel(PortAddr iop_base) | |
27c868c2 | 11638 | { |
51219358 | 11639 | ushort channel; |
1da177e4 | 11640 | |
51219358 MW |
11641 | channel = AscGetChipCfgLsw(iop_base) & 0x0003; |
11642 | if (channel == 0x03) | |
11643 | return (0); | |
11644 | else if (channel == 0x00) | |
11645 | return (7); | |
11646 | return (channel + 4); | |
11647 | } | |
1da177e4 | 11648 | |
51219358 MW |
11649 | static ushort __devinit AscSetIsaDmaChannel(PortAddr iop_base, ushort dma_channel) |
11650 | { | |
11651 | ushort cfg_lsw; | |
11652 | uchar value; | |
1da177e4 | 11653 | |
51219358 MW |
11654 | if ((dma_channel >= 5) && (dma_channel <= 7)) { |
11655 | if (dma_channel == 7) | |
11656 | value = 0x00; | |
11657 | else | |
11658 | value = dma_channel - 4; | |
11659 | cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC; | |
11660 | cfg_lsw |= value; | |
11661 | AscSetChipCfgLsw(iop_base, cfg_lsw); | |
11662 | return (AscGetIsaDmaChannel(iop_base)); | |
11663 | } | |
11664 | return 0; | |
11665 | } | |
1da177e4 | 11666 | |
51219358 MW |
11667 | static uchar __devinit AscGetIsaDmaSpeed(PortAddr iop_base) |
11668 | { | |
11669 | uchar speed_value; | |
1da177e4 | 11670 | |
51219358 MW |
11671 | AscSetBank(iop_base, 1); |
11672 | speed_value = AscReadChipDmaSpeed(iop_base); | |
11673 | speed_value &= 0x07; | |
11674 | AscSetBank(iop_base, 0); | |
11675 | return speed_value; | |
11676 | } | |
1da177e4 | 11677 | |
51219358 MW |
11678 | static uchar __devinit AscSetIsaDmaSpeed(PortAddr iop_base, uchar speed_value) |
11679 | { | |
11680 | speed_value &= 0x07; | |
11681 | AscSetBank(iop_base, 1); | |
11682 | AscWriteChipDmaSpeed(iop_base, speed_value); | |
11683 | AscSetBank(iop_base, 0); | |
11684 | return AscGetIsaDmaSpeed(iop_base); | |
11685 | } | |
11686 | #endif /* CONFIG_ISA */ | |
1da177e4 | 11687 | |
51219358 MW |
11688 | static ushort __devinit AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc) |
11689 | { | |
11690 | int i; | |
11691 | PortAddr iop_base; | |
11692 | ushort warn_code; | |
11693 | uchar chip_version; | |
1da177e4 | 11694 | |
51219358 MW |
11695 | iop_base = asc_dvc->iop_base; |
11696 | warn_code = 0; | |
11697 | asc_dvc->err_code = 0; | |
11698 | if ((asc_dvc->bus_type & | |
11699 | (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) { | |
11700 | asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE; | |
27c868c2 | 11701 | } |
51219358 MW |
11702 | AscSetChipControl(iop_base, CC_HALT); |
11703 | AscSetChipStatus(iop_base, 0); | |
11704 | asc_dvc->bug_fix_cntl = 0; | |
11705 | asc_dvc->pci_fix_asyn_xfer = 0; | |
11706 | asc_dvc->pci_fix_asyn_xfer_always = 0; | |
11707 | /* asc_dvc->init_state initalized in AscInitGetConfig(). */ | |
11708 | asc_dvc->sdtr_done = 0; | |
11709 | asc_dvc->cur_total_qng = 0; | |
11710 | asc_dvc->is_in_int = 0; | |
11711 | asc_dvc->in_critical_cnt = 0; | |
11712 | asc_dvc->last_q_shortage = 0; | |
11713 | asc_dvc->use_tagged_qng = 0; | |
11714 | asc_dvc->no_scam = 0; | |
11715 | asc_dvc->unit_not_ready = 0; | |
11716 | asc_dvc->queue_full_or_busy = 0; | |
11717 | asc_dvc->redo_scam = 0; | |
11718 | asc_dvc->res2 = 0; | |
11719 | asc_dvc->host_init_sdtr_index = 0; | |
11720 | asc_dvc->cfg->can_tagged_qng = 0; | |
11721 | asc_dvc->cfg->cmd_qng_enabled = 0; | |
11722 | asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL; | |
11723 | asc_dvc->init_sdtr = 0; | |
11724 | asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG; | |
11725 | asc_dvc->scsi_reset_wait = 3; | |
11726 | asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET; | |
11727 | asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type); | |
11728 | asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET; | |
11729 | asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET; | |
11730 | asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID; | |
11731 | asc_dvc->cfg->lib_serial_no = ASC_LIB_SERIAL_NUMBER; | |
11732 | asc_dvc->cfg->lib_version = (ASC_LIB_VERSION_MAJOR << 8) | | |
11733 | ASC_LIB_VERSION_MINOR; | |
11734 | chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type); | |
11735 | asc_dvc->cfg->chip_version = chip_version; | |
11736 | asc_dvc->sdtr_period_tbl[0] = SYN_XFER_NS_0; | |
11737 | asc_dvc->sdtr_period_tbl[1] = SYN_XFER_NS_1; | |
11738 | asc_dvc->sdtr_period_tbl[2] = SYN_XFER_NS_2; | |
11739 | asc_dvc->sdtr_period_tbl[3] = SYN_XFER_NS_3; | |
11740 | asc_dvc->sdtr_period_tbl[4] = SYN_XFER_NS_4; | |
11741 | asc_dvc->sdtr_period_tbl[5] = SYN_XFER_NS_5; | |
11742 | asc_dvc->sdtr_period_tbl[6] = SYN_XFER_NS_6; | |
11743 | asc_dvc->sdtr_period_tbl[7] = SYN_XFER_NS_7; | |
11744 | asc_dvc->max_sdtr_index = 7; | |
11745 | if ((asc_dvc->bus_type & ASC_IS_PCI) && | |
11746 | (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) { | |
11747 | asc_dvc->bus_type = ASC_IS_PCI_ULTRA; | |
11748 | asc_dvc->sdtr_period_tbl[0] = SYN_ULTRA_XFER_NS_0; | |
11749 | asc_dvc->sdtr_period_tbl[1] = SYN_ULTRA_XFER_NS_1; | |
11750 | asc_dvc->sdtr_period_tbl[2] = SYN_ULTRA_XFER_NS_2; | |
11751 | asc_dvc->sdtr_period_tbl[3] = SYN_ULTRA_XFER_NS_3; | |
11752 | asc_dvc->sdtr_period_tbl[4] = SYN_ULTRA_XFER_NS_4; | |
11753 | asc_dvc->sdtr_period_tbl[5] = SYN_ULTRA_XFER_NS_5; | |
11754 | asc_dvc->sdtr_period_tbl[6] = SYN_ULTRA_XFER_NS_6; | |
11755 | asc_dvc->sdtr_period_tbl[7] = SYN_ULTRA_XFER_NS_7; | |
11756 | asc_dvc->sdtr_period_tbl[8] = SYN_ULTRA_XFER_NS_8; | |
11757 | asc_dvc->sdtr_period_tbl[9] = SYN_ULTRA_XFER_NS_9; | |
11758 | asc_dvc->sdtr_period_tbl[10] = SYN_ULTRA_XFER_NS_10; | |
11759 | asc_dvc->sdtr_period_tbl[11] = SYN_ULTRA_XFER_NS_11; | |
11760 | asc_dvc->sdtr_period_tbl[12] = SYN_ULTRA_XFER_NS_12; | |
11761 | asc_dvc->sdtr_period_tbl[13] = SYN_ULTRA_XFER_NS_13; | |
11762 | asc_dvc->sdtr_period_tbl[14] = SYN_ULTRA_XFER_NS_14; | |
11763 | asc_dvc->sdtr_period_tbl[15] = SYN_ULTRA_XFER_NS_15; | |
11764 | asc_dvc->max_sdtr_index = 15; | |
11765 | if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) { | |
11766 | AscSetExtraControl(iop_base, | |
11767 | (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); | |
11768 | } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) { | |
11769 | AscSetExtraControl(iop_base, | |
11770 | (SEC_ACTIVE_NEGATE | | |
11771 | SEC_ENABLE_FILTER)); | |
27c868c2 MW |
11772 | } |
11773 | } | |
51219358 MW |
11774 | if (asc_dvc->bus_type == ASC_IS_PCI) { |
11775 | AscSetExtraControl(iop_base, | |
11776 | (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); | |
11777 | } | |
1da177e4 | 11778 | |
51219358 MW |
11779 | asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED; |
11780 | #ifdef CONFIG_ISA | |
11781 | if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) { | |
11782 | if (chip_version >= ASC_CHIP_MIN_VER_ISA_PNP) { | |
11783 | AscSetChipIFC(iop_base, IFC_INIT_DEFAULT); | |
11784 | asc_dvc->bus_type = ASC_IS_ISAPNP; | |
27c868c2 | 11785 | } |
51219358 MW |
11786 | asc_dvc->cfg->isa_dma_channel = |
11787 | (uchar)AscGetIsaDmaChannel(iop_base); | |
27c868c2 | 11788 | } |
51219358 MW |
11789 | #endif /* CONFIG_ISA */ |
11790 | for (i = 0; i <= ASC_MAX_TID; i++) { | |
11791 | asc_dvc->cur_dvc_qng[i] = 0; | |
11792 | asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG; | |
11793 | asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L; | |
11794 | asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L; | |
11795 | asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG; | |
27c868c2 | 11796 | } |
51219358 MW |
11797 | return warn_code; |
11798 | } | |
1da177e4 | 11799 | |
51219358 MW |
11800 | static int __devinit AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg) |
11801 | { | |
11802 | int retry; | |
27c868c2 | 11803 | |
51219358 MW |
11804 | for (retry = 0; retry < ASC_EEP_MAX_RETRY; retry++) { |
11805 | unsigned char read_back; | |
11806 | AscSetChipEEPCmd(iop_base, cmd_reg); | |
11807 | mdelay(1); | |
11808 | read_back = AscGetChipEEPCmd(iop_base); | |
11809 | if (read_back == cmd_reg) | |
11810 | return 1; | |
27c868c2 | 11811 | } |
51219358 MW |
11812 | return 0; |
11813 | } | |
1da177e4 | 11814 | |
51219358 MW |
11815 | static void __devinit AscWaitEEPRead(void) |
11816 | { | |
11817 | mdelay(1); | |
27c868c2 | 11818 | } |
1da177e4 | 11819 | |
51219358 | 11820 | static ushort __devinit AscReadEEPWord(PortAddr iop_base, uchar addr) |
27c868c2 | 11821 | { |
51219358 MW |
11822 | ushort read_wval; |
11823 | uchar cmd_reg; | |
27c868c2 | 11824 | |
51219358 MW |
11825 | AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE); |
11826 | AscWaitEEPRead(); | |
11827 | cmd_reg = addr | ASC_EEP_CMD_READ; | |
11828 | AscWriteEEPCmdReg(iop_base, cmd_reg); | |
11829 | AscWaitEEPRead(); | |
11830 | read_wval = AscGetChipEEPData(iop_base); | |
11831 | AscWaitEEPRead(); | |
11832 | return read_wval; | |
11833 | } | |
27c868c2 | 11834 | |
51219358 MW |
11835 | static ushort __devinit |
11836 | AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type) | |
11837 | { | |
11838 | ushort wval; | |
11839 | ushort sum; | |
11840 | ushort *wbuf; | |
11841 | int cfg_beg; | |
11842 | int cfg_end; | |
11843 | int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2; | |
11844 | int s_addr; | |
27c868c2 | 11845 | |
51219358 MW |
11846 | wbuf = (ushort *)cfg_buf; |
11847 | sum = 0; | |
11848 | /* Read two config words; Byte-swapping done by AscReadEEPWord(). */ | |
11849 | for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { | |
11850 | *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr); | |
11851 | sum += *wbuf; | |
11852 | } | |
11853 | if (bus_type & ASC_IS_VL) { | |
11854 | cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; | |
11855 | cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; | |
11856 | } else { | |
11857 | cfg_beg = ASC_EEP_DVC_CFG_BEG; | |
11858 | cfg_end = ASC_EEP_MAX_DVC_ADDR; | |
11859 | } | |
11860 | for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { | |
11861 | wval = AscReadEEPWord(iop_base, (uchar)s_addr); | |
11862 | if (s_addr <= uchar_end_in_config) { | |
11863 | /* | |
11864 | * Swap all char fields - must unswap bytes already swapped | |
11865 | * by AscReadEEPWord(). | |
11866 | */ | |
11867 | *wbuf = le16_to_cpu(wval); | |
11868 | } else { | |
11869 | /* Don't swap word field at the end - cntl field. */ | |
11870 | *wbuf = wval; | |
11871 | } | |
11872 | sum += wval; /* Checksum treats all EEPROM data as words. */ | |
11873 | } | |
27c868c2 | 11874 | /* |
51219358 MW |
11875 | * Read the checksum word which will be compared against 'sum' |
11876 | * by the caller. Word field already swapped. | |
27c868c2 | 11877 | */ |
51219358 MW |
11878 | *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr); |
11879 | return sum; | |
11880 | } | |
1da177e4 | 11881 | |
51219358 MW |
11882 | static int __devinit AscTestExternalLram(ASC_DVC_VAR *asc_dvc) |
11883 | { | |
11884 | PortAddr iop_base; | |
11885 | ushort q_addr; | |
11886 | ushort saved_word; | |
11887 | int sta; | |
1da177e4 | 11888 | |
51219358 MW |
11889 | iop_base = asc_dvc->iop_base; |
11890 | sta = 0; | |
11891 | q_addr = ASC_QNO_TO_QADDR(241); | |
11892 | saved_word = AscReadLramWord(iop_base, q_addr); | |
11893 | AscSetChipLramAddr(iop_base, q_addr); | |
11894 | AscSetChipLramData(iop_base, 0x55AA); | |
11895 | mdelay(10); | |
11896 | AscSetChipLramAddr(iop_base, q_addr); | |
11897 | if (AscGetChipLramData(iop_base) == 0x55AA) { | |
11898 | sta = 1; | |
11899 | AscWriteLramWord(iop_base, q_addr, saved_word); | |
11900 | } | |
11901 | return (sta); | |
11902 | } | |
1da177e4 | 11903 | |
51219358 MW |
11904 | static void __devinit AscWaitEEPWrite(void) |
11905 | { | |
11906 | mdelay(20); | |
11907 | return; | |
11908 | } | |
1da177e4 | 11909 | |
51219358 MW |
11910 | static int __devinit AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg) |
11911 | { | |
11912 | ushort read_back; | |
11913 | int retry; | |
1da177e4 | 11914 | |
51219358 MW |
11915 | retry = 0; |
11916 | while (TRUE) { | |
11917 | AscSetChipEEPData(iop_base, data_reg); | |
11918 | mdelay(1); | |
11919 | read_back = AscGetChipEEPData(iop_base); | |
11920 | if (read_back == data_reg) { | |
11921 | return (1); | |
11922 | } | |
11923 | if (retry++ > ASC_EEP_MAX_RETRY) { | |
11924 | return (0); | |
11925 | } | |
27c868c2 | 11926 | } |
51219358 | 11927 | } |
27c868c2 | 11928 | |
51219358 MW |
11929 | static ushort __devinit |
11930 | AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val) | |
11931 | { | |
11932 | ushort read_wval; | |
11933 | ||
11934 | read_wval = AscReadEEPWord(iop_base, addr); | |
11935 | if (read_wval != word_val) { | |
11936 | AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE); | |
11937 | AscWaitEEPRead(); | |
11938 | AscWriteEEPDataReg(iop_base, word_val); | |
11939 | AscWaitEEPRead(); | |
11940 | AscWriteEEPCmdReg(iop_base, | |
11941 | (uchar)((uchar)ASC_EEP_CMD_WRITE | addr)); | |
11942 | AscWaitEEPWrite(); | |
11943 | AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE); | |
11944 | AscWaitEEPRead(); | |
11945 | return (AscReadEEPWord(iop_base, addr)); | |
11946 | } | |
11947 | return (read_wval); | |
11948 | } | |
11949 | ||
11950 | static int __devinit | |
11951 | AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type) | |
11952 | { | |
11953 | int n_error; | |
11954 | ushort *wbuf; | |
11955 | ushort word; | |
11956 | ushort sum; | |
11957 | int s_addr; | |
11958 | int cfg_beg; | |
11959 | int cfg_end; | |
11960 | int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2; | |
11961 | ||
11962 | wbuf = (ushort *)cfg_buf; | |
11963 | n_error = 0; | |
11964 | sum = 0; | |
11965 | /* Write two config words; AscWriteEEPWord() will swap bytes. */ | |
11966 | for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { | |
11967 | sum += *wbuf; | |
11968 | if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) { | |
11969 | n_error++; | |
27c868c2 | 11970 | } |
51219358 MW |
11971 | } |
11972 | if (bus_type & ASC_IS_VL) { | |
11973 | cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; | |
11974 | cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; | |
11975 | } else { | |
11976 | cfg_beg = ASC_EEP_DVC_CFG_BEG; | |
11977 | cfg_end = ASC_EEP_MAX_DVC_ADDR; | |
11978 | } | |
11979 | for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { | |
11980 | if (s_addr <= uchar_end_in_config) { | |
11981 | /* | |
11982 | * This is a char field. Swap char fields before they are | |
11983 | * swapped again by AscWriteEEPWord(). | |
11984 | */ | |
11985 | word = cpu_to_le16(*wbuf); | |
11986 | if (word != | |
11987 | AscWriteEEPWord(iop_base, (uchar)s_addr, word)) { | |
11988 | n_error++; | |
11989 | } | |
11990 | } else { | |
11991 | /* Don't swap word field at the end - cntl field. */ | |
11992 | if (*wbuf != | |
11993 | AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) { | |
11994 | n_error++; | |
11995 | } | |
27c868c2 | 11996 | } |
51219358 MW |
11997 | sum += *wbuf; /* Checksum calculated from word values. */ |
11998 | } | |
11999 | /* Write checksum word. It will be swapped by AscWriteEEPWord(). */ | |
12000 | *wbuf = sum; | |
12001 | if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) { | |
12002 | n_error++; | |
27c868c2 | 12003 | } |
1da177e4 | 12004 | |
51219358 MW |
12005 | /* Read EEPROM back again. */ |
12006 | wbuf = (ushort *)cfg_buf; | |
27c868c2 | 12007 | /* |
51219358 | 12008 | * Read two config words; Byte-swapping done by AscReadEEPWord(). |
27c868c2 | 12009 | */ |
51219358 MW |
12010 | for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { |
12011 | if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) { | |
12012 | n_error++; | |
27c868c2 MW |
12013 | } |
12014 | } | |
51219358 MW |
12015 | if (bus_type & ASC_IS_VL) { |
12016 | cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; | |
12017 | cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; | |
12018 | } else { | |
12019 | cfg_beg = ASC_EEP_DVC_CFG_BEG; | |
12020 | cfg_end = ASC_EEP_MAX_DVC_ADDR; | |
12021 | } | |
12022 | for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { | |
12023 | if (s_addr <= uchar_end_in_config) { | |
12024 | /* | |
12025 | * Swap all char fields. Must unswap bytes already swapped | |
12026 | * by AscReadEEPWord(). | |
12027 | */ | |
12028 | word = | |
12029 | le16_to_cpu(AscReadEEPWord | |
12030 | (iop_base, (uchar)s_addr)); | |
27c868c2 | 12031 | } else { |
51219358 MW |
12032 | /* Don't swap word field at the end - cntl field. */ |
12033 | word = AscReadEEPWord(iop_base, (uchar)s_addr); | |
12034 | } | |
12035 | if (*wbuf != word) { | |
12036 | n_error++; | |
27c868c2 MW |
12037 | } |
12038 | } | |
51219358 MW |
12039 | /* Read checksum; Byte swapping not needed. */ |
12040 | if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) { | |
12041 | n_error++; | |
27c868c2 | 12042 | } |
51219358 MW |
12043 | return n_error; |
12044 | } | |
1da177e4 | 12045 | |
51219358 MW |
12046 | static int __devinit |
12047 | AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type) | |
12048 | { | |
12049 | int retry; | |
12050 | int n_error; | |
27c868c2 | 12051 | |
51219358 MW |
12052 | retry = 0; |
12053 | while (TRUE) { | |
12054 | if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf, | |
12055 | bus_type)) == 0) { | |
12056 | break; | |
12057 | } | |
12058 | if (++retry > ASC_EEP_MAX_RETRY) { | |
12059 | break; | |
12060 | } | |
12061 | } | |
12062 | return n_error; | |
12063 | } | |
27c868c2 | 12064 | |
51219358 MW |
12065 | static ushort __devinit AscInitFromEEP(ASC_DVC_VAR *asc_dvc) |
12066 | { | |
12067 | ASCEEP_CONFIG eep_config_buf; | |
12068 | ASCEEP_CONFIG *eep_config; | |
12069 | PortAddr iop_base; | |
12070 | ushort chksum; | |
12071 | ushort warn_code; | |
12072 | ushort cfg_msw, cfg_lsw; | |
12073 | int i; | |
12074 | int write_eep = 0; | |
27c868c2 | 12075 | |
51219358 MW |
12076 | iop_base = asc_dvc->iop_base; |
12077 | warn_code = 0; | |
12078 | AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE); | |
12079 | AscStopQueueExe(iop_base); | |
12080 | if ((AscStopChip(iop_base) == FALSE) || | |
12081 | (AscGetChipScsiCtrl(iop_base) != 0)) { | |
12082 | asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE; | |
12083 | AscResetChipAndScsiBus(asc_dvc); | |
12084 | mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */ | |
12085 | } | |
12086 | if (AscIsChipHalted(iop_base) == FALSE) { | |
12087 | asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP; | |
12088 | return (warn_code); | |
12089 | } | |
12090 | AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR); | |
12091 | if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) { | |
12092 | asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR; | |
12093 | return (warn_code); | |
12094 | } | |
12095 | eep_config = (ASCEEP_CONFIG *)&eep_config_buf; | |
12096 | cfg_msw = AscGetChipCfgMsw(iop_base); | |
12097 | cfg_lsw = AscGetChipCfgLsw(iop_base); | |
12098 | if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { | |
12099 | cfg_msw &= ~ASC_CFG_MSW_CLR_MASK; | |
12100 | warn_code |= ASC_WARN_CFG_MSW_RECOVER; | |
12101 | AscSetChipCfgMsw(iop_base, cfg_msw); | |
12102 | } | |
12103 | chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type); | |
12104 | ASC_DBG1(1, "AscInitFromEEP: chksum 0x%x\n", chksum); | |
12105 | if (chksum == 0) { | |
12106 | chksum = 0xaa55; | |
12107 | } | |
12108 | if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) { | |
12109 | warn_code |= ASC_WARN_AUTO_CONFIG; | |
12110 | if (asc_dvc->cfg->chip_version == 3) { | |
12111 | if (eep_config->cfg_lsw != cfg_lsw) { | |
12112 | warn_code |= ASC_WARN_EEPROM_RECOVER; | |
12113 | eep_config->cfg_lsw = | |
12114 | AscGetChipCfgLsw(iop_base); | |
12115 | } | |
12116 | if (eep_config->cfg_msw != cfg_msw) { | |
12117 | warn_code |= ASC_WARN_EEPROM_RECOVER; | |
12118 | eep_config->cfg_msw = | |
12119 | AscGetChipCfgMsw(iop_base); | |
12120 | } | |
12121 | } | |
12122 | } | |
12123 | eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK; | |
12124 | eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON; | |
12125 | ASC_DBG1(1, "AscInitFromEEP: eep_config->chksum 0x%x\n", | |
12126 | eep_config->chksum); | |
12127 | if (chksum != eep_config->chksum) { | |
12128 | if (AscGetChipVersion(iop_base, asc_dvc->bus_type) == | |
12129 | ASC_CHIP_VER_PCI_ULTRA_3050) { | |
12130 | ASC_DBG(1, | |
12131 | "AscInitFromEEP: chksum error ignored; EEPROM-less board\n"); | |
12132 | eep_config->init_sdtr = 0xFF; | |
12133 | eep_config->disc_enable = 0xFF; | |
12134 | eep_config->start_motor = 0xFF; | |
12135 | eep_config->use_cmd_qng = 0; | |
12136 | eep_config->max_total_qng = 0xF0; | |
12137 | eep_config->max_tag_qng = 0x20; | |
12138 | eep_config->cntl = 0xBFFF; | |
12139 | ASC_EEP_SET_CHIP_ID(eep_config, 7); | |
12140 | eep_config->no_scam = 0; | |
12141 | eep_config->adapter_info[0] = 0; | |
12142 | eep_config->adapter_info[1] = 0; | |
12143 | eep_config->adapter_info[2] = 0; | |
12144 | eep_config->adapter_info[3] = 0; | |
12145 | eep_config->adapter_info[4] = 0; | |
12146 | /* Indicate EEPROM-less board. */ | |
12147 | eep_config->adapter_info[5] = 0xBB; | |
27c868c2 | 12148 | } else { |
51219358 MW |
12149 | ASC_PRINT |
12150 | ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n"); | |
12151 | write_eep = 1; | |
12152 | warn_code |= ASC_WARN_EEPROM_CHKSUM; | |
12153 | } | |
12154 | } | |
12155 | asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr; | |
12156 | asc_dvc->cfg->disc_enable = eep_config->disc_enable; | |
12157 | asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng; | |
12158 | asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config); | |
12159 | asc_dvc->start_motor = eep_config->start_motor; | |
12160 | asc_dvc->dvc_cntl = eep_config->cntl; | |
12161 | asc_dvc->no_scam = eep_config->no_scam; | |
12162 | asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0]; | |
12163 | asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1]; | |
12164 | asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2]; | |
12165 | asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3]; | |
12166 | asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4]; | |
12167 | asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5]; | |
12168 | if (!AscTestExternalLram(asc_dvc)) { | |
12169 | if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == | |
12170 | ASC_IS_PCI_ULTRA)) { | |
12171 | eep_config->max_total_qng = | |
12172 | ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG; | |
12173 | eep_config->max_tag_qng = | |
12174 | ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG; | |
12175 | } else { | |
12176 | eep_config->cfg_msw |= 0x0800; | |
12177 | cfg_msw |= 0x0800; | |
12178 | AscSetChipCfgMsw(iop_base, cfg_msw); | |
12179 | eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG; | |
12180 | eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG; | |
27c868c2 | 12181 | } |
51219358 MW |
12182 | } else { |
12183 | } | |
12184 | if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) { | |
12185 | eep_config->max_total_qng = ASC_MIN_TOTAL_QNG; | |
12186 | } | |
12187 | if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) { | |
12188 | eep_config->max_total_qng = ASC_MAX_TOTAL_QNG; | |
12189 | } | |
12190 | if (eep_config->max_tag_qng > eep_config->max_total_qng) { | |
12191 | eep_config->max_tag_qng = eep_config->max_total_qng; | |
12192 | } | |
12193 | if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) { | |
12194 | eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC; | |
12195 | } | |
12196 | asc_dvc->max_total_qng = eep_config->max_total_qng; | |
12197 | if ((eep_config->use_cmd_qng & eep_config->disc_enable) != | |
12198 | eep_config->use_cmd_qng) { | |
12199 | eep_config->disc_enable = eep_config->use_cmd_qng; | |
12200 | warn_code |= ASC_WARN_CMD_QNG_CONFLICT; | |
12201 | } | |
12202 | if (asc_dvc->bus_type & (ASC_IS_ISA | ASC_IS_VL | ASC_IS_EISA)) { | |
12203 | asc_dvc->irq_no = AscGetChipIRQ(iop_base, asc_dvc->bus_type); | |
12204 | } | |
12205 | ASC_EEP_SET_CHIP_ID(eep_config, | |
12206 | ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID); | |
12207 | asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config); | |
12208 | if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) && | |
12209 | !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) { | |
12210 | asc_dvc->host_init_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX; | |
27c868c2 | 12211 | } |
1da177e4 | 12212 | |
51219358 MW |
12213 | for (i = 0; i <= ASC_MAX_TID; i++) { |
12214 | asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i]; | |
12215 | asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng; | |
12216 | asc_dvc->cfg->sdtr_period_offset[i] = | |
12217 | (uchar)(ASC_DEF_SDTR_OFFSET | | |
12218 | (asc_dvc->host_init_sdtr_index << 4)); | |
12219 | } | |
12220 | eep_config->cfg_msw = AscGetChipCfgMsw(iop_base); | |
12221 | if (write_eep) { | |
12222 | if ((i = AscSetEEPConfig(iop_base, eep_config, | |
12223 | asc_dvc->bus_type)) != 0) { | |
12224 | ASC_PRINT1 | |
12225 | ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n", | |
12226 | i); | |
27c868c2 | 12227 | } else { |
51219358 MW |
12228 | ASC_PRINT |
12229 | ("AscInitFromEEP: Successfully re-wrote EEPROM.\n"); | |
27c868c2 MW |
12230 | } |
12231 | } | |
51219358 | 12232 | return (warn_code); |
1da177e4 LT |
12233 | } |
12234 | ||
51219358 | 12235 | static int __devinit AscInitGetConfig(asc_board_t *boardp) |
1da177e4 | 12236 | { |
51219358 MW |
12237 | ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var; |
12238 | unsigned short warn_code = 0; | |
27c868c2 | 12239 | |
51219358 MW |
12240 | asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG; |
12241 | if (asc_dvc->err_code != 0) | |
12242 | return asc_dvc->err_code; | |
27c868c2 | 12243 | |
51219358 MW |
12244 | if (AscFindSignature(asc_dvc->iop_base)) { |
12245 | warn_code |= AscInitAscDvcVar(asc_dvc); | |
12246 | warn_code |= AscInitFromEEP(asc_dvc); | |
12247 | asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG; | |
12248 | if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT) | |
12249 | asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT; | |
12250 | } else { | |
12251 | asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE; | |
12252 | } | |
27c868c2 | 12253 | |
51219358 MW |
12254 | switch (warn_code) { |
12255 | case 0: /* No error */ | |
12256 | break; | |
12257 | case ASC_WARN_IO_PORT_ROTATE: | |
12258 | ASC_PRINT1("AscInitGetConfig: board %d: I/O port address " | |
12259 | "modified\n", boardp->id); | |
12260 | break; | |
12261 | case ASC_WARN_AUTO_CONFIG: | |
12262 | ASC_PRINT1("AscInitGetConfig: board %d: I/O port increment " | |
12263 | "switch enabled\n", boardp->id); | |
12264 | break; | |
12265 | case ASC_WARN_EEPROM_CHKSUM: | |
12266 | ASC_PRINT1("AscInitGetConfig: board %d: EEPROM checksum " | |
12267 | "error\n", boardp->id); | |
12268 | break; | |
12269 | case ASC_WARN_IRQ_MODIFIED: | |
12270 | ASC_PRINT1("AscInitGetConfig: board %d: IRQ modified\n", | |
12271 | boardp->id); | |
12272 | break; | |
12273 | case ASC_WARN_CMD_QNG_CONFLICT: | |
12274 | ASC_PRINT1("AscInitGetConfig: board %d: tag queuing enabled " | |
12275 | "w/o disconnects\n", boardp->id); | |
12276 | break; | |
12277 | default: | |
12278 | ASC_PRINT2("AscInitGetConfig: board %d: unknown warning: " | |
12279 | "0x%x\n", boardp->id, warn_code); | |
12280 | break; | |
12281 | } | |
1da177e4 | 12282 | |
51219358 MW |
12283 | if (asc_dvc->err_code != 0) { |
12284 | ASC_PRINT3("AscInitGetConfig: board %d error: init_state 0x%x, " | |
12285 | "err_code 0x%x\n", boardp->id, asc_dvc->init_state, | |
12286 | asc_dvc->err_code); | |
12287 | } | |
27c868c2 | 12288 | |
51219358 MW |
12289 | return asc_dvc->err_code; |
12290 | } | |
1da177e4 | 12291 | |
51219358 MW |
12292 | static int __devinit AscInitSetConfig(struct pci_dev *pdev, asc_board_t *boardp) |
12293 | { | |
12294 | ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var; | |
12295 | PortAddr iop_base = asc_dvc->iop_base; | |
12296 | unsigned short cfg_msw; | |
12297 | unsigned short warn_code = 0; | |
1da177e4 | 12298 | |
51219358 MW |
12299 | asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG; |
12300 | if (asc_dvc->err_code != 0) | |
12301 | return asc_dvc->err_code; | |
12302 | if (!AscFindSignature(asc_dvc->iop_base)) { | |
12303 | asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE; | |
12304 | return asc_dvc->err_code; | |
27c868c2 | 12305 | } |
1da177e4 | 12306 | |
51219358 MW |
12307 | cfg_msw = AscGetChipCfgMsw(iop_base); |
12308 | if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { | |
12309 | cfg_msw &= ~ASC_CFG_MSW_CLR_MASK; | |
12310 | warn_code |= ASC_WARN_CFG_MSW_RECOVER; | |
12311 | AscSetChipCfgMsw(iop_base, cfg_msw); | |
12312 | } | |
12313 | if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) != | |
12314 | asc_dvc->cfg->cmd_qng_enabled) { | |
12315 | asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled; | |
12316 | warn_code |= ASC_WARN_CMD_QNG_CONFLICT; | |
12317 | } | |
12318 | if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) { | |
12319 | warn_code |= ASC_WARN_AUTO_CONFIG; | |
12320 | } | |
12321 | if ((asc_dvc->bus_type & (ASC_IS_ISA | ASC_IS_VL)) != 0) { | |
12322 | if (AscSetChipIRQ(iop_base, asc_dvc->irq_no, asc_dvc->bus_type) | |
12323 | != asc_dvc->irq_no) { | |
12324 | asc_dvc->err_code |= ASC_IERR_SET_IRQ_NO; | |
27c868c2 | 12325 | } |
27c868c2 | 12326 | } |
51219358 MW |
12327 | #ifdef CONFIG_PCI |
12328 | if (asc_dvc->bus_type & ASC_IS_PCI) { | |
12329 | cfg_msw &= 0xFFC0; | |
12330 | AscSetChipCfgMsw(iop_base, cfg_msw); | |
12331 | if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) { | |
27c868c2 | 12332 | } else { |
51219358 MW |
12333 | if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) || |
12334 | (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) { | |
12335 | asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB; | |
12336 | asc_dvc->bug_fix_cntl |= | |
12337 | ASC_BUG_FIX_ASYN_USE_SYN; | |
12338 | } | |
27c868c2 | 12339 | } |
51219358 MW |
12340 | } else |
12341 | #endif /* CONFIG_PCI */ | |
12342 | if (asc_dvc->bus_type == ASC_IS_ISAPNP) { | |
12343 | if (AscGetChipVersion(iop_base, asc_dvc->bus_type) | |
12344 | == ASC_CHIP_VER_ASYN_BUG) { | |
12345 | asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN; | |
27c868c2 MW |
12346 | } |
12347 | } | |
51219358 MW |
12348 | if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) != |
12349 | asc_dvc->cfg->chip_scsi_id) { | |
12350 | asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID; | |
12351 | } | |
12352 | #ifdef CONFIG_ISA | |
12353 | if (asc_dvc->bus_type & ASC_IS_ISA) { | |
12354 | AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel); | |
12355 | AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed); | |
12356 | } | |
12357 | #endif /* CONFIG_ISA */ | |
1da177e4 | 12358 | |
51219358 MW |
12359 | asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG; |
12360 | ||
12361 | switch (warn_code) { | |
12362 | case 0: /* No error. */ | |
12363 | break; | |
12364 | case ASC_WARN_IO_PORT_ROTATE: | |
12365 | ASC_PRINT1("AscInitSetConfig: board %d: I/O port address " | |
12366 | "modified\n", boardp->id); | |
12367 | break; | |
12368 | case ASC_WARN_AUTO_CONFIG: | |
12369 | ASC_PRINT1("AscInitSetConfig: board %d: I/O port increment " | |
12370 | "switch enabled\n", boardp->id); | |
12371 | break; | |
12372 | case ASC_WARN_EEPROM_CHKSUM: | |
12373 | ASC_PRINT1("AscInitSetConfig: board %d: EEPROM checksum " | |
12374 | "error\n", boardp->id); | |
12375 | break; | |
12376 | case ASC_WARN_IRQ_MODIFIED: | |
12377 | ASC_PRINT1("AscInitSetConfig: board %d: IRQ modified\n", | |
12378 | boardp->id); | |
12379 | break; | |
12380 | case ASC_WARN_CMD_QNG_CONFLICT: | |
12381 | ASC_PRINT1("AscInitSetConfig: board %d: tag queuing w/o " | |
12382 | "disconnects\n", | |
12383 | boardp->id); | |
12384 | break; | |
12385 | default: | |
12386 | ASC_PRINT2("AscInitSetConfig: board %d: unknown warning: " | |
12387 | "0x%x\n", boardp->id, warn_code); | |
12388 | break; | |
27c868c2 | 12389 | } |
1da177e4 | 12390 | |
51219358 MW |
12391 | if (asc_dvc->err_code != 0) { |
12392 | ASC_PRINT3("AscInitSetConfig: board %d error: init_state 0x%x, " | |
12393 | "err_code 0x%x\n", boardp->id, asc_dvc->init_state, | |
12394 | asc_dvc->err_code); | |
12395 | } | |
27c868c2 | 12396 | |
51219358 MW |
12397 | return asc_dvc->err_code; |
12398 | } | |
27c868c2 | 12399 | |
51219358 MW |
12400 | /* |
12401 | * EEPROM Configuration. | |
12402 | * | |
12403 | * All drivers should use this structure to set the default EEPROM | |
12404 | * configuration. The BIOS now uses this structure when it is built. | |
12405 | * Additional structure information can be found in a_condor.h where | |
12406 | * the structure is defined. | |
12407 | * | |
12408 | * The *_Field_IsChar structs are needed to correct for endianness. | |
12409 | * These values are read from the board 16 bits at a time directly | |
12410 | * into the structs. Because some fields are char, the values will be | |
12411 | * in the wrong order. The *_Field_IsChar tells when to flip the | |
12412 | * bytes. Data read and written to PCI memory is automatically swapped | |
12413 | * on big-endian platforms so char fields read as words are actually being | |
12414 | * unswapped on big-endian platforms. | |
12415 | */ | |
12416 | static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config __devinitdata = { | |
12417 | ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */ | |
12418 | 0x0000, /* cfg_msw */ | |
12419 | 0xFFFF, /* disc_enable */ | |
12420 | 0xFFFF, /* wdtr_able */ | |
12421 | 0xFFFF, /* sdtr_able */ | |
12422 | 0xFFFF, /* start_motor */ | |
12423 | 0xFFFF, /* tagqng_able */ | |
12424 | 0xFFFF, /* bios_scan */ | |
12425 | 0, /* scam_tolerant */ | |
12426 | 7, /* adapter_scsi_id */ | |
12427 | 0, /* bios_boot_delay */ | |
12428 | 3, /* scsi_reset_delay */ | |
12429 | 0, /* bios_id_lun */ | |
12430 | 0, /* termination */ | |
12431 | 0, /* reserved1 */ | |
12432 | 0xFFE7, /* bios_ctrl */ | |
12433 | 0xFFFF, /* ultra_able */ | |
12434 | 0, /* reserved2 */ | |
12435 | ASC_DEF_MAX_HOST_QNG, /* max_host_qng */ | |
12436 | ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */ | |
12437 | 0, /* dvc_cntl */ | |
12438 | 0, /* bug_fix */ | |
12439 | 0, /* serial_number_word1 */ | |
12440 | 0, /* serial_number_word2 */ | |
12441 | 0, /* serial_number_word3 */ | |
12442 | 0, /* check_sum */ | |
12443 | {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} | |
12444 | , /* oem_name[16] */ | |
12445 | 0, /* dvc_err_code */ | |
12446 | 0, /* adv_err_code */ | |
12447 | 0, /* adv_err_addr */ | |
12448 | 0, /* saved_dvc_err_code */ | |
12449 | 0, /* saved_adv_err_code */ | |
12450 | 0, /* saved_adv_err_addr */ | |
12451 | 0 /* num_of_err */ | |
12452 | }; | |
27c868c2 | 12453 | |
51219358 MW |
12454 | static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar __devinitdata = { |
12455 | 0, /* cfg_lsw */ | |
12456 | 0, /* cfg_msw */ | |
12457 | 0, /* -disc_enable */ | |
12458 | 0, /* wdtr_able */ | |
12459 | 0, /* sdtr_able */ | |
12460 | 0, /* start_motor */ | |
12461 | 0, /* tagqng_able */ | |
12462 | 0, /* bios_scan */ | |
12463 | 0, /* scam_tolerant */ | |
12464 | 1, /* adapter_scsi_id */ | |
12465 | 1, /* bios_boot_delay */ | |
12466 | 1, /* scsi_reset_delay */ | |
12467 | 1, /* bios_id_lun */ | |
12468 | 1, /* termination */ | |
12469 | 1, /* reserved1 */ | |
12470 | 0, /* bios_ctrl */ | |
12471 | 0, /* ultra_able */ | |
12472 | 0, /* reserved2 */ | |
12473 | 1, /* max_host_qng */ | |
12474 | 1, /* max_dvc_qng */ | |
12475 | 0, /* dvc_cntl */ | |
12476 | 0, /* bug_fix */ | |
12477 | 0, /* serial_number_word1 */ | |
12478 | 0, /* serial_number_word2 */ | |
12479 | 0, /* serial_number_word3 */ | |
12480 | 0, /* check_sum */ | |
12481 | {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1} | |
12482 | , /* oem_name[16] */ | |
12483 | 0, /* dvc_err_code */ | |
12484 | 0, /* adv_err_code */ | |
12485 | 0, /* adv_err_addr */ | |
12486 | 0, /* saved_dvc_err_code */ | |
12487 | 0, /* saved_adv_err_code */ | |
12488 | 0, /* saved_adv_err_addr */ | |
12489 | 0 /* num_of_err */ | |
12490 | }; | |
1da177e4 | 12491 | |
51219358 MW |
12492 | static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config __devinitdata = { |
12493 | ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ | |
12494 | 0x0000, /* 01 cfg_msw */ | |
12495 | 0xFFFF, /* 02 disc_enable */ | |
12496 | 0xFFFF, /* 03 wdtr_able */ | |
12497 | 0x4444, /* 04 sdtr_speed1 */ | |
12498 | 0xFFFF, /* 05 start_motor */ | |
12499 | 0xFFFF, /* 06 tagqng_able */ | |
12500 | 0xFFFF, /* 07 bios_scan */ | |
12501 | 0, /* 08 scam_tolerant */ | |
12502 | 7, /* 09 adapter_scsi_id */ | |
12503 | 0, /* bios_boot_delay */ | |
12504 | 3, /* 10 scsi_reset_delay */ | |
12505 | 0, /* bios_id_lun */ | |
12506 | 0, /* 11 termination_se */ | |
12507 | 0, /* termination_lvd */ | |
12508 | 0xFFE7, /* 12 bios_ctrl */ | |
12509 | 0x4444, /* 13 sdtr_speed2 */ | |
12510 | 0x4444, /* 14 sdtr_speed3 */ | |
12511 | ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ | |
12512 | ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */ | |
12513 | 0, /* 16 dvc_cntl */ | |
12514 | 0x4444, /* 17 sdtr_speed4 */ | |
12515 | 0, /* 18 serial_number_word1 */ | |
12516 | 0, /* 19 serial_number_word2 */ | |
12517 | 0, /* 20 serial_number_word3 */ | |
12518 | 0, /* 21 check_sum */ | |
12519 | {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} | |
12520 | , /* 22-29 oem_name[16] */ | |
12521 | 0, /* 30 dvc_err_code */ | |
12522 | 0, /* 31 adv_err_code */ | |
12523 | 0, /* 32 adv_err_addr */ | |
12524 | 0, /* 33 saved_dvc_err_code */ | |
12525 | 0, /* 34 saved_adv_err_code */ | |
12526 | 0, /* 35 saved_adv_err_addr */ | |
12527 | 0, /* 36 reserved */ | |
12528 | 0, /* 37 reserved */ | |
12529 | 0, /* 38 reserved */ | |
12530 | 0, /* 39 reserved */ | |
12531 | 0, /* 40 reserved */ | |
12532 | 0, /* 41 reserved */ | |
12533 | 0, /* 42 reserved */ | |
12534 | 0, /* 43 reserved */ | |
12535 | 0, /* 44 reserved */ | |
12536 | 0, /* 45 reserved */ | |
12537 | 0, /* 46 reserved */ | |
12538 | 0, /* 47 reserved */ | |
12539 | 0, /* 48 reserved */ | |
12540 | 0, /* 49 reserved */ | |
12541 | 0, /* 50 reserved */ | |
12542 | 0, /* 51 reserved */ | |
12543 | 0, /* 52 reserved */ | |
12544 | 0, /* 53 reserved */ | |
12545 | 0, /* 54 reserved */ | |
12546 | 0, /* 55 reserved */ | |
12547 | 0, /* 56 cisptr_lsw */ | |
12548 | 0, /* 57 cisprt_msw */ | |
12549 | PCI_VENDOR_ID_ASP, /* 58 subsysvid */ | |
12550 | PCI_DEVICE_ID_38C0800_REV1, /* 59 subsysid */ | |
12551 | 0, /* 60 reserved */ | |
12552 | 0, /* 61 reserved */ | |
12553 | 0, /* 62 reserved */ | |
12554 | 0 /* 63 reserved */ | |
12555 | }; | |
27c868c2 | 12556 | |
51219358 MW |
12557 | static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar __devinitdata = { |
12558 | 0, /* 00 cfg_lsw */ | |
12559 | 0, /* 01 cfg_msw */ | |
12560 | 0, /* 02 disc_enable */ | |
12561 | 0, /* 03 wdtr_able */ | |
12562 | 0, /* 04 sdtr_speed1 */ | |
12563 | 0, /* 05 start_motor */ | |
12564 | 0, /* 06 tagqng_able */ | |
12565 | 0, /* 07 bios_scan */ | |
12566 | 0, /* 08 scam_tolerant */ | |
12567 | 1, /* 09 adapter_scsi_id */ | |
12568 | 1, /* bios_boot_delay */ | |
12569 | 1, /* 10 scsi_reset_delay */ | |
12570 | 1, /* bios_id_lun */ | |
12571 | 1, /* 11 termination_se */ | |
12572 | 1, /* termination_lvd */ | |
12573 | 0, /* 12 bios_ctrl */ | |
12574 | 0, /* 13 sdtr_speed2 */ | |
12575 | 0, /* 14 sdtr_speed3 */ | |
12576 | 1, /* 15 max_host_qng */ | |
12577 | 1, /* max_dvc_qng */ | |
12578 | 0, /* 16 dvc_cntl */ | |
12579 | 0, /* 17 sdtr_speed4 */ | |
12580 | 0, /* 18 serial_number_word1 */ | |
12581 | 0, /* 19 serial_number_word2 */ | |
12582 | 0, /* 20 serial_number_word3 */ | |
12583 | 0, /* 21 check_sum */ | |
12584 | {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1} | |
12585 | , /* 22-29 oem_name[16] */ | |
12586 | 0, /* 30 dvc_err_code */ | |
12587 | 0, /* 31 adv_err_code */ | |
12588 | 0, /* 32 adv_err_addr */ | |
12589 | 0, /* 33 saved_dvc_err_code */ | |
12590 | 0, /* 34 saved_adv_err_code */ | |
12591 | 0, /* 35 saved_adv_err_addr */ | |
12592 | 0, /* 36 reserved */ | |
12593 | 0, /* 37 reserved */ | |
12594 | 0, /* 38 reserved */ | |
12595 | 0, /* 39 reserved */ | |
12596 | 0, /* 40 reserved */ | |
12597 | 0, /* 41 reserved */ | |
12598 | 0, /* 42 reserved */ | |
12599 | 0, /* 43 reserved */ | |
12600 | 0, /* 44 reserved */ | |
12601 | 0, /* 45 reserved */ | |
12602 | 0, /* 46 reserved */ | |
12603 | 0, /* 47 reserved */ | |
12604 | 0, /* 48 reserved */ | |
12605 | 0, /* 49 reserved */ | |
12606 | 0, /* 50 reserved */ | |
12607 | 0, /* 51 reserved */ | |
12608 | 0, /* 52 reserved */ | |
12609 | 0, /* 53 reserved */ | |
12610 | 0, /* 54 reserved */ | |
12611 | 0, /* 55 reserved */ | |
12612 | 0, /* 56 cisptr_lsw */ | |
12613 | 0, /* 57 cisprt_msw */ | |
12614 | 0, /* 58 subsysvid */ | |
12615 | 0, /* 59 subsysid */ | |
12616 | 0, /* 60 reserved */ | |
12617 | 0, /* 61 reserved */ | |
12618 | 0, /* 62 reserved */ | |
12619 | 0 /* 63 reserved */ | |
12620 | }; | |
27c868c2 | 12621 | |
51219358 MW |
12622 | static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config __devinitdata = { |
12623 | ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ | |
12624 | 0x0000, /* 01 cfg_msw */ | |
12625 | 0xFFFF, /* 02 disc_enable */ | |
12626 | 0xFFFF, /* 03 wdtr_able */ | |
12627 | 0x5555, /* 04 sdtr_speed1 */ | |
12628 | 0xFFFF, /* 05 start_motor */ | |
12629 | 0xFFFF, /* 06 tagqng_able */ | |
12630 | 0xFFFF, /* 07 bios_scan */ | |
12631 | 0, /* 08 scam_tolerant */ | |
12632 | 7, /* 09 adapter_scsi_id */ | |
12633 | 0, /* bios_boot_delay */ | |
12634 | 3, /* 10 scsi_reset_delay */ | |
12635 | 0, /* bios_id_lun */ | |
12636 | 0, /* 11 termination_se */ | |
12637 | 0, /* termination_lvd */ | |
12638 | 0xFFE7, /* 12 bios_ctrl */ | |
12639 | 0x5555, /* 13 sdtr_speed2 */ | |
12640 | 0x5555, /* 14 sdtr_speed3 */ | |
12641 | ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ | |
12642 | ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */ | |
12643 | 0, /* 16 dvc_cntl */ | |
12644 | 0x5555, /* 17 sdtr_speed4 */ | |
12645 | 0, /* 18 serial_number_word1 */ | |
12646 | 0, /* 19 serial_number_word2 */ | |
12647 | 0, /* 20 serial_number_word3 */ | |
12648 | 0, /* 21 check_sum */ | |
12649 | {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} | |
12650 | , /* 22-29 oem_name[16] */ | |
12651 | 0, /* 30 dvc_err_code */ | |
12652 | 0, /* 31 adv_err_code */ | |
12653 | 0, /* 32 adv_err_addr */ | |
12654 | 0, /* 33 saved_dvc_err_code */ | |
12655 | 0, /* 34 saved_adv_err_code */ | |
12656 | 0, /* 35 saved_adv_err_addr */ | |
12657 | 0, /* 36 reserved */ | |
12658 | 0, /* 37 reserved */ | |
12659 | 0, /* 38 reserved */ | |
12660 | 0, /* 39 reserved */ | |
12661 | 0, /* 40 reserved */ | |
12662 | 0, /* 41 reserved */ | |
12663 | 0, /* 42 reserved */ | |
12664 | 0, /* 43 reserved */ | |
12665 | 0, /* 44 reserved */ | |
12666 | 0, /* 45 reserved */ | |
12667 | 0, /* 46 reserved */ | |
12668 | 0, /* 47 reserved */ | |
12669 | 0, /* 48 reserved */ | |
12670 | 0, /* 49 reserved */ | |
12671 | 0, /* 50 reserved */ | |
12672 | 0, /* 51 reserved */ | |
12673 | 0, /* 52 reserved */ | |
12674 | 0, /* 53 reserved */ | |
12675 | 0, /* 54 reserved */ | |
12676 | 0, /* 55 reserved */ | |
12677 | 0, /* 56 cisptr_lsw */ | |
12678 | 0, /* 57 cisprt_msw */ | |
12679 | PCI_VENDOR_ID_ASP, /* 58 subsysvid */ | |
12680 | PCI_DEVICE_ID_38C1600_REV1, /* 59 subsysid */ | |
12681 | 0, /* 60 reserved */ | |
12682 | 0, /* 61 reserved */ | |
12683 | 0, /* 62 reserved */ | |
12684 | 0 /* 63 reserved */ | |
12685 | }; | |
1da177e4 | 12686 | |
51219358 MW |
12687 | static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar __devinitdata = { |
12688 | 0, /* 00 cfg_lsw */ | |
12689 | 0, /* 01 cfg_msw */ | |
12690 | 0, /* 02 disc_enable */ | |
12691 | 0, /* 03 wdtr_able */ | |
12692 | 0, /* 04 sdtr_speed1 */ | |
12693 | 0, /* 05 start_motor */ | |
12694 | 0, /* 06 tagqng_able */ | |
12695 | 0, /* 07 bios_scan */ | |
12696 | 0, /* 08 scam_tolerant */ | |
12697 | 1, /* 09 adapter_scsi_id */ | |
12698 | 1, /* bios_boot_delay */ | |
12699 | 1, /* 10 scsi_reset_delay */ | |
12700 | 1, /* bios_id_lun */ | |
12701 | 1, /* 11 termination_se */ | |
12702 | 1, /* termination_lvd */ | |
12703 | 0, /* 12 bios_ctrl */ | |
12704 | 0, /* 13 sdtr_speed2 */ | |
12705 | 0, /* 14 sdtr_speed3 */ | |
12706 | 1, /* 15 max_host_qng */ | |
12707 | 1, /* max_dvc_qng */ | |
12708 | 0, /* 16 dvc_cntl */ | |
12709 | 0, /* 17 sdtr_speed4 */ | |
12710 | 0, /* 18 serial_number_word1 */ | |
12711 | 0, /* 19 serial_number_word2 */ | |
12712 | 0, /* 20 serial_number_word3 */ | |
12713 | 0, /* 21 check_sum */ | |
12714 | {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1} | |
12715 | , /* 22-29 oem_name[16] */ | |
12716 | 0, /* 30 dvc_err_code */ | |
12717 | 0, /* 31 adv_err_code */ | |
12718 | 0, /* 32 adv_err_addr */ | |
12719 | 0, /* 33 saved_dvc_err_code */ | |
12720 | 0, /* 34 saved_adv_err_code */ | |
12721 | 0, /* 35 saved_adv_err_addr */ | |
12722 | 0, /* 36 reserved */ | |
12723 | 0, /* 37 reserved */ | |
12724 | 0, /* 38 reserved */ | |
12725 | 0, /* 39 reserved */ | |
12726 | 0, /* 40 reserved */ | |
12727 | 0, /* 41 reserved */ | |
12728 | 0, /* 42 reserved */ | |
12729 | 0, /* 43 reserved */ | |
12730 | 0, /* 44 reserved */ | |
12731 | 0, /* 45 reserved */ | |
12732 | 0, /* 46 reserved */ | |
12733 | 0, /* 47 reserved */ | |
12734 | 0, /* 48 reserved */ | |
12735 | 0, /* 49 reserved */ | |
12736 | 0, /* 50 reserved */ | |
12737 | 0, /* 51 reserved */ | |
12738 | 0, /* 52 reserved */ | |
12739 | 0, /* 53 reserved */ | |
12740 | 0, /* 54 reserved */ | |
12741 | 0, /* 55 reserved */ | |
12742 | 0, /* 56 cisptr_lsw */ | |
12743 | 0, /* 57 cisprt_msw */ | |
12744 | 0, /* 58 subsysvid */ | |
12745 | 0, /* 59 subsysid */ | |
12746 | 0, /* 60 reserved */ | |
12747 | 0, /* 61 reserved */ | |
12748 | 0, /* 62 reserved */ | |
12749 | 0 /* 63 reserved */ | |
12750 | }; | |
1da177e4 | 12751 | |
51219358 | 12752 | #ifdef CONFIG_PCI |
1da177e4 | 12753 | /* |
51219358 | 12754 | * Wait for EEPROM command to complete |
1da177e4 | 12755 | */ |
51219358 | 12756 | static void __devinit AdvWaitEEPCmd(AdvPortAddr iop_base) |
1da177e4 | 12757 | { |
51219358 | 12758 | int eep_delay_ms; |
27c868c2 | 12759 | |
51219358 MW |
12760 | for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) { |
12761 | if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) & | |
12762 | ASC_EEP_CMD_DONE) { | |
12763 | break; | |
27c868c2 | 12764 | } |
51219358 | 12765 | mdelay(1); |
27c868c2 | 12766 | } |
51219358 MW |
12767 | if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) == |
12768 | 0) | |
12769 | BUG(); | |
1da177e4 LT |
12770 | } |
12771 | ||
12772 | /* | |
51219358 | 12773 | * Read the EEPROM from specified location |
1da177e4 | 12774 | */ |
51219358 MW |
12775 | static ushort __devinit AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr) |
12776 | { | |
12777 | AdvWriteWordRegister(iop_base, IOPW_EE_CMD, | |
12778 | ASC_EEP_CMD_READ | eep_word_addr); | |
12779 | AdvWaitEEPCmd(iop_base); | |
12780 | return AdvReadWordRegister(iop_base, IOPW_EE_DATA); | |
12781 | } | |
12782 | ||
12783 | /* | |
12784 | * Write the EEPROM from 'cfg_buf'. | |
12785 | */ | |
12786 | void __devinit | |
12787 | AdvSet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf) | |
1da177e4 | 12788 | { |
27c868c2 | 12789 | ushort *wbuf; |
51219358 | 12790 | ushort addr, chksum; |
27c868c2 MW |
12791 | ushort *charfields; |
12792 | ||
27c868c2 | 12793 | wbuf = (ushort *)cfg_buf; |
51219358 | 12794 | charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar; |
27c868c2 MW |
12795 | chksum = 0; |
12796 | ||
51219358 MW |
12797 | AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); |
12798 | AdvWaitEEPCmd(iop_base); | |
12799 | ||
12800 | /* | |
12801 | * Write EEPROM from word 0 to word 20. | |
12802 | */ | |
12803 | for (addr = ADV_EEP_DVC_CFG_BEGIN; | |
12804 | addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) { | |
12805 | ushort word; | |
12806 | ||
27c868c2 | 12807 | if (*charfields++) { |
51219358 | 12808 | word = cpu_to_le16(*wbuf); |
27c868c2 | 12809 | } else { |
51219358 | 12810 | word = *wbuf; |
27c868c2 | 12811 | } |
51219358 MW |
12812 | chksum += *wbuf; /* Checksum is calculated from word values. */ |
12813 | AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word); | |
12814 | AdvWriteWordRegister(iop_base, IOPW_EE_CMD, | |
12815 | ASC_EEP_CMD_WRITE | addr); | |
12816 | AdvWaitEEPCmd(iop_base); | |
12817 | mdelay(ADV_EEP_DELAY_MS); | |
27c868c2 | 12818 | } |
51219358 MW |
12819 | |
12820 | /* | |
12821 | * Write EEPROM checksum at word 21. | |
12822 | */ | |
12823 | AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum); | |
12824 | AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr); | |
12825 | AdvWaitEEPCmd(iop_base); | |
27c868c2 MW |
12826 | wbuf++; |
12827 | charfields++; | |
12828 | ||
51219358 MW |
12829 | /* |
12830 | * Write EEPROM OEM name at words 22 to 29. | |
12831 | */ | |
12832 | for (addr = ADV_EEP_DVC_CTL_BEGIN; | |
12833 | addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) { | |
12834 | ushort word; | |
12835 | ||
27c868c2 | 12836 | if (*charfields++) { |
51219358 MW |
12837 | word = cpu_to_le16(*wbuf); |
12838 | } else { | |
12839 | word = *wbuf; | |
27c868c2 | 12840 | } |
51219358 MW |
12841 | AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word); |
12842 | AdvWriteWordRegister(iop_base, IOPW_EE_CMD, | |
12843 | ASC_EEP_CMD_WRITE | addr); | |
12844 | AdvWaitEEPCmd(iop_base); | |
27c868c2 | 12845 | } |
51219358 MW |
12846 | AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE); |
12847 | AdvWaitEEPCmd(iop_base); | |
1da177e4 LT |
12848 | } |
12849 | ||
12850 | /* | |
51219358 | 12851 | * Write the EEPROM from 'cfg_buf'. |
1da177e4 | 12852 | */ |
51219358 MW |
12853 | void __devinit |
12854 | AdvSet38C0800EEPConfig(AdvPortAddr iop_base, ADVEEP_38C0800_CONFIG *cfg_buf) | |
1da177e4 | 12855 | { |
27c868c2 | 12856 | ushort *wbuf; |
27c868c2 | 12857 | ushort *charfields; |
51219358 | 12858 | ushort addr, chksum; |
27c868c2 | 12859 | |
27c868c2 | 12860 | wbuf = (ushort *)cfg_buf; |
51219358 | 12861 | charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar; |
27c868c2 MW |
12862 | chksum = 0; |
12863 | ||
51219358 MW |
12864 | AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); |
12865 | AdvWaitEEPCmd(iop_base); | |
12866 | ||
12867 | /* | |
12868 | * Write EEPROM from word 0 to word 20. | |
12869 | */ | |
12870 | for (addr = ADV_EEP_DVC_CFG_BEGIN; | |
12871 | addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) { | |
12872 | ushort word; | |
12873 | ||
27c868c2 | 12874 | if (*charfields++) { |
51219358 | 12875 | word = cpu_to_le16(*wbuf); |
27c868c2 | 12876 | } else { |
51219358 | 12877 | word = *wbuf; |
27c868c2 | 12878 | } |
51219358 MW |
12879 | chksum += *wbuf; /* Checksum is calculated from word values. */ |
12880 | AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word); | |
12881 | AdvWriteWordRegister(iop_base, IOPW_EE_CMD, | |
12882 | ASC_EEP_CMD_WRITE | addr); | |
12883 | AdvWaitEEPCmd(iop_base); | |
12884 | mdelay(ADV_EEP_DELAY_MS); | |
27c868c2 | 12885 | } |
51219358 MW |
12886 | |
12887 | /* | |
12888 | * Write EEPROM checksum at word 21. | |
12889 | */ | |
12890 | AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum); | |
12891 | AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr); | |
12892 | AdvWaitEEPCmd(iop_base); | |
27c868c2 MW |
12893 | wbuf++; |
12894 | charfields++; | |
12895 | ||
51219358 MW |
12896 | /* |
12897 | * Write EEPROM OEM name at words 22 to 29. | |
12898 | */ | |
12899 | for (addr = ADV_EEP_DVC_CTL_BEGIN; | |
12900 | addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) { | |
12901 | ushort word; | |
12902 | ||
27c868c2 | 12903 | if (*charfields++) { |
51219358 MW |
12904 | word = cpu_to_le16(*wbuf); |
12905 | } else { | |
12906 | word = *wbuf; | |
27c868c2 | 12907 | } |
51219358 MW |
12908 | AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word); |
12909 | AdvWriteWordRegister(iop_base, IOPW_EE_CMD, | |
12910 | ASC_EEP_CMD_WRITE | addr); | |
12911 | AdvWaitEEPCmd(iop_base); | |
27c868c2 | 12912 | } |
51219358 | 12913 | AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE); |
27c868c2 | 12914 | AdvWaitEEPCmd(iop_base); |
1da177e4 LT |
12915 | } |
12916 | ||
12917 | /* | |
12918 | * Write the EEPROM from 'cfg_buf'. | |
12919 | */ | |
78e77d8b | 12920 | void __devinit |
51219358 | 12921 | AdvSet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf) |
1da177e4 | 12922 | { |
27c868c2 | 12923 | ushort *wbuf; |
27c868c2 | 12924 | ushort *charfields; |
51219358 | 12925 | ushort addr, chksum; |
27c868c2 MW |
12926 | |
12927 | wbuf = (ushort *)cfg_buf; | |
51219358 | 12928 | charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar; |
27c868c2 MW |
12929 | chksum = 0; |
12930 | ||
12931 | AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); | |
12932 | AdvWaitEEPCmd(iop_base); | |
12933 | ||
12934 | /* | |
12935 | * Write EEPROM from word 0 to word 20. | |
12936 | */ | |
12937 | for (addr = ADV_EEP_DVC_CFG_BEGIN; | |
12938 | addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) { | |
12939 | ushort word; | |
12940 | ||
12941 | if (*charfields++) { | |
12942 | word = cpu_to_le16(*wbuf); | |
12943 | } else { | |
12944 | word = *wbuf; | |
12945 | } | |
12946 | chksum += *wbuf; /* Checksum is calculated from word values. */ | |
12947 | AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word); | |
12948 | AdvWriteWordRegister(iop_base, IOPW_EE_CMD, | |
12949 | ASC_EEP_CMD_WRITE | addr); | |
12950 | AdvWaitEEPCmd(iop_base); | |
b009bef6 | 12951 | mdelay(ADV_EEP_DELAY_MS); |
27c868c2 | 12952 | } |
1da177e4 | 12953 | |
27c868c2 MW |
12954 | /* |
12955 | * Write EEPROM checksum at word 21. | |
12956 | */ | |
12957 | AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum); | |
12958 | AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr); | |
12959 | AdvWaitEEPCmd(iop_base); | |
12960 | wbuf++; | |
12961 | charfields++; | |
12962 | ||
12963 | /* | |
12964 | * Write EEPROM OEM name at words 22 to 29. | |
12965 | */ | |
12966 | for (addr = ADV_EEP_DVC_CTL_BEGIN; | |
12967 | addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) { | |
12968 | ushort word; | |
12969 | ||
12970 | if (*charfields++) { | |
12971 | word = cpu_to_le16(*wbuf); | |
12972 | } else { | |
12973 | word = *wbuf; | |
12974 | } | |
12975 | AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word); | |
12976 | AdvWriteWordRegister(iop_base, IOPW_EE_CMD, | |
12977 | ASC_EEP_CMD_WRITE | addr); | |
12978 | AdvWaitEEPCmd(iop_base); | |
12979 | } | |
12980 | AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE); | |
12981 | AdvWaitEEPCmd(iop_base); | |
1da177e4 LT |
12982 | } |
12983 | ||
12984 | /* | |
51219358 MW |
12985 | * Read EEPROM configuration into the specified buffer. |
12986 | * | |
12987 | * Return a checksum based on the EEPROM configuration read. | |
1da177e4 | 12988 | */ |
51219358 MW |
12989 | static ushort __devinit |
12990 | AdvGet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf) | |
1da177e4 | 12991 | { |
51219358 | 12992 | ushort wval, chksum; |
27c868c2 | 12993 | ushort *wbuf; |
51219358 | 12994 | int eep_addr; |
27c868c2 | 12995 | ushort *charfields; |
27c868c2 | 12996 | |
51219358 | 12997 | charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar; |
27c868c2 | 12998 | wbuf = (ushort *)cfg_buf; |
27c868c2 MW |
12999 | chksum = 0; |
13000 | ||
51219358 MW |
13001 | for (eep_addr = ADV_EEP_DVC_CFG_BEGIN; |
13002 | eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) { | |
13003 | wval = AdvReadEEPWord(iop_base, eep_addr); | |
13004 | chksum += wval; /* Checksum is calculated from word values. */ | |
13005 | if (*charfields++) { | |
13006 | *wbuf = le16_to_cpu(wval); | |
13007 | } else { | |
13008 | *wbuf = wval; | |
13009 | } | |
13010 | } | |
13011 | /* Read checksum word. */ | |
13012 | *wbuf = AdvReadEEPWord(iop_base, eep_addr); | |
13013 | wbuf++; | |
13014 | charfields++; | |
27c868c2 | 13015 | |
51219358 MW |
13016 | /* Read rest of EEPROM not covered by the checksum. */ |
13017 | for (eep_addr = ADV_EEP_DVC_CTL_BEGIN; | |
13018 | eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) { | |
13019 | *wbuf = AdvReadEEPWord(iop_base, eep_addr); | |
13020 | if (*charfields++) { | |
13021 | *wbuf = le16_to_cpu(*wbuf); | |
13022 | } | |
13023 | } | |
13024 | return chksum; | |
13025 | } | |
13026 | ||
13027 | /* | |
13028 | * Read EEPROM configuration into the specified buffer. | |
13029 | * | |
13030 | * Return a checksum based on the EEPROM configuration read. | |
13031 | */ | |
13032 | static ushort __devinit | |
13033 | AdvGet38C0800EEPConfig(AdvPortAddr iop_base, ADVEEP_38C0800_CONFIG *cfg_buf) | |
13034 | { | |
13035 | ushort wval, chksum; | |
13036 | ushort *wbuf; | |
13037 | int eep_addr; | |
13038 | ushort *charfields; | |
27c868c2 | 13039 | |
51219358 MW |
13040 | charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar; |
13041 | wbuf = (ushort *)cfg_buf; | |
13042 | chksum = 0; | |
13043 | ||
13044 | for (eep_addr = ADV_EEP_DVC_CFG_BEGIN; | |
13045 | eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) { | |
13046 | wval = AdvReadEEPWord(iop_base, eep_addr); | |
13047 | chksum += wval; /* Checksum is calculated from word values. */ | |
27c868c2 | 13048 | if (*charfields++) { |
51219358 | 13049 | *wbuf = le16_to_cpu(wval); |
27c868c2 | 13050 | } else { |
51219358 | 13051 | *wbuf = wval; |
27c868c2 | 13052 | } |
27c868c2 | 13053 | } |
51219358 MW |
13054 | /* Read checksum word. */ |
13055 | *wbuf = AdvReadEEPWord(iop_base, eep_addr); | |
27c868c2 MW |
13056 | wbuf++; |
13057 | charfields++; | |
13058 | ||
51219358 MW |
13059 | /* Read rest of EEPROM not covered by the checksum. */ |
13060 | for (eep_addr = ADV_EEP_DVC_CTL_BEGIN; | |
13061 | eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) { | |
13062 | *wbuf = AdvReadEEPWord(iop_base, eep_addr); | |
27c868c2 | 13063 | if (*charfields++) { |
51219358 | 13064 | *wbuf = le16_to_cpu(*wbuf); |
27c868c2 | 13065 | } |
27c868c2 | 13066 | } |
51219358 | 13067 | return chksum; |
1da177e4 LT |
13068 | } |
13069 | ||
13070 | /* | |
51219358 MW |
13071 | * Read EEPROM configuration into the specified buffer. |
13072 | * | |
13073 | * Return a checksum based on the EEPROM configuration read. | |
1da177e4 | 13074 | */ |
51219358 MW |
13075 | static ushort __devinit |
13076 | AdvGet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf) | |
1da177e4 | 13077 | { |
51219358 | 13078 | ushort wval, chksum; |
27c868c2 | 13079 | ushort *wbuf; |
51219358 | 13080 | int eep_addr; |
27c868c2 | 13081 | ushort *charfields; |
27c868c2 | 13082 | |
27c868c2 | 13083 | charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar; |
51219358 | 13084 | wbuf = (ushort *)cfg_buf; |
27c868c2 MW |
13085 | chksum = 0; |
13086 | ||
51219358 MW |
13087 | for (eep_addr = ADV_EEP_DVC_CFG_BEGIN; |
13088 | eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) { | |
13089 | wval = AdvReadEEPWord(iop_base, eep_addr); | |
13090 | chksum += wval; /* Checksum is calculated from word values. */ | |
27c868c2 | 13091 | if (*charfields++) { |
51219358 | 13092 | *wbuf = le16_to_cpu(wval); |
27c868c2 | 13093 | } else { |
51219358 | 13094 | *wbuf = wval; |
27c868c2 | 13095 | } |
27c868c2 | 13096 | } |
51219358 MW |
13097 | /* Read checksum word. */ |
13098 | *wbuf = AdvReadEEPWord(iop_base, eep_addr); | |
27c868c2 MW |
13099 | wbuf++; |
13100 | charfields++; | |
13101 | ||
51219358 MW |
13102 | /* Read rest of EEPROM not covered by the checksum. */ |
13103 | for (eep_addr = ADV_EEP_DVC_CTL_BEGIN; | |
13104 | eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) { | |
13105 | *wbuf = AdvReadEEPWord(iop_base, eep_addr); | |
27c868c2 | 13106 | if (*charfields++) { |
51219358 | 13107 | *wbuf = le16_to_cpu(*wbuf); |
27c868c2 | 13108 | } |
27c868c2 | 13109 | } |
51219358 | 13110 | return chksum; |
1da177e4 LT |
13111 | } |
13112 | ||
1da177e4 | 13113 | /* |
51219358 MW |
13114 | * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and |
13115 | * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while | |
13116 | * all of this is done. | |
1da177e4 | 13117 | * |
51219358 | 13118 | * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR. |
1da177e4 | 13119 | * |
51219358 MW |
13120 | * For a non-fatal error return a warning code. If there are no warnings |
13121 | * then 0 is returned. | |
1da177e4 | 13122 | * |
51219358 | 13123 | * Note: Chip is stopped on entry. |
1da177e4 | 13124 | */ |
51219358 | 13125 | static int __devinit AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc) |
1da177e4 | 13126 | { |
27c868c2 | 13127 | AdvPortAddr iop_base; |
51219358 MW |
13128 | ushort warn_code; |
13129 | ADVEEP_3550_CONFIG eep_config; | |
1da177e4 | 13130 | |
27c868c2 | 13131 | iop_base = asc_dvc->iop_base; |
1da177e4 | 13132 | |
51219358 | 13133 | warn_code = 0; |
27c868c2 MW |
13134 | |
13135 | /* | |
51219358 MW |
13136 | * Read the board's EEPROM configuration. |
13137 | * | |
13138 | * Set default values if a bad checksum is found. | |
27c868c2 | 13139 | */ |
51219358 MW |
13140 | if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) { |
13141 | warn_code |= ASC_WARN_EEPROM_CHKSUM; | |
27c868c2 | 13142 | |
51219358 MW |
13143 | /* |
13144 | * Set EEPROM default values. | |
13145 | */ | |
13146 | memcpy(&eep_config, &Default_3550_EEPROM_Config, | |
13147 | sizeof(ADVEEP_3550_CONFIG)); | |
27c868c2 | 13148 | |
51219358 MW |
13149 | /* |
13150 | * Assume the 6 byte board serial number that was read from | |
13151 | * EEPROM is correct even if the EEPROM checksum failed. | |
13152 | */ | |
13153 | eep_config.serial_number_word3 = | |
13154 | AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1); | |
27c868c2 | 13155 | |
51219358 MW |
13156 | eep_config.serial_number_word2 = |
13157 | AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2); | |
27c868c2 | 13158 | |
51219358 MW |
13159 | eep_config.serial_number_word1 = |
13160 | AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3); | |
27c868c2 | 13161 | |
51219358 MW |
13162 | AdvSet3550EEPConfig(iop_base, &eep_config); |
13163 | } | |
13164 | /* | |
13165 | * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the | |
13166 | * EEPROM configuration that was read. | |
13167 | * | |
13168 | * This is the mapping of EEPROM fields to Adv Library fields. | |
13169 | */ | |
13170 | asc_dvc->wdtr_able = eep_config.wdtr_able; | |
13171 | asc_dvc->sdtr_able = eep_config.sdtr_able; | |
13172 | asc_dvc->ultra_able = eep_config.ultra_able; | |
13173 | asc_dvc->tagqng_able = eep_config.tagqng_able; | |
13174 | asc_dvc->cfg->disc_enable = eep_config.disc_enable; | |
13175 | asc_dvc->max_host_qng = eep_config.max_host_qng; | |
13176 | asc_dvc->max_dvc_qng = eep_config.max_dvc_qng; | |
13177 | asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID); | |
13178 | asc_dvc->start_motor = eep_config.start_motor; | |
13179 | asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay; | |
13180 | asc_dvc->bios_ctrl = eep_config.bios_ctrl; | |
13181 | asc_dvc->no_scam = eep_config.scam_tolerant; | |
13182 | asc_dvc->cfg->serial1 = eep_config.serial_number_word1; | |
13183 | asc_dvc->cfg->serial2 = eep_config.serial_number_word2; | |
13184 | asc_dvc->cfg->serial3 = eep_config.serial_number_word3; | |
27c868c2 | 13185 | |
27c868c2 | 13186 | /* |
51219358 MW |
13187 | * Set the host maximum queuing (max. 253, min. 16) and the per device |
13188 | * maximum queuing (max. 63, min. 4). | |
27c868c2 | 13189 | */ |
51219358 MW |
13190 | if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) { |
13191 | eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; | |
13192 | } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) { | |
13193 | /* If the value is zero, assume it is uninitialized. */ | |
13194 | if (eep_config.max_host_qng == 0) { | |
13195 | eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; | |
13196 | } else { | |
13197 | eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG; | |
13198 | } | |
13199 | } | |
13200 | ||
13201 | if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) { | |
13202 | eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; | |
13203 | } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) { | |
13204 | /* If the value is zero, assume it is uninitialized. */ | |
13205 | if (eep_config.max_dvc_qng == 0) { | |
13206 | eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; | |
13207 | } else { | |
13208 | eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG; | |
13209 | } | |
13210 | } | |
27c868c2 MW |
13211 | |
13212 | /* | |
51219358 MW |
13213 | * If 'max_dvc_qng' is greater than 'max_host_qng', then |
13214 | * set 'max_dvc_qng' to 'max_host_qng'. | |
27c868c2 | 13215 | */ |
51219358 MW |
13216 | if (eep_config.max_dvc_qng > eep_config.max_host_qng) { |
13217 | eep_config.max_dvc_qng = eep_config.max_host_qng; | |
13218 | } | |
27c868c2 MW |
13219 | |
13220 | /* | |
51219358 MW |
13221 | * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng' |
13222 | * values based on possibly adjusted EEPROM values. | |
27c868c2 | 13223 | */ |
51219358 MW |
13224 | asc_dvc->max_host_qng = eep_config.max_host_qng; |
13225 | asc_dvc->max_dvc_qng = eep_config.max_dvc_qng; | |
27c868c2 MW |
13226 | |
13227 | /* | |
51219358 MW |
13228 | * If the EEPROM 'termination' field is set to automatic (0), then set |
13229 | * the ADV_DVC_CFG 'termination' field to automatic also. | |
13230 | * | |
13231 | * If the termination is specified with a non-zero 'termination' | |
13232 | * value check that a legal value is set and set the ADV_DVC_CFG | |
13233 | * 'termination' field appropriately. | |
27c868c2 | 13234 | */ |
51219358 MW |
13235 | if (eep_config.termination == 0) { |
13236 | asc_dvc->cfg->termination = 0; /* auto termination */ | |
13237 | } else { | |
13238 | /* Enable manual control with low off / high off. */ | |
13239 | if (eep_config.termination == 1) { | |
13240 | asc_dvc->cfg->termination = TERM_CTL_SEL; | |
27c868c2 | 13241 | |
51219358 MW |
13242 | /* Enable manual control with low off / high on. */ |
13243 | } else if (eep_config.termination == 2) { | |
13244 | asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H; | |
13245 | ||
13246 | /* Enable manual control with low on / high on. */ | |
13247 | } else if (eep_config.termination == 3) { | |
13248 | asc_dvc->cfg->termination = | |
13249 | TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L; | |
13250 | } else { | |
27c868c2 | 13251 | /* |
51219358 MW |
13252 | * The EEPROM 'termination' field contains a bad value. Use |
13253 | * automatic termination instead. | |
27c868c2 | 13254 | */ |
51219358 MW |
13255 | asc_dvc->cfg->termination = 0; |
13256 | warn_code |= ASC_WARN_EEPROM_TERMINATION; | |
27c868c2 | 13257 | } |
27c868c2 | 13258 | } |
1da177e4 | 13259 | |
51219358 | 13260 | return warn_code; |
1da177e4 LT |
13261 | } |
13262 | ||
13263 | /* | |
51219358 MW |
13264 | * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and |
13265 | * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while | |
13266 | * all of this is done. | |
1da177e4 | 13267 | * |
51219358 MW |
13268 | * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR. |
13269 | * | |
13270 | * For a non-fatal error return a warning code. If there are no warnings | |
13271 | * then 0 is returned. | |
13272 | * | |
13273 | * Note: Chip is stopped on entry. | |
1da177e4 | 13274 | */ |
51219358 | 13275 | static int __devinit AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc) |
1da177e4 | 13276 | { |
51219358 MW |
13277 | AdvPortAddr iop_base; |
13278 | ushort warn_code; | |
13279 | ADVEEP_38C0800_CONFIG eep_config; | |
13280 | uchar tid, termination; | |
13281 | ushort sdtr_speed = 0; | |
27c868c2 | 13282 | |
51219358 | 13283 | iop_base = asc_dvc->iop_base; |
1da177e4 | 13284 | |
51219358 | 13285 | warn_code = 0; |
27c868c2 MW |
13286 | |
13287 | /* | |
51219358 MW |
13288 | * Read the board's EEPROM configuration. |
13289 | * | |
13290 | * Set default values if a bad checksum is found. | |
27c868c2 | 13291 | */ |
51219358 MW |
13292 | if (AdvGet38C0800EEPConfig(iop_base, &eep_config) != |
13293 | eep_config.check_sum) { | |
13294 | warn_code |= ASC_WARN_EEPROM_CHKSUM; | |
27c868c2 | 13295 | |
51219358 MW |
13296 | /* |
13297 | * Set EEPROM default values. | |
13298 | */ | |
13299 | memcpy(&eep_config, &Default_38C0800_EEPROM_Config, | |
13300 | sizeof(ADVEEP_38C0800_CONFIG)); | |
1da177e4 | 13301 | |
51219358 MW |
13302 | /* |
13303 | * Assume the 6 byte board serial number that was read from | |
13304 | * EEPROM is correct even if the EEPROM checksum failed. | |
13305 | */ | |
13306 | eep_config.serial_number_word3 = | |
13307 | AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1); | |
1da177e4 | 13308 | |
51219358 MW |
13309 | eep_config.serial_number_word2 = |
13310 | AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2); | |
27c868c2 | 13311 | |
51219358 MW |
13312 | eep_config.serial_number_word1 = |
13313 | AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3); | |
27c868c2 | 13314 | |
51219358 | 13315 | AdvSet38C0800EEPConfig(iop_base, &eep_config); |
27c868c2 | 13316 | } |
27c868c2 | 13317 | /* |
51219358 MW |
13318 | * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the |
13319 | * EEPROM configuration that was read. | |
13320 | * | |
13321 | * This is the mapping of EEPROM fields to Adv Library fields. | |
27c868c2 | 13322 | */ |
51219358 MW |
13323 | asc_dvc->wdtr_able = eep_config.wdtr_able; |
13324 | asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1; | |
13325 | asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2; | |
13326 | asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3; | |
13327 | asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4; | |
13328 | asc_dvc->tagqng_able = eep_config.tagqng_able; | |
13329 | asc_dvc->cfg->disc_enable = eep_config.disc_enable; | |
13330 | asc_dvc->max_host_qng = eep_config.max_host_qng; | |
13331 | asc_dvc->max_dvc_qng = eep_config.max_dvc_qng; | |
13332 | asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID); | |
13333 | asc_dvc->start_motor = eep_config.start_motor; | |
13334 | asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay; | |
13335 | asc_dvc->bios_ctrl = eep_config.bios_ctrl; | |
13336 | asc_dvc->no_scam = eep_config.scam_tolerant; | |
13337 | asc_dvc->cfg->serial1 = eep_config.serial_number_word1; | |
13338 | asc_dvc->cfg->serial2 = eep_config.serial_number_word2; | |
13339 | asc_dvc->cfg->serial3 = eep_config.serial_number_word3; | |
27c868c2 MW |
13340 | |
13341 | /* | |
51219358 MW |
13342 | * For every Target ID if any of its 'sdtr_speed[1234]' bits |
13343 | * are set, then set an 'sdtr_able' bit for it. | |
27c868c2 | 13344 | */ |
51219358 MW |
13345 | asc_dvc->sdtr_able = 0; |
13346 | for (tid = 0; tid <= ADV_MAX_TID; tid++) { | |
13347 | if (tid == 0) { | |
13348 | sdtr_speed = asc_dvc->sdtr_speed1; | |
13349 | } else if (tid == 4) { | |
13350 | sdtr_speed = asc_dvc->sdtr_speed2; | |
13351 | } else if (tid == 8) { | |
13352 | sdtr_speed = asc_dvc->sdtr_speed3; | |
13353 | } else if (tid == 12) { | |
13354 | sdtr_speed = asc_dvc->sdtr_speed4; | |
13355 | } | |
13356 | if (sdtr_speed & ADV_MAX_TID) { | |
13357 | asc_dvc->sdtr_able |= (1 << tid); | |
13358 | } | |
13359 | sdtr_speed >>= 4; | |
13360 | } | |
27c868c2 MW |
13361 | |
13362 | /* | |
51219358 MW |
13363 | * Set the host maximum queuing (max. 253, min. 16) and the per device |
13364 | * maximum queuing (max. 63, min. 4). | |
27c868c2 | 13365 | */ |
51219358 MW |
13366 | if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) { |
13367 | eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; | |
13368 | } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) { | |
13369 | /* If the value is zero, assume it is uninitialized. */ | |
13370 | if (eep_config.max_host_qng == 0) { | |
13371 | eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; | |
13372 | } else { | |
13373 | eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG; | |
13374 | } | |
27c868c2 | 13375 | } |
1da177e4 | 13376 | |
51219358 MW |
13377 | if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) { |
13378 | eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; | |
13379 | } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) { | |
13380 | /* If the value is zero, assume it is uninitialized. */ | |
13381 | if (eep_config.max_dvc_qng == 0) { | |
13382 | eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; | |
13383 | } else { | |
13384 | eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG; | |
13385 | } | |
13386 | } | |
13387 | ||
13388 | /* | |
13389 | * If 'max_dvc_qng' is greater than 'max_host_qng', then | |
13390 | * set 'max_dvc_qng' to 'max_host_qng'. | |
13391 | */ | |
13392 | if (eep_config.max_dvc_qng > eep_config.max_host_qng) { | |
13393 | eep_config.max_dvc_qng = eep_config.max_host_qng; | |
27c868c2 | 13394 | } |
1da177e4 | 13395 | |
27c868c2 | 13396 | /* |
51219358 MW |
13397 | * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng' |
13398 | * values based on possibly adjusted EEPROM values. | |
27c868c2 | 13399 | */ |
51219358 MW |
13400 | asc_dvc->max_host_qng = eep_config.max_host_qng; |
13401 | asc_dvc->max_dvc_qng = eep_config.max_dvc_qng; | |
27c868c2 MW |
13402 | |
13403 | /* | |
51219358 MW |
13404 | * If the EEPROM 'termination' field is set to automatic (0), then set |
13405 | * the ADV_DVC_CFG 'termination' field to automatic also. | |
13406 | * | |
13407 | * If the termination is specified with a non-zero 'termination' | |
13408 | * value check that a legal value is set and set the ADV_DVC_CFG | |
13409 | * 'termination' field appropriately. | |
27c868c2 | 13410 | */ |
51219358 MW |
13411 | if (eep_config.termination_se == 0) { |
13412 | termination = 0; /* auto termination for SE */ | |
13413 | } else { | |
13414 | /* Enable manual control with low off / high off. */ | |
13415 | if (eep_config.termination_se == 1) { | |
13416 | termination = 0; | |
13417 | ||
13418 | /* Enable manual control with low off / high on. */ | |
13419 | } else if (eep_config.termination_se == 2) { | |
13420 | termination = TERM_SE_HI; | |
13421 | ||
13422 | /* Enable manual control with low on / high on. */ | |
13423 | } else if (eep_config.termination_se == 3) { | |
13424 | termination = TERM_SE; | |
13425 | } else { | |
13426 | /* | |
13427 | * The EEPROM 'termination_se' field contains a bad value. | |
13428 | * Use automatic termination instead. | |
13429 | */ | |
13430 | termination = 0; | |
13431 | warn_code |= ASC_WARN_EEPROM_TERMINATION; | |
13432 | } | |
27c868c2 | 13433 | } |
51219358 MW |
13434 | |
13435 | if (eep_config.termination_lvd == 0) { | |
13436 | asc_dvc->cfg->termination = termination; /* auto termination for LVD */ | |
13437 | } else { | |
13438 | /* Enable manual control with low off / high off. */ | |
13439 | if (eep_config.termination_lvd == 1) { | |
13440 | asc_dvc->cfg->termination = termination; | |
13441 | ||
13442 | /* Enable manual control with low off / high on. */ | |
13443 | } else if (eep_config.termination_lvd == 2) { | |
13444 | asc_dvc->cfg->termination = termination | TERM_LVD_HI; | |
13445 | ||
13446 | /* Enable manual control with low on / high on. */ | |
13447 | } else if (eep_config.termination_lvd == 3) { | |
13448 | asc_dvc->cfg->termination = termination | TERM_LVD; | |
13449 | } else { | |
13450 | /* | |
13451 | * The EEPROM 'termination_lvd' field contains a bad value. | |
13452 | * Use automatic termination instead. | |
13453 | */ | |
13454 | asc_dvc->cfg->termination = termination; | |
13455 | warn_code |= ASC_WARN_EEPROM_TERMINATION; | |
13456 | } | |
27c868c2 | 13457 | } |
1da177e4 | 13458 | |
51219358 | 13459 | return warn_code; |
1da177e4 LT |
13460 | } |
13461 | ||
13462 | /* | |
51219358 MW |
13463 | * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and |
13464 | * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while | |
13465 | * all of this is done. | |
1da177e4 | 13466 | * |
51219358 | 13467 | * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR. |
1da177e4 | 13468 | * |
51219358 MW |
13469 | * For a non-fatal error return a warning code. If there are no warnings |
13470 | * then 0 is returned. | |
1da177e4 | 13471 | * |
51219358 | 13472 | * Note: Chip is stopped on entry. |
1da177e4 | 13473 | */ |
51219358 | 13474 | static int __devinit AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc) |
1da177e4 | 13475 | { |
27c868c2 | 13476 | AdvPortAddr iop_base; |
51219358 MW |
13477 | ushort warn_code; |
13478 | ADVEEP_38C1600_CONFIG eep_config; | |
13479 | uchar tid, termination; | |
13480 | ushort sdtr_speed = 0; | |
1da177e4 | 13481 | |
27c868c2 MW |
13482 | iop_base = asc_dvc->iop_base; |
13483 | ||
51219358 | 13484 | warn_code = 0; |
27c868c2 | 13485 | |
51219358 MW |
13486 | /* |
13487 | * Read the board's EEPROM configuration. | |
13488 | * | |
13489 | * Set default values if a bad checksum is found. | |
13490 | */ | |
13491 | if (AdvGet38C1600EEPConfig(iop_base, &eep_config) != | |
13492 | eep_config.check_sum) { | |
13493 | struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc); | |
13494 | warn_code |= ASC_WARN_EEPROM_CHKSUM; | |
13495 | ||
13496 | /* | |
13497 | * Set EEPROM default values. | |
13498 | */ | |
13499 | memcpy(&eep_config, &Default_38C1600_EEPROM_Config, | |
13500 | sizeof(ADVEEP_38C1600_CONFIG)); | |
13501 | ||
13502 | if (PCI_FUNC(pdev->devfn) != 0) { | |
13503 | u8 ints; | |
13504 | /* | |
13505 | * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60 | |
13506 | * and old Mac system booting problem. The Expansion | |
13507 | * ROM must be disabled in Function 1 for these systems | |
13508 | */ | |
13509 | eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE; | |
13510 | /* | |
13511 | * Clear the INTAB (bit 11) if the GPIO 0 input | |
13512 | * indicates the Function 1 interrupt line is wired | |
13513 | * to INTB. | |
13514 | * | |
13515 | * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input: | |
13516 | * 1 - Function 1 interrupt line wired to INT A. | |
13517 | * 0 - Function 1 interrupt line wired to INT B. | |
13518 | * | |
13519 | * Note: Function 0 is always wired to INTA. | |
13520 | * Put all 5 GPIO bits in input mode and then read | |
13521 | * their input values. | |
13522 | */ | |
13523 | AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0); | |
13524 | ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA); | |
13525 | if ((ints & 0x01) == 0) | |
13526 | eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB; | |
13527 | } | |
13528 | ||
13529 | /* | |
13530 | * Assume the 6 byte board serial number that was read from | |
13531 | * EEPROM is correct even if the EEPROM checksum failed. | |
13532 | */ | |
13533 | eep_config.serial_number_word3 = | |
13534 | AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1); | |
13535 | eep_config.serial_number_word2 = | |
13536 | AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2); | |
13537 | eep_config.serial_number_word1 = | |
13538 | AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3); | |
13539 | ||
13540 | AdvSet38C1600EEPConfig(iop_base, &eep_config); | |
27c868c2 MW |
13541 | } |
13542 | ||
13543 | /* | |
51219358 MW |
13544 | * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the |
13545 | * EEPROM configuration that was read. | |
13546 | * | |
13547 | * This is the mapping of EEPROM fields to Adv Library fields. | |
27c868c2 | 13548 | */ |
51219358 MW |
13549 | asc_dvc->wdtr_able = eep_config.wdtr_able; |
13550 | asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1; | |
13551 | asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2; | |
13552 | asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3; | |
13553 | asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4; | |
13554 | asc_dvc->ppr_able = 0; | |
13555 | asc_dvc->tagqng_able = eep_config.tagqng_able; | |
13556 | asc_dvc->cfg->disc_enable = eep_config.disc_enable; | |
13557 | asc_dvc->max_host_qng = eep_config.max_host_qng; | |
13558 | asc_dvc->max_dvc_qng = eep_config.max_dvc_qng; | |
13559 | asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID); | |
13560 | asc_dvc->start_motor = eep_config.start_motor; | |
13561 | asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay; | |
13562 | asc_dvc->bios_ctrl = eep_config.bios_ctrl; | |
13563 | asc_dvc->no_scam = eep_config.scam_tolerant; | |
27c868c2 | 13564 | |
51219358 MW |
13565 | /* |
13566 | * For every Target ID if any of its 'sdtr_speed[1234]' bits | |
13567 | * are set, then set an 'sdtr_able' bit for it. | |
13568 | */ | |
13569 | asc_dvc->sdtr_able = 0; | |
13570 | for (tid = 0; tid <= ASC_MAX_TID; tid++) { | |
13571 | if (tid == 0) { | |
13572 | sdtr_speed = asc_dvc->sdtr_speed1; | |
13573 | } else if (tid == 4) { | |
13574 | sdtr_speed = asc_dvc->sdtr_speed2; | |
13575 | } else if (tid == 8) { | |
13576 | sdtr_speed = asc_dvc->sdtr_speed3; | |
13577 | } else if (tid == 12) { | |
13578 | sdtr_speed = asc_dvc->sdtr_speed4; | |
13579 | } | |
13580 | if (sdtr_speed & ASC_MAX_TID) { | |
13581 | asc_dvc->sdtr_able |= (1 << tid); | |
13582 | } | |
13583 | sdtr_speed >>= 4; | |
13584 | } | |
27c868c2 | 13585 | |
51219358 MW |
13586 | /* |
13587 | * Set the host maximum queuing (max. 253, min. 16) and the per device | |
13588 | * maximum queuing (max. 63, min. 4). | |
13589 | */ | |
13590 | if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) { | |
13591 | eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; | |
13592 | } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) { | |
13593 | /* If the value is zero, assume it is uninitialized. */ | |
13594 | if (eep_config.max_host_qng == 0) { | |
13595 | eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; | |
13596 | } else { | |
13597 | eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG; | |
27c868c2 | 13598 | } |
51219358 | 13599 | } |
27c868c2 | 13600 | |
51219358 MW |
13601 | if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) { |
13602 | eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; | |
13603 | } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) { | |
13604 | /* If the value is zero, assume it is uninitialized. */ | |
13605 | if (eep_config.max_dvc_qng == 0) { | |
13606 | eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; | |
13607 | } else { | |
13608 | eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG; | |
13609 | } | |
13610 | } | |
13611 | ||
13612 | /* | |
13613 | * If 'max_dvc_qng' is greater than 'max_host_qng', then | |
13614 | * set 'max_dvc_qng' to 'max_host_qng'. | |
13615 | */ | |
13616 | if (eep_config.max_dvc_qng > eep_config.max_host_qng) { | |
13617 | eep_config.max_dvc_qng = eep_config.max_host_qng; | |
27c868c2 MW |
13618 | } |
13619 | ||
13620 | /* | |
51219358 MW |
13621 | * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng' |
13622 | * values based on possibly adjusted EEPROM values. | |
13623 | */ | |
13624 | asc_dvc->max_host_qng = eep_config.max_host_qng; | |
13625 | asc_dvc->max_dvc_qng = eep_config.max_dvc_qng; | |
13626 | ||
13627 | /* | |
13628 | * If the EEPROM 'termination' field is set to automatic (0), then set | |
13629 | * the ASC_DVC_CFG 'termination' field to automatic also. | |
13630 | * | |
13631 | * If the termination is specified with a non-zero 'termination' | |
13632 | * value check that a legal value is set and set the ASC_DVC_CFG | |
13633 | * 'termination' field appropriately. | |
27c868c2 | 13634 | */ |
51219358 MW |
13635 | if (eep_config.termination_se == 0) { |
13636 | termination = 0; /* auto termination for SE */ | |
13637 | } else { | |
13638 | /* Enable manual control with low off / high off. */ | |
13639 | if (eep_config.termination_se == 1) { | |
13640 | termination = 0; | |
27c868c2 | 13641 | |
51219358 MW |
13642 | /* Enable manual control with low off / high on. */ |
13643 | } else if (eep_config.termination_se == 2) { | |
13644 | termination = TERM_SE_HI; | |
27c868c2 | 13645 | |
51219358 MW |
13646 | /* Enable manual control with low on / high on. */ |
13647 | } else if (eep_config.termination_se == 3) { | |
13648 | termination = TERM_SE; | |
13649 | } else { | |
13650 | /* | |
13651 | * The EEPROM 'termination_se' field contains a bad value. | |
13652 | * Use automatic termination instead. | |
13653 | */ | |
13654 | termination = 0; | |
13655 | warn_code |= ASC_WARN_EEPROM_TERMINATION; | |
13656 | } | |
13657 | } | |
27c868c2 | 13658 | |
51219358 MW |
13659 | if (eep_config.termination_lvd == 0) { |
13660 | asc_dvc->cfg->termination = termination; /* auto termination for LVD */ | |
13661 | } else { | |
13662 | /* Enable manual control with low off / high off. */ | |
13663 | if (eep_config.termination_lvd == 1) { | |
13664 | asc_dvc->cfg->termination = termination; | |
27c868c2 | 13665 | |
51219358 MW |
13666 | /* Enable manual control with low off / high on. */ |
13667 | } else if (eep_config.termination_lvd == 2) { | |
13668 | asc_dvc->cfg->termination = termination | TERM_LVD_HI; | |
27c868c2 | 13669 | |
51219358 MW |
13670 | /* Enable manual control with low on / high on. */ |
13671 | } else if (eep_config.termination_lvd == 3) { | |
13672 | asc_dvc->cfg->termination = termination | TERM_LVD; | |
13673 | } else { | |
13674 | /* | |
13675 | * The EEPROM 'termination_lvd' field contains a bad value. | |
13676 | * Use automatic termination instead. | |
13677 | */ | |
13678 | asc_dvc->cfg->termination = termination; | |
13679 | warn_code |= ASC_WARN_EEPROM_TERMINATION; | |
13680 | } | |
27c868c2 | 13681 | } |
51219358 MW |
13682 | |
13683 | return warn_code; | |
1da177e4 LT |
13684 | } |
13685 | ||
13686 | /* | |
51219358 | 13687 | * Initialize the ADV_DVC_VAR structure. |
1da177e4 | 13688 | * |
51219358 | 13689 | * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR. |
1da177e4 | 13690 | * |
51219358 MW |
13691 | * For a non-fatal error return a warning code. If there are no warnings |
13692 | * then 0 is returned. | |
1da177e4 | 13693 | */ |
51219358 MW |
13694 | static int __devinit |
13695 | AdvInitGetConfig(struct pci_dev *pdev, asc_board_t *boardp) | |
1da177e4 | 13696 | { |
51219358 MW |
13697 | ADV_DVC_VAR *asc_dvc = &boardp->dvc_var.adv_dvc_var; |
13698 | unsigned short warn_code = 0; | |
13699 | AdvPortAddr iop_base = asc_dvc->iop_base; | |
13700 | u16 cmd; | |
13701 | int status; | |
27c868c2 | 13702 | |
51219358 | 13703 | asc_dvc->err_code = 0; |
27c868c2 MW |
13704 | |
13705 | /* | |
51219358 MW |
13706 | * Save the state of the PCI Configuration Command Register |
13707 | * "Parity Error Response Control" Bit. If the bit is clear (0), | |
13708 | * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore | |
13709 | * DMA parity errors. | |
27c868c2 | 13710 | */ |
51219358 MW |
13711 | asc_dvc->cfg->control_flag = 0; |
13712 | pci_read_config_word(pdev, PCI_COMMAND, &cmd); | |
13713 | if ((cmd & PCI_COMMAND_PARITY) == 0) | |
13714 | asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR; | |
27c868c2 | 13715 | |
51219358 MW |
13716 | asc_dvc->cfg->lib_version = (ADV_LIB_VERSION_MAJOR << 8) | |
13717 | ADV_LIB_VERSION_MINOR; | |
13718 | asc_dvc->cfg->chip_version = | |
13719 | AdvGetChipVersion(iop_base, asc_dvc->bus_type); | |
13720 | ||
13721 | ASC_DBG2(1, "AdvInitGetConfig: iopb_chip_id_1: 0x%x 0x%x\n", | |
13722 | (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1), | |
13723 | (ushort)ADV_CHIP_ID_BYTE); | |
13724 | ||
13725 | ASC_DBG2(1, "AdvInitGetConfig: iopw_chip_id_0: 0x%x 0x%x\n", | |
13726 | (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0), | |
13727 | (ushort)ADV_CHIP_ID_WORD); | |
27c868c2 MW |
13728 | |
13729 | /* | |
51219358 | 13730 | * Reset the chip to start and allow register writes. |
27c868c2 | 13731 | */ |
51219358 MW |
13732 | if (AdvFindSignature(iop_base) == 0) { |
13733 | asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE; | |
13734 | return ADV_ERROR; | |
13735 | } else { | |
27c868c2 | 13736 | /* |
51219358 | 13737 | * The caller must set 'chip_type' to a valid setting. |
27c868c2 | 13738 | */ |
51219358 MW |
13739 | if (asc_dvc->chip_type != ADV_CHIP_ASC3550 && |
13740 | asc_dvc->chip_type != ADV_CHIP_ASC38C0800 && | |
13741 | asc_dvc->chip_type != ADV_CHIP_ASC38C1600) { | |
13742 | asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE; | |
13743 | return ADV_ERROR; | |
13744 | } | |
1da177e4 | 13745 | |
51219358 MW |
13746 | /* |
13747 | * Reset Chip. | |
13748 | */ | |
13749 | AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, | |
13750 | ADV_CTRL_REG_CMD_RESET); | |
13751 | mdelay(100); | |
13752 | AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, | |
13753 | ADV_CTRL_REG_CMD_WR_IO_REG); | |
13754 | ||
13755 | if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) { | |
13756 | status = AdvInitFrom38C1600EEP(asc_dvc); | |
13757 | } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) { | |
13758 | status = AdvInitFrom38C0800EEP(asc_dvc); | |
13759 | } else { | |
13760 | status = AdvInitFrom3550EEP(asc_dvc); | |
27c868c2 | 13761 | } |
51219358 | 13762 | warn_code |= status; |
27c868c2 | 13763 | } |
1da177e4 | 13764 | |
51219358 MW |
13765 | if (warn_code != 0) { |
13766 | ASC_PRINT2("AdvInitGetConfig: board %d: warning: 0x%x\n", | |
13767 | boardp->id, warn_code); | |
13768 | } | |
13769 | ||
13770 | if (asc_dvc->err_code) { | |
13771 | ASC_PRINT2("AdvInitGetConfig: board %d error: err_code 0x%x\n", | |
13772 | boardp->id, asc_dvc->err_code); | |
13773 | } | |
13774 | ||
13775 | return asc_dvc->err_code; | |
1da177e4 | 13776 | } |
51219358 MW |
13777 | #endif |
13778 | ||
13779 | static struct scsi_host_template advansys_template = { | |
13780 | .proc_name = DRV_NAME, | |
13781 | #ifdef CONFIG_PROC_FS | |
13782 | .proc_info = advansys_proc_info, | |
13783 | #endif | |
13784 | .name = DRV_NAME, | |
13785 | .info = advansys_info, | |
13786 | .queuecommand = advansys_queuecommand, | |
13787 | .eh_bus_reset_handler = advansys_reset, | |
13788 | .bios_param = advansys_biosparam, | |
13789 | .slave_configure = advansys_slave_configure, | |
13790 | /* | |
13791 | * Because the driver may control an ISA adapter 'unchecked_isa_dma' | |
13792 | * must be set. The flag will be cleared in advansys_board_found | |
13793 | * for non-ISA adapters. | |
13794 | */ | |
13795 | .unchecked_isa_dma = 1, | |
13796 | /* | |
13797 | * All adapters controlled by this driver are capable of large | |
13798 | * scatter-gather lists. According to the mid-level SCSI documentation | |
13799 | * this obviates any performance gain provided by setting | |
13800 | * 'use_clustering'. But empirically while CPU utilization is increased | |
13801 | * by enabling clustering, I/O throughput increases as well. | |
13802 | */ | |
13803 | .use_clustering = ENABLE_CLUSTERING, | |
13804 | }; | |
1da177e4 | 13805 | |
b2c16f58 MW |
13806 | static int __devinit |
13807 | advansys_wide_init_chip(asc_board_t *boardp, ADV_DVC_VAR *adv_dvc_varp) | |
13808 | { | |
13809 | int req_cnt = 0; | |
13810 | adv_req_t *reqp = NULL; | |
13811 | int sg_cnt = 0; | |
13812 | adv_sgblk_t *sgp; | |
13813 | int warn_code, err_code; | |
13814 | ||
13815 | /* | |
13816 | * Allocate buffer carrier structures. The total size | |
13817 | * is about 4 KB, so allocate all at once. | |
13818 | */ | |
13819 | boardp->carrp = kmalloc(ADV_CARRIER_BUFSIZE, GFP_KERNEL); | |
13820 | ASC_DBG1(1, "advansys_wide_init_chip: carrp 0x%p\n", boardp->carrp); | |
13821 | ||
13822 | if (!boardp->carrp) | |
13823 | goto kmalloc_failed; | |
13824 | ||
13825 | /* | |
13826 | * Allocate up to 'max_host_qng' request structures for the Wide | |
13827 | * board. The total size is about 16 KB, so allocate all at once. | |
13828 | * If the allocation fails decrement and try again. | |
13829 | */ | |
13830 | for (req_cnt = adv_dvc_varp->max_host_qng; req_cnt > 0; req_cnt--) { | |
13831 | reqp = kmalloc(sizeof(adv_req_t) * req_cnt, GFP_KERNEL); | |
13832 | ||
13833 | ASC_DBG3(1, "advansys_wide_init_chip: reqp 0x%p, req_cnt %d, " | |
13834 | "bytes %lu\n", reqp, req_cnt, | |
13835 | (ulong)sizeof(adv_req_t) * req_cnt); | |
13836 | ||
13837 | if (reqp) | |
13838 | break; | |
13839 | } | |
13840 | ||
13841 | if (!reqp) | |
13842 | goto kmalloc_failed; | |
13843 | ||
13844 | boardp->orig_reqp = reqp; | |
13845 | ||
13846 | /* | |
13847 | * Allocate up to ADV_TOT_SG_BLOCK request structures for | |
13848 | * the Wide board. Each structure is about 136 bytes. | |
13849 | */ | |
13850 | boardp->adv_sgblkp = NULL; | |
13851 | for (sg_cnt = 0; sg_cnt < ADV_TOT_SG_BLOCK; sg_cnt++) { | |
13852 | sgp = kmalloc(sizeof(adv_sgblk_t), GFP_KERNEL); | |
13853 | ||
13854 | if (!sgp) | |
13855 | break; | |
13856 | ||
13857 | sgp->next_sgblkp = boardp->adv_sgblkp; | |
13858 | boardp->adv_sgblkp = sgp; | |
13859 | ||
13860 | } | |
13861 | ||
13862 | ASC_DBG3(1, "advansys_wide_init_chip: sg_cnt %d * %u = %u bytes\n", | |
13863 | sg_cnt, sizeof(adv_sgblk_t), | |
13864 | (unsigned)(sizeof(adv_sgblk_t) * sg_cnt)); | |
13865 | ||
13866 | if (!boardp->adv_sgblkp) | |
13867 | goto kmalloc_failed; | |
13868 | ||
13869 | adv_dvc_varp->carrier_buf = boardp->carrp; | |
13870 | ||
13871 | /* | |
13872 | * Point 'adv_reqp' to the request structures and | |
13873 | * link them together. | |
13874 | */ | |
13875 | req_cnt--; | |
13876 | reqp[req_cnt].next_reqp = NULL; | |
13877 | for (; req_cnt > 0; req_cnt--) { | |
13878 | reqp[req_cnt - 1].next_reqp = &reqp[req_cnt]; | |
13879 | } | |
13880 | boardp->adv_reqp = &reqp[0]; | |
13881 | ||
13882 | if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { | |
13883 | ASC_DBG(2, "advansys_wide_init_chip: AdvInitAsc3550Driver()\n"); | |
13884 | warn_code = AdvInitAsc3550Driver(adv_dvc_varp); | |
13885 | } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { | |
13886 | ASC_DBG(2, "advansys_wide_init_chip: AdvInitAsc38C0800Driver()" | |
13887 | "\n"); | |
13888 | warn_code = AdvInitAsc38C0800Driver(adv_dvc_varp); | |
13889 | } else { | |
13890 | ASC_DBG(2, "advansys_wide_init_chip: AdvInitAsc38C1600Driver()" | |
13891 | "\n"); | |
13892 | warn_code = AdvInitAsc38C1600Driver(adv_dvc_varp); | |
13893 | } | |
13894 | err_code = adv_dvc_varp->err_code; | |
13895 | ||
13896 | if (warn_code || err_code) { | |
13897 | ASC_PRINT3("advansys_wide_init_chip: board %d error: warn 0x%x," | |
13898 | " error 0x%x\n", boardp->id, warn_code, err_code); | |
13899 | } | |
13900 | ||
13901 | goto exit; | |
13902 | ||
13903 | kmalloc_failed: | |
13904 | ASC_PRINT1("advansys_wide_init_chip: board %d error: kmalloc() " | |
13905 | "failed\n", boardp->id); | |
13906 | err_code = ADV_ERROR; | |
13907 | exit: | |
13908 | return err_code; | |
13909 | } | |
13910 | ||
13911 | static void advansys_wide_free_mem(asc_board_t *boardp) | |
13912 | { | |
13913 | kfree(boardp->carrp); | |
13914 | boardp->carrp = NULL; | |
13915 | kfree(boardp->orig_reqp); | |
13916 | boardp->orig_reqp = boardp->adv_reqp = NULL; | |
13917 | while (boardp->adv_sgblkp) { | |
13918 | adv_sgblk_t *sgp = boardp->adv_sgblkp; | |
13919 | boardp->adv_sgblkp = sgp->next_sgblkp; | |
13920 | kfree(sgp); | |
13921 | } | |
13922 | } | |
13923 | ||
27c868c2 MW |
13924 | static struct Scsi_Host *__devinit |
13925 | advansys_board_found(int iop, struct device *dev, int bus_type) | |
13926 | { | |
13927 | struct Scsi_Host *shost; | |
13928 | struct pci_dev *pdev = bus_type == ASC_IS_PCI ? to_pci_dev(dev) : NULL; | |
13929 | asc_board_t *boardp; | |
13930 | ASC_DVC_VAR *asc_dvc_varp = NULL; | |
13931 | ADV_DVC_VAR *adv_dvc_varp = NULL; | |
074c8fe4 | 13932 | int share_irq; |
27c868c2 MW |
13933 | int warn_code, err_code; |
13934 | int ret; | |
13935 | ||
13936 | /* | |
27c868c2 MW |
13937 | * Register the adapter, get its configuration, and |
13938 | * initialize it. | |
13939 | */ | |
8dfb5379 MW |
13940 | ASC_DBG(2, "advansys_board_found: scsi_host_alloc()\n"); |
13941 | shost = scsi_host_alloc(&advansys_template, sizeof(asc_board_t)); | |
27c868c2 MW |
13942 | if (!shost) |
13943 | return NULL; | |
13944 | ||
27c868c2 MW |
13945 | /* Initialize private per board data */ |
13946 | boardp = ASC_BOARDP(shost); | |
13947 | memset(boardp, 0, sizeof(asc_board_t)); | |
78e77d8b | 13948 | boardp->id = asc_board_count++; |
27c868c2 | 13949 | spin_lock_init(&boardp->lock); |
394dbf3f | 13950 | boardp->dev = dev; |
27c868c2 MW |
13951 | |
13952 | /* | |
13953 | * Handle both narrow and wide boards. | |
13954 | * | |
13955 | * If a Wide board was detected, set the board structure | |
13956 | * wide board flag. Set-up the board structure based on | |
13957 | * the board type. | |
13958 | */ | |
13959 | #ifdef CONFIG_PCI | |
13960 | if (bus_type == ASC_IS_PCI && | |
13961 | (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW || | |
13962 | pdev->device == PCI_DEVICE_ID_38C0800_REV1 || | |
13963 | pdev->device == PCI_DEVICE_ID_38C1600_REV1)) { | |
13964 | boardp->flags |= ASC_IS_WIDE_BOARD; | |
13965 | } | |
13966 | #endif /* CONFIG_PCI */ | |
13967 | ||
13968 | if (ASC_NARROW_BOARD(boardp)) { | |
13969 | ASC_DBG(1, "advansys_board_found: narrow board\n"); | |
13970 | asc_dvc_varp = &boardp->dvc_var.asc_dvc_var; | |
13971 | asc_dvc_varp->bus_type = bus_type; | |
13972 | asc_dvc_varp->drv_ptr = boardp; | |
13973 | asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg; | |
13974 | asc_dvc_varp->cfg->overrun_buf = &overrun_buf[0]; | |
13975 | asc_dvc_varp->iop_base = iop; | |
27c868c2 | 13976 | } else { |
57ba5fe9 | 13977 | #ifdef CONFIG_PCI |
27c868c2 MW |
13978 | ASC_DBG(1, "advansys_board_found: wide board\n"); |
13979 | adv_dvc_varp = &boardp->dvc_var.adv_dvc_var; | |
13980 | adv_dvc_varp->drv_ptr = boardp; | |
13981 | adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg; | |
27c868c2 MW |
13982 | if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) { |
13983 | ASC_DBG(1, "advansys_board_found: ASC-3550\n"); | |
13984 | adv_dvc_varp->chip_type = ADV_CHIP_ASC3550; | |
13985 | } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) { | |
13986 | ASC_DBG(1, "advansys_board_found: ASC-38C0800\n"); | |
13987 | adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800; | |
13988 | } else { | |
13989 | ASC_DBG(1, "advansys_board_found: ASC-38C1600\n"); | |
13990 | adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600; | |
13991 | } | |
27c868c2 | 13992 | |
57ba5fe9 MW |
13993 | boardp->asc_n_io_port = pci_resource_len(pdev, 1); |
13994 | boardp->ioremap_addr = ioremap(pci_resource_start(pdev, 1), | |
13995 | boardp->asc_n_io_port); | |
13996 | if (!boardp->ioremap_addr) { | |
27c868c2 MW |
13997 | ASC_PRINT3 |
13998 | ("advansys_board_found: board %d: ioremap(%x, %d) returned NULL\n", | |
57ba5fe9 MW |
13999 | boardp->id, pci_resource_start(pdev, 1), |
14000 | boardp->asc_n_io_port); | |
b2c16f58 | 14001 | goto err_shost; |
27c868c2 | 14002 | } |
57ba5fe9 | 14003 | adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr |
71f36115 | 14004 | ASC_DBG1(1, "advansys_board_found: iop_base: 0x%lx\n", |
27c868c2 | 14005 | adv_dvc_varp->iop_base); |
27c868c2 MW |
14006 | |
14007 | /* | |
14008 | * Even though it isn't used to access wide boards, other | |
14009 | * than for the debug line below, save I/O Port address so | |
14010 | * that it can be reported. | |
14011 | */ | |
14012 | boardp->ioport = iop; | |
14013 | ||
57ba5fe9 MW |
14014 | ASC_DBG2(1, "advansys_board_found: iopb_chip_id_1 0x%x, " |
14015 | "iopw_chip_id_0 0x%x\n", (ushort)inp(iop + 1), | |
14016 | (ushort)inpw(iop)); | |
14017 | #endif /* CONFIG_PCI */ | |
27c868c2 MW |
14018 | } |
14019 | ||
14020 | #ifdef CONFIG_PROC_FS | |
14021 | /* | |
14022 | * Allocate buffer for printing information from | |
14023 | * /proc/scsi/advansys/[0...]. | |
14024 | */ | |
b2c16f58 MW |
14025 | boardp->prtbuf = kmalloc(ASC_PRTBUF_SIZE, GFP_KERNEL); |
14026 | if (!boardp->prtbuf) { | |
14027 | ASC_PRINT2("advansys_board_found: board %d: kmalloc(%d) " | |
14028 | "returned NULL\n", boardp->id, ASC_PRTBUF_SIZE); | |
14029 | goto err_unmap; | |
27c868c2 MW |
14030 | } |
14031 | #endif /* CONFIG_PROC_FS */ | |
14032 | ||
14033 | if (ASC_NARROW_BOARD(boardp)) { | |
27c868c2 MW |
14034 | /* |
14035 | * Set the board bus type and PCI IRQ before | |
14036 | * calling AscInitGetConfig(). | |
14037 | */ | |
14038 | switch (asc_dvc_varp->bus_type) { | |
14039 | #ifdef CONFIG_ISA | |
14040 | case ASC_IS_ISA: | |
14041 | shost->unchecked_isa_dma = TRUE; | |
074c8fe4 | 14042 | share_irq = 0; |
27c868c2 MW |
14043 | break; |
14044 | case ASC_IS_VL: | |
14045 | shost->unchecked_isa_dma = FALSE; | |
074c8fe4 | 14046 | share_irq = 0; |
27c868c2 MW |
14047 | break; |
14048 | case ASC_IS_EISA: | |
14049 | shost->unchecked_isa_dma = FALSE; | |
074c8fe4 | 14050 | share_irq = IRQF_SHARED; |
27c868c2 MW |
14051 | break; |
14052 | #endif /* CONFIG_ISA */ | |
14053 | #ifdef CONFIG_PCI | |
14054 | case ASC_IS_PCI: | |
14055 | shost->irq = asc_dvc_varp->irq_no = pdev->irq; | |
27c868c2 | 14056 | shost->unchecked_isa_dma = FALSE; |
074c8fe4 | 14057 | share_irq = IRQF_SHARED; |
27c868c2 MW |
14058 | break; |
14059 | #endif /* CONFIG_PCI */ | |
14060 | default: | |
14061 | ASC_PRINT2 | |
14062 | ("advansys_board_found: board %d: unknown adapter type: %d\n", | |
14063 | boardp->id, asc_dvc_varp->bus_type); | |
14064 | shost->unchecked_isa_dma = TRUE; | |
074c8fe4 | 14065 | share_irq = 0; |
27c868c2 MW |
14066 | break; |
14067 | } | |
27c868c2 | 14068 | |
27c868c2 MW |
14069 | /* |
14070 | * NOTE: AscInitGetConfig() may change the board's | |
14071 | * bus_type value. The bus_type value should no | |
14072 | * longer be used. If the bus_type field must be | |
14073 | * referenced only use the bit-wise AND operator "&". | |
14074 | */ | |
14075 | ASC_DBG(2, "advansys_board_found: AscInitGetConfig()\n"); | |
c2dce2fa | 14076 | err_code = AscInitGetConfig(boardp); |
27c868c2 | 14077 | } else { |
c2dce2fa MW |
14078 | #ifdef CONFIG_PCI |
14079 | /* | |
14080 | * For Wide boards set PCI information before calling | |
14081 | * AdvInitGetConfig(). | |
14082 | */ | |
14083 | shost->irq = adv_dvc_varp->irq_no = pdev->irq; | |
14084 | shost->unchecked_isa_dma = FALSE; | |
14085 | share_irq = IRQF_SHARED; | |
27c868c2 | 14086 | ASC_DBG(2, "advansys_board_found: AdvInitGetConfig()\n"); |
394dbf3f | 14087 | |
c2dce2fa MW |
14088 | err_code = AdvInitGetConfig(pdev, boardp); |
14089 | #endif /* CONFIG_PCI */ | |
27c868c2 MW |
14090 | } |
14091 | ||
b2c16f58 MW |
14092 | if (err_code != 0) |
14093 | goto err_free_proc; | |
27c868c2 MW |
14094 | |
14095 | /* | |
14096 | * Save the EEPROM configuration so that it can be displayed | |
14097 | * from /proc/scsi/advansys/[0...]. | |
14098 | */ | |
14099 | if (ASC_NARROW_BOARD(boardp)) { | |
14100 | ||
14101 | ASCEEP_CONFIG *ep; | |
14102 | ||
14103 | /* | |
14104 | * Set the adapter's target id bit in the 'init_tidmask' field. | |
14105 | */ | |
14106 | boardp->init_tidmask |= | |
14107 | ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id); | |
14108 | ||
14109 | /* | |
14110 | * Save EEPROM settings for the board. | |
14111 | */ | |
14112 | ep = &boardp->eep_config.asc_eep; | |
14113 | ||
14114 | ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable; | |
14115 | ep->disc_enable = asc_dvc_varp->cfg->disc_enable; | |
14116 | ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled; | |
14117 | ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed); | |
14118 | ep->start_motor = asc_dvc_varp->start_motor; | |
14119 | ep->cntl = asc_dvc_varp->dvc_cntl; | |
14120 | ep->no_scam = asc_dvc_varp->no_scam; | |
14121 | ep->max_total_qng = asc_dvc_varp->max_total_qng; | |
14122 | ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id); | |
14123 | /* 'max_tag_qng' is set to the same value for every device. */ | |
14124 | ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0]; | |
14125 | ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0]; | |
14126 | ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1]; | |
14127 | ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2]; | |
14128 | ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3]; | |
14129 | ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4]; | |
14130 | ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5]; | |
14131 | ||
14132 | /* | |
14133 | * Modify board configuration. | |
14134 | */ | |
14135 | ASC_DBG(2, "advansys_board_found: AscInitSetConfig()\n"); | |
c2dce2fa MW |
14136 | err_code = AscInitSetConfig(pdev, boardp); |
14137 | if (err_code) | |
b2c16f58 | 14138 | goto err_free_proc; |
27c868c2 MW |
14139 | |
14140 | /* | |
14141 | * Finish initializing the 'Scsi_Host' structure. | |
14142 | */ | |
14143 | /* AscInitSetConfig() will set the IRQ for non-PCI boards. */ | |
14144 | if ((asc_dvc_varp->bus_type & ASC_IS_PCI) == 0) { | |
14145 | shost->irq = asc_dvc_varp->irq_no; | |
14146 | } | |
14147 | } else { | |
14148 | ADVEEP_3550_CONFIG *ep_3550; | |
14149 | ADVEEP_38C0800_CONFIG *ep_38C0800; | |
14150 | ADVEEP_38C1600_CONFIG *ep_38C1600; | |
14151 | ||
14152 | /* | |
14153 | * Save Wide EEP Configuration Information. | |
14154 | */ | |
14155 | if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { | |
14156 | ep_3550 = &boardp->eep_config.adv_3550_eep; | |
14157 | ||
14158 | ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id; | |
14159 | ep_3550->max_host_qng = adv_dvc_varp->max_host_qng; | |
14160 | ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng; | |
14161 | ep_3550->termination = adv_dvc_varp->cfg->termination; | |
14162 | ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable; | |
14163 | ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl; | |
14164 | ep_3550->wdtr_able = adv_dvc_varp->wdtr_able; | |
14165 | ep_3550->sdtr_able = adv_dvc_varp->sdtr_able; | |
14166 | ep_3550->ultra_able = adv_dvc_varp->ultra_able; | |
14167 | ep_3550->tagqng_able = adv_dvc_varp->tagqng_able; | |
14168 | ep_3550->start_motor = adv_dvc_varp->start_motor; | |
14169 | ep_3550->scsi_reset_delay = | |
14170 | adv_dvc_varp->scsi_reset_wait; | |
14171 | ep_3550->serial_number_word1 = | |
14172 | adv_dvc_varp->cfg->serial1; | |
14173 | ep_3550->serial_number_word2 = | |
14174 | adv_dvc_varp->cfg->serial2; | |
14175 | ep_3550->serial_number_word3 = | |
14176 | adv_dvc_varp->cfg->serial3; | |
14177 | } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { | |
14178 | ep_38C0800 = &boardp->eep_config.adv_38C0800_eep; | |
14179 | ||
14180 | ep_38C0800->adapter_scsi_id = | |
14181 | adv_dvc_varp->chip_scsi_id; | |
14182 | ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng; | |
14183 | ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng; | |
14184 | ep_38C0800->termination_lvd = | |
14185 | adv_dvc_varp->cfg->termination; | |
14186 | ep_38C0800->disc_enable = | |
14187 | adv_dvc_varp->cfg->disc_enable; | |
14188 | ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl; | |
14189 | ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able; | |
14190 | ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able; | |
14191 | ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1; | |
14192 | ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2; | |
14193 | ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3; | |
14194 | ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4; | |
14195 | ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able; | |
14196 | ep_38C0800->start_motor = adv_dvc_varp->start_motor; | |
14197 | ep_38C0800->scsi_reset_delay = | |
14198 | adv_dvc_varp->scsi_reset_wait; | |
14199 | ep_38C0800->serial_number_word1 = | |
14200 | adv_dvc_varp->cfg->serial1; | |
14201 | ep_38C0800->serial_number_word2 = | |
14202 | adv_dvc_varp->cfg->serial2; | |
14203 | ep_38C0800->serial_number_word3 = | |
14204 | adv_dvc_varp->cfg->serial3; | |
14205 | } else { | |
14206 | ep_38C1600 = &boardp->eep_config.adv_38C1600_eep; | |
14207 | ||
14208 | ep_38C1600->adapter_scsi_id = | |
14209 | adv_dvc_varp->chip_scsi_id; | |
14210 | ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng; | |
14211 | ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng; | |
14212 | ep_38C1600->termination_lvd = | |
14213 | adv_dvc_varp->cfg->termination; | |
14214 | ep_38C1600->disc_enable = | |
14215 | adv_dvc_varp->cfg->disc_enable; | |
14216 | ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl; | |
14217 | ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able; | |
14218 | ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able; | |
14219 | ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1; | |
14220 | ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2; | |
14221 | ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3; | |
14222 | ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4; | |
14223 | ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able; | |
14224 | ep_38C1600->start_motor = adv_dvc_varp->start_motor; | |
14225 | ep_38C1600->scsi_reset_delay = | |
14226 | adv_dvc_varp->scsi_reset_wait; | |
14227 | ep_38C1600->serial_number_word1 = | |
14228 | adv_dvc_varp->cfg->serial1; | |
14229 | ep_38C1600->serial_number_word2 = | |
14230 | adv_dvc_varp->cfg->serial2; | |
14231 | ep_38C1600->serial_number_word3 = | |
14232 | adv_dvc_varp->cfg->serial3; | |
14233 | } | |
14234 | ||
14235 | /* | |
14236 | * Set the adapter's target id bit in the 'init_tidmask' field. | |
14237 | */ | |
14238 | boardp->init_tidmask |= | |
14239 | ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id); | |
27c868c2 MW |
14240 | } |
14241 | ||
14242 | /* | |
14243 | * Channels are numbered beginning with 0. For AdvanSys one host | |
14244 | * structure supports one channel. Multi-channel boards have a | |
14245 | * separate host structure for each channel. | |
14246 | */ | |
14247 | shost->max_channel = 0; | |
14248 | if (ASC_NARROW_BOARD(boardp)) { | |
14249 | shost->max_id = ASC_MAX_TID + 1; | |
14250 | shost->max_lun = ASC_MAX_LUN + 1; | |
f05ec594 | 14251 | shost->max_cmd_len = ASC_MAX_CDB_LEN; |
27c868c2 MW |
14252 | |
14253 | shost->io_port = asc_dvc_varp->iop_base; | |
14254 | boardp->asc_n_io_port = ASC_IOADR_GAP; | |
14255 | shost->this_id = asc_dvc_varp->cfg->chip_scsi_id; | |
14256 | ||
14257 | /* Set maximum number of queues the adapter can handle. */ | |
14258 | shost->can_queue = asc_dvc_varp->max_total_qng; | |
14259 | } else { | |
14260 | shost->max_id = ADV_MAX_TID + 1; | |
14261 | shost->max_lun = ADV_MAX_LUN + 1; | |
f05ec594 | 14262 | shost->max_cmd_len = ADV_MAX_CDB_LEN; |
27c868c2 MW |
14263 | |
14264 | /* | |
14265 | * Save the I/O Port address and length even though | |
14266 | * I/O ports are not used to access Wide boards. | |
14267 | * Instead the Wide boards are accessed with | |
14268 | * PCI Memory Mapped I/O. | |
14269 | */ | |
14270 | shost->io_port = iop; | |
27c868c2 MW |
14271 | |
14272 | shost->this_id = adv_dvc_varp->chip_scsi_id; | |
14273 | ||
14274 | /* Set maximum number of queues the adapter can handle. */ | |
14275 | shost->can_queue = adv_dvc_varp->max_host_qng; | |
14276 | } | |
14277 | ||
27c868c2 MW |
14278 | /* |
14279 | * Following v1.3.89, 'cmd_per_lun' is no longer needed | |
14280 | * and should be set to zero. | |
14281 | * | |
14282 | * But because of a bug introduced in v1.3.89 if the driver is | |
14283 | * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level | |
14284 | * SCSI function 'allocate_device' will panic. To allow the driver | |
14285 | * to work as a module in these kernels set 'cmd_per_lun' to 1. | |
14286 | * | |
14287 | * Note: This is wrong. cmd_per_lun should be set to the depth | |
14288 | * you want on untagged devices always. | |
14289 | #ifdef MODULE | |
14290 | */ | |
14291 | shost->cmd_per_lun = 1; | |
14292 | /* #else | |
14293 | shost->cmd_per_lun = 0; | |
14294 | #endif */ | |
14295 | ||
14296 | /* | |
14297 | * Set the maximum number of scatter-gather elements the | |
14298 | * adapter can handle. | |
14299 | */ | |
14300 | if (ASC_NARROW_BOARD(boardp)) { | |
14301 | /* | |
14302 | * Allow two commands with 'sg_tablesize' scatter-gather | |
14303 | * elements to be executed simultaneously. This value is | |
14304 | * the theoretical hardware limit. It may be decreased | |
14305 | * below. | |
14306 | */ | |
14307 | shost->sg_tablesize = | |
14308 | (((asc_dvc_varp->max_total_qng - 2) / 2) * | |
14309 | ASC_SG_LIST_PER_Q) + 1; | |
14310 | } else { | |
14311 | shost->sg_tablesize = ADV_MAX_SG_LIST; | |
14312 | } | |
14313 | ||
14314 | /* | |
14315 | * The value of 'sg_tablesize' can not exceed the SCSI | |
14316 | * mid-level driver definition of SG_ALL. SG_ALL also | |
14317 | * must not be exceeded, because it is used to define the | |
14318 | * size of the scatter-gather table in 'struct asc_sg_head'. | |
14319 | */ | |
14320 | if (shost->sg_tablesize > SG_ALL) { | |
14321 | shost->sg_tablesize = SG_ALL; | |
14322 | } | |
14323 | ||
14324 | ASC_DBG1(1, "advansys_board_found: sg_tablesize: %d\n", shost->sg_tablesize); | |
14325 | ||
14326 | /* BIOS start address. */ | |
14327 | if (ASC_NARROW_BOARD(boardp)) { | |
b2c16f58 MW |
14328 | shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base, |
14329 | asc_dvc_varp->bus_type); | |
27c868c2 MW |
14330 | } else { |
14331 | /* | |
14332 | * Fill-in BIOS board variables. The Wide BIOS saves | |
14333 | * information in LRAM that is used by the driver. | |
14334 | */ | |
14335 | AdvReadWordLram(adv_dvc_varp->iop_base, | |
14336 | BIOS_SIGNATURE, boardp->bios_signature); | |
14337 | AdvReadWordLram(adv_dvc_varp->iop_base, | |
14338 | BIOS_VERSION, boardp->bios_version); | |
14339 | AdvReadWordLram(adv_dvc_varp->iop_base, | |
14340 | BIOS_CODESEG, boardp->bios_codeseg); | |
14341 | AdvReadWordLram(adv_dvc_varp->iop_base, | |
14342 | BIOS_CODELEN, boardp->bios_codelen); | |
14343 | ||
14344 | ASC_DBG2(1, | |
14345 | "advansys_board_found: bios_signature 0x%x, bios_version 0x%x\n", | |
14346 | boardp->bios_signature, boardp->bios_version); | |
14347 | ||
14348 | ASC_DBG2(1, | |
14349 | "advansys_board_found: bios_codeseg 0x%x, bios_codelen 0x%x\n", | |
14350 | boardp->bios_codeseg, boardp->bios_codelen); | |
14351 | ||
14352 | /* | |
14353 | * If the BIOS saved a valid signature, then fill in | |
14354 | * the BIOS code segment base address. | |
14355 | */ | |
14356 | if (boardp->bios_signature == 0x55AA) { | |
14357 | /* | |
14358 | * Convert x86 realmode code segment to a linear | |
14359 | * address by shifting left 4. | |
14360 | */ | |
14361 | shost->base = ((ulong)boardp->bios_codeseg << 4); | |
14362 | } else { | |
14363 | shost->base = 0; | |
14364 | } | |
14365 | } | |
14366 | ||
14367 | /* | |
14368 | * Register Board Resources - I/O Port, DMA, IRQ | |
14369 | */ | |
14370 | ||
27c868c2 MW |
14371 | /* Register DMA Channel for Narrow boards. */ |
14372 | shost->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */ | |
14373 | #ifdef CONFIG_ISA | |
14374 | if (ASC_NARROW_BOARD(boardp)) { | |
14375 | /* Register DMA channel for ISA bus. */ | |
14376 | if (asc_dvc_varp->bus_type & ASC_IS_ISA) { | |
14377 | shost->dma_channel = asc_dvc_varp->cfg->isa_dma_channel; | |
01fbfe0b | 14378 | ret = request_dma(shost->dma_channel, DRV_NAME); |
b2c16f58 | 14379 | if (ret) { |
27c868c2 MW |
14380 | ASC_PRINT3 |
14381 | ("advansys_board_found: board %d: request_dma() %d failed %d\n", | |
14382 | boardp->id, shost->dma_channel, ret); | |
71f36115 | 14383 | goto err_free_proc; |
27c868c2 MW |
14384 | } |
14385 | AscEnableIsaDma(shost->dma_channel); | |
14386 | } | |
14387 | } | |
14388 | #endif /* CONFIG_ISA */ | |
14389 | ||
14390 | /* Register IRQ Number. */ | |
14391 | ASC_DBG1(2, "advansys_board_found: request_irq() %d\n", shost->irq); | |
074c8fe4 MW |
14392 | |
14393 | ret = request_irq(shost->irq, advansys_interrupt, share_irq, | |
01fbfe0b | 14394 | DRV_NAME, shost); |
074c8fe4 MW |
14395 | |
14396 | if (ret) { | |
27c868c2 MW |
14397 | if (ret == -EBUSY) { |
14398 | ASC_PRINT2 | |
14399 | ("advansys_board_found: board %d: request_irq(): IRQ 0x%x already in use.\n", | |
14400 | boardp->id, shost->irq); | |
14401 | } else if (ret == -EINVAL) { | |
14402 | ASC_PRINT2 | |
14403 | ("advansys_board_found: board %d: request_irq(): IRQ 0x%x not valid.\n", | |
14404 | boardp->id, shost->irq); | |
14405 | } else { | |
14406 | ASC_PRINT3 | |
14407 | ("advansys_board_found: board %d: request_irq(): IRQ 0x%x failed with %d\n", | |
14408 | boardp->id, shost->irq, ret); | |
14409 | } | |
b2c16f58 | 14410 | goto err_free_dma; |
27c868c2 MW |
14411 | } |
14412 | ||
14413 | /* | |
14414 | * Initialize board RISC chip and enable interrupts. | |
14415 | */ | |
14416 | if (ASC_NARROW_BOARD(boardp)) { | |
14417 | ASC_DBG(2, "advansys_board_found: AscInitAsc1000Driver()\n"); | |
14418 | warn_code = AscInitAsc1000Driver(asc_dvc_varp); | |
14419 | err_code = asc_dvc_varp->err_code; | |
14420 | ||
14421 | if (warn_code || err_code) { | |
14422 | ASC_PRINT4 | |
14423 | ("advansys_board_found: board %d error: init_state 0x%x, warn 0x%x, error 0x%x\n", | |
14424 | boardp->id, | |
14425 | asc_dvc_varp->init_state, warn_code, err_code); | |
14426 | } | |
14427 | } else { | |
b2c16f58 | 14428 | err_code = advansys_wide_init_chip(boardp, adv_dvc_varp); |
27c868c2 MW |
14429 | } |
14430 | ||
b2c16f58 MW |
14431 | if (err_code != 0) |
14432 | goto err_free_wide_mem; | |
14433 | ||
27c868c2 MW |
14434 | ASC_DBG_PRT_SCSI_HOST(2, shost); |
14435 | ||
8dfb5379 MW |
14436 | ret = scsi_add_host(shost, dev); |
14437 | if (ret) | |
14438 | goto err_free_wide_mem; | |
14439 | ||
14440 | scsi_scan_host(shost); | |
27c868c2 | 14441 | return shost; |
b2c16f58 MW |
14442 | |
14443 | err_free_wide_mem: | |
14444 | advansys_wide_free_mem(boardp); | |
14445 | free_irq(shost->irq, shost); | |
14446 | err_free_dma: | |
14447 | if (shost->dma_channel != NO_ISA_DMA) | |
14448 | free_dma(shost->dma_channel); | |
b2c16f58 MW |
14449 | err_free_proc: |
14450 | kfree(boardp->prtbuf); | |
14451 | err_unmap: | |
14452 | if (boardp->ioremap_addr) | |
14453 | iounmap(boardp->ioremap_addr); | |
14454 | err_shost: | |
8dfb5379 | 14455 | scsi_host_put(shost); |
b2c16f58 | 14456 | return NULL; |
27c868c2 MW |
14457 | } |
14458 | ||
27c868c2 MW |
14459 | /* |
14460 | * advansys_release() | |
14461 | * | |
14462 | * Release resources allocated for a single AdvanSys adapter. | |
14463 | */ | |
14464 | static int advansys_release(struct Scsi_Host *shost) | |
14465 | { | |
14466 | asc_board_t *boardp; | |
14467 | ||
14468 | ASC_DBG(1, "advansys_release: begin\n"); | |
8dfb5379 | 14469 | scsi_remove_host(shost); |
27c868c2 | 14470 | boardp = ASC_BOARDP(shost); |
074c8fe4 | 14471 | free_irq(shost->irq, shost); |
27c868c2 MW |
14472 | if (shost->dma_channel != NO_ISA_DMA) { |
14473 | ASC_DBG(1, "advansys_release: free_dma()\n"); | |
14474 | free_dma(shost->dma_channel); | |
14475 | } | |
27c868c2 | 14476 | if (ASC_WIDE_BOARD(boardp)) { |
27c868c2 | 14477 | iounmap(boardp->ioremap_addr); |
b2c16f58 | 14478 | advansys_wide_free_mem(boardp); |
27c868c2 | 14479 | } |
27c868c2 | 14480 | kfree(boardp->prtbuf); |
8dfb5379 | 14481 | scsi_host_put(shost); |
27c868c2 MW |
14482 | ASC_DBG(1, "advansys_release: end\n"); |
14483 | return 0; | |
14484 | } | |
14485 | ||
95c9f162 MW |
14486 | #define ASC_IOADR_TABLE_MAX_IX 11 |
14487 | ||
c304ec94 MW |
14488 | static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] __devinitdata = { |
14489 | 0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190, | |
14490 | 0x0210, 0x0230, 0x0250, 0x0330 | |
14491 | }; | |
14492 | ||
14493 | static int __devinit advansys_isa_probe(struct device *dev, unsigned int id) | |
14494 | { | |
14495 | PortAddr iop_base = _asc_def_iop_base[id]; | |
14496 | struct Scsi_Host *shost; | |
14497 | ||
01fbfe0b | 14498 | if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) { |
71f36115 MW |
14499 | ASC_DBG1(1, "advansys_isa_match: I/O port 0x%x busy\n", |
14500 | iop_base); | |
c304ec94 MW |
14501 | return -ENODEV; |
14502 | } | |
14503 | ASC_DBG1(1, "advansys_isa_match: probing I/O port 0x%x\n", iop_base); | |
c304ec94 MW |
14504 | if (!AscFindSignature(iop_base)) |
14505 | goto nodev; | |
14506 | if (!(AscGetChipVersion(iop_base, ASC_IS_ISA) & ASC_CHIP_VER_ISA_BIT)) | |
14507 | goto nodev; | |
14508 | ||
14509 | shost = advansys_board_found(iop_base, dev, ASC_IS_ISA); | |
c304ec94 MW |
14510 | if (!shost) |
14511 | goto nodev; | |
14512 | ||
14513 | dev_set_drvdata(dev, shost); | |
14514 | return 0; | |
14515 | ||
14516 | nodev: | |
71f36115 | 14517 | release_region(iop_base, ASC_IOADR_GAP); |
c304ec94 MW |
14518 | return -ENODEV; |
14519 | } | |
14520 | ||
14521 | static int __devexit advansys_isa_remove(struct device *dev, unsigned int id) | |
14522 | { | |
71f36115 | 14523 | int ioport = _asc_def_iop_base[id]; |
c304ec94 | 14524 | advansys_release(dev_get_drvdata(dev)); |
71f36115 | 14525 | release_region(ioport, ASC_IOADR_GAP); |
c304ec94 MW |
14526 | return 0; |
14527 | } | |
14528 | ||
14529 | static struct isa_driver advansys_isa_driver = { | |
14530 | .probe = advansys_isa_probe, | |
14531 | .remove = __devexit_p(advansys_isa_remove), | |
14532 | .driver = { | |
14533 | .owner = THIS_MODULE, | |
01fbfe0b | 14534 | .name = DRV_NAME, |
c304ec94 MW |
14535 | }, |
14536 | }; | |
14537 | ||
14538 | static int __devinit advansys_vlb_probe(struct device *dev, unsigned int id) | |
14539 | { | |
14540 | PortAddr iop_base = _asc_def_iop_base[id]; | |
14541 | struct Scsi_Host *shost; | |
14542 | ||
01fbfe0b | 14543 | if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) { |
71f36115 MW |
14544 | ASC_DBG1(1, "advansys_vlb_match: I/O port 0x%x busy\n", |
14545 | iop_base); | |
c304ec94 MW |
14546 | return -ENODEV; |
14547 | } | |
14548 | ASC_DBG1(1, "advansys_vlb_match: probing I/O port 0x%x\n", iop_base); | |
c304ec94 MW |
14549 | if (!AscFindSignature(iop_base)) |
14550 | goto nodev; | |
14551 | /* | |
14552 | * I don't think this condition can actually happen, but the old | |
14553 | * driver did it, and the chances of finding a VLB setup in 2007 | |
14554 | * to do testing with is slight to none. | |
14555 | */ | |
14556 | if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL) | |
14557 | goto nodev; | |
14558 | ||
14559 | shost = advansys_board_found(iop_base, dev, ASC_IS_VL); | |
c304ec94 MW |
14560 | if (!shost) |
14561 | goto nodev; | |
14562 | ||
14563 | dev_set_drvdata(dev, shost); | |
14564 | return 0; | |
14565 | ||
14566 | nodev: | |
71f36115 | 14567 | release_region(iop_base, ASC_IOADR_GAP); |
c304ec94 MW |
14568 | return -ENODEV; |
14569 | } | |
14570 | ||
14571 | static struct isa_driver advansys_vlb_driver = { | |
14572 | .probe = advansys_vlb_probe, | |
14573 | .remove = __devexit_p(advansys_isa_remove), | |
14574 | .driver = { | |
14575 | .owner = THIS_MODULE, | |
b8e5152b | 14576 | .name = "advansys_vlb", |
c304ec94 MW |
14577 | }, |
14578 | }; | |
14579 | ||
b09e05a7 MW |
14580 | static struct eisa_device_id advansys_eisa_table[] __devinitdata = { |
14581 | { "ABP7401" }, | |
14582 | { "ABP7501" }, | |
14583 | { "" } | |
14584 | }; | |
14585 | ||
14586 | MODULE_DEVICE_TABLE(eisa, advansys_eisa_table); | |
14587 | ||
14588 | /* | |
14589 | * EISA is a little more tricky than PCI; each EISA device may have two | |
14590 | * channels, and this driver is written to make each channel its own Scsi_Host | |
14591 | */ | |
14592 | struct eisa_scsi_data { | |
14593 | struct Scsi_Host *host[2]; | |
14594 | }; | |
14595 | ||
14596 | static int __devinit advansys_eisa_probe(struct device *dev) | |
14597 | { | |
14598 | int i, ioport; | |
14599 | int err; | |
14600 | struct eisa_device *edev = to_eisa_device(dev); | |
14601 | struct eisa_scsi_data *data; | |
14602 | ||
14603 | err = -ENOMEM; | |
14604 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
14605 | if (!data) | |
14606 | goto fail; | |
14607 | ioport = edev->base_addr + 0xc30; | |
14608 | ||
14609 | err = -ENODEV; | |
14610 | for (i = 0; i < 2; i++, ioport += 0x20) { | |
01fbfe0b | 14611 | if (!request_region(ioport, ASC_IOADR_GAP, DRV_NAME)) { |
71f36115 MW |
14612 | printk(KERN_WARNING "Region %x-%x busy\n", ioport, |
14613 | ioport + ASC_IOADR_GAP - 1); | |
14614 | continue; | |
14615 | } | |
14616 | if (!AscFindSignature(ioport)) { | |
14617 | release_region(ioport, ASC_IOADR_GAP); | |
b09e05a7 | 14618 | continue; |
71f36115 MW |
14619 | } |
14620 | ||
b09e05a7 MW |
14621 | /* |
14622 | * I don't know why we need to do this for EISA chips, but | |
14623 | * not for any others. It looks to be equivalent to | |
14624 | * AscGetChipCfgMsw, but I may have overlooked something, | |
14625 | * so I'm not converting it until I get an EISA board to | |
14626 | * test with. | |
14627 | */ | |
14628 | inw(ioport + 4); | |
14629 | data->host[i] = advansys_board_found(ioport, dev, ASC_IS_EISA); | |
71f36115 | 14630 | if (data->host[i]) { |
b09e05a7 | 14631 | err = 0; |
71f36115 MW |
14632 | } else { |
14633 | release_region(ioport, ASC_IOADR_GAP); | |
14634 | } | |
b09e05a7 MW |
14635 | } |
14636 | ||
14637 | if (err) { | |
14638 | kfree(data); | |
14639 | } else { | |
14640 | dev_set_drvdata(dev, data); | |
14641 | } | |
14642 | ||
14643 | fail: | |
14644 | return err; | |
14645 | } | |
14646 | ||
14647 | static __devexit int advansys_eisa_remove(struct device *dev) | |
14648 | { | |
14649 | int i; | |
14650 | struct eisa_scsi_data *data = dev_get_drvdata(dev); | |
14651 | ||
14652 | for (i = 0; i < 2; i++) { | |
71f36115 | 14653 | int ioport; |
b09e05a7 MW |
14654 | struct Scsi_Host *shost = data->host[i]; |
14655 | if (!shost) | |
14656 | continue; | |
71f36115 | 14657 | ioport = shost->io_port; |
b09e05a7 | 14658 | advansys_release(shost); |
71f36115 | 14659 | release_region(ioport, ASC_IOADR_GAP); |
b09e05a7 MW |
14660 | } |
14661 | ||
14662 | kfree(data); | |
14663 | return 0; | |
14664 | } | |
14665 | ||
14666 | static struct eisa_driver advansys_eisa_driver = { | |
14667 | .id_table = advansys_eisa_table, | |
14668 | .driver = { | |
01fbfe0b | 14669 | .name = DRV_NAME, |
b09e05a7 MW |
14670 | .probe = advansys_eisa_probe, |
14671 | .remove = __devexit_p(advansys_eisa_remove), | |
14672 | } | |
14673 | }; | |
14674 | ||
2672ea86 DJ |
14675 | /* PCI Devices supported by this driver */ |
14676 | static struct pci_device_id advansys_pci_tbl[] __devinitdata = { | |
27c868c2 MW |
14677 | {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A, |
14678 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
14679 | {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940, | |
14680 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
14681 | {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U, | |
14682 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
14683 | {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW, | |
14684 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
14685 | {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1, | |
14686 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
14687 | {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1, | |
14688 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
14689 | {} | |
2672ea86 | 14690 | }; |
27c868c2 | 14691 | |
2672ea86 | 14692 | MODULE_DEVICE_TABLE(pci, advansys_pci_tbl); |
78e77d8b | 14693 | |
9649af39 MW |
14694 | static void __devinit advansys_set_latency(struct pci_dev *pdev) |
14695 | { | |
14696 | if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) || | |
14697 | (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) { | |
14698 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0); | |
14699 | } else { | |
14700 | u8 latency; | |
14701 | pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency); | |
14702 | if (latency < 0x20) | |
14703 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20); | |
14704 | } | |
14705 | } | |
14706 | ||
78e77d8b MW |
14707 | static int __devinit |
14708 | advansys_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
14709 | { | |
14710 | int err, ioport; | |
14711 | struct Scsi_Host *shost; | |
14712 | ||
14713 | err = pci_enable_device(pdev); | |
14714 | if (err) | |
14715 | goto fail; | |
01fbfe0b | 14716 | err = pci_request_regions(pdev, DRV_NAME); |
71f36115 MW |
14717 | if (err) |
14718 | goto disable_device; | |
9649af39 MW |
14719 | pci_set_master(pdev); |
14720 | advansys_set_latency(pdev); | |
78e77d8b MW |
14721 | |
14722 | if (pci_resource_len(pdev, 0) == 0) | |
14723 | goto nodev; | |
14724 | ||
14725 | ioport = pci_resource_start(pdev, 0); | |
14726 | shost = advansys_board_found(ioport, &pdev->dev, ASC_IS_PCI); | |
14727 | ||
14728 | if (!shost) | |
14729 | goto nodev; | |
14730 | ||
14731 | pci_set_drvdata(pdev, shost); | |
14732 | return 0; | |
14733 | ||
14734 | nodev: | |
14735 | err = -ENODEV; | |
71f36115 MW |
14736 | pci_release_regions(pdev); |
14737 | disable_device: | |
78e77d8b MW |
14738 | pci_disable_device(pdev); |
14739 | fail: | |
14740 | return err; | |
14741 | } | |
14742 | ||
14743 | static void __devexit advansys_pci_remove(struct pci_dev *pdev) | |
14744 | { | |
14745 | advansys_release(pci_get_drvdata(pdev)); | |
71f36115 | 14746 | pci_release_regions(pdev); |
78e77d8b MW |
14747 | pci_disable_device(pdev); |
14748 | } | |
14749 | ||
14750 | static struct pci_driver advansys_pci_driver = { | |
01fbfe0b | 14751 | .name = DRV_NAME, |
78e77d8b MW |
14752 | .id_table = advansys_pci_tbl, |
14753 | .probe = advansys_pci_probe, | |
14754 | .remove = __devexit_p(advansys_pci_remove), | |
14755 | }; | |
8c6af9e1 | 14756 | |
8dfb5379 MW |
14757 | static int __init advansys_init(void) |
14758 | { | |
c304ec94 | 14759 | int error; |
b09e05a7 | 14760 | |
c304ec94 MW |
14761 | error = isa_register_driver(&advansys_isa_driver, |
14762 | ASC_IOADR_TABLE_MAX_IX); | |
78e77d8b MW |
14763 | if (error) |
14764 | goto fail; | |
8dfb5379 | 14765 | |
c304ec94 MW |
14766 | error = isa_register_driver(&advansys_vlb_driver, |
14767 | ASC_IOADR_TABLE_MAX_IX); | |
14768 | if (error) | |
14769 | goto unregister_isa; | |
14770 | ||
14771 | error = eisa_driver_register(&advansys_eisa_driver); | |
14772 | if (error) | |
14773 | goto unregister_vlb; | |
14774 | ||
b09e05a7 MW |
14775 | error = pci_register_driver(&advansys_pci_driver); |
14776 | if (error) | |
14777 | goto unregister_eisa; | |
14778 | ||
8dfb5379 | 14779 | return 0; |
78e77d8b | 14780 | |
b09e05a7 MW |
14781 | unregister_eisa: |
14782 | eisa_driver_unregister(&advansys_eisa_driver); | |
c304ec94 MW |
14783 | unregister_vlb: |
14784 | isa_unregister_driver(&advansys_vlb_driver); | |
14785 | unregister_isa: | |
14786 | isa_unregister_driver(&advansys_isa_driver); | |
78e77d8b | 14787 | fail: |
78e77d8b | 14788 | return error; |
8dfb5379 MW |
14789 | } |
14790 | ||
14791 | static void __exit advansys_exit(void) | |
14792 | { | |
78e77d8b | 14793 | pci_unregister_driver(&advansys_pci_driver); |
b09e05a7 | 14794 | eisa_driver_unregister(&advansys_eisa_driver); |
c304ec94 MW |
14795 | isa_unregister_driver(&advansys_vlb_driver); |
14796 | isa_unregister_driver(&advansys_isa_driver); | |
8dfb5379 MW |
14797 | } |
14798 | ||
14799 | module_init(advansys_init); | |
14800 | module_exit(advansys_exit); | |
14801 | ||
8c6af9e1 | 14802 | MODULE_LICENSE("GPL"); |