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scsi: replace seq_printf with seq_puts
[deliverable/linux.git] / drivers / scsi / advansys.c
CommitLineData
01fbfe0b 1#define DRV_NAME "advansys"
8c6af9e1 2#define ASC_VERSION "3.4" /* AdvanSys Driver Version */
1da177e4
LT		 3
4/*
5 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
6 *
7 * Copyright (c) 1995-2000 Advanced System Products, Inc.
8 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
8c6af9e1 9 * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
1da177e4
LT		 10 * All Rights Reserved.
11 *
8c6af9e1
MW		 12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 */
17
18/*
1da177e4
LT		 19 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
20 * changed its name to ConnectCom Solutions, Inc.
8c6af9e1 21 * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
1da177e4
LT		 22 */
23
1da177e4 24#include <linux/module.h>
1da177e4
LT		 25#include <linux/string.h>
26#include <linux/kernel.h>
27#include <linux/types.h>
28#include <linux/ioport.h>
29#include <linux/interrupt.h>
30#include <linux/delay.h>
31#include <linux/slab.h>
32#include <linux/mm.h>
33#include <linux/proc_fs.h>
34#include <linux/init.h>
35#include <linux/blkdev.h>
c304ec94 36#include <linux/isa.h>
b09e05a7 37#include <linux/eisa.h>
8c6af9e1 38#include <linux/pci.h>
1da177e4
LT		 39#include <linux/spinlock.h>
40#include <linux/dma-mapping.h>
989bb5f5 41#include <linux/firmware.h>
1da177e4
LT		 42
43#include <asm/io.h>
1da177e4
LT		 44#include <asm/dma.h>
45
8c6af9e1
MW		 46#include <scsi/scsi_cmnd.h>
47#include <scsi/scsi_device.h>
48#include <scsi/scsi_tcq.h>
49#include <scsi/scsi.h>
50#include <scsi/scsi_host.h>
51
4bd6d7f3 52/* FIXME:
1da177e4 53 *
4bd6d7f3
MW		 54 * 1. Although all of the necessary command mapping places have the
55 * appropriate dma_map.. APIs, the driver still processes its internal
56 * queue using bus_to_virt() and virt_to_bus() which are illegal under
57 * the API. The entire queue processing structure will need to be
58 * altered to fix this.
59 * 2. Need to add memory mapping workaround. Test the memory mapping.
60 * If it doesn't work revert to I/O port access. Can a test be done
61 * safely?
62 * 3. Handle an interrupt not working. Keep an interrupt counter in
63 * the interrupt handler. In the timeout function if the interrupt
64 * has not occurred then print a message and run in polled mode.
65 * 4. Need to add support for target mode commands, cf. CAM XPT.
66 * 5. check DMA mapping functions for failure
349d2c44
MW		 67 * 6. Use scsi_transport_spi
68 * 7. advansys_info is not safe against multiple simultaneous callers
9d0e96eb 69 * 8. Add module_param to override ISA/VLB ioport array
1da177e4
LT		 70 */
71#warning this driver is still not properly converted to the DMA API
72
1da177e4
LT		 73/* Enable driver /proc statistics. */
74#define ADVANSYS_STATS
75
76/* Enable driver tracing. */
b352f923 77#undef ADVANSYS_DEBUG
1da177e4 78
1da177e4
LT		 79/*
80 * Portable Data Types
81 *
82 * Any instance where a 32-bit long or pointer type is assumed
83 * for precision or HW defined structures, the following define
84 * types must be used. In Linux the char, short, and int types
85 * are all consistent at 8, 16, and 32 bits respectively. Pointers
86 * and long types are 64 bits on Alpha and UltraSPARC.
87 */
27c868c2
MW		 88#define ASC_PADDR __u32 /* Physical/Bus address data type. */
89#define ASC_VADDR __u32 /* Virtual address data type. */
90#define ASC_DCNT __u32 /* Unsigned Data count type. */
91#define ASC_SDCNT __s32 /* Signed Data count type. */
1da177e4 92
1da177e4
LT		 93typedef unsigned char uchar;
94
95#ifndef TRUE
96#define TRUE (1)
97#endif
98#ifndef FALSE
99#define FALSE (0)
100#endif
101
1da177e4
LT		 102#define ERR (-1)
103#define UW_ERR (uint)(0xFFFF)
104#define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
1da177e4 105
2672ea86
DJ		 106#define PCI_VENDOR_ID_ASP 0x10cd
107#define PCI_DEVICE_ID_ASP_1200A 0x1100
108#define PCI_DEVICE_ID_ASP_ABP940 0x1200
109#define PCI_DEVICE_ID_ASP_ABP940U 0x1300
110#define PCI_DEVICE_ID_ASP_ABP940UW 0x2300
111#define PCI_DEVICE_ID_38C0800_REV1 0x2500
112#define PCI_DEVICE_ID_38C1600_REV1 0x2700
113
1da177e4
LT		 114/*
115 * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
116 * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
117 * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
118 * SRB structure.
119 */
120#define CC_VERY_LONG_SG_LIST 0
121#define ASC_SRB2SCSIQ(srb_ptr) (srb_ptr)
122
9d511a4b 123#define PortAddr unsigned int /* port address size */
1da177e4
LT		 124#define inp(port) inb(port)
125#define outp(port, byte) outb((byte), (port))
126
127#define inpw(port) inw(port)
128#define outpw(port, word) outw((word), (port))
129
130#define ASC_MAX_SG_QUEUE 7
131#define ASC_MAX_SG_LIST 255
132
133#define ASC_CS_TYPE unsigned short
134
135#define ASC_IS_ISA (0x0001)
136#define ASC_IS_ISAPNP (0x0081)
137#define ASC_IS_EISA (0x0002)
138#define ASC_IS_PCI (0x0004)
139#define ASC_IS_PCI_ULTRA (0x0104)
140#define ASC_IS_PCMCIA (0x0008)
141#define ASC_IS_MCA (0x0020)
142#define ASC_IS_VL (0x0040)
1da177e4
LT		 143#define ASC_IS_WIDESCSI_16 (0x0100)
144#define ASC_IS_WIDESCSI_32 (0x0200)
145#define ASC_IS_BIG_ENDIAN (0x8000)
95c9f162 146
1da177e4
LT		 147#define ASC_CHIP_MIN_VER_VL (0x01)
148#define ASC_CHIP_MAX_VER_VL (0x07)
149#define ASC_CHIP_MIN_VER_PCI (0x09)
150#define ASC_CHIP_MAX_VER_PCI (0x0F)
151#define ASC_CHIP_VER_PCI_BIT (0x08)
152#define ASC_CHIP_MIN_VER_ISA (0x11)
153#define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
154#define ASC_CHIP_MAX_VER_ISA (0x27)
155#define ASC_CHIP_VER_ISA_BIT (0x30)
156#define ASC_CHIP_VER_ISAPNP_BIT (0x20)
157#define ASC_CHIP_VER_ASYN_BUG (0x21)
158#define ASC_CHIP_VER_PCI 0x08
159#define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
160#define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
161#define ASC_CHIP_MIN_VER_EISA (0x41)
162#define ASC_CHIP_MAX_VER_EISA (0x47)
163#define ASC_CHIP_VER_EISA_BIT (0x40)
164#define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
1da177e4 165#define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
1da177e4 166#define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
1da177e4 167#define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL)
1da177e4
LT		 168
169#define ASC_SCSI_ID_BITS 3
170#define ASC_SCSI_TIX_TYPE uchar
171#define ASC_ALL_DEVICE_BIT_SET 0xFF
172#define ASC_SCSI_BIT_ID_TYPE uchar
173#define ASC_MAX_TID 7
174#define ASC_MAX_LUN 7
175#define ASC_SCSI_WIDTH_BIT_SET 0xFF
176#define ASC_MAX_SENSE_LEN 32
177#define ASC_MIN_SENSE_LEN 14
1da177e4
LT		 178#define ASC_SCSI_RESET_HOLD_TIME_US 60
179
f05ec594
MW		 180/*
181 * Narrow boards only support 12-byte commands, while wide boards
182 * extend to 16-byte commands.
183 */
184#define ASC_MAX_CDB_LEN 12
185#define ADV_MAX_CDB_LEN 16
186
1da177e4 187#define MS_SDTR_LEN 0x03
1da177e4 188#define MS_WDTR_LEN 0x02
1da177e4
LT		 189
190#define ASC_SG_LIST_PER_Q 7
191#define QS_FREE 0x00
192#define QS_READY 0x01
193#define QS_DISC1 0x02
194#define QS_DISC2 0x04
195#define QS_BUSY 0x08
196#define QS_ABORTED 0x40
197#define QS_DONE 0x80
198#define QC_NO_CALLBACK 0x01
199#define QC_SG_SWAP_QUEUE 0x02
200#define QC_SG_HEAD 0x04
201#define QC_DATA_IN 0x08
202#define QC_DATA_OUT 0x10
203#define QC_URGENT 0x20
204#define QC_MSG_OUT 0x40
205#define QC_REQ_SENSE 0x80
206#define QCSG_SG_XFER_LIST 0x02
207#define QCSG_SG_XFER_MORE 0x04
208#define QCSG_SG_XFER_END 0x08
209#define QD_IN_PROGRESS 0x00
210#define QD_NO_ERROR 0x01
211#define QD_ABORTED_BY_HOST 0x02
212#define QD_WITH_ERROR 0x04
213#define QD_INVALID_REQUEST 0x80
214#define QD_INVALID_HOST_NUM 0x81
215#define QD_INVALID_DEVICE 0x82
216#define QD_ERR_INTERNAL 0xFF
217#define QHSTA_NO_ERROR 0x00
218#define QHSTA_M_SEL_TIMEOUT 0x11
219#define QHSTA_M_DATA_OVER_RUN 0x12
220#define QHSTA_M_DATA_UNDER_RUN 0x12
221#define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
222#define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
223#define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
224#define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
225#define QHSTA_D_HOST_ABORT_FAILED 0x23
226#define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
227#define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
228#define QHSTA_D_ASPI_NO_BUF_POOL 0x26
229#define QHSTA_M_WTM_TIMEOUT 0x41
230#define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
231#define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
232#define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
233#define QHSTA_M_TARGET_STATUS_BUSY 0x45
234#define QHSTA_M_BAD_TAG_CODE 0x46
235#define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
236#define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
237#define QHSTA_D_LRAM_CMP_ERROR 0x81
238#define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
239#define ASC_FLAG_SCSIQ_REQ 0x01
240#define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
241#define ASC_FLAG_BIOS_ASYNC_IO 0x04
242#define ASC_FLAG_SRB_LINEAR_ADDR 0x08
243#define ASC_FLAG_WIN16 0x10
244#define ASC_FLAG_WIN32 0x20
245#define ASC_FLAG_ISA_OVER_16MB 0x40
246#define ASC_FLAG_DOS_VM_CALLBACK 0x80
247#define ASC_TAG_FLAG_EXTRA_BYTES 0x10
248#define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
249#define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
250#define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
251#define ASC_SCSIQ_CPY_BEG 4
252#define ASC_SCSIQ_SGHD_CPY_BEG 2
253#define ASC_SCSIQ_B_FWD 0
254#define ASC_SCSIQ_B_BWD 1
255#define ASC_SCSIQ_B_STATUS 2
256#define ASC_SCSIQ_B_QNO 3
257#define ASC_SCSIQ_B_CNTL 4
258#define ASC_SCSIQ_B_SG_QUEUE_CNT 5
259#define ASC_SCSIQ_D_DATA_ADDR 8
260#define ASC_SCSIQ_D_DATA_CNT 12
261#define ASC_SCSIQ_B_SENSE_LEN 20
262#define ASC_SCSIQ_DONE_INFO_BEG 22
263#define ASC_SCSIQ_D_SRBPTR 22
264#define ASC_SCSIQ_B_TARGET_IX 26
265#define ASC_SCSIQ_B_CDB_LEN 28
266#define ASC_SCSIQ_B_TAG_CODE 29
267#define ASC_SCSIQ_W_VM_ID 30
268#define ASC_SCSIQ_DONE_STATUS 32
269#define ASC_SCSIQ_HOST_STATUS 33
270#define ASC_SCSIQ_SCSI_STATUS 34
271#define ASC_SCSIQ_CDB_BEG 36
272#define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
273#define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
274#define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
275#define ASC_SCSIQ_B_SG_WK_QP 49
276#define ASC_SCSIQ_B_SG_WK_IX 50
277#define ASC_SCSIQ_W_ALT_DC1 52
278#define ASC_SCSIQ_B_LIST_CNT 6
279#define ASC_SCSIQ_B_CUR_LIST_CNT 7
280#define ASC_SGQ_B_SG_CNTL 4
281#define ASC_SGQ_B_SG_HEAD_QP 5
282#define ASC_SGQ_B_SG_LIST_CNT 6
283#define ASC_SGQ_B_SG_CUR_LIST_CNT 7
284#define ASC_SGQ_LIST_BEG 8
285#define ASC_DEF_SCSI1_QNG 4
286#define ASC_MAX_SCSI1_QNG 4
287#define ASC_DEF_SCSI2_QNG 16
288#define ASC_MAX_SCSI2_QNG 32
289#define ASC_TAG_CODE_MASK 0x23
290#define ASC_STOP_REQ_RISC_STOP 0x01
291#define ASC_STOP_ACK_RISC_STOP 0x03
292#define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
293#define ASC_STOP_CLEAN_UP_DISC_Q 0x20
294#define ASC_STOP_HOST_REQ_RISC_HALT 0x40
295#define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
296#define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
297#define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
298#define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
299#define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
300#define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
301#define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
302
303typedef struct asc_scsiq_1 {
27c868c2
MW		 304 uchar status;
305 uchar q_no;
306 uchar cntl;
307 uchar sg_queue_cnt;
308 uchar target_id;
309 uchar target_lun;
310 ASC_PADDR data_addr;
311 ASC_DCNT data_cnt;
312 ASC_PADDR sense_addr;
313 uchar sense_len;
314 uchar extra_bytes;
1da177e4
LT		 315} ASC_SCSIQ_1;
316
317typedef struct asc_scsiq_2 {
27c868c2
MW		 318 ASC_VADDR srb_ptr;
319 uchar target_ix;
320 uchar flag;
321 uchar cdb_len;
322 uchar tag_code;
323 ushort vm_id;
1da177e4
LT		 324} ASC_SCSIQ_2;
325
326typedef struct asc_scsiq_3 {
27c868c2
MW		 327 uchar done_stat;
328 uchar host_stat;
329 uchar scsi_stat;
330 uchar scsi_msg;
1da177e4
LT		 331} ASC_SCSIQ_3;
332
333typedef struct asc_scsiq_4 {
27c868c2
MW		 334 uchar cdb[ASC_MAX_CDB_LEN];
335 uchar y_first_sg_list_qp;
336 uchar y_working_sg_qp;
337 uchar y_working_sg_ix;
338 uchar y_res;
339 ushort x_req_count;
340 ushort x_reconnect_rtn;
341 ASC_PADDR x_saved_data_addr;
342 ASC_DCNT x_saved_data_cnt;
1da177e4
LT		 343} ASC_SCSIQ_4;
344
345typedef struct asc_q_done_info {
27c868c2
MW		 346 ASC_SCSIQ_2 d2;
347 ASC_SCSIQ_3 d3;
348 uchar q_status;
349 uchar q_no;
350 uchar cntl;
351 uchar sense_len;
352 uchar extra_bytes;
353 uchar res;
354 ASC_DCNT remain_bytes;
1da177e4
LT		 355} ASC_QDONE_INFO;
356
357typedef struct asc_sg_list {
27c868c2
MW		 358 ASC_PADDR addr;
359 ASC_DCNT bytes;
1da177e4
LT		 360} ASC_SG_LIST;
361
362typedef struct asc_sg_head {
27c868c2
MW		 363 ushort entry_cnt;
364 ushort queue_cnt;
365 ushort entry_to_copy;
366 ushort res;
05848b6e 367 ASC_SG_LIST sg_list[0];
1da177e4
LT		 368} ASC_SG_HEAD;
369
1da177e4 370typedef struct asc_scsi_q {
27c868c2
MW		 371 ASC_SCSIQ_1 q1;
372 ASC_SCSIQ_2 q2;
373 uchar *cdbptr;
374 ASC_SG_HEAD *sg_head;
375 ushort remain_sg_entry_cnt;
376 ushort next_sg_index;
1da177e4
LT		 377} ASC_SCSI_Q;
378
379typedef struct asc_scsi_req_q {
27c868c2
MW		 380 ASC_SCSIQ_1 r1;
381 ASC_SCSIQ_2 r2;
382 uchar *cdbptr;
383 ASC_SG_HEAD *sg_head;
384 uchar *sense_ptr;
385 ASC_SCSIQ_3 r3;
386 uchar cdb[ASC_MAX_CDB_LEN];
387 uchar sense[ASC_MIN_SENSE_LEN];
1da177e4
LT		 388} ASC_SCSI_REQ_Q;
389
390typedef struct asc_scsi_bios_req_q {
27c868c2
MW		 391 ASC_SCSIQ_1 r1;
392 ASC_SCSIQ_2 r2;
393 uchar *cdbptr;
394 ASC_SG_HEAD *sg_head;
395 uchar *sense_ptr;
396 ASC_SCSIQ_3 r3;
397 uchar cdb[ASC_MAX_CDB_LEN];
398 uchar sense[ASC_MIN_SENSE_LEN];
1da177e4
LT		 399} ASC_SCSI_BIOS_REQ_Q;
400
401typedef struct asc_risc_q {
27c868c2
MW		 402 uchar fwd;
403 uchar bwd;
404 ASC_SCSIQ_1 i1;
405 ASC_SCSIQ_2 i2;
406 ASC_SCSIQ_3 i3;
407 ASC_SCSIQ_4 i4;
1da177e4
LT		 408} ASC_RISC_Q;
409
410typedef struct asc_sg_list_q {
27c868c2
MW		 411 uchar seq_no;
412 uchar q_no;
413 uchar cntl;
414 uchar sg_head_qp;
415 uchar sg_list_cnt;
416 uchar sg_cur_list_cnt;
1da177e4
LT		 417} ASC_SG_LIST_Q;
418
419typedef struct asc_risc_sg_list_q {
27c868c2
MW		 420 uchar fwd;
421 uchar bwd;
422 ASC_SG_LIST_Q sg;
423 ASC_SG_LIST sg_list[7];
1da177e4
LT		 424} ASC_RISC_SG_LIST_Q;
425
1da177e4 426#define ASCQ_ERR_Q_STATUS 0x0D
1da177e4
LT		 427#define ASCQ_ERR_CUR_QNG 0x17
428#define ASCQ_ERR_SG_Q_LINKS 0x18
1da177e4
LT		 429#define ASCQ_ERR_ISR_RE_ENTRY 0x1A
430#define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
431#define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
1da177e4
LT		 432
433/*
434 * Warning code values are set in ASC_DVC_VAR 'warn_code'.
435 */
436#define ASC_WARN_NO_ERROR 0x0000
437#define ASC_WARN_IO_PORT_ROTATE 0x0001
438#define ASC_WARN_EEPROM_CHKSUM 0x0002
439#define ASC_WARN_IRQ_MODIFIED 0x0004
440#define ASC_WARN_AUTO_CONFIG 0x0008
441#define ASC_WARN_CMD_QNG_CONFLICT 0x0010
442#define ASC_WARN_EEPROM_RECOVER 0x0020
443#define ASC_WARN_CFG_MSW_RECOVER 0x0040
1da177e4
LT		 444
445/*
720349a8 446 * Error code values are set in {ASC/ADV}_DVC_VAR 'err_code'.
1da177e4 447 */
720349a8
MW		 448#define ASC_IERR_NO_CARRIER 0x0001 /* No more carrier memory */
449#define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
450#define ASC_IERR_SET_PC_ADDR 0x0004
451#define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
452#define ASC_IERR_ILLEGAL_CONNECTION 0x0010 /* Illegal cable connection */
453#define ASC_IERR_SINGLE_END_DEVICE 0x0020 /* SE device on DIFF bus */
454#define ASC_IERR_REVERSED_CABLE 0x0040 /* Narrow flat cable reversed */
455#define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
456#define ASC_IERR_HVD_DEVICE 0x0100 /* HVD device on LVD port */
457#define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
458#define ASC_IERR_NO_BUS_TYPE 0x0400
459#define ASC_IERR_BIST_PRE_TEST 0x0800 /* BIST pre-test error */
460#define ASC_IERR_BIST_RAM_TEST 0x1000 /* BIST RAM test error */
461#define ASC_IERR_BAD_CHIPTYPE 0x2000 /* Invalid chip_type setting */
1da177e4 462
1da177e4
LT		 463#define ASC_DEF_MAX_TOTAL_QNG (0xF0)
464#define ASC_MIN_TAG_Q_PER_DVC (0x04)
95c9f162 465#define ASC_MIN_FREE_Q (0x02)
1da177e4
LT		 466#define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
467#define ASC_MAX_TOTAL_QNG 240
468#define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
469#define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
470#define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
471#define ASC_MAX_INRAM_TAG_QNG 16
1da177e4 472#define ASC_IOADR_GAP 0x10
1da177e4
LT		 473#define ASC_SYN_MAX_OFFSET 0x0F
474#define ASC_DEF_SDTR_OFFSET 0x0F
1da177e4 475#define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
afbb68c3
MW		 476#define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
477
478/* The narrow chip only supports a limited selection of transfer rates.
479 * These are encoded in the range 0..7 or 0..15 depending whether the chip
480 * is Ultra-capable or not. These tables let us convert from one to the other.
481 */
482static const unsigned char asc_syn_xfer_period[8] = {
483 25, 30, 35, 40, 50, 60, 70, 85
484};
485
486static const unsigned char asc_syn_ultra_xfer_period[16] = {
487 12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107
488};
1da177e4
LT		 489
490typedef struct ext_msg {
27c868c2
MW		 491 uchar msg_type;
492 uchar msg_len;
493 uchar msg_req;
494 union {
495 struct {
496 uchar sdtr_xfer_period;
497 uchar sdtr_req_ack_offset;
498 } sdtr;
499 struct {
500 uchar wdtr_width;
501 } wdtr;
502 struct {
503 uchar mdp_b3;
504 uchar mdp_b2;
505 uchar mdp_b1;
506 uchar mdp_b0;
507 } mdp;
508 } u_ext_msg;
509 uchar res;
1da177e4
LT		 510} EXT_MSG;
511
512#define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
513#define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
514#define wdtr_width u_ext_msg.wdtr.wdtr_width
515#define mdp_b3 u_ext_msg.mdp_b3
516#define mdp_b2 u_ext_msg.mdp_b2
517#define mdp_b1 u_ext_msg.mdp_b1
518#define mdp_b0 u_ext_msg.mdp_b0
519
520typedef struct asc_dvc_cfg {
27c868c2
MW		 521 ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
522 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
523 ASC_SCSI_BIT_ID_TYPE disc_enable;
524 ASC_SCSI_BIT_ID_TYPE sdtr_enable;
525 uchar chip_scsi_id;
526 uchar isa_dma_speed;
527 uchar isa_dma_channel;
528 uchar chip_version;
27c868c2
MW		 529 ushort mcode_date;
530 ushort mcode_version;
531 uchar max_tag_qng[ASC_MAX_TID + 1];
27c868c2 532 uchar sdtr_period_offset[ASC_MAX_TID + 1];
27c868c2 533 uchar adapter_info[6];
1da177e4
LT		 534} ASC_DVC_CFG;
535
536#define ASC_DEF_DVC_CNTL 0xFFFF
537#define ASC_DEF_CHIP_SCSI_ID 7
538#define ASC_DEF_ISA_DMA_SPEED 4
1da177e4
LT		 539#define ASC_INIT_STATE_BEG_GET_CFG 0x0001
540#define ASC_INIT_STATE_END_GET_CFG 0x0002
541#define ASC_INIT_STATE_BEG_SET_CFG 0x0004
542#define ASC_INIT_STATE_END_SET_CFG 0x0008
543#define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
544#define ASC_INIT_STATE_END_LOAD_MC 0x0020
545#define ASC_INIT_STATE_BEG_INQUIRY 0x0040
546#define ASC_INIT_STATE_END_INQUIRY 0x0080
547#define ASC_INIT_RESET_SCSI_DONE 0x0100
548#define ASC_INIT_STATE_WITHOUT_EEP 0x8000
1da177e4
LT		 549#define ASC_BUG_FIX_IF_NOT_DWB 0x0001
550#define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
1da177e4
LT		 551#define ASC_MIN_TAGGED_CMD 7
552#define ASC_MAX_SCSI_RESET_WAIT 30
d10fb2c7 553#define ASC_OVERRUN_BSIZE 64
1da177e4 554
27c868c2 555struct asc_dvc_var; /* Forward Declaration. */
1da177e4 556
1da177e4 557typedef struct asc_dvc_var {
27c868c2
MW		 558 PortAddr iop_base;
559 ushort err_code;
560 ushort dvc_cntl;
561 ushort bug_fix_cntl;
562 ushort bus_type;
27c868c2
MW		 563 ASC_SCSI_BIT_ID_TYPE init_sdtr;
564 ASC_SCSI_BIT_ID_TYPE sdtr_done;
565 ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
566 ASC_SCSI_BIT_ID_TYPE unit_not_ready;
567 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
568 ASC_SCSI_BIT_ID_TYPE start_motor;
7d5d408c 569 uchar *overrun_buf;
d10fb2c7 570 dma_addr_t overrun_dma;
27c868c2
MW		 571 uchar scsi_reset_wait;
572 uchar chip_no;
573 char is_in_int;
574 uchar max_total_qng;
575 uchar cur_total_qng;
576 uchar in_critical_cnt;
27c868c2
MW		 577 uchar last_q_shortage;
578 ushort init_state;
579 uchar cur_dvc_qng[ASC_MAX_TID + 1];
580 uchar max_dvc_qng[ASC_MAX_TID + 1];
581 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
582 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
afbb68c3 583 const uchar *sdtr_period_tbl;
27c868c2
MW		 584 ASC_DVC_CFG *cfg;
585 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
586 char redo_scam;
587 ushort res2;
588 uchar dos_int13_table[ASC_MAX_TID + 1];
589 ASC_DCNT max_dma_count;
590 ASC_SCSI_BIT_ID_TYPE no_scam;
591 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
afbb68c3 592 uchar min_sdtr_index;
27c868c2 593 uchar max_sdtr_index;
27c868c2 594 struct asc_board *drv_ptr;
b249c7fd
MW		 595 int ptr_map_count;
596 void **ptr_map;
27c868c2 597 ASC_DCNT uc_break;
1da177e4
LT		 598} ASC_DVC_VAR;
599
600typedef struct asc_dvc_inq_info {
27c868c2 601 uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
1da177e4
LT		 602} ASC_DVC_INQ_INFO;
603
604typedef struct asc_cap_info {
27c868c2
MW		 605 ASC_DCNT lba;
606 ASC_DCNT blk_size;
1da177e4
LT		 607} ASC_CAP_INFO;
608
609typedef struct asc_cap_info_array {
27c868c2 610 ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
1da177e4
LT		 611} ASC_CAP_INFO_ARRAY;
612
613#define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
614#define ASC_MCNTL_NULL_TARGET (ushort)0x0002
615#define ASC_CNTL_INITIATOR (ushort)0x0001
616#define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
617#define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
618#define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
619#define ASC_CNTL_NO_SCAM (ushort)0x0010
620#define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
621#define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
622#define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
623#define ASC_CNTL_RESET_SCSI (ushort)0x0200
624#define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
625#define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
626#define ASC_CNTL_SCSI_PARITY (ushort)0x1000
627#define ASC_CNTL_BURST_MODE (ushort)0x2000
628#define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
629#define ASC_EEP_DVC_CFG_BEG_VL 2
630#define ASC_EEP_MAX_DVC_ADDR_VL 15
631#define ASC_EEP_DVC_CFG_BEG 32
632#define ASC_EEP_MAX_DVC_ADDR 45
1da177e4 633#define ASC_EEP_MAX_RETRY 20
1da177e4
LT		 634
635/*
636 * These macros keep the chip SCSI id and ISA DMA speed
637 * bitfields in board order. C bitfields aren't portable
638 * between big and little-endian platforms so they are
639 * not used.
640 */
641
642#define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
643#define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
644#define ASC_EEP_SET_CHIP_ID(cfg, sid) \
645 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
646#define ASC_EEP_SET_DMA_SPD(cfg, spd) \
647 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
648
649typedef struct asceep_config {
27c868c2
MW		 650 ushort cfg_lsw;
651 ushort cfg_msw;
652 uchar init_sdtr;
653 uchar disc_enable;
654 uchar use_cmd_qng;
655 uchar start_motor;
656 uchar max_total_qng;
657 uchar max_tag_qng;
658 uchar bios_scan;
659 uchar power_up_wait;
660 uchar no_scam;
661 uchar id_speed; /* low order 4 bits is chip scsi id */
662 /* high order 4 bits is isa dma speed */
663 uchar dos_int13_table[ASC_MAX_TID + 1];
664 uchar adapter_info[6];
665 ushort cntl;
666 ushort chksum;
1da177e4
LT		 667} ASCEEP_CONFIG;
668
1da177e4
LT		 669#define ASC_EEP_CMD_READ 0x80
670#define ASC_EEP_CMD_WRITE 0x40
671#define ASC_EEP_CMD_WRITE_ABLE 0x30
672#define ASC_EEP_CMD_WRITE_DISABLE 0x00
1da177e4
LT		 673#define ASCV_MSGOUT_BEG 0x0000
674#define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
675#define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
676#define ASCV_BREAK_SAVED_CODE (ushort)0x0006
677#define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
678#define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
679#define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
680#define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
681#define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
682#define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
683#define ASCV_BREAK_ADDR (ushort)0x0028
684#define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
685#define ASCV_BREAK_CONTROL (ushort)0x002C
686#define ASCV_BREAK_HIT_COUNT (ushort)0x002E
687
688#define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
689#define ASCV_MCODE_CHKSUM_W (ushort)0x0032
690#define ASCV_MCODE_SIZE_W (ushort)0x0034
691#define ASCV_STOP_CODE_B (ushort)0x0036
692#define ASCV_DVC_ERR_CODE_B (ushort)0x0037
693#define ASCV_OVERRUN_PADDR_D (ushort)0x0038
694#define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
695#define ASCV_HALTCODE_W (ushort)0x0040
696#define ASCV_CHKSUM_W (ushort)0x0042
697#define ASCV_MC_DATE_W (ushort)0x0044
698#define ASCV_MC_VER_W (ushort)0x0046
699#define ASCV_NEXTRDY_B (ushort)0x0048
700#define ASCV_DONENEXT_B (ushort)0x0049
701#define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
702#define ASCV_SCSIBUSY_B (ushort)0x004B
703#define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
704#define ASCV_CURCDB_B (ushort)0x004D
705#define ASCV_RCLUN_B (ushort)0x004E
706#define ASCV_BUSY_QHEAD_B (ushort)0x004F
707#define ASCV_DISC1_QHEAD_B (ushort)0x0050
708#define ASCV_DISC_ENABLE_B (ushort)0x0052
709#define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
710#define ASCV_HOSTSCSI_ID_B (ushort)0x0055
711#define ASCV_MCODE_CNTL_B (ushort)0x0056
712#define ASCV_NULL_TARGET_B (ushort)0x0057
713#define ASCV_FREE_Q_HEAD_W (ushort)0x0058
714#define ASCV_DONE_Q_TAIL_W (ushort)0x005A
715#define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
716#define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
717#define ASCV_HOST_FLAG_B (ushort)0x005D
718#define ASCV_TOTAL_READY_Q_B (ushort)0x0064
719#define ASCV_VER_SERIAL_B (ushort)0x0065
720#define ASCV_HALTCODE_SAVED_W (ushort)0x0066
721#define ASCV_WTM_FLAG_B (ushort)0x0068
722#define ASCV_RISC_FLAG_B (ushort)0x006A
723#define ASCV_REQ_SG_LIST_QP (ushort)0x006B
724#define ASC_HOST_FLAG_IN_ISR 0x01
725#define ASC_HOST_FLAG_ACK_INT 0x02
726#define ASC_RISC_FLAG_GEN_INT 0x01
727#define ASC_RISC_FLAG_REQ_SG_LIST 0x02
728#define IOP_CTRL (0x0F)
729#define IOP_STATUS (0x0E)
730#define IOP_INT_ACK IOP_STATUS
731#define IOP_REG_IFC (0x0D)
732#define IOP_SYN_OFFSET (0x0B)
733#define IOP_EXTRA_CONTROL (0x0D)
734#define IOP_REG_PC (0x0C)
735#define IOP_RAM_ADDR (0x0A)
736#define IOP_RAM_DATA (0x08)
737#define IOP_EEP_DATA (0x06)
738#define IOP_EEP_CMD (0x07)
739#define IOP_VERSION (0x03)
740#define IOP_CONFIG_HIGH (0x04)
741#define IOP_CONFIG_LOW (0x02)
742#define IOP_SIG_BYTE (0x01)
743#define IOP_SIG_WORD (0x00)
744#define IOP_REG_DC1 (0x0E)
745#define IOP_REG_DC0 (0x0C)
746#define IOP_REG_SB (0x0B)
747#define IOP_REG_DA1 (0x0A)
748#define IOP_REG_DA0 (0x08)
749#define IOP_REG_SC (0x09)
750#define IOP_DMA_SPEED (0x07)
751#define IOP_REG_FLAG (0x07)
752#define IOP_FIFO_H (0x06)
753#define IOP_FIFO_L (0x04)
754#define IOP_REG_ID (0x05)
755#define IOP_REG_QP (0x03)
756#define IOP_REG_IH (0x02)
757#define IOP_REG_IX (0x01)
758#define IOP_REG_AX (0x00)
759#define IFC_REG_LOCK (0x00)
760#define IFC_REG_UNLOCK (0x09)
761#define IFC_WR_EN_FILTER (0x10)
762#define IFC_RD_NO_EEPROM (0x10)
763#define IFC_SLEW_RATE (0x20)
764#define IFC_ACT_NEG (0x40)
765#define IFC_INP_FILTER (0x80)
766#define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
767#define SC_SEL (uchar)(0x80)
768#define SC_BSY (uchar)(0x40)
769#define SC_ACK (uchar)(0x20)
770#define SC_REQ (uchar)(0x10)
771#define SC_ATN (uchar)(0x08)
772#define SC_IO (uchar)(0x04)
773#define SC_CD (uchar)(0x02)
774#define SC_MSG (uchar)(0x01)
775#define SEC_SCSI_CTL (uchar)(0x80)
776#define SEC_ACTIVE_NEGATE (uchar)(0x40)
777#define SEC_SLEW_RATE (uchar)(0x20)
778#define SEC_ENABLE_FILTER (uchar)(0x10)
779#define ASC_HALT_EXTMSG_IN (ushort)0x8000
780#define ASC_HALT_CHK_CONDITION (ushort)0x8100
781#define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
782#define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
783#define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
784#define ASC_HALT_SDTR_REJECTED (ushort)0x4000
785#define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
786#define ASC_MAX_QNO 0xF8
787#define ASC_DATA_SEC_BEG (ushort)0x0080
788#define ASC_DATA_SEC_END (ushort)0x0080
789#define ASC_CODE_SEC_BEG (ushort)0x0080
790#define ASC_CODE_SEC_END (ushort)0x0080
791#define ASC_QADR_BEG (0x4000)
792#define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
793#define ASC_QADR_END (ushort)0x7FFF
794#define ASC_QLAST_ADR (ushort)0x7FC0
795#define ASC_QBLK_SIZE 0x40
796#define ASC_BIOS_DATA_QBEG 0xF8
797#define ASC_MIN_ACTIVE_QNO 0x01
798#define ASC_QLINK_END 0xFF
799#define ASC_EEPROM_WORDS 0x10
800#define ASC_MAX_MGS_LEN 0x10
801#define ASC_BIOS_ADDR_DEF 0xDC00
802#define ASC_BIOS_SIZE 0x3800
803#define ASC_BIOS_RAM_OFF 0x3800
804#define ASC_BIOS_RAM_SIZE 0x800
805#define ASC_BIOS_MIN_ADDR 0xC000
806#define ASC_BIOS_MAX_ADDR 0xEC00
807#define ASC_BIOS_BANK_SIZE 0x0400
808#define ASC_MCODE_START_ADDR 0x0080
809#define ASC_CFG0_HOST_INT_ON 0x0020
810#define ASC_CFG0_BIOS_ON 0x0040
811#define ASC_CFG0_VERA_BURST_ON 0x0080
812#define ASC_CFG0_SCSI_PARITY_ON 0x0800
813#define ASC_CFG1_SCSI_TARGET_ON 0x0080
814#define ASC_CFG1_LRAM_8BITS_ON 0x0800
815#define ASC_CFG_MSW_CLR_MASK 0x3080
816#define CSW_TEST1 (ASC_CS_TYPE)0x8000
817#define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
818#define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
819#define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
820#define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
821#define CSW_TEST2 (ASC_CS_TYPE)0x0400
822#define CSW_TEST3 (ASC_CS_TYPE)0x0200
823#define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
824#define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
825#define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
826#define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
827#define CSW_HALTED (ASC_CS_TYPE)0x0010
828#define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
829#define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
830#define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
831#define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
832#define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
833#define CIW_INT_ACK (ASC_CS_TYPE)0x0100
834#define CIW_TEST1 (ASC_CS_TYPE)0x0200
835#define CIW_TEST2 (ASC_CS_TYPE)0x0400
836#define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
837#define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
838#define CC_CHIP_RESET (uchar)0x80
839#define CC_SCSI_RESET (uchar)0x40
840#define CC_HALT (uchar)0x20
841#define CC_SINGLE_STEP (uchar)0x10
842#define CC_DMA_ABLE (uchar)0x08
843#define CC_TEST (uchar)0x04
844#define CC_BANK_ONE (uchar)0x02
845#define CC_DIAG (uchar)0x01
846#define ASC_1000_ID0W 0x04C1
847#define ASC_1000_ID0W_FIX 0x00C1
848#define ASC_1000_ID1B 0x25
1da177e4 849#define ASC_EISA_REV_IOP_MASK (0x0C83)
1da177e4
LT		 850#define ASC_EISA_CFG_IOP_MASK (0x0C86)
851#define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
1da177e4
LT		 852#define INS_HALTINT (ushort)0x6281
853#define INS_HALT (ushort)0x6280
854#define INS_SINT (ushort)0x6200
855#define INS_RFLAG_WTM (ushort)0x7380
856#define ASC_MC_SAVE_CODE_WSIZE 0x500
857#define ASC_MC_SAVE_DATA_WSIZE 0x40
858
859typedef struct asc_mc_saved {
27c868c2
MW		 860 ushort data[ASC_MC_SAVE_DATA_WSIZE];
861 ushort code[ASC_MC_SAVE_CODE_WSIZE];
1da177e4
LT		 862} ASC_MC_SAVED;
863
864#define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
865#define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
866#define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
867#define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
868#define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
869#define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
870#define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
871#define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
872#define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
873#define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
51219358
MW		 874#define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
875#define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
876#define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
877#define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
1da177e4
LT		 878#define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
879#define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
880#define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
881#define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
882#define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
883#define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
884#define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
885#define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
886#define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
887#define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
888#define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
889#define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
890#define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
891#define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
892#define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
893#define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
894#define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
895#define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
896#define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
897#define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
898#define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
899#define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
900#define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
901#define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
902#define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
903#define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
904#define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
905#define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
906#define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
907#define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
908#define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
909#define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
910#define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
911#define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
912#define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
913#define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
914#define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
915#define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
916#define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
917#define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
918#define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
919#define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
920#define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
921#define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
922#define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
923#define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
924#define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
925#define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
926#define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
927#define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
928#define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
929#define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
930#define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
931
1da177e4
LT		 932/*
933 * Portable Data Types
934 *
935 * Any instance where a 32-bit long or pointer type is assumed
936 * for precision or HW defined structures, the following define
937 * types must be used. In Linux the char, short, and int types
938 * are all consistent at 8, 16, and 32 bits respectively. Pointers
939 * and long types are 64 bits on Alpha and UltraSPARC.
940 */
27c868c2
MW		 941#define ADV_PADDR __u32 /* Physical address data type. */
942#define ADV_VADDR __u32 /* Virtual address data type. */
943#define ADV_DCNT __u32 /* Unsigned Data count type. */
944#define ADV_SDCNT __s32 /* Signed Data count type. */
1da177e4
LT		 945
946/*
947 * These macros are used to convert a virtual address to a
948 * 32-bit value. This currently can be used on Linux Alpha
949 * which uses 64-bit virtual address but a 32-bit bus address.
950 * This is likely to break in the future, but doing this now
951 * will give us time to change the HW and FW to handle 64-bit
952 * addresses.
953 */
954#define ADV_VADDR_TO_U32 virt_to_bus
955#define ADV_U32_TO_VADDR bus_to_virt
956
27c868c2 957#define AdvPortAddr void __iomem * /* Virtual memory address size */
1da177e4
LT		 958
959/*
960 * Define Adv Library required memory access macros.
961 */
962#define ADV_MEM_READB(addr) readb(addr)
963#define ADV_MEM_READW(addr) readw(addr)
964#define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
965#define ADV_MEM_WRITEW(addr, word) writew(word, addr)
966#define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
967
968#define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 15)
969
1da177e4
LT		 970/*
971 * Define total number of simultaneous maximum element scatter-gather
972 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
973 * maximum number of outstanding commands per wide host adapter. Each
974 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
975 * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
976 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
977 * structures or 255 scatter-gather elements.
1da177e4
LT		 978 */
979#define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
980
981/*
98d41c29 982 * Define maximum number of scatter-gather elements per request.
1da177e4
LT		 983 */
984#define ADV_MAX_SG_LIST 255
98d41c29 985#define NO_OF_SG_PER_BLOCK 15
1da177e4 986
1da177e4
LT		 987#define ADV_EEP_DVC_CFG_BEGIN (0x00)
988#define ADV_EEP_DVC_CFG_END (0x15)
27c868c2 989#define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
1da177e4
LT		 990#define ADV_EEP_MAX_WORD_ADDR (0x1E)
991
992#define ADV_EEP_DELAY_MS 100
993
27c868c2
MW		 994#define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
995#define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
1da177e4
LT		 996/*
997 * For the ASC3550 Bit 13 is Termination Polarity control bit.
998 * For later ICs Bit 13 controls whether the CIS (Card Information
999 * Service Section) is loaded from EEPROM.
1000 */
27c868c2
MW		 1001#define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
1002#define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
1da177e4
LT		 1003/*
1004 * ASC38C1600 Bit 11
1005 *
1006 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
1007 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
1008 * Function 0 will specify INT B.
1009 *
1010 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
1011 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
1012 * Function 1 will specify INT A.
1013 */
27c868c2
MW		 1014#define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
1015
1016typedef struct adveep_3550_config {
1017 /* Word Offset, Description */
1018
1019 ushort cfg_lsw; /* 00 power up initialization */
1020 /* bit 13 set - Term Polarity Control */
1021 /* bit 14 set - BIOS Enable */
1022 /* bit 15 set - Big Endian Mode */
1023 ushort cfg_msw; /* 01 unused */
1024 ushort disc_enable; /* 02 disconnect enable */
1025 ushort wdtr_able; /* 03 Wide DTR able */
1026 ushort sdtr_able; /* 04 Synchronous DTR able */
1027 ushort start_motor; /* 05 send start up motor */
1028 ushort tagqng_able; /* 06 tag queuing able */
1029 ushort bios_scan; /* 07 BIOS device control */
1030 ushort scam_tolerant; /* 08 no scam */
1031
1032 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1033 uchar bios_boot_delay; /* power up wait */
1034
1035 uchar scsi_reset_delay; /* 10 reset delay */
1036 uchar bios_id_lun; /* first boot device scsi id & lun */
1037 /* high nibble is lun */
1038 /* low nibble is scsi id */
1039
1040 uchar termination; /* 11 0 - automatic */
1041 /* 1 - low off / high off */
1042 /* 2 - low off / high on */
1043 /* 3 - low on / high on */
1044 /* There is no low on / high off */
1045
1046 uchar reserved1; /* reserved byte (not used) */
1047
1048 ushort bios_ctrl; /* 12 BIOS control bits */
1049 /* bit 0 BIOS don't act as initiator. */
1050 /* bit 1 BIOS > 1 GB support */
1051 /* bit 2 BIOS > 2 Disk Support */
1052 /* bit 3 BIOS don't support removables */
1053 /* bit 4 BIOS support bootable CD */
1054 /* bit 5 BIOS scan enabled */
1055 /* bit 6 BIOS support multiple LUNs */
1056 /* bit 7 BIOS display of message */
1057 /* bit 8 SCAM disabled */
1058 /* bit 9 Reset SCSI bus during init. */
1059 /* bit 10 */
1060 /* bit 11 No verbose initialization. */
1061 /* bit 12 SCSI parity enabled */
1062 /* bit 13 */
1063 /* bit 14 */
1064 /* bit 15 */
1065 ushort ultra_able; /* 13 ULTRA speed able */
1066 ushort reserved2; /* 14 reserved */
1067 uchar max_host_qng; /* 15 maximum host queuing */
1068 uchar max_dvc_qng; /* maximum per device queuing */
1069 ushort dvc_cntl; /* 16 control bit for driver */
1070 ushort bug_fix; /* 17 control bit for bug fix */
1071 ushort serial_number_word1; /* 18 Board serial number word 1 */
1072 ushort serial_number_word2; /* 19 Board serial number word 2 */
1073 ushort serial_number_word3; /* 20 Board serial number word 3 */
1074 ushort check_sum; /* 21 EEP check sum */
1075 uchar oem_name[16]; /* 22 OEM name */
1076 ushort dvc_err_code; /* 30 last device driver error code */
1077 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1078 ushort adv_err_addr; /* 32 last uc error address */
1079 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1080 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1081 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1082 ushort num_of_err; /* 36 number of error */
1da177e4
LT		 1083} ADVEEP_3550_CONFIG;
1084
27c868c2
MW		 1085typedef struct adveep_38C0800_config {
1086 /* Word Offset, Description */
1087
1088 ushort cfg_lsw; /* 00 power up initialization */
1089 /* bit 13 set - Load CIS */
1090 /* bit 14 set - BIOS Enable */
1091 /* bit 15 set - Big Endian Mode */
1092 ushort cfg_msw; /* 01 unused */
1093 ushort disc_enable; /* 02 disconnect enable */
1094 ushort wdtr_able; /* 03 Wide DTR able */
1095 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1096 ushort start_motor; /* 05 send start up motor */
1097 ushort tagqng_able; /* 06 tag queuing able */
1098 ushort bios_scan; /* 07 BIOS device control */
1099 ushort scam_tolerant; /* 08 no scam */
1100
1101 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1102 uchar bios_boot_delay; /* power up wait */
1103
1104 uchar scsi_reset_delay; /* 10 reset delay */
1105 uchar bios_id_lun; /* first boot device scsi id & lun */
1106 /* high nibble is lun */
1107 /* low nibble is scsi id */
1108
1109 uchar termination_se; /* 11 0 - automatic */
1110 /* 1 - low off / high off */
1111 /* 2 - low off / high on */
1112 /* 3 - low on / high on */
1113 /* There is no low on / high off */
1114
1115 uchar termination_lvd; /* 11 0 - automatic */
1116 /* 1 - low off / high off */
1117 /* 2 - low off / high on */
1118 /* 3 - low on / high on */
1119 /* There is no low on / high off */
1120
1121 ushort bios_ctrl; /* 12 BIOS control bits */
1122 /* bit 0 BIOS don't act as initiator. */
1123 /* bit 1 BIOS > 1 GB support */
1124 /* bit 2 BIOS > 2 Disk Support */
1125 /* bit 3 BIOS don't support removables */
1126 /* bit 4 BIOS support bootable CD */
1127 /* bit 5 BIOS scan enabled */
1128 /* bit 6 BIOS support multiple LUNs */
1129 /* bit 7 BIOS display of message */
1130 /* bit 8 SCAM disabled */
1131 /* bit 9 Reset SCSI bus during init. */
1132 /* bit 10 */
1133 /* bit 11 No verbose initialization. */
1134 /* bit 12 SCSI parity enabled */
1135 /* bit 13 */
1136 /* bit 14 */
1137 /* bit 15 */
1138 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1139 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1140 uchar max_host_qng; /* 15 maximum host queueing */
1141 uchar max_dvc_qng; /* maximum per device queuing */
1142 ushort dvc_cntl; /* 16 control bit for driver */
1143 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1144 ushort serial_number_word1; /* 18 Board serial number word 1 */
1145 ushort serial_number_word2; /* 19 Board serial number word 2 */
1146 ushort serial_number_word3; /* 20 Board serial number word 3 */
1147 ushort check_sum; /* 21 EEP check sum */
1148 uchar oem_name[16]; /* 22 OEM name */
1149 ushort dvc_err_code; /* 30 last device driver error code */
1150 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1151 ushort adv_err_addr; /* 32 last uc error address */
1152 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1153 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1154 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1155 ushort reserved36; /* 36 reserved */
1156 ushort reserved37; /* 37 reserved */
1157 ushort reserved38; /* 38 reserved */
1158 ushort reserved39; /* 39 reserved */
1159 ushort reserved40; /* 40 reserved */
1160 ushort reserved41; /* 41 reserved */
1161 ushort reserved42; /* 42 reserved */
1162 ushort reserved43; /* 43 reserved */
1163 ushort reserved44; /* 44 reserved */
1164 ushort reserved45; /* 45 reserved */
1165 ushort reserved46; /* 46 reserved */
1166 ushort reserved47; /* 47 reserved */
1167 ushort reserved48; /* 48 reserved */
1168 ushort reserved49; /* 49 reserved */
1169 ushort reserved50; /* 50 reserved */
1170 ushort reserved51; /* 51 reserved */
1171 ushort reserved52; /* 52 reserved */
1172 ushort reserved53; /* 53 reserved */
1173 ushort reserved54; /* 54 reserved */
1174 ushort reserved55; /* 55 reserved */
1175 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1176 ushort cisprt_msw; /* 57 CIS PTR MSW */
1177 ushort subsysvid; /* 58 SubSystem Vendor ID */
1178 ushort subsysid; /* 59 SubSystem ID */
1179 ushort reserved60; /* 60 reserved */
1180 ushort reserved61; /* 61 reserved */
1181 ushort reserved62; /* 62 reserved */
1182 ushort reserved63; /* 63 reserved */
1da177e4
LT		 1183} ADVEEP_38C0800_CONFIG;
1184
27c868c2
MW		 1185typedef struct adveep_38C1600_config {
1186 /* Word Offset, Description */
1187
1188 ushort cfg_lsw; /* 00 power up initialization */
1189 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */
1190 /* clear - Func. 0 INTA, Func. 1 INTB */
1191 /* bit 13 set - Load CIS */
1192 /* bit 14 set - BIOS Enable */
1193 /* bit 15 set - Big Endian Mode */
1194 ushort cfg_msw; /* 01 unused */
1195 ushort disc_enable; /* 02 disconnect enable */
1196 ushort wdtr_able; /* 03 Wide DTR able */
1197 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1198 ushort start_motor; /* 05 send start up motor */
1199 ushort tagqng_able; /* 06 tag queuing able */
1200 ushort bios_scan; /* 07 BIOS device control */
1201 ushort scam_tolerant; /* 08 no scam */
1202
1203 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1204 uchar bios_boot_delay; /* power up wait */
1205
1206 uchar scsi_reset_delay; /* 10 reset delay */
1207 uchar bios_id_lun; /* first boot device scsi id & lun */
1208 /* high nibble is lun */
1209 /* low nibble is scsi id */
1210
1211 uchar termination_se; /* 11 0 - automatic */
1212 /* 1 - low off / high off */
1213 /* 2 - low off / high on */
1214 /* 3 - low on / high on */
1215 /* There is no low on / high off */
1216
1217 uchar termination_lvd; /* 11 0 - automatic */
1218 /* 1 - low off / high off */
1219 /* 2 - low off / high on */
1220 /* 3 - low on / high on */
1221 /* There is no low on / high off */
1222
1223 ushort bios_ctrl; /* 12 BIOS control bits */
1224 /* bit 0 BIOS don't act as initiator. */
1225 /* bit 1 BIOS > 1 GB support */
1226 /* bit 2 BIOS > 2 Disk Support */
1227 /* bit 3 BIOS don't support removables */
1228 /* bit 4 BIOS support bootable CD */
1229 /* bit 5 BIOS scan enabled */
1230 /* bit 6 BIOS support multiple LUNs */
1231 /* bit 7 BIOS display of message */
1232 /* bit 8 SCAM disabled */
1233 /* bit 9 Reset SCSI bus during init. */
1234 /* bit 10 Basic Integrity Checking disabled */
1235 /* bit 11 No verbose initialization. */
1236 /* bit 12 SCSI parity enabled */
1237 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
1238 /* bit 14 */
1239 /* bit 15 */
1240 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1241 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1242 uchar max_host_qng; /* 15 maximum host queueing */
1243 uchar max_dvc_qng; /* maximum per device queuing */
1244 ushort dvc_cntl; /* 16 control bit for driver */
1245 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1246 ushort serial_number_word1; /* 18 Board serial number word 1 */
1247 ushort serial_number_word2; /* 19 Board serial number word 2 */
1248 ushort serial_number_word3; /* 20 Board serial number word 3 */
1249 ushort check_sum; /* 21 EEP check sum */
1250 uchar oem_name[16]; /* 22 OEM name */
1251 ushort dvc_err_code; /* 30 last device driver error code */
1252 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1253 ushort adv_err_addr; /* 32 last uc error address */
1254 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1255 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1256 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1257 ushort reserved36; /* 36 reserved */
1258 ushort reserved37; /* 37 reserved */
1259 ushort reserved38; /* 38 reserved */
1260 ushort reserved39; /* 39 reserved */
1261 ushort reserved40; /* 40 reserved */
1262 ushort reserved41; /* 41 reserved */
1263 ushort reserved42; /* 42 reserved */
1264 ushort reserved43; /* 43 reserved */
1265 ushort reserved44; /* 44 reserved */
1266 ushort reserved45; /* 45 reserved */
1267 ushort reserved46; /* 46 reserved */
1268 ushort reserved47; /* 47 reserved */
1269 ushort reserved48; /* 48 reserved */
1270 ushort reserved49; /* 49 reserved */
1271 ushort reserved50; /* 50 reserved */
1272 ushort reserved51; /* 51 reserved */
1273 ushort reserved52; /* 52 reserved */
1274 ushort reserved53; /* 53 reserved */
1275 ushort reserved54; /* 54 reserved */
1276 ushort reserved55; /* 55 reserved */
1277 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1278 ushort cisprt_msw; /* 57 CIS PTR MSW */
1279 ushort subsysvid; /* 58 SubSystem Vendor ID */
1280 ushort subsysid; /* 59 SubSystem ID */
1281 ushort reserved60; /* 60 reserved */
1282 ushort reserved61; /* 61 reserved */
1283 ushort reserved62; /* 62 reserved */
1284 ushort reserved63; /* 63 reserved */
1da177e4
LT		 1285} ADVEEP_38C1600_CONFIG;
1286
1287/*
1288 * EEPROM Commands
1289 */
1290#define ASC_EEP_CMD_DONE 0x0200
1da177e4
LT		 1291
1292/* bios_ctrl */
1293#define BIOS_CTRL_BIOS 0x0001
1294#define BIOS_CTRL_EXTENDED_XLAT 0x0002
1295#define BIOS_CTRL_GT_2_DISK 0x0004
1296#define BIOS_CTRL_BIOS_REMOVABLE 0x0008
1297#define BIOS_CTRL_BOOTABLE_CD 0x0010
1298#define BIOS_CTRL_MULTIPLE_LUN 0x0040
1299#define BIOS_CTRL_DISPLAY_MSG 0x0080
1300#define BIOS_CTRL_NO_SCAM 0x0100
1301#define BIOS_CTRL_RESET_SCSI_BUS 0x0200
1302#define BIOS_CTRL_INIT_VERBOSE 0x0800
1303#define BIOS_CTRL_SCSI_PARITY 0x1000
1304#define BIOS_CTRL_AIPP_DIS 0x2000
1305
27c868c2 1306#define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
1da177e4 1307
27c868c2 1308#define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1da177e4
LT		 1309
1310/*
1311 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
1312 * a special 16K Adv Library and Microcode version. After the issue is
1313 * resolved, should restore 32K support.
1314 *
1315 * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
1316 */
27c868c2 1317#define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1da177e4
LT		 1318
1319/*
1320 * Byte I/O register address from base of 'iop_base'.
1321 */
1322#define IOPB_INTR_STATUS_REG 0x00
1323#define IOPB_CHIP_ID_1 0x01
1324#define IOPB_INTR_ENABLES 0x02
1325#define IOPB_CHIP_TYPE_REV 0x03
1326#define IOPB_RES_ADDR_4 0x04
1327#define IOPB_RES_ADDR_5 0x05
1328#define IOPB_RAM_DATA 0x06
1329#define IOPB_RES_ADDR_7 0x07
1330#define IOPB_FLAG_REG 0x08
1331#define IOPB_RES_ADDR_9 0x09
1332#define IOPB_RISC_CSR 0x0A
1333#define IOPB_RES_ADDR_B 0x0B
1334#define IOPB_RES_ADDR_C 0x0C
1335#define IOPB_RES_ADDR_D 0x0D
1336#define IOPB_SOFT_OVER_WR 0x0E
1337#define IOPB_RES_ADDR_F 0x0F
1338#define IOPB_MEM_CFG 0x10
1339#define IOPB_RES_ADDR_11 0x11
1340#define IOPB_GPIO_DATA 0x12
1341#define IOPB_RES_ADDR_13 0x13
1342#define IOPB_FLASH_PAGE 0x14
1343#define IOPB_RES_ADDR_15 0x15
1344#define IOPB_GPIO_CNTL 0x16
1345#define IOPB_RES_ADDR_17 0x17
1346#define IOPB_FLASH_DATA 0x18
1347#define IOPB_RES_ADDR_19 0x19
1348#define IOPB_RES_ADDR_1A 0x1A
1349#define IOPB_RES_ADDR_1B 0x1B
1350#define IOPB_RES_ADDR_1C 0x1C
1351#define IOPB_RES_ADDR_1D 0x1D
1352#define IOPB_RES_ADDR_1E 0x1E
1353#define IOPB_RES_ADDR_1F 0x1F
1354#define IOPB_DMA_CFG0 0x20
1355#define IOPB_DMA_CFG1 0x21
1356#define IOPB_TICKLE 0x22
1357#define IOPB_DMA_REG_WR 0x23
1358#define IOPB_SDMA_STATUS 0x24
1359#define IOPB_SCSI_BYTE_CNT 0x25
1360#define IOPB_HOST_BYTE_CNT 0x26
1361#define IOPB_BYTE_LEFT_TO_XFER 0x27
1362#define IOPB_BYTE_TO_XFER_0 0x28
1363#define IOPB_BYTE_TO_XFER_1 0x29
1364#define IOPB_BYTE_TO_XFER_2 0x2A
1365#define IOPB_BYTE_TO_XFER_3 0x2B
1366#define IOPB_ACC_GRP 0x2C
1367#define IOPB_RES_ADDR_2D 0x2D
1368#define IOPB_DEV_ID 0x2E
1369#define IOPB_RES_ADDR_2F 0x2F
1370#define IOPB_SCSI_DATA 0x30
1371#define IOPB_RES_ADDR_31 0x31
1372#define IOPB_RES_ADDR_32 0x32
1373#define IOPB_SCSI_DATA_HSHK 0x33
1374#define IOPB_SCSI_CTRL 0x34
1375#define IOPB_RES_ADDR_35 0x35
1376#define IOPB_RES_ADDR_36 0x36
1377#define IOPB_RES_ADDR_37 0x37
1378#define IOPB_RAM_BIST 0x38
1379#define IOPB_PLL_TEST 0x39
1380#define IOPB_PCI_INT_CFG 0x3A
1381#define IOPB_RES_ADDR_3B 0x3B
1382#define IOPB_RFIFO_CNT 0x3C
1383#define IOPB_RES_ADDR_3D 0x3D
1384#define IOPB_RES_ADDR_3E 0x3E
1385#define IOPB_RES_ADDR_3F 0x3F
1386
1387/*
1388 * Word I/O register address from base of 'iop_base'.
1389 */
27c868c2
MW		 1390#define IOPW_CHIP_ID_0 0x00 /* CID0 */
1391#define IOPW_CTRL_REG 0x02 /* CC */
1392#define IOPW_RAM_ADDR 0x04 /* LA */
1393#define IOPW_RAM_DATA 0x06 /* LD */
1da177e4 1394#define IOPW_RES_ADDR_08 0x08
27c868c2
MW		 1395#define IOPW_RISC_CSR 0x0A /* CSR */
1396#define IOPW_SCSI_CFG0 0x0C /* CFG0 */
1397#define IOPW_SCSI_CFG1 0x0E /* CFG1 */
1da177e4 1398#define IOPW_RES_ADDR_10 0x10
27c868c2 1399#define IOPW_SEL_MASK 0x12 /* SM */
1da177e4 1400#define IOPW_RES_ADDR_14 0x14
27c868c2 1401#define IOPW_FLASH_ADDR 0x16 /* FA */
1da177e4 1402#define IOPW_RES_ADDR_18 0x18
27c868c2
MW		 1403#define IOPW_EE_CMD 0x1A /* EC */
1404#define IOPW_EE_DATA 0x1C /* ED */
1405#define IOPW_SFIFO_CNT 0x1E /* SFC */
1da177e4 1406#define IOPW_RES_ADDR_20 0x20
27c868c2
MW		 1407#define IOPW_Q_BASE 0x22 /* QB */
1408#define IOPW_QP 0x24 /* QP */
1409#define IOPW_IX 0x26 /* IX */
1410#define IOPW_SP 0x28 /* SP */
1411#define IOPW_PC 0x2A /* PC */
1da177e4
LT		 1412#define IOPW_RES_ADDR_2C 0x2C
1413#define IOPW_RES_ADDR_2E 0x2E
27c868c2
MW		 1414#define IOPW_SCSI_DATA 0x30 /* SD */
1415#define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
1416#define IOPW_SCSI_CTRL 0x34 /* SC */
1417#define IOPW_HSHK_CFG 0x36 /* HCFG */
1418#define IOPW_SXFR_STATUS 0x36 /* SXS */
1419#define IOPW_SXFR_CNTL 0x38 /* SXL */
1420#define IOPW_SXFR_CNTH 0x3A /* SXH */
1da177e4 1421#define IOPW_RES_ADDR_3C 0x3C
27c868c2 1422#define IOPW_RFIFO_DATA 0x3E /* RFD */
1da177e4
LT		 1423
1424/*
1425 * Doubleword I/O register address from base of 'iop_base'.
1426 */
1427#define IOPDW_RES_ADDR_0 0x00
1428#define IOPDW_RAM_DATA 0x04
1429#define IOPDW_RES_ADDR_8 0x08
1430#define IOPDW_RES_ADDR_C 0x0C
1431#define IOPDW_RES_ADDR_10 0x10
1432#define IOPDW_COMMA 0x14
1433#define IOPDW_COMMB 0x18
1434#define IOPDW_RES_ADDR_1C 0x1C
1435#define IOPDW_SDMA_ADDR0 0x20
1436#define IOPDW_SDMA_ADDR1 0x24
1437#define IOPDW_SDMA_COUNT 0x28
1438#define IOPDW_SDMA_ERROR 0x2C
1439#define IOPDW_RDMA_ADDR0 0x30
1440#define IOPDW_RDMA_ADDR1 0x34
1441#define IOPDW_RDMA_COUNT 0x38
1442#define IOPDW_RDMA_ERROR 0x3C
1443
1444#define ADV_CHIP_ID_BYTE 0x25
1445#define ADV_CHIP_ID_WORD 0x04C1
1446
1da177e4
LT		 1447#define ADV_INTR_ENABLE_HOST_INTR 0x01
1448#define ADV_INTR_ENABLE_SEL_INTR 0x02
1449#define ADV_INTR_ENABLE_DPR_INTR 0x04
1450#define ADV_INTR_ENABLE_RTA_INTR 0x08
1451#define ADV_INTR_ENABLE_RMA_INTR 0x10
1452#define ADV_INTR_ENABLE_RST_INTR 0x20
1453#define ADV_INTR_ENABLE_DPE_INTR 0x40
1454#define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
1455
1456#define ADV_INTR_STATUS_INTRA 0x01
1457#define ADV_INTR_STATUS_INTRB 0x02
1458#define ADV_INTR_STATUS_INTRC 0x04
1459
1460#define ADV_RISC_CSR_STOP (0x0000)
1461#define ADV_RISC_TEST_COND (0x2000)
1462#define ADV_RISC_CSR_RUN (0x4000)
1463#define ADV_RISC_CSR_SINGLE_STEP (0x8000)
1464
1465#define ADV_CTRL_REG_HOST_INTR 0x0100
1466#define ADV_CTRL_REG_SEL_INTR 0x0200
1467#define ADV_CTRL_REG_DPR_INTR 0x0400
1468#define ADV_CTRL_REG_RTA_INTR 0x0800
1469#define ADV_CTRL_REG_RMA_INTR 0x1000
1470#define ADV_CTRL_REG_RES_BIT14 0x2000
1471#define ADV_CTRL_REG_DPE_INTR 0x4000
1472#define ADV_CTRL_REG_POWER_DONE 0x8000
1473#define ADV_CTRL_REG_ANY_INTR 0xFF00
1474
1475#define ADV_CTRL_REG_CMD_RESET 0x00C6
1476#define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
1477#define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
1478#define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
1479#define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
1480
1481#define ADV_TICKLE_NOP 0x00
1482#define ADV_TICKLE_A 0x01
1483#define ADV_TICKLE_B 0x02
1484#define ADV_TICKLE_C 0x03
1485
1da177e4
LT		 1486#define AdvIsIntPending(port) \
1487 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
1488
1489/*
1490 * SCSI_CFG0 Register bit definitions
1491 */
27c868c2
MW		 1492#define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
1493#define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
1494#define EVEN_PARITY 0x1000 /* Select Even Parity */
1495#define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
1496#define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
1497#define PRIM_MODE 0x0100 /* Primitive SCSI mode */
1498#define SCAM_EN 0x0080 /* Enable SCAM selection */
1499#define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
1500#define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
1501#define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
1502#define OUR_ID 0x000F /* SCSI ID */
1da177e4
LT		 1503
1504/*
1505 * SCSI_CFG1 Register bit definitions
1506 */
27c868c2
MW		 1507#define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
1508#define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
1509#define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
1510#define FILTER_SEL 0x0C00 /* Filter Period Selection */
1511#define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
1512#define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
1513#define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
1514#define ACTIVE_DBL 0x0200 /* Disable Active Negation */
1515#define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
1516#define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
1517#define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
1518#define TERM_CTL 0x0030 /* External SCSI Termination Bits */
1519#define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
1520#define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
1521#define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
1da177e4
LT		 1522
1523/*
1524 * Addendum for ASC-38C0800 Chip
1525 *
1526 * The ASC-38C1600 Chip uses the same definitions except that the
1527 * bus mode override bits [12:10] have been moved to byte register
1528 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
1529 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
1530 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
1531 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
1532 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
1533 */
27c868c2
MW		 1534#define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
1535#define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
1536#define HVD 0x1000 /* HVD Device Detect */
1537#define LVD 0x0800 /* LVD Device Detect */
1538#define SE 0x0400 /* SE Device Detect */
1539#define TERM_LVD 0x00C0 /* LVD Termination Bits */
1540#define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
1541#define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
1542#define TERM_SE 0x0030 /* SE Termination Bits */
1543#define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
1544#define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
1545#define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
1546#define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
1547#define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
1548#define C_DET_SE 0x0003 /* SE Cable Detect Bits */
1549#define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
1550#define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
1da177e4
LT		 1551
1552#define CABLE_ILLEGAL_A 0x7
1553 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
1554
1555#define CABLE_ILLEGAL_B 0xB
1556 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
1557
1558/*
1559 * MEM_CFG Register bit definitions
1560 */
27c868c2
MW		 1561#define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
1562#define FAST_EE_CLK 0x20 /* Diagnostic Bit */
1563#define RAM_SZ 0x1C /* Specify size of RAM to RISC */
1564#define RAM_SZ_2KB 0x00 /* 2 KB */
1565#define RAM_SZ_4KB 0x04 /* 4 KB */
1566#define RAM_SZ_8KB 0x08 /* 8 KB */
1567#define RAM_SZ_16KB 0x0C /* 16 KB */
1568#define RAM_SZ_32KB 0x10 /* 32 KB */
1569#define RAM_SZ_64KB 0x14 /* 64 KB */
1da177e4
LT		 1570
1571/*
1572 * DMA_CFG0 Register bit definitions
1573 *
1574 * This register is only accessible to the host.
1575 */
27c868c2
MW		 1576#define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
1577#define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
1578#define FIFO_THRESH_16B 0x00 /* 16 bytes */
1579#define FIFO_THRESH_32B 0x20 /* 32 bytes */
1580#define FIFO_THRESH_48B 0x30 /* 48 bytes */
1581#define FIFO_THRESH_64B 0x40 /* 64 bytes */
1582#define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
1583#define FIFO_THRESH_96B 0x60 /* 96 bytes */
1584#define FIFO_THRESH_112B 0x70 /* 112 bytes */
1585#define START_CTL 0x0C /* DMA start conditions */
1586#define START_CTL_TH 0x00 /* Wait threshold level (default) */
1587#define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
1588#define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
1589#define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
1590#define READ_CMD 0x03 /* Memory Read Method */
1591#define READ_CMD_MR 0x00 /* Memory Read */
1592#define READ_CMD_MRL 0x02 /* Memory Read Long */
1593#define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
1da177e4
LT		 1594
1595/*
1596 * ASC-38C0800 RAM BIST Register bit definitions
1597 */
1598#define RAM_TEST_MODE 0x80
1599#define PRE_TEST_MODE 0x40
1600#define NORMAL_MODE 0x00
1601#define RAM_TEST_DONE 0x10
1602#define RAM_TEST_STATUS 0x0F
1603#define RAM_TEST_HOST_ERROR 0x08
1604#define RAM_TEST_INTRAM_ERROR 0x04
1605#define RAM_TEST_RISC_ERROR 0x02
1606#define RAM_TEST_SCSI_ERROR 0x01
1607#define RAM_TEST_SUCCESS 0x00
1608#define PRE_TEST_VALUE 0x05
1609#define NORMAL_VALUE 0x00
1610
1611/*
1612 * ASC38C1600 Definitions
1613 *
1614 * IOPB_PCI_INT_CFG Bit Field Definitions
1615 */
1616
27c868c2 1617#define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
1da177e4
LT		 1618
1619/*
1620 * Bit 1 can be set to change the interrupt for the Function to operate in
1621 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
1622 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
1623 * mode, otherwise the operating mode is undefined.
1624 */
1625#define TOTEMPOLE 0x02
1626
1627/*
1628 * Bit 0 can be used to change the Int Pin for the Function. The value is
1629 * 0 by default for both Functions with Function 0 using INT A and Function
1630 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
1631 * INT A is used.
1632 *
1633 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
1634 * value specified in the PCI Configuration Space.
1635 */
1636#define INTAB 0x01
1637
1da177e4
LT		 1638/*
1639 * Adv Library Status Definitions
1640 */
1641#define ADV_TRUE 1
1642#define ADV_FALSE 0
1da177e4
LT		 1643#define ADV_SUCCESS 1
1644#define ADV_BUSY 0
1645#define ADV_ERROR (-1)
1646
1da177e4
LT		 1647/*
1648 * ADV_DVC_VAR 'warn_code' values
1649 */
27c868c2
MW		 1650#define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
1651#define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
1652#define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
27c868c2 1653#define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
1da177e4 1654
27c868c2
MW		 1655#define ADV_MAX_TID 15 /* max. target identifier */
1656#define ADV_MAX_LUN 7 /* max. logical unit number */
1da177e4 1657
1da177e4
LT		 1658/*
1659 * Fixed locations of microcode operating variables.
1660 */
27c868c2
MW		 1661#define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
1662#define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
1663#define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
1664#define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
1665#define ASC_MC_VERSION_NUM 0x003A /* microcode number */
1666#define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
1667#define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
1668#define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
1669#define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
1670#define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
1671#define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
1672#define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
1673#define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
1da177e4
LT		 1674#define ASC_MC_CHIP_TYPE 0x009A
1675#define ASC_MC_INTRB_CODE 0x009B
1676#define ASC_MC_WDTR_ABLE 0x009C
1677#define ASC_MC_SDTR_ABLE 0x009E
1678#define ASC_MC_TAGQNG_ABLE 0x00A0
1679#define ASC_MC_DISC_ENABLE 0x00A2
1680#define ASC_MC_IDLE_CMD_STATUS 0x00A4
1681#define ASC_MC_IDLE_CMD 0x00A6
1682#define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
1683#define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
1684#define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
1685#define ASC_MC_DEFAULT_MEM_CFG 0x00B0
1686#define ASC_MC_DEFAULT_SEL_MASK 0x00B2
1687#define ASC_MC_SDTR_DONE 0x00B6
1688#define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
1689#define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
1690#define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
27c868c2 1691#define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
1da177e4 1692#define ASC_MC_WDTR_DONE 0x0124
27c868c2 1693#define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
1da177e4
LT		 1694#define ASC_MC_ICQ 0x0160
1695#define ASC_MC_IRQ 0x0164
1696#define ASC_MC_PPR_ABLE 0x017A
1697
1698/*
1699 * BIOS LRAM variable absolute offsets.
1700 */
1701#define BIOS_CODESEG 0x54
1702#define BIOS_CODELEN 0x56
1703#define BIOS_SIGNATURE 0x58
1704#define BIOS_VERSION 0x5A
1705
1706/*
1707 * Microcode Control Flags
1708 *
1709 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
1710 * and handled by the microcode.
1711 */
27c868c2
MW		 1712#define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
1713#define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
1da177e4
LT		 1714
1715/*
1716 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
1717 */
1718#define HSHK_CFG_WIDE_XFR 0x8000
1719#define HSHK_CFG_RATE 0x0F00
1720#define HSHK_CFG_OFFSET 0x001F
1721
27c868c2
MW		 1722#define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
1723#define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
1724#define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
1725#define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
1726
1727#define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
1728#define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
1729#define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
1730#define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
1731#define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
1732
1733#define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
1734#define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
1735#define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
1736#define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
1737#define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
1da177e4
LT		 1738/*
1739 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
1740 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
1741 */
27c868c2
MW		 1742#define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
1743#define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
1da177e4
LT		 1744
1745/*
1746 * All fields here are accessed by the board microcode and need to be
1747 * little-endian.
1748 */
27c868c2
MW		 1749typedef struct adv_carr_t {
1750 ADV_VADDR carr_va; /* Carrier Virtual Address */
1751 ADV_PADDR carr_pa; /* Carrier Physical Address */
1752 ADV_VADDR areq_vpa; /* ASC_SCSI_REQ_Q Virtual or Physical Address */
1753 /*
1754 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer
1755 *
1756 * next_vpa [3:1] Reserved Bits
1757 * next_vpa [0] Done Flag set in Response Queue.
1758 */
1759 ADV_VADDR next_vpa;
1da177e4
LT		 1760} ADV_CARR_T;
1761
1762/*
1763 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
1764 */
1765#define ASC_NEXT_VPA_MASK 0xFFFFFFF0
1766
1767#define ASC_RQ_DONE 0x00000001
1768#define ASC_RQ_GOOD 0x00000002
1769#define ASC_CQ_STOPPER 0x00000000
1770
1771#define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
1772
1773#define ADV_CARRIER_NUM_PAGE_CROSSING \
fd625f47 1774 (((ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) + (PAGE_SIZE - 1))/PAGE_SIZE)
1da177e4
LT		 1775
1776#define ADV_CARRIER_BUFSIZE \
1777 ((ADV_CARRIER_COUNT + ADV_CARRIER_NUM_PAGE_CROSSING) * sizeof(ADV_CARR_T))
1778
1779/*
1780 * ASC_SCSI_REQ_Q 'a_flag' definitions
1781 *
1782 * The Adv Library should limit use to the lower nibble (4 bits) of
1783 * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
1784 */
27c868c2
MW		 1785#define ADV_POLL_REQUEST 0x01 /* poll for request completion */
1786#define ADV_SCSIQ_DONE 0x02 /* request done */
1787#define ADV_DONT_RETRY 0x08 /* don't do retry */
1da177e4 1788
27c868c2
MW		 1789#define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
1790#define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
1791#define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
1da177e4
LT		 1792
1793/*
1794 * Adapter temporary configuration structure
1795 *
1796 * This structure can be discarded after initialization. Don't add
1797 * fields here needed after initialization.
1798 *
1799 * Field naming convention:
1800 *
1801 * *_enable indicates the field enables or disables a feature. The
1802 * value of the field is never reset.
1803 */
1804typedef struct adv_dvc_cfg {
27c868c2
MW		 1805 ushort disc_enable; /* enable disconnection */
1806 uchar chip_version; /* chip version */
1807 uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
27c868c2
MW		 1808 ushort control_flag; /* Microcode Control Flag */
1809 ushort mcode_date; /* Microcode date */
1810 ushort mcode_version; /* Microcode version */
27c868c2
MW		 1811 ushort serial1; /* EEPROM serial number word 1 */
1812 ushort serial2; /* EEPROM serial number word 2 */
1813 ushort serial3; /* EEPROM serial number word 3 */
1da177e4
LT		 1814} ADV_DVC_CFG;
1815
1816struct adv_dvc_var;
1817struct adv_scsi_req_q;
1818
1da177e4 1819typedef struct asc_sg_block {
27c868c2
MW		 1820 uchar reserved1;
1821 uchar reserved2;
1822 uchar reserved3;
1823 uchar sg_cnt; /* Valid entries in block. */
1824 ADV_PADDR sg_ptr; /* Pointer to next sg block. */
1825 struct {
1826 ADV_PADDR sg_addr; /* SG element address. */
1827 ADV_DCNT sg_count; /* SG element count. */
1828 } sg_list[NO_OF_SG_PER_BLOCK];
1da177e4
LT		 1829} ADV_SG_BLOCK;
1830
1831/*
1832 * ADV_SCSI_REQ_Q - microcode request structure
1833 *
1834 * All fields in this structure up to byte 60 are used by the microcode.
1835 * The microcode makes assumptions about the size and ordering of fields
1836 * in this structure. Do not change the structure definition here without
1837 * coordinating the change with the microcode.
1838 *
1839 * All fields accessed by microcode must be maintained in little_endian
1840 * order.
1841 */
1842typedef struct adv_scsi_req_q {
27c868c2
MW		 1843 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
1844 uchar target_cmd;
1845 uchar target_id; /* Device target identifier. */
1846 uchar target_lun; /* Device target logical unit number. */
1847 ADV_PADDR data_addr; /* Data buffer physical address. */
1848 ADV_DCNT data_cnt; /* Data count. Ucode sets to residual. */
1849 ADV_PADDR sense_addr;
1850 ADV_PADDR carr_pa;
1851 uchar mflag;
1852 uchar sense_len;
1853 uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
1854 uchar scsi_cntl;
1855 uchar done_status; /* Completion status. */
1856 uchar scsi_status; /* SCSI status byte. */
1857 uchar host_status; /* Ucode host status. */
1858 uchar sg_working_ix;
1859 uchar cdb[12]; /* SCSI CDB bytes 0-11. */
1860 ADV_PADDR sg_real_addr; /* SG list physical address. */
1861 ADV_PADDR scsiq_rptr;
1862 uchar cdb16[4]; /* SCSI CDB bytes 12-15. */
1863 ADV_VADDR scsiq_ptr;
1864 ADV_VADDR carr_va;
1865 /*
1866 * End of microcode structure - 60 bytes. The rest of the structure
1867 * is used by the Adv Library and ignored by the microcode.
1868 */
1869 ADV_VADDR srb_ptr;
1870 ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
1871 char *vdata_addr; /* Data buffer virtual address. */
1872 uchar a_flag;
1873 uchar pad[2]; /* Pad out to a word boundary. */
1da177e4
LT		 1874} ADV_SCSI_REQ_Q;
1875
98d41c29
MW		 1876/*
1877 * The following two structures are used to process Wide Board requests.
1878 *
1879 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
1880 * and microcode with the ADV_SCSI_REQ_Q field 'srb_ptr' pointing to the
1881 * adv_req_t. The adv_req_t structure 'cmndp' field in turn points to the
1882 * Mid-Level SCSI request structure.
1883 *
1884 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
1885 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
1886 * up to 255 scatter-gather elements may be used per request or
1887 * ADV_SCSI_REQ_Q.
1888 *
1889 * Both structures must be 32 byte aligned.
1890 */
1891typedef struct adv_sgblk {
1892 ADV_SG_BLOCK sg_block; /* Sgblock structure. */
1893 uchar align[32]; /* Sgblock structure padding. */
1894 struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */
1895} adv_sgblk_t;
1896
1897typedef struct adv_req {
1898 ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */
1899 uchar align[32]; /* Request structure padding. */
1900 struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */
1901 adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */
1902 struct adv_req *next_reqp; /* Next Request Structure. */
1903} adv_req_t;
1904
1905/*
1906 * Adapter operation variable structure.
1907 *
1908 * One structure is required per host adapter.
1909 *
1910 * Field naming convention:
1911 *
1912 * *_able indicates both whether a feature should be enabled or disabled
1913 * and whether a device isi capable of the feature. At initialization
1914 * this field may be set, but later if a device is found to be incapable
1915 * of the feature, the field is cleared.
1916 */
1917typedef struct adv_dvc_var {
1918 AdvPortAddr iop_base; /* I/O port address */
1919 ushort err_code; /* fatal error code */
1920 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
1921 ushort wdtr_able; /* try WDTR for a device */
1922 ushort sdtr_able; /* try SDTR for a device */
1923 ushort ultra_able; /* try SDTR Ultra speed for a device */
1924 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
1925 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
1926 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
1927 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
1928 ushort tagqng_able; /* try tagged queuing with a device */
1929 ushort ppr_able; /* PPR message capable per TID bitmask. */
1930 uchar max_dvc_qng; /* maximum number of tagged commands per device */
1931 ushort start_motor; /* start motor command allowed */
1932 uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */
1933 uchar chip_no; /* should be assigned by caller */
1934 uchar max_host_qng; /* maximum number of Q'ed command allowed */
1935 ushort no_scam; /* scam_tolerant of EEPROM */
1936 struct asc_board *drv_ptr; /* driver pointer to private structure */
1937 uchar chip_scsi_id; /* chip SCSI target ID */
1938 uchar chip_type;
1939 uchar bist_err_code;
1940 ADV_CARR_T *carrier_buf;
1941 ADV_CARR_T *carr_freelist; /* Carrier free list. */
1942 ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */
1943 ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */
1944 ushort carr_pending_cnt; /* Count of pending carriers. */
1945 struct adv_req *orig_reqp; /* adv_req_t memory block. */
1946 /*
1947 * Note: The following fields will not be used after initialization. The
1948 * driver may discard the buffer after initialization is done.
1949 */
1950 ADV_DVC_CFG *cfg; /* temporary configuration structure */
1951} ADV_DVC_VAR;
1952
1da177e4
LT		 1953/*
1954 * Microcode idle loop commands
1955 */
1956#define IDLE_CMD_COMPLETED 0
1957#define IDLE_CMD_STOP_CHIP 0x0001
1958#define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
1959#define IDLE_CMD_SEND_INT 0x0004
1960#define IDLE_CMD_ABORT 0x0008
1961#define IDLE_CMD_DEVICE_RESET 0x0010
27c868c2
MW		 1962#define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
1963#define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
1da177e4
LT		 1964#define IDLE_CMD_SCSIREQ 0x0080
1965
1966#define IDLE_CMD_STATUS_SUCCESS 0x0001
1967#define IDLE_CMD_STATUS_FAILURE 0x0002
1968
1969/*
1970 * AdvSendIdleCmd() flag definitions.
1971 */
1972#define ADV_NOWAIT 0x01
1973
1974/*
1975 * Wait loop time out values.
1976 */
27c868c2
MW		 1977#define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
1978#define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
27c868c2 1979#define SCSI_MAX_RETRY 10 /* retry count */
1da177e4 1980
27c868c2
MW		 1981#define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
1982#define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
1983#define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
1984#define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
1da177e4 1985
27c868c2 1986#define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
1da177e4 1987
1da177e4
LT		 1988/* Read byte from a register. */
1989#define AdvReadByteRegister(iop_base, reg_off) \
1990 (ADV_MEM_READB((iop_base) + (reg_off)))
1991
1992/* Write byte to a register. */
1993#define AdvWriteByteRegister(iop_base, reg_off, byte) \
1994 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
1995
1996/* Read word (2 bytes) from a register. */
1997#define AdvReadWordRegister(iop_base, reg_off) \
1998 (ADV_MEM_READW((iop_base) + (reg_off)))
1999
2000/* Write word (2 bytes) to a register. */
2001#define AdvWriteWordRegister(iop_base, reg_off, word) \
2002 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
2003
2004/* Write dword (4 bytes) to a register. */
2005#define AdvWriteDWordRegister(iop_base, reg_off, dword) \
2006 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
2007
2008/* Read byte from LRAM. */
2009#define AdvReadByteLram(iop_base, addr, byte) \
2010do { \
2011 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2012 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
2013} while (0)
2014
2015/* Write byte to LRAM. */
2016#define AdvWriteByteLram(iop_base, addr, byte) \
2017 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2018 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
2019
2020/* Read word (2 bytes) from LRAM. */
2021#define AdvReadWordLram(iop_base, addr, word) \
2022do { \
2023 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2024 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
2025} while (0)
2026
2027/* Write word (2 bytes) to LRAM. */
2028#define AdvWriteWordLram(iop_base, addr, word) \
2029 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2030 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2031
2032/* Write little-endian double word (4 bytes) to LRAM */
2033/* Because of unspecified C language ordering don't use auto-increment. */
2034#define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
2035 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2036 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2037 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
2038 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
2039 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2040 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
2041
2042/* Read word (2 bytes) from LRAM assuming that the address is already set. */
2043#define AdvReadWordAutoIncLram(iop_base) \
2044 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
2045
2046/* Write word (2 bytes) to LRAM assuming that the address is already set. */
2047#define AdvWriteWordAutoIncLram(iop_base, word) \
2048 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2049
1da177e4
LT		 2050/*
2051 * Define macro to check for Condor signature.
2052 *
2053 * Evaluate to ADV_TRUE if a Condor chip is found the specified port
2054 * address 'iop_base'. Otherwise evalue to ADV_FALSE.
2055 */
2056#define AdvFindSignature(iop_base) \
2057 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
2058 ADV_CHIP_ID_BYTE) && \
2059 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
2060 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
2061
2062/*
2063 * Define macro to Return the version number of the chip at 'iop_base'.
2064 *
2065 * The second parameter 'bus_type' is currently unused.
2066 */
2067#define AdvGetChipVersion(iop_base, bus_type) \
2068 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
2069
2070/*
2071 * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must
2072 * match the ASC_SCSI_REQ_Q 'srb_ptr' field.
2073 *
2074 * If the request has not yet been sent to the device it will simply be
2075 * aborted from RISC memory. If the request is disconnected it will be
2076 * aborted on reselection by sending an Abort Message to the target ID.
2077 *
2078 * Return value:
2079 * ADV_TRUE(1) - Queue was successfully aborted.
2080 * ADV_FALSE(0) - Queue was not found on the active queue list.
2081 */
2082#define AdvAbortQueue(asc_dvc, scsiq) \
2083 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
2084 (ADV_DCNT) (scsiq))
2085
2086/*
2087 * Send a Bus Device Reset Message to the specified target ID.
2088 *
2089 * All outstanding commands will be purged if sending the
2090 * Bus Device Reset Message is successful.
2091 *
2092 * Return Value:
2093 * ADV_TRUE(1) - All requests on the target are purged.
2094 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
2095 * are not purged.
2096 */
2097#define AdvResetDevice(asc_dvc, target_id) \
2098 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
2099 (ADV_DCNT) (target_id))
2100
2101/*
2102 * SCSI Wide Type definition.
2103 */
2104#define ADV_SCSI_BIT_ID_TYPE ushort
2105
2106/*
2107 * AdvInitScsiTarget() 'cntl_flag' options.
2108 */
2109#define ADV_SCAN_LUN 0x01
2110#define ADV_CAPINFO_NOLUN 0x02
2111
2112/*
2113 * Convert target id to target id bit mask.
2114 */
2115#define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
2116
2117/*
2118 * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
2119 */
2120
27c868c2 2121#define QD_NO_STATUS 0x00 /* Request not completed yet. */
1da177e4
LT		 2122#define QD_NO_ERROR 0x01
2123#define QD_ABORTED_BY_HOST 0x02
2124#define QD_WITH_ERROR 0x04
2125
2126#define QHSTA_NO_ERROR 0x00
2127#define QHSTA_M_SEL_TIMEOUT 0x11
2128#define QHSTA_M_DATA_OVER_RUN 0x12
2129#define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
2130#define QHSTA_M_QUEUE_ABORTED 0x15
27c868c2
MW		 2131#define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
2132#define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
2133#define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
2134#define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
2135#define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
2136#define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
2137#define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
1da177e4 2138/* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
27c868c2
MW		 2139#define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
2140#define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
2141#define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
2142#define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
2143#define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
2144#define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
2145#define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
2146#define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
1da177e4
LT		 2147#define QHSTA_M_WTM_TIMEOUT 0x41
2148#define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
2149#define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
2150#define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
27c868c2
MW		 2151#define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
2152#define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
2153#define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
1da177e4 2154
1da177e4
LT		 2155/* Return the address that is aligned at the next doubleword >= to 'addr'. */
2156#define ADV_8BALIGN(addr) (((ulong) (addr) + 0x7) & ~0x7)
2157#define ADV_16BALIGN(addr) (((ulong) (addr) + 0xF) & ~0xF)
2158#define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F)
2159
2160/*
2161 * Total contiguous memory needed for driver SG blocks.
2162 *
2163 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
2164 * number of scatter-gather elements the driver supports in a
2165 * single request.
2166 */
2167
2168#define ADV_SG_LIST_MAX_BYTE_SIZE \
2169 (sizeof(ADV_SG_BLOCK) * \
2170 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
2171
d2411495 2172/* struct asc_board flags */
27c868c2 2173#define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */
1da177e4
LT		 2174
2175#define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
1da177e4 2176
27c868c2 2177#define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */
1da177e4 2178
27c868c2 2179#define ASC_INFO_SIZE 128 /* advansys_info() line size */
1da177e4 2180
1da177e4
LT		 2181/* Asc Library return codes */
2182#define ASC_TRUE 1
2183#define ASC_FALSE 0
2184#define ASC_NOERROR 1
2185#define ASC_BUSY 0
2186#define ASC_ERROR (-1)
2187
2188/* struct scsi_cmnd function return codes */
2189#define STATUS_BYTE(byte) (byte)
2190#define MSG_BYTE(byte) ((byte) << 8)
2191#define HOST_BYTE(byte) ((byte) << 16)
2192#define DRIVER_BYTE(byte) ((byte) << 24)
2193
d2411495 2194#define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1)
1da177e4 2195#ifndef ADVANSYS_STATS
27c868c2 2196#define ASC_STATS_ADD(shost, counter, count)
1da177e4 2197#else /* ADVANSYS_STATS */
27c868c2 2198#define ASC_STATS_ADD(shost, counter, count) \
d2411495 2199 (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count))
1da177e4
LT		 2200#endif /* ADVANSYS_STATS */
2201
1da177e4
LT		 2202/* If the result wraps when calculating tenths, return 0. */
2203#define ASC_TENTHS(num, den) \
2204 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
2205 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
2206
2207/*
2208 * Display a message to the console.
2209 */
2210#define ASC_PRINT(s) \
2211 { \
2212 printk("advansys: "); \
2213 printk(s); \
2214 }
2215
2216#define ASC_PRINT1(s, a1) \
2217 { \
2218 printk("advansys: "); \
2219 printk((s), (a1)); \
2220 }
2221
2222#define ASC_PRINT2(s, a1, a2) \
2223 { \
2224 printk("advansys: "); \
2225 printk((s), (a1), (a2)); \
2226 }
2227
2228#define ASC_PRINT3(s, a1, a2, a3) \
2229 { \
2230 printk("advansys: "); \
2231 printk((s), (a1), (a2), (a3)); \
2232 }
2233
2234#define ASC_PRINT4(s, a1, a2, a3, a4) \
2235 { \
2236 printk("advansys: "); \
2237 printk((s), (a1), (a2), (a3), (a4)); \
2238 }
2239
1da177e4
LT		 2240#ifndef ADVANSYS_DEBUG
2241
b352f923 2242#define ASC_DBG(lvl, s...)
1da177e4 2243#define ASC_DBG_PRT_SCSI_HOST(lvl, s)
1da177e4
LT		 2244#define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
2245#define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2246#define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
2247#define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2248#define ASC_DBG_PRT_HEX(lvl, name, start, length)
2249#define ASC_DBG_PRT_CDB(lvl, cdb, len)
2250#define ASC_DBG_PRT_SENSE(lvl, sense, len)
2251#define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
2252
2253#else /* ADVANSYS_DEBUG */
2254
2255/*
2256 * Debugging Message Levels:
2257 * 0: Errors Only
2258 * 1: High-Level Tracing
2259 * 2-N: Verbose Tracing
2260 */
2261
b352f923
MW		 2262#define ASC_DBG(lvl, format, arg...) { \
2263 if (asc_dbglvl >= (lvl)) \
2264 printk(KERN_DEBUG "%s: %s: " format, DRV_NAME, \
cadbd4a5 2265 __func__ , ## arg); \
b352f923 2266}
1da177e4
LT		 2267
2268#define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
2269 { \
2270 if (asc_dbglvl >= (lvl)) { \
2271 asc_prt_scsi_host(s); \
2272 } \
2273 }
2274
1da177e4
LT		 2275#define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
2276 { \
2277 if (asc_dbglvl >= (lvl)) { \
2278 asc_prt_asc_scsi_q(scsiqp); \
2279 } \
2280 }
2281
2282#define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
2283 { \
2284 if (asc_dbglvl >= (lvl)) { \
2285 asc_prt_asc_qdone_info(qdone); \
2286 } \
2287 }
2288
2289#define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
2290 { \
2291 if (asc_dbglvl >= (lvl)) { \
2292 asc_prt_adv_scsi_req_q(scsiqp); \
2293 } \
2294 }
2295
2296#define ASC_DBG_PRT_HEX(lvl, name, start, length) \
2297 { \
2298 if (asc_dbglvl >= (lvl)) { \
2299 asc_prt_hex((name), (start), (length)); \
2300 } \
2301 }
2302
2303#define ASC_DBG_PRT_CDB(lvl, cdb, len) \
2304 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
2305
2306#define ASC_DBG_PRT_SENSE(lvl, sense, len) \
2307 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
2308
2309#define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
2310 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
2311#endif /* ADVANSYS_DEBUG */
2312
1da177e4
LT		 2313#ifdef ADVANSYS_STATS
2314
2315/* Per board statistics structure */
2316struct asc_stats {
27c868c2
MW		 2317 /* Driver Entrypoint Statistics */
2318 ADV_DCNT queuecommand; /* # calls to advansys_queuecommand() */
2319 ADV_DCNT reset; /* # calls to advansys_eh_bus_reset() */
2320 ADV_DCNT biosparam; /* # calls to advansys_biosparam() */
2321 ADV_DCNT interrupt; /* # advansys_interrupt() calls */
2322 ADV_DCNT callback; /* # calls to asc/adv_isr_callback() */
2323 ADV_DCNT done; /* # calls to request's scsi_done function */
2324 ADV_DCNT build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
2325 ADV_DCNT adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
2326 ADV_DCNT adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
2327 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
2328 ADV_DCNT exe_noerror; /* # ASC_NOERROR returns. */
2329 ADV_DCNT exe_busy; /* # ASC_BUSY returns. */
2330 ADV_DCNT exe_error; /* # ASC_ERROR returns. */
2331 ADV_DCNT exe_unknown; /* # unknown returns. */
2332 /* Data Transfer Statistics */
52c334e9
MW		 2333 ADV_DCNT xfer_cnt; /* # I/O requests received */
2334 ADV_DCNT xfer_elem; /* # scatter-gather elements */
2335 ADV_DCNT xfer_sect; /* # 512-byte blocks */
1da177e4
LT		 2336};
2337#endif /* ADVANSYS_STATS */
2338
1da177e4
LT		 2339/*
2340 * Structure allocated for each board.
2341 *
8dfb5379 2342 * This structure is allocated by scsi_host_alloc() at the end
1da177e4
LT		 2343 * of the 'Scsi_Host' structure starting at the 'hostdata'
2344 * field. It is guaranteed to be allocated from DMA-able memory.
2345 */
d2411495 2346struct asc_board {
394dbf3f 2347 struct device *dev;
27c868c2 2348 uint flags; /* Board flags */
d361db48 2349 unsigned int irq;
27c868c2
MW		 2350 union {
2351 ASC_DVC_VAR asc_dvc_var; /* Narrow board */
2352 ADV_DVC_VAR adv_dvc_var; /* Wide board */
2353 } dvc_var;
2354 union {
2355 ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */
2356 ADV_DVC_CFG adv_dvc_cfg; /* Wide board */
2357 } dvc_cfg;
2358 ushort asc_n_io_port; /* Number I/O ports. */
27c868c2 2359 ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */
27c868c2
MW		 2360 ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
2361 ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */
2362 ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
2363 union {
2364 ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */
2365 ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */
2366 ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */
2367 ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */
2368 } eep_config;
2369 ulong last_reset; /* Saved last reset time */
27c868c2 2370 /* /proc/scsi/advansys/[0...] */
1da177e4 2371#ifdef ADVANSYS_STATS
27c868c2
MW		 2372 struct asc_stats asc_stats; /* Board statistics */
2373#endif /* ADVANSYS_STATS */
2374 /*
2375 * The following fields are used only for Narrow Boards.
2376 */
27c868c2
MW		 2377 uchar sdtr_data[ASC_MAX_TID + 1]; /* SDTR information */
2378 /*
2379 * The following fields are used only for Wide Boards.
2380 */
2381 void __iomem *ioremap_addr; /* I/O Memory remap address. */
2382 ushort ioport; /* I/O Port address. */
27c868c2
MW		 2383 adv_req_t *adv_reqp; /* Request structures. */
2384 adv_sgblk_t *adv_sgblkp; /* Scatter-gather structures. */
2385 ushort bios_signature; /* BIOS Signature. */
2386 ushort bios_version; /* BIOS Version. */
2387 ushort bios_codeseg; /* BIOS Code Segment. */
2388 ushort bios_codelen; /* BIOS Code Segment Length. */
d2411495 2389};
1da177e4 2390
d10fb2c7
MW		 2391#define asc_dvc_to_board(asc_dvc) container_of(asc_dvc, struct asc_board, \
2392 dvc_var.asc_dvc_var)
13ac2d9c
MW		 2393#define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
2394 dvc_var.adv_dvc_var)
2395#define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
2396
1da177e4 2397#ifdef ADVANSYS_DEBUG
27c868c2 2398static int asc_dbglvl = 3;
1da177e4 2399
1da177e4 2400/*
51219358 2401 * asc_prt_asc_dvc_var()
1da177e4 2402 */
51219358 2403static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
1da177e4 2404{
51219358 2405 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
27c868c2 2406
51219358
MW		 2407 printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
2408 "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
2409
2410 printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
2411 (unsigned)h->init_sdtr);
2412
2413 printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
2414 "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
2415 (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
2416 (unsigned)h->chip_no);
2417
2418 printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
2419 "%u,\n", (unsigned)h->queue_full_or_busy,
2420 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2421
2422 printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
2423 "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
2424 (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
2425 (unsigned)h->in_critical_cnt);
2426
2427 printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
2428 "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
2429 (unsigned)h->init_state, (unsigned)h->no_scam,
2430 (unsigned)h->pci_fix_asyn_xfer);
2431
d361db48 2432 printk(" cfg 0x%lx\n", (ulong)h->cfg);
1da177e4
LT		 2433}
2434
51219358
MW		 2435/*
2436 * asc_prt_asc_dvc_cfg()
2437 */
2438static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
6ed1ef07 2439{
51219358 2440 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
6ed1ef07 2441
51219358
MW		 2442 printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
2443 h->can_tagged_qng, h->cmd_qng_enabled);
2444 printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
2445 h->disc_enable, h->sdtr_enable);
6ed1ef07 2446
b08fc565
MW		 2447 printk(" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, "
2448 "chip_version %d,\n", h->chip_scsi_id, h->isa_dma_speed,
2449 h->isa_dma_channel, h->chip_version);
51219358 2450
d10fb2c7
MW		 2451 printk(" mcode_date 0x%x, mcode_version %d\n",
2452 h->mcode_date, h->mcode_version);
6ed1ef07
MW		 2453}
2454
1da177e4 2455/*
51219358 2456 * asc_prt_adv_dvc_var()
1da177e4 2457 *
51219358 2458 * Display an ADV_DVC_VAR structure.
1da177e4 2459 */
51219358 2460static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
1da177e4 2461{
51219358 2462 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
27c868c2 2463
51219358
MW		 2464 printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
2465 (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
1da177e4 2466
b352f923
MW		 2467 printk(" sdtr_able 0x%x, wdtr_able 0x%x\n",
2468 (unsigned)h->sdtr_able, (unsigned)h->wdtr_able);
1da177e4 2469
d361db48
MW		 2470 printk(" start_motor 0x%x, scsi_reset_wait 0x%x\n",
2471 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
1da177e4 2472
51219358
MW		 2473 printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%lxn\n",
2474 (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
2475 (ulong)h->carr_freelist);
1da177e4 2476
51219358
MW		 2477 printk(" icq_sp 0x%lx, irq_sp 0x%lx\n",
2478 (ulong)h->icq_sp, (ulong)h->irq_sp);
1da177e4 2479
51219358
MW		 2480 printk(" no_scam 0x%x, tagqng_able 0x%x\n",
2481 (unsigned)h->no_scam, (unsigned)h->tagqng_able);
1da177e4 2482
51219358
MW		 2483 printk(" chip_scsi_id 0x%x, cfg 0x%lx\n",
2484 (unsigned)h->chip_scsi_id, (ulong)h->cfg);
2485}
1da177e4 2486
51219358
MW		 2487/*
2488 * asc_prt_adv_dvc_cfg()
2489 *
2490 * Display an ADV_DVC_CFG structure.
2491 */
2492static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
2493{
2494 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
27c868c2 2495
51219358
MW		 2496 printk(" disc_enable 0x%x, termination 0x%x\n",
2497 h->disc_enable, h->termination);
1da177e4 2498
51219358
MW		 2499 printk(" chip_version 0x%x, mcode_date 0x%x\n",
2500 h->chip_version, h->mcode_date);
27c868c2 2501
b352f923
MW		 2502 printk(" mcode_version 0x%x, control_flag 0x%x\n",
2503 h->mcode_version, h->control_flag);
1da177e4
LT		 2504}
2505
2506/*
b352f923 2507 * asc_prt_scsi_host()
1da177e4 2508 */
b352f923 2509static void asc_prt_scsi_host(struct Scsi_Host *s)
1da177e4 2510{
b352f923 2511 struct asc_board *boardp = shost_priv(s);
51219358 2512
71610f55 2513 printk("Scsi_Host at addr 0x%p, device %s\n", s, dev_name(boardp->dev));
50d14a70 2514 printk(" host_busy %u, host_no %d,\n",
74665016 2515 atomic_read(&s->host_busy), s->host_no);
51219358 2516
b352f923
MW		 2517 printk(" base 0x%lx, io_port 0x%lx, irq %d,\n",
2518 (ulong)s->base, (ulong)s->io_port, boardp->irq);
51219358 2519
b352f923
MW		 2520 printk(" dma_channel %d, this_id %d, can_queue %d,\n",
2521 s->dma_channel, s->this_id, s->can_queue);
1da177e4 2522
b352f923
MW		 2523 printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
2524 s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
27c868c2 2525
b352f923
MW		 2526 if (ASC_NARROW_BOARD(boardp)) {
2527 asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var);
2528 asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg);
2529 } else {
2530 asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var);
2531 asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg);
074c8fe4 2532 }
1da177e4
LT		 2533}
2534
51219358
MW		 2535/*
2536 * asc_prt_hex()
2537 *
2538 * Print hexadecimal output in 4 byte groupings 32 bytes
2539 * or 8 double-words per line.
2540 */
2541static void asc_prt_hex(char *f, uchar *s, int l)
47d853cc 2542{
51219358
MW		 2543 int i;
2544 int j;
2545 int k;
2546 int m;
47d853cc 2547
51219358
MW		 2548 printk("%s: (%d bytes)\n", f, l);
2549
2550 for (i = 0; i < l; i += 32) {
2551
2552 /* Display a maximum of 8 double-words per line. */
2553 if ((k = (l - i) / 4) >= 8) {
2554 k = 8;
2555 m = 0;
47d853cc 2556 } else {
51219358 2557 m = (l - i) % 4;
47d853cc
MW		 2558 }
2559
51219358
MW		 2560 for (j = 0; j < k; j++) {
2561 printk(" %2.2X%2.2X%2.2X%2.2X",
2562 (unsigned)s[i + (j * 4)],
2563 (unsigned)s[i + (j * 4) + 1],
2564 (unsigned)s[i + (j * 4) + 2],
2565 (unsigned)s[i + (j * 4) + 3]);
47d853cc 2566 }
47d853cc 2567
51219358
MW		 2568 switch (m) {
2569 case 0:
2570 default:
2571 break;
2572 case 1:
2573 printk(" %2.2X", (unsigned)s[i + (j * 4)]);
2574 break;
2575 case 2:
2576 printk(" %2.2X%2.2X",
2577 (unsigned)s[i + (j * 4)],
2578 (unsigned)s[i + (j * 4) + 1]);
2579 break;
2580 case 3:
2581 printk(" %2.2X%2.2X%2.2X",
2582 (unsigned)s[i + (j * 4) + 1],
2583 (unsigned)s[i + (j * 4) + 2],
2584 (unsigned)s[i + (j * 4) + 3]);
2585 break;
2586 }
47d853cc 2587
51219358 2588 printk("\n");
47d853cc
MW		 2589 }
2590}
b352f923
MW		 2591
2592/*
2593 * asc_prt_asc_scsi_q()
2594 */
2595static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
2596{
2597 ASC_SG_HEAD *sgp;
2598 int i;
2599
2600 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
2601
2602 printk
2603 (" target_ix 0x%x, target_lun %u, srb_ptr 0x%lx, tag_code 0x%x,\n",
2604 q->q2.target_ix, q->q1.target_lun, (ulong)q->q2.srb_ptr,
2605 q->q2.tag_code);
2606
2607 printk
2608 (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2609 (ulong)le32_to_cpu(q->q1.data_addr),
2610 (ulong)le32_to_cpu(q->q1.data_cnt),
2611 (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
2612
2613 printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
2614 (ulong)q->cdbptr, q->q2.cdb_len,
2615 (ulong)q->sg_head, q->q1.sg_queue_cnt);
2616
2617 if (q->sg_head) {
2618 sgp = q->sg_head;
2619 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
2620 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
2621 sgp->queue_cnt);
2622 for (i = 0; i < sgp->entry_cnt; i++) {
2623 printk(" [%u]: addr 0x%lx, bytes %lu\n",
2624 i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
2625 (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
2626 }
2627
2628 }
2629}
2630
2631/*
2632 * asc_prt_asc_qdone_info()
2633 */
2634static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
2635{
2636 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
2637 printk(" srb_ptr 0x%lx, target_ix %u, cdb_len %u, tag_code %u,\n",
2638 (ulong)q->d2.srb_ptr, q->d2.target_ix, q->d2.cdb_len,
2639 q->d2.tag_code);
2640 printk
2641 (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
2642 q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
2643}
2644
2645/*
2646 * asc_prt_adv_sgblock()
2647 *
2648 * Display an ADV_SG_BLOCK structure.
2649 */
2650static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
2651{
2652 int i;
2653
2654 printk(" ASC_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
2655 (ulong)b, sgblockno);
2656 printk(" sg_cnt %u, sg_ptr 0x%lx\n",
2657 b->sg_cnt, (ulong)le32_to_cpu(b->sg_ptr));
2658 BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
2659 if (b->sg_ptr != 0)
2660 BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
2661 for (i = 0; i < b->sg_cnt; i++) {
2662 printk(" [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
2663 i, (ulong)b->sg_list[i].sg_addr,
2664 (ulong)b->sg_list[i].sg_count);
2665 }
2666}
2667
2668/*
2669 * asc_prt_adv_scsi_req_q()
2670 *
2671 * Display an ADV_SCSI_REQ_Q structure.
2672 */
2673static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
2674{
2675 int sg_blk_cnt;
2676 struct asc_sg_block *sg_ptr;
2677
2678 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
2679
2680 printk(" target_id %u, target_lun %u, srb_ptr 0x%lx, a_flag 0x%x\n",
2681 q->target_id, q->target_lun, (ulong)q->srb_ptr, q->a_flag);
2682
2683 printk(" cntl 0x%x, data_addr 0x%lx, vdata_addr 0x%lx\n",
2684 q->cntl, (ulong)le32_to_cpu(q->data_addr), (ulong)q->vdata_addr);
2685
2686 printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2687 (ulong)le32_to_cpu(q->data_cnt),
2688 (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
2689
2690 printk
2691 (" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
2692 q->cdb_len, q->done_status, q->host_status, q->scsi_status);
2693
2694 printk(" sg_working_ix 0x%x, target_cmd %u\n",
2695 q->sg_working_ix, q->target_cmd);
2696
2697 printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
2698 (ulong)le32_to_cpu(q->scsiq_rptr),
2699 (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
2700
2701 /* Display the request's ADV_SG_BLOCK structures. */
2702 if (q->sg_list_ptr != NULL) {
2703 sg_blk_cnt = 0;
2704 while (1) {
2705 /*
2706 * 'sg_ptr' is a physical address. Convert it to a virtual
2707 * address by indexing 'sg_blk_cnt' into the virtual address
2708 * array 'sg_list_ptr'.
2709 *
2710 * XXX - Assumes all SG physical blocks are virtually contiguous.
2711 */
2712 sg_ptr =
2713 &(((ADV_SG_BLOCK *)(q->sg_list_ptr))[sg_blk_cnt]);
2714 asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
2715 if (sg_ptr->sg_ptr == 0) {
2716 break;
2717 }
2718 sg_blk_cnt++;
2719 }
2720 }
2721}
51219358 2722#endif /* ADVANSYS_DEBUG */
47d853cc 2723
b249c7fd
MW		 2724/*
2725 * The advansys chip/microcode contains a 32-bit identifier for each command
2726 * known as the 'srb'. I don't know what it stands for. The driver used
2727 * to encode the scsi_cmnd pointer by calling virt_to_bus and retrieve it
2728 * with bus_to_virt. Now the driver keeps a per-host map of integers to
2729 * pointers. It auto-expands when full, unless it can't allocate memory.
2730 * Note that an srb of 0 is treated specially by the chip/firmware, hence
2731 * the return of i+1 in this routine, and the corresponding subtraction in
2732 * the inverse routine.
2733 */
2734#define BAD_SRB 0
2735static u32 advansys_ptr_to_srb(struct asc_dvc_var *asc_dvc, void *ptr)
2736{
2737 int i;
2738 void **new_ptr;
2739
2740 for (i = 0; i < asc_dvc->ptr_map_count; i++) {
2741 if (!asc_dvc->ptr_map[i])
2742 goto out;
2743 }
2744
2745 if (asc_dvc->ptr_map_count == 0)
2746 asc_dvc->ptr_map_count = 1;
2747 else
2748 asc_dvc->ptr_map_count *= 2;
2749
2750 new_ptr = krealloc(asc_dvc->ptr_map,
2751 asc_dvc->ptr_map_count * sizeof(void *), GFP_ATOMIC);
2752 if (!new_ptr)
2753 return BAD_SRB;
2754 asc_dvc->ptr_map = new_ptr;
2755 out:
2756 ASC_DBG(3, "Putting ptr %p into array offset %d\n", ptr, i);
2757 asc_dvc->ptr_map[i] = ptr;
2758 return i + 1;
2759}
2760
2761static void * advansys_srb_to_ptr(struct asc_dvc_var *asc_dvc, u32 srb)
2762{
2763 void *ptr;
2764
2765 srb--;
2766 if (srb >= asc_dvc->ptr_map_count) {
2767 printk("advansys: bad SRB %u, max %u\n", srb,
2768 asc_dvc->ptr_map_count);
2769 return NULL;
2770 }
2771 ptr = asc_dvc->ptr_map[srb];
2772 asc_dvc->ptr_map[srb] = NULL;
2773 ASC_DBG(3, "Returning ptr %p from array offset %d\n", ptr, srb);
2774 return ptr;
2775}
2776
1da177e4 2777/*
51219358 2778 * advansys_info()
47d853cc 2779 *
51219358
MW		 2780 * Return suitable for printing on the console with the argument
2781 * adapter's configuration information.
2782 *
2783 * Note: The information line should not exceed ASC_INFO_SIZE bytes,
2784 * otherwise the static 'info' array will be overrun.
1da177e4 2785 */
51219358 2786static const char *advansys_info(struct Scsi_Host *shost)
1da177e4 2787{
51219358 2788 static char info[ASC_INFO_SIZE];
d2411495 2789 struct asc_board *boardp = shost_priv(shost);
51219358
MW		 2790 ASC_DVC_VAR *asc_dvc_varp;
2791 ADV_DVC_VAR *adv_dvc_varp;
2792 char *busname;
2793 char *widename = NULL;
1da177e4 2794
51219358
MW		 2795 if (ASC_NARROW_BOARD(boardp)) {
2796 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
b352f923 2797 ASC_DBG(1, "begin\n");
51219358
MW		 2798 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2799 if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
2800 ASC_IS_ISAPNP) {
2801 busname = "ISA PnP";
2802 } else {
2803 busname = "ISA";
2804 }
2805 sprintf(info,
2806 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
2807 ASC_VERSION, busname,
2808 (ulong)shost->io_port,
2809 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
d361db48 2810 boardp->irq, shost->dma_channel);
51219358
MW		 2811 } else {
2812 if (asc_dvc_varp->bus_type & ASC_IS_VL) {
2813 busname = "VL";
2814 } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
2815 busname = "EISA";
2816 } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
2817 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
2818 == ASC_IS_PCI_ULTRA) {
2819 busname = "PCI Ultra";
2820 } else {
2821 busname = "PCI";
2822 }
2823 } else {
2824 busname = "?";
9d0e96eb
MW		 2825 shost_printk(KERN_ERR, shost, "unknown bus "
2826 "type %d\n", asc_dvc_varp->bus_type);
51219358
MW		 2827 }
2828 sprintf(info,
2829 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
2830 ASC_VERSION, busname, (ulong)shost->io_port,
2831 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
d361db48 2832 boardp->irq);
51219358
MW		 2833 }
2834 } else {
2835 /*
2836 * Wide Adapter Information
2837 *
2838 * Memory-mapped I/O is used instead of I/O space to access
2839 * the adapter, but display the I/O Port range. The Memory
2840 * I/O address is displayed through the driver /proc file.
2841 */
2842 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2843 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2844 widename = "Ultra-Wide";
2845 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2846 widename = "Ultra2-Wide";
2847 } else {
2848 widename = "Ultra3-Wide";
2849 }
2850 sprintf(info,
2851 "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
2852 ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
d361db48 2853 (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq);
51219358
MW		 2854 }
2855 BUG_ON(strlen(info) >= ASC_INFO_SIZE);
b352f923 2856 ASC_DBG(1, "end\n");
51219358 2857 return info;
47d853cc
MW		 2858}
2859
51219358 2860#ifdef CONFIG_PROC_FS
47d853cc
MW		 2861
2862/*
51219358 2863 * asc_prt_board_devices()
47d853cc 2864 *
51219358 2865 * Print driver information for devices attached to the board.
47d853cc 2866 */
b59fb6fd 2867static void asc_prt_board_devices(struct seq_file *m, struct Scsi_Host *shost)
47d853cc 2868{
d2411495 2869 struct asc_board *boardp = shost_priv(shost);
51219358
MW		 2870 int chip_scsi_id;
2871 int i;
47d853cc 2872
b59fb6fd
AV		 2873 seq_printf(m,
2874 "\nDevice Information for AdvanSys SCSI Host %d:\n",
2875 shost->host_no);
47d853cc 2876
51219358
MW		 2877 if (ASC_NARROW_BOARD(boardp)) {
2878 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
2879 } else {
2880 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
47d853cc
MW		 2881 }
2882
2f979427 2883 seq_puts(m, "Target IDs Detected:");
51219358 2884 for (i = 0; i <= ADV_MAX_TID; i++) {
b59fb6fd
AV		 2885 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i))
2886 seq_printf(m, " %X,", i);
27c868c2 2887 }
b59fb6fd 2888 seq_printf(m, " (%X=Host Adapter)\n", chip_scsi_id);
47d853cc
MW		 2889}
2890
2891/*
51219358 2892 * Display Wide Board BIOS Information.
47d853cc 2893 */
b59fb6fd 2894static void asc_prt_adv_bios(struct seq_file *m, struct Scsi_Host *shost)
47d853cc 2895{
d2411495 2896 struct asc_board *boardp = shost_priv(shost);
51219358
MW		 2897 ushort major, minor, letter;
2898
2f979427 2899 seq_puts(m, "\nROM BIOS Version: ");
47d853cc
MW		 2900
2901 /*
51219358
MW		 2902 * If the BIOS saved a valid signature, then fill in
2903 * the BIOS code segment base address.
47d853cc 2904 */
51219358 2905 if (boardp->bios_signature != 0x55AA) {
2f979427
RV		 2906 seq_puts(m, "Disabled or Pre-3.1\n");
2907 seq_puts(m,
2908 "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n");
2909 seq_puts(m,
2910 "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
51219358
MW		 2911 } else {
2912 major = (boardp->bios_version >> 12) & 0xF;
2913 minor = (boardp->bios_version >> 8) & 0xF;
2914 letter = (boardp->bios_version & 0xFF);
47d853cc 2915
b59fb6fd 2916 seq_printf(m, "%d.%d%c\n",
51219358
MW		 2917 major, minor,
2918 letter >= 26 ? '?' : letter + 'A');
51219358
MW		 2919 /*
2920 * Current available ROM BIOS release is 3.1I for UW
2921 * and 3.2I for U2W. This code doesn't differentiate
2922 * UW and U2W boards.
2923 */
2924 if (major < 3 || (major <= 3 && minor < 1) ||
2925 (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
2f979427
RV		 2926 seq_puts(m,
2927 "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n");
2928 seq_puts(m, "ftp://ftp.connectcom.net/pub\n");
51219358
MW		 2929 }
2930 }
1da177e4
LT		 2931}
2932
1da177e4 2933/*
51219358
MW		 2934 * Add serial number to information bar if signature AAh
2935 * is found in at bit 15-9 (7 bits) of word 1.
1da177e4 2936 *
51219358 2937 * Serial Number consists fo 12 alpha-numeric digits.
1da177e4 2938 *
51219358
MW		 2939 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits)
2940 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits)
2941 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits)
2942 * 5 - Product revision (A-J) Word0: " "
1da177e4 2943 *
51219358
MW		 2944 * Signature Word1: 15-9 (7 bits)
2945 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
2946 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits)
1da177e4 2947 *
51219358 2948 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
1da177e4 2949 *
51219358 2950 * Note 1: Only production cards will have a serial number.
1da177e4 2951 *
51219358 2952 * Note 2: Signature is most significant 7 bits (0xFE).
1da177e4 2953 *
51219358 2954 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
1da177e4 2955 */
51219358 2956static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
1da177e4 2957{
51219358 2958 ushort w, num;
27c868c2 2959
51219358
MW		 2960 if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
2961 return ASC_FALSE;
2962 } else {
2963 /*
2964 * First word - 6 digits.
2965 */
2966 w = serialnum[0];
27c868c2 2967
51219358
MW		 2968 /* Product type - 1st digit. */
2969 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
2970 /* Product type is P=Prototype */
2971 *cp += 0x8;
2972 }
2973 cp++;
2974
2975 /* Manufacturing location - 2nd digit. */
2976 *cp++ = 'A' + ((w & 0x1C00) >> 10);
2977
2978 /* Product ID - 3rd, 4th digits. */
2979 num = w & 0x3FF;
2980 *cp++ = '0' + (num / 100);
2981 num %= 100;
2982 *cp++ = '0' + (num / 10);
2983
2984 /* Product revision - 5th digit. */
2985 *cp++ = 'A' + (num % 10);
27c868c2 2986
27c868c2 2987 /*
51219358 2988 * Second word
27c868c2 2989 */
51219358 2990 w = serialnum[1];
27c868c2
MW		 2991
2992 /*
51219358 2993 * Year - 6th digit.
27c868c2 2994 *
51219358
MW		 2995 * If bit 15 of third word is set, then the
2996 * last digit of the year is greater than 7.
27c868c2 2997 */
51219358
MW		 2998 if (serialnum[2] & 0x8000) {
2999 *cp++ = '8' + ((w & 0x1C0) >> 6);
3000 } else {
3001 *cp++ = '0' + ((w & 0x1C0) >> 6);
27c868c2
MW		 3002 }
3003
51219358
MW		 3004 /* Week of year - 7th, 8th digits. */
3005 num = w & 0x003F;
3006 *cp++ = '0' + num / 10;
3007 num %= 10;
3008 *cp++ = '0' + num;
27c868c2
MW		 3009
3010 /*
51219358 3011 * Third word
27c868c2 3012 */
51219358 3013 w = serialnum[2] & 0x7FFF;
1da177e4 3014
51219358
MW		 3015 /* Serial number - 9th digit. */
3016 *cp++ = 'A' + (w / 1000);
27c868c2 3017
51219358
MW		 3018 /* 10th, 11th, 12th digits. */
3019 num = w % 1000;
3020 *cp++ = '0' + num / 100;
3021 num %= 100;
3022 *cp++ = '0' + num / 10;
3023 num %= 10;
3024 *cp++ = '0' + num;
3025
3026 *cp = '\0'; /* Null Terminate the string. */
3027 return ASC_TRUE;
3028 }
1da177e4
LT		 3029}
3030
3031/*
51219358 3032 * asc_prt_asc_board_eeprom()
1da177e4 3033 *
51219358 3034 * Print board EEPROM configuration.
1da177e4 3035 */
b59fb6fd 3036static void asc_prt_asc_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 3037{
d2411495 3038 struct asc_board *boardp = shost_priv(shost);
51219358 3039 ASC_DVC_VAR *asc_dvc_varp;
51219358
MW		 3040 ASCEEP_CONFIG *ep;
3041 int i;
3042#ifdef CONFIG_ISA
3043 int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
3044#endif /* CONFIG_ISA */
3045 uchar serialstr[13];
27c868c2 3046
51219358
MW		 3047 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
3048 ep = &boardp->eep_config.asc_eep;
27c868c2 3049
b59fb6fd
AV		 3050 seq_printf(m,
3051 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3052 shost->host_no);
1da177e4 3053
51219358 3054 if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
b59fb6fd
AV		 3055 == ASC_TRUE)
3056 seq_printf(m, " Serial Number: %s\n", serialstr);
3057 else if (ep->adapter_info[5] == 0xBB)
2f979427
RV		 3058 seq_puts(m,
3059 " Default Settings Used for EEPROM-less Adapter.\n");
b59fb6fd 3060 else
2f979427 3061 seq_puts(m, " Serial Number Signature Not Present.\n");
b59fb6fd
AV		 3062
3063 seq_printf(m,
3064 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3065 ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
3066 ep->max_tag_qng);
3067
3068 seq_printf(m,
3069 " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
3070
2f979427 3071 seq_puts(m, " Target ID: ");
b59fb6fd
AV		 3072 for (i = 0; i <= ASC_MAX_TID; i++)
3073 seq_printf(m, " %d", i);
2f979427 3074 seq_puts(m, "\n");
b59fb6fd 3075
2f979427 3076 seq_puts(m, " Disconnects: ");
b59fb6fd
AV		 3077 for (i = 0; i <= ASC_MAX_TID; i++)
3078 seq_printf(m, " %c",
3079 (ep->disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2f979427 3080 seq_puts(m, "\n");
b59fb6fd 3081
2f979427 3082 seq_puts(m, " Command Queuing: ");
b59fb6fd
AV		 3083 for (i = 0; i <= ASC_MAX_TID; i++)
3084 seq_printf(m, " %c",
3085 (ep->use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2f979427 3086 seq_puts(m, "\n");
b59fb6fd 3087
2f979427 3088 seq_puts(m, " Start Motor: ");
b59fb6fd
AV		 3089 for (i = 0; i <= ASC_MAX_TID; i++)
3090 seq_printf(m, " %c",
3091 (ep->start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2f979427 3092 seq_puts(m, "\n");
b59fb6fd 3093
2f979427 3094 seq_puts(m, " Synchronous Transfer:");
b59fb6fd
AV		 3095 for (i = 0; i <= ASC_MAX_TID; i++)
3096 seq_printf(m, " %c",
3097 (ep->init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2f979427 3098 seq_puts(m, "\n");
51219358
MW		 3099
3100#ifdef CONFIG_ISA
3101 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
b59fb6fd
AV		 3102 seq_printf(m,
3103 " Host ISA DMA speed: %d MB/S\n",
3104 isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
51219358
MW		 3105 }
3106#endif /* CONFIG_ISA */
1da177e4
LT		 3107}
3108
3109/*
51219358 3110 * asc_prt_adv_board_eeprom()
1da177e4 3111 *
51219358 3112 * Print board EEPROM configuration.
1da177e4 3113 */
b59fb6fd 3114static void asc_prt_adv_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 3115{
d2411495 3116 struct asc_board *boardp = shost_priv(shost);
51219358 3117 ADV_DVC_VAR *adv_dvc_varp;
27c868c2 3118 int i;
51219358
MW		 3119 char *termstr;
3120 uchar serialstr[13];
3121 ADVEEP_3550_CONFIG *ep_3550 = NULL;
3122 ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
3123 ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
3124 ushort word;
3125 ushort *wordp;
3126 ushort sdtr_speed = 0;
27c868c2 3127
51219358
MW		 3128 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
3129 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3130 ep_3550 = &boardp->eep_config.adv_3550_eep;
3131 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3132 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
27c868c2 3133 } else {
51219358 3134 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
27c868c2 3135 }
1da177e4 3136
b59fb6fd
AV		 3137 seq_printf(m,
3138 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3139 shost->host_no);
27c868c2 3140
51219358
MW		 3141 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3142 wordp = &ep_3550->serial_number_word1;
3143 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3144 wordp = &ep_38C0800->serial_number_word1;
3145 } else {
3146 wordp = &ep_38C1600->serial_number_word1;
3147 }
27c868c2 3148
b59fb6fd
AV		 3149 if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE)
3150 seq_printf(m, " Serial Number: %s\n", serialstr);
3151 else
2f979427 3152 seq_puts(m, " Serial Number Signature Not Present.\n");
27c868c2 3153
b59fb6fd
AV		 3154 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3155 seq_printf(m,
3156 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3157 ep_3550->adapter_scsi_id,
3158 ep_3550->max_host_qng, ep_3550->max_dvc_qng);
3159 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3160 seq_printf(m,
3161 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3162 ep_38C0800->adapter_scsi_id,
3163 ep_38C0800->max_host_qng,
3164 ep_38C0800->max_dvc_qng);
3165 else
3166 seq_printf(m,
3167 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3168 ep_38C1600->adapter_scsi_id,
3169 ep_38C1600->max_host_qng,
3170 ep_38C1600->max_dvc_qng);
51219358
MW		 3171 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3172 word = ep_3550->termination;
3173 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3174 word = ep_38C0800->termination_lvd;
3175 } else {
3176 word = ep_38C1600->termination_lvd;
3177 }
3178 switch (word) {
3179 case 1:
3180 termstr = "Low Off/High Off";
3181 break;
3182 case 2:
3183 termstr = "Low Off/High On";
3184 break;
3185 case 3:
3186 termstr = "Low On/High On";
3187 break;
3188 default:
3189 case 0:
3190 termstr = "Automatic";
3191 break;
27c868c2 3192 }
1da177e4 3193
b59fb6fd
AV		 3194 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3195 seq_printf(m,
3196 " termination: %u (%s), bios_ctrl: 0x%x\n",
3197 ep_3550->termination, termstr,
3198 ep_3550->bios_ctrl);
3199 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3200 seq_printf(m,
3201 " termination: %u (%s), bios_ctrl: 0x%x\n",
3202 ep_38C0800->termination_lvd, termstr,
3203 ep_38C0800->bios_ctrl);
3204 else
3205 seq_printf(m,
3206 " termination: %u (%s), bios_ctrl: 0x%x\n",
3207 ep_38C1600->termination_lvd, termstr,
3208 ep_38C1600->bios_ctrl);
1da177e4 3209
2f979427 3210 seq_puts(m, " Target ID: ");
b59fb6fd
AV		 3211 for (i = 0; i <= ADV_MAX_TID; i++)
3212 seq_printf(m, " %X", i);
2f979427 3213 seq_puts(m, "\n");
1da177e4 3214
51219358
MW		 3215 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3216 word = ep_3550->disc_enable;
3217 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3218 word = ep_38C0800->disc_enable;
3219 } else {
3220 word = ep_38C1600->disc_enable;
3221 }
2f979427 3222 seq_puts(m, " Disconnects: ");
b59fb6fd
AV		 3223 for (i = 0; i <= ADV_MAX_TID; i++)
3224 seq_printf(m, " %c",
3225 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2f979427 3226 seq_puts(m, "\n");
1da177e4 3227
51219358
MW		 3228 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3229 word = ep_3550->tagqng_able;
3230 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3231 word = ep_38C0800->tagqng_able;
3232 } else {
3233 word = ep_38C1600->tagqng_able;
3234 }
2f979427 3235 seq_puts(m, " Command Queuing: ");
b59fb6fd
AV		 3236 for (i = 0; i <= ADV_MAX_TID; i++)
3237 seq_printf(m, " %c",
3238 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2f979427 3239 seq_puts(m, "\n");
1da177e4 3240
51219358
MW		 3241 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3242 word = ep_3550->start_motor;
3243 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3244 word = ep_38C0800->start_motor;
27c868c2 3245 } else {
51219358
MW		 3246 word = ep_38C1600->start_motor;
3247 }
2f979427 3248 seq_puts(m, " Start Motor: ");
b59fb6fd
AV		 3249 for (i = 0; i <= ADV_MAX_TID; i++)
3250 seq_printf(m, " %c",
3251 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2f979427 3252 seq_puts(m, "\n");
27c868c2 3253
51219358 3254 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2f979427 3255 seq_puts(m, " Synchronous Transfer:");
b59fb6fd
AV		 3256 for (i = 0; i <= ADV_MAX_TID; i++)
3257 seq_printf(m, " %c",
3258 (ep_3550->sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
3259 'Y' : 'N');
2f979427 3260 seq_puts(m, "\n");
51219358 3261 }
27c868c2 3262
51219358 3263 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2f979427 3264 seq_puts(m, " Ultra Transfer: ");
b59fb6fd
AV		 3265 for (i = 0; i <= ADV_MAX_TID; i++)
3266 seq_printf(m, " %c",
3267 (ep_3550->ultra_able & ADV_TID_TO_TIDMASK(i))
3268 ? 'Y' : 'N');
2f979427 3269 seq_puts(m, "\n");
51219358 3270 }
27c868c2 3271
51219358
MW		 3272 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3273 word = ep_3550->wdtr_able;
3274 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3275 word = ep_38C0800->wdtr_able;
3276 } else {
3277 word = ep_38C1600->wdtr_able;
3278 }
2f979427 3279 seq_puts(m, " Wide Transfer: ");
b59fb6fd
AV		 3280 for (i = 0; i <= ADV_MAX_TID; i++)
3281 seq_printf(m, " %c",
3282 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2f979427 3283 seq_puts(m, "\n");
1da177e4 3284
51219358
MW		 3285 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
3286 adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
2f979427 3287 seq_puts(m, " Synchronous Transfer Speed (Mhz):\n ");
51219358
MW		 3288 for (i = 0; i <= ADV_MAX_TID; i++) {
3289 char *speed_str;
1da177e4 3290
51219358
MW		 3291 if (i == 0) {
3292 sdtr_speed = adv_dvc_varp->sdtr_speed1;
3293 } else if (i == 4) {
3294 sdtr_speed = adv_dvc_varp->sdtr_speed2;
3295 } else if (i == 8) {
3296 sdtr_speed = adv_dvc_varp->sdtr_speed3;
3297 } else if (i == 12) {
3298 sdtr_speed = adv_dvc_varp->sdtr_speed4;
3299 }
3300 switch (sdtr_speed & ADV_MAX_TID) {
3301 case 0:
3302 speed_str = "Off";
3303 break;
3304 case 1:
3305 speed_str = " 5";
3306 break;
3307 case 2:
3308 speed_str = " 10";
3309 break;
3310 case 3:
3311 speed_str = " 20";
3312 break;
3313 case 4:
3314 speed_str = " 40";
3315 break;
3316 case 5:
3317 speed_str = " 80";
3318 break;
3319 default:
3320 speed_str = "Unk";
3321 break;
3322 }
b59fb6fd
AV		 3323 seq_printf(m, "%X:%s ", i, speed_str);
3324 if (i == 7)
2f979427 3325 seq_puts(m, "\n ");
51219358
MW		 3326 sdtr_speed >>= 4;
3327 }
2f979427 3328 seq_puts(m, "\n");
51219358 3329 }
1da177e4
LT		 3330}
3331
3332/*
51219358 3333 * asc_prt_driver_conf()
1da177e4 3334 */
b59fb6fd 3335static void asc_prt_driver_conf(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 3336{
d2411495 3337 struct asc_board *boardp = shost_priv(shost);
51219358 3338 int chip_scsi_id;
27c868c2 3339
b59fb6fd
AV		 3340 seq_printf(m,
3341 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
3342 shost->host_no);
27c868c2 3343
b59fb6fd 3344 seq_printf(m,
1abf635d 3345 " host_busy %u, max_id %u, max_lun %llu, max_channel %u\n",
74665016 3346 atomic_read(&shost->host_busy), shost->max_id,
b59fb6fd 3347 shost->max_lun, shost->max_channel);
95c9f162 3348
b59fb6fd
AV		 3349 seq_printf(m,
3350 " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
3351 shost->unique_id, shost->can_queue, shost->this_id,
3352 shost->sg_tablesize, shost->cmd_per_lun);
95c9f162 3353
b59fb6fd
AV		 3354 seq_printf(m,
3355 " unchecked_isa_dma %d, use_clustering %d\n",
3356 shost->unchecked_isa_dma, shost->use_clustering);
95c9f162 3357
b59fb6fd 3358 seq_printf(m,
31491e1a 3359 " flags 0x%x, last_reset 0x%lx, jiffies 0x%lx, asc_n_io_port 0x%x\n",
b59fb6fd
AV		 3360 boardp->flags, boardp->last_reset, jiffies,
3361 boardp->asc_n_io_port);
27c868c2 3362
31491e1a 3363 seq_printf(m, " io_port 0x%lx\n", shost->io_port);
27c868c2 3364
51219358
MW		 3365 if (ASC_NARROW_BOARD(boardp)) {
3366 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
3367 } else {
3368 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
27c868c2 3369 }
1da177e4
LT		 3370}
3371
3372/*
51219358 3373 * asc_prt_asc_board_info()
1da177e4 3374 *
51219358 3375 * Print dynamic board configuration information.
1da177e4 3376 */
b59fb6fd 3377static void asc_prt_asc_board_info(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 3378{
d2411495 3379 struct asc_board *boardp = shost_priv(shost);
51219358 3380 int chip_scsi_id;
51219358
MW		 3381 ASC_DVC_VAR *v;
3382 ASC_DVC_CFG *c;
3383 int i;
3384 int renegotiate = 0;
27c868c2 3385
51219358
MW		 3386 v = &boardp->dvc_var.asc_dvc_var;
3387 c = &boardp->dvc_cfg.asc_dvc_cfg;
3388 chip_scsi_id = c->chip_scsi_id;
27c868c2 3389
b59fb6fd
AV		 3390 seq_printf(m,
3391 "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3392 shost->host_no);
27c868c2 3393
b59fb6fd
AV		 3394 seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3395 "mcode_version 0x%x, err_code %u\n",
3396 c->chip_version, c->mcode_date, c->mcode_version,
3397 v->err_code);
1da177e4 3398
51219358 3399 /* Current number of commands waiting for the host. */
b59fb6fd
AV		 3400 seq_printf(m,
3401 " Total Command Pending: %d\n", v->cur_total_qng);
1da177e4 3402
2f979427 3403 seq_puts(m, " Command Queuing:");
51219358
MW		 3404 for (i = 0; i <= ASC_MAX_TID; i++) {
3405 if ((chip_scsi_id == i) ||
3406 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3407 continue;
27c868c2 3408 }
b59fb6fd
AV		 3409 seq_printf(m, " %X:%c",
3410 i,
3411 (v->use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
51219358 3412 }
2f979427 3413 seq_puts(m, "\n");
27c868c2 3414
51219358 3415 /* Current number of commands waiting for a device. */
2f979427 3416 seq_puts(m, " Command Queue Pending:");
51219358
MW		 3417 for (i = 0; i <= ASC_MAX_TID; i++) {
3418 if ((chip_scsi_id == i) ||
3419 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3420 continue;
27c868c2 3421 }
b59fb6fd 3422 seq_printf(m, " %X:%u", i, v->cur_dvc_qng[i]);
27c868c2 3423 }
2f979427 3424 seq_puts(m, "\n");
1da177e4 3425
51219358 3426 /* Current limit on number of commands that can be sent to a device. */
2f979427 3427 seq_puts(m, " Command Queue Limit:");
51219358
MW		 3428 for (i = 0; i <= ASC_MAX_TID; i++) {
3429 if ((chip_scsi_id == i) ||
3430 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3431 continue;
3432 }
b59fb6fd 3433 seq_printf(m, " %X:%u", i, v->max_dvc_qng[i]);
27c868c2 3434 }
2f979427 3435 seq_puts(m, "\n");
1da177e4 3436
51219358 3437 /* Indicate whether the device has returned queue full status. */
2f979427 3438 seq_puts(m, " Command Queue Full:");
51219358
MW		 3439 for (i = 0; i <= ASC_MAX_TID; i++) {
3440 if ((chip_scsi_id == i) ||
3441 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3442 continue;
3443 }
b59fb6fd
AV		 3444 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i))
3445 seq_printf(m, " %X:Y-%d",
3446 i, boardp->queue_full_cnt[i]);
3447 else
3448 seq_printf(m, " %X:N", i);
51219358 3449 }
2f979427 3450 seq_puts(m, "\n");
1da177e4 3451
2f979427 3452 seq_puts(m, " Synchronous Transfer:");
51219358
MW		 3453 for (i = 0; i <= ASC_MAX_TID; i++) {
3454 if ((chip_scsi_id == i) ||
3455 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3456 continue;
3457 }
b59fb6fd
AV		 3458 seq_printf(m, " %X:%c",
3459 i,
3460 (v->sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
27c868c2 3461 }
2f979427 3462 seq_puts(m, "\n");
1da177e4 3463
51219358
MW		 3464 for (i = 0; i <= ASC_MAX_TID; i++) {
3465 uchar syn_period_ix;
1da177e4 3466
51219358
MW		 3467 if ((chip_scsi_id == i) ||
3468 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3469 ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
3470 continue;
27c868c2 3471 }
27c868c2 3472
b59fb6fd 3473 seq_printf(m, " %X:", i);
27c868c2 3474
51219358 3475 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
2f979427 3476 seq_puts(m, " Asynchronous");
51219358
MW		 3477 } else {
3478 syn_period_ix =
3479 (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
3480 1);
27c868c2 3481
b59fb6fd
AV		 3482 seq_printf(m,
3483 " Transfer Period Factor: %d (%d.%d Mhz),",
3484 v->sdtr_period_tbl[syn_period_ix],
3485 250 / v->sdtr_period_tbl[syn_period_ix],
3486 ASC_TENTHS(250,
3487 v->sdtr_period_tbl[syn_period_ix]));
27c868c2 3488
b59fb6fd
AV		 3489 seq_printf(m, " REQ/ACK Offset: %d",
3490 boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET);
51219358 3491 }
1da177e4 3492
51219358 3493 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
2f979427 3494 seq_puts(m, "*\n");
51219358
MW		 3495 renegotiate = 1;
3496 } else {
2f979427 3497 seq_puts(m, "\n");
51219358 3498 }
27c868c2 3499 }
1da177e4 3500
51219358 3501 if (renegotiate) {
2f979427 3502 seq_puts(m, " * = Re-negotiation pending before next command.\n");
27c868c2 3503 }
1da177e4
LT		 3504}
3505
1da177e4 3506/*
51219358 3507 * asc_prt_adv_board_info()
1da177e4 3508 *
51219358 3509 * Print dynamic board configuration information.
1da177e4 3510 */
b59fb6fd 3511static void asc_prt_adv_board_info(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 3512{
d2411495 3513 struct asc_board *boardp = shost_priv(shost);
27c868c2 3514 int i;
51219358
MW		 3515 ADV_DVC_VAR *v;
3516 ADV_DVC_CFG *c;
3517 AdvPortAddr iop_base;
3518 ushort chip_scsi_id;
3519 ushort lramword;
3520 uchar lrambyte;
3521 ushort tagqng_able;
3522 ushort sdtr_able, wdtr_able;
3523 ushort wdtr_done, sdtr_done;
3524 ushort period = 0;
3525 int renegotiate = 0;
27c868c2 3526
51219358
MW		 3527 v = &boardp->dvc_var.adv_dvc_var;
3528 c = &boardp->dvc_cfg.adv_dvc_cfg;
3529 iop_base = v->iop_base;
3530 chip_scsi_id = v->chip_scsi_id;
3531
b59fb6fd
AV		 3532 seq_printf(m,
3533 "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3534 shost->host_no);
27c868c2 3535
b59fb6fd
AV		 3536 seq_printf(m,
3537 " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
31491e1a 3538 (unsigned long)v->iop_base,
b59fb6fd
AV		 3539 AdvReadWordRegister(iop_base,IOPW_SCSI_CFG1) & CABLE_DETECT,
3540 v->err_code);
1da177e4 3541
b59fb6fd
AV		 3542 seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3543 "mcode_version 0x%x\n", c->chip_version,
3544 c->mcode_date, c->mcode_version);
51219358
MW		 3545
3546 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
2f979427 3547 seq_puts(m, " Queuing Enabled:");
27c868c2 3548 for (i = 0; i <= ADV_MAX_TID; i++) {
51219358
MW		 3549 if ((chip_scsi_id == i) ||
3550 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3551 continue;
27c868c2 3552 }
51219358 3553
b59fb6fd
AV		 3554 seq_printf(m, " %X:%c",
3555 i,
3556 (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
27c868c2 3557 }
2f979427 3558 seq_puts(m, "\n");
1da177e4 3559
2f979427 3560 seq_puts(m, " Queue Limit:");
51219358
MW		 3561 for (i = 0; i <= ADV_MAX_TID; i++) {
3562 if ((chip_scsi_id == i) ||
3563 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3564 continue;
3565 }
1da177e4 3566
51219358
MW		 3567 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
3568 lrambyte);
27c868c2 3569
b59fb6fd 3570 seq_printf(m, " %X:%d", i, lrambyte);
51219358 3571 }
2f979427 3572 seq_puts(m, "\n");
27c868c2 3573
2f979427 3574 seq_puts(m, " Command Pending:");
51219358
MW		 3575 for (i = 0; i <= ADV_MAX_TID; i++) {
3576 if ((chip_scsi_id == i) ||
3577 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3578 continue;
3579 }
27c868c2 3580
51219358
MW		 3581 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
3582 lrambyte);
1da177e4 3583
b59fb6fd 3584 seq_printf(m, " %X:%d", i, lrambyte);
51219358 3585 }
2f979427 3586 seq_puts(m, "\n");
1da177e4 3587
51219358 3588 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
2f979427 3589 seq_puts(m, " Wide Enabled:");
51219358
MW		 3590 for (i = 0; i <= ADV_MAX_TID; i++) {
3591 if ((chip_scsi_id == i) ||
3592 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3593 continue;
27c868c2 3594 }
51219358 3595
b59fb6fd
AV		 3596 seq_printf(m, " %X:%c",
3597 i,
3598 (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
27c868c2 3599 }
2f979427 3600 seq_puts(m, "\n");
1da177e4 3601
51219358 3602 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
2f979427 3603 seq_puts(m, " Transfer Bit Width:");
51219358
MW		 3604 for (i = 0; i <= ADV_MAX_TID; i++) {
3605 if ((chip_scsi_id == i) ||
3606 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3607 continue;
3608 }
1da177e4 3609
51219358
MW		 3610 AdvReadWordLram(iop_base,
3611 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3612 lramword);
27c868c2 3613
b59fb6fd
AV		 3614 seq_printf(m, " %X:%d",
3615 i, (lramword & 0x8000) ? 16 : 8);
27c868c2 3616
51219358
MW		 3617 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
3618 (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
2f979427 3619 seq_puts(m, "*");
51219358 3620 renegotiate = 1;
27c868c2 3621 }
51219358 3622 }
2f979427 3623 seq_puts(m, "\n");
27c868c2 3624
51219358 3625 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
2f979427 3626 seq_puts(m, " Synchronous Enabled:");
51219358
MW		 3627 for (i = 0; i <= ADV_MAX_TID; i++) {
3628 if ((chip_scsi_id == i) ||
3629 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3630 continue;
3631 }
27c868c2 3632
b59fb6fd
AV		 3633 seq_printf(m, " %X:%c",
3634 i,
3635 (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
51219358 3636 }
2f979427 3637 seq_puts(m, "\n");
27c868c2 3638
51219358
MW		 3639 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
3640 for (i = 0; i <= ADV_MAX_TID; i++) {
27c868c2 3641
51219358
MW		 3642 AdvReadWordLram(iop_base,
3643 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3644 lramword);
3645 lramword &= ~0x8000;
27c868c2 3646
51219358
MW		 3647 if ((chip_scsi_id == i) ||
3648 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3649 ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
3650 continue;
27c868c2
MW		 3651 }
3652
b59fb6fd 3653 seq_printf(m, " %X:", i);
27c868c2 3654
51219358 3655 if ((lramword & 0x1F) == 0) { /* Check for REQ/ACK Offset 0. */
2f979427 3656 seq_puts(m, " Asynchronous");
51219358 3657 } else {
2f979427 3658 seq_puts(m, " Transfer Period Factor: ");
27c868c2 3659
51219358 3660 if ((lramword & 0x1F00) == 0x1100) { /* 80 Mhz */
2f979427 3661 seq_puts(m, "9 (80.0 Mhz),");
51219358 3662 } else if ((lramword & 0x1F00) == 0x1000) { /* 40 Mhz */
2f979427 3663 seq_puts(m, "10 (40.0 Mhz),");
51219358 3664 } else { /* 20 Mhz or below. */
27c868c2 3665
51219358
MW		 3666 period = (((lramword >> 8) * 25) + 50) / 4;
3667
3668 if (period == 0) { /* Should never happen. */
31491e1a 3669 seq_printf(m, "%d (? Mhz), ", period);
51219358 3670 } else {
b59fb6fd
AV		 3671 seq_printf(m,
3672 "%d (%d.%d Mhz),",
3673 period, 250 / period,
3674 ASC_TENTHS(250, period));
51219358
MW		 3675 }
3676 }
3677
b59fb6fd
AV		 3678 seq_printf(m, " REQ/ACK Offset: %d",
3679 lramword & 0x1F);
51219358
MW		 3680 }
3681
3682 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
2f979427 3683 seq_puts(m, "*\n");
51219358
MW		 3684 renegotiate = 1;
3685 } else {
2f979427 3686 seq_puts(m, "\n");
51219358 3687 }
27c868c2 3688 }
51219358
MW		 3689
3690 if (renegotiate) {
2f979427 3691 seq_puts(m, " * = Re-negotiation pending before next command.\n");
51219358 3692 }
51219358
MW		 3693}
3694
3695#ifdef ADVANSYS_STATS
3696/*
3697 * asc_prt_board_stats()
1da177e4 3698 */
b59fb6fd 3699static void asc_prt_board_stats(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 3700{
d2411495
MW		 3701 struct asc_board *boardp = shost_priv(shost);
3702 struct asc_stats *s = &boardp->asc_stats;
27c868c2 3703
b59fb6fd
AV		 3704 seq_printf(m,
3705 "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
3706 shost->host_no);
51219358 3707
b59fb6fd 3708 seq_printf(m,
31491e1a 3709 " queuecommand %u, reset %u, biosparam %u, interrupt %u\n",
b59fb6fd
AV		 3710 s->queuecommand, s->reset, s->biosparam,
3711 s->interrupt);
27c868c2 3712
b59fb6fd 3713 seq_printf(m,
31491e1a 3714 " callback %u, done %u, build_error %u, build_noreq %u, build_nosg %u\n",
b59fb6fd
AV		 3715 s->callback, s->done, s->build_error,
3716 s->adv_build_noreq, s->adv_build_nosg);
27c868c2 3717
b59fb6fd 3718 seq_printf(m,
31491e1a 3719 " exe_noerror %u, exe_busy %u, exe_error %u, exe_unknown %u\n",
b59fb6fd
AV		 3720 s->exe_noerror, s->exe_busy, s->exe_error,
3721 s->exe_unknown);
51219358
MW		 3722
3723 /*
3724 * Display data transfer statistics.
3725 */
52c334e9 3726 if (s->xfer_cnt > 0) {
31491e1a 3727 seq_printf(m, " xfer_cnt %u, xfer_elem %u, ",
b59fb6fd 3728 s->xfer_cnt, s->xfer_elem);
27c868c2 3729
31491e1a 3730 seq_printf(m, "xfer_bytes %u.%01u kb\n",
b59fb6fd 3731 s->xfer_sect / 2, ASC_TENTHS(s->xfer_sect, 2));
1da177e4 3732
51219358 3733 /* Scatter gather transfer statistics */
31491e1a 3734 seq_printf(m, " avg_num_elem %u.%01u, ",
b59fb6fd
AV		 3735 s->xfer_elem / s->xfer_cnt,
3736 ASC_TENTHS(s->xfer_elem, s->xfer_cnt));
51219358 3737
31491e1a 3738 seq_printf(m, "avg_elem_size %u.%01u kb, ",
b59fb6fd
AV		 3739 (s->xfer_sect / 2) / s->xfer_elem,
3740 ASC_TENTHS((s->xfer_sect / 2), s->xfer_elem));
51219358 3741
31491e1a 3742 seq_printf(m, "avg_xfer_size %u.%01u kb\n",
b59fb6fd
AV		 3743 (s->xfer_sect / 2) / s->xfer_cnt,
3744 ASC_TENTHS((s->xfer_sect / 2), s->xfer_cnt));
27c868c2 3745 }
1da177e4 3746}
51219358 3747#endif /* ADVANSYS_STATS */
1da177e4
LT		 3748
3749/*
b59fb6fd 3750 * advansys_show_info() - /proc/scsi/advansys/{0,1,2,3,...}
1da177e4 3751 *
b59fb6fd
AV		 3752 * m: seq_file to print into
3753 * shost: Scsi_Host
1da177e4 3754 *
51219358
MW		 3755 * Return the number of bytes read from or written to a
3756 * /proc/scsi/advansys/[0...] file.
1da177e4 3757 */
51219358 3758static int
b59fb6fd 3759advansys_show_info(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 3760{
d2411495 3761 struct asc_board *boardp = shost_priv(shost);
27c868c2 3762
b352f923 3763 ASC_DBG(1, "begin\n");
51219358 3764
51219358
MW		 3765 /*
3766 * User read of /proc/scsi/advansys/[0...] file.
3767 */
1da177e4 3768
51219358
MW		 3769 /*
3770 * Get board configuration information.
3771 *
3772 * advansys_info() returns the board string from its own static buffer.
3773 */
51219358 3774 /* Copy board information. */
b59fb6fd 3775 seq_printf(m, "%s\n", (char *)advansys_info(shost));
51219358
MW		 3776 /*
3777 * Display Wide Board BIOS Information.
3778 */
b59fb6fd
AV		 3779 if (!ASC_NARROW_BOARD(boardp))
3780 asc_prt_adv_bios(m, shost);
1da177e4 3781
51219358
MW		 3782 /*
3783 * Display driver information for each device attached to the board.
3784 */
b59fb6fd 3785 asc_prt_board_devices(m, shost);
51219358
MW		 3786
3787 /*
3788 * Display EEPROM configuration for the board.
3789 */
b59fb6fd
AV		 3790 if (ASC_NARROW_BOARD(boardp))
3791 asc_prt_asc_board_eeprom(m, shost);
3792 else
3793 asc_prt_adv_board_eeprom(m, shost);
1da177e4 3794
51219358
MW		 3795 /*
3796 * Display driver configuration and information for the board.
3797 */
b59fb6fd 3798 asc_prt_driver_conf(m, shost);
1da177e4 3799
51219358
MW		 3800#ifdef ADVANSYS_STATS
3801 /*
3802 * Display driver statistics for the board.
3803 */
b59fb6fd 3804 asc_prt_board_stats(m, shost);
51219358 3805#endif /* ADVANSYS_STATS */
1da177e4 3806
51219358
MW		 3807 /*
3808 * Display Asc Library dynamic configuration information
3809 * for the board.
3810 */
b59fb6fd
AV		 3811 if (ASC_NARROW_BOARD(boardp))
3812 asc_prt_asc_board_info(m, shost);
3813 else
3814 asc_prt_adv_board_info(m, shost);
3815 return 0;
51219358
MW		 3816}
3817#endif /* CONFIG_PROC_FS */
3818
3819static void asc_scsi_done(struct scsi_cmnd *scp)
3820{
52c334e9 3821 scsi_dma_unmap(scp);
51219358 3822 ASC_STATS(scp->device->host, done);
51219358
MW		 3823 scp->scsi_done(scp);
3824}
3825
3826static void AscSetBank(PortAddr iop_base, uchar bank)
3827{
3828 uchar val;
3829
3830 val = AscGetChipControl(iop_base) &
3831 (~
3832 (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
3833 CC_CHIP_RESET));
3834 if (bank == 1) {
3835 val |= CC_BANK_ONE;
3836 } else if (bank == 2) {
3837 val |= CC_DIAG | CC_BANK_ONE;
27c868c2 3838 } else {
51219358 3839 val &= ~CC_BANK_ONE;
27c868c2 3840 }
51219358 3841 AscSetChipControl(iop_base, val);
51219358
MW		 3842}
3843
3844static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
3845{
3846 AscSetBank(iop_base, 1);
3847 AscWriteChipIH(iop_base, ins_code);
3848 AscSetBank(iop_base, 0);
51219358
MW		 3849}
3850
3851static int AscStartChip(PortAddr iop_base)
3852{
3853 AscSetChipControl(iop_base, 0);
3854 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3855 return (0);
27c868c2 3856 }
51219358
MW		 3857 return (1);
3858}
27c868c2 3859
51219358
MW		 3860static int AscStopChip(PortAddr iop_base)
3861{
3862 uchar cc_val;
3863
3864 cc_val =
3865 AscGetChipControl(iop_base) &
3866 (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
3867 AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
3868 AscSetChipIH(iop_base, INS_HALT);
3869 AscSetChipIH(iop_base, INS_RFLAG_WTM);
3870 if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
3871 return (0);
27c868c2 3872 }
51219358
MW		 3873 return (1);
3874}
27c868c2 3875
51219358
MW		 3876static int AscIsChipHalted(PortAddr iop_base)
3877{
3878 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3879 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
3880 return (1);
27c868c2 3881 }
27c868c2 3882 }
51219358
MW		 3883 return (0);
3884}
27c868c2 3885
51219358
MW		 3886static int AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
3887{
3888 PortAddr iop_base;
3889 int i = 10;
3890
3891 iop_base = asc_dvc->iop_base;
3892 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
3893 && (i-- > 0)) {
3894 mdelay(100);
27c868c2 3895 }
51219358
MW		 3896 AscStopChip(iop_base);
3897 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
3898 udelay(60);
3899 AscSetChipIH(iop_base, INS_RFLAG_WTM);
3900 AscSetChipIH(iop_base, INS_HALT);
3901 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
3902 AscSetChipControl(iop_base, CC_HALT);
3903 mdelay(200);
3904 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
3905 AscSetChipStatus(iop_base, 0);
3906 return (AscIsChipHalted(iop_base));
3907}
27c868c2 3908
51219358
MW		 3909static int AscFindSignature(PortAddr iop_base)
3910{
3911 ushort sig_word;
27c868c2 3912
b352f923 3913 ASC_DBG(1, "AscGetChipSignatureByte(0x%x) 0x%x\n",
51219358
MW		 3914 iop_base, AscGetChipSignatureByte(iop_base));
3915 if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
b352f923 3916 ASC_DBG(1, "AscGetChipSignatureWord(0x%x) 0x%x\n",
51219358
MW		 3917 iop_base, AscGetChipSignatureWord(iop_base));
3918 sig_word = AscGetChipSignatureWord(iop_base);
3919 if ((sig_word == (ushort)ASC_1000_ID0W) ||
3920 (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
3921 return (1);
27c868c2 3922 }
27c868c2 3923 }
51219358 3924 return (0);
27c868c2
MW		 3925}
3926
51219358 3927static void AscEnableInterrupt(PortAddr iop_base)
1da177e4 3928{
51219358 3929 ushort cfg;
27c868c2 3930
51219358
MW		 3931 cfg = AscGetChipCfgLsw(iop_base);
3932 AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
51219358 3933}
27c868c2 3934
51219358
MW		 3935static void AscDisableInterrupt(PortAddr iop_base)
3936{
3937 ushort cfg;
27c868c2 3938
51219358
MW		 3939 cfg = AscGetChipCfgLsw(iop_base);
3940 AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
51219358 3941}
27c868c2 3942
51219358
MW		 3943static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
3944{
3945 unsigned char byte_data;
3946 unsigned short word_data;
27c868c2 3947
51219358
MW		 3948 if (isodd_word(addr)) {
3949 AscSetChipLramAddr(iop_base, addr - 1);
3950 word_data = AscGetChipLramData(iop_base);
3951 byte_data = (word_data >> 8) & 0xFF;
3952 } else {
3953 AscSetChipLramAddr(iop_base, addr);
3954 word_data = AscGetChipLramData(iop_base);
3955 byte_data = word_data & 0xFF;
3956 }
3957 return byte_data;
3958}
27c868c2 3959
51219358
MW		 3960static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
3961{
3962 ushort word_data;
27c868c2 3963
51219358
MW		 3964 AscSetChipLramAddr(iop_base, addr);
3965 word_data = AscGetChipLramData(iop_base);
3966 return (word_data);
3967}
27c868c2 3968
51219358
MW		 3969#if CC_VERY_LONG_SG_LIST
3970static ASC_DCNT AscReadLramDWord(PortAddr iop_base, ushort addr)
3971{
3972 ushort val_low, val_high;
3973 ASC_DCNT dword_data;
27c868c2 3974
51219358
MW		 3975 AscSetChipLramAddr(iop_base, addr);
3976 val_low = AscGetChipLramData(iop_base);
3977 val_high = AscGetChipLramData(iop_base);
3978 dword_data = ((ASC_DCNT) val_high << 16) | (ASC_DCNT) val_low;
3979 return (dword_data);
3980}
3981#endif /* CC_VERY_LONG_SG_LIST */
3982
3983static void
3984AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
3985{
3986 int i;
3987
3988 AscSetChipLramAddr(iop_base, s_addr);
3989 for (i = 0; i < words; i++) {
3990 AscSetChipLramData(iop_base, set_wval);
27c868c2 3991 }
51219358 3992}
1da177e4 3993
51219358
MW		 3994static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
3995{
3996 AscSetChipLramAddr(iop_base, addr);
3997 AscSetChipLramData(iop_base, word_val);
51219358
MW		 3998}
3999
4000static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
4001{
4002 ushort word_data;
4003
4004 if (isodd_word(addr)) {
4005 addr--;
4006 word_data = AscReadLramWord(iop_base, addr);
4007 word_data &= 0x00FF;
4008 word_data |= (((ushort)byte_val << 8) & 0xFF00);
4009 } else {
4010 word_data = AscReadLramWord(iop_base, addr);
4011 word_data &= 0xFF00;
4012 word_data |= ((ushort)byte_val & 0x00FF);
4013 }
4014 AscWriteLramWord(iop_base, addr, word_data);
1da177e4
LT		 4015}
4016
4017/*
51219358 4018 * Copy 2 bytes to LRAM.
1da177e4 4019 *
51219358
MW		 4020 * The source data is assumed to be in little-endian order in memory
4021 * and is maintained in little-endian order when written to LRAM.
1da177e4 4022 */
51219358 4023static void
989bb5f5
JSR		 4024AscMemWordCopyPtrToLram(PortAddr iop_base, ushort s_addr,
4025 const uchar *s_buffer, int words)
1da177e4 4026{
27c868c2 4027 int i;
27c868c2 4028
51219358
MW		 4029 AscSetChipLramAddr(iop_base, s_addr);
4030 for (i = 0; i < 2 * words; i += 2) {
4031 /*
4032 * On a little-endian system the second argument below
4033 * produces a little-endian ushort which is written to
4034 * LRAM in little-endian order. On a big-endian system
4035 * the second argument produces a big-endian ushort which
4036 * is "transparently" byte-swapped by outpw() and written
4037 * in little-endian order to LRAM.
4038 */
4039 outpw(iop_base + IOP_RAM_DATA,
4040 ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
4041 }
51219358 4042}
27c868c2 4043
51219358
MW		 4044/*
4045 * Copy 4 bytes to LRAM.
4046 *
4047 * The source data is assumed to be in little-endian order in memory
25985edc 4048 * and is maintained in little-endian order when written to LRAM.
51219358
MW		 4049 */
4050static void
4051AscMemDWordCopyPtrToLram(PortAddr iop_base,
4052 ushort s_addr, uchar *s_buffer, int dwords)
4053{
4054 int i;
27c868c2 4055
51219358
MW		 4056 AscSetChipLramAddr(iop_base, s_addr);
4057 for (i = 0; i < 4 * dwords; i += 4) {
4058 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */
4059 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */
4060 }
51219358 4061}
27c868c2 4062
51219358
MW		 4063/*
4064 * Copy 2 bytes from LRAM.
4065 *
4066 * The source data is assumed to be in little-endian order in LRAM
4067 * and is maintained in little-endian order when written to memory.
4068 */
4069static void
4070AscMemWordCopyPtrFromLram(PortAddr iop_base,
4071 ushort s_addr, uchar *d_buffer, int words)
4072{
4073 int i;
4074 ushort word;
27c868c2 4075
51219358
MW		 4076 AscSetChipLramAddr(iop_base, s_addr);
4077 for (i = 0; i < 2 * words; i += 2) {
4078 word = inpw(iop_base + IOP_RAM_DATA);
4079 d_buffer[i] = word & 0xff;
4080 d_buffer[i + 1] = (word >> 8) & 0xff;
27c868c2 4081 }
51219358 4082}
27c868c2 4083
51219358
MW		 4084static ASC_DCNT AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
4085{
4086 ASC_DCNT sum;
4087 int i;
27c868c2 4088
51219358
MW		 4089 sum = 0L;
4090 for (i = 0; i < words; i++, s_addr += 2) {
4091 sum += AscReadLramWord(iop_base, s_addr);
27c868c2 4092 }
51219358
MW		 4093 return (sum);
4094}
27c868c2 4095
51219358
MW		 4096static ushort AscInitLram(ASC_DVC_VAR *asc_dvc)
4097{
4098 uchar i;
4099 ushort s_addr;
4100 PortAddr iop_base;
4101 ushort warn_code;
27c868c2 4102
51219358
MW		 4103 iop_base = asc_dvc->iop_base;
4104 warn_code = 0;
4105 AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
4106 (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
4107 64) >> 1));
4108 i = ASC_MIN_ACTIVE_QNO;
4109 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
4110 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4111 (uchar)(i + 1));
4112 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4113 (uchar)(asc_dvc->max_total_qng));
4114 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4115 (uchar)i);
4116 i++;
4117 s_addr += ASC_QBLK_SIZE;
4118 for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
4119 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4120 (uchar)(i + 1));
4121 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4122 (uchar)(i - 1));
4123 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4124 (uchar)i);
27c868c2 4125 }
51219358
MW		 4126 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4127 (uchar)ASC_QLINK_END);
4128 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4129 (uchar)(asc_dvc->max_total_qng - 1));
4130 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4131 (uchar)asc_dvc->max_total_qng);
4132 i++;
4133 s_addr += ASC_QBLK_SIZE;
4134 for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
4135 i++, s_addr += ASC_QBLK_SIZE) {
4136 AscWriteLramByte(iop_base,
4137 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
4138 AscWriteLramByte(iop_base,
4139 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
4140 AscWriteLramByte(iop_base,
4141 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
27c868c2 4142 }
51219358 4143 return warn_code;
1da177e4
LT		 4144}
4145
51219358 4146static ASC_DCNT
989bb5f5
JSR		 4147AscLoadMicroCode(PortAddr iop_base, ushort s_addr,
4148 const uchar *mcode_buf, ushort mcode_size)
1da177e4 4149{
51219358
MW		 4150 ASC_DCNT chksum;
4151 ushort mcode_word_size;
4152 ushort mcode_chksum;
27c868c2 4153
51219358
MW		 4154 /* Write the microcode buffer starting at LRAM address 0. */
4155 mcode_word_size = (ushort)(mcode_size >> 1);
4156 AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
4157 AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
27c868c2 4158
51219358 4159 chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
b352f923 4160 ASC_DBG(1, "chksum 0x%lx\n", (ulong)chksum);
51219358
MW		 4161 mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
4162 (ushort)ASC_CODE_SEC_BEG,
4163 (ushort)((mcode_size -
4164 s_addr - (ushort)
4165 ASC_CODE_SEC_BEG) /
4166 2));
b352f923 4167 ASC_DBG(1, "mcode_chksum 0x%lx\n", (ulong)mcode_chksum);
51219358
MW		 4168 AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
4169 AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
b352f923 4170 return chksum;
51219358 4171}
27c868c2 4172
51219358
MW		 4173static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
4174{
4175 PortAddr iop_base;
4176 int i;
4177 ushort lram_addr;
4178
4179 iop_base = asc_dvc->iop_base;
4180 AscPutRiscVarFreeQHead(iop_base, 1);
4181 AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4182 AscPutVarFreeQHead(iop_base, 1);
4183 AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4184 AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
4185 (uchar)((int)asc_dvc->max_total_qng + 1));
4186 AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
4187 (uchar)((int)asc_dvc->max_total_qng + 2));
4188 AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
4189 asc_dvc->max_total_qng);
4190 AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
4191 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
4192 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
4193 AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
4194 AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
4195 AscPutQDoneInProgress(iop_base, 0);
4196 lram_addr = ASC_QADR_BEG;
4197 for (i = 0; i < 32; i++, lram_addr += 2) {
4198 AscWriteLramWord(iop_base, lram_addr, 0);
4199 }
4200}
4201
4202static ushort AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
4203{
4204 int i;
4205 ushort warn_code;
4206 PortAddr iop_base;
4207 ASC_PADDR phy_addr;
4208 ASC_DCNT phy_size;
d10fb2c7 4209 struct asc_board *board = asc_dvc_to_board(asc_dvc);
51219358
MW		 4210
4211 iop_base = asc_dvc->iop_base;
4212 warn_code = 0;
4213 for (i = 0; i <= ASC_MAX_TID; i++) {
4214 AscPutMCodeInitSDTRAtID(iop_base, i,
4215 asc_dvc->cfg->sdtr_period_offset[i]);
4216 }
4217
4218 AscInitQLinkVar(asc_dvc);
4219 AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
4220 asc_dvc->cfg->disc_enable);
4221 AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
4222 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
4223
d10fb2c7
MW		 4224 /* Ensure overrun buffer is aligned on an 8 byte boundary. */
4225 BUG_ON((unsigned long)asc_dvc->overrun_buf & 7);
4226 asc_dvc->overrun_dma = dma_map_single(board->dev, asc_dvc->overrun_buf,
4227 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
9a908c1a
HRK		 4228 if (dma_mapping_error(board->dev, asc_dvc->overrun_dma)) {
4229 warn_code = -ENOMEM;
4230 goto err_dma_map;
4231 }
d10fb2c7 4232 phy_addr = cpu_to_le32(asc_dvc->overrun_dma);
51219358
MW		 4233 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
4234 (uchar *)&phy_addr, 1);
d10fb2c7 4235 phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE);
51219358
MW		 4236 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
4237 (uchar *)&phy_size, 1);
4238
4239 asc_dvc->cfg->mcode_date =
4240 AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
4241 asc_dvc->cfg->mcode_version =
4242 AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
4243
4244 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
4245 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
4246 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
9a908c1a
HRK		 4247 warn_code = UW_ERR;
4248 goto err_mcode_start;
51219358
MW		 4249 }
4250 if (AscStartChip(iop_base) != 1) {
4251 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
9a908c1a
HRK		 4252 warn_code = UW_ERR;
4253 goto err_mcode_start;
51219358
MW		 4254 }
4255
4256 return warn_code;
9a908c1a
HRK		 4257
4258err_mcode_start:
4259 dma_unmap_single(board->dev, asc_dvc->overrun_dma,
4260 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4261err_dma_map:
4262 asc_dvc->overrun_dma = 0;
4263 return warn_code;
51219358
MW		 4264}
4265
4266static ushort AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
4267{
989bb5f5
JSR		 4268 const struct firmware *fw;
4269 const char fwname[] = "advansys/mcode.bin";
4270 int err;
4271 unsigned long chksum;
51219358
MW		 4272 ushort warn_code;
4273 PortAddr iop_base;
4274
4275 iop_base = asc_dvc->iop_base;
4276 warn_code = 0;
4277 if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
4278 !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
4279 AscResetChipAndScsiBus(asc_dvc);
4280 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4281 }
4282 asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
4283 if (asc_dvc->err_code != 0)
4284 return UW_ERR;
4285 if (!AscFindSignature(asc_dvc->iop_base)) {
4286 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
4287 return warn_code;
4288 }
4289 AscDisableInterrupt(iop_base);
4290 warn_code |= AscInitLram(asc_dvc);
4291 if (asc_dvc->err_code != 0)
4292 return UW_ERR;
989bb5f5
JSR		 4293
4294 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4295 if (err) {
4296 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4297 fwname, err);
cf747445 4298 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 4299 return err;
4300 }
4301 if (fw->size < 4) {
4302 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4303 fw->size, fwname);
4304 release_firmware(fw);
cf747445 4305 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 4306 return -EINVAL;
4307 }
4308 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4309 (fw->data[1] << 8) | fw->data[0];
4310 ASC_DBG(1, "_asc_mcode_chksum 0x%lx\n", (ulong)chksum);
4311 if (AscLoadMicroCode(iop_base, 0, &fw->data[4],
4312 fw->size - 4) != chksum) {
51219358 4313 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
989bb5f5 4314 release_firmware(fw);
51219358
MW		 4315 return warn_code;
4316 }
989bb5f5 4317 release_firmware(fw);
51219358 4318 warn_code |= AscInitMicroCodeVar(asc_dvc);
9a908c1a
HRK		 4319 if (!asc_dvc->overrun_dma)
4320 return warn_code;
51219358
MW		 4321 asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
4322 AscEnableInterrupt(iop_base);
4323 return warn_code;
4324}
4325
4326/*
4327 * Load the Microcode
4328 *
4329 * Write the microcode image to RISC memory starting at address 0.
4330 *
4331 * The microcode is stored compressed in the following format:
4332 *
4333 * 254 word (508 byte) table indexed by byte code followed
4334 * by the following byte codes:
4335 *
4336 * 1-Byte Code:
4337 * 00: Emit word 0 in table.
4338 * 01: Emit word 1 in table.
4339 * .
4340 * FD: Emit word 253 in table.
4341 *
4342 * Multi-Byte Code:
4343 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
4344 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
4345 *
4346 * Returns 0 or an error if the checksum doesn't match
4347 */
989bb5f5
JSR		 4348static int AdvLoadMicrocode(AdvPortAddr iop_base, const unsigned char *buf,
4349 int size, int memsize, int chksum)
51219358
MW		 4350{
4351 int i, j, end, len = 0;
4352 ADV_DCNT sum;
4353
4354 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4355
4356 for (i = 253 * 2; i < size; i++) {
4357 if (buf[i] == 0xff) {
4358 unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
4359 for (j = 0; j < buf[i + 1]; j++) {
4360 AdvWriteWordAutoIncLram(iop_base, word);
4361 len += 2;
4362 }
4363 i += 3;
4364 } else if (buf[i] == 0xfe) {
4365 unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
4366 AdvWriteWordAutoIncLram(iop_base, word);
4367 i += 2;
4368 len += 2;
4369 } else {
951b62c1 4370 unsigned int off = buf[i] * 2;
51219358
MW		 4371 unsigned short word = (buf[off + 1] << 8) | buf[off];
4372 AdvWriteWordAutoIncLram(iop_base, word);
4373 len += 2;
4374 }
4375 }
4376
4377 end = len;
4378
4379 while (len < memsize) {
4380 AdvWriteWordAutoIncLram(iop_base, 0);
4381 len += 2;
4382 }
4383
4384 /* Verify the microcode checksum. */
4385 sum = 0;
4386 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4387
4388 for (len = 0; len < end; len += 2) {
4389 sum += AdvReadWordAutoIncLram(iop_base);
4390 }
4391
4392 if (sum != chksum)
4393 return ASC_IERR_MCODE_CHKSUM;
4394
4395 return 0;
4396}
4397
51219358
MW		 4398static void AdvBuildCarrierFreelist(struct adv_dvc_var *asc_dvc)
4399{
4400 ADV_CARR_T *carrp;
4401 ADV_SDCNT buf_size;
4402 ADV_PADDR carr_paddr;
4403
51219358
MW		 4404 carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
4405 asc_dvc->carr_freelist = NULL;
4406 if (carrp == asc_dvc->carrier_buf) {
4407 buf_size = ADV_CARRIER_BUFSIZE;
4408 } else {
4409 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
4410 }
4411
4412 do {
4413 /* Get physical address of the carrier 'carrp'. */
fd625f47 4414 carr_paddr = cpu_to_le32(virt_to_bus(carrp));
51219358
MW		 4415
4416 buf_size -= sizeof(ADV_CARR_T);
4417
51219358
MW		 4418 carrp->carr_pa = carr_paddr;
4419 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
4420
4421 /*
4422 * Insert the carrier at the beginning of the freelist.
4423 */
4424 carrp->next_vpa =
4425 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
4426 asc_dvc->carr_freelist = carrp;
4427
4428 carrp++;
4429 } while (buf_size > 0);
4430}
4431
4432/*
4433 * Send an idle command to the chip and wait for completion.
4434 *
4435 * Command completion is polled for once per microsecond.
4436 *
4437 * The function can be called from anywhere including an interrupt handler.
4438 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
4439 * functions to prevent reentrancy.
4440 *
4441 * Return Values:
4442 * ADV_TRUE - command completed successfully
4443 * ADV_FALSE - command failed
4444 * ADV_ERROR - command timed out
4445 */
4446static int
4447AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
4448 ushort idle_cmd, ADV_DCNT idle_cmd_parameter)
4449{
4450 int result;
4451 ADV_DCNT i, j;
4452 AdvPortAddr iop_base;
4453
4454 iop_base = asc_dvc->iop_base;
4455
4456 /*
4457 * Clear the idle command status which is set by the microcode
4458 * to a non-zero value to indicate when the command is completed.
4459 * The non-zero result is one of the IDLE_CMD_STATUS_* values
4460 */
4461 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
4462
4463 /*
4464 * Write the idle command value after the idle command parameter
4465 * has been written to avoid a race condition. If the order is not
4466 * followed, the microcode may process the idle command before the
4467 * parameters have been written to LRAM.
4468 */
4469 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
4470 cpu_to_le32(idle_cmd_parameter));
4471 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
4472
4473 /*
4474 * Tickle the RISC to tell it to process the idle command.
4475 */
4476 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
4477 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
4478 /*
4479 * Clear the tickle value. In the ASC-3550 the RISC flag
4480 * command 'clr_tickle_b' does not work unless the host
4481 * value is cleared.
4482 */
4483 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
4484 }
4485
4486 /* Wait for up to 100 millisecond for the idle command to timeout. */
4487 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
4488 /* Poll once each microsecond for command completion. */
4489 for (j = 0; j < SCSI_US_PER_MSEC; j++) {
4490 AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
4491 result);
4492 if (result != 0)
4493 return result;
4494 udelay(1);
4495 }
4496 }
4497
4498 BUG(); /* The idle command should never timeout. */
4499 return ADV_ERROR;
4500}
4501
4502/*
4503 * Reset SCSI Bus and purge all outstanding requests.
4504 *
4505 * Return Value:
4506 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset.
4507 * ADV_FALSE(0) - Microcode command failed.
4508 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
4509 * may be hung which requires driver recovery.
4510 */
4511static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
4512{
4513 int status;
4514
4515 /*
4516 * Send the SCSI Bus Reset idle start idle command which asserts
4517 * the SCSI Bus Reset signal.
4518 */
4519 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
4520 if (status != ADV_TRUE) {
4521 return status;
4522 }
4523
4524 /*
4525 * Delay for the specified SCSI Bus Reset hold time.
4526 *
4527 * The hold time delay is done on the host because the RISC has no
4528 * microsecond accurate timer.
4529 */
4530 udelay(ASC_SCSI_RESET_HOLD_TIME_US);
4531
4532 /*
4533 * Send the SCSI Bus Reset end idle command which de-asserts
4534 * the SCSI Bus Reset signal and purges any pending requests.
4535 */
4536 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
4537 if (status != ADV_TRUE) {
4538 return status;
4539 }
4540
4541 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4542
4543 return status;
4544}
4545
4546/*
4547 * Initialize the ASC-3550.
4548 *
4549 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4550 *
4551 * For a non-fatal error return a warning code. If there are no warnings
4552 * then 0 is returned.
4553 *
4554 * Needed after initialization for error recovery.
4555 */
4556static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
4557{
989bb5f5
JSR		 4558 const struct firmware *fw;
4559 const char fwname[] = "advansys/3550.bin";
51219358
MW		 4560 AdvPortAddr iop_base;
4561 ushort warn_code;
4562 int begin_addr;
4563 int end_addr;
4564 ushort code_sum;
4565 int word;
4566 int i;
989bb5f5
JSR		 4567 int err;
4568 unsigned long chksum;
51219358
MW		 4569 ushort scsi_cfg1;
4570 uchar tid;
4571 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
4572 ushort wdtr_able = 0, sdtr_able, tagqng_able;
4573 uchar max_cmd[ADV_MAX_TID + 1];
4574
4575 /* If there is already an error, don't continue. */
4576 if (asc_dvc->err_code != 0)
4577 return ADV_ERROR;
4578
4579 /*
4580 * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
4581 */
4582 if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
4583 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
4584 return ADV_ERROR;
4585 }
4586
4587 warn_code = 0;
4588 iop_base = asc_dvc->iop_base;
4589
4590 /*
4591 * Save the RISC memory BIOS region before writing the microcode.
4592 * The BIOS may already be loaded and using its RISC LRAM region
4593 * so its region must be saved and restored.
4594 *
4595 * Note: This code makes the assumption, which is currently true,
4596 * that a chip reset does not clear RISC LRAM.
4597 */
4598 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4599 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4600 bios_mem[i]);
4601 }
4602
4603 /*
4604 * Save current per TID negotiated values.
4605 */
4606 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) {
4607 ushort bios_version, major, minor;
4608
4609 bios_version =
4610 bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2];
4611 major = (bios_version >> 12) & 0xF;
4612 minor = (bios_version >> 8) & 0xF;
4613 if (major < 3 || (major == 3 && minor == 1)) {
4614 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
4615 AdvReadWordLram(iop_base, 0x120, wdtr_able);
4616 } else {
4617 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4618 }
4619 }
4620 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4621 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
4622 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4623 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
4624 max_cmd[tid]);
4625 }
4626
989bb5f5
JSR		 4627 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4628 if (err) {
4629 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4630 fwname, err);
cf747445 4631 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 4632 return err;
4633 }
4634 if (fw->size < 4) {
4635 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4636 fw->size, fwname);
4637 release_firmware(fw);
cf747445 4638 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 4639 return -EINVAL;
4640 }
4641 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4642 (fw->data[1] << 8) | fw->data[0];
4643 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
4644 fw->size - 4, ADV_3550_MEMSIZE,
4645 chksum);
4646 release_firmware(fw);
51219358
MW		 4647 if (asc_dvc->err_code)
4648 return ADV_ERROR;
4649
4650 /*
4651 * Restore the RISC memory BIOS region.
4652 */
4653 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4654 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4655 bios_mem[i]);
4656 }
4657
4658 /*
4659 * Calculate and write the microcode code checksum to the microcode
4660 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
4661 */
4662 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
4663 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
4664 code_sum = 0;
4665 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
4666 for (word = begin_addr; word < end_addr; word += 2) {
4667 code_sum += AdvReadWordAutoIncLram(iop_base);
4668 }
4669 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
4670
4671 /*
4672 * Read and save microcode version and date.
4673 */
4674 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
4675 asc_dvc->cfg->mcode_date);
4676 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
4677 asc_dvc->cfg->mcode_version);
4678
4679 /*
4680 * Set the chip type to indicate the ASC3550.
4681 */
4682 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
4683
4684 /*
4685 * If the PCI Configuration Command Register "Parity Error Response
4686 * Control" Bit was clear (0), then set the microcode variable
4687 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
4688 * to ignore DMA parity errors.
4689 */
4690 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
4691 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4692 word |= CONTROL_FLAG_IGNORE_PERR;
4693 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4694 }
4695
4696 /*
4697 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
4698 * threshold of 128 bytes. This register is only accessible to the host.
4699 */
4700 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
4701 START_CTL_EMFU | READ_CMD_MRM);
4702
4703 /*
4704 * Microcode operating variables for WDTR, SDTR, and command tag
4705 * queuing will be set in slave_configure() based on what a
4706 * device reports it is capable of in Inquiry byte 7.
4707 *
4708 * If SCSI Bus Resets have been disabled, then directly set
4709 * SDTR and WDTR from the EEPROM configuration. This will allow
4710 * the BIOS and warm boot to work without a SCSI bus hang on
4711 * the Inquiry caused by host and target mismatched DTR values.
4712 * Without the SCSI Bus Reset, before an Inquiry a device can't
4713 * be assumed to be in Asynchronous, Narrow mode.
4714 */
4715 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
4716 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
4717 asc_dvc->wdtr_able);
4718 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
4719 asc_dvc->sdtr_able);
4720 }
4721
4722 /*
4723 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
4724 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
4725 * bitmask. These values determine the maximum SDTR speed negotiated
4726 * with a device.
4727 *
4728 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
4729 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
4730 * without determining here whether the device supports SDTR.
4731 *
4732 * 4-bit speed SDTR speed name
4733 * =========== ===============
4734 * 0000b (0x0) SDTR disabled
4735 * 0001b (0x1) 5 Mhz
4736 * 0010b (0x2) 10 Mhz
4737 * 0011b (0x3) 20 Mhz (Ultra)
4738 * 0100b (0x4) 40 Mhz (LVD/Ultra2)
4739 * 0101b (0x5) 80 Mhz (LVD2/Ultra3)
4740 * 0110b (0x6) Undefined
4741 * .
4742 * 1111b (0xF) Undefined
4743 */
4744 word = 0;
4745 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4746 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) {
4747 /* Set Ultra speed for TID 'tid'. */
4748 word |= (0x3 << (4 * (tid % 4)));
4749 } else {
4750 /* Set Fast speed for TID 'tid'. */
4751 word |= (0x2 << (4 * (tid % 4)));
4752 }
4753 if (tid == 3) { /* Check if done with sdtr_speed1. */
4754 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
4755 word = 0;
4756 } else if (tid == 7) { /* Check if done with sdtr_speed2. */
4757 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
4758 word = 0;
4759 } else if (tid == 11) { /* Check if done with sdtr_speed3. */
4760 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
4761 word = 0;
4762 } else if (tid == 15) { /* Check if done with sdtr_speed4. */
4763 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
4764 /* End of loop. */
4765 }
4766 }
4767
4768 /*
4769 * Set microcode operating variable for the disconnect per TID bitmask.
4770 */
4771 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
4772 asc_dvc->cfg->disc_enable);
4773
4774 /*
4775 * Set SCSI_CFG0 Microcode Default Value.
4776 *
4777 * The microcode will set the SCSI_CFG0 register using this value
4778 * after it is started below.
4779 */
4780 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
4781 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
4782 asc_dvc->chip_scsi_id);
4783
4784 /*
4785 * Determine SCSI_CFG1 Microcode Default Value.
4786 *
4787 * The microcode will set the SCSI_CFG1 register using this value
4788 * after it is started below.
4789 */
4790
4791 /* Read current SCSI_CFG1 Register value. */
4792 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
4793
4794 /*
4795 * If all three connectors are in use, return an error.
4796 */
4797 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
4798 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
4799 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
4800 return ADV_ERROR;
4801 }
4802
4803 /*
4804 * If the internal narrow cable is reversed all of the SCSI_CTRL
4805 * register signals will be set. Check for and return an error if
4806 * this condition is found.
4807 */
4808 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
4809 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
4810 return ADV_ERROR;
4811 }
4812
4813 /*
4814 * If this is a differential board and a single-ended device
4815 * is attached to one of the connectors, return an error.
4816 */
4817 if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) {
4818 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
4819 return ADV_ERROR;
4820 }
4821
4822 /*
4823 * If automatic termination control is enabled, then set the
4824 * termination value based on a table listed in a_condor.h.
4825 *
4826 * If manual termination was specified with an EEPROM setting
4827 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
4828 * is ready to be 'ored' into SCSI_CFG1.
4829 */
4830 if (asc_dvc->cfg->termination == 0) {
4831 /*
4832 * The software always controls termination by setting TERM_CTL_SEL.
4833 * If TERM_CTL_SEL were set to 0, the hardware would set termination.
4834 */
4835 asc_dvc->cfg->termination |= TERM_CTL_SEL;
4836
4837 switch (scsi_cfg1 & CABLE_DETECT) {
4838 /* TERM_CTL_H: on, TERM_CTL_L: on */
4839 case 0x3:
4840 case 0x7:
4841 case 0xB:
4842 case 0xD:
4843 case 0xE:
4844 case 0xF:
4845 asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
4846 break;
4847
4848 /* TERM_CTL_H: on, TERM_CTL_L: off */
4849 case 0x1:
4850 case 0x5:
4851 case 0x9:
4852 case 0xA:
4853 case 0xC:
4854 asc_dvc->cfg->termination |= TERM_CTL_H;
4855 break;
4856
4857 /* TERM_CTL_H: off, TERM_CTL_L: off */
4858 case 0x2:
4859 case 0x6:
4860 break;
4861 }
4862 }
4863
4864 /*
4865 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
4866 */
4867 scsi_cfg1 &= ~TERM_CTL;
4868
4869 /*
4870 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
4871 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
4872 * referenced, because the hardware internally inverts
4873 * the Termination High and Low bits if TERM_POL is set.
4874 */
4875 scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
4876
4877 /*
4878 * Set SCSI_CFG1 Microcode Default Value
4879 *
4880 * Set filter value and possibly modified termination control
4881 * bits in the Microcode SCSI_CFG1 Register Value.
4882 *
4883 * The microcode will set the SCSI_CFG1 register using this value
4884 * after it is started below.
4885 */
4886 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
4887 FLTR_DISABLE | scsi_cfg1);
4888
4889 /*
4890 * Set MEM_CFG Microcode Default Value
4891 *
4892 * The microcode will set the MEM_CFG register using this value
4893 * after it is started below.
4894 *
4895 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
4896 * are defined.
4897 *
4898 * ASC-3550 has 8KB internal memory.
4899 */
4900 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
4901 BIOS_EN | RAM_SZ_8KB);
4902
4903 /*
4904 * Set SEL_MASK Microcode Default Value
4905 *
4906 * The microcode will set the SEL_MASK register using this value
4907 * after it is started below.
4908 */
4909 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
4910 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
4911
4912 AdvBuildCarrierFreelist(asc_dvc);
4913
4914 /*
4915 * Set-up the Host->RISC Initiator Command Queue (ICQ).
4916 */
4917
4918 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
4919 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4920 return ADV_ERROR;
4921 }
4922 asc_dvc->carr_freelist = (ADV_CARR_T *)
4923 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
4924
4925 /*
4926 * The first command issued will be placed in the stopper carrier.
4927 */
4928 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
4929
4930 /*
4931 * Set RISC ICQ physical address start value.
4932 */
4933 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
4934
4935 /*
4936 * Set-up the RISC->Host Initiator Response Queue (IRQ).
4937 */
4938 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
4939 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4940 return ADV_ERROR;
4941 }
4942 asc_dvc->carr_freelist = (ADV_CARR_T *)
4943 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
4944
4945 /*
4946 * The first command completed by the RISC will be placed in
4947 * the stopper.
4948 *
4949 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
4950 * completed the RISC will set the ASC_RQ_STOPPER bit.
4951 */
4952 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
4953
4954 /*
4955 * Set RISC IRQ physical address start value.
4956 */
4957 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
4958 asc_dvc->carr_pending_cnt = 0;
4959
4960 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
4961 (ADV_INTR_ENABLE_HOST_INTR |
4962 ADV_INTR_ENABLE_GLOBAL_INTR));
4963
4964 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
4965 AdvWriteWordRegister(iop_base, IOPW_PC, word);
4966
4967 /* finally, finally, gentlemen, start your engine */
4968 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
4969
4970 /*
4971 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
4972 * Resets should be performed. The RISC has to be running
4973 * to issue a SCSI Bus Reset.
4974 */
4975 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
4976 /*
4977 * If the BIOS Signature is present in memory, restore the
4978 * BIOS Handshake Configuration Table and do not perform
4979 * a SCSI Bus Reset.
4980 */
4981 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
4982 0x55AA) {
4983 /*
4984 * Restore per TID negotiated values.
4985 */
4986 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4987 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4988 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
4989 tagqng_able);
4990 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4991 AdvWriteByteLram(iop_base,
4992 ASC_MC_NUMBER_OF_MAX_CMD + tid,
4993 max_cmd[tid]);
4994 }
4995 } else {
4996 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
4997 warn_code = ASC_WARN_BUSRESET_ERROR;
4998 }
4999 }
5000 }
5001
5002 return warn_code;
5003}
5004
5005/*
5006 * Initialize the ASC-38C0800.
5007 *
5008 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
5009 *
5010 * For a non-fatal error return a warning code. If there are no warnings
5011 * then 0 is returned.
5012 *
5013 * Needed after initialization for error recovery.
5014 */
5015static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
5016{
989bb5f5
JSR		 5017 const struct firmware *fw;
5018 const char fwname[] = "advansys/38C0800.bin";
51219358
MW		 5019 AdvPortAddr iop_base;
5020 ushort warn_code;
5021 int begin_addr;
5022 int end_addr;
5023 ushort code_sum;
5024 int word;
5025 int i;
989bb5f5
JSR		 5026 int err;
5027 unsigned long chksum;
51219358
MW		 5028 ushort scsi_cfg1;
5029 uchar byte;
5030 uchar tid;
5031 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
5032 ushort wdtr_able, sdtr_able, tagqng_able;
5033 uchar max_cmd[ADV_MAX_TID + 1];
5034
5035 /* If there is already an error, don't continue. */
5036 if (asc_dvc->err_code != 0)
5037 return ADV_ERROR;
5038
5039 /*
5040 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
5041 */
5042 if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) {
5043 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
5044 return ADV_ERROR;
5045 }
5046
5047 warn_code = 0;
5048 iop_base = asc_dvc->iop_base;
5049
5050 /*
5051 * Save the RISC memory BIOS region before writing the microcode.
5052 * The BIOS may already be loaded and using its RISC LRAM region
5053 * so its region must be saved and restored.
5054 *
5055 * Note: This code makes the assumption, which is currently true,
5056 * that a chip reset does not clear RISC LRAM.
5057 */
5058 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5059 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5060 bios_mem[i]);
5061 }
5062
5063 /*
5064 * Save current per TID negotiated values.
5065 */
5066 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5067 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5068 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5069 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5070 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5071 max_cmd[tid]);
5072 }
5073
5074 /*
5075 * RAM BIST (RAM Built-In Self Test)
5076 *
5077 * Address : I/O base + offset 0x38h register (byte).
5078 * Function: Bit 7-6(RW) : RAM mode
5079 * Normal Mode : 0x00
5080 * Pre-test Mode : 0x40
5081 * RAM Test Mode : 0x80
5082 * Bit 5 : unused
5083 * Bit 4(RO) : Done bit
5084 * Bit 3-0(RO) : Status
5085 * Host Error : 0x08
5086 * Int_RAM Error : 0x04
5087 * RISC Error : 0x02
5088 * SCSI Error : 0x01
5089 * No Error : 0x00
5090 *
5091 * Note: RAM BIST code should be put right here, before loading the
5092 * microcode and after saving the RISC memory BIOS region.
5093 */
5094
5095 /*
5096 * LRAM Pre-test
5097 *
5098 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
5099 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
5100 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
5101 * to NORMAL_MODE, return an error too.
5102 */
5103 for (i = 0; i < 2; i++) {
5104 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
5105 mdelay(10); /* Wait for 10ms before reading back. */
5106 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5107 if ((byte & RAM_TEST_DONE) == 0
5108 || (byte & 0x0F) != PRE_TEST_VALUE) {
5109 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5110 return ADV_ERROR;
5111 }
5112
5113 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5114 mdelay(10); /* Wait for 10ms before reading back. */
5115 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
5116 != NORMAL_VALUE) {
5117 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5118 return ADV_ERROR;
5119 }
5120 }
5121
5122 /*
5123 * LRAM Test - It takes about 1.5 ms to run through the test.
5124 *
5125 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
5126 * If Done bit not set or Status not 0, save register byte, set the
5127 * err_code, and return an error.
5128 */
5129 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
5130 mdelay(10); /* Wait for 10ms before checking status. */
5131
5132 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5133 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
5134 /* Get here if Done bit not set or Status not 0. */
5135 asc_dvc->bist_err_code = byte; /* for BIOS display message */
5136 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
5137 return ADV_ERROR;
5138 }
5139
5140 /* We need to reset back to normal mode after LRAM test passes. */
5141 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5142
989bb5f5
JSR		 5143 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5144 if (err) {
5145 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5146 fwname, err);
cf747445 5147 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 5148 return err;
5149 }
5150 if (fw->size < 4) {
5151 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5152 fw->size, fwname);
5153 release_firmware(fw);
cf747445 5154 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 5155 return -EINVAL;
5156 }
5157 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5158 (fw->data[1] << 8) | fw->data[0];
5159 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5160 fw->size - 4, ADV_38C0800_MEMSIZE,
5161 chksum);
5162 release_firmware(fw);
51219358
MW		 5163 if (asc_dvc->err_code)
5164 return ADV_ERROR;
5165
5166 /*
5167 * Restore the RISC memory BIOS region.
5168 */
5169 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5170 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5171 bios_mem[i]);
5172 }
5173
5174 /*
5175 * Calculate and write the microcode code checksum to the microcode
5176 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5177 */
5178 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5179 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5180 code_sum = 0;
5181 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5182 for (word = begin_addr; word < end_addr; word += 2) {
5183 code_sum += AdvReadWordAutoIncLram(iop_base);
5184 }
5185 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5186
5187 /*
5188 * Read microcode version and date.
5189 */
5190 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5191 asc_dvc->cfg->mcode_date);
5192 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5193 asc_dvc->cfg->mcode_version);
5194
5195 /*
5196 * Set the chip type to indicate the ASC38C0800.
5197 */
5198 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
5199
5200 /*
5201 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5202 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5203 * cable detection and then we are able to read C_DET[3:0].
5204 *
5205 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5206 * Microcode Default Value' section below.
5207 */
5208 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5209 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5210 scsi_cfg1 | DIS_TERM_DRV);
5211
5212 /*
5213 * If the PCI Configuration Command Register "Parity Error Response
5214 * Control" Bit was clear (0), then set the microcode variable
5215 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5216 * to ignore DMA parity errors.
5217 */
5218 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5219 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5220 word |= CONTROL_FLAG_IGNORE_PERR;
5221 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5222 }
5223
5224 /*
5225 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
5226 * bits for the default FIFO threshold.
5227 *
5228 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
5229 *
5230 * For DMA Errata #4 set the BC_THRESH_ENB bit.
5231 */
5232 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5233 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH |
5234 READ_CMD_MRM);
5235
5236 /*
5237 * Microcode operating variables for WDTR, SDTR, and command tag
5238 * queuing will be set in slave_configure() based on what a
5239 * device reports it is capable of in Inquiry byte 7.
5240 *
5241 * If SCSI Bus Resets have been disabled, then directly set
5242 * SDTR and WDTR from the EEPROM configuration. This will allow
5243 * the BIOS and warm boot to work without a SCSI bus hang on
5244 * the Inquiry caused by host and target mismatched DTR values.
5245 * Without the SCSI Bus Reset, before an Inquiry a device can't
5246 * be assumed to be in Asynchronous, Narrow mode.
5247 */
5248 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5249 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5250 asc_dvc->wdtr_able);
5251 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5252 asc_dvc->sdtr_able);
5253 }
5254
5255 /*
5256 * Set microcode operating variables for DISC and SDTR_SPEED1,
5257 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5258 * configuration values.
5259 *
5260 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5261 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5262 * without determining here whether the device supports SDTR.
5263 */
5264 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5265 asc_dvc->cfg->disc_enable);
5266 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5267 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5268 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5269 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5270
5271 /*
5272 * Set SCSI_CFG0 Microcode Default Value.
5273 *
5274 * The microcode will set the SCSI_CFG0 register using this value
5275 * after it is started below.
5276 */
5277 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5278 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5279 asc_dvc->chip_scsi_id);
5280
5281 /*
5282 * Determine SCSI_CFG1 Microcode Default Value.
5283 *
5284 * The microcode will set the SCSI_CFG1 register using this value
5285 * after it is started below.
5286 */
5287
5288 /* Read current SCSI_CFG1 Register value. */
5289 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5290
5291 /*
5292 * If the internal narrow cable is reversed all of the SCSI_CTRL
5293 * register signals will be set. Check for and return an error if
5294 * this condition is found.
5295 */
5296 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5297 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5298 return ADV_ERROR;
5299 }
5300
5301 /*
5302 * All kind of combinations of devices attached to one of four
5303 * connectors are acceptable except HVD device attached. For example,
5304 * LVD device can be attached to SE connector while SE device attached
5305 * to LVD connector. If LVD device attached to SE connector, it only
5306 * runs up to Ultra speed.
5307 *
5308 * If an HVD device is attached to one of LVD connectors, return an
5309 * error. However, there is no way to detect HVD device attached to
5310 * SE connectors.
5311 */
5312 if (scsi_cfg1 & HVD) {
5313 asc_dvc->err_code = ASC_IERR_HVD_DEVICE;
5314 return ADV_ERROR;
5315 }
5316
5317 /*
5318 * If either SE or LVD automatic termination control is enabled, then
5319 * set the termination value based on a table listed in a_condor.h.
5320 *
5321 * If manual termination was specified with an EEPROM setting then
5322 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready
5323 * to be 'ored' into SCSI_CFG1.
5324 */
5325 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5326 /* SE automatic termination control is enabled. */
5327 switch (scsi_cfg1 & C_DET_SE) {
5328 /* TERM_SE_HI: on, TERM_SE_LO: on */
5329 case 0x1:
5330 case 0x2:
5331 case 0x3:
5332 asc_dvc->cfg->termination |= TERM_SE;
5333 break;
5334
5335 /* TERM_SE_HI: on, TERM_SE_LO: off */
5336 case 0x0:
5337 asc_dvc->cfg->termination |= TERM_SE_HI;
5338 break;
5339 }
5340 }
5341
5342 if ((asc_dvc->cfg->termination & TERM_LVD) == 0) {
5343 /* LVD automatic termination control is enabled. */
5344 switch (scsi_cfg1 & C_DET_LVD) {
5345 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
5346 case 0x4:
5347 case 0x8:
5348 case 0xC:
5349 asc_dvc->cfg->termination |= TERM_LVD;
5350 break;
5351
5352 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
5353 case 0x0:
5354 break;
5355 }
5356 }
5357
5358 /*
5359 * Clear any set TERM_SE and TERM_LVD bits.
5360 */
5361 scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
5362
5363 /*
5364 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
5365 */
5366 scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
5367
5368 /*
5369 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE
5370 * bits and set possibly modified termination control bits in the
5371 * Microcode SCSI_CFG1 Register Value.
5372 */
5373 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
5374
5375 /*
5376 * Set SCSI_CFG1 Microcode Default Value
5377 *
5378 * Set possibly modified termination control and reset DIS_TERM_DRV
5379 * bits in the Microcode SCSI_CFG1 Register Value.
5380 *
5381 * The microcode will set the SCSI_CFG1 register using this value
5382 * after it is started below.
5383 */
5384 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5385
5386 /*
5387 * Set MEM_CFG Microcode Default Value
5388 *
5389 * The microcode will set the MEM_CFG register using this value
5390 * after it is started below.
5391 *
5392 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5393 * are defined.
5394 *
5395 * ASC-38C0800 has 16KB internal memory.
5396 */
5397 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5398 BIOS_EN | RAM_SZ_16KB);
5399
5400 /*
5401 * Set SEL_MASK Microcode Default Value
5402 *
5403 * The microcode will set the SEL_MASK register using this value
5404 * after it is started below.
5405 */
5406 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5407 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5408
5409 AdvBuildCarrierFreelist(asc_dvc);
5410
5411 /*
5412 * Set-up the Host->RISC Initiator Command Queue (ICQ).
5413 */
5414
5415 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
5416 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5417 return ADV_ERROR;
5418 }
5419 asc_dvc->carr_freelist = (ADV_CARR_T *)
5420 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
5421
5422 /*
5423 * The first command issued will be placed in the stopper carrier.
5424 */
5425 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
5426
5427 /*
5428 * Set RISC ICQ physical address start value.
5429 * carr_pa is LE, must be native before write
5430 */
5431 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5432
5433 /*
5434 * Set-up the RISC->Host Initiator Response Queue (IRQ).
5435 */
5436 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
5437 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5438 return ADV_ERROR;
5439 }
5440 asc_dvc->carr_freelist = (ADV_CARR_T *)
5441 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
5442
5443 /*
5444 * The first command completed by the RISC will be placed in
5445 * the stopper.
5446 *
5447 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
5448 * completed the RISC will set the ASC_RQ_STOPPER bit.
5449 */
5450 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
5451
5452 /*
5453 * Set RISC IRQ physical address start value.
5454 *
5455 * carr_pa is LE, must be native before write *
5456 */
5457 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5458 asc_dvc->carr_pending_cnt = 0;
5459
5460 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5461 (ADV_INTR_ENABLE_HOST_INTR |
5462 ADV_INTR_ENABLE_GLOBAL_INTR));
5463
5464 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5465 AdvWriteWordRegister(iop_base, IOPW_PC, word);
5466
5467 /* finally, finally, gentlemen, start your engine */
5468 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5469
5470 /*
5471 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5472 * Resets should be performed. The RISC has to be running
5473 * to issue a SCSI Bus Reset.
5474 */
5475 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5476 /*
5477 * If the BIOS Signature is present in memory, restore the
5478 * BIOS Handshake Configuration Table and do not perform
5479 * a SCSI Bus Reset.
5480 */
5481 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5482 0x55AA) {
5483 /*
5484 * Restore per TID negotiated values.
5485 */
5486 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5487 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5488 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5489 tagqng_able);
5490 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5491 AdvWriteByteLram(iop_base,
5492 ASC_MC_NUMBER_OF_MAX_CMD + tid,
5493 max_cmd[tid]);
5494 }
5495 } else {
5496 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5497 warn_code = ASC_WARN_BUSRESET_ERROR;
5498 }
5499 }
5500 }
5501
5502 return warn_code;
5503}
5504
5505/*
5506 * Initialize the ASC-38C1600.
5507 *
5508 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
5509 *
5510 * For a non-fatal error return a warning code. If there are no warnings
5511 * then 0 is returned.
5512 *
5513 * Needed after initialization for error recovery.
5514 */
5515static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
5516{
989bb5f5
JSR		 5517 const struct firmware *fw;
5518 const char fwname[] = "advansys/38C1600.bin";
51219358
MW		 5519 AdvPortAddr iop_base;
5520 ushort warn_code;
5521 int begin_addr;
5522 int end_addr;
5523 ushort code_sum;
5524 long word;
5525 int i;
989bb5f5
JSR		 5526 int err;
5527 unsigned long chksum;
51219358
MW		 5528 ushort scsi_cfg1;
5529 uchar byte;
5530 uchar tid;
5531 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
5532 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
5533 uchar max_cmd[ASC_MAX_TID + 1];
5534
5535 /* If there is already an error, don't continue. */
5536 if (asc_dvc->err_code != 0) {
5537 return ADV_ERROR;
5538 }
5539
5540 /*
5541 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
5542 */
5543 if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
5544 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
5545 return ADV_ERROR;
5546 }
5547
5548 warn_code = 0;
5549 iop_base = asc_dvc->iop_base;
5550
5551 /*
5552 * Save the RISC memory BIOS region before writing the microcode.
5553 * The BIOS may already be loaded and using its RISC LRAM region
5554 * so its region must be saved and restored.
5555 *
5556 * Note: This code makes the assumption, which is currently true,
5557 * that a chip reset does not clear RISC LRAM.
5558 */
5559 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5560 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5561 bios_mem[i]);
5562 }
5563
5564 /*
5565 * Save current per TID negotiated values.
5566 */
5567 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5568 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5569 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5570 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5571 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
5572 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5573 max_cmd[tid]);
5574 }
5575
5576 /*
5577 * RAM BIST (Built-In Self Test)
5578 *
5579 * Address : I/O base + offset 0x38h register (byte).
5580 * Function: Bit 7-6(RW) : RAM mode
5581 * Normal Mode : 0x00
5582 * Pre-test Mode : 0x40
5583 * RAM Test Mode : 0x80
5584 * Bit 5 : unused
5585 * Bit 4(RO) : Done bit
5586 * Bit 3-0(RO) : Status
5587 * Host Error : 0x08
5588 * Int_RAM Error : 0x04
5589 * RISC Error : 0x02
5590 * SCSI Error : 0x01
5591 * No Error : 0x00
5592 *
5593 * Note: RAM BIST code should be put right here, before loading the
5594 * microcode and after saving the RISC memory BIOS region.
5595 */
5596
5597 /*
5598 * LRAM Pre-test
5599 *
5600 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
5601 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
5602 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
5603 * to NORMAL_MODE, return an error too.
5604 */
5605 for (i = 0; i < 2; i++) {
5606 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
5607 mdelay(10); /* Wait for 10ms before reading back. */
5608 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5609 if ((byte & RAM_TEST_DONE) == 0
5610 || (byte & 0x0F) != PRE_TEST_VALUE) {
5611 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5612 return ADV_ERROR;
5613 }
5614
5615 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5616 mdelay(10); /* Wait for 10ms before reading back. */
5617 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
5618 != NORMAL_VALUE) {
5619 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5620 return ADV_ERROR;
5621 }
5622 }
5623
5624 /*
5625 * LRAM Test - It takes about 1.5 ms to run through the test.
5626 *
5627 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
5628 * If Done bit not set or Status not 0, save register byte, set the
5629 * err_code, and return an error.
5630 */
5631 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
5632 mdelay(10); /* Wait for 10ms before checking status. */
5633
5634 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5635 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
5636 /* Get here if Done bit not set or Status not 0. */
5637 asc_dvc->bist_err_code = byte; /* for BIOS display message */
5638 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
5639 return ADV_ERROR;
5640 }
5641
5642 /* We need to reset back to normal mode after LRAM test passes. */
5643 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5644
989bb5f5
JSR		 5645 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5646 if (err) {
5647 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5648 fwname, err);
cf747445 5649 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 5650 return err;
5651 }
5652 if (fw->size < 4) {
5653 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5654 fw->size, fwname);
5655 release_firmware(fw);
cf747445 5656 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 5657 return -EINVAL;
5658 }
5659 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5660 (fw->data[1] << 8) | fw->data[0];
5661 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5662 fw->size - 4, ADV_38C1600_MEMSIZE,
5663 chksum);
5664 release_firmware(fw);
51219358
MW		 5665 if (asc_dvc->err_code)
5666 return ADV_ERROR;
5667
5668 /*
5669 * Restore the RISC memory BIOS region.
5670 */
5671 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5672 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5673 bios_mem[i]);
5674 }
5675
5676 /*
5677 * Calculate and write the microcode code checksum to the microcode
5678 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5679 */
5680 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5681 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5682 code_sum = 0;
5683 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5684 for (word = begin_addr; word < end_addr; word += 2) {
5685 code_sum += AdvReadWordAutoIncLram(iop_base);
5686 }
5687 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5688
5689 /*
5690 * Read microcode version and date.
5691 */
5692 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5693 asc_dvc->cfg->mcode_date);
5694 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5695 asc_dvc->cfg->mcode_version);
5696
5697 /*
5698 * Set the chip type to indicate the ASC38C1600.
5699 */
5700 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
5701
5702 /*
5703 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5704 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5705 * cable detection and then we are able to read C_DET[3:0].
5706 *
5707 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5708 * Microcode Default Value' section below.
5709 */
5710 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5711 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5712 scsi_cfg1 | DIS_TERM_DRV);
5713
5714 /*
5715 * If the PCI Configuration Command Register "Parity Error Response
5716 * Control" Bit was clear (0), then set the microcode variable
5717 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5718 * to ignore DMA parity errors.
5719 */
5720 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5721 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5722 word |= CONTROL_FLAG_IGNORE_PERR;
5723 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5724 }
5725
5726 /*
5727 * If the BIOS control flag AIPP (Asynchronous Information
5728 * Phase Protection) disable bit is not set, then set the firmware
5729 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
5730 * AIPP checking and encoding.
5731 */
5732 if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
5733 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5734 word |= CONTROL_FLAG_ENABLE_AIPP;
5735 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5736 }
5737
5738 /*
5739 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
5740 * and START_CTL_TH [3:2].
5741 */
5742 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5743 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
5744
5745 /*
5746 * Microcode operating variables for WDTR, SDTR, and command tag
5747 * queuing will be set in slave_configure() based on what a
5748 * device reports it is capable of in Inquiry byte 7.
5749 *
5750 * If SCSI Bus Resets have been disabled, then directly set
5751 * SDTR and WDTR from the EEPROM configuration. This will allow
5752 * the BIOS and warm boot to work without a SCSI bus hang on
5753 * the Inquiry caused by host and target mismatched DTR values.
5754 * Without the SCSI Bus Reset, before an Inquiry a device can't
5755 * be assumed to be in Asynchronous, Narrow mode.
5756 */
5757 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5758 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5759 asc_dvc->wdtr_able);
5760 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5761 asc_dvc->sdtr_able);
5762 }
5763
5764 /*
5765 * Set microcode operating variables for DISC and SDTR_SPEED1,
5766 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5767 * configuration values.
5768 *
5769 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5770 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5771 * without determining here whether the device supports SDTR.
5772 */
5773 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5774 asc_dvc->cfg->disc_enable);
5775 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5776 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5777 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5778 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5779
5780 /*
5781 * Set SCSI_CFG0 Microcode Default Value.
5782 *
5783 * The microcode will set the SCSI_CFG0 register using this value
5784 * after it is started below.
5785 */
5786 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5787 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5788 asc_dvc->chip_scsi_id);
5789
5790 /*
5791 * Calculate SCSI_CFG1 Microcode Default Value.
5792 *
5793 * The microcode will set the SCSI_CFG1 register using this value
5794 * after it is started below.
5795 *
5796 * Each ASC-38C1600 function has only two cable detect bits.
5797 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
5798 */
5799 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5800
5801 /*
5802 * If the cable is reversed all of the SCSI_CTRL register signals
5803 * will be set. Check for and return an error if this condition is
5804 * found.
5805 */
5806 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5807 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5808 return ADV_ERROR;
5809 }
5810
5811 /*
5812 * Each ASC-38C1600 function has two connectors. Only an HVD device
5813 * can not be connected to either connector. An LVD device or SE device
5814 * may be connected to either connecor. If an SE device is connected,
5815 * then at most Ultra speed (20 Mhz) can be used on both connectors.
5816 *
5817 * If an HVD device is attached, return an error.
5818 */
5819 if (scsi_cfg1 & HVD) {
5820 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
5821 return ADV_ERROR;
5822 }
5823
5824 /*
5825 * Each function in the ASC-38C1600 uses only the SE cable detect and
5826 * termination because there are two connectors for each function. Each
5827 * function may use either LVD or SE mode. Corresponding the SE automatic
5828 * termination control EEPROM bits are used for each function. Each
5829 * function has its own EEPROM. If SE automatic control is enabled for
5830 * the function, then set the termination value based on a table listed
5831 * in a_condor.h.
5832 *
5833 * If manual termination is specified in the EEPROM for the function,
5834 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
5835 * ready to be 'ored' into SCSI_CFG1.
5836 */
5837 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5838 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
5839 /* SE automatic termination control is enabled. */
5840 switch (scsi_cfg1 & C_DET_SE) {
5841 /* TERM_SE_HI: on, TERM_SE_LO: on */
5842 case 0x1:
5843 case 0x2:
5844 case 0x3:
5845 asc_dvc->cfg->termination |= TERM_SE;
5846 break;
5847
5848 case 0x0:
5849 if (PCI_FUNC(pdev->devfn) == 0) {
5850 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
5851 } else {
5852 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
5853 asc_dvc->cfg->termination |= TERM_SE_HI;
5854 }
5855 break;
5856 }
5857 }
5858
5859 /*
5860 * Clear any set TERM_SE bits.
5861 */
5862 scsi_cfg1 &= ~TERM_SE;
5863
5864 /*
5865 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
5866 */
5867 scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
5868
5869 /*
5870 * Clear Big Endian and Terminator Polarity bits and set possibly
5871 * modified termination control bits in the Microcode SCSI_CFG1
5872 * Register Value.
5873 *
5874 * Big Endian bit is not used even on big endian machines.
5875 */
5876 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
5877
5878 /*
5879 * Set SCSI_CFG1 Microcode Default Value
5880 *
5881 * Set possibly modified termination control bits in the Microcode
5882 * SCSI_CFG1 Register Value.
5883 *
5884 * The microcode will set the SCSI_CFG1 register using this value
5885 * after it is started below.
5886 */
5887 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5888
5889 /*
5890 * Set MEM_CFG Microcode Default Value
5891 *
5892 * The microcode will set the MEM_CFG register using this value
5893 * after it is started below.
5894 *
5895 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5896 * are defined.
5897 *
5898 * ASC-38C1600 has 32KB internal memory.
5899 *
5900 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
5901 * out a special 16K Adv Library and Microcode version. After the issue
5902 * resolved, we should turn back to the 32K support. Both a_condor.h and
5903 * mcode.sas files also need to be updated.
5904 *
5905 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5906 * BIOS_EN | RAM_SZ_32KB);
5907 */
5908 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5909 BIOS_EN | RAM_SZ_16KB);
5910
5911 /*
5912 * Set SEL_MASK Microcode Default Value
5913 *
5914 * The microcode will set the SEL_MASK register using this value
5915 * after it is started below.
5916 */
5917 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5918 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5919
5920 AdvBuildCarrierFreelist(asc_dvc);
5921
5922 /*
5923 * Set-up the Host->RISC Initiator Command Queue (ICQ).
5924 */
5925 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
5926 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5927 return ADV_ERROR;
5928 }
5929 asc_dvc->carr_freelist = (ADV_CARR_T *)
5930 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
5931
5932 /*
5933 * The first command issued will be placed in the stopper carrier.
5934 */
5935 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
5936
5937 /*
5938 * Set RISC ICQ physical address start value. Initialize the
5939 * COMMA register to the same value otherwise the RISC will
5940 * prematurely detect a command is available.
5941 */
5942 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5943 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
5944 le32_to_cpu(asc_dvc->icq_sp->carr_pa));
5945
5946 /*
5947 * Set-up the RISC->Host Initiator Response Queue (IRQ).
5948 */
5949 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
5950 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5951 return ADV_ERROR;
5952 }
5953 asc_dvc->carr_freelist = (ADV_CARR_T *)
5954 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
5955
5956 /*
5957 * The first command completed by the RISC will be placed in
5958 * the stopper.
5959 *
5960 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
5961 * completed the RISC will set the ASC_RQ_STOPPER bit.
5962 */
5963 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
5964
5965 /*
5966 * Set RISC IRQ physical address start value.
5967 */
5968 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5969 asc_dvc->carr_pending_cnt = 0;
5970
5971 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5972 (ADV_INTR_ENABLE_HOST_INTR |
5973 ADV_INTR_ENABLE_GLOBAL_INTR));
5974 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5975 AdvWriteWordRegister(iop_base, IOPW_PC, word);
5976
5977 /* finally, finally, gentlemen, start your engine */
5978 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5979
5980 /*
5981 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5982 * Resets should be performed. The RISC has to be running
5983 * to issue a SCSI Bus Reset.
5984 */
5985 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5986 /*
5987 * If the BIOS Signature is present in memory, restore the
5988 * per TID microcode operating variables.
5989 */
5990 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5991 0x55AA) {
5992 /*
5993 * Restore per TID negotiated values.
5994 */
5995 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5996 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5997 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5998 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5999 tagqng_able);
6000 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
6001 AdvWriteByteLram(iop_base,
6002 ASC_MC_NUMBER_OF_MAX_CMD + tid,
6003 max_cmd[tid]);
6004 }
6005 } else {
6006 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
6007 warn_code = ASC_WARN_BUSRESET_ERROR;
6008 }
6009 }
6010 }
6011
6012 return warn_code;
6013}
6014
6015/*
6016 * Reset chip and SCSI Bus.
6017 *
6018 * Return Value:
6019 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
6020 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
6021 */
6022static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
6023{
6024 int status;
6025 ushort wdtr_able, sdtr_able, tagqng_able;
6026 ushort ppr_able = 0;
6027 uchar tid, max_cmd[ADV_MAX_TID + 1];
6028 AdvPortAddr iop_base;
6029 ushort bios_sig;
6030
6031 iop_base = asc_dvc->iop_base;
6032
6033 /*
6034 * Save current per TID negotiated values.
6035 */
6036 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
6037 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
6038 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
6039 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
6040 }
6041 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
6042 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
6043 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
6044 max_cmd[tid]);
6045 }
6046
6047 /*
6048 * Force the AdvInitAsc3550/38C0800Driver() function to
6049 * perform a SCSI Bus Reset by clearing the BIOS signature word.
6050 * The initialization functions assumes a SCSI Bus Reset is not
6051 * needed if the BIOS signature word is present.
6052 */
6053 AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
6054 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
6055
6056 /*
6057 * Stop chip and reset it.
6058 */
6059 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
6060 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
6061 mdelay(100);
6062 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
6063 ADV_CTRL_REG_CMD_WR_IO_REG);
6064
6065 /*
6066 * Reset Adv Library error code, if any, and try
6067 * re-initializing the chip.
6068 */
6069 asc_dvc->err_code = 0;
6070 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
6071 status = AdvInitAsc38C1600Driver(asc_dvc);
6072 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
6073 status = AdvInitAsc38C0800Driver(asc_dvc);
6074 } else {
6075 status = AdvInitAsc3550Driver(asc_dvc);
6076 }
6077
6078 /* Translate initialization return value to status value. */
6079 if (status == 0) {
6080 status = ADV_TRUE;
6081 } else {
6082 status = ADV_FALSE;
6083 }
6084
6085 /*
6086 * Restore the BIOS signature word.
6087 */
6088 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
6089
6090 /*
6091 * Restore per TID negotiated values.
6092 */
6093 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
6094 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
6095 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
6096 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
6097 }
6098 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
6099 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
6100 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
6101 max_cmd[tid]);
6102 }
6103
6104 return status;
6105}
6106
6107/*
6108 * adv_async_callback() - Adv Library asynchronous event callback function.
6109 */
6110static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
6111{
6112 switch (code) {
6113 case ADV_ASYNC_SCSI_BUS_RESET_DET:
6114 /*
6115 * The firmware detected a SCSI Bus reset.
6116 */
b352f923 6117 ASC_DBG(0, "ADV_ASYNC_SCSI_BUS_RESET_DET\n");
51219358
MW		 6118 break;
6119
6120 case ADV_ASYNC_RDMA_FAILURE:
6121 /*
6122 * Handle RDMA failure by resetting the SCSI Bus and
6123 * possibly the chip if it is unresponsive. Log the error
6124 * with a unique code.
6125 */
b352f923 6126 ASC_DBG(0, "ADV_ASYNC_RDMA_FAILURE\n");
51219358
MW		 6127 AdvResetChipAndSB(adv_dvc_varp);
6128 break;
6129
6130 case ADV_HOST_SCSI_BUS_RESET:
6131 /*
6132 * Host generated SCSI bus reset occurred.
6133 */
b352f923 6134 ASC_DBG(0, "ADV_HOST_SCSI_BUS_RESET\n");
51219358
MW		 6135 break;
6136
6137 default:
b352f923 6138 ASC_DBG(0, "unknown code 0x%x\n", code);
51219358
MW		 6139 break;
6140 }
6141}
6142
6143/*
6144 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
6145 *
6146 * Callback function for the Wide SCSI Adv Library.
6147 */
6148static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
6149{
d2411495 6150 struct asc_board *boardp;
51219358
MW		 6151 adv_req_t *reqp;
6152 adv_sgblk_t *sgblkp;
6153 struct scsi_cmnd *scp;
6154 struct Scsi_Host *shost;
6155 ADV_DCNT resid_cnt;
6156
b352f923 6157 ASC_DBG(1, "adv_dvc_varp 0x%lx, scsiqp 0x%lx\n",
51219358
MW		 6158 (ulong)adv_dvc_varp, (ulong)scsiqp);
6159 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
6160
6161 /*
6162 * Get the adv_req_t structure for the command that has been
6163 * completed. The adv_req_t structure actually contains the
6164 * completed ADV_SCSI_REQ_Q structure.
6165 */
6166 reqp = (adv_req_t *)ADV_U32_TO_VADDR(scsiqp->srb_ptr);
b352f923 6167 ASC_DBG(1, "reqp 0x%lx\n", (ulong)reqp);
51219358
MW		 6168 if (reqp == NULL) {
6169 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
6170 return;
6171 }
6172
6173 /*
6174 * Get the struct scsi_cmnd structure and Scsi_Host structure for the
6175 * command that has been completed.
6176 *
6177 * Note: The adv_req_t request structure and adv_sgblk_t structure,
6178 * if any, are dropped, because a board structure pointer can not be
6179 * determined.
6180 */
6181 scp = reqp->cmndp;
b352f923 6182 ASC_DBG(1, "scp 0x%p\n", scp);
51219358
MW		 6183 if (scp == NULL) {
6184 ASC_PRINT
6185 ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
6186 return;
6187 }
6188 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
6189
6190 shost = scp->device->host;
6191 ASC_STATS(shost, callback);
b352f923 6192 ASC_DBG(1, "shost 0x%p\n", shost);
51219358 6193
d2411495 6194 boardp = shost_priv(shost);
51219358
MW		 6195 BUG_ON(adv_dvc_varp != &boardp->dvc_var.adv_dvc_var);
6196
6197 /*
6198 * 'done_status' contains the command's ending status.
6199 */
6200 switch (scsiqp->done_status) {
6201 case QD_NO_ERROR:
b352f923 6202 ASC_DBG(2, "QD_NO_ERROR\n");
51219358
MW		 6203 scp->result = 0;
6204
6205 /*
6206 * Check for an underrun condition.
6207 *
6208 * If there was no error and an underrun condition, then
6209 * then return the number of underrun bytes.
6210 */
6211 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
52c334e9
MW		 6212 if (scsi_bufflen(scp) != 0 && resid_cnt != 0 &&
6213 resid_cnt <= scsi_bufflen(scp)) {
b352f923 6214 ASC_DBG(1, "underrun condition %lu bytes\n",
51219358 6215 (ulong)resid_cnt);
52c334e9 6216 scsi_set_resid(scp, resid_cnt);
51219358
MW		 6217 }
6218 break;
6219
6220 case QD_WITH_ERROR:
b352f923 6221 ASC_DBG(2, "QD_WITH_ERROR\n");
51219358
MW		 6222 switch (scsiqp->host_status) {
6223 case QHSTA_NO_ERROR:
6224 if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
b352f923 6225 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
51219358 6226 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
b80ca4f7 6227 SCSI_SENSE_BUFFERSIZE);
51219358
MW		 6228 /*
6229 * Note: The 'status_byte()' macro used by
6230 * target drivers defined in scsi.h shifts the
6231 * status byte returned by host drivers right
6232 * by 1 bit. This is why target drivers also
6233 * use right shifted status byte definitions.
6234 * For instance target drivers use
6235 * CHECK_CONDITION, defined to 0x1, instead of
6236 * the SCSI defined check condition value of
6237 * 0x2. Host drivers are supposed to return
6238 * the status byte as it is defined by SCSI.
6239 */
6240 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
6241 STATUS_BYTE(scsiqp->scsi_status);
6242 } else {
6243 scp->result = STATUS_BYTE(scsiqp->scsi_status);
6244 }
6245 break;
6246
6247 default:
6248 /* Some other QHSTA error occurred. */
b352f923 6249 ASC_DBG(1, "host_status 0x%x\n", scsiqp->host_status);
51219358
MW		 6250 scp->result = HOST_BYTE(DID_BAD_TARGET);
6251 break;
6252 }
6253 break;
6254
6255 case QD_ABORTED_BY_HOST:
b352f923 6256 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
51219358
MW		 6257 scp->result =
6258 HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
6259 break;
6260
6261 default:
b352f923 6262 ASC_DBG(1, "done_status 0x%x\n", scsiqp->done_status);
51219358
MW		 6263 scp->result =
6264 HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
6265 break;
6266 }
6267
6268 /*
6269 * If the 'init_tidmask' bit isn't already set for the target and the
6270 * current request finished normally, then set the bit for the target
6271 * to indicate that a device is present.
6272 */
6273 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
6274 scsiqp->done_status == QD_NO_ERROR &&
6275 scsiqp->host_status == QHSTA_NO_ERROR) {
6276 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
6277 }
6278
6279 asc_scsi_done(scp);
6280
6281 /*
6282 * Free all 'adv_sgblk_t' structures allocated for the request.
6283 */
6284 while ((sgblkp = reqp->sgblkp) != NULL) {
6285 /* Remove 'sgblkp' from the request list. */
6286 reqp->sgblkp = sgblkp->next_sgblkp;
6287
6288 /* Add 'sgblkp' to the board free list. */
6289 sgblkp->next_sgblkp = boardp->adv_sgblkp;
6290 boardp->adv_sgblkp = sgblkp;
6291 }
6292
6293 /*
6294 * Free the adv_req_t structure used with the command by adding
6295 * it back to the board free list.
6296 */
6297 reqp->next_reqp = boardp->adv_reqp;
6298 boardp->adv_reqp = reqp;
6299
b352f923 6300 ASC_DBG(1, "done\n");
51219358
MW		 6301}
6302
6303/*
6304 * Adv Library Interrupt Service Routine
6305 *
6306 * This function is called by a driver's interrupt service routine.
6307 * The function disables and re-enables interrupts.
6308 *
6309 * When a microcode idle command is completed, the ADV_DVC_VAR
6310 * 'idle_cmd_done' field is set to ADV_TRUE.
6311 *
6312 * Note: AdvISR() can be called when interrupts are disabled or even
6313 * when there is no hardware interrupt condition present. It will
6314 * always check for completed idle commands and microcode requests.
6315 * This is an important feature that shouldn't be changed because it
6316 * allows commands to be completed from polling mode loops.
6317 *
6318 * Return:
6319 * ADV_TRUE(1) - interrupt was pending
6320 * ADV_FALSE(0) - no interrupt was pending
6321 */
6322static int AdvISR(ADV_DVC_VAR *asc_dvc)
6323{
6324 AdvPortAddr iop_base;
6325 uchar int_stat;
6326 ushort target_bit;
6327 ADV_CARR_T *free_carrp;
6328 ADV_VADDR irq_next_vpa;
6329 ADV_SCSI_REQ_Q *scsiq;
6330
6331 iop_base = asc_dvc->iop_base;
6332
6333 /* Reading the register clears the interrupt. */
6334 int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
6335
6336 if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
6337 ADV_INTR_STATUS_INTRC)) == 0) {
6338 return ADV_FALSE;
6339 }
6340
6341 /*
6342 * Notify the driver of an asynchronous microcode condition by
6343 * calling the adv_async_callback function. The function
6344 * is passed the microcode ASC_MC_INTRB_CODE byte value.
6345 */
6346 if (int_stat & ADV_INTR_STATUS_INTRB) {
6347 uchar intrb_code;
6348
6349 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
6350
6351 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
6352 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
6353 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
6354 asc_dvc->carr_pending_cnt != 0) {
6355 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
6356 ADV_TICKLE_A);
6357 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
6358 AdvWriteByteRegister(iop_base,
6359 IOPB_TICKLE,
6360 ADV_TICKLE_NOP);
6361 }
6362 }
6363 }
6364
6365 adv_async_callback(asc_dvc, intrb_code);
6366 }
6367
6368 /*
6369 * Check if the IRQ stopper carrier contains a completed request.
6370 */
6371 while (((irq_next_vpa =
6372 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0) {
6373 /*
6374 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
6375 * The RISC will have set 'areq_vpa' to a virtual address.
6376 *
6377 * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr
6378 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
6379 * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr'
6380 * in AdvExeScsiQueue().
6381 */
6382 scsiq = (ADV_SCSI_REQ_Q *)
6383 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->areq_vpa));
6384
6385 /*
6386 * Request finished with good status and the queue was not
6387 * DMAed to host memory by the firmware. Set all status fields
6388 * to indicate good status.
6389 */
6390 if ((irq_next_vpa & ASC_RQ_GOOD) != 0) {
6391 scsiq->done_status = QD_NO_ERROR;
6392 scsiq->host_status = scsiq->scsi_status = 0;
6393 scsiq->data_cnt = 0L;
6394 }
6395
6396 /*
6397 * Advance the stopper pointer to the next carrier
6398 * ignoring the lower four bits. Free the previous
6399 * stopper carrier.
6400 */
6401 free_carrp = asc_dvc->irq_sp;
6402 asc_dvc->irq_sp = (ADV_CARR_T *)
6403 ADV_U32_TO_VADDR(ASC_GET_CARRP(irq_next_vpa));
6404
6405 free_carrp->next_vpa =
6406 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
6407 asc_dvc->carr_freelist = free_carrp;
6408 asc_dvc->carr_pending_cnt--;
6409
6410 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
6411
6412 /*
6413 * Clear request microcode control flag.
6414 */
6415 scsiq->cntl = 0;
6416
6417 /*
6418 * Notify the driver of the completed request by passing
6419 * the ADV_SCSI_REQ_Q pointer to its callback function.
6420 */
6421 scsiq->a_flag |= ADV_SCSIQ_DONE;
6422 adv_isr_callback(asc_dvc, scsiq);
6423 /*
6424 * Note: After the driver callback function is called, 'scsiq'
6425 * can no longer be referenced.
6426 *
6427 * Fall through and continue processing other completed
6428 * requests...
6429 */
6430 }
6431 return ADV_TRUE;
6432}
6433
6434static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code)
6435{
6436 if (asc_dvc->err_code == 0) {
6437 asc_dvc->err_code = err_code;
6438 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
6439 err_code);
6440 }
6441 return err_code;
6442}
6443
6444static void AscAckInterrupt(PortAddr iop_base)
6445{
6446 uchar host_flag;
6447 uchar risc_flag;
6448 ushort loop;
6449
6450 loop = 0;
6451 do {
6452 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
6453 if (loop++ > 0x7FFF) {
6454 break;
6455 }
6456 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
6457 host_flag =
6458 AscReadLramByte(iop_base,
6459 ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
6460 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
6461 (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT));
6462 AscSetChipStatus(iop_base, CIW_INT_ACK);
6463 loop = 0;
6464 while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
6465 AscSetChipStatus(iop_base, CIW_INT_ACK);
6466 if (loop++ > 3) {
6467 break;
6468 }
6469 }
6470 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
51219358
MW		 6471}
6472
6473static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
6474{
afbb68c3 6475 const uchar *period_table;
51219358
MW		 6476 int max_index;
6477 int min_index;
6478 int i;
6479
6480 period_table = asc_dvc->sdtr_period_tbl;
6481 max_index = (int)asc_dvc->max_sdtr_index;
afbb68c3 6482 min_index = (int)asc_dvc->min_sdtr_index;
51219358
MW		 6483 if ((syn_time <= period_table[max_index])) {
6484 for (i = min_index; i < (max_index - 1); i++) {
6485 if (syn_time <= period_table[i]) {
6486 return (uchar)i;
6487 }
6488 }
6489 return (uchar)max_index;
6490 } else {
6491 return (uchar)(max_index + 1);
6492 }
6493}
6494
6495static uchar
6496AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset)
6497{
6498 EXT_MSG sdtr_buf;
6499 uchar sdtr_period_index;
6500 PortAddr iop_base;
6501
6502 iop_base = asc_dvc->iop_base;
6503 sdtr_buf.msg_type = EXTENDED_MESSAGE;
6504 sdtr_buf.msg_len = MS_SDTR_LEN;
6505 sdtr_buf.msg_req = EXTENDED_SDTR;
6506 sdtr_buf.xfer_period = sdtr_period;
6507 sdtr_offset &= ASC_SYN_MAX_OFFSET;
6508 sdtr_buf.req_ack_offset = sdtr_offset;
6509 sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
6510 if (sdtr_period_index <= asc_dvc->max_sdtr_index) {
6511 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6512 (uchar *)&sdtr_buf,
6513 sizeof(EXT_MSG) >> 1);
6514 return ((sdtr_period_index << 4) | sdtr_offset);
6515 } else {
6516 sdtr_buf.req_ack_offset = 0;
6517 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6518 (uchar *)&sdtr_buf,
6519 sizeof(EXT_MSG) >> 1);
6520 return 0;
6521 }
6522}
6523
6524static uchar
6525AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
6526{
6527 uchar byte;
6528 uchar sdtr_period_ix;
6529
6530 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
afbb68c3 6531 if (sdtr_period_ix > asc_dvc->max_sdtr_index)
51219358 6532 return 0xFF;
51219358
MW		 6533 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
6534 return byte;
6535}
6536
6537static int AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data)
6538{
6539 ASC_SCSI_BIT_ID_TYPE org_id;
6540 int i;
6541 int sta = TRUE;
6542
6543 AscSetBank(iop_base, 1);
6544 org_id = AscReadChipDvcID(iop_base);
6545 for (i = 0; i <= ASC_MAX_TID; i++) {
6546 if (org_id == (0x01 << i))
6547 break;
6548 }
6549 org_id = (ASC_SCSI_BIT_ID_TYPE) i;
6550 AscWriteChipDvcID(iop_base, id);
6551 if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
6552 AscSetBank(iop_base, 0);
6553 AscSetChipSyn(iop_base, sdtr_data);
6554 if (AscGetChipSyn(iop_base) != sdtr_data) {
6555 sta = FALSE;
6556 }
6557 } else {
6558 sta = FALSE;
6559 }
6560 AscSetBank(iop_base, 1);
6561 AscWriteChipDvcID(iop_base, org_id);
6562 AscSetBank(iop_base, 0);
6563 return (sta);
6564}
6565
6566static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no)
6567{
6568 AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
6569 AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
6570}
6571
6572static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
6573{
6574 EXT_MSG ext_msg;
6575 EXT_MSG out_msg;
6576 ushort halt_q_addr;
6577 int sdtr_accept;
6578 ushort int_halt_code;
6579 ASC_SCSI_BIT_ID_TYPE scsi_busy;
6580 ASC_SCSI_BIT_ID_TYPE target_id;
6581 PortAddr iop_base;
6582 uchar tag_code;
6583 uchar q_status;
6584 uchar halt_qp;
6585 uchar sdtr_data;
6586 uchar target_ix;
6587 uchar q_cntl, tid_no;
6588 uchar cur_dvc_qng;
6589 uchar asyn_sdtr;
6590 uchar scsi_status;
d2411495 6591 struct asc_board *boardp;
51219358
MW		 6592
6593 BUG_ON(!asc_dvc->drv_ptr);
6594 boardp = asc_dvc->drv_ptr;
6595
6596 iop_base = asc_dvc->iop_base;
6597 int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
6598
6599 halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
6600 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
6601 target_ix = AscReadLramByte(iop_base,
6602 (ushort)(halt_q_addr +
6603 (ushort)ASC_SCSIQ_B_TARGET_IX));
6604 q_cntl = AscReadLramByte(iop_base,
6605 (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL));
6606 tid_no = ASC_TIX_TO_TID(target_ix);
6607 target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no);
6608 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6609 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
6610 } else {
6611 asyn_sdtr = 0;
6612 }
6613 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
6614 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6615 AscSetChipSDTR(iop_base, 0, tid_no);
6616 boardp->sdtr_data[tid_no] = 0;
6617 }
6618 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6619 return (0);
6620 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
6621 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6622 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6623 boardp->sdtr_data[tid_no] = asyn_sdtr;
6624 }
6625 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6626 return (0);
6627 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
6628 AscMemWordCopyPtrFromLram(iop_base,
6629 ASCV_MSGIN_BEG,
6630 (uchar *)&ext_msg,
6631 sizeof(EXT_MSG) >> 1);
6632
6633 if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6634 ext_msg.msg_req == EXTENDED_SDTR &&
6635 ext_msg.msg_len == MS_SDTR_LEN) {
6636 sdtr_accept = TRUE;
6637 if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
6638
6639 sdtr_accept = FALSE;
6640 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
6641 }
6642 if ((ext_msg.xfer_period <
afbb68c3 6643 asc_dvc->sdtr_period_tbl[asc_dvc->min_sdtr_index])
51219358
MW		 6644 || (ext_msg.xfer_period >
6645 asc_dvc->sdtr_period_tbl[asc_dvc->
6646 max_sdtr_index])) {
6647 sdtr_accept = FALSE;
6648 ext_msg.xfer_period =
6649 asc_dvc->sdtr_period_tbl[asc_dvc->
afbb68c3 6650 min_sdtr_index];
51219358
MW		 6651 }
6652 if (sdtr_accept) {
6653 sdtr_data =
6654 AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
6655 ext_msg.req_ack_offset);
6656 if ((sdtr_data == 0xFF)) {
6657
6658 q_cntl |= QC_MSG_OUT;
6659 asc_dvc->init_sdtr &= ~target_id;
6660 asc_dvc->sdtr_done &= ~target_id;
6661 AscSetChipSDTR(iop_base, asyn_sdtr,
6662 tid_no);
6663 boardp->sdtr_data[tid_no] = asyn_sdtr;
6664 }
6665 }
6666 if (ext_msg.req_ack_offset == 0) {
6667
6668 q_cntl &= ~QC_MSG_OUT;
6669 asc_dvc->init_sdtr &= ~target_id;
6670 asc_dvc->sdtr_done &= ~target_id;
6671 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6672 } else {
6673 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
51219358
MW		 6674 q_cntl &= ~QC_MSG_OUT;
6675 asc_dvc->sdtr_done |= target_id;
6676 asc_dvc->init_sdtr |= target_id;
6677 asc_dvc->pci_fix_asyn_xfer &=
6678 ~target_id;
6679 sdtr_data =
6680 AscCalSDTRData(asc_dvc,
6681 ext_msg.xfer_period,
6682 ext_msg.
6683 req_ack_offset);
6684 AscSetChipSDTR(iop_base, sdtr_data,
6685 tid_no);
6686 boardp->sdtr_data[tid_no] = sdtr_data;
6687 } else {
51219358
MW		 6688 q_cntl |= QC_MSG_OUT;
6689 AscMsgOutSDTR(asc_dvc,
6690 ext_msg.xfer_period,
6691 ext_msg.req_ack_offset);
6692 asc_dvc->pci_fix_asyn_xfer &=
6693 ~target_id;
6694 sdtr_data =
6695 AscCalSDTRData(asc_dvc,
6696 ext_msg.xfer_period,
6697 ext_msg.
6698 req_ack_offset);
6699 AscSetChipSDTR(iop_base, sdtr_data,
6700 tid_no);
6701 boardp->sdtr_data[tid_no] = sdtr_data;
6702 asc_dvc->sdtr_done |= target_id;
6703 asc_dvc->init_sdtr |= target_id;
6704 }
6705 }
6706
6707 AscWriteLramByte(iop_base,
6708 (ushort)(halt_q_addr +
6709 (ushort)ASC_SCSIQ_B_CNTL),
6710 q_cntl);
6711 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6712 return (0);
6713 } else if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6714 ext_msg.msg_req == EXTENDED_WDTR &&
6715 ext_msg.msg_len == MS_WDTR_LEN) {
6716
6717 ext_msg.wdtr_width = 0;
6718 AscMemWordCopyPtrToLram(iop_base,
6719 ASCV_MSGOUT_BEG,
6720 (uchar *)&ext_msg,
6721 sizeof(EXT_MSG) >> 1);
6722 q_cntl |= QC_MSG_OUT;
6723 AscWriteLramByte(iop_base,
6724 (ushort)(halt_q_addr +
6725 (ushort)ASC_SCSIQ_B_CNTL),
6726 q_cntl);
6727 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6728 return (0);
6729 } else {
6730
6731 ext_msg.msg_type = MESSAGE_REJECT;
6732 AscMemWordCopyPtrToLram(iop_base,
6733 ASCV_MSGOUT_BEG,
6734 (uchar *)&ext_msg,
6735 sizeof(EXT_MSG) >> 1);
6736 q_cntl |= QC_MSG_OUT;
6737 AscWriteLramByte(iop_base,
6738 (ushort)(halt_q_addr +
6739 (ushort)ASC_SCSIQ_B_CNTL),
6740 q_cntl);
6741 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6742 return (0);
6743 }
6744 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
6745
6746 q_cntl |= QC_REQ_SENSE;
6747
6748 if ((asc_dvc->init_sdtr & target_id) != 0) {
6749
6750 asc_dvc->sdtr_done &= ~target_id;
6751
6752 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
6753 q_cntl |= QC_MSG_OUT;
6754 AscMsgOutSDTR(asc_dvc,
6755 asc_dvc->
6756 sdtr_period_tbl[(sdtr_data >> 4) &
6757 (uchar)(asc_dvc->
6758 max_sdtr_index -
6759 1)],
6760 (uchar)(sdtr_data & (uchar)
6761 ASC_SYN_MAX_OFFSET));
6762 }
6763
6764 AscWriteLramByte(iop_base,
6765 (ushort)(halt_q_addr +
6766 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6767
6768 tag_code = AscReadLramByte(iop_base,
6769 (ushort)(halt_q_addr + (ushort)
6770 ASC_SCSIQ_B_TAG_CODE));
6771 tag_code &= 0xDC;
6772 if ((asc_dvc->pci_fix_asyn_xfer & target_id)
6773 && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
6774 ) {
6775
6776 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
6777 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
6778
6779 }
6780 AscWriteLramByte(iop_base,
6781 (ushort)(halt_q_addr +
6782 (ushort)ASC_SCSIQ_B_TAG_CODE),
6783 tag_code);
6784
6785 q_status = AscReadLramByte(iop_base,
6786 (ushort)(halt_q_addr + (ushort)
6787 ASC_SCSIQ_B_STATUS));
6788 q_status |= (QS_READY | QS_BUSY);
6789 AscWriteLramByte(iop_base,
6790 (ushort)(halt_q_addr +
6791 (ushort)ASC_SCSIQ_B_STATUS),
6792 q_status);
6793
6794 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B);
6795 scsi_busy &= ~target_id;
6796 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6797
6798 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6799 return (0);
6800 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
6801
6802 AscMemWordCopyPtrFromLram(iop_base,
6803 ASCV_MSGOUT_BEG,
6804 (uchar *)&out_msg,
6805 sizeof(EXT_MSG) >> 1);
6806
6807 if ((out_msg.msg_type == EXTENDED_MESSAGE) &&
6808 (out_msg.msg_len == MS_SDTR_LEN) &&
6809 (out_msg.msg_req == EXTENDED_SDTR)) {
6810
6811 asc_dvc->init_sdtr &= ~target_id;
6812 asc_dvc->sdtr_done &= ~target_id;
6813 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6814 boardp->sdtr_data[tid_no] = asyn_sdtr;
6815 }
6816 q_cntl &= ~QC_MSG_OUT;
6817 AscWriteLramByte(iop_base,
6818 (ushort)(halt_q_addr +
6819 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6820 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6821 return (0);
6822 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
6823
6824 scsi_status = AscReadLramByte(iop_base,
6825 (ushort)((ushort)halt_q_addr +
6826 (ushort)
6827 ASC_SCSIQ_SCSI_STATUS));
6828 cur_dvc_qng =
6829 AscReadLramByte(iop_base,
6830 (ushort)((ushort)ASC_QADR_BEG +
6831 (ushort)target_ix));
6832 if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
6833
6834 scsi_busy = AscReadLramByte(iop_base,
6835 (ushort)ASCV_SCSIBUSY_B);
6836 scsi_busy |= target_id;
6837 AscWriteLramByte(iop_base,
6838 (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6839 asc_dvc->queue_full_or_busy |= target_id;
6840
6841 if (scsi_status == SAM_STAT_TASK_SET_FULL) {
6842 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
6843 cur_dvc_qng -= 1;
6844 asc_dvc->max_dvc_qng[tid_no] =
6845 cur_dvc_qng;
6846
6847 AscWriteLramByte(iop_base,
6848 (ushort)((ushort)
6849 ASCV_MAX_DVC_QNG_BEG
6850 + (ushort)
6851 tid_no),
6852 cur_dvc_qng);
6853
6854 /*
6855 * Set the device queue depth to the
6856 * number of active requests when the
6857 * QUEUE FULL condition was encountered.
6858 */
6859 boardp->queue_full |= target_id;
6860 boardp->queue_full_cnt[tid_no] =
6861 cur_dvc_qng;
6862 }
6863 }
6864 }
6865 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6866 return (0);
6867 }
6868#if CC_VERY_LONG_SG_LIST
6869 else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC) {
6870 uchar q_no;
6871 ushort q_addr;
6872 uchar sg_wk_q_no;
6873 uchar first_sg_wk_q_no;
6874 ASC_SCSI_Q *scsiq; /* Ptr to driver request. */
6875 ASC_SG_HEAD *sg_head; /* Ptr to driver SG request. */
6876 ASC_SG_LIST_Q scsi_sg_q; /* Structure written to queue. */
6877 ushort sg_list_dwords;
6878 ushort sg_entry_cnt;
6879 uchar next_qp;
6880 int i;
6881
6882 q_no = AscReadLramByte(iop_base, (ushort)ASCV_REQ_SG_LIST_QP);
6883 if (q_no == ASC_QLINK_END)
6884 return 0;
6885
6886 q_addr = ASC_QNO_TO_QADDR(q_no);
6887
6888 /*
6889 * Convert the request's SRB pointer to a host ASC_SCSI_REQ
6890 * structure pointer using a macro provided by the driver.
6891 * The ASC_SCSI_REQ pointer provides a pointer to the
6892 * host ASC_SG_HEAD structure.
6893 */
6894 /* Read request's SRB pointer. */
6895 scsiq = (ASC_SCSI_Q *)
6896 ASC_SRB2SCSIQ(ASC_U32_TO_VADDR(AscReadLramDWord(iop_base,
6897 (ushort)
6898 (q_addr +
6899 ASC_SCSIQ_D_SRBPTR))));
6900
6901 /*
6902 * Get request's first and working SG queue.
6903 */
6904 sg_wk_q_no = AscReadLramByte(iop_base,
6905 (ushort)(q_addr +
6906 ASC_SCSIQ_B_SG_WK_QP));
6907
6908 first_sg_wk_q_no = AscReadLramByte(iop_base,
6909 (ushort)(q_addr +
6910 ASC_SCSIQ_B_FIRST_SG_WK_QP));
6911
6912 /*
6913 * Reset request's working SG queue back to the
6914 * first SG queue.
6915 */
6916 AscWriteLramByte(iop_base,
6917 (ushort)(q_addr +
6918 (ushort)ASC_SCSIQ_B_SG_WK_QP),
6919 first_sg_wk_q_no);
6920
6921 sg_head = scsiq->sg_head;
6922
6923 /*
6924 * Set sg_entry_cnt to the number of SG elements
6925 * that will be completed on this interrupt.
6926 *
6927 * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
6928 * SG elements. The data_cnt and data_addr fields which
6929 * add 1 to the SG element capacity are not used when
6930 * restarting SG handling after a halt.
6931 */
6932 if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1)) {
6933 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
6934
6935 /*
6936 * Keep track of remaining number of SG elements that
6937 * will need to be handled on the next interrupt.
6938 */
6939 scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1);
6940 } else {
6941 sg_entry_cnt = scsiq->remain_sg_entry_cnt;
6942 scsiq->remain_sg_entry_cnt = 0;
6943 }
6944
6945 /*
6946 * Copy SG elements into the list of allocated SG queues.
6947 *
6948 * Last index completed is saved in scsiq->next_sg_index.
6949 */
6950 next_qp = first_sg_wk_q_no;
6951 q_addr = ASC_QNO_TO_QADDR(next_qp);
6952 scsi_sg_q.sg_head_qp = q_no;
6953 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
6954 for (i = 0; i < sg_head->queue_cnt; i++) {
6955 scsi_sg_q.seq_no = i + 1;
6956 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
6957 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
6958 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
6959 /*
6960 * After very first SG queue RISC FW uses next
6961 * SG queue first element then checks sg_list_cnt
6962 * against zero and then decrements, so set
6963 * sg_list_cnt 1 less than number of SG elements
6964 * in each SG queue.
6965 */
6966 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
6967 scsi_sg_q.sg_cur_list_cnt =
6968 ASC_SG_LIST_PER_Q - 1;
6969 } else {
6970 /*
6971 * This is the last SG queue in the list of
6972 * allocated SG queues. If there are more
6973 * SG elements than will fit in the allocated
6974 * queues, then set the QCSG_SG_XFER_MORE flag.
6975 */
6976 if (scsiq->remain_sg_entry_cnt != 0) {
6977 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
6978 } else {
6979 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
6980 }
6981 /* equals sg_entry_cnt * 2 */
6982 sg_list_dwords = sg_entry_cnt << 1;
6983 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
6984 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
6985 sg_entry_cnt = 0;
6986 }
6987
6988 scsi_sg_q.q_no = next_qp;
6989 AscMemWordCopyPtrToLram(iop_base,
6990 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
6991 (uchar *)&scsi_sg_q,
6992 sizeof(ASC_SG_LIST_Q) >> 1);
6993
6994 AscMemDWordCopyPtrToLram(iop_base,
6995 q_addr + ASC_SGQ_LIST_BEG,
6996 (uchar *)&sg_head->
6997 sg_list[scsiq->next_sg_index],
6998 sg_list_dwords);
6999
7000 scsiq->next_sg_index += ASC_SG_LIST_PER_Q;
7001
7002 /*
7003 * If the just completed SG queue contained the
7004 * last SG element, then no more SG queues need
7005 * to be written.
7006 */
7007 if (scsi_sg_q.cntl & QCSG_SG_XFER_END) {
7008 break;
7009 }
7010
7011 next_qp = AscReadLramByte(iop_base,
7012 (ushort)(q_addr +
7013 ASC_SCSIQ_B_FWD));
7014 q_addr = ASC_QNO_TO_QADDR(next_qp);
7015 }
7016
7017 /*
7018 * Clear the halt condition so the RISC will be restarted
7019 * after the return.
7020 */
7021 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
7022 return (0);
7023 }
7024#endif /* CC_VERY_LONG_SG_LIST */
7025 return (0);
7026}
1da177e4 7027
1da177e4 7028/*
51219358
MW		 7029 * void
7030 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
1da177e4 7031 *
51219358
MW		 7032 * Calling/Exit State:
7033 * none
1da177e4 7034 *
51219358
MW		 7035 * Description:
7036 * Input an ASC_QDONE_INFO structure from the chip
1da177e4 7037 */
51219358
MW		 7038static void
7039DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
7040{
7041 int i;
7042 ushort word;
7043
7044 AscSetChipLramAddr(iop_base, s_addr);
7045 for (i = 0; i < 2 * words; i += 2) {
7046 if (i == 10) {
7047 continue;
7048 }
7049 word = inpw(iop_base + IOP_RAM_DATA);
7050 inbuf[i] = word & 0xff;
7051 inbuf[i + 1] = (word >> 8) & 0xff;
7052 }
7053 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
7054}
7055
7056static uchar
7057_AscCopyLramScsiDoneQ(PortAddr iop_base,
7058 ushort q_addr,
7059 ASC_QDONE_INFO *scsiq, ASC_DCNT max_dma_count)
7060{
7061 ushort _val;
7062 uchar sg_queue_cnt;
7063
7064 DvcGetQinfo(iop_base,
7065 q_addr + ASC_SCSIQ_DONE_INFO_BEG,
7066 (uchar *)scsiq,
7067 (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2);
7068
7069 _val = AscReadLramWord(iop_base,
7070 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS));
7071 scsiq->q_status = (uchar)_val;
7072 scsiq->q_no = (uchar)(_val >> 8);
7073 _val = AscReadLramWord(iop_base,
7074 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL));
7075 scsiq->cntl = (uchar)_val;
7076 sg_queue_cnt = (uchar)(_val >> 8);
7077 _val = AscReadLramWord(iop_base,
7078 (ushort)(q_addr +
7079 (ushort)ASC_SCSIQ_B_SENSE_LEN));
7080 scsiq->sense_len = (uchar)_val;
7081 scsiq->extra_bytes = (uchar)(_val >> 8);
7082
7083 /*
7084 * Read high word of remain bytes from alternate location.
7085 */
7086 scsiq->remain_bytes = (((ADV_DCNT)AscReadLramWord(iop_base,
7087 (ushort)(q_addr +
7088 (ushort)
7089 ASC_SCSIQ_W_ALT_DC1)))
7090 << 16);
7091 /*
7092 * Read low word of remain bytes from original location.
7093 */
7094 scsiq->remain_bytes += AscReadLramWord(iop_base,
7095 (ushort)(q_addr + (ushort)
7096 ASC_SCSIQ_DW_REMAIN_XFER_CNT));
7097
7098 scsiq->remain_bytes &= max_dma_count;
7099 return sg_queue_cnt;
7100}
7101
7102/*
7103 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
7104 *
7105 * Interrupt callback function for the Narrow SCSI Asc Library.
7106 */
7107static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
7108{
d2411495 7109 struct asc_board *boardp;
51219358
MW		 7110 struct scsi_cmnd *scp;
7111 struct Scsi_Host *shost;
7112
b352f923 7113 ASC_DBG(1, "asc_dvc_varp 0x%p, qdonep 0x%p\n", asc_dvc_varp, qdonep);
51219358
MW		 7114 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
7115
b249c7fd
MW		 7116 scp = advansys_srb_to_ptr(asc_dvc_varp, qdonep->d2.srb_ptr);
7117 if (!scp)
51219358 7118 return;
b249c7fd 7119
51219358
MW		 7120 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
7121
7122 shost = scp->device->host;
7123 ASC_STATS(shost, callback);
b352f923 7124 ASC_DBG(1, "shost 0x%p\n", shost);
51219358 7125
d2411495 7126 boardp = shost_priv(shost);
51219358
MW		 7127 BUG_ON(asc_dvc_varp != &boardp->dvc_var.asc_dvc_var);
7128
b249c7fd 7129 dma_unmap_single(boardp->dev, scp->SCp.dma_handle,
b80ca4f7 7130 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
51219358
MW		 7131 /*
7132 * 'qdonep' contains the command's ending status.
7133 */
7134 switch (qdonep->d3.done_stat) {
7135 case QD_NO_ERROR:
b352f923 7136 ASC_DBG(2, "QD_NO_ERROR\n");
51219358
MW		 7137 scp->result = 0;
7138
7139 /*
7140 * Check for an underrun condition.
7141 *
7142 * If there was no error and an underrun condition, then
7143 * return the number of underrun bytes.
7144 */
52c334e9
MW		 7145 if (scsi_bufflen(scp) != 0 && qdonep->remain_bytes != 0 &&
7146 qdonep->remain_bytes <= scsi_bufflen(scp)) {
b352f923 7147 ASC_DBG(1, "underrun condition %u bytes\n",
51219358 7148 (unsigned)qdonep->remain_bytes);
52c334e9 7149 scsi_set_resid(scp, qdonep->remain_bytes);
51219358
MW		 7150 }
7151 break;
7152
7153 case QD_WITH_ERROR:
b352f923 7154 ASC_DBG(2, "QD_WITH_ERROR\n");
51219358
MW		 7155 switch (qdonep->d3.host_stat) {
7156 case QHSTA_NO_ERROR:
7157 if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
b352f923 7158 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
51219358 7159 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
b80ca4f7 7160 SCSI_SENSE_BUFFERSIZE);
51219358
MW		 7161 /*
7162 * Note: The 'status_byte()' macro used by
7163 * target drivers defined in scsi.h shifts the
7164 * status byte returned by host drivers right
7165 * by 1 bit. This is why target drivers also
7166 * use right shifted status byte definitions.
7167 * For instance target drivers use
7168 * CHECK_CONDITION, defined to 0x1, instead of
7169 * the SCSI defined check condition value of
7170 * 0x2. Host drivers are supposed to return
7171 * the status byte as it is defined by SCSI.
7172 */
7173 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
7174 STATUS_BYTE(qdonep->d3.scsi_stat);
7175 } else {
7176 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
7177 }
7178 break;
7179
7180 default:
7181 /* QHSTA error occurred */
b352f923 7182 ASC_DBG(1, "host_stat 0x%x\n", qdonep->d3.host_stat);
51219358
MW		 7183 scp->result = HOST_BYTE(DID_BAD_TARGET);
7184 break;
7185 }
7186 break;
7187
7188 case QD_ABORTED_BY_HOST:
b352f923 7189 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
51219358
MW		 7190 scp->result =
7191 HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.
7192 scsi_msg) |
7193 STATUS_BYTE(qdonep->d3.scsi_stat);
7194 break;
7195
7196 default:
b352f923 7197 ASC_DBG(1, "done_stat 0x%x\n", qdonep->d3.done_stat);
51219358
MW		 7198 scp->result =
7199 HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.
7200 scsi_msg) |
7201 STATUS_BYTE(qdonep->d3.scsi_stat);
7202 break;
7203 }
7204
7205 /*
7206 * If the 'init_tidmask' bit isn't already set for the target and the
7207 * current request finished normally, then set the bit for the target
7208 * to indicate that a device is present.
7209 */
7210 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
7211 qdonep->d3.done_stat == QD_NO_ERROR &&
7212 qdonep->d3.host_stat == QHSTA_NO_ERROR) {
7213 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
7214 }
1da177e4 7215
51219358 7216 asc_scsi_done(scp);
51219358
MW		 7217}
7218
7219static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
7220{
7221 uchar next_qp;
7222 uchar n_q_used;
7223 uchar sg_list_qp;
7224 uchar sg_queue_cnt;
7225 uchar q_cnt;
7226 uchar done_q_tail;
7227 uchar tid_no;
7228 ASC_SCSI_BIT_ID_TYPE scsi_busy;
7229 ASC_SCSI_BIT_ID_TYPE target_id;
7230 PortAddr iop_base;
7231 ushort q_addr;
7232 ushort sg_q_addr;
7233 uchar cur_target_qng;
7234 ASC_QDONE_INFO scsiq_buf;
7235 ASC_QDONE_INFO *scsiq;
7236 int false_overrun;
7237
7238 iop_base = asc_dvc->iop_base;
7239 n_q_used = 1;
7240 scsiq = (ASC_QDONE_INFO *)&scsiq_buf;
7241 done_q_tail = (uchar)AscGetVarDoneQTail(iop_base);
7242 q_addr = ASC_QNO_TO_QADDR(done_q_tail);
7243 next_qp = AscReadLramByte(iop_base,
7244 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD));
7245 if (next_qp != ASC_QLINK_END) {
7246 AscPutVarDoneQTail(iop_base, next_qp);
7247 q_addr = ASC_QNO_TO_QADDR(next_qp);
7248 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
7249 asc_dvc->max_dma_count);
7250 AscWriteLramByte(iop_base,
7251 (ushort)(q_addr +
7252 (ushort)ASC_SCSIQ_B_STATUS),
7253 (uchar)(scsiq->
7254 q_status & (uchar)~(QS_READY |
7255 QS_ABORTED)));
7256 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
7257 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
7258 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
7259 sg_q_addr = q_addr;
7260 sg_list_qp = next_qp;
7261 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
7262 sg_list_qp = AscReadLramByte(iop_base,
7263 (ushort)(sg_q_addr
7264 + (ushort)
7265 ASC_SCSIQ_B_FWD));
7266 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
7267 if (sg_list_qp == ASC_QLINK_END) {
7268 AscSetLibErrorCode(asc_dvc,
7269 ASCQ_ERR_SG_Q_LINKS);
7270 scsiq->d3.done_stat = QD_WITH_ERROR;
7271 scsiq->d3.host_stat =
7272 QHSTA_D_QDONE_SG_LIST_CORRUPTED;
7273 goto FATAL_ERR_QDONE;
7274 }
7275 AscWriteLramByte(iop_base,
7276 (ushort)(sg_q_addr + (ushort)
7277 ASC_SCSIQ_B_STATUS),
7278 QS_FREE);
7279 }
7280 n_q_used = sg_queue_cnt + 1;
7281 AscPutVarDoneQTail(iop_base, sg_list_qp);
7282 }
7283 if (asc_dvc->queue_full_or_busy & target_id) {
7284 cur_target_qng = AscReadLramByte(iop_base,
7285 (ushort)((ushort)
7286 ASC_QADR_BEG
7287 + (ushort)
7288 scsiq->d2.
7289 target_ix));
7290 if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
7291 scsi_busy = AscReadLramByte(iop_base, (ushort)
7292 ASCV_SCSIBUSY_B);
7293 scsi_busy &= ~target_id;
7294 AscWriteLramByte(iop_base,
7295 (ushort)ASCV_SCSIBUSY_B,
7296 scsi_busy);
7297 asc_dvc->queue_full_or_busy &= ~target_id;
7298 }
7299 }
7300 if (asc_dvc->cur_total_qng >= n_q_used) {
7301 asc_dvc->cur_total_qng -= n_q_used;
7302 if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
7303 asc_dvc->cur_dvc_qng[tid_no]--;
7304 }
7305 } else {
7306 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
7307 scsiq->d3.done_stat = QD_WITH_ERROR;
7308 goto FATAL_ERR_QDONE;
7309 }
7310 if ((scsiq->d2.srb_ptr == 0UL) ||
7311 ((scsiq->q_status & QS_ABORTED) != 0)) {
7312 return (0x11);
7313 } else if (scsiq->q_status == QS_DONE) {
7314 false_overrun = FALSE;
7315 if (scsiq->extra_bytes != 0) {
7316 scsiq->remain_bytes +=
7317 (ADV_DCNT)scsiq->extra_bytes;
7318 }
7319 if (scsiq->d3.done_stat == QD_WITH_ERROR) {
7320 if (scsiq->d3.host_stat ==
7321 QHSTA_M_DATA_OVER_RUN) {
7322 if ((scsiq->
7323 cntl & (QC_DATA_IN | QC_DATA_OUT))
7324 == 0) {
7325 scsiq->d3.done_stat =
7326 QD_NO_ERROR;
7327 scsiq->d3.host_stat =
7328 QHSTA_NO_ERROR;
7329 } else if (false_overrun) {
7330 scsiq->d3.done_stat =
7331 QD_NO_ERROR;
7332 scsiq->d3.host_stat =
7333 QHSTA_NO_ERROR;
7334 }
7335 } else if (scsiq->d3.host_stat ==
7336 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
7337 AscStopChip(iop_base);
7338 AscSetChipControl(iop_base,
7339 (uchar)(CC_SCSI_RESET
7340 | CC_HALT));
7341 udelay(60);
7342 AscSetChipControl(iop_base, CC_HALT);
7343 AscSetChipStatus(iop_base,
7344 CIW_CLR_SCSI_RESET_INT);
7345 AscSetChipStatus(iop_base, 0);
7346 AscSetChipControl(iop_base, 0);
7347 }
7348 }
7349 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7350 asc_isr_callback(asc_dvc, scsiq);
7351 } else {
7352 if ((AscReadLramByte(iop_base,
7353 (ushort)(q_addr + (ushort)
7354 ASC_SCSIQ_CDB_BEG))
7355 == START_STOP)) {
7356 asc_dvc->unit_not_ready &= ~target_id;
7357 if (scsiq->d3.done_stat != QD_NO_ERROR) {
7358 asc_dvc->start_motor &=
7359 ~target_id;
7360 }
7361 }
7362 }
7363 return (1);
7364 } else {
7365 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
7366 FATAL_ERR_QDONE:
7367 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7368 asc_isr_callback(asc_dvc, scsiq);
7369 }
7370 return (0x80);
7371 }
7372 }
7373 return (0);
7374}
1da177e4 7375
51219358
MW		 7376static int AscISR(ASC_DVC_VAR *asc_dvc)
7377{
7378 ASC_CS_TYPE chipstat;
7379 PortAddr iop_base;
7380 ushort saved_ram_addr;
7381 uchar ctrl_reg;
7382 uchar saved_ctrl_reg;
7383 int int_pending;
7384 int status;
7385 uchar host_flag;
1da177e4 7386
51219358
MW		 7387 iop_base = asc_dvc->iop_base;
7388 int_pending = FALSE;
1da177e4 7389
51219358
MW		 7390 if (AscIsIntPending(iop_base) == 0)
7391 return int_pending;
7392
7393 if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) {
7394 return ERR;
7395 }
7396 if (asc_dvc->in_critical_cnt != 0) {
7397 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
7398 return ERR;
7399 }
7400 if (asc_dvc->is_in_int) {
7401 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
7402 return ERR;
7403 }
7404 asc_dvc->is_in_int = TRUE;
7405 ctrl_reg = AscGetChipControl(iop_base);
7406 saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
7407 CC_SINGLE_STEP | CC_DIAG | CC_TEST));
7408 chipstat = AscGetChipStatus(iop_base);
7409 if (chipstat & CSW_SCSI_RESET_LATCH) {
7410 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
7411 int i = 10;
7412 int_pending = TRUE;
7413 asc_dvc->sdtr_done = 0;
7414 saved_ctrl_reg &= (uchar)(~CC_HALT);
7415 while ((AscGetChipStatus(iop_base) &
7416 CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) {
7417 mdelay(100);
7418 }
7419 AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
7420 AscSetChipControl(iop_base, CC_HALT);
7421 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
7422 AscSetChipStatus(iop_base, 0);
7423 chipstat = AscGetChipStatus(iop_base);
7424 }
7425 }
7426 saved_ram_addr = AscGetChipLramAddr(iop_base);
7427 host_flag = AscReadLramByte(iop_base,
7428 ASCV_HOST_FLAG_B) &
7429 (uchar)(~ASC_HOST_FLAG_IN_ISR);
7430 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
7431 (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR));
7432 if ((chipstat & CSW_INT_PENDING) || (int_pending)) {
7433 AscAckInterrupt(iop_base);
7434 int_pending = TRUE;
7435 if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {
7436 if (AscIsrChipHalted(asc_dvc) == ERR) {
7437 goto ISR_REPORT_QDONE_FATAL_ERROR;
7438 } else {
7439 saved_ctrl_reg &= (uchar)(~CC_HALT);
7440 }
7441 } else {
7442 ISR_REPORT_QDONE_FATAL_ERROR:
7443 if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
7444 while (((status =
7445 AscIsrQDone(asc_dvc)) & 0x01) != 0) {
7446 }
7447 } else {
7448 do {
7449 if ((status =
7450 AscIsrQDone(asc_dvc)) == 1) {
7451 break;
7452 }
7453 } while (status == 0x11);
7454 }
7455 if ((status & 0x80) != 0)
7456 int_pending = ERR;
7457 }
7458 }
7459 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
7460 AscSetChipLramAddr(iop_base, saved_ram_addr);
7461 AscSetChipControl(iop_base, saved_ctrl_reg);
7462 asc_dvc->is_in_int = FALSE;
7463 return int_pending;
7464}
1da177e4
LT		 7465
7466/*
51219358 7467 * advansys_reset()
1da177e4 7468 *
51219358 7469 * Reset the bus associated with the command 'scp'.
1da177e4 7470 *
51219358
MW		 7471 * This function runs its own thread. Interrupts must be blocked but
7472 * sleeping is allowed and no locking other than for host structures is
7473 * required. Returns SUCCESS or FAILED.
1da177e4 7474 */
51219358 7475static int advansys_reset(struct scsi_cmnd *scp)
1da177e4 7476{
52fa0777 7477 struct Scsi_Host *shost = scp->device->host;
d2411495 7478 struct asc_board *boardp = shost_priv(shost);
52fa0777 7479 unsigned long flags;
27c868c2 7480 int status;
51219358 7481 int ret = SUCCESS;
27c868c2 7482
b352f923 7483 ASC_DBG(1, "0x%p\n", scp);
27c868c2 7484
52fa0777 7485 ASC_STATS(shost, reset);
27c868c2 7486
52fa0777 7487 scmd_printk(KERN_INFO, scp, "SCSI bus reset started...\n");
51219358
MW		 7488
7489 if (ASC_NARROW_BOARD(boardp)) {
52fa0777 7490 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
1da177e4 7491
52fa0777 7492 /* Reset the chip and SCSI bus. */
b352f923 7493 ASC_DBG(1, "before AscInitAsc1000Driver()\n");
52fa0777 7494 status = AscInitAsc1000Driver(asc_dvc);
27c868c2 7495
6070d81e 7496 /* Refer to ASC_IERR_* definitions for meaning of 'err_code'. */
9a908c1a 7497 if (asc_dvc->err_code || !asc_dvc->overrun_dma) {
52fa0777 7498 scmd_printk(KERN_INFO, scp, "SCSI bus reset error: "
9a908c1a
HRK		 7499 "0x%x, status: 0x%x\n", asc_dvc->err_code,
7500 status);
51219358
MW		 7501 ret = FAILED;
7502 } else if (status) {
52fa0777
MW		 7503 scmd_printk(KERN_INFO, scp, "SCSI bus reset warning: "
7504 "0x%x\n", status);
27c868c2 7505 } else {
52fa0777
MW		 7506 scmd_printk(KERN_INFO, scp, "SCSI bus reset "
7507 "successful\n");
27c868c2 7508 }
a9f4a59a 7509
b352f923 7510 ASC_DBG(1, "after AscInitAsc1000Driver()\n");
f092d229 7511 spin_lock_irqsave(shost->host_lock, flags);
a9f4a59a 7512 } else {
a9f4a59a 7513 /*
51219358
MW		 7514 * If the suggest reset bus flags are set, then reset the bus.
7515 * Otherwise only reset the device.
a9f4a59a 7516 */
52fa0777 7517 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
a9f4a59a
MW		 7518
7519 /*
51219358 7520 * Reset the target's SCSI bus.
a9f4a59a 7521 */
b352f923 7522 ASC_DBG(1, "before AdvResetChipAndSB()\n");
52fa0777 7523 switch (AdvResetChipAndSB(adv_dvc)) {
51219358 7524 case ASC_TRUE:
52fa0777
MW		 7525 scmd_printk(KERN_INFO, scp, "SCSI bus reset "
7526 "successful\n");
51219358
MW		 7527 break;
7528 case ASC_FALSE:
7529 default:
52fa0777 7530 scmd_printk(KERN_INFO, scp, "SCSI bus reset error\n");
51219358
MW		 7531 ret = FAILED;
7532 break;
b9d96614 7533 }
f092d229 7534 spin_lock_irqsave(shost->host_lock, flags);
52fa0777 7535 AdvISR(adv_dvc);
b9d96614
MW		 7536 }
7537
51219358
MW		 7538 /* Save the time of the most recently completed reset. */
7539 boardp->last_reset = jiffies;
f092d229 7540 spin_unlock_irqrestore(shost->host_lock, flags);
b9d96614 7541
b352f923 7542 ASC_DBG(1, "ret %d\n", ret);
b9d96614 7543
51219358 7544 return ret;
b9d96614
MW		 7545}
7546
1da177e4 7547/*
51219358 7548 * advansys_biosparam()
1da177e4 7549 *
51219358
MW		 7550 * Translate disk drive geometry if the "BIOS greater than 1 GB"
7551 * support is enabled for a drive.
1da177e4 7552 *
51219358
MW		 7553 * ip (information pointer) is an int array with the following definition:
7554 * ip[0]: heads
7555 * ip[1]: sectors
7556 * ip[2]: cylinders
1da177e4 7557 */
51219358
MW		 7558static int
7559advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
7560 sector_t capacity, int ip[])
1da177e4 7561{
d2411495 7562 struct asc_board *boardp = shost_priv(sdev->host);
1da177e4 7563
b352f923 7564 ASC_DBG(1, "begin\n");
51219358 7565 ASC_STATS(sdev->host, biosparam);
51219358
MW		 7566 if (ASC_NARROW_BOARD(boardp)) {
7567 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
7568 ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
7569 ip[0] = 255;
7570 ip[1] = 63;
7571 } else {
7572 ip[0] = 64;
7573 ip[1] = 32;
7574 }
7575 } else {
7576 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
7577 BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
7578 ip[0] = 255;
7579 ip[1] = 63;
7580 } else {
7581 ip[0] = 64;
7582 ip[1] = 32;
7583 }
27c868c2 7584 }
51219358 7585 ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
b352f923 7586 ASC_DBG(1, "end\n");
51219358
MW		 7587 return 0;
7588}
1da177e4 7589
51219358
MW		 7590/*
7591 * First-level interrupt handler.
7592 *
7593 * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host.
7594 */
7595static irqreturn_t advansys_interrupt(int irq, void *dev_id)
7596{
51219358 7597 struct Scsi_Host *shost = dev_id;
d2411495 7598 struct asc_board *boardp = shost_priv(shost);
51219358 7599 irqreturn_t result = IRQ_NONE;
27c868c2 7600
b352f923 7601 ASC_DBG(2, "boardp 0x%p\n", boardp);
f092d229 7602 spin_lock(shost->host_lock);
51219358
MW		 7603 if (ASC_NARROW_BOARD(boardp)) {
7604 if (AscIsIntPending(shost->io_port)) {
7605 result = IRQ_HANDLED;
7606 ASC_STATS(shost, interrupt);
b352f923 7607 ASC_DBG(1, "before AscISR()\n");
51219358
MW		 7608 AscISR(&boardp->dvc_var.asc_dvc_var);
7609 }
7610 } else {
b352f923 7611 ASC_DBG(1, "before AdvISR()\n");
51219358
MW		 7612 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
7613 result = IRQ_HANDLED;
7614 ASC_STATS(shost, interrupt);
7615 }
27c868c2 7616 }
f092d229 7617 spin_unlock(shost->host_lock);
1da177e4 7618
b352f923 7619 ASC_DBG(1, "end\n");
51219358
MW		 7620 return result;
7621}
27c868c2 7622
51219358
MW		 7623static int AscHostReqRiscHalt(PortAddr iop_base)
7624{
7625 int count = 0;
7626 int sta = 0;
7627 uchar saved_stop_code;
7628
7629 if (AscIsChipHalted(iop_base))
7630 return (1);
7631 saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
7632 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
7633 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP);
7634 do {
7635 if (AscIsChipHalted(iop_base)) {
7636 sta = 1;
7637 break;
27c868c2 7638 }
51219358
MW		 7639 mdelay(100);
7640 } while (count++ < 20);
7641 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
7642 return (sta);
7643}
1da177e4 7644
51219358
MW		 7645static int
7646AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data)
7647{
7648 int sta = FALSE;
1da177e4 7649
51219358
MW		 7650 if (AscHostReqRiscHalt(iop_base)) {
7651 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
7652 AscStartChip(iop_base);
27c868c2 7653 }
51219358
MW		 7654 return sta;
7655}
1da177e4 7656
51219358
MW		 7657static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev)
7658{
7659 char type = sdev->type;
7660 ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id;
27c868c2 7661
51219358
MW		 7662 if (!(asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN))
7663 return;
7664 if (asc_dvc->init_sdtr & tid_bits)
7665 return;
27c868c2 7666
51219358
MW		 7667 if ((type == TYPE_ROM) && (strncmp(sdev->vendor, "HP ", 3) == 0))
7668 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
27c868c2 7669
51219358
MW		 7670 asc_dvc->pci_fix_asyn_xfer |= tid_bits;
7671 if ((type == TYPE_PROCESSOR) || (type == TYPE_SCANNER) ||
7672 (type == TYPE_ROM) || (type == TYPE_TAPE))
7673 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
7674
7675 if (asc_dvc->pci_fix_asyn_xfer & tid_bits)
7676 AscSetRunChipSynRegAtID(asc_dvc->iop_base, sdev->id,
7677 ASYN_SDTR_DATA_FIX_PCI_REV_AB);
7678}
1da177e4 7679
51219358
MW		 7680static void
7681advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc)
7682{
7683 ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id;
7684 ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng;
27c868c2 7685
51219358
MW		 7686 if (sdev->lun == 0) {
7687 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr;
7688 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) {
7689 asc_dvc->init_sdtr |= tid_bit;
7690 } else {
7691 asc_dvc->init_sdtr &= ~tid_bit;
7692 }
7693
7694 if (orig_init_sdtr != asc_dvc->init_sdtr)
7695 AscAsyncFix(asc_dvc, sdev);
27c868c2 7696 }
1da177e4 7697
51219358
MW		 7698 if (sdev->tagged_supported) {
7699 if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) {
7700 if (sdev->lun == 0) {
7701 asc_dvc->cfg->can_tagged_qng |= tid_bit;
7702 asc_dvc->use_tagged_qng |= tid_bit;
7703 }
db5ed4df 7704 scsi_change_queue_depth(sdev,
51219358 7705 asc_dvc->max_dvc_qng[sdev->id]);
27c868c2 7706 }
51219358
MW		 7707 } else {
7708 if (sdev->lun == 0) {
7709 asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
7710 asc_dvc->use_tagged_qng &= ~tid_bit;
27c868c2
MW		 7711 }
7712 }
1da177e4 7713
51219358
MW		 7714 if ((sdev->lun == 0) &&
7715 (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) {
7716 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
7717 asc_dvc->cfg->disc_enable);
7718 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
7719 asc_dvc->use_tagged_qng);
7720 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
7721 asc_dvc->cfg->can_tagged_qng);
27c868c2 7722
51219358
MW		 7723 asc_dvc->max_dvc_qng[sdev->id] =
7724 asc_dvc->cfg->max_tag_qng[sdev->id];
7725 AscWriteLramByte(asc_dvc->iop_base,
7726 (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id),
7727 asc_dvc->max_dvc_qng[sdev->id]);
7728 }
7729}
27c868c2 7730
51219358
MW		 7731/*
7732 * Wide Transfers
7733 *
7734 * If the EEPROM enabled WDTR for the device and the device supports wide
7735 * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and
7736 * write the new value to the microcode.
7737 */
7738static void
7739advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask)
7740{
7741 unsigned short cfg_word;
7742 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
7743 if ((cfg_word & tidmask) != 0)
7744 return;
27c868c2 7745
51219358
MW		 7746 cfg_word |= tidmask;
7747 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
27c868c2
MW		 7748
7749 /*
51219358
MW		 7750 * Clear the microcode SDTR and WDTR negotiation done indicators for
7751 * the target to cause it to negotiate with the new setting set above.
7752 * WDTR when accepted causes the target to enter asynchronous mode, so
7753 * SDTR must be negotiated.
27c868c2 7754 */
51219358
MW		 7755 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7756 cfg_word &= ~tidmask;
7757 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7758 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
7759 cfg_word &= ~tidmask;
7760 AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
7761}
1da177e4 7762
51219358
MW		 7763/*
7764 * Synchronous Transfers
7765 *
7766 * If the EEPROM enabled SDTR for the device and the device
7767 * supports synchronous transfers, then turn on the device's
7768 * 'sdtr_able' bit. Write the new value to the microcode.
7769 */
7770static void
7771advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask)
7772{
7773 unsigned short cfg_word;
7774 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
7775 if ((cfg_word & tidmask) != 0)
7776 return;
1da177e4 7777
51219358
MW		 7778 cfg_word |= tidmask;
7779 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
1da177e4 7780
27c868c2 7781 /*
51219358
MW		 7782 * Clear the microcode "SDTR negotiation" done indicator for the
7783 * target to cause it to negotiate with the new setting set above.
27c868c2 7784 */
51219358
MW		 7785 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7786 cfg_word &= ~tidmask;
7787 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7788}
27c868c2 7789
51219358
MW		 7790/*
7791 * PPR (Parallel Protocol Request) Capable
7792 *
7793 * If the device supports DT mode, then it must be PPR capable.
7794 * The PPR message will be used in place of the SDTR and WDTR
7795 * messages to negotiate synchronous speed and offset, transfer
7796 * width, and protocol options.
7797 */
7798static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc,
7799 AdvPortAddr iop_base, unsigned short tidmask)
7800{
7801 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
7802 adv_dvc->ppr_able |= tidmask;
7803 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
7804}
27c868c2 7805
51219358
MW		 7806static void
7807advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc)
7808{
7809 AdvPortAddr iop_base = adv_dvc->iop_base;
7810 unsigned short tidmask = 1 << sdev->id;
7811
7812 if (sdev->lun == 0) {
7813 /*
7814 * Handle WDTR, SDTR, and Tag Queuing. If the feature
7815 * is enabled in the EEPROM and the device supports the
7816 * feature, then enable it in the microcode.
7817 */
27c868c2 7818
51219358
MW		 7819 if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr)
7820 advansys_wide_enable_wdtr(iop_base, tidmask);
7821 if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr)
7822 advansys_wide_enable_sdtr(iop_base, tidmask);
7823 if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr)
7824 advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask);
7825
7826 /*
7827 * Tag Queuing is disabled for the BIOS which runs in polled
7828 * mode and would see no benefit from Tag Queuing. Also by
7829 * disabling Tag Queuing in the BIOS devices with Tag Queuing
7830 * bugs will at least work with the BIOS.
7831 */
7832 if ((adv_dvc->tagqng_able & tidmask) &&
7833 sdev->tagged_supported) {
7834 unsigned short cfg_word;
7835 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
7836 cfg_word |= tidmask;
7837 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
7838 cfg_word);
7839 AdvWriteByteLram(iop_base,
7840 ASC_MC_NUMBER_OF_MAX_CMD + sdev->id,
7841 adv_dvc->max_dvc_qng);
27c868c2
MW		 7842 }
7843 }
1da177e4 7844
db5ed4df
CH		 7845 if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported)
7846 scsi_change_queue_depth(sdev, adv_dvc->max_dvc_qng);
51219358 7847}
27c868c2 7848
51219358
MW		 7849/*
7850 * Set the number of commands to queue per device for the
7851 * specified host adapter.
7852 */
7853static int advansys_slave_configure(struct scsi_device *sdev)
7854{
d2411495 7855 struct asc_board *boardp = shost_priv(sdev->host);
27c868c2 7856
51219358
MW		 7857 if (ASC_NARROW_BOARD(boardp))
7858 advansys_narrow_slave_configure(sdev,
7859 &boardp->dvc_var.asc_dvc_var);
7860 else
7861 advansys_wide_slave_configure(sdev,
7862 &boardp->dvc_var.adv_dvc_var);
1da177e4 7863
51219358
MW		 7864 return 0;
7865}
27c868c2 7866
b249c7fd
MW		 7867static __le32 advansys_get_sense_buffer_dma(struct scsi_cmnd *scp)
7868{
7869 struct asc_board *board = shost_priv(scp->device->host);
7870 scp->SCp.dma_handle = dma_map_single(board->dev, scp->sense_buffer,
b80ca4f7 7871 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
b249c7fd 7872 dma_cache_sync(board->dev, scp->sense_buffer,
b80ca4f7 7873 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
b249c7fd
MW		 7874 return cpu_to_le32(scp->SCp.dma_handle);
7875}
7876
d2411495 7877static int asc_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
05848b6e 7878 struct asc_scsi_q *asc_scsi_q)
51219358 7879{
b249c7fd 7880 struct asc_dvc_var *asc_dvc = &boardp->dvc_var.asc_dvc_var;
52c334e9
MW		 7881 int use_sg;
7882
05848b6e 7883 memset(asc_scsi_q, 0, sizeof(*asc_scsi_q));
27c868c2
MW		 7884
7885 /*
51219358 7886 * Point the ASC_SCSI_Q to the 'struct scsi_cmnd'.
27c868c2 7887 */
b249c7fd
MW		 7888 asc_scsi_q->q2.srb_ptr = advansys_ptr_to_srb(asc_dvc, scp);
7889 if (asc_scsi_q->q2.srb_ptr == BAD_SRB) {
7890 scp->result = HOST_BYTE(DID_SOFT_ERROR);
7891 return ASC_ERROR;
7892 }
27c868c2
MW		 7893
7894 /*
51219358 7895 * Build the ASC_SCSI_Q request.
27c868c2 7896 */
05848b6e
MW		 7897 asc_scsi_q->cdbptr = &scp->cmnd[0];
7898 asc_scsi_q->q2.cdb_len = scp->cmd_len;
7899 asc_scsi_q->q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
7900 asc_scsi_q->q1.target_lun = scp->device->lun;
7901 asc_scsi_q->q2.target_ix =
51219358 7902 ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
b249c7fd 7903 asc_scsi_q->q1.sense_addr = advansys_get_sense_buffer_dma(scp);
b80ca4f7 7904 asc_scsi_q->q1.sense_len = SCSI_SENSE_BUFFERSIZE;
27c868c2
MW		 7905
7906 /*
51219358
MW		 7907 * If there are any outstanding requests for the current target,
7908 * then every 255th request send an ORDERED request. This heuristic
7909 * tries to retain the benefit of request sorting while preventing
7910 * request starvation. 255 is the max number of tags or pending commands
7911 * a device may have outstanding.
7912 *
7913 * The request count is incremented below for every successfully
7914 * started request.
27c868c2 7915 *
27c868c2 7916 */
b249c7fd 7917 if ((asc_dvc->cur_dvc_qng[scp->device->id] > 0) &&
51219358 7918 (boardp->reqcnt[scp->device->id] % 255) == 0) {
68d81f40 7919 asc_scsi_q->q2.tag_code = ORDERED_QUEUE_TAG;
51219358 7920 } else {
68d81f40 7921 asc_scsi_q->q2.tag_code = SIMPLE_QUEUE_TAG;
51219358 7922 }
27c868c2 7923
52c334e9
MW		 7924 /* Build ASC_SCSI_Q */
7925 use_sg = scsi_dma_map(scp);
7926 if (use_sg != 0) {
51219358 7927 int sgcnt;
51219358 7928 struct scatterlist *slp;
05848b6e 7929 struct asc_sg_head *asc_sg_head;
27c868c2 7930
51219358 7931 if (use_sg > scp->device->host->sg_tablesize) {
9d0e96eb
MW		 7932 scmd_printk(KERN_ERR, scp, "use_sg %d > "
7933 "sg_tablesize %d\n", use_sg,
7934 scp->device->host->sg_tablesize);
52c334e9 7935 scsi_dma_unmap(scp);
51219358
MW		 7936 scp->result = HOST_BYTE(DID_ERROR);
7937 return ASC_ERROR;
7938 }
27c868c2 7939
05848b6e
MW		 7940 asc_sg_head = kzalloc(sizeof(asc_scsi_q->sg_head) +
7941 use_sg * sizeof(struct asc_sg_list), GFP_ATOMIC);
7942 if (!asc_sg_head) {
52c334e9 7943 scsi_dma_unmap(scp);
05848b6e
MW		 7944 scp->result = HOST_BYTE(DID_SOFT_ERROR);
7945 return ASC_ERROR;
7946 }
51219358 7947
05848b6e
MW		 7948 asc_scsi_q->q1.cntl |= QC_SG_HEAD;
7949 asc_scsi_q->sg_head = asc_sg_head;
7950 asc_scsi_q->q1.data_cnt = 0;
7951 asc_scsi_q->q1.data_addr = 0;
51219358 7952 /* This is a byte value, otherwise it would need to be swapped. */
05848b6e 7953 asc_sg_head->entry_cnt = asc_scsi_q->q1.sg_queue_cnt = use_sg;
52c334e9 7954 ASC_STATS_ADD(scp->device->host, xfer_elem,
05848b6e 7955 asc_sg_head->entry_cnt);
51219358
MW		 7956
7957 /*
7958 * Convert scatter-gather list into ASC_SG_HEAD list.
7959 */
52c334e9 7960 scsi_for_each_sg(scp, slp, use_sg, sgcnt) {
05848b6e 7961 asc_sg_head->sg_list[sgcnt].addr =
51219358 7962 cpu_to_le32(sg_dma_address(slp));
05848b6e 7963 asc_sg_head->sg_list[sgcnt].bytes =
51219358 7964 cpu_to_le32(sg_dma_len(slp));
52c334e9
MW		 7965 ASC_STATS_ADD(scp->device->host, xfer_sect,
7966 DIV_ROUND_UP(sg_dma_len(slp), 512));
27c868c2
MW		 7967 }
7968 }
1da177e4 7969
52c334e9
MW		 7970 ASC_STATS(scp->device->host, xfer_cnt);
7971
b352f923 7972 ASC_DBG_PRT_ASC_SCSI_Q(2, asc_scsi_q);
51219358
MW		 7973 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
7974
7975 return ASC_NOERROR;
27c868c2 7976}
1da177e4 7977
27c868c2 7978/*
51219358 7979 * Build scatter-gather list for Adv Library (Wide Board).
27c868c2 7980 *
51219358
MW		 7981 * Additional ADV_SG_BLOCK structures will need to be allocated
7982 * if the total number of scatter-gather elements exceeds
7983 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
7984 * assumed to be physically contiguous.
27c868c2 7985 *
51219358
MW		 7986 * Return:
7987 * ADV_SUCCESS(1) - SG List successfully created
7988 * ADV_ERROR(-1) - SG List creation failed
27c868c2 7989 */
51219358 7990static int
d2411495 7991adv_get_sglist(struct asc_board *boardp, adv_req_t *reqp, struct scsi_cmnd *scp,
51219358 7992 int use_sg)
27c868c2 7993{
51219358
MW		 7994 adv_sgblk_t *sgblkp;
7995 ADV_SCSI_REQ_Q *scsiqp;
7996 struct scatterlist *slp;
7997 int sg_elem_cnt;
7998 ADV_SG_BLOCK *sg_block, *prev_sg_block;
7999 ADV_PADDR sg_block_paddr;
27c868c2 8000 int i;
27c868c2 8001
51219358 8002 scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
52c334e9 8003 slp = scsi_sglist(scp);
51219358
MW		 8004 sg_elem_cnt = use_sg;
8005 prev_sg_block = NULL;
8006 reqp->sgblkp = NULL;
1da177e4 8007
51219358
MW		 8008 for (;;) {
8009 /*
8010 * Allocate a 'adv_sgblk_t' structure from the board free
8011 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
8012 * (15) scatter-gather elements.
8013 */
8014 if ((sgblkp = boardp->adv_sgblkp) == NULL) {
b352f923 8015 ASC_DBG(1, "no free adv_sgblk_t\n");
51219358 8016 ASC_STATS(scp->device->host, adv_build_nosg);
1da177e4 8017
51219358
MW		 8018 /*
8019 * Allocation failed. Free 'adv_sgblk_t' structures
8020 * already allocated for the request.
8021 */
8022 while ((sgblkp = reqp->sgblkp) != NULL) {
8023 /* Remove 'sgblkp' from the request list. */
8024 reqp->sgblkp = sgblkp->next_sgblkp;
27c868c2 8025
51219358
MW		 8026 /* Add 'sgblkp' to the board free list. */
8027 sgblkp->next_sgblkp = boardp->adv_sgblkp;
8028 boardp->adv_sgblkp = sgblkp;
8029 }
8030 return ASC_BUSY;
8031 }
1da177e4 8032
51219358
MW		 8033 /* Complete 'adv_sgblk_t' board allocation. */
8034 boardp->adv_sgblkp = sgblkp->next_sgblkp;
8035 sgblkp->next_sgblkp = NULL;
1da177e4 8036
51219358
MW		 8037 /*
8038 * Get 8 byte aligned virtual and physical addresses
8039 * for the allocated ADV_SG_BLOCK structure.
8040 */
8041 sg_block = (ADV_SG_BLOCK *)ADV_8BALIGN(&sgblkp->sg_block);
8042 sg_block_paddr = virt_to_bus(sg_block);
27c868c2 8043
51219358
MW		 8044 /*
8045 * Check if this is the first 'adv_sgblk_t' for the
8046 * request.
8047 */
8048 if (reqp->sgblkp == NULL) {
8049 /* Request's first scatter-gather block. */
8050 reqp->sgblkp = sgblkp;
27c868c2 8051
51219358
MW		 8052 /*
8053 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
8054 * address pointers.
8055 */
8056 scsiqp->sg_list_ptr = sg_block;
8057 scsiqp->sg_real_addr = cpu_to_le32(sg_block_paddr);
8058 } else {
8059 /* Request's second or later scatter-gather block. */
8060 sgblkp->next_sgblkp = reqp->sgblkp;
8061 reqp->sgblkp = sgblkp;
8062
8063 /*
8064 * Point the previous ADV_SG_BLOCK structure to
8065 * the newly allocated ADV_SG_BLOCK structure.
8066 */
8067 prev_sg_block->sg_ptr = cpu_to_le32(sg_block_paddr);
27c868c2 8068 }
1da177e4 8069
51219358
MW		 8070 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
8071 sg_block->sg_list[i].sg_addr =
8072 cpu_to_le32(sg_dma_address(slp));
8073 sg_block->sg_list[i].sg_count =
8074 cpu_to_le32(sg_dma_len(slp));
52c334e9
MW		 8075 ASC_STATS_ADD(scp->device->host, xfer_sect,
8076 DIV_ROUND_UP(sg_dma_len(slp), 512));
27c868c2 8077
51219358
MW		 8078 if (--sg_elem_cnt == 0) { /* Last ADV_SG_BLOCK and scatter-gather entry. */
8079 sg_block->sg_cnt = i + 1;
8080 sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */
8081 return ADV_SUCCESS;
8082 }
8083 slp++;
8084 }
8085 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
8086 prev_sg_block = sg_block;
27c868c2 8087 }
51219358 8088}
1da177e4 8089
51219358
MW		 8090/*
8091 * Build a request structure for the Adv Library (Wide Board).
8092 *
8093 * If an adv_req_t can not be allocated to issue the request,
8094 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
8095 *
8096 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the
8097 * microcode for DMA addresses or math operations are byte swapped
8098 * to little-endian order.
8099 */
8100static int
d2411495 8101adv_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
51219358
MW		 8102 ADV_SCSI_REQ_Q **adv_scsiqpp)
8103{
8104 adv_req_t *reqp;
8105 ADV_SCSI_REQ_Q *scsiqp;
8106 int i;
8107 int ret;
52c334e9 8108 int use_sg;
1da177e4 8109
27c868c2 8110 /*
51219358
MW		 8111 * Allocate an adv_req_t structure from the board to execute
8112 * the command.
27c868c2 8113 */
51219358 8114 if (boardp->adv_reqp == NULL) {
b352f923 8115 ASC_DBG(1, "no free adv_req_t\n");
51219358
MW		 8116 ASC_STATS(scp->device->host, adv_build_noreq);
8117 return ASC_BUSY;
8118 } else {
8119 reqp = boardp->adv_reqp;
8120 boardp->adv_reqp = reqp->next_reqp;
8121 reqp->next_reqp = NULL;
27c868c2 8122 }
1da177e4 8123
27c868c2 8124 /*
51219358 8125 * Get 32-byte aligned ADV_SCSI_REQ_Q and ADV_SG_BLOCK pointers.
27c868c2 8126 */
51219358 8127 scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
27c868c2
MW		 8128
8129 /*
51219358 8130 * Initialize the structure.
27c868c2 8131 */
51219358 8132 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
27c868c2
MW		 8133
8134 /*
51219358 8135 * Set the ADV_SCSI_REQ_Q 'srb_ptr' to point to the adv_req_t structure.
27c868c2 8136 */
b249c7fd 8137 scsiqp->srb_ptr = ADV_VADDR_TO_U32(reqp);
27c868c2
MW		 8138
8139 /*
51219358 8140 * Set the adv_req_t 'cmndp' to point to the struct scsi_cmnd structure.
27c868c2 8141 */
51219358 8142 reqp->cmndp = scp;
27c868c2
MW		 8143
8144 /*
51219358 8145 * Build the ADV_SCSI_REQ_Q request.
27c868c2 8146 */
51219358
MW		 8147
8148 /* Set CDB length and copy it to the request structure. */
8149 scsiqp->cdb_len = scp->cmd_len;
8150 /* Copy first 12 CDB bytes to cdb[]. */
8151 for (i = 0; i < scp->cmd_len && i < 12; i++) {
8152 scsiqp->cdb[i] = scp->cmnd[i];
8153 }
8154 /* Copy last 4 CDB bytes, if present, to cdb16[]. */
8155 for (; i < scp->cmd_len; i++) {
8156 scsiqp->cdb16[i - 12] = scp->cmnd[i];
27c868c2 8157 }
1da177e4 8158
51219358
MW		 8159 scsiqp->target_id = scp->device->id;
8160 scsiqp->target_lun = scp->device->lun;
8161
8162 scsiqp->sense_addr = cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
b80ca4f7 8163 scsiqp->sense_len = SCSI_SENSE_BUFFERSIZE;
27c868c2 8164
52c334e9 8165 /* Build ADV_SCSI_REQ_Q */
51219358 8166
52c334e9
MW		 8167 use_sg = scsi_dma_map(scp);
8168 if (use_sg == 0) {
8169 /* Zero-length transfer */
51219358 8170 reqp->sgblkp = NULL;
52c334e9
MW		 8171 scsiqp->data_cnt = 0;
8172 scsiqp->vdata_addr = NULL;
8173
8174 scsiqp->data_addr = 0;
51219358
MW		 8175 scsiqp->sg_list_ptr = NULL;
8176 scsiqp->sg_real_addr = 0;
51219358 8177 } else {
51219358 8178 if (use_sg > ADV_MAX_SG_LIST) {
9d0e96eb
MW		 8179 scmd_printk(KERN_ERR, scp, "use_sg %d > "
8180 "ADV_MAX_SG_LIST %d\n", use_sg,
51219358 8181 scp->device->host->sg_tablesize);
52c334e9 8182 scsi_dma_unmap(scp);
51219358
MW		 8183 scp->result = HOST_BYTE(DID_ERROR);
8184
8185 /*
8186 * Free the 'adv_req_t' structure by adding it back
8187 * to the board free list.
8188 */
8189 reqp->next_reqp = boardp->adv_reqp;
8190 boardp->adv_reqp = reqp;
8191
8192 return ASC_ERROR;
8193 }
8194
52c334e9
MW		 8195 scsiqp->data_cnt = cpu_to_le32(scsi_bufflen(scp));
8196
51219358
MW		 8197 ret = adv_get_sglist(boardp, reqp, scp, use_sg);
8198 if (ret != ADV_SUCCESS) {
8199 /*
8200 * Free the adv_req_t structure by adding it back to
8201 * the board free list.
8202 */
8203 reqp->next_reqp = boardp->adv_reqp;
8204 boardp->adv_reqp = reqp;
8205
8206 return ret;
8207 }
8208
52c334e9 8209 ASC_STATS_ADD(scp->device->host, xfer_elem, use_sg);
27c868c2 8210 }
1da177e4 8211
52c334e9
MW		 8212 ASC_STATS(scp->device->host, xfer_cnt);
8213
51219358
MW		 8214 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
8215 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
27c868c2 8216
51219358 8217 *adv_scsiqpp = scsiqp;
27c868c2 8218
51219358
MW		 8219 return ASC_NOERROR;
8220}
8221
8222static int AscSgListToQueue(int sg_list)
8223{
8224 int n_sg_list_qs;
8225
8226 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
8227 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
8228 n_sg_list_qs++;
8229 return n_sg_list_qs + 1;
8230}
8231
8232static uint
8233AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs)
8234{
8235 uint cur_used_qs;
8236 uint cur_free_qs;
8237 ASC_SCSI_BIT_ID_TYPE target_id;
8238 uchar tid_no;
8239
8240 target_id = ASC_TIX_TO_TARGET_ID(target_ix);
8241 tid_no = ASC_TIX_TO_TID(target_ix);
8242 if ((asc_dvc->unit_not_ready & target_id) ||
8243 (asc_dvc->queue_full_or_busy & target_id)) {
8244 return 0;
8245 }
8246 if (n_qs == 1) {
8247 cur_used_qs = (uint) asc_dvc->cur_total_qng +
8248 (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q;
8249 } else {
8250 cur_used_qs = (uint) asc_dvc->cur_total_qng +
8251 (uint) ASC_MIN_FREE_Q;
8252 }
8253 if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
8254 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
8255 if (asc_dvc->cur_dvc_qng[tid_no] >=
8256 asc_dvc->max_dvc_qng[tid_no]) {
8257 return 0;
8258 }
8259 return cur_free_qs;
8260 }
8261 if (n_qs > 1) {
8262 if ((n_qs > asc_dvc->last_q_shortage)
8263 && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
8264 asc_dvc->last_q_shortage = n_qs;
8265 }
8266 }
8267 return 0;
8268}
8269
8270static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head)
8271{
8272 ushort q_addr;
8273 uchar next_qp;
8274 uchar q_status;
8275
8276 q_addr = ASC_QNO_TO_QADDR(free_q_head);
8277 q_status = (uchar)AscReadLramByte(iop_base,
8278 (ushort)(q_addr +
8279 ASC_SCSIQ_B_STATUS));
8280 next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD));
8281 if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END))
8282 return next_qp;
8283 return ASC_QLINK_END;
8284}
8285
8286static uchar
8287AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q)
8288{
8289 uchar i;
27c868c2 8290
51219358
MW		 8291 for (i = 0; i < n_free_q; i++) {
8292 free_q_head = AscAllocFreeQueue(iop_base, free_q_head);
8293 if (free_q_head == ASC_QLINK_END)
8294 break;
8295 }
8296 return free_q_head;
8297}
27c868c2 8298
51219358
MW		 8299/*
8300 * void
8301 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8302 *
8303 * Calling/Exit State:
8304 * none
8305 *
8306 * Description:
8307 * Output an ASC_SCSI_Q structure to the chip
8308 */
8309static void
8310DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8311{
8312 int i;
8313
8314 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
8315 AscSetChipLramAddr(iop_base, s_addr);
8316 for (i = 0; i < 2 * words; i += 2) {
8317 if (i == 4 || i == 20) {
8318 continue;
8319 }
8320 outpw(iop_base + IOP_RAM_DATA,
8321 ((ushort)outbuf[i + 1] << 8) | outbuf[i]);
27c868c2 8322 }
51219358 8323}
1da177e4 8324
51219358
MW		 8325static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
8326{
8327 ushort q_addr;
8328 uchar tid_no;
8329 uchar sdtr_data;
8330 uchar syn_period_ix;
8331 uchar syn_offset;
8332 PortAddr iop_base;
8333
8334 iop_base = asc_dvc->iop_base;
8335 if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
8336 ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
8337 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
8338 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8339 syn_period_ix =
8340 (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
8341 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
8342 AscMsgOutSDTR(asc_dvc,
8343 asc_dvc->sdtr_period_tbl[syn_period_ix],
8344 syn_offset);
8345 scsiq->q1.cntl |= QC_MSG_OUT;
8346 }
8347 q_addr = ASC_QNO_TO_QADDR(q_no);
8348 if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
68d81f40 8349 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG;
27c868c2 8350 }
51219358
MW		 8351 scsiq->q1.status = QS_FREE;
8352 AscMemWordCopyPtrToLram(iop_base,
8353 q_addr + ASC_SCSIQ_CDB_BEG,
8354 (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1);
8355
8356 DvcPutScsiQ(iop_base,
8357 q_addr + ASC_SCSIQ_CPY_BEG,
8358 (uchar *)&scsiq->q1.cntl,
8359 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
8360 AscWriteLramWord(iop_base,
8361 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS),
8362 (ushort)(((ushort)scsiq->q1.
8363 q_no << 8) | (ushort)QS_READY));
8364 return 1;
8365}
8366
8367static int
8368AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
8369{
8370 int sta;
8371 int i;
8372 ASC_SG_HEAD *sg_head;
8373 ASC_SG_LIST_Q scsi_sg_q;
8374 ASC_DCNT saved_data_addr;
8375 ASC_DCNT saved_data_cnt;
8376 PortAddr iop_base;
8377 ushort sg_list_dwords;
8378 ushort sg_index;
8379 ushort sg_entry_cnt;
8380 ushort q_addr;
8381 uchar next_qp;
1da177e4 8382
51219358
MW		 8383 iop_base = asc_dvc->iop_base;
8384 sg_head = scsiq->sg_head;
8385 saved_data_addr = scsiq->q1.data_addr;
8386 saved_data_cnt = scsiq->q1.data_cnt;
8387 scsiq->q1.data_addr = (ASC_PADDR) sg_head->sg_list[0].addr;
8388 scsiq->q1.data_cnt = (ASC_DCNT) sg_head->sg_list[0].bytes;
8389#if CC_VERY_LONG_SG_LIST
27c868c2 8390 /*
51219358
MW		 8391 * If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST
8392 * then not all SG elements will fit in the allocated queues.
8393 * The rest of the SG elements will be copied when the RISC
8394 * completes the SG elements that fit and halts.
27c868c2 8395 */
51219358
MW		 8396 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
8397 /*
8398 * Set sg_entry_cnt to be the number of SG elements that
8399 * will fit in the allocated SG queues. It is minus 1, because
8400 * the first SG element is handled above. ASC_MAX_SG_LIST is
8401 * already inflated by 1 to account for this. For example it
8402 * may be 50 which is 1 + 7 queues * 7 SG elements.
8403 */
8404 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
27c868c2 8405
51219358
MW		 8406 /*
8407 * Keep track of remaining number of SG elements that will
8408 * need to be handled from a_isr.c.
8409 */
8410 scsiq->remain_sg_entry_cnt =
8411 sg_head->entry_cnt - ASC_MAX_SG_LIST;
8412 } else {
8413#endif /* CC_VERY_LONG_SG_LIST */
8414 /*
8415 * Set sg_entry_cnt to be the number of SG elements that
8416 * will fit in the allocated SG queues. It is minus 1, because
8417 * the first SG element is handled above.
8418 */
8419 sg_entry_cnt = sg_head->entry_cnt - 1;
8420#if CC_VERY_LONG_SG_LIST
8421 }
8422#endif /* CC_VERY_LONG_SG_LIST */
8423 if (sg_entry_cnt != 0) {
8424 scsiq->q1.cntl |= QC_SG_HEAD;
8425 q_addr = ASC_QNO_TO_QADDR(q_no);
8426 sg_index = 1;
8427 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
8428 scsi_sg_q.sg_head_qp = q_no;
8429 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
8430 for (i = 0; i < sg_head->queue_cnt; i++) {
8431 scsi_sg_q.seq_no = i + 1;
8432 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
8433 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
8434 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
8435 if (i == 0) {
8436 scsi_sg_q.sg_list_cnt =
8437 ASC_SG_LIST_PER_Q;
8438 scsi_sg_q.sg_cur_list_cnt =
8439 ASC_SG_LIST_PER_Q;
8440 } else {
8441 scsi_sg_q.sg_list_cnt =
8442 ASC_SG_LIST_PER_Q - 1;
8443 scsi_sg_q.sg_cur_list_cnt =
8444 ASC_SG_LIST_PER_Q - 1;
8445 }
8446 } else {
8447#if CC_VERY_LONG_SG_LIST
8448 /*
8449 * This is the last SG queue in the list of
8450 * allocated SG queues. If there are more
8451 * SG elements than will fit in the allocated
8452 * queues, then set the QCSG_SG_XFER_MORE flag.
8453 */
8454 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
8455 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
8456 } else {
8457#endif /* CC_VERY_LONG_SG_LIST */
8458 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
8459#if CC_VERY_LONG_SG_LIST
8460 }
8461#endif /* CC_VERY_LONG_SG_LIST */
8462 sg_list_dwords = sg_entry_cnt << 1;
8463 if (i == 0) {
8464 scsi_sg_q.sg_list_cnt = sg_entry_cnt;
8465 scsi_sg_q.sg_cur_list_cnt =
8466 sg_entry_cnt;
8467 } else {
8468 scsi_sg_q.sg_list_cnt =
8469 sg_entry_cnt - 1;
8470 scsi_sg_q.sg_cur_list_cnt =
8471 sg_entry_cnt - 1;
8472 }
8473 sg_entry_cnt = 0;
8474 }
8475 next_qp = AscReadLramByte(iop_base,
8476 (ushort)(q_addr +
8477 ASC_SCSIQ_B_FWD));
8478 scsi_sg_q.q_no = next_qp;
8479 q_addr = ASC_QNO_TO_QADDR(next_qp);
8480 AscMemWordCopyPtrToLram(iop_base,
8481 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
8482 (uchar *)&scsi_sg_q,
8483 sizeof(ASC_SG_LIST_Q) >> 1);
8484 AscMemDWordCopyPtrToLram(iop_base,
8485 q_addr + ASC_SGQ_LIST_BEG,
8486 (uchar *)&sg_head->
8487 sg_list[sg_index],
8488 sg_list_dwords);
8489 sg_index += ASC_SG_LIST_PER_Q;
8490 scsiq->next_sg_index = sg_index;
27c868c2 8491 }
51219358
MW		 8492 } else {
8493 scsiq->q1.cntl &= ~QC_SG_HEAD;
27c868c2 8494 }
51219358
MW		 8495 sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
8496 scsiq->q1.data_addr = saved_data_addr;
8497 scsiq->q1.data_cnt = saved_data_cnt;
8498 return (sta);
8499}
27c868c2 8500
51219358
MW		 8501static int
8502AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required)
8503{
8504 PortAddr iop_base;
8505 uchar free_q_head;
8506 uchar next_qp;
8507 uchar tid_no;
8508 uchar target_ix;
8509 int sta;
27c868c2 8510
51219358
MW		 8511 iop_base = asc_dvc->iop_base;
8512 target_ix = scsiq->q2.target_ix;
8513 tid_no = ASC_TIX_TO_TID(target_ix);
8514 sta = 0;
8515 free_q_head = (uchar)AscGetVarFreeQHead(iop_base);
8516 if (n_q_required > 1) {
8517 next_qp = AscAllocMultipleFreeQueue(iop_base, free_q_head,
8518 (uchar)n_q_required);
8519 if (next_qp != ASC_QLINK_END) {
8520 asc_dvc->last_q_shortage = 0;
8521 scsiq->sg_head->queue_cnt = n_q_required - 1;
8522 scsiq->q1.q_no = free_q_head;
8523 sta = AscPutReadySgListQueue(asc_dvc, scsiq,
8524 free_q_head);
8525 }
8526 } else if (n_q_required == 1) {
8527 next_qp = AscAllocFreeQueue(iop_base, free_q_head);
8528 if (next_qp != ASC_QLINK_END) {
8529 scsiq->q1.q_no = free_q_head;
8530 sta = AscPutReadyQueue(asc_dvc, scsiq, free_q_head);
27c868c2
MW		 8531 }
8532 }
51219358
MW		 8533 if (sta == 1) {
8534 AscPutVarFreeQHead(iop_base, next_qp);
8535 asc_dvc->cur_total_qng += n_q_required;
8536 asc_dvc->cur_dvc_qng[tid_no]++;
27c868c2 8537 }
51219358
MW		 8538 return sta;
8539}
27c868c2 8540
51219358
MW		 8541#define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16
8542static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = {
8543 INQUIRY,
8544 REQUEST_SENSE,
8545 READ_CAPACITY,
8546 READ_TOC,
8547 MODE_SELECT,
8548 MODE_SENSE,
8549 MODE_SELECT_10,
8550 MODE_SENSE_10,
8551 0xFF,
8552 0xFF,
8553 0xFF,
8554 0xFF,
8555 0xFF,
8556 0xFF,
8557 0xFF,
8558 0xFF
8559};
27c868c2 8560
51219358
MW		 8561static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
8562{
8563 PortAddr iop_base;
8564 int sta;
8565 int n_q_required;
8566 int disable_syn_offset_one_fix;
8567 int i;
8568 ASC_PADDR addr;
8569 ushort sg_entry_cnt = 0;
8570 ushort sg_entry_cnt_minus_one = 0;
8571 uchar target_ix;
8572 uchar tid_no;
8573 uchar sdtr_data;
8574 uchar extra_bytes;
8575 uchar scsi_cmd;
8576 uchar disable_cmd;
8577 ASC_SG_HEAD *sg_head;
8578 ASC_DCNT data_cnt;
27c868c2 8579
51219358
MW		 8580 iop_base = asc_dvc->iop_base;
8581 sg_head = scsiq->sg_head;
8582 if (asc_dvc->err_code != 0)
8583 return (ERR);
8584 scsiq->q1.q_no = 0;
8585 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
8586 scsiq->q1.extra_bytes = 0;
27c868c2 8587 }
51219358
MW		 8588 sta = 0;
8589 target_ix = scsiq->q2.target_ix;
8590 tid_no = ASC_TIX_TO_TID(target_ix);
8591 n_q_required = 1;
8592 if (scsiq->cdbptr[0] == REQUEST_SENSE) {
8593 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
8594 asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
8595 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8596 AscMsgOutSDTR(asc_dvc,
8597 asc_dvc->
8598 sdtr_period_tbl[(sdtr_data >> 4) &
8599 (uchar)(asc_dvc->
8600 max_sdtr_index -
8601 1)],
8602 (uchar)(sdtr_data & (uchar)
8603 ASC_SYN_MAX_OFFSET));
8604 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
8605 }
8606 }
8607 if (asc_dvc->in_critical_cnt != 0) {
8608 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
8609 return (ERR);
8610 }
8611 asc_dvc->in_critical_cnt++;
8612 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
8613 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
8614 asc_dvc->in_critical_cnt--;
8615 return (ERR);
8616 }
8617#if !CC_VERY_LONG_SG_LIST
8618 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
8619 asc_dvc->in_critical_cnt--;
8620 return (ERR);
8621 }
8622#endif /* !CC_VERY_LONG_SG_LIST */
8623 if (sg_entry_cnt == 1) {
8624 scsiq->q1.data_addr =
8625 (ADV_PADDR)sg_head->sg_list[0].addr;
8626 scsiq->q1.data_cnt =
8627 (ADV_DCNT)sg_head->sg_list[0].bytes;
8628 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
8629 }
8630 sg_entry_cnt_minus_one = sg_entry_cnt - 1;
8631 }
8632 scsi_cmd = scsiq->cdbptr[0];
8633 disable_syn_offset_one_fix = FALSE;
8634 if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
8635 !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
8636 if (scsiq->q1.cntl & QC_SG_HEAD) {
8637 data_cnt = 0;
8638 for (i = 0; i < sg_entry_cnt; i++) {
8639 data_cnt +=
8640 (ADV_DCNT)le32_to_cpu(sg_head->sg_list[i].
8641 bytes);
8642 }
8643 } else {
8644 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
8645 }
8646 if (data_cnt != 0UL) {
8647 if (data_cnt < 512UL) {
8648 disable_syn_offset_one_fix = TRUE;
8649 } else {
8650 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST;
8651 i++) {
8652 disable_cmd =
8653 _syn_offset_one_disable_cmd[i];
8654 if (disable_cmd == 0xFF) {
8655 break;
8656 }
8657 if (scsi_cmd == disable_cmd) {
8658 disable_syn_offset_one_fix =
8659 TRUE;
8660 break;
8661 }
8662 }
8663 }
8664 }
8665 }
8666 if (disable_syn_offset_one_fix) {
68d81f40 8667 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG;
51219358
MW		 8668 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
8669 ASC_TAG_FLAG_DISABLE_DISCONNECT);
8670 } else {
8671 scsiq->q2.tag_code &= 0x27;
8672 }
8673 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
8674 if (asc_dvc->bug_fix_cntl) {
8675 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
8676 if ((scsi_cmd == READ_6) ||
8677 (scsi_cmd == READ_10)) {
8678 addr =
8679 (ADV_PADDR)le32_to_cpu(sg_head->
8680 sg_list
8681 [sg_entry_cnt_minus_one].
8682 addr) +
8683 (ADV_DCNT)le32_to_cpu(sg_head->
8684 sg_list
8685 [sg_entry_cnt_minus_one].
8686 bytes);
8687 extra_bytes =
8688 (uchar)((ushort)addr & 0x0003);
8689 if ((extra_bytes != 0)
8690 &&
8691 ((scsiq->q2.
8692 tag_code &
8693 ASC_TAG_FLAG_EXTRA_BYTES)
8694 == 0)) {
8695 scsiq->q2.tag_code |=
8696 ASC_TAG_FLAG_EXTRA_BYTES;
8697 scsiq->q1.extra_bytes =
8698 extra_bytes;
8699 data_cnt =
8700 le32_to_cpu(sg_head->
8701 sg_list
8702 [sg_entry_cnt_minus_one].
8703 bytes);
8704 data_cnt -=
8705 (ASC_DCNT) extra_bytes;
8706 sg_head->
8707 sg_list
8708 [sg_entry_cnt_minus_one].
8709 bytes =
8710 cpu_to_le32(data_cnt);
8711 }
8712 }
8713 }
8714 }
8715 sg_head->entry_to_copy = sg_head->entry_cnt;
8716#if CC_VERY_LONG_SG_LIST
27c868c2 8717 /*
51219358
MW		 8718 * Set the sg_entry_cnt to the maximum possible. The rest of
8719 * the SG elements will be copied when the RISC completes the
8720 * SG elements that fit and halts.
27c868c2 8721 */
51219358
MW		 8722 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
8723 sg_entry_cnt = ASC_MAX_SG_LIST;
8724 }
8725#endif /* CC_VERY_LONG_SG_LIST */
8726 n_q_required = AscSgListToQueue(sg_entry_cnt);
8727 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
8728 (uint) n_q_required)
8729 || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
8730 if ((sta =
8731 AscSendScsiQueue(asc_dvc, scsiq,
8732 n_q_required)) == 1) {
8733 asc_dvc->in_critical_cnt--;
8734 return (sta);
27c868c2 8735 }
51219358
MW		 8736 }
8737 } else {
8738 if (asc_dvc->bug_fix_cntl) {
8739 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
8740 if ((scsi_cmd == READ_6) ||
8741 (scsi_cmd == READ_10)) {
8742 addr =
8743 le32_to_cpu(scsiq->q1.data_addr) +
8744 le32_to_cpu(scsiq->q1.data_cnt);
8745 extra_bytes =
8746 (uchar)((ushort)addr & 0x0003);
8747 if ((extra_bytes != 0)
8748 &&
8749 ((scsiq->q2.
8750 tag_code &
8751 ASC_TAG_FLAG_EXTRA_BYTES)
8752 == 0)) {
8753 data_cnt =
8754 le32_to_cpu(scsiq->q1.
8755 data_cnt);
8756 if (((ushort)data_cnt & 0x01FF)
8757 == 0) {
8758 scsiq->q2.tag_code |=
8759 ASC_TAG_FLAG_EXTRA_BYTES;
8760 data_cnt -= (ASC_DCNT)
8761 extra_bytes;
8762 scsiq->q1.data_cnt =
8763 cpu_to_le32
8764 (data_cnt);
8765 scsiq->q1.extra_bytes =
8766 extra_bytes;
8767 }
8768 }
8769 }
8770 }
8771 }
8772 n_q_required = 1;
8773 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
8774 ((scsiq->q1.cntl & QC_URGENT) != 0)) {
8775 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
8776 n_q_required)) == 1) {
8777 asc_dvc->in_critical_cnt--;
8778 return (sta);
27c868c2
MW		 8779 }
8780 }
8781 }
51219358
MW		 8782 asc_dvc->in_critical_cnt--;
8783 return (sta);
1da177e4
LT		 8784}
8785
8786/*
51219358 8787 * AdvExeScsiQueue() - Send a request to the RISC microcode program.
1da177e4 8788 *
51219358
MW		 8789 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
8790 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
8791 * RISC to notify it a new command is ready to be executed.
8792 *
8793 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
8794 * set to SCSI_MAX_RETRY.
8795 *
8796 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode
8797 * for DMA addresses or math operations are byte swapped to little-endian
8798 * order.
8799 *
8800 * Return:
8801 * ADV_SUCCESS(1) - The request was successfully queued.
8802 * ADV_BUSY(0) - Resource unavailable; Retry again after pending
8803 * request completes.
8804 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure
8805 * host IC error.
8806 */
8807static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq)
8808{
8809 AdvPortAddr iop_base;
51219358
MW		 8810 ADV_PADDR req_paddr;
8811 ADV_CARR_T *new_carrp;
1da177e4 8812
27c868c2 8813 /*
51219358 8814 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
27c868c2 8815 */
51219358
MW		 8816 if (scsiq->target_id > ADV_MAX_TID) {
8817 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
8818 scsiq->done_status = QD_WITH_ERROR;
27c868c2
MW		 8819 return ADV_ERROR;
8820 }
1da177e4 8821
51219358 8822 iop_base = asc_dvc->iop_base;
1da177e4 8823
27c868c2 8824 /*
51219358
MW		 8825 * Allocate a carrier ensuring at least one carrier always
8826 * remains on the freelist and initialize fields.
27c868c2 8827 */
51219358
MW		 8828 if ((new_carrp = asc_dvc->carr_freelist) == NULL) {
8829 return ADV_BUSY;
27c868c2 8830 }
51219358
MW		 8831 asc_dvc->carr_freelist = (ADV_CARR_T *)
8832 ADV_U32_TO_VADDR(le32_to_cpu(new_carrp->next_vpa));
8833 asc_dvc->carr_pending_cnt++;
1da177e4 8834
27c868c2 8835 /*
51219358
MW		 8836 * Set the carrier to be a stopper by setting 'next_vpa'
8837 * to the stopper value. The current stopper will be changed
8838 * below to point to the new stopper.
27c868c2 8839 */
51219358 8840 new_carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
27c868c2
MW		 8841
8842 /*
51219358 8843 * Clear the ADV_SCSI_REQ_Q done flag.
27c868c2 8844 */
51219358 8845 scsiq->a_flag &= ~ADV_SCSIQ_DONE;
27c868c2 8846
fd625f47 8847 req_paddr = virt_to_bus(scsiq);
51219358 8848 BUG_ON(req_paddr & 31);
51219358
MW		 8849 /* Wait for assertion before making little-endian */
8850 req_paddr = cpu_to_le32(req_paddr);
27c868c2 8851
51219358
MW		 8852 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
8853 scsiq->scsiq_ptr = cpu_to_le32(ADV_VADDR_TO_U32(scsiq));
8854 scsiq->scsiq_rptr = req_paddr;
8855
8856 scsiq->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->icq_sp));
27c868c2 8857 /*
51219358
MW		 8858 * Every ADV_CARR_T.carr_pa is byte swapped to little-endian
8859 * order during initialization.
27c868c2 8860 */
51219358 8861 scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
1da177e4 8862
27c868c2 8863 /*
51219358
MW		 8864 * Use the current stopper to send the ADV_SCSI_REQ_Q command to
8865 * the microcode. The newly allocated stopper will become the new
8866 * stopper.
27c868c2 8867 */
51219358 8868 asc_dvc->icq_sp->areq_vpa = req_paddr;
1da177e4 8869
27c868c2 8870 /*
51219358
MW		 8871 * Set the 'next_vpa' pointer for the old stopper to be the
8872 * physical address of the new stopper. The RISC can only
8873 * follow physical addresses.
27c868c2 8874 */
51219358 8875 asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
27c868c2
MW		 8876
8877 /*
51219358 8878 * Set the host adapter stopper pointer to point to the new carrier.
27c868c2 8879 */
51219358
MW		 8880 asc_dvc->icq_sp = new_carrp;
8881
8882 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
8883 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
8884 /*
8885 * Tickle the RISC to tell it to read its Command Queue Head pointer.
8886 */
8887 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
8888 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
8889 /*
8890 * Clear the tickle value. In the ASC-3550 the RISC flag
8891 * command 'clr_tickle_a' does not work unless the host
8892 * value is cleared.
8893 */
8894 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
8895 ADV_TICKLE_NOP);
8896 }
8897 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8898 /*
8899 * Notify the RISC a carrier is ready by writing the physical
8900 * address of the new carrier stopper to the COMMA register.
8901 */
8902 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
8903 le32_to_cpu(new_carrp->carr_pa));
27c868c2 8904 }
1da177e4 8905
51219358
MW		 8906 return ADV_SUCCESS;
8907}
8908
8909/*
8910 * Execute a single 'Scsi_Cmnd'.
51219358
MW		 8911 */
8912static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
8913{
41d2493d 8914 int ret, err_code;
d2411495 8915 struct asc_board *boardp = shost_priv(scp->device->host);
51219358 8916
b352f923 8917 ASC_DBG(1, "scp 0x%p\n", scp);
27c868c2 8918
51219358 8919 if (ASC_NARROW_BOARD(boardp)) {
41d2493d 8920 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
05848b6e 8921 struct asc_scsi_q asc_scsi_q;
27c868c2 8922
41d2493d 8923 /* asc_build_req() can not return ASC_BUSY. */
05848b6e
MW		 8924 ret = asc_build_req(boardp, scp, &asc_scsi_q);
8925 if (ret == ASC_ERROR) {
51219358
MW		 8926 ASC_STATS(scp->device->host, build_error);
8927 return ASC_ERROR;
8928 }
1da177e4 8929
41d2493d 8930 ret = AscExeScsiQueue(asc_dvc, &asc_scsi_q);
05848b6e 8931 kfree(asc_scsi_q.sg_head);
41d2493d 8932 err_code = asc_dvc->err_code;
51219358 8933 } else {
41d2493d
MW		 8934 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
8935 ADV_SCSI_REQ_Q *adv_scsiqp;
27c868c2 8936
51219358
MW		 8937 switch (adv_build_req(boardp, scp, &adv_scsiqp)) {
8938 case ASC_NOERROR:
b352f923 8939 ASC_DBG(3, "adv_build_req ASC_NOERROR\n");
51219358
MW		 8940 break;
8941 case ASC_BUSY:
b352f923 8942 ASC_DBG(1, "adv_build_req ASC_BUSY\n");
51219358
MW		 8943 /*
8944 * The asc_stats fields 'adv_build_noreq' and
8945 * 'adv_build_nosg' count wide board busy conditions.
8946 * They are updated in adv_build_req and
8947 * adv_get_sglist, respectively.
8948 */
8949 return ASC_BUSY;
8950 case ASC_ERROR:
8951 default:
b352f923 8952 ASC_DBG(1, "adv_build_req ASC_ERROR\n");
51219358
MW		 8953 ASC_STATS(scp->device->host, build_error);
8954 return ASC_ERROR;
8955 }
8956
41d2493d
MW		 8957 ret = AdvExeScsiQueue(adv_dvc, adv_scsiqp);
8958 err_code = adv_dvc->err_code;
8959 }
8960
8961 switch (ret) {
8962 case ASC_NOERROR:
8963 ASC_STATS(scp->device->host, exe_noerror);
8964 /*
8965 * Increment monotonically increasing per device
8966 * successful request counter. Wrapping doesn't matter.
8967 */
8968 boardp->reqcnt[scp->device->id]++;
b352f923 8969 ASC_DBG(1, "ExeScsiQueue() ASC_NOERROR\n");
41d2493d
MW		 8970 break;
8971 case ASC_BUSY:
8972 ASC_STATS(scp->device->host, exe_busy);
8973 break;
8974 case ASC_ERROR:
9d0e96eb
MW		 8975 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() ASC_ERROR, "
8976 "err_code 0x%x\n", err_code);
41d2493d
MW		 8977 ASC_STATS(scp->device->host, exe_error);
8978 scp->result = HOST_BYTE(DID_ERROR);
8979 break;
8980 default:
9d0e96eb
MW		 8981 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() unknown, "
8982 "err_code 0x%x\n", err_code);
41d2493d
MW		 8983 ASC_STATS(scp->device->host, exe_unknown);
8984 scp->result = HOST_BYTE(DID_ERROR);
8985 break;
27c868c2 8986 }
1da177e4 8987
b352f923 8988 ASC_DBG(1, "end\n");
51219358
MW		 8989 return ret;
8990}
27c868c2 8991
51219358
MW		 8992/*
8993 * advansys_queuecommand() - interrupt-driven I/O entrypoint.
8994 *
8995 * This function always returns 0. Command return status is saved
8996 * in the 'scp' result field.
8997 */
8998static int
f281233d 8999advansys_queuecommand_lck(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *))
51219358
MW		 9000{
9001 struct Scsi_Host *shost = scp->device->host;
51219358 9002 int asc_res, result = 0;
27c868c2 9003
51219358
MW		 9004 ASC_STATS(shost, queuecommand);
9005 scp->scsi_done = done;
27c868c2 9006
51219358 9007 asc_res = asc_execute_scsi_cmnd(scp);
51219358
MW		 9008
9009 switch (asc_res) {
9010 case ASC_NOERROR:
9011 break;
9012 case ASC_BUSY:
9013 result = SCSI_MLQUEUE_HOST_BUSY;
9014 break;
9015 case ASC_ERROR:
9016 default:
9017 asc_scsi_done(scp);
9018 break;
9019 }
9020
9021 return result;
9022}
9023
f281233d
JG		 9024static DEF_SCSI_QCMD(advansys_queuecommand)
9025
6f039790 9026static ushort AscGetEisaChipCfg(PortAddr iop_base)
51219358
MW		 9027{
9028 PortAddr eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
9029 (PortAddr) (ASC_EISA_CFG_IOP_MASK);
9030 return inpw(eisa_cfg_iop);
9031}
9032
9033/*
9034 * Return the BIOS address of the adapter at the specified
9035 * I/O port and with the specified bus type.
9036 */
6f039790
GKH		 9037static unsigned short AscGetChipBiosAddress(PortAddr iop_base,
9038 unsigned short bus_type)
51219358
MW		 9039{
9040 unsigned short cfg_lsw;
9041 unsigned short bios_addr;
27c868c2
MW		 9042
9043 /*
51219358
MW		 9044 * The PCI BIOS is re-located by the motherboard BIOS. Because
9045 * of this the driver can not determine where a PCI BIOS is
9046 * loaded and executes.
27c868c2 9047 */
51219358
MW		 9048 if (bus_type & ASC_IS_PCI)
9049 return 0;
27c868c2 9050
51219358
MW		 9051 if ((bus_type & ASC_IS_EISA) != 0) {
9052 cfg_lsw = AscGetEisaChipCfg(iop_base);
9053 cfg_lsw &= 0x000F;
9054 bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE;
9055 return bios_addr;
9056 }
27c868c2 9057
51219358 9058 cfg_lsw = AscGetChipCfgLsw(iop_base);
27c868c2
MW		 9059
9060 /*
51219358 9061 * ISA PnP uses the top bit as the 32K BIOS flag
27c868c2 9062 */
51219358
MW		 9063 if (bus_type == ASC_IS_ISAPNP)
9064 cfg_lsw &= 0x7FFF;
9065 bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE;
9066 return bios_addr;
9067}
9068
6f039790 9069static uchar AscSetChipScsiID(PortAddr iop_base, uchar new_host_id)
51219358
MW		 9070{
9071 ushort cfg_lsw;
9072
9073 if (AscGetChipScsiID(iop_base) == new_host_id) {
9074 return (new_host_id);
27c868c2 9075 }
51219358
MW		 9076 cfg_lsw = AscGetChipCfgLsw(iop_base);
9077 cfg_lsw &= 0xF8FF;
9078 cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8);
9079 AscSetChipCfgLsw(iop_base, cfg_lsw);
9080 return (AscGetChipScsiID(iop_base));
9081}
27c868c2 9082
6f039790 9083static unsigned char AscGetChipScsiCtrl(PortAddr iop_base)
51219358
MW		 9084{
9085 unsigned char sc;
27c868c2 9086
51219358
MW		 9087 AscSetBank(iop_base, 1);
9088 sc = inp(iop_base + IOP_REG_SC);
9089 AscSetBank(iop_base, 0);
9090 return sc;
9091}
27c868c2 9092
6f039790
GKH		 9093static unsigned char AscGetChipVersion(PortAddr iop_base,
9094 unsigned short bus_type)
51219358
MW		 9095{
9096 if (bus_type & ASC_IS_EISA) {
9097 PortAddr eisa_iop;
9098 unsigned char revision;
9099 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
9100 (PortAddr) ASC_EISA_REV_IOP_MASK;
9101 revision = inp(eisa_iop);
9102 return ASC_CHIP_MIN_VER_EISA - 1 + revision;
27c868c2 9103 }
51219358
MW		 9104 return AscGetChipVerNo(iop_base);
9105}
27c868c2 9106
51219358 9107#ifdef CONFIG_ISA
6f039790 9108static void AscEnableIsaDma(uchar dma_channel)
51219358
MW		 9109{
9110 if (dma_channel < 4) {
9111 outp(0x000B, (ushort)(0xC0 | dma_channel));
9112 outp(0x000A, dma_channel);
9113 } else if (dma_channel < 8) {
9114 outp(0x00D6, (ushort)(0xC0 | (dma_channel - 4)));
9115 outp(0x00D4, (ushort)(dma_channel - 4));
9116 }
51219358
MW		 9117}
9118#endif /* CONFIG_ISA */
9119
9120static int AscStopQueueExe(PortAddr iop_base)
9121{
9122 int count = 0;
9123
9124 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
9125 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
9126 ASC_STOP_REQ_RISC_STOP);
9127 do {
9128 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
9129 ASC_STOP_ACK_RISC_STOP) {
9130 return (1);
9131 }
9132 mdelay(100);
9133 } while (count++ < 20);
9134 }
9135 return (0);
9136}
9137
6f039790 9138static ASC_DCNT AscGetMaxDmaCount(ushort bus_type)
51219358
MW		 9139{
9140 if (bus_type & ASC_IS_ISA)
9141 return ASC_MAX_ISA_DMA_COUNT;
9142 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
9143 return ASC_MAX_VL_DMA_COUNT;
9144 return ASC_MAX_PCI_DMA_COUNT;
27c868c2 9145}
1da177e4 9146
51219358 9147#ifdef CONFIG_ISA
6f039790 9148static ushort AscGetIsaDmaChannel(PortAddr iop_base)
27c868c2 9149{
51219358 9150 ushort channel;
1da177e4 9151
51219358
MW		 9152 channel = AscGetChipCfgLsw(iop_base) & 0x0003;
9153 if (channel == 0x03)
9154 return (0);
9155 else if (channel == 0x00)
9156 return (7);
9157 return (channel + 4);
9158}
1da177e4 9159
6f039790 9160static ushort AscSetIsaDmaChannel(PortAddr iop_base, ushort dma_channel)
51219358
MW		 9161{
9162 ushort cfg_lsw;
9163 uchar value;
1da177e4 9164
51219358
MW		 9165 if ((dma_channel >= 5) && (dma_channel <= 7)) {
9166 if (dma_channel == 7)
9167 value = 0x00;
9168 else
9169 value = dma_channel - 4;
9170 cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
9171 cfg_lsw |= value;
9172 AscSetChipCfgLsw(iop_base, cfg_lsw);
9173 return (AscGetIsaDmaChannel(iop_base));
9174 }
9175 return 0;
9176}
1da177e4 9177
6f039790 9178static uchar AscGetIsaDmaSpeed(PortAddr iop_base)
51219358
MW		 9179{
9180 uchar speed_value;
1da177e4 9181
51219358
MW		 9182 AscSetBank(iop_base, 1);
9183 speed_value = AscReadChipDmaSpeed(iop_base);
9184 speed_value &= 0x07;
9185 AscSetBank(iop_base, 0);
9186 return speed_value;
9187}
1da177e4 9188
6f039790 9189static uchar AscSetIsaDmaSpeed(PortAddr iop_base, uchar speed_value)
51219358
MW		 9190{
9191 speed_value &= 0x07;
9192 AscSetBank(iop_base, 1);
9193 AscWriteChipDmaSpeed(iop_base, speed_value);
9194 AscSetBank(iop_base, 0);
9195 return AscGetIsaDmaSpeed(iop_base);
9196}
9197#endif /* CONFIG_ISA */
1da177e4 9198
6f039790 9199static ushort AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
51219358
MW		 9200{
9201 int i;
9202 PortAddr iop_base;
9203 ushort warn_code;
9204 uchar chip_version;
1da177e4 9205
51219358
MW		 9206 iop_base = asc_dvc->iop_base;
9207 warn_code = 0;
9208 asc_dvc->err_code = 0;
9209 if ((asc_dvc->bus_type &
9210 (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
9211 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
27c868c2 9212 }
51219358
MW		 9213 AscSetChipControl(iop_base, CC_HALT);
9214 AscSetChipStatus(iop_base, 0);
9215 asc_dvc->bug_fix_cntl = 0;
9216 asc_dvc->pci_fix_asyn_xfer = 0;
9217 asc_dvc->pci_fix_asyn_xfer_always = 0;
421f91d2 9218 /* asc_dvc->init_state initialized in AscInitGetConfig(). */
51219358
MW		 9219 asc_dvc->sdtr_done = 0;
9220 asc_dvc->cur_total_qng = 0;
9221 asc_dvc->is_in_int = 0;
9222 asc_dvc->in_critical_cnt = 0;
9223 asc_dvc->last_q_shortage = 0;
9224 asc_dvc->use_tagged_qng = 0;
9225 asc_dvc->no_scam = 0;
9226 asc_dvc->unit_not_ready = 0;
9227 asc_dvc->queue_full_or_busy = 0;
9228 asc_dvc->redo_scam = 0;
9229 asc_dvc->res2 = 0;
afbb68c3 9230 asc_dvc->min_sdtr_index = 0;
51219358
MW		 9231 asc_dvc->cfg->can_tagged_qng = 0;
9232 asc_dvc->cfg->cmd_qng_enabled = 0;
9233 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
9234 asc_dvc->init_sdtr = 0;
9235 asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
9236 asc_dvc->scsi_reset_wait = 3;
9237 asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
9238 asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
9239 asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
9240 asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
9241 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
51219358
MW		 9242 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
9243 asc_dvc->cfg->chip_version = chip_version;
afbb68c3 9244 asc_dvc->sdtr_period_tbl = asc_syn_xfer_period;
51219358
MW		 9245 asc_dvc->max_sdtr_index = 7;
9246 if ((asc_dvc->bus_type & ASC_IS_PCI) &&
9247 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
9248 asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
afbb68c3 9249 asc_dvc->sdtr_period_tbl = asc_syn_ultra_xfer_period;
51219358
MW		 9250 asc_dvc->max_sdtr_index = 15;
9251 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) {
9252 AscSetExtraControl(iop_base,
9253 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
9254 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
9255 AscSetExtraControl(iop_base,
9256 (SEC_ACTIVE_NEGATE |
9257 SEC_ENABLE_FILTER));
27c868c2
MW		 9258 }
9259 }
51219358
MW		 9260 if (asc_dvc->bus_type == ASC_IS_PCI) {
9261 AscSetExtraControl(iop_base,
9262 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
9263 }
1da177e4 9264
51219358
MW		 9265 asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
9266#ifdef CONFIG_ISA
9267 if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
9268 if (chip_version >= ASC_CHIP_MIN_VER_ISA_PNP) {
9269 AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
9270 asc_dvc->bus_type = ASC_IS_ISAPNP;
27c868c2 9271 }
51219358
MW		 9272 asc_dvc->cfg->isa_dma_channel =
9273 (uchar)AscGetIsaDmaChannel(iop_base);
27c868c2 9274 }
51219358
MW		 9275#endif /* CONFIG_ISA */
9276 for (i = 0; i <= ASC_MAX_TID; i++) {
9277 asc_dvc->cur_dvc_qng[i] = 0;
9278 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
9279 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L;
9280 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L;
9281 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
27c868c2 9282 }
51219358
MW		 9283 return warn_code;
9284}
1da177e4 9285
6f039790 9286static int AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg)
51219358
MW		 9287{
9288 int retry;
27c868c2 9289
51219358
MW		 9290 for (retry = 0; retry < ASC_EEP_MAX_RETRY; retry++) {
9291 unsigned char read_back;
9292 AscSetChipEEPCmd(iop_base, cmd_reg);
9293 mdelay(1);
9294 read_back = AscGetChipEEPCmd(iop_base);
9295 if (read_back == cmd_reg)
9296 return 1;
27c868c2 9297 }
51219358
MW		 9298 return 0;
9299}
1da177e4 9300
6f039790 9301static void AscWaitEEPRead(void)
51219358
MW		 9302{
9303 mdelay(1);
27c868c2 9304}
1da177e4 9305
6f039790 9306static ushort AscReadEEPWord(PortAddr iop_base, uchar addr)
27c868c2 9307{
51219358
MW		 9308 ushort read_wval;
9309 uchar cmd_reg;
27c868c2 9310
51219358
MW		 9311 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
9312 AscWaitEEPRead();
9313 cmd_reg = addr | ASC_EEP_CMD_READ;
9314 AscWriteEEPCmdReg(iop_base, cmd_reg);
9315 AscWaitEEPRead();
9316 read_wval = AscGetChipEEPData(iop_base);
9317 AscWaitEEPRead();
9318 return read_wval;
9319}
27c868c2 9320
6f039790
GKH		 9321static ushort AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9322 ushort bus_type)
51219358
MW		 9323{
9324 ushort wval;
9325 ushort sum;
9326 ushort *wbuf;
9327 int cfg_beg;
9328 int cfg_end;
9329 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
9330 int s_addr;
27c868c2 9331
51219358
MW		 9332 wbuf = (ushort *)cfg_buf;
9333 sum = 0;
9334 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
9335 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9336 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
9337 sum += *wbuf;
9338 }
9339 if (bus_type & ASC_IS_VL) {
9340 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9341 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9342 } else {
9343 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9344 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9345 }
9346 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9347 wval = AscReadEEPWord(iop_base, (uchar)s_addr);
9348 if (s_addr <= uchar_end_in_config) {
9349 /*
9350 * Swap all char fields - must unswap bytes already swapped
9351 * by AscReadEEPWord().
9352 */
9353 *wbuf = le16_to_cpu(wval);
9354 } else {
9355 /* Don't swap word field at the end - cntl field. */
9356 *wbuf = wval;
9357 }
9358 sum += wval; /* Checksum treats all EEPROM data as words. */
9359 }
27c868c2 9360 /*
51219358
MW		 9361 * Read the checksum word which will be compared against 'sum'
9362 * by the caller. Word field already swapped.
27c868c2 9363 */
51219358
MW		 9364 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
9365 return sum;
9366}
1da177e4 9367
6f039790 9368static int AscTestExternalLram(ASC_DVC_VAR *asc_dvc)
51219358
MW		 9369{
9370 PortAddr iop_base;
9371 ushort q_addr;
9372 ushort saved_word;
9373 int sta;
1da177e4 9374
51219358
MW		 9375 iop_base = asc_dvc->iop_base;
9376 sta = 0;
9377 q_addr = ASC_QNO_TO_QADDR(241);
9378 saved_word = AscReadLramWord(iop_base, q_addr);
9379 AscSetChipLramAddr(iop_base, q_addr);
9380 AscSetChipLramData(iop_base, 0x55AA);
9381 mdelay(10);
9382 AscSetChipLramAddr(iop_base, q_addr);
9383 if (AscGetChipLramData(iop_base) == 0x55AA) {
9384 sta = 1;
9385 AscWriteLramWord(iop_base, q_addr, saved_word);
9386 }
9387 return (sta);
9388}
1da177e4 9389
6f039790 9390static void AscWaitEEPWrite(void)
51219358
MW		 9391{
9392 mdelay(20);
51219358 9393}
1da177e4 9394
6f039790 9395static int AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg)
51219358
MW		 9396{
9397 ushort read_back;
9398 int retry;
1da177e4 9399
51219358
MW		 9400 retry = 0;
9401 while (TRUE) {
9402 AscSetChipEEPData(iop_base, data_reg);
9403 mdelay(1);
9404 read_back = AscGetChipEEPData(iop_base);
9405 if (read_back == data_reg) {
9406 return (1);
9407 }
9408 if (retry++ > ASC_EEP_MAX_RETRY) {
9409 return (0);
9410 }
27c868c2 9411 }
51219358 9412}
27c868c2 9413
6f039790 9414static ushort AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val)
51219358
MW		 9415{
9416 ushort read_wval;
9417
9418 read_wval = AscReadEEPWord(iop_base, addr);
9419 if (read_wval != word_val) {
9420 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
9421 AscWaitEEPRead();
9422 AscWriteEEPDataReg(iop_base, word_val);
9423 AscWaitEEPRead();
9424 AscWriteEEPCmdReg(iop_base,
9425 (uchar)((uchar)ASC_EEP_CMD_WRITE | addr));
9426 AscWaitEEPWrite();
9427 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
9428 AscWaitEEPRead();
9429 return (AscReadEEPWord(iop_base, addr));
9430 }
9431 return (read_wval);
9432}
9433
6f039790
GKH		 9434static int AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9435 ushort bus_type)
51219358
MW		 9436{
9437 int n_error;
9438 ushort *wbuf;
9439 ushort word;
9440 ushort sum;
9441 int s_addr;
9442 int cfg_beg;
9443 int cfg_end;
9444 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
9445
9446 wbuf = (ushort *)cfg_buf;
9447 n_error = 0;
9448 sum = 0;
9449 /* Write two config words; AscWriteEEPWord() will swap bytes. */
9450 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9451 sum += *wbuf;
9452 if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9453 n_error++;
27c868c2 9454 }
51219358
MW		 9455 }
9456 if (bus_type & ASC_IS_VL) {
9457 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9458 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9459 } else {
9460 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9461 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9462 }
9463 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9464 if (s_addr <= uchar_end_in_config) {
9465 /*
9466 * This is a char field. Swap char fields before they are
9467 * swapped again by AscWriteEEPWord().
9468 */
9469 word = cpu_to_le16(*wbuf);
9470 if (word !=
9471 AscWriteEEPWord(iop_base, (uchar)s_addr, word)) {
9472 n_error++;
9473 }
9474 } else {
9475 /* Don't swap word field at the end - cntl field. */
9476 if (*wbuf !=
9477 AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9478 n_error++;
9479 }
27c868c2 9480 }
51219358
MW		 9481 sum += *wbuf; /* Checksum calculated from word values. */
9482 }
9483 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
9484 *wbuf = sum;
9485 if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) {
9486 n_error++;
27c868c2 9487 }
1da177e4 9488
51219358
MW		 9489 /* Read EEPROM back again. */
9490 wbuf = (ushort *)cfg_buf;
27c868c2 9491 /*
51219358 9492 * Read two config words; Byte-swapping done by AscReadEEPWord().
27c868c2 9493 */
51219358
MW		 9494 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9495 if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) {
9496 n_error++;
27c868c2
MW		 9497 }
9498 }
51219358
MW		 9499 if (bus_type & ASC_IS_VL) {
9500 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9501 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9502 } else {
9503 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9504 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9505 }
9506 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9507 if (s_addr <= uchar_end_in_config) {
9508 /*
9509 * Swap all char fields. Must unswap bytes already swapped
9510 * by AscReadEEPWord().
9511 */
9512 word =
9513 le16_to_cpu(AscReadEEPWord
9514 (iop_base, (uchar)s_addr));
27c868c2 9515 } else {
51219358
MW		 9516 /* Don't swap word field at the end - cntl field. */
9517 word = AscReadEEPWord(iop_base, (uchar)s_addr);
9518 }
9519 if (*wbuf != word) {
9520 n_error++;
27c868c2
MW		 9521 }
9522 }
51219358
MW		 9523 /* Read checksum; Byte swapping not needed. */
9524 if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) {
9525 n_error++;
27c868c2 9526 }
51219358
MW		 9527 return n_error;
9528}
1da177e4 9529
6f039790
GKH		 9530static int AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9531 ushort bus_type)
51219358
MW		 9532{
9533 int retry;
9534 int n_error;
27c868c2 9535
51219358
MW		 9536 retry = 0;
9537 while (TRUE) {
9538 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
9539 bus_type)) == 0) {
9540 break;
9541 }
9542 if (++retry > ASC_EEP_MAX_RETRY) {
9543 break;
9544 }
9545 }
9546 return n_error;
9547}
27c868c2 9548
6f039790 9549static ushort AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
51219358
MW		 9550{
9551 ASCEEP_CONFIG eep_config_buf;
9552 ASCEEP_CONFIG *eep_config;
9553 PortAddr iop_base;
9554 ushort chksum;
9555 ushort warn_code;
9556 ushort cfg_msw, cfg_lsw;
9557 int i;
9558 int write_eep = 0;
27c868c2 9559
51219358
MW		 9560 iop_base = asc_dvc->iop_base;
9561 warn_code = 0;
9562 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
9563 AscStopQueueExe(iop_base);
9564 if ((AscStopChip(iop_base) == FALSE) ||
9565 (AscGetChipScsiCtrl(iop_base) != 0)) {
9566 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
9567 AscResetChipAndScsiBus(asc_dvc);
9568 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
9569 }
9570 if (AscIsChipHalted(iop_base) == FALSE) {
9571 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
9572 return (warn_code);
9573 }
9574 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
9575 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
9576 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
9577 return (warn_code);
9578 }
9579 eep_config = (ASCEEP_CONFIG *)&eep_config_buf;
9580 cfg_msw = AscGetChipCfgMsw(iop_base);
9581 cfg_lsw = AscGetChipCfgLsw(iop_base);
9582 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
9583 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9584 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
9585 AscSetChipCfgMsw(iop_base, cfg_msw);
9586 }
9587 chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
b352f923 9588 ASC_DBG(1, "chksum 0x%x\n", chksum);
51219358
MW		 9589 if (chksum == 0) {
9590 chksum = 0xaa55;
9591 }
9592 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
9593 warn_code |= ASC_WARN_AUTO_CONFIG;
9594 if (asc_dvc->cfg->chip_version == 3) {
9595 if (eep_config->cfg_lsw != cfg_lsw) {
9596 warn_code |= ASC_WARN_EEPROM_RECOVER;
9597 eep_config->cfg_lsw =
9598 AscGetChipCfgLsw(iop_base);
9599 }
9600 if (eep_config->cfg_msw != cfg_msw) {
9601 warn_code |= ASC_WARN_EEPROM_RECOVER;
9602 eep_config->cfg_msw =
9603 AscGetChipCfgMsw(iop_base);
9604 }
9605 }
9606 }
9607 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9608 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
b352f923 9609 ASC_DBG(1, "eep_config->chksum 0x%x\n", eep_config->chksum);
51219358
MW		 9610 if (chksum != eep_config->chksum) {
9611 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
9612 ASC_CHIP_VER_PCI_ULTRA_3050) {
b352f923 9613 ASC_DBG(1, "chksum error ignored; EEPROM-less board\n");
51219358
MW		 9614 eep_config->init_sdtr = 0xFF;
9615 eep_config->disc_enable = 0xFF;
9616 eep_config->start_motor = 0xFF;
9617 eep_config->use_cmd_qng = 0;
9618 eep_config->max_total_qng = 0xF0;
9619 eep_config->max_tag_qng = 0x20;
9620 eep_config->cntl = 0xBFFF;
9621 ASC_EEP_SET_CHIP_ID(eep_config, 7);
9622 eep_config->no_scam = 0;
9623 eep_config->adapter_info[0] = 0;
9624 eep_config->adapter_info[1] = 0;
9625 eep_config->adapter_info[2] = 0;
9626 eep_config->adapter_info[3] = 0;
9627 eep_config->adapter_info[4] = 0;
9628 /* Indicate EEPROM-less board. */
9629 eep_config->adapter_info[5] = 0xBB;
27c868c2 9630 } else {
51219358
MW		 9631 ASC_PRINT
9632 ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
9633 write_eep = 1;
9634 warn_code |= ASC_WARN_EEPROM_CHKSUM;
9635 }
9636 }
9637 asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
9638 asc_dvc->cfg->disc_enable = eep_config->disc_enable;
9639 asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
9640 asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
9641 asc_dvc->start_motor = eep_config->start_motor;
9642 asc_dvc->dvc_cntl = eep_config->cntl;
9643 asc_dvc->no_scam = eep_config->no_scam;
9644 asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
9645 asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
9646 asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
9647 asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
9648 asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
9649 asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
9650 if (!AscTestExternalLram(asc_dvc)) {
9651 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) ==
9652 ASC_IS_PCI_ULTRA)) {
9653 eep_config->max_total_qng =
9654 ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
9655 eep_config->max_tag_qng =
9656 ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
9657 } else {
9658 eep_config->cfg_msw |= 0x0800;
9659 cfg_msw |= 0x0800;
9660 AscSetChipCfgMsw(iop_base, cfg_msw);
9661 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
9662 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
27c868c2 9663 }
51219358
MW		 9664 } else {
9665 }
9666 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
9667 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
9668 }
9669 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
9670 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
9671 }
9672 if (eep_config->max_tag_qng > eep_config->max_total_qng) {
9673 eep_config->max_tag_qng = eep_config->max_total_qng;
9674 }
9675 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
9676 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
9677 }
9678 asc_dvc->max_total_qng = eep_config->max_total_qng;
9679 if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
9680 eep_config->use_cmd_qng) {
9681 eep_config->disc_enable = eep_config->use_cmd_qng;
9682 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
9683 }
51219358
MW		 9684 ASC_EEP_SET_CHIP_ID(eep_config,
9685 ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
9686 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
9687 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
9688 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
afbb68c3 9689 asc_dvc->min_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
27c868c2 9690 }
1da177e4 9691
51219358
MW		 9692 for (i = 0; i <= ASC_MAX_TID; i++) {
9693 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
9694 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
9695 asc_dvc->cfg->sdtr_period_offset[i] =
9696 (uchar)(ASC_DEF_SDTR_OFFSET |
afbb68c3 9697 (asc_dvc->min_sdtr_index << 4));
51219358
MW		 9698 }
9699 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
9700 if (write_eep) {
9701 if ((i = AscSetEEPConfig(iop_base, eep_config,
9702 asc_dvc->bus_type)) != 0) {
9703 ASC_PRINT1
9704 ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n",
9705 i);
27c868c2 9706 } else {
51219358
MW		 9707 ASC_PRINT
9708 ("AscInitFromEEP: Successfully re-wrote EEPROM.\n");
27c868c2
MW		 9709 }
9710 }
51219358 9711 return (warn_code);
1da177e4
LT		 9712}
9713
6f039790 9714static int AscInitGetConfig(struct Scsi_Host *shost)
1da177e4 9715{
9d0e96eb
MW		 9716 struct asc_board *board = shost_priv(shost);
9717 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
51219358 9718 unsigned short warn_code = 0;
27c868c2 9719
51219358
MW		 9720 asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
9721 if (asc_dvc->err_code != 0)
9722 return asc_dvc->err_code;
27c868c2 9723
51219358
MW		 9724 if (AscFindSignature(asc_dvc->iop_base)) {
9725 warn_code |= AscInitAscDvcVar(asc_dvc);
9726 warn_code |= AscInitFromEEP(asc_dvc);
9727 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
9728 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
9729 asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
9730 } else {
9731 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
9732 }
27c868c2 9733
51219358
MW		 9734 switch (warn_code) {
9735 case 0: /* No error */
9736 break;
9737 case ASC_WARN_IO_PORT_ROTATE:
9d0e96eb
MW		 9738 shost_printk(KERN_WARNING, shost, "I/O port address "
9739 "modified\n");
51219358
MW		 9740 break;
9741 case ASC_WARN_AUTO_CONFIG:
9d0e96eb
MW		 9742 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
9743 "enabled\n");
51219358
MW		 9744 break;
9745 case ASC_WARN_EEPROM_CHKSUM:
9d0e96eb 9746 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
51219358
MW		 9747 break;
9748 case ASC_WARN_IRQ_MODIFIED:
9d0e96eb 9749 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
51219358
MW		 9750 break;
9751 case ASC_WARN_CMD_QNG_CONFLICT:
9d0e96eb
MW		 9752 shost_printk(KERN_WARNING, shost, "tag queuing enabled w/o "
9753 "disconnects\n");
51219358
MW		 9754 break;
9755 default:
9d0e96eb
MW		 9756 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
9757 warn_code);
51219358
MW		 9758 break;
9759 }
1da177e4 9760
9d0e96eb
MW		 9761 if (asc_dvc->err_code != 0)
9762 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
9763 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
27c868c2 9764
51219358
MW		 9765 return asc_dvc->err_code;
9766}
1da177e4 9767
6f039790 9768static int AscInitSetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
51219358 9769{
9d0e96eb
MW		 9770 struct asc_board *board = shost_priv(shost);
9771 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
51219358
MW		 9772 PortAddr iop_base = asc_dvc->iop_base;
9773 unsigned short cfg_msw;
9774 unsigned short warn_code = 0;
1da177e4 9775
51219358
MW		 9776 asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
9777 if (asc_dvc->err_code != 0)
9778 return asc_dvc->err_code;
9779 if (!AscFindSignature(asc_dvc->iop_base)) {
9780 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
9781 return asc_dvc->err_code;
27c868c2 9782 }
1da177e4 9783
51219358
MW		 9784 cfg_msw = AscGetChipCfgMsw(iop_base);
9785 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
9786 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9787 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
9788 AscSetChipCfgMsw(iop_base, cfg_msw);
9789 }
9790 if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
9791 asc_dvc->cfg->cmd_qng_enabled) {
9792 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
9793 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
9794 }
9795 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
9796 warn_code |= ASC_WARN_AUTO_CONFIG;
9797 }
51219358
MW		 9798#ifdef CONFIG_PCI
9799 if (asc_dvc->bus_type & ASC_IS_PCI) {
9800 cfg_msw &= 0xFFC0;
9801 AscSetChipCfgMsw(iop_base, cfg_msw);
9802 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
27c868c2 9803 } else {
51219358
MW		 9804 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
9805 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
9806 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
9807 asc_dvc->bug_fix_cntl |=
9808 ASC_BUG_FIX_ASYN_USE_SYN;
9809 }
27c868c2 9810 }
51219358
MW		 9811 } else
9812#endif /* CONFIG_PCI */
9813 if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
9814 if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
9815 == ASC_CHIP_VER_ASYN_BUG) {
9816 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
27c868c2
MW		 9817 }
9818 }
51219358
MW		 9819 if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
9820 asc_dvc->cfg->chip_scsi_id) {
9821 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
9822 }
9823#ifdef CONFIG_ISA
9824 if (asc_dvc->bus_type & ASC_IS_ISA) {
9825 AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
9826 AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
9827 }
9828#endif /* CONFIG_ISA */
1da177e4 9829
51219358
MW		 9830 asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
9831
9832 switch (warn_code) {
9833 case 0: /* No error. */
9834 break;
9835 case ASC_WARN_IO_PORT_ROTATE:
9d0e96eb
MW		 9836 shost_printk(KERN_WARNING, shost, "I/O port address "
9837 "modified\n");
51219358
MW		 9838 break;
9839 case ASC_WARN_AUTO_CONFIG:
9d0e96eb
MW		 9840 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
9841 "enabled\n");
51219358
MW		 9842 break;
9843 case ASC_WARN_EEPROM_CHKSUM:
9d0e96eb 9844 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
51219358
MW		 9845 break;
9846 case ASC_WARN_IRQ_MODIFIED:
9d0e96eb 9847 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
51219358
MW		 9848 break;
9849 case ASC_WARN_CMD_QNG_CONFLICT:
9d0e96eb
MW		 9850 shost_printk(KERN_WARNING, shost, "tag queuing w/o "
9851 "disconnects\n");
51219358
MW		 9852 break;
9853 default:
9d0e96eb
MW		 9854 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
9855 warn_code);
51219358 9856 break;
27c868c2 9857 }
1da177e4 9858
9d0e96eb
MW		 9859 if (asc_dvc->err_code != 0)
9860 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
9861 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
27c868c2 9862
51219358
MW		 9863 return asc_dvc->err_code;
9864}
27c868c2 9865
51219358
MW		 9866/*
9867 * EEPROM Configuration.
9868 *
9869 * All drivers should use this structure to set the default EEPROM
9870 * configuration. The BIOS now uses this structure when it is built.
9871 * Additional structure information can be found in a_condor.h where
9872 * the structure is defined.
9873 *
9874 * The *_Field_IsChar structs are needed to correct for endianness.
9875 * These values are read from the board 16 bits at a time directly
9876 * into the structs. Because some fields are char, the values will be
9877 * in the wrong order. The *_Field_IsChar tells when to flip the
9878 * bytes. Data read and written to PCI memory is automatically swapped
9879 * on big-endian platforms so char fields read as words are actually being
9880 * unswapped on big-endian platforms.
9881 */
6f039790 9882static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config = {
51219358
MW		 9883 ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
9884 0x0000, /* cfg_msw */
9885 0xFFFF, /* disc_enable */
9886 0xFFFF, /* wdtr_able */
9887 0xFFFF, /* sdtr_able */
9888 0xFFFF, /* start_motor */
9889 0xFFFF, /* tagqng_able */
9890 0xFFFF, /* bios_scan */
9891 0, /* scam_tolerant */
9892 7, /* adapter_scsi_id */
9893 0, /* bios_boot_delay */
9894 3, /* scsi_reset_delay */
9895 0, /* bios_id_lun */
9896 0, /* termination */
9897 0, /* reserved1 */
9898 0xFFE7, /* bios_ctrl */
9899 0xFFFF, /* ultra_able */
9900 0, /* reserved2 */
9901 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */
9902 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9903 0, /* dvc_cntl */
9904 0, /* bug_fix */
9905 0, /* serial_number_word1 */
9906 0, /* serial_number_word2 */
9907 0, /* serial_number_word3 */
9908 0, /* check_sum */
9909 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9910 , /* oem_name[16] */
9911 0, /* dvc_err_code */
9912 0, /* adv_err_code */
9913 0, /* adv_err_addr */
9914 0, /* saved_dvc_err_code */
9915 0, /* saved_adv_err_code */
9916 0, /* saved_adv_err_addr */
9917 0 /* num_of_err */
9918};
27c868c2 9919
6f039790 9920static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar = {
51219358
MW		 9921 0, /* cfg_lsw */
9922 0, /* cfg_msw */
9923 0, /* -disc_enable */
9924 0, /* wdtr_able */
9925 0, /* sdtr_able */
9926 0, /* start_motor */
9927 0, /* tagqng_able */
9928 0, /* bios_scan */
9929 0, /* scam_tolerant */
9930 1, /* adapter_scsi_id */
9931 1, /* bios_boot_delay */
9932 1, /* scsi_reset_delay */
9933 1, /* bios_id_lun */
9934 1, /* termination */
9935 1, /* reserved1 */
9936 0, /* bios_ctrl */
9937 0, /* ultra_able */
9938 0, /* reserved2 */
9939 1, /* max_host_qng */
9940 1, /* max_dvc_qng */
9941 0, /* dvc_cntl */
9942 0, /* bug_fix */
9943 0, /* serial_number_word1 */
9944 0, /* serial_number_word2 */
9945 0, /* serial_number_word3 */
9946 0, /* check_sum */
9947 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
9948 , /* oem_name[16] */
9949 0, /* dvc_err_code */
9950 0, /* adv_err_code */
9951 0, /* adv_err_addr */
9952 0, /* saved_dvc_err_code */
9953 0, /* saved_adv_err_code */
9954 0, /* saved_adv_err_addr */
9955 0 /* num_of_err */
9956};
1da177e4 9957
6f039790 9958static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config = {
51219358
MW		 9959 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
9960 0x0000, /* 01 cfg_msw */
9961 0xFFFF, /* 02 disc_enable */
9962 0xFFFF, /* 03 wdtr_able */
9963 0x4444, /* 04 sdtr_speed1 */
9964 0xFFFF, /* 05 start_motor */
9965 0xFFFF, /* 06 tagqng_able */
9966 0xFFFF, /* 07 bios_scan */
9967 0, /* 08 scam_tolerant */
9968 7, /* 09 adapter_scsi_id */
9969 0, /* bios_boot_delay */
9970 3, /* 10 scsi_reset_delay */
9971 0, /* bios_id_lun */
9972 0, /* 11 termination_se */
9973 0, /* termination_lvd */
9974 0xFFE7, /* 12 bios_ctrl */
9975 0x4444, /* 13 sdtr_speed2 */
9976 0x4444, /* 14 sdtr_speed3 */
9977 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
9978 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9979 0, /* 16 dvc_cntl */
9980 0x4444, /* 17 sdtr_speed4 */
9981 0, /* 18 serial_number_word1 */
9982 0, /* 19 serial_number_word2 */
9983 0, /* 20 serial_number_word3 */
9984 0, /* 21 check_sum */
9985 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9986 , /* 22-29 oem_name[16] */
9987 0, /* 30 dvc_err_code */
9988 0, /* 31 adv_err_code */
9989 0, /* 32 adv_err_addr */
9990 0, /* 33 saved_dvc_err_code */
9991 0, /* 34 saved_adv_err_code */
9992 0, /* 35 saved_adv_err_addr */
9993 0, /* 36 reserved */
9994 0, /* 37 reserved */
9995 0, /* 38 reserved */
9996 0, /* 39 reserved */
9997 0, /* 40 reserved */
9998 0, /* 41 reserved */
9999 0, /* 42 reserved */
10000 0, /* 43 reserved */
10001 0, /* 44 reserved */
10002 0, /* 45 reserved */
10003 0, /* 46 reserved */
10004 0, /* 47 reserved */
10005 0, /* 48 reserved */
10006 0, /* 49 reserved */
10007 0, /* 50 reserved */
10008 0, /* 51 reserved */
10009 0, /* 52 reserved */
10010 0, /* 53 reserved */
10011 0, /* 54 reserved */
10012 0, /* 55 reserved */
10013 0, /* 56 cisptr_lsw */
10014 0, /* 57 cisprt_msw */
10015 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
10016 PCI_DEVICE_ID_38C0800_REV1, /* 59 subsysid */
10017 0, /* 60 reserved */
10018 0, /* 61 reserved */
10019 0, /* 62 reserved */
10020 0 /* 63 reserved */
10021};
27c868c2 10022
6f039790 10023static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar = {
51219358
MW		 10024 0, /* 00 cfg_lsw */
10025 0, /* 01 cfg_msw */
10026 0, /* 02 disc_enable */
10027 0, /* 03 wdtr_able */
10028 0, /* 04 sdtr_speed1 */
10029 0, /* 05 start_motor */
10030 0, /* 06 tagqng_able */
10031 0, /* 07 bios_scan */
10032 0, /* 08 scam_tolerant */
10033 1, /* 09 adapter_scsi_id */
10034 1, /* bios_boot_delay */
10035 1, /* 10 scsi_reset_delay */
10036 1, /* bios_id_lun */
10037 1, /* 11 termination_se */
10038 1, /* termination_lvd */
10039 0, /* 12 bios_ctrl */
10040 0, /* 13 sdtr_speed2 */
10041 0, /* 14 sdtr_speed3 */
10042 1, /* 15 max_host_qng */
10043 1, /* max_dvc_qng */
10044 0, /* 16 dvc_cntl */
10045 0, /* 17 sdtr_speed4 */
10046 0, /* 18 serial_number_word1 */
10047 0, /* 19 serial_number_word2 */
10048 0, /* 20 serial_number_word3 */
10049 0, /* 21 check_sum */
10050 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
10051 , /* 22-29 oem_name[16] */
10052 0, /* 30 dvc_err_code */
10053 0, /* 31 adv_err_code */
10054 0, /* 32 adv_err_addr */
10055 0, /* 33 saved_dvc_err_code */
10056 0, /* 34 saved_adv_err_code */
10057 0, /* 35 saved_adv_err_addr */
10058 0, /* 36 reserved */
10059 0, /* 37 reserved */
10060 0, /* 38 reserved */
10061 0, /* 39 reserved */
10062 0, /* 40 reserved */
10063 0, /* 41 reserved */
10064 0, /* 42 reserved */
10065 0, /* 43 reserved */
10066 0, /* 44 reserved */
10067 0, /* 45 reserved */
10068 0, /* 46 reserved */
10069 0, /* 47 reserved */
10070 0, /* 48 reserved */
10071 0, /* 49 reserved */
10072 0, /* 50 reserved */
10073 0, /* 51 reserved */
10074 0, /* 52 reserved */
10075 0, /* 53 reserved */
10076 0, /* 54 reserved */
10077 0, /* 55 reserved */
10078 0, /* 56 cisptr_lsw */
10079 0, /* 57 cisprt_msw */
10080 0, /* 58 subsysvid */
10081 0, /* 59 subsysid */
10082 0, /* 60 reserved */
10083 0, /* 61 reserved */
10084 0, /* 62 reserved */
10085 0 /* 63 reserved */
10086};
27c868c2 10087
6f039790 10088static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config = {
51219358
MW		 10089 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
10090 0x0000, /* 01 cfg_msw */
10091 0xFFFF, /* 02 disc_enable */
10092 0xFFFF, /* 03 wdtr_able */
10093 0x5555, /* 04 sdtr_speed1 */
10094 0xFFFF, /* 05 start_motor */
10095 0xFFFF, /* 06 tagqng_able */
10096 0xFFFF, /* 07 bios_scan */
10097 0, /* 08 scam_tolerant */
10098 7, /* 09 adapter_scsi_id */
10099 0, /* bios_boot_delay */
10100 3, /* 10 scsi_reset_delay */
10101 0, /* bios_id_lun */
10102 0, /* 11 termination_se */
10103 0, /* termination_lvd */
10104 0xFFE7, /* 12 bios_ctrl */
10105 0x5555, /* 13 sdtr_speed2 */
10106 0x5555, /* 14 sdtr_speed3 */
10107 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
10108 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
10109 0, /* 16 dvc_cntl */
10110 0x5555, /* 17 sdtr_speed4 */
10111 0, /* 18 serial_number_word1 */
10112 0, /* 19 serial_number_word2 */
10113 0, /* 20 serial_number_word3 */
10114 0, /* 21 check_sum */
10115 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
10116 , /* 22-29 oem_name[16] */
10117 0, /* 30 dvc_err_code */
10118 0, /* 31 adv_err_code */
10119 0, /* 32 adv_err_addr */
10120 0, /* 33 saved_dvc_err_code */
10121 0, /* 34 saved_adv_err_code */
10122 0, /* 35 saved_adv_err_addr */
10123 0, /* 36 reserved */
10124 0, /* 37 reserved */
10125 0, /* 38 reserved */
10126 0, /* 39 reserved */
10127 0, /* 40 reserved */
10128 0, /* 41 reserved */
10129 0, /* 42 reserved */
10130 0, /* 43 reserved */
10131 0, /* 44 reserved */
10132 0, /* 45 reserved */
10133 0, /* 46 reserved */
10134 0, /* 47 reserved */
10135 0, /* 48 reserved */
10136 0, /* 49 reserved */
10137 0, /* 50 reserved */
10138 0, /* 51 reserved */
10139 0, /* 52 reserved */
10140 0, /* 53 reserved */
10141 0, /* 54 reserved */
10142 0, /* 55 reserved */
10143 0, /* 56 cisptr_lsw */
10144 0, /* 57 cisprt_msw */
10145 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
10146 PCI_DEVICE_ID_38C1600_REV1, /* 59 subsysid */
10147 0, /* 60 reserved */
10148 0, /* 61 reserved */
10149 0, /* 62 reserved */
10150 0 /* 63 reserved */
10151};
1da177e4 10152
6f039790 10153static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar = {
51219358
MW		 10154 0, /* 00 cfg_lsw */
10155 0, /* 01 cfg_msw */
10156 0, /* 02 disc_enable */
10157 0, /* 03 wdtr_able */
10158 0, /* 04 sdtr_speed1 */
10159 0, /* 05 start_motor */
10160 0, /* 06 tagqng_able */
10161 0, /* 07 bios_scan */
10162 0, /* 08 scam_tolerant */
10163 1, /* 09 adapter_scsi_id */
10164 1, /* bios_boot_delay */
10165 1, /* 10 scsi_reset_delay */
10166 1, /* bios_id_lun */
10167 1, /* 11 termination_se */
10168 1, /* termination_lvd */
10169 0, /* 12 bios_ctrl */
10170 0, /* 13 sdtr_speed2 */
10171 0, /* 14 sdtr_speed3 */
10172 1, /* 15 max_host_qng */
10173 1, /* max_dvc_qng */
10174 0, /* 16 dvc_cntl */
10175 0, /* 17 sdtr_speed4 */
10176 0, /* 18 serial_number_word1 */
10177 0, /* 19 serial_number_word2 */
10178 0, /* 20 serial_number_word3 */
10179 0, /* 21 check_sum */
10180 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
10181 , /* 22-29 oem_name[16] */
10182 0, /* 30 dvc_err_code */
10183 0, /* 31 adv_err_code */
10184 0, /* 32 adv_err_addr */
10185 0, /* 33 saved_dvc_err_code */
10186 0, /* 34 saved_adv_err_code */
10187 0, /* 35 saved_adv_err_addr */
10188 0, /* 36 reserved */
10189 0, /* 37 reserved */
10190 0, /* 38 reserved */
10191 0, /* 39 reserved */
10192 0, /* 40 reserved */
10193 0, /* 41 reserved */
10194 0, /* 42 reserved */
10195 0, /* 43 reserved */
10196 0, /* 44 reserved */
10197 0, /* 45 reserved */
10198 0, /* 46 reserved */
10199 0, /* 47 reserved */
10200 0, /* 48 reserved */
10201 0, /* 49 reserved */
10202 0, /* 50 reserved */
10203 0, /* 51 reserved */
10204 0, /* 52 reserved */
10205 0, /* 53 reserved */
10206 0, /* 54 reserved */
10207 0, /* 55 reserved */
10208 0, /* 56 cisptr_lsw */
10209 0, /* 57 cisprt_msw */
10210 0, /* 58 subsysvid */
10211 0, /* 59 subsysid */
10212 0, /* 60 reserved */
10213 0, /* 61 reserved */
10214 0, /* 62 reserved */
10215 0 /* 63 reserved */
10216};
1da177e4 10217
51219358 10218#ifdef CONFIG_PCI
1da177e4 10219/*
51219358 10220 * Wait for EEPROM command to complete
1da177e4 10221 */
6f039790 10222static void AdvWaitEEPCmd(AdvPortAddr iop_base)
1da177e4 10223{
51219358 10224 int eep_delay_ms;
27c868c2 10225
51219358
MW		 10226 for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) {
10227 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) &
10228 ASC_EEP_CMD_DONE) {
10229 break;
27c868c2 10230 }
51219358 10231 mdelay(1);
27c868c2 10232 }
51219358
MW		 10233 if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) ==
10234 0)
10235 BUG();
1da177e4
LT		 10236}
10237
10238/*
51219358 10239 * Read the EEPROM from specified location
1da177e4 10240 */
6f039790 10241static ushort AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
51219358
MW		 10242{
10243 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10244 ASC_EEP_CMD_READ | eep_word_addr);
10245 AdvWaitEEPCmd(iop_base);
10246 return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
10247}
10248
10249/*
10250 * Write the EEPROM from 'cfg_buf'.
10251 */
6f039790
GKH		 10252static void AdvSet3550EEPConfig(AdvPortAddr iop_base,
10253 ADVEEP_3550_CONFIG *cfg_buf)
1da177e4 10254{
27c868c2 10255 ushort *wbuf;
51219358 10256 ushort addr, chksum;
27c868c2
MW		 10257 ushort *charfields;
10258
27c868c2 10259 wbuf = (ushort *)cfg_buf;
51219358 10260 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
27c868c2
MW		 10261 chksum = 0;
10262
51219358
MW		 10263 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10264 AdvWaitEEPCmd(iop_base);
10265
10266 /*
10267 * Write EEPROM from word 0 to word 20.
10268 */
10269 for (addr = ADV_EEP_DVC_CFG_BEGIN;
10270 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10271 ushort word;
10272
27c868c2 10273 if (*charfields++) {
51219358 10274 word = cpu_to_le16(*wbuf);
27c868c2 10275 } else {
51219358 10276 word = *wbuf;
27c868c2 10277 }
51219358
MW		 10278 chksum += *wbuf; /* Checksum is calculated from word values. */
10279 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10280 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10281 ASC_EEP_CMD_WRITE | addr);
10282 AdvWaitEEPCmd(iop_base);
10283 mdelay(ADV_EEP_DELAY_MS);
27c868c2 10284 }
51219358
MW		 10285
10286 /*
10287 * Write EEPROM checksum at word 21.
10288 */
10289 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10290 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10291 AdvWaitEEPCmd(iop_base);
27c868c2
MW		 10292 wbuf++;
10293 charfields++;
10294
51219358
MW		 10295 /*
10296 * Write EEPROM OEM name at words 22 to 29.
10297 */
10298 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10299 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10300 ushort word;
10301
27c868c2 10302 if (*charfields++) {
51219358
MW		 10303 word = cpu_to_le16(*wbuf);
10304 } else {
10305 word = *wbuf;
27c868c2 10306 }
51219358
MW		 10307 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10308 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10309 ASC_EEP_CMD_WRITE | addr);
10310 AdvWaitEEPCmd(iop_base);
27c868c2 10311 }
51219358
MW		 10312 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10313 AdvWaitEEPCmd(iop_base);
1da177e4
LT		 10314}
10315
10316/*
51219358 10317 * Write the EEPROM from 'cfg_buf'.
1da177e4 10318 */
6f039790
GKH		 10319static void AdvSet38C0800EEPConfig(AdvPortAddr iop_base,
10320 ADVEEP_38C0800_CONFIG *cfg_buf)
1da177e4 10321{
27c868c2 10322 ushort *wbuf;
27c868c2 10323 ushort *charfields;
51219358 10324 ushort addr, chksum;
27c868c2 10325
27c868c2 10326 wbuf = (ushort *)cfg_buf;
51219358 10327 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
27c868c2
MW		 10328 chksum = 0;
10329
51219358
MW		 10330 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10331 AdvWaitEEPCmd(iop_base);
10332
10333 /*
10334 * Write EEPROM from word 0 to word 20.
10335 */
10336 for (addr = ADV_EEP_DVC_CFG_BEGIN;
10337 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10338 ushort word;
10339
27c868c2 10340 if (*charfields++) {
51219358 10341 word = cpu_to_le16(*wbuf);
27c868c2 10342 } else {
51219358 10343 word = *wbuf;
27c868c2 10344 }
51219358
MW		 10345 chksum += *wbuf; /* Checksum is calculated from word values. */
10346 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10347 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10348 ASC_EEP_CMD_WRITE | addr);
10349 AdvWaitEEPCmd(iop_base);
10350 mdelay(ADV_EEP_DELAY_MS);
27c868c2 10351 }
51219358
MW		 10352
10353 /*
10354 * Write EEPROM checksum at word 21.
10355 */
10356 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10357 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10358 AdvWaitEEPCmd(iop_base);
27c868c2
MW		 10359 wbuf++;
10360 charfields++;
10361
51219358
MW		 10362 /*
10363 * Write EEPROM OEM name at words 22 to 29.
10364 */
10365 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10366 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10367 ushort word;
10368
27c868c2 10369 if (*charfields++) {
51219358
MW		 10370 word = cpu_to_le16(*wbuf);
10371 } else {
10372 word = *wbuf;
27c868c2 10373 }
51219358
MW		 10374 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10375 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10376 ASC_EEP_CMD_WRITE | addr);
10377 AdvWaitEEPCmd(iop_base);
27c868c2 10378 }
51219358 10379 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
27c868c2 10380 AdvWaitEEPCmd(iop_base);
1da177e4
LT		 10381}
10382
10383/*
10384 * Write the EEPROM from 'cfg_buf'.
10385 */
6f039790
GKH		 10386static void AdvSet38C1600EEPConfig(AdvPortAddr iop_base,
10387 ADVEEP_38C1600_CONFIG *cfg_buf)
1da177e4 10388{
27c868c2 10389 ushort *wbuf;
27c868c2 10390 ushort *charfields;
51219358 10391 ushort addr, chksum;
27c868c2
MW		 10392
10393 wbuf = (ushort *)cfg_buf;
51219358 10394 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
27c868c2
MW		 10395 chksum = 0;
10396
10397 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10398 AdvWaitEEPCmd(iop_base);
10399
10400 /*
10401 * Write EEPROM from word 0 to word 20.
10402 */
10403 for (addr = ADV_EEP_DVC_CFG_BEGIN;
10404 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10405 ushort word;
10406
10407 if (*charfields++) {
10408 word = cpu_to_le16(*wbuf);
10409 } else {
10410 word = *wbuf;
10411 }
10412 chksum += *wbuf; /* Checksum is calculated from word values. */
10413 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10414 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10415 ASC_EEP_CMD_WRITE | addr);
10416 AdvWaitEEPCmd(iop_base);
b009bef6 10417 mdelay(ADV_EEP_DELAY_MS);
27c868c2 10418 }
1da177e4 10419
27c868c2
MW		 10420 /*
10421 * Write EEPROM checksum at word 21.
10422 */
10423 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10424 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10425 AdvWaitEEPCmd(iop_base);
10426 wbuf++;
10427 charfields++;
10428
10429 /*
10430 * Write EEPROM OEM name at words 22 to 29.
10431 */
10432 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10433 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10434 ushort word;
10435
10436 if (*charfields++) {
10437 word = cpu_to_le16(*wbuf);
10438 } else {
10439 word = *wbuf;
10440 }
10441 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10442 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10443 ASC_EEP_CMD_WRITE | addr);
10444 AdvWaitEEPCmd(iop_base);
10445 }
10446 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10447 AdvWaitEEPCmd(iop_base);
1da177e4
LT		 10448}
10449
10450/*
51219358
MW		 10451 * Read EEPROM configuration into the specified buffer.
10452 *
10453 * Return a checksum based on the EEPROM configuration read.
1da177e4 10454 */
6f039790
GKH		 10455static ushort AdvGet3550EEPConfig(AdvPortAddr iop_base,
10456 ADVEEP_3550_CONFIG *cfg_buf)
1da177e4 10457{
51219358 10458 ushort wval, chksum;
27c868c2 10459 ushort *wbuf;
51219358 10460 int eep_addr;
27c868c2 10461 ushort *charfields;
27c868c2 10462
51219358 10463 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
27c868c2 10464 wbuf = (ushort *)cfg_buf;
27c868c2
MW		 10465 chksum = 0;
10466
51219358
MW		 10467 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10468 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10469 wval = AdvReadEEPWord(iop_base, eep_addr);
10470 chksum += wval; /* Checksum is calculated from word values. */
10471 if (*charfields++) {
10472 *wbuf = le16_to_cpu(wval);
10473 } else {
10474 *wbuf = wval;
10475 }
10476 }
10477 /* Read checksum word. */
10478 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10479 wbuf++;
10480 charfields++;
27c868c2 10481
51219358
MW		 10482 /* Read rest of EEPROM not covered by the checksum. */
10483 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10484 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10485 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10486 if (*charfields++) {
10487 *wbuf = le16_to_cpu(*wbuf);
10488 }
10489 }
10490 return chksum;
10491}
10492
10493/*
10494 * Read EEPROM configuration into the specified buffer.
10495 *
10496 * Return a checksum based on the EEPROM configuration read.
10497 */
6f039790
GKH		 10498static ushort AdvGet38C0800EEPConfig(AdvPortAddr iop_base,
10499 ADVEEP_38C0800_CONFIG *cfg_buf)
51219358
MW		 10500{
10501 ushort wval, chksum;
10502 ushort *wbuf;
10503 int eep_addr;
10504 ushort *charfields;
27c868c2 10505
51219358
MW		 10506 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
10507 wbuf = (ushort *)cfg_buf;
10508 chksum = 0;
10509
10510 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10511 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10512 wval = AdvReadEEPWord(iop_base, eep_addr);
10513 chksum += wval; /* Checksum is calculated from word values. */
27c868c2 10514 if (*charfields++) {
51219358 10515 *wbuf = le16_to_cpu(wval);
27c868c2 10516 } else {
51219358 10517 *wbuf = wval;
27c868c2 10518 }
27c868c2 10519 }
51219358
MW		 10520 /* Read checksum word. */
10521 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
27c868c2
MW		 10522 wbuf++;
10523 charfields++;
10524
51219358
MW		 10525 /* Read rest of EEPROM not covered by the checksum. */
10526 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10527 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10528 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
27c868c2 10529 if (*charfields++) {
51219358 10530 *wbuf = le16_to_cpu(*wbuf);
27c868c2 10531 }
27c868c2 10532 }
51219358 10533 return chksum;
1da177e4
LT		 10534}
10535
10536/*
51219358
MW		 10537 * Read EEPROM configuration into the specified buffer.
10538 *
10539 * Return a checksum based on the EEPROM configuration read.
1da177e4 10540 */
6f039790
GKH		 10541static ushort AdvGet38C1600EEPConfig(AdvPortAddr iop_base,
10542 ADVEEP_38C1600_CONFIG *cfg_buf)
1da177e4 10543{
51219358 10544 ushort wval, chksum;
27c868c2 10545 ushort *wbuf;
51219358 10546 int eep_addr;
27c868c2 10547 ushort *charfields;
27c868c2 10548
27c868c2 10549 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
51219358 10550 wbuf = (ushort *)cfg_buf;
27c868c2
MW		 10551 chksum = 0;
10552
51219358
MW		 10553 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10554 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10555 wval = AdvReadEEPWord(iop_base, eep_addr);
10556 chksum += wval; /* Checksum is calculated from word values. */
27c868c2 10557 if (*charfields++) {
51219358 10558 *wbuf = le16_to_cpu(wval);
27c868c2 10559 } else {
51219358 10560 *wbuf = wval;
27c868c2 10561 }
27c868c2 10562 }
51219358
MW		 10563 /* Read checksum word. */
10564 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
27c868c2
MW		 10565 wbuf++;
10566 charfields++;
10567
51219358
MW		 10568 /* Read rest of EEPROM not covered by the checksum. */
10569 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10570 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10571 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
27c868c2 10572 if (*charfields++) {
51219358 10573 *wbuf = le16_to_cpu(*wbuf);
27c868c2 10574 }
27c868c2 10575 }
51219358 10576 return chksum;
1da177e4
LT		 10577}
10578
1da177e4 10579/*
51219358
MW		 10580 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
10581 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
10582 * all of this is done.
1da177e4 10583 *
51219358 10584 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
1da177e4 10585 *
51219358
MW		 10586 * For a non-fatal error return a warning code. If there are no warnings
10587 * then 0 is returned.
1da177e4 10588 *
51219358 10589 * Note: Chip is stopped on entry.
1da177e4 10590 */
6f039790 10591static int AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
1da177e4 10592{
27c868c2 10593 AdvPortAddr iop_base;
51219358
MW		 10594 ushort warn_code;
10595 ADVEEP_3550_CONFIG eep_config;
1da177e4 10596
27c868c2 10597 iop_base = asc_dvc->iop_base;
1da177e4 10598
51219358 10599 warn_code = 0;
27c868c2
MW		 10600
10601 /*
51219358
MW		 10602 * Read the board's EEPROM configuration.
10603 *
10604 * Set default values if a bad checksum is found.
27c868c2 10605 */
51219358
MW		 10606 if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) {
10607 warn_code |= ASC_WARN_EEPROM_CHKSUM;
27c868c2 10608
51219358
MW		 10609 /*
10610 * Set EEPROM default values.
10611 */
10612 memcpy(&eep_config, &Default_3550_EEPROM_Config,
10613 sizeof(ADVEEP_3550_CONFIG));
27c868c2 10614
51219358
MW		 10615 /*
10616 * Assume the 6 byte board serial number that was read from
10617 * EEPROM is correct even if the EEPROM checksum failed.
10618 */
10619 eep_config.serial_number_word3 =
10620 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
27c868c2 10621
51219358
MW		 10622 eep_config.serial_number_word2 =
10623 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
27c868c2 10624
51219358
MW		 10625 eep_config.serial_number_word1 =
10626 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
27c868c2 10627
51219358
MW		 10628 AdvSet3550EEPConfig(iop_base, &eep_config);
10629 }
10630 /*
10631 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
10632 * EEPROM configuration that was read.
10633 *
10634 * This is the mapping of EEPROM fields to Adv Library fields.
10635 */
10636 asc_dvc->wdtr_able = eep_config.wdtr_able;
10637 asc_dvc->sdtr_able = eep_config.sdtr_able;
10638 asc_dvc->ultra_able = eep_config.ultra_able;
10639 asc_dvc->tagqng_able = eep_config.tagqng_able;
10640 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10641 asc_dvc->max_host_qng = eep_config.max_host_qng;
10642 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10643 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
10644 asc_dvc->start_motor = eep_config.start_motor;
10645 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10646 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10647 asc_dvc->no_scam = eep_config.scam_tolerant;
10648 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
10649 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
10650 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
27c868c2 10651
27c868c2 10652 /*
51219358
MW		 10653 * Set the host maximum queuing (max. 253, min. 16) and the per device
10654 * maximum queuing (max. 63, min. 4).
27c868c2 10655 */
51219358
MW		 10656 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10657 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10658 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10659 /* If the value is zero, assume it is uninitialized. */
10660 if (eep_config.max_host_qng == 0) {
10661 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10662 } else {
10663 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10664 }
10665 }
10666
10667 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10668 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10669 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10670 /* If the value is zero, assume it is uninitialized. */
10671 if (eep_config.max_dvc_qng == 0) {
10672 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10673 } else {
10674 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10675 }
10676 }
27c868c2
MW		 10677
10678 /*
51219358
MW		 10679 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10680 * set 'max_dvc_qng' to 'max_host_qng'.
27c868c2 10681 */
51219358
MW		 10682 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10683 eep_config.max_dvc_qng = eep_config.max_host_qng;
10684 }
27c868c2
MW		 10685
10686 /*
51219358
MW		 10687 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
10688 * values based on possibly adjusted EEPROM values.
27c868c2 10689 */
51219358
MW		 10690 asc_dvc->max_host_qng = eep_config.max_host_qng;
10691 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
27c868c2
MW		 10692
10693 /*
51219358
MW		 10694 * If the EEPROM 'termination' field is set to automatic (0), then set
10695 * the ADV_DVC_CFG 'termination' field to automatic also.
10696 *
10697 * If the termination is specified with a non-zero 'termination'
10698 * value check that a legal value is set and set the ADV_DVC_CFG
10699 * 'termination' field appropriately.
27c868c2 10700 */
51219358
MW		 10701 if (eep_config.termination == 0) {
10702 asc_dvc->cfg->termination = 0; /* auto termination */
10703 } else {
10704 /* Enable manual control with low off / high off. */
10705 if (eep_config.termination == 1) {
10706 asc_dvc->cfg->termination = TERM_CTL_SEL;
27c868c2 10707
51219358
MW		 10708 /* Enable manual control with low off / high on. */
10709 } else if (eep_config.termination == 2) {
10710 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
10711
10712 /* Enable manual control with low on / high on. */
10713 } else if (eep_config.termination == 3) {
10714 asc_dvc->cfg->termination =
10715 TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
10716 } else {
27c868c2 10717 /*
51219358
MW		 10718 * The EEPROM 'termination' field contains a bad value. Use
10719 * automatic termination instead.
27c868c2 10720 */
51219358
MW		 10721 asc_dvc->cfg->termination = 0;
10722 warn_code |= ASC_WARN_EEPROM_TERMINATION;
27c868c2 10723 }
27c868c2 10724 }
1da177e4 10725
51219358 10726 return warn_code;
1da177e4
LT		 10727}
10728
10729/*
51219358
MW		 10730 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
10731 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
10732 * all of this is done.
1da177e4 10733 *
51219358
MW		 10734 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
10735 *
10736 * For a non-fatal error return a warning code. If there are no warnings
10737 * then 0 is returned.
10738 *
10739 * Note: Chip is stopped on entry.
1da177e4 10740 */
6f039790 10741static int AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
1da177e4 10742{
51219358
MW		 10743 AdvPortAddr iop_base;
10744 ushort warn_code;
10745 ADVEEP_38C0800_CONFIG eep_config;
10746 uchar tid, termination;
10747 ushort sdtr_speed = 0;
27c868c2 10748
51219358 10749 iop_base = asc_dvc->iop_base;
1da177e4 10750
51219358 10751 warn_code = 0;
27c868c2
MW		 10752
10753 /*
51219358
MW		 10754 * Read the board's EEPROM configuration.
10755 *
10756 * Set default values if a bad checksum is found.
27c868c2 10757 */
51219358
MW		 10758 if (AdvGet38C0800EEPConfig(iop_base, &eep_config) !=
10759 eep_config.check_sum) {
10760 warn_code |= ASC_WARN_EEPROM_CHKSUM;
27c868c2 10761
51219358
MW		 10762 /*
10763 * Set EEPROM default values.
10764 */
10765 memcpy(&eep_config, &Default_38C0800_EEPROM_Config,
10766 sizeof(ADVEEP_38C0800_CONFIG));
1da177e4 10767
51219358
MW		 10768 /*
10769 * Assume the 6 byte board serial number that was read from
10770 * EEPROM is correct even if the EEPROM checksum failed.
10771 */
10772 eep_config.serial_number_word3 =
10773 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
1da177e4 10774
51219358
MW		 10775 eep_config.serial_number_word2 =
10776 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
27c868c2 10777
51219358
MW		 10778 eep_config.serial_number_word1 =
10779 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
27c868c2 10780
51219358 10781 AdvSet38C0800EEPConfig(iop_base, &eep_config);
27c868c2 10782 }
27c868c2 10783 /*
51219358
MW		 10784 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
10785 * EEPROM configuration that was read.
10786 *
10787 * This is the mapping of EEPROM fields to Adv Library fields.
27c868c2 10788 */
51219358
MW		 10789 asc_dvc->wdtr_able = eep_config.wdtr_able;
10790 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
10791 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
10792 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
10793 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
10794 asc_dvc->tagqng_able = eep_config.tagqng_able;
10795 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10796 asc_dvc->max_host_qng = eep_config.max_host_qng;
10797 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10798 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
10799 asc_dvc->start_motor = eep_config.start_motor;
10800 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10801 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10802 asc_dvc->no_scam = eep_config.scam_tolerant;
10803 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
10804 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
10805 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
27c868c2
MW		 10806
10807 /*
51219358
MW		 10808 * For every Target ID if any of its 'sdtr_speed[1234]' bits
10809 * are set, then set an 'sdtr_able' bit for it.
27c868c2 10810 */
51219358
MW		 10811 asc_dvc->sdtr_able = 0;
10812 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
10813 if (tid == 0) {
10814 sdtr_speed = asc_dvc->sdtr_speed1;
10815 } else if (tid == 4) {
10816 sdtr_speed = asc_dvc->sdtr_speed2;
10817 } else if (tid == 8) {
10818 sdtr_speed = asc_dvc->sdtr_speed3;
10819 } else if (tid == 12) {
10820 sdtr_speed = asc_dvc->sdtr_speed4;
10821 }
10822 if (sdtr_speed & ADV_MAX_TID) {
10823 asc_dvc->sdtr_able |= (1 << tid);
10824 }
10825 sdtr_speed >>= 4;
10826 }
27c868c2
MW		 10827
10828 /*
51219358
MW		 10829 * Set the host maximum queuing (max. 253, min. 16) and the per device
10830 * maximum queuing (max. 63, min. 4).
27c868c2 10831 */
51219358
MW		 10832 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10833 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10834 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10835 /* If the value is zero, assume it is uninitialized. */
10836 if (eep_config.max_host_qng == 0) {
10837 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10838 } else {
10839 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10840 }
27c868c2 10841 }
1da177e4 10842
51219358
MW		 10843 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10844 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10845 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10846 /* If the value is zero, assume it is uninitialized. */
10847 if (eep_config.max_dvc_qng == 0) {
10848 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10849 } else {
10850 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10851 }
10852 }
10853
10854 /*
10855 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10856 * set 'max_dvc_qng' to 'max_host_qng'.
10857 */
10858 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10859 eep_config.max_dvc_qng = eep_config.max_host_qng;
27c868c2 10860 }
1da177e4 10861
27c868c2 10862 /*
51219358
MW		 10863 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
10864 * values based on possibly adjusted EEPROM values.
27c868c2 10865 */
51219358
MW		 10866 asc_dvc->max_host_qng = eep_config.max_host_qng;
10867 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
27c868c2
MW		 10868
10869 /*
51219358
MW		 10870 * If the EEPROM 'termination' field is set to automatic (0), then set
10871 * the ADV_DVC_CFG 'termination' field to automatic also.
10872 *
10873 * If the termination is specified with a non-zero 'termination'
10874 * value check that a legal value is set and set the ADV_DVC_CFG
10875 * 'termination' field appropriately.
27c868c2 10876 */
51219358
MW		 10877 if (eep_config.termination_se == 0) {
10878 termination = 0; /* auto termination for SE */
10879 } else {
10880 /* Enable manual control with low off / high off. */
10881 if (eep_config.termination_se == 1) {
10882 termination = 0;
10883
10884 /* Enable manual control with low off / high on. */
10885 } else if (eep_config.termination_se == 2) {
10886 termination = TERM_SE_HI;
10887
10888 /* Enable manual control with low on / high on. */
10889 } else if (eep_config.termination_se == 3) {
10890 termination = TERM_SE;
10891 } else {
10892 /*
10893 * The EEPROM 'termination_se' field contains a bad value.
10894 * Use automatic termination instead.
10895 */
10896 termination = 0;
10897 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10898 }
27c868c2 10899 }
51219358
MW		 10900
10901 if (eep_config.termination_lvd == 0) {
10902 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
10903 } else {
10904 /* Enable manual control with low off / high off. */
10905 if (eep_config.termination_lvd == 1) {
10906 asc_dvc->cfg->termination = termination;
10907
10908 /* Enable manual control with low off / high on. */
10909 } else if (eep_config.termination_lvd == 2) {
10910 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
10911
10912 /* Enable manual control with low on / high on. */
10913 } else if (eep_config.termination_lvd == 3) {
10914 asc_dvc->cfg->termination = termination | TERM_LVD;
10915 } else {
10916 /*
10917 * The EEPROM 'termination_lvd' field contains a bad value.
10918 * Use automatic termination instead.
10919 */
10920 asc_dvc->cfg->termination = termination;
10921 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10922 }
27c868c2 10923 }
1da177e4 10924
51219358 10925 return warn_code;
1da177e4
LT		 10926}
10927
10928/*
51219358
MW		 10929 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
10930 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
10931 * all of this is done.
1da177e4 10932 *
51219358 10933 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
1da177e4 10934 *
51219358
MW		 10935 * For a non-fatal error return a warning code. If there are no warnings
10936 * then 0 is returned.
1da177e4 10937 *
51219358 10938 * Note: Chip is stopped on entry.
1da177e4 10939 */
6f039790 10940static int AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
1da177e4 10941{
27c868c2 10942 AdvPortAddr iop_base;
51219358
MW		 10943 ushort warn_code;
10944 ADVEEP_38C1600_CONFIG eep_config;
10945 uchar tid, termination;
10946 ushort sdtr_speed = 0;
1da177e4 10947
27c868c2
MW		 10948 iop_base = asc_dvc->iop_base;
10949
51219358 10950 warn_code = 0;
27c868c2 10951
51219358
MW		 10952 /*
10953 * Read the board's EEPROM configuration.
10954 *
10955 * Set default values if a bad checksum is found.
10956 */
10957 if (AdvGet38C1600EEPConfig(iop_base, &eep_config) !=
10958 eep_config.check_sum) {
10959 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
10960 warn_code |= ASC_WARN_EEPROM_CHKSUM;
10961
10962 /*
10963 * Set EEPROM default values.
10964 */
10965 memcpy(&eep_config, &Default_38C1600_EEPROM_Config,
10966 sizeof(ADVEEP_38C1600_CONFIG));
10967
10968 if (PCI_FUNC(pdev->devfn) != 0) {
10969 u8 ints;
10970 /*
10971 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60
10972 * and old Mac system booting problem. The Expansion
10973 * ROM must be disabled in Function 1 for these systems
10974 */
10975 eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE;
10976 /*
10977 * Clear the INTAB (bit 11) if the GPIO 0 input
10978 * indicates the Function 1 interrupt line is wired
10979 * to INTB.
10980 *
10981 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
10982 * 1 - Function 1 interrupt line wired to INT A.
10983 * 0 - Function 1 interrupt line wired to INT B.
10984 *
10985 * Note: Function 0 is always wired to INTA.
10986 * Put all 5 GPIO bits in input mode and then read
10987 * their input values.
10988 */
10989 AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
10990 ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA);
10991 if ((ints & 0x01) == 0)
10992 eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB;
10993 }
10994
10995 /*
10996 * Assume the 6 byte board serial number that was read from
10997 * EEPROM is correct even if the EEPROM checksum failed.
10998 */
10999 eep_config.serial_number_word3 =
11000 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
11001 eep_config.serial_number_word2 =
11002 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
11003 eep_config.serial_number_word1 =
11004 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
11005
11006 AdvSet38C1600EEPConfig(iop_base, &eep_config);
27c868c2
MW		 11007 }
11008
11009 /*
51219358
MW		 11010 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
11011 * EEPROM configuration that was read.
11012 *
11013 * This is the mapping of EEPROM fields to Adv Library fields.
27c868c2 11014 */
51219358
MW		 11015 asc_dvc->wdtr_able = eep_config.wdtr_able;
11016 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
11017 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
11018 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
11019 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
11020 asc_dvc->ppr_able = 0;
11021 asc_dvc->tagqng_able = eep_config.tagqng_able;
11022 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
11023 asc_dvc->max_host_qng = eep_config.max_host_qng;
11024 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
11025 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
11026 asc_dvc->start_motor = eep_config.start_motor;
11027 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
11028 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
11029 asc_dvc->no_scam = eep_config.scam_tolerant;
27c868c2 11030
51219358
MW		 11031 /*
11032 * For every Target ID if any of its 'sdtr_speed[1234]' bits
11033 * are set, then set an 'sdtr_able' bit for it.
11034 */
11035 asc_dvc->sdtr_able = 0;
11036 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
11037 if (tid == 0) {
11038 sdtr_speed = asc_dvc->sdtr_speed1;
11039 } else if (tid == 4) {
11040 sdtr_speed = asc_dvc->sdtr_speed2;
11041 } else if (tid == 8) {
11042 sdtr_speed = asc_dvc->sdtr_speed3;
11043 } else if (tid == 12) {
11044 sdtr_speed = asc_dvc->sdtr_speed4;
11045 }
11046 if (sdtr_speed & ASC_MAX_TID) {
11047 asc_dvc->sdtr_able |= (1 << tid);
11048 }
11049 sdtr_speed >>= 4;
11050 }
27c868c2 11051
51219358
MW		 11052 /*
11053 * Set the host maximum queuing (max. 253, min. 16) and the per device
11054 * maximum queuing (max. 63, min. 4).
11055 */
11056 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
11057 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
11058 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
11059 /* If the value is zero, assume it is uninitialized. */
11060 if (eep_config.max_host_qng == 0) {
11061 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
11062 } else {
11063 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
27c868c2 11064 }
51219358 11065 }
27c868c2 11066
51219358
MW		 11067 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
11068 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
11069 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
11070 /* If the value is zero, assume it is uninitialized. */
11071 if (eep_config.max_dvc_qng == 0) {
11072 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
11073 } else {
11074 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
11075 }
11076 }
11077
11078 /*
11079 * If 'max_dvc_qng' is greater than 'max_host_qng', then
11080 * set 'max_dvc_qng' to 'max_host_qng'.
11081 */
11082 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
11083 eep_config.max_dvc_qng = eep_config.max_host_qng;
27c868c2
MW		 11084 }
11085
11086 /*
51219358
MW		 11087 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
11088 * values based on possibly adjusted EEPROM values.
11089 */
11090 asc_dvc->max_host_qng = eep_config.max_host_qng;
11091 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
11092
11093 /*
11094 * If the EEPROM 'termination' field is set to automatic (0), then set
11095 * the ASC_DVC_CFG 'termination' field to automatic also.
11096 *
11097 * If the termination is specified with a non-zero 'termination'
11098 * value check that a legal value is set and set the ASC_DVC_CFG
11099 * 'termination' field appropriately.
27c868c2 11100 */
51219358
MW		 11101 if (eep_config.termination_se == 0) {
11102 termination = 0; /* auto termination for SE */
11103 } else {
11104 /* Enable manual control with low off / high off. */
11105 if (eep_config.termination_se == 1) {
11106 termination = 0;
27c868c2 11107
51219358
MW		 11108 /* Enable manual control with low off / high on. */
11109 } else if (eep_config.termination_se == 2) {
11110 termination = TERM_SE_HI;
27c868c2 11111
51219358
MW		 11112 /* Enable manual control with low on / high on. */
11113 } else if (eep_config.termination_se == 3) {
11114 termination = TERM_SE;
11115 } else {
11116 /*
11117 * The EEPROM 'termination_se' field contains a bad value.
11118 * Use automatic termination instead.
11119 */
11120 termination = 0;
11121 warn_code |= ASC_WARN_EEPROM_TERMINATION;
11122 }
11123 }
27c868c2 11124
51219358
MW		 11125 if (eep_config.termination_lvd == 0) {
11126 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
11127 } else {
11128 /* Enable manual control with low off / high off. */
11129 if (eep_config.termination_lvd == 1) {
11130 asc_dvc->cfg->termination = termination;
27c868c2 11131
51219358
MW		 11132 /* Enable manual control with low off / high on. */
11133 } else if (eep_config.termination_lvd == 2) {
11134 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
27c868c2 11135
51219358
MW		 11136 /* Enable manual control with low on / high on. */
11137 } else if (eep_config.termination_lvd == 3) {
11138 asc_dvc->cfg->termination = termination | TERM_LVD;
11139 } else {
11140 /*
11141 * The EEPROM 'termination_lvd' field contains a bad value.
11142 * Use automatic termination instead.
11143 */
11144 asc_dvc->cfg->termination = termination;
11145 warn_code |= ASC_WARN_EEPROM_TERMINATION;
11146 }
27c868c2 11147 }
51219358
MW		 11148
11149 return warn_code;
1da177e4
LT		 11150}
11151
11152/*
51219358 11153 * Initialize the ADV_DVC_VAR structure.
1da177e4 11154 *
51219358 11155 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
1da177e4 11156 *
51219358
MW		 11157 * For a non-fatal error return a warning code. If there are no warnings
11158 * then 0 is returned.
1da177e4 11159 */
6f039790 11160static int AdvInitGetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
1da177e4 11161{
9d0e96eb
MW		 11162 struct asc_board *board = shost_priv(shost);
11163 ADV_DVC_VAR *asc_dvc = &board->dvc_var.adv_dvc_var;
51219358
MW		 11164 unsigned short warn_code = 0;
11165 AdvPortAddr iop_base = asc_dvc->iop_base;
11166 u16 cmd;
11167 int status;
27c868c2 11168
51219358 11169 asc_dvc->err_code = 0;
27c868c2
MW		 11170
11171 /*
51219358
MW		 11172 * Save the state of the PCI Configuration Command Register
11173 * "Parity Error Response Control" Bit. If the bit is clear (0),
11174 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
11175 * DMA parity errors.
27c868c2 11176 */
51219358
MW		 11177 asc_dvc->cfg->control_flag = 0;
11178 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
11179 if ((cmd & PCI_COMMAND_PARITY) == 0)
11180 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
27c868c2 11181
51219358
MW		 11182 asc_dvc->cfg->chip_version =
11183 AdvGetChipVersion(iop_base, asc_dvc->bus_type);
11184
b352f923 11185 ASC_DBG(1, "iopb_chip_id_1: 0x%x 0x%x\n",
51219358
MW		 11186 (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
11187 (ushort)ADV_CHIP_ID_BYTE);
11188
b352f923 11189 ASC_DBG(1, "iopw_chip_id_0: 0x%x 0x%x\n",
51219358
MW		 11190 (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
11191 (ushort)ADV_CHIP_ID_WORD);
27c868c2
MW		 11192
11193 /*
51219358 11194 * Reset the chip to start and allow register writes.
27c868c2 11195 */
51219358
MW		 11196 if (AdvFindSignature(iop_base) == 0) {
11197 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
11198 return ADV_ERROR;
11199 } else {
27c868c2 11200 /*
51219358 11201 * The caller must set 'chip_type' to a valid setting.
27c868c2 11202 */
51219358
MW		 11203 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
11204 asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
11205 asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
11206 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
11207 return ADV_ERROR;
11208 }
1da177e4 11209
51219358
MW		 11210 /*
11211 * Reset Chip.
11212 */
11213 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
11214 ADV_CTRL_REG_CMD_RESET);
11215 mdelay(100);
11216 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
11217 ADV_CTRL_REG_CMD_WR_IO_REG);
11218
11219 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
11220 status = AdvInitFrom38C1600EEP(asc_dvc);
11221 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
11222 status = AdvInitFrom38C0800EEP(asc_dvc);
11223 } else {
11224 status = AdvInitFrom3550EEP(asc_dvc);
27c868c2 11225 }
51219358 11226 warn_code |= status;
27c868c2 11227 }
1da177e4 11228
9d0e96eb
MW		 11229 if (warn_code != 0)
11230 shost_printk(KERN_WARNING, shost, "warning: 0x%x\n", warn_code);
51219358 11231
9d0e96eb
MW		 11232 if (asc_dvc->err_code)
11233 shost_printk(KERN_ERR, shost, "error code 0x%x\n",
11234 asc_dvc->err_code);
51219358
MW		 11235
11236 return asc_dvc->err_code;
1da177e4 11237}
51219358
MW		 11238#endif
11239
11240static struct scsi_host_template advansys_template = {
11241 .proc_name = DRV_NAME,
11242#ifdef CONFIG_PROC_FS
b59fb6fd 11243 .show_info = advansys_show_info,
51219358
MW		 11244#endif
11245 .name = DRV_NAME,
11246 .info = advansys_info,
11247 .queuecommand = advansys_queuecommand,
11248 .eh_bus_reset_handler = advansys_reset,
11249 .bios_param = advansys_biosparam,
11250 .slave_configure = advansys_slave_configure,
11251 /*
11252 * Because the driver may control an ISA adapter 'unchecked_isa_dma'
11253 * must be set. The flag will be cleared in advansys_board_found
11254 * for non-ISA adapters.
11255 */
11256 .unchecked_isa_dma = 1,
11257 /*
11258 * All adapters controlled by this driver are capable of large
11259 * scatter-gather lists. According to the mid-level SCSI documentation
11260 * this obviates any performance gain provided by setting
11261 * 'use_clustering'. But empirically while CPU utilization is increased
11262 * by enabling clustering, I/O throughput increases as well.
11263 */
11264 .use_clustering = ENABLE_CLUSTERING,
11265};
1da177e4 11266
6f039790 11267static int advansys_wide_init_chip(struct Scsi_Host *shost)
b2c16f58 11268{
9d0e96eb
MW		 11269 struct asc_board *board = shost_priv(shost);
11270 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
b2c16f58
MW		 11271 int req_cnt = 0;
11272 adv_req_t *reqp = NULL;
11273 int sg_cnt = 0;
11274 adv_sgblk_t *sgp;
11275 int warn_code, err_code;
11276
11277 /*
11278 * Allocate buffer carrier structures. The total size
11279 * is about 4 KB, so allocate all at once.
11280 */
98d41c29
MW		 11281 adv_dvc->carrier_buf = kmalloc(ADV_CARRIER_BUFSIZE, GFP_KERNEL);
11282 ASC_DBG(1, "carrier_buf 0x%p\n", adv_dvc->carrier_buf);
b2c16f58 11283
98d41c29 11284 if (!adv_dvc->carrier_buf)
b2c16f58
MW		 11285 goto kmalloc_failed;
11286
11287 /*
11288 * Allocate up to 'max_host_qng' request structures for the Wide
11289 * board. The total size is about 16 KB, so allocate all at once.
11290 * If the allocation fails decrement and try again.
11291 */
9d0e96eb 11292 for (req_cnt = adv_dvc->max_host_qng; req_cnt > 0; req_cnt--) {
b2c16f58
MW		 11293 reqp = kmalloc(sizeof(adv_req_t) * req_cnt, GFP_KERNEL);
11294
b352f923 11295 ASC_DBG(1, "reqp 0x%p, req_cnt %d, bytes %lu\n", reqp, req_cnt,
b2c16f58
MW		 11296 (ulong)sizeof(adv_req_t) * req_cnt);
11297
11298 if (reqp)
11299 break;
11300 }
11301
11302 if (!reqp)
11303 goto kmalloc_failed;
11304
98d41c29 11305 adv_dvc->orig_reqp = reqp;
b2c16f58
MW		 11306
11307 /*
11308 * Allocate up to ADV_TOT_SG_BLOCK request structures for
11309 * the Wide board. Each structure is about 136 bytes.
11310 */
9d0e96eb 11311 board->adv_sgblkp = NULL;
b2c16f58
MW		 11312 for (sg_cnt = 0; sg_cnt < ADV_TOT_SG_BLOCK; sg_cnt++) {
11313 sgp = kmalloc(sizeof(adv_sgblk_t), GFP_KERNEL);
11314
11315 if (!sgp)
11316 break;
11317
9d0e96eb
MW		 11318 sgp->next_sgblkp = board->adv_sgblkp;
11319 board->adv_sgblkp = sgp;
b2c16f58
MW		 11320
11321 }
11322
9d511a4b
MW		 11323 ASC_DBG(1, "sg_cnt %d * %lu = %lu bytes\n", sg_cnt, sizeof(adv_sgblk_t),
11324 sizeof(adv_sgblk_t) * sg_cnt);
b2c16f58 11325
9d0e96eb 11326 if (!board->adv_sgblkp)
b2c16f58
MW		 11327 goto kmalloc_failed;
11328
b2c16f58
MW		 11329 /*
11330 * Point 'adv_reqp' to the request structures and
11331 * link them together.
11332 */
11333 req_cnt--;
11334 reqp[req_cnt].next_reqp = NULL;
11335 for (; req_cnt > 0; req_cnt--) {
11336 reqp[req_cnt - 1].next_reqp = &reqp[req_cnt];
11337 }
9d0e96eb 11338 board->adv_reqp = &reqp[0];
b2c16f58 11339
9d0e96eb 11340 if (adv_dvc->chip_type == ADV_CHIP_ASC3550) {
b352f923 11341 ASC_DBG(2, "AdvInitAsc3550Driver()\n");
9d0e96eb
MW		 11342 warn_code = AdvInitAsc3550Driver(adv_dvc);
11343 } else if (adv_dvc->chip_type == ADV_CHIP_ASC38C0800) {
b352f923 11344 ASC_DBG(2, "AdvInitAsc38C0800Driver()\n");
9d0e96eb 11345 warn_code = AdvInitAsc38C0800Driver(adv_dvc);
b2c16f58 11346 } else {
b352f923 11347 ASC_DBG(2, "AdvInitAsc38C1600Driver()\n");
9d0e96eb 11348 warn_code = AdvInitAsc38C1600Driver(adv_dvc);
b2c16f58 11349 }
9d0e96eb 11350 err_code = adv_dvc->err_code;
b2c16f58
MW		 11351
11352 if (warn_code || err_code) {
9d0e96eb
MW		 11353 shost_printk(KERN_WARNING, shost, "error: warn 0x%x, error "
11354 "0x%x\n", warn_code, err_code);
b2c16f58
MW		 11355 }
11356
11357 goto exit;
11358
11359 kmalloc_failed:
9d0e96eb 11360 shost_printk(KERN_ERR, shost, "error: kmalloc() failed\n");
b2c16f58
MW		 11361 err_code = ADV_ERROR;
11362 exit:
11363 return err_code;
11364}
11365
98d41c29 11366static void advansys_wide_free_mem(struct asc_board *board)
b2c16f58 11367{
98d41c29
MW		 11368 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
11369 kfree(adv_dvc->carrier_buf);
11370 adv_dvc->carrier_buf = NULL;
11371 kfree(adv_dvc->orig_reqp);
11372 adv_dvc->orig_reqp = board->adv_reqp = NULL;
11373 while (board->adv_sgblkp) {
11374 adv_sgblk_t *sgp = board->adv_sgblkp;
11375 board->adv_sgblkp = sgp->next_sgblkp;
b2c16f58
MW		 11376 kfree(sgp);
11377 }
11378}
11379
6f039790
GKH		 11380static int advansys_board_found(struct Scsi_Host *shost, unsigned int iop,
11381 int bus_type)
27c868c2 11382{
d361db48 11383 struct pci_dev *pdev;
d2411495 11384 struct asc_board *boardp = shost_priv(shost);
27c868c2
MW		 11385 ASC_DVC_VAR *asc_dvc_varp = NULL;
11386 ADV_DVC_VAR *adv_dvc_varp = NULL;
d361db48 11387 int share_irq, warn_code, ret;
27c868c2 11388
d361db48 11389 pdev = (bus_type == ASC_IS_PCI) ? to_pci_dev(boardp->dev) : NULL;
27c868c2
MW		 11390
11391 if (ASC_NARROW_BOARD(boardp)) {
b352f923 11392 ASC_DBG(1, "narrow board\n");
27c868c2
MW		 11393 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
11394 asc_dvc_varp->bus_type = bus_type;
11395 asc_dvc_varp->drv_ptr = boardp;
11396 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
27c868c2 11397 asc_dvc_varp->iop_base = iop;
27c868c2 11398 } else {
57ba5fe9 11399#ifdef CONFIG_PCI
27c868c2
MW		 11400 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
11401 adv_dvc_varp->drv_ptr = boardp;
11402 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
27c868c2 11403 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) {
b352f923 11404 ASC_DBG(1, "wide board ASC-3550\n");
27c868c2
MW		 11405 adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
11406 } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) {
b352f923 11407 ASC_DBG(1, "wide board ASC-38C0800\n");
27c868c2
MW		 11408 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
11409 } else {
b352f923 11410 ASC_DBG(1, "wide board ASC-38C1600\n");
27c868c2
MW		 11411 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
11412 }
27c868c2 11413
57ba5fe9 11414 boardp->asc_n_io_port = pci_resource_len(pdev, 1);
25729a7f 11415 boardp->ioremap_addr = pci_ioremap_bar(pdev, 1);
57ba5fe9 11416 if (!boardp->ioremap_addr) {
9d511a4b 11417 shost_printk(KERN_ERR, shost, "ioremap(%lx, %d) "
9d0e96eb 11418 "returned NULL\n",
9d511a4b 11419 (long)pci_resource_start(pdev, 1),
9d0e96eb 11420 boardp->asc_n_io_port);
d361db48 11421 ret = -ENODEV;
b2c16f58 11422 goto err_shost;
27c868c2 11423 }
b352f923
MW		 11424 adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr;
11425 ASC_DBG(1, "iop_base: 0x%p\n", adv_dvc_varp->iop_base);
27c868c2
MW		 11426
11427 /*
11428 * Even though it isn't used to access wide boards, other
11429 * than for the debug line below, save I/O Port address so
11430 * that it can be reported.
11431 */
11432 boardp->ioport = iop;
11433
b352f923
MW		 11434 ASC_DBG(1, "iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n",
11435 (ushort)inp(iop + 1), (ushort)inpw(iop));
57ba5fe9 11436#endif /* CONFIG_PCI */
27c868c2
MW		 11437 }
11438
27c868c2 11439 if (ASC_NARROW_BOARD(boardp)) {
27c868c2
MW		 11440 /*
11441 * Set the board bus type and PCI IRQ before
11442 * calling AscInitGetConfig().
11443 */
11444 switch (asc_dvc_varp->bus_type) {
11445#ifdef CONFIG_ISA
11446 case ASC_IS_ISA:
11447 shost->unchecked_isa_dma = TRUE;
074c8fe4 11448 share_irq = 0;
27c868c2
MW		 11449 break;
11450 case ASC_IS_VL:
11451 shost->unchecked_isa_dma = FALSE;
074c8fe4 11452 share_irq = 0;
27c868c2
MW		 11453 break;
11454 case ASC_IS_EISA:
11455 shost->unchecked_isa_dma = FALSE;
074c8fe4 11456 share_irq = IRQF_SHARED;
27c868c2
MW		 11457 break;
11458#endif /* CONFIG_ISA */
11459#ifdef CONFIG_PCI
11460 case ASC_IS_PCI:
27c868c2 11461 shost->unchecked_isa_dma = FALSE;
074c8fe4 11462 share_irq = IRQF_SHARED;
27c868c2
MW		 11463 break;
11464#endif /* CONFIG_PCI */
11465 default:
9d0e96eb
MW		 11466 shost_printk(KERN_ERR, shost, "unknown adapter type: "
11467 "%d\n", asc_dvc_varp->bus_type);
27c868c2 11468 shost->unchecked_isa_dma = TRUE;
074c8fe4 11469 share_irq = 0;
27c868c2
MW		 11470 break;
11471 }
27c868c2 11472
27c868c2
MW		 11473 /*
11474 * NOTE: AscInitGetConfig() may change the board's
11475 * bus_type value. The bus_type value should no
11476 * longer be used. If the bus_type field must be
11477 * referenced only use the bit-wise AND operator "&".
11478 */
b352f923 11479 ASC_DBG(2, "AscInitGetConfig()\n");
9d0e96eb 11480 ret = AscInitGetConfig(shost) ? -ENODEV : 0;
27c868c2 11481 } else {
c2dce2fa
MW		 11482#ifdef CONFIG_PCI
11483 /*
11484 * For Wide boards set PCI information before calling
11485 * AdvInitGetConfig().
11486 */
c2dce2fa
MW		 11487 shost->unchecked_isa_dma = FALSE;
11488 share_irq = IRQF_SHARED;
b352f923 11489 ASC_DBG(2, "AdvInitGetConfig()\n");
394dbf3f 11490
9d0e96eb 11491 ret = AdvInitGetConfig(pdev, shost) ? -ENODEV : 0;
c2dce2fa 11492#endif /* CONFIG_PCI */
27c868c2
MW		 11493 }
11494
d361db48 11495 if (ret)
b59fb6fd 11496 goto err_unmap;
27c868c2
MW		 11497
11498 /*
11499 * Save the EEPROM configuration so that it can be displayed
11500 * from /proc/scsi/advansys/[0...].
11501 */
11502 if (ASC_NARROW_BOARD(boardp)) {
11503
11504 ASCEEP_CONFIG *ep;
11505
11506 /*
11507 * Set the adapter's target id bit in the 'init_tidmask' field.
11508 */
11509 boardp->init_tidmask |=
11510 ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
11511
11512 /*
11513 * Save EEPROM settings for the board.
11514 */
11515 ep = &boardp->eep_config.asc_eep;
11516
11517 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
11518 ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
11519 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
11520 ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
11521 ep->start_motor = asc_dvc_varp->start_motor;
11522 ep->cntl = asc_dvc_varp->dvc_cntl;
11523 ep->no_scam = asc_dvc_varp->no_scam;
11524 ep->max_total_qng = asc_dvc_varp->max_total_qng;
11525 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
11526 /* 'max_tag_qng' is set to the same value for every device. */
11527 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
11528 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
11529 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
11530 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
11531 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
11532 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
11533 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
11534
11535 /*
11536 * Modify board configuration.
11537 */
b352f923 11538 ASC_DBG(2, "AscInitSetConfig()\n");
9d0e96eb 11539 ret = AscInitSetConfig(pdev, shost) ? -ENODEV : 0;
d361db48 11540 if (ret)
b59fb6fd 11541 goto err_unmap;
27c868c2
MW		 11542 } else {
11543 ADVEEP_3550_CONFIG *ep_3550;
11544 ADVEEP_38C0800_CONFIG *ep_38C0800;
11545 ADVEEP_38C1600_CONFIG *ep_38C1600;
11546
11547 /*
11548 * Save Wide EEP Configuration Information.
11549 */
11550 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
11551 ep_3550 = &boardp->eep_config.adv_3550_eep;
11552
11553 ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
11554 ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
11555 ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11556 ep_3550->termination = adv_dvc_varp->cfg->termination;
11557 ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
11558 ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
11559 ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
11560 ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
11561 ep_3550->ultra_able = adv_dvc_varp->ultra_able;
11562 ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
11563 ep_3550->start_motor = adv_dvc_varp->start_motor;
11564 ep_3550->scsi_reset_delay =
11565 adv_dvc_varp->scsi_reset_wait;
11566 ep_3550->serial_number_word1 =
11567 adv_dvc_varp->cfg->serial1;
11568 ep_3550->serial_number_word2 =
11569 adv_dvc_varp->cfg->serial2;
11570 ep_3550->serial_number_word3 =
11571 adv_dvc_varp->cfg->serial3;
11572 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
11573 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
11574
11575 ep_38C0800->adapter_scsi_id =
11576 adv_dvc_varp->chip_scsi_id;
11577 ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
11578 ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11579 ep_38C0800->termination_lvd =
11580 adv_dvc_varp->cfg->termination;
11581 ep_38C0800->disc_enable =
11582 adv_dvc_varp->cfg->disc_enable;
11583 ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
11584 ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
11585 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
11586 ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
11587 ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
11588 ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
11589 ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
11590 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
11591 ep_38C0800->start_motor = adv_dvc_varp->start_motor;
11592 ep_38C0800->scsi_reset_delay =
11593 adv_dvc_varp->scsi_reset_wait;
11594 ep_38C0800->serial_number_word1 =
11595 adv_dvc_varp->cfg->serial1;
11596 ep_38C0800->serial_number_word2 =
11597 adv_dvc_varp->cfg->serial2;
11598 ep_38C0800->serial_number_word3 =
11599 adv_dvc_varp->cfg->serial3;
11600 } else {
11601 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
11602
11603 ep_38C1600->adapter_scsi_id =
11604 adv_dvc_varp->chip_scsi_id;
11605 ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
11606 ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11607 ep_38C1600->termination_lvd =
11608 adv_dvc_varp->cfg->termination;
11609 ep_38C1600->disc_enable =
11610 adv_dvc_varp->cfg->disc_enable;
11611 ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
11612 ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
11613 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
11614 ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
11615 ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
11616 ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
11617 ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
11618 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
11619 ep_38C1600->start_motor = adv_dvc_varp->start_motor;
11620 ep_38C1600->scsi_reset_delay =
11621 adv_dvc_varp->scsi_reset_wait;
11622 ep_38C1600->serial_number_word1 =
11623 adv_dvc_varp->cfg->serial1;
11624 ep_38C1600->serial_number_word2 =
11625 adv_dvc_varp->cfg->serial2;
11626 ep_38C1600->serial_number_word3 =
11627 adv_dvc_varp->cfg->serial3;
11628 }
11629
11630 /*
11631 * Set the adapter's target id bit in the 'init_tidmask' field.
11632 */
11633 boardp->init_tidmask |=
11634 ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
27c868c2
MW		 11635 }
11636
11637 /*
11638 * Channels are numbered beginning with 0. For AdvanSys one host
11639 * structure supports one channel. Multi-channel boards have a
11640 * separate host structure for each channel.
11641 */
11642 shost->max_channel = 0;
11643 if (ASC_NARROW_BOARD(boardp)) {
11644 shost->max_id = ASC_MAX_TID + 1;
11645 shost->max_lun = ASC_MAX_LUN + 1;
f05ec594 11646 shost->max_cmd_len = ASC_MAX_CDB_LEN;
27c868c2
MW		 11647
11648 shost->io_port = asc_dvc_varp->iop_base;
11649 boardp->asc_n_io_port = ASC_IOADR_GAP;
11650 shost->this_id = asc_dvc_varp->cfg->chip_scsi_id;
11651
11652 /* Set maximum number of queues the adapter can handle. */
11653 shost->can_queue = asc_dvc_varp->max_total_qng;
11654 } else {
11655 shost->max_id = ADV_MAX_TID + 1;
11656 shost->max_lun = ADV_MAX_LUN + 1;
f05ec594 11657 shost->max_cmd_len = ADV_MAX_CDB_LEN;
27c868c2
MW		 11658
11659 /*
11660 * Save the I/O Port address and length even though
11661 * I/O ports are not used to access Wide boards.
11662 * Instead the Wide boards are accessed with
11663 * PCI Memory Mapped I/O.
11664 */
11665 shost->io_port = iop;
27c868c2
MW		 11666
11667 shost->this_id = adv_dvc_varp->chip_scsi_id;
11668
11669 /* Set maximum number of queues the adapter can handle. */
11670 shost->can_queue = adv_dvc_varp->max_host_qng;
11671 }
11672
27c868c2
MW		 11673 /*
11674 * Following v1.3.89, 'cmd_per_lun' is no longer needed
11675 * and should be set to zero.
11676 *
11677 * But because of a bug introduced in v1.3.89 if the driver is
11678 * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level
11679 * SCSI function 'allocate_device' will panic. To allow the driver
11680 * to work as a module in these kernels set 'cmd_per_lun' to 1.
11681 *
11682 * Note: This is wrong. cmd_per_lun should be set to the depth
11683 * you want on untagged devices always.
11684 #ifdef MODULE
11685 */
11686 shost->cmd_per_lun = 1;
11687/* #else
11688 shost->cmd_per_lun = 0;
11689#endif */
11690
11691 /*
11692 * Set the maximum number of scatter-gather elements the
11693 * adapter can handle.
11694 */
11695 if (ASC_NARROW_BOARD(boardp)) {
11696 /*
11697 * Allow two commands with 'sg_tablesize' scatter-gather
11698 * elements to be executed simultaneously. This value is
11699 * the theoretical hardware limit. It may be decreased
11700 * below.
11701 */
11702 shost->sg_tablesize =
11703 (((asc_dvc_varp->max_total_qng - 2) / 2) *
11704 ASC_SG_LIST_PER_Q) + 1;
11705 } else {
11706 shost->sg_tablesize = ADV_MAX_SG_LIST;
11707 }
11708
11709 /*
11710 * The value of 'sg_tablesize' can not exceed the SCSI
11711 * mid-level driver definition of SG_ALL. SG_ALL also
11712 * must not be exceeded, because it is used to define the
11713 * size of the scatter-gather table in 'struct asc_sg_head'.
11714 */
11715 if (shost->sg_tablesize > SG_ALL) {
11716 shost->sg_tablesize = SG_ALL;
11717 }
11718
b352f923 11719 ASC_DBG(1, "sg_tablesize: %d\n", shost->sg_tablesize);
27c868c2
MW		 11720
11721 /* BIOS start address. */
11722 if (ASC_NARROW_BOARD(boardp)) {
b2c16f58
MW		 11723 shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base,
11724 asc_dvc_varp->bus_type);
27c868c2
MW		 11725 } else {
11726 /*
11727 * Fill-in BIOS board variables. The Wide BIOS saves
11728 * information in LRAM that is used by the driver.
11729 */
11730 AdvReadWordLram(adv_dvc_varp->iop_base,
11731 BIOS_SIGNATURE, boardp->bios_signature);
11732 AdvReadWordLram(adv_dvc_varp->iop_base,
11733 BIOS_VERSION, boardp->bios_version);
11734 AdvReadWordLram(adv_dvc_varp->iop_base,
11735 BIOS_CODESEG, boardp->bios_codeseg);
11736 AdvReadWordLram(adv_dvc_varp->iop_base,
11737 BIOS_CODELEN, boardp->bios_codelen);
11738
b352f923 11739 ASC_DBG(1, "bios_signature 0x%x, bios_version 0x%x\n",
27c868c2
MW		 11740 boardp->bios_signature, boardp->bios_version);
11741
b352f923 11742 ASC_DBG(1, "bios_codeseg 0x%x, bios_codelen 0x%x\n",
27c868c2
MW		 11743 boardp->bios_codeseg, boardp->bios_codelen);
11744
11745 /*
11746 * If the BIOS saved a valid signature, then fill in
11747 * the BIOS code segment base address.
11748 */
11749 if (boardp->bios_signature == 0x55AA) {
11750 /*
11751 * Convert x86 realmode code segment to a linear
11752 * address by shifting left 4.
11753 */
11754 shost->base = ((ulong)boardp->bios_codeseg << 4);
11755 } else {
11756 shost->base = 0;
11757 }
11758 }
11759
11760 /*
11761 * Register Board Resources - I/O Port, DMA, IRQ
11762 */
11763
27c868c2
MW		 11764 /* Register DMA Channel for Narrow boards. */
11765 shost->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */
11766#ifdef CONFIG_ISA
11767 if (ASC_NARROW_BOARD(boardp)) {
11768 /* Register DMA channel for ISA bus. */
11769 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
11770 shost->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
01fbfe0b 11771 ret = request_dma(shost->dma_channel, DRV_NAME);
b2c16f58 11772 if (ret) {
9d0e96eb
MW		 11773 shost_printk(KERN_ERR, shost, "request_dma() "
11774 "%d failed %d\n",
11775 shost->dma_channel, ret);
b59fb6fd 11776 goto err_unmap;
27c868c2
MW		 11777 }
11778 AscEnableIsaDma(shost->dma_channel);
11779 }
11780 }
11781#endif /* CONFIG_ISA */
11782
11783 /* Register IRQ Number. */
b352f923 11784 ASC_DBG(2, "request_irq(%d, %p)\n", boardp->irq, shost);
074c8fe4 11785
d361db48 11786 ret = request_irq(boardp->irq, advansys_interrupt, share_irq,
01fbfe0b 11787 DRV_NAME, shost);
074c8fe4
MW		 11788
11789 if (ret) {
27c868c2 11790 if (ret == -EBUSY) {
9d0e96eb
MW		 11791 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11792 "already in use\n", boardp->irq);
27c868c2 11793 } else if (ret == -EINVAL) {
9d0e96eb
MW		 11794 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11795 "not valid\n", boardp->irq);
27c868c2 11796 } else {
9d0e96eb
MW		 11797 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11798 "failed with %d\n", boardp->irq, ret);
27c868c2 11799 }
b2c16f58 11800 goto err_free_dma;
27c868c2
MW		 11801 }
11802
11803 /*
11804 * Initialize board RISC chip and enable interrupts.
11805 */
11806 if (ASC_NARROW_BOARD(boardp)) {
b352f923 11807 ASC_DBG(2, "AscInitAsc1000Driver()\n");
7d5d408c
FT		 11808
11809 asc_dvc_varp->overrun_buf = kzalloc(ASC_OVERRUN_BSIZE, GFP_KERNEL);
11810 if (!asc_dvc_varp->overrun_buf) {
11811 ret = -ENOMEM;
9a908c1a 11812 goto err_free_irq;
7d5d408c 11813 }
27c868c2 11814 warn_code = AscInitAsc1000Driver(asc_dvc_varp);
27c868c2 11815
d361db48 11816 if (warn_code || asc_dvc_varp->err_code) {
9d0e96eb
MW		 11817 shost_printk(KERN_ERR, shost, "error: init_state 0x%x, "
11818 "warn 0x%x, error 0x%x\n",
11819 asc_dvc_varp->init_state, warn_code,
11820 asc_dvc_varp->err_code);
9a908c1a 11821 if (!asc_dvc_varp->overrun_dma) {
d361db48 11822 ret = -ENODEV;
9a908c1a 11823 goto err_free_mem;
7d5d408c 11824 }
27c868c2
MW		 11825 }
11826 } else {
9a908c1a 11827 if (advansys_wide_init_chip(shost)) {
d361db48 11828 ret = -ENODEV;
9a908c1a
HRK		 11829 goto err_free_mem;
11830 }
27c868c2
MW		 11831 }
11832
27c868c2
MW		 11833 ASC_DBG_PRT_SCSI_HOST(2, shost);
11834
d361db48 11835 ret = scsi_add_host(shost, boardp->dev);
8dfb5379 11836 if (ret)
9a908c1a 11837 goto err_free_mem;
8dfb5379
MW		 11838
11839 scsi_scan_host(shost);
d361db48 11840 return 0;
b2c16f58 11841
9a908c1a
HRK		 11842 err_free_mem:
11843 if (ASC_NARROW_BOARD(boardp)) {
11844 if (asc_dvc_varp->overrun_dma)
11845 dma_unmap_single(boardp->dev, asc_dvc_varp->overrun_dma,
11846 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
11847 kfree(asc_dvc_varp->overrun_buf);
11848 } else
11849 advansys_wide_free_mem(boardp);
11850 err_free_irq:
d361db48 11851 free_irq(boardp->irq, shost);
b2c16f58 11852 err_free_dma:
30037818 11853#ifdef CONFIG_ISA
b2c16f58
MW		 11854 if (shost->dma_channel != NO_ISA_DMA)
11855 free_dma(shost->dma_channel);
30037818 11856#endif
b2c16f58
MW		 11857 err_unmap:
11858 if (boardp->ioremap_addr)
11859 iounmap(boardp->ioremap_addr);
11860 err_shost:
d361db48 11861 return ret;
27c868c2
MW		 11862}
11863
27c868c2
MW		 11864/*
11865 * advansys_release()
11866 *
11867 * Release resources allocated for a single AdvanSys adapter.
11868 */
11869static int advansys_release(struct Scsi_Host *shost)
11870{
d10fb2c7 11871 struct asc_board *board = shost_priv(shost);
b352f923 11872 ASC_DBG(1, "begin\n");
8dfb5379 11873 scsi_remove_host(shost);
d10fb2c7 11874 free_irq(board->irq, shost);
30037818 11875#ifdef CONFIG_ISA
27c868c2 11876 if (shost->dma_channel != NO_ISA_DMA) {
b352f923 11877 ASC_DBG(1, "free_dma()\n");
27c868c2
MW		 11878 free_dma(shost->dma_channel);
11879 }
30037818 11880#endif
d10fb2c7
MW		 11881 if (ASC_NARROW_BOARD(board)) {
11882 dma_unmap_single(board->dev,
11883 board->dvc_var.asc_dvc_var.overrun_dma,
11884 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
7d5d408c 11885 kfree(board->dvc_var.asc_dvc_var.overrun_buf);
d10fb2c7
MW		 11886 } else {
11887 iounmap(board->ioremap_addr);
11888 advansys_wide_free_mem(board);
27c868c2 11889 }
8dfb5379 11890 scsi_host_put(shost);
b352f923 11891 ASC_DBG(1, "end\n");
27c868c2
MW		 11892 return 0;
11893}
11894
95c9f162
MW		 11895#define ASC_IOADR_TABLE_MAX_IX 11
11896
747d016e 11897static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] = {
c304ec94
MW		 11898 0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190,
11899 0x0210, 0x0230, 0x0250, 0x0330
11900};
11901
d361db48
MW		 11902/*
11903 * The ISA IRQ number is found in bits 2 and 3 of the CfgLsw. It decodes as:
11904 * 00: 10
11905 * 01: 11
11906 * 10: 12
11907 * 11: 15
11908 */
6f039790 11909static unsigned int advansys_isa_irq_no(PortAddr iop_base)
d361db48
MW		 11910{
11911 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
11912 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x03) + 10;
11913 if (chip_irq == 13)
11914 chip_irq = 15;
11915 return chip_irq;
11916}
11917
6f039790 11918static int advansys_isa_probe(struct device *dev, unsigned int id)
c304ec94 11919{
d361db48 11920 int err = -ENODEV;
c304ec94
MW		 11921 PortAddr iop_base = _asc_def_iop_base[id];
11922 struct Scsi_Host *shost;
d361db48 11923 struct asc_board *board;
c304ec94 11924
01fbfe0b 11925 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
b352f923 11926 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
c304ec94
MW		 11927 return -ENODEV;
11928 }
b352f923 11929 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
c304ec94 11930 if (!AscFindSignature(iop_base))
d361db48 11931 goto release_region;
c304ec94 11932 if (!(AscGetChipVersion(iop_base, ASC_IS_ISA) & ASC_CHIP_VER_ISA_BIT))
d361db48 11933 goto release_region;
c304ec94 11934
d361db48
MW		 11935 err = -ENOMEM;
11936 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
c304ec94 11937 if (!shost)
d361db48
MW		 11938 goto release_region;
11939
d2411495 11940 board = shost_priv(shost);
d361db48
MW		 11941 board->irq = advansys_isa_irq_no(iop_base);
11942 board->dev = dev;
11943
11944 err = advansys_board_found(shost, iop_base, ASC_IS_ISA);
11945 if (err)
11946 goto free_host;
c304ec94
MW		 11947
11948 dev_set_drvdata(dev, shost);
11949 return 0;
11950
d361db48
MW		 11951 free_host:
11952 scsi_host_put(shost);
11953 release_region:
71f36115 11954 release_region(iop_base, ASC_IOADR_GAP);
d361db48 11955 return err;
c304ec94
MW		 11956}
11957
6f039790 11958static int advansys_isa_remove(struct device *dev, unsigned int id)
c304ec94 11959{
71f36115 11960 int ioport = _asc_def_iop_base[id];
c304ec94 11961 advansys_release(dev_get_drvdata(dev));
71f36115 11962 release_region(ioport, ASC_IOADR_GAP);
c304ec94
MW		 11963 return 0;
11964}
11965
11966static struct isa_driver advansys_isa_driver = {
11967 .probe = advansys_isa_probe,
6f039790 11968 .remove = advansys_isa_remove,
c304ec94
MW		 11969 .driver = {
11970 .owner = THIS_MODULE,
01fbfe0b 11971 .name = DRV_NAME,
c304ec94
MW		 11972 },
11973};
11974
d361db48
MW		 11975/*
11976 * The VLB IRQ number is found in bits 2 to 4 of the CfgLsw. It decodes as:
11977 * 000: invalid
11978 * 001: 10
11979 * 010: 11
11980 * 011: 12
11981 * 100: invalid
11982 * 101: 14
11983 * 110: 15
11984 * 111: invalid
11985 */
6f039790 11986static unsigned int advansys_vlb_irq_no(PortAddr iop_base)
d361db48
MW		 11987{
11988 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
11989 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x07) + 9;
11990 if ((chip_irq < 10) || (chip_irq == 13) || (chip_irq > 15))
11991 return 0;
11992 return chip_irq;
11993}
11994
6f039790 11995static int advansys_vlb_probe(struct device *dev, unsigned int id)
c304ec94 11996{
d361db48 11997 int err = -ENODEV;
c304ec94
MW		 11998 PortAddr iop_base = _asc_def_iop_base[id];
11999 struct Scsi_Host *shost;
d361db48 12000 struct asc_board *board;
c304ec94 12001
01fbfe0b 12002 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
b352f923 12003 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
c304ec94
MW		 12004 return -ENODEV;
12005 }
b352f923 12006 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
c304ec94 12007 if (!AscFindSignature(iop_base))
d361db48 12008 goto release_region;
c304ec94
MW		 12009 /*
12010 * I don't think this condition can actually happen, but the old
12011 * driver did it, and the chances of finding a VLB setup in 2007
12012 * to do testing with is slight to none.
12013 */
12014 if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL)
d361db48 12015 goto release_region;
c304ec94 12016
d361db48
MW		 12017 err = -ENOMEM;
12018 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
c304ec94 12019 if (!shost)
d361db48
MW		 12020 goto release_region;
12021
d2411495 12022 board = shost_priv(shost);
d361db48
MW		 12023 board->irq = advansys_vlb_irq_no(iop_base);
12024 board->dev = dev;
12025
12026 err = advansys_board_found(shost, iop_base, ASC_IS_VL);
12027 if (err)
12028 goto free_host;
c304ec94
MW		 12029
12030 dev_set_drvdata(dev, shost);
12031 return 0;
12032
d361db48
MW		 12033 free_host:
12034 scsi_host_put(shost);
12035 release_region:
71f36115 12036 release_region(iop_base, ASC_IOADR_GAP);
c304ec94
MW		 12037 return -ENODEV;
12038}
12039
12040static struct isa_driver advansys_vlb_driver = {
12041 .probe = advansys_vlb_probe,
6f039790 12042 .remove = advansys_isa_remove,
c304ec94
MW		 12043 .driver = {
12044 .owner = THIS_MODULE,
b8e5152b 12045 .name = "advansys_vlb",
c304ec94
MW		 12046 },
12047};
12048
6f039790 12049static struct eisa_device_id advansys_eisa_table[] = {
b09e05a7
MW		 12050 { "ABP7401" },
12051 { "ABP7501" },
12052 { "" }
12053};
12054
12055MODULE_DEVICE_TABLE(eisa, advansys_eisa_table);
12056
12057/*
12058 * EISA is a little more tricky than PCI; each EISA device may have two
12059 * channels, and this driver is written to make each channel its own Scsi_Host
12060 */
12061struct eisa_scsi_data {
12062 struct Scsi_Host *host[2];
12063};
12064
d361db48
MW		 12065/*
12066 * The EISA IRQ number is found in bits 8 to 10 of the CfgLsw. It decodes as:
12067 * 000: 10
12068 * 001: 11
12069 * 010: 12
12070 * 011: invalid
12071 * 100: 14
12072 * 101: 15
12073 * 110: invalid
12074 * 111: invalid
12075 */
6f039790 12076static unsigned int advansys_eisa_irq_no(struct eisa_device *edev)
d361db48
MW		 12077{
12078 unsigned short cfg_lsw = inw(edev->base_addr + 0xc86);
12079 unsigned int chip_irq = ((cfg_lsw >> 8) & 0x07) + 10;
12080 if ((chip_irq == 13) || (chip_irq > 15))
12081 return 0;
12082 return chip_irq;
12083}
12084
6f039790 12085static int advansys_eisa_probe(struct device *dev)
b09e05a7 12086{
d361db48 12087 int i, ioport, irq = 0;
b09e05a7
MW		 12088 int err;
12089 struct eisa_device *edev = to_eisa_device(dev);
12090 struct eisa_scsi_data *data;
12091
12092 err = -ENOMEM;
12093 data = kzalloc(sizeof(*data), GFP_KERNEL);
12094 if (!data)
12095 goto fail;
12096 ioport = edev->base_addr + 0xc30;
12097
12098 err = -ENODEV;
12099 for (i = 0; i < 2; i++, ioport += 0x20) {
d361db48
MW		 12100 struct asc_board *board;
12101 struct Scsi_Host *shost;
01fbfe0b 12102 if (!request_region(ioport, ASC_IOADR_GAP, DRV_NAME)) {
71f36115
MW		 12103 printk(KERN_WARNING "Region %x-%x busy\n", ioport,
12104 ioport + ASC_IOADR_GAP - 1);
12105 continue;
12106 }
12107 if (!AscFindSignature(ioport)) {
12108 release_region(ioport, ASC_IOADR_GAP);
b09e05a7 12109 continue;
71f36115
MW		 12110 }
12111
b09e05a7
MW		 12112 /*
12113 * I don't know why we need to do this for EISA chips, but
12114 * not for any others. It looks to be equivalent to
12115 * AscGetChipCfgMsw, but I may have overlooked something,
12116 * so I'm not converting it until I get an EISA board to
12117 * test with.
12118 */
12119 inw(ioport + 4);
d361db48
MW		 12120
12121 if (!irq)
12122 irq = advansys_eisa_irq_no(edev);
12123
12124 err = -ENOMEM;
12125 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
12126 if (!shost)
12127 goto release_region;
12128
d2411495 12129 board = shost_priv(shost);
d361db48
MW		 12130 board->irq = irq;
12131 board->dev = dev;
12132
12133 err = advansys_board_found(shost, ioport, ASC_IS_EISA);
12134 if (!err) {
12135 data->host[i] = shost;
12136 continue;
71f36115 12137 }
b09e05a7 12138
d361db48
MW		 12139 scsi_host_put(shost);
12140 release_region:
12141 release_region(ioport, ASC_IOADR_GAP);
12142 break;
b09e05a7
MW		 12143 }
12144
d361db48
MW		 12145 if (err)
12146 goto free_data;
12147 dev_set_drvdata(dev, data);
12148 return 0;
12149
12150 free_data:
12151 kfree(data->host[0]);
12152 kfree(data->host[1]);
12153 kfree(data);
b09e05a7
MW		 12154 fail:
12155 return err;
12156}
12157
6f039790 12158static int advansys_eisa_remove(struct device *dev)
b09e05a7
MW		 12159{
12160 int i;
12161 struct eisa_scsi_data *data = dev_get_drvdata(dev);
12162
12163 for (i = 0; i < 2; i++) {
71f36115 12164 int ioport;
b09e05a7
MW		 12165 struct Scsi_Host *shost = data->host[i];
12166 if (!shost)
12167 continue;
71f36115 12168 ioport = shost->io_port;
b09e05a7 12169 advansys_release(shost);
71f36115 12170 release_region(ioport, ASC_IOADR_GAP);
b09e05a7
MW		 12171 }
12172
12173 kfree(data);
12174 return 0;
12175}
12176
12177static struct eisa_driver advansys_eisa_driver = {
12178 .id_table = advansys_eisa_table,
12179 .driver = {
01fbfe0b 12180 .name = DRV_NAME,
b09e05a7 12181 .probe = advansys_eisa_probe,
6f039790 12182 .remove = advansys_eisa_remove,
b09e05a7
MW		 12183 }
12184};
12185
2672ea86 12186/* PCI Devices supported by this driver */
6f039790 12187static struct pci_device_id advansys_pci_tbl[] = {
27c868c2
MW		 12188 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A,
12189 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12190 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940,
12191 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12192 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U,
12193 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12194 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW,
12195 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12196 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1,
12197 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12198 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1,
12199 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12200 {}
2672ea86 12201};
27c868c2 12202
2672ea86 12203MODULE_DEVICE_TABLE(pci, advansys_pci_tbl);
78e77d8b 12204
6f039790 12205static void advansys_set_latency(struct pci_dev *pdev)
9649af39
MW		 12206{
12207 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
12208 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
12209 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0);
12210 } else {
12211 u8 latency;
12212 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency);
12213 if (latency < 0x20)
12214 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
12215 }
12216}
12217
6f039790
GKH		 12218static int advansys_pci_probe(struct pci_dev *pdev,
12219 const struct pci_device_id *ent)
78e77d8b
MW		 12220{
12221 int err, ioport;
12222 struct Scsi_Host *shost;
d361db48 12223 struct asc_board *board;
78e77d8b
MW		 12224
12225 err = pci_enable_device(pdev);
12226 if (err)
12227 goto fail;
01fbfe0b 12228 err = pci_request_regions(pdev, DRV_NAME);
71f36115
MW		 12229 if (err)
12230 goto disable_device;
9649af39
MW		 12231 pci_set_master(pdev);
12232 advansys_set_latency(pdev);
78e77d8b 12233
d361db48 12234 err = -ENODEV;
78e77d8b 12235 if (pci_resource_len(pdev, 0) == 0)
d361db48 12236 goto release_region;
78e77d8b
MW		 12237
12238 ioport = pci_resource_start(pdev, 0);
78e77d8b 12239
d361db48
MW		 12240 err = -ENOMEM;
12241 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
78e77d8b 12242 if (!shost)
d361db48
MW		 12243 goto release_region;
12244
d2411495 12245 board = shost_priv(shost);
d361db48
MW		 12246 board->irq = pdev->irq;
12247 board->dev = &pdev->dev;
12248
12249 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW ||
12250 pdev->device == PCI_DEVICE_ID_38C0800_REV1 ||
12251 pdev->device == PCI_DEVICE_ID_38C1600_REV1) {
12252 board->flags |= ASC_IS_WIDE_BOARD;
12253 }
12254
12255 err = advansys_board_found(shost, ioport, ASC_IS_PCI);
12256 if (err)
12257 goto free_host;
78e77d8b
MW		 12258
12259 pci_set_drvdata(pdev, shost);
12260 return 0;
12261
d361db48
MW		 12262 free_host:
12263 scsi_host_put(shost);
12264 release_region:
71f36115
MW		 12265 pci_release_regions(pdev);
12266 disable_device:
78e77d8b
MW		 12267 pci_disable_device(pdev);
12268 fail:
12269 return err;
12270}
12271
6f039790 12272static void advansys_pci_remove(struct pci_dev *pdev)
78e77d8b
MW		 12273{
12274 advansys_release(pci_get_drvdata(pdev));
71f36115 12275 pci_release_regions(pdev);
78e77d8b
MW		 12276 pci_disable_device(pdev);
12277}
12278
12279static struct pci_driver advansys_pci_driver = {
01fbfe0b 12280 .name = DRV_NAME,
78e77d8b
MW		 12281 .id_table = advansys_pci_tbl,
12282 .probe = advansys_pci_probe,
6f039790 12283 .remove = advansys_pci_remove,
78e77d8b 12284};
8c6af9e1 12285
8dfb5379
MW		 12286static int __init advansys_init(void)
12287{
c304ec94 12288 int error;
b09e05a7 12289
c304ec94
MW		 12290 error = isa_register_driver(&advansys_isa_driver,
12291 ASC_IOADR_TABLE_MAX_IX);
78e77d8b
MW		 12292 if (error)
12293 goto fail;
8dfb5379 12294
c304ec94
MW		 12295 error = isa_register_driver(&advansys_vlb_driver,
12296 ASC_IOADR_TABLE_MAX_IX);
12297 if (error)
12298 goto unregister_isa;
12299
12300 error = eisa_driver_register(&advansys_eisa_driver);
12301 if (error)
12302 goto unregister_vlb;
12303
b09e05a7
MW		 12304 error = pci_register_driver(&advansys_pci_driver);
12305 if (error)
12306 goto unregister_eisa;
12307
8dfb5379 12308 return 0;
78e77d8b 12309
b09e05a7
MW		 12310 unregister_eisa:
12311 eisa_driver_unregister(&advansys_eisa_driver);
c304ec94
MW		 12312 unregister_vlb:
12313 isa_unregister_driver(&advansys_vlb_driver);
12314 unregister_isa:
12315 isa_unregister_driver(&advansys_isa_driver);
78e77d8b 12316 fail:
78e77d8b 12317 return error;
8dfb5379
MW		 12318}
12319
12320static void __exit advansys_exit(void)
12321{
78e77d8b 12322 pci_unregister_driver(&advansys_pci_driver);
b09e05a7 12323 eisa_driver_unregister(&advansys_eisa_driver);
c304ec94
MW		 12324 isa_unregister_driver(&advansys_vlb_driver);
12325 isa_unregister_driver(&advansys_isa_driver);
8dfb5379
MW		 12326}
12327
12328module_init(advansys_init);
12329module_exit(advansys_exit);
12330
8c6af9e1 12331MODULE_LICENSE("GPL");
989bb5f5
JSR		 12332MODULE_FIRMWARE("advansys/mcode.bin");
12333MODULE_FIRMWARE("advansys/3550.bin");
12334MODULE_FIRMWARE("advansys/38C0800.bin");
12335MODULE_FIRMWARE("advansys/38C1600.bin");
Linux kernel - Deliverables
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