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advansys: use shared host tag map for command lookup
[deliverable/linux.git] / drivers / scsi / advansys.c
CommitLineData
01fbfe0b 1#define DRV_NAME "advansys"
8c6af9e1 2#define ASC_VERSION "3.4" /* AdvanSys Driver Version */
1da177e4
LT		 3
4/*
5 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
6 *
7 * Copyright (c) 1995-2000 Advanced System Products, Inc.
8 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
8c6af9e1 9 * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
1da177e4
LT		 10 * All Rights Reserved.
11 *
8c6af9e1
MW		 12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 */
17
18/*
1da177e4
LT		 19 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
20 * changed its name to ConnectCom Solutions, Inc.
8c6af9e1 21 * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
1da177e4
LT		 22 */
23
1da177e4 24#include <linux/module.h>
1da177e4
LT		 25#include <linux/string.h>
26#include <linux/kernel.h>
27#include <linux/types.h>
28#include <linux/ioport.h>
29#include <linux/interrupt.h>
30#include <linux/delay.h>
31#include <linux/slab.h>
32#include <linux/mm.h>
33#include <linux/proc_fs.h>
34#include <linux/init.h>
35#include <linux/blkdev.h>
c304ec94 36#include <linux/isa.h>
b09e05a7 37#include <linux/eisa.h>
8c6af9e1 38#include <linux/pci.h>
1da177e4
LT		 39#include <linux/spinlock.h>
40#include <linux/dma-mapping.h>
989bb5f5 41#include <linux/firmware.h>
1da177e4
LT		 42
43#include <asm/io.h>
1da177e4
LT		 44#include <asm/dma.h>
45
8c6af9e1
MW		 46#include <scsi/scsi_cmnd.h>
47#include <scsi/scsi_device.h>
48#include <scsi/scsi_tcq.h>
49#include <scsi/scsi.h>
50#include <scsi/scsi_host.h>
51
4bd6d7f3 52/* FIXME:
1da177e4 53 *
4bd6d7f3
MW		 54 * 1. Although all of the necessary command mapping places have the
55 * appropriate dma_map.. APIs, the driver still processes its internal
56 * queue using bus_to_virt() and virt_to_bus() which are illegal under
57 * the API. The entire queue processing structure will need to be
58 * altered to fix this.
59 * 2. Need to add memory mapping workaround. Test the memory mapping.
60 * If it doesn't work revert to I/O port access. Can a test be done
61 * safely?
62 * 3. Handle an interrupt not working. Keep an interrupt counter in
63 * the interrupt handler. In the timeout function if the interrupt
64 * has not occurred then print a message and run in polled mode.
65 * 4. Need to add support for target mode commands, cf. CAM XPT.
66 * 5. check DMA mapping functions for failure
349d2c44
MW		 67 * 6. Use scsi_transport_spi
68 * 7. advansys_info is not safe against multiple simultaneous callers
9d0e96eb 69 * 8. Add module_param to override ISA/VLB ioport array
1da177e4
LT		 70 */
71#warning this driver is still not properly converted to the DMA API
72
1da177e4
LT		 73/* Enable driver /proc statistics. */
74#define ADVANSYS_STATS
75
76/* Enable driver tracing. */
b352f923 77#undef ADVANSYS_DEBUG
1da177e4 78
1da177e4
LT		 79/*
80 * Portable Data Types
81 *
82 * Any instance where a 32-bit long or pointer type is assumed
83 * for precision or HW defined structures, the following define
84 * types must be used. In Linux the char, short, and int types
85 * are all consistent at 8, 16, and 32 bits respectively. Pointers
86 * and long types are 64 bits on Alpha and UltraSPARC.
87 */
27c868c2
MW		 88#define ASC_PADDR __u32 /* Physical/Bus address data type. */
89#define ASC_VADDR __u32 /* Virtual address data type. */
90#define ASC_DCNT __u32 /* Unsigned Data count type. */
91#define ASC_SDCNT __s32 /* Signed Data count type. */
1da177e4 92
1da177e4
LT		 93typedef unsigned char uchar;
94
95#ifndef TRUE
96#define TRUE (1)
97#endif
98#ifndef FALSE
99#define FALSE (0)
100#endif
101
1da177e4
LT		 102#define ERR (-1)
103#define UW_ERR (uint)(0xFFFF)
104#define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
1da177e4 105
2672ea86
DJ		 106#define PCI_VENDOR_ID_ASP 0x10cd
107#define PCI_DEVICE_ID_ASP_1200A 0x1100
108#define PCI_DEVICE_ID_ASP_ABP940 0x1200
109#define PCI_DEVICE_ID_ASP_ABP940U 0x1300
110#define PCI_DEVICE_ID_ASP_ABP940UW 0x2300
111#define PCI_DEVICE_ID_38C0800_REV1 0x2500
112#define PCI_DEVICE_ID_38C1600_REV1 0x2700
113
1da177e4
LT		 114/*
115 * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
116 * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
117 * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
118 * SRB structure.
119 */
120#define CC_VERY_LONG_SG_LIST 0
121#define ASC_SRB2SCSIQ(srb_ptr) (srb_ptr)
122
9d511a4b 123#define PortAddr unsigned int /* port address size */
1da177e4
LT		 124#define inp(port) inb(port)
125#define outp(port, byte) outb((byte), (port))
126
127#define inpw(port) inw(port)
128#define outpw(port, word) outw((word), (port))
129
130#define ASC_MAX_SG_QUEUE 7
131#define ASC_MAX_SG_LIST 255
132
133#define ASC_CS_TYPE unsigned short
134
135#define ASC_IS_ISA (0x0001)
136#define ASC_IS_ISAPNP (0x0081)
137#define ASC_IS_EISA (0x0002)
138#define ASC_IS_PCI (0x0004)
139#define ASC_IS_PCI_ULTRA (0x0104)
140#define ASC_IS_PCMCIA (0x0008)
141#define ASC_IS_MCA (0x0020)
142#define ASC_IS_VL (0x0040)
1da177e4
LT		 143#define ASC_IS_WIDESCSI_16 (0x0100)
144#define ASC_IS_WIDESCSI_32 (0x0200)
145#define ASC_IS_BIG_ENDIAN (0x8000)
95c9f162 146
1da177e4
LT		 147#define ASC_CHIP_MIN_VER_VL (0x01)
148#define ASC_CHIP_MAX_VER_VL (0x07)
149#define ASC_CHIP_MIN_VER_PCI (0x09)
150#define ASC_CHIP_MAX_VER_PCI (0x0F)
151#define ASC_CHIP_VER_PCI_BIT (0x08)
152#define ASC_CHIP_MIN_VER_ISA (0x11)
153#define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
154#define ASC_CHIP_MAX_VER_ISA (0x27)
155#define ASC_CHIP_VER_ISA_BIT (0x30)
156#define ASC_CHIP_VER_ISAPNP_BIT (0x20)
157#define ASC_CHIP_VER_ASYN_BUG (0x21)
158#define ASC_CHIP_VER_PCI 0x08
159#define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
160#define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
161#define ASC_CHIP_MIN_VER_EISA (0x41)
162#define ASC_CHIP_MAX_VER_EISA (0x47)
163#define ASC_CHIP_VER_EISA_BIT (0x40)
164#define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
1da177e4 165#define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
1da177e4 166#define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
1da177e4 167#define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL)
1da177e4
LT		 168
169#define ASC_SCSI_ID_BITS 3
170#define ASC_SCSI_TIX_TYPE uchar
171#define ASC_ALL_DEVICE_BIT_SET 0xFF
172#define ASC_SCSI_BIT_ID_TYPE uchar
173#define ASC_MAX_TID 7
174#define ASC_MAX_LUN 7
175#define ASC_SCSI_WIDTH_BIT_SET 0xFF
176#define ASC_MAX_SENSE_LEN 32
177#define ASC_MIN_SENSE_LEN 14
1da177e4
LT		 178#define ASC_SCSI_RESET_HOLD_TIME_US 60
179
f05ec594
MW		 180/*
181 * Narrow boards only support 12-byte commands, while wide boards
182 * extend to 16-byte commands.
183 */
184#define ASC_MAX_CDB_LEN 12
185#define ADV_MAX_CDB_LEN 16
186
1da177e4 187#define MS_SDTR_LEN 0x03
1da177e4 188#define MS_WDTR_LEN 0x02
1da177e4
LT		 189
190#define ASC_SG_LIST_PER_Q 7
191#define QS_FREE 0x00
192#define QS_READY 0x01
193#define QS_DISC1 0x02
194#define QS_DISC2 0x04
195#define QS_BUSY 0x08
196#define QS_ABORTED 0x40
197#define QS_DONE 0x80
198#define QC_NO_CALLBACK 0x01
199#define QC_SG_SWAP_QUEUE 0x02
200#define QC_SG_HEAD 0x04
201#define QC_DATA_IN 0x08
202#define QC_DATA_OUT 0x10
203#define QC_URGENT 0x20
204#define QC_MSG_OUT 0x40
205#define QC_REQ_SENSE 0x80
206#define QCSG_SG_XFER_LIST 0x02
207#define QCSG_SG_XFER_MORE 0x04
208#define QCSG_SG_XFER_END 0x08
209#define QD_IN_PROGRESS 0x00
210#define QD_NO_ERROR 0x01
211#define QD_ABORTED_BY_HOST 0x02
212#define QD_WITH_ERROR 0x04
213#define QD_INVALID_REQUEST 0x80
214#define QD_INVALID_HOST_NUM 0x81
215#define QD_INVALID_DEVICE 0x82
216#define QD_ERR_INTERNAL 0xFF
217#define QHSTA_NO_ERROR 0x00
218#define QHSTA_M_SEL_TIMEOUT 0x11
219#define QHSTA_M_DATA_OVER_RUN 0x12
220#define QHSTA_M_DATA_UNDER_RUN 0x12
221#define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
222#define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
223#define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
224#define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
225#define QHSTA_D_HOST_ABORT_FAILED 0x23
226#define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
227#define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
228#define QHSTA_D_ASPI_NO_BUF_POOL 0x26
229#define QHSTA_M_WTM_TIMEOUT 0x41
230#define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
231#define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
232#define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
233#define QHSTA_M_TARGET_STATUS_BUSY 0x45
234#define QHSTA_M_BAD_TAG_CODE 0x46
235#define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
236#define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
237#define QHSTA_D_LRAM_CMP_ERROR 0x81
238#define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
239#define ASC_FLAG_SCSIQ_REQ 0x01
240#define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
241#define ASC_FLAG_BIOS_ASYNC_IO 0x04
242#define ASC_FLAG_SRB_LINEAR_ADDR 0x08
243#define ASC_FLAG_WIN16 0x10
244#define ASC_FLAG_WIN32 0x20
245#define ASC_FLAG_ISA_OVER_16MB 0x40
246#define ASC_FLAG_DOS_VM_CALLBACK 0x80
247#define ASC_TAG_FLAG_EXTRA_BYTES 0x10
248#define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
249#define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
250#define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
251#define ASC_SCSIQ_CPY_BEG 4
252#define ASC_SCSIQ_SGHD_CPY_BEG 2
253#define ASC_SCSIQ_B_FWD 0
254#define ASC_SCSIQ_B_BWD 1
255#define ASC_SCSIQ_B_STATUS 2
256#define ASC_SCSIQ_B_QNO 3
257#define ASC_SCSIQ_B_CNTL 4
258#define ASC_SCSIQ_B_SG_QUEUE_CNT 5
259#define ASC_SCSIQ_D_DATA_ADDR 8
260#define ASC_SCSIQ_D_DATA_CNT 12
261#define ASC_SCSIQ_B_SENSE_LEN 20
262#define ASC_SCSIQ_DONE_INFO_BEG 22
263#define ASC_SCSIQ_D_SRBPTR 22
264#define ASC_SCSIQ_B_TARGET_IX 26
265#define ASC_SCSIQ_B_CDB_LEN 28
266#define ASC_SCSIQ_B_TAG_CODE 29
267#define ASC_SCSIQ_W_VM_ID 30
268#define ASC_SCSIQ_DONE_STATUS 32
269#define ASC_SCSIQ_HOST_STATUS 33
270#define ASC_SCSIQ_SCSI_STATUS 34
271#define ASC_SCSIQ_CDB_BEG 36
272#define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
273#define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
274#define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
275#define ASC_SCSIQ_B_SG_WK_QP 49
276#define ASC_SCSIQ_B_SG_WK_IX 50
277#define ASC_SCSIQ_W_ALT_DC1 52
278#define ASC_SCSIQ_B_LIST_CNT 6
279#define ASC_SCSIQ_B_CUR_LIST_CNT 7
280#define ASC_SGQ_B_SG_CNTL 4
281#define ASC_SGQ_B_SG_HEAD_QP 5
282#define ASC_SGQ_B_SG_LIST_CNT 6
283#define ASC_SGQ_B_SG_CUR_LIST_CNT 7
284#define ASC_SGQ_LIST_BEG 8
285#define ASC_DEF_SCSI1_QNG 4
286#define ASC_MAX_SCSI1_QNG 4
287#define ASC_DEF_SCSI2_QNG 16
288#define ASC_MAX_SCSI2_QNG 32
289#define ASC_TAG_CODE_MASK 0x23
290#define ASC_STOP_REQ_RISC_STOP 0x01
291#define ASC_STOP_ACK_RISC_STOP 0x03
292#define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
293#define ASC_STOP_CLEAN_UP_DISC_Q 0x20
294#define ASC_STOP_HOST_REQ_RISC_HALT 0x40
295#define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
296#define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
297#define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
298#define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
299#define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
300#define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
301#define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
302
303typedef struct asc_scsiq_1 {
27c868c2
MW		 304 uchar status;
305 uchar q_no;
306 uchar cntl;
307 uchar sg_queue_cnt;
308 uchar target_id;
309 uchar target_lun;
310 ASC_PADDR data_addr;
311 ASC_DCNT data_cnt;
312 ASC_PADDR sense_addr;
313 uchar sense_len;
314 uchar extra_bytes;
1da177e4
LT		 315} ASC_SCSIQ_1;
316
317typedef struct asc_scsiq_2 {
9c17c62a 318 u32 srb_tag;
27c868c2
MW		 319 uchar target_ix;
320 uchar flag;
321 uchar cdb_len;
322 uchar tag_code;
323 ushort vm_id;
1da177e4
LT		 324} ASC_SCSIQ_2;
325
326typedef struct asc_scsiq_3 {
27c868c2
MW		 327 uchar done_stat;
328 uchar host_stat;
329 uchar scsi_stat;
330 uchar scsi_msg;
1da177e4
LT		 331} ASC_SCSIQ_3;
332
333typedef struct asc_scsiq_4 {
27c868c2
MW		 334 uchar cdb[ASC_MAX_CDB_LEN];
335 uchar y_first_sg_list_qp;
336 uchar y_working_sg_qp;
337 uchar y_working_sg_ix;
338 uchar y_res;
339 ushort x_req_count;
340 ushort x_reconnect_rtn;
341 ASC_PADDR x_saved_data_addr;
342 ASC_DCNT x_saved_data_cnt;
1da177e4
LT		 343} ASC_SCSIQ_4;
344
345typedef struct asc_q_done_info {
27c868c2
MW		 346 ASC_SCSIQ_2 d2;
347 ASC_SCSIQ_3 d3;
348 uchar q_status;
349 uchar q_no;
350 uchar cntl;
351 uchar sense_len;
352 uchar extra_bytes;
353 uchar res;
354 ASC_DCNT remain_bytes;
1da177e4
LT		 355} ASC_QDONE_INFO;
356
357typedef struct asc_sg_list {
27c868c2
MW		 358 ASC_PADDR addr;
359 ASC_DCNT bytes;
1da177e4
LT		 360} ASC_SG_LIST;
361
362typedef struct asc_sg_head {
27c868c2
MW		 363 ushort entry_cnt;
364 ushort queue_cnt;
365 ushort entry_to_copy;
366 ushort res;
05848b6e 367 ASC_SG_LIST sg_list[0];
1da177e4
LT		 368} ASC_SG_HEAD;
369
1da177e4 370typedef struct asc_scsi_q {
27c868c2
MW		 371 ASC_SCSIQ_1 q1;
372 ASC_SCSIQ_2 q2;
373 uchar *cdbptr;
374 ASC_SG_HEAD *sg_head;
375 ushort remain_sg_entry_cnt;
376 ushort next_sg_index;
1da177e4
LT		 377} ASC_SCSI_Q;
378
379typedef struct asc_scsi_req_q {
27c868c2
MW		 380 ASC_SCSIQ_1 r1;
381 ASC_SCSIQ_2 r2;
382 uchar *cdbptr;
383 ASC_SG_HEAD *sg_head;
384 uchar *sense_ptr;
385 ASC_SCSIQ_3 r3;
386 uchar cdb[ASC_MAX_CDB_LEN];
387 uchar sense[ASC_MIN_SENSE_LEN];
1da177e4
LT		 388} ASC_SCSI_REQ_Q;
389
390typedef struct asc_scsi_bios_req_q {
27c868c2
MW		 391 ASC_SCSIQ_1 r1;
392 ASC_SCSIQ_2 r2;
393 uchar *cdbptr;
394 ASC_SG_HEAD *sg_head;
395 uchar *sense_ptr;
396 ASC_SCSIQ_3 r3;
397 uchar cdb[ASC_MAX_CDB_LEN];
398 uchar sense[ASC_MIN_SENSE_LEN];
1da177e4
LT		 399} ASC_SCSI_BIOS_REQ_Q;
400
401typedef struct asc_risc_q {
27c868c2
MW		 402 uchar fwd;
403 uchar bwd;
404 ASC_SCSIQ_1 i1;
405 ASC_SCSIQ_2 i2;
406 ASC_SCSIQ_3 i3;
407 ASC_SCSIQ_4 i4;
1da177e4
LT		 408} ASC_RISC_Q;
409
410typedef struct asc_sg_list_q {
27c868c2
MW		 411 uchar seq_no;
412 uchar q_no;
413 uchar cntl;
414 uchar sg_head_qp;
415 uchar sg_list_cnt;
416 uchar sg_cur_list_cnt;
1da177e4
LT		 417} ASC_SG_LIST_Q;
418
419typedef struct asc_risc_sg_list_q {
27c868c2
MW		 420 uchar fwd;
421 uchar bwd;
422 ASC_SG_LIST_Q sg;
423 ASC_SG_LIST sg_list[7];
1da177e4
LT		 424} ASC_RISC_SG_LIST_Q;
425
1da177e4 426#define ASCQ_ERR_Q_STATUS 0x0D
1da177e4
LT		 427#define ASCQ_ERR_CUR_QNG 0x17
428#define ASCQ_ERR_SG_Q_LINKS 0x18
1da177e4
LT		 429#define ASCQ_ERR_ISR_RE_ENTRY 0x1A
430#define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
431#define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
1da177e4
LT		 432
433/*
434 * Warning code values are set in ASC_DVC_VAR 'warn_code'.
435 */
436#define ASC_WARN_NO_ERROR 0x0000
437#define ASC_WARN_IO_PORT_ROTATE 0x0001
438#define ASC_WARN_EEPROM_CHKSUM 0x0002
439#define ASC_WARN_IRQ_MODIFIED 0x0004
440#define ASC_WARN_AUTO_CONFIG 0x0008
441#define ASC_WARN_CMD_QNG_CONFLICT 0x0010
442#define ASC_WARN_EEPROM_RECOVER 0x0020
443#define ASC_WARN_CFG_MSW_RECOVER 0x0040
1da177e4
LT		 444
445/*
720349a8 446 * Error code values are set in {ASC/ADV}_DVC_VAR 'err_code'.
1da177e4 447 */
720349a8
MW		 448#define ASC_IERR_NO_CARRIER 0x0001 /* No more carrier memory */
449#define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
450#define ASC_IERR_SET_PC_ADDR 0x0004
451#define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
452#define ASC_IERR_ILLEGAL_CONNECTION 0x0010 /* Illegal cable connection */
453#define ASC_IERR_SINGLE_END_DEVICE 0x0020 /* SE device on DIFF bus */
454#define ASC_IERR_REVERSED_CABLE 0x0040 /* Narrow flat cable reversed */
455#define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
456#define ASC_IERR_HVD_DEVICE 0x0100 /* HVD device on LVD port */
457#define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
458#define ASC_IERR_NO_BUS_TYPE 0x0400
459#define ASC_IERR_BIST_PRE_TEST 0x0800 /* BIST pre-test error */
460#define ASC_IERR_BIST_RAM_TEST 0x1000 /* BIST RAM test error */
461#define ASC_IERR_BAD_CHIPTYPE 0x2000 /* Invalid chip_type setting */
1da177e4 462
1da177e4
LT		 463#define ASC_DEF_MAX_TOTAL_QNG (0xF0)
464#define ASC_MIN_TAG_Q_PER_DVC (0x04)
95c9f162 465#define ASC_MIN_FREE_Q (0x02)
1da177e4
LT		 466#define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
467#define ASC_MAX_TOTAL_QNG 240
468#define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
469#define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
470#define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
471#define ASC_MAX_INRAM_TAG_QNG 16
1da177e4 472#define ASC_IOADR_GAP 0x10
1da177e4
LT		 473#define ASC_SYN_MAX_OFFSET 0x0F
474#define ASC_DEF_SDTR_OFFSET 0x0F
1da177e4 475#define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
afbb68c3
MW		 476#define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
477
478/* The narrow chip only supports a limited selection of transfer rates.
479 * These are encoded in the range 0..7 or 0..15 depending whether the chip
480 * is Ultra-capable or not. These tables let us convert from one to the other.
481 */
482static const unsigned char asc_syn_xfer_period[8] = {
483 25, 30, 35, 40, 50, 60, 70, 85
484};
485
486static const unsigned char asc_syn_ultra_xfer_period[16] = {
487 12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107
488};
1da177e4
LT		 489
490typedef struct ext_msg {
27c868c2
MW		 491 uchar msg_type;
492 uchar msg_len;
493 uchar msg_req;
494 union {
495 struct {
496 uchar sdtr_xfer_period;
497 uchar sdtr_req_ack_offset;
498 } sdtr;
499 struct {
500 uchar wdtr_width;
501 } wdtr;
502 struct {
503 uchar mdp_b3;
504 uchar mdp_b2;
505 uchar mdp_b1;
506 uchar mdp_b0;
507 } mdp;
508 } u_ext_msg;
509 uchar res;
1da177e4
LT		 510} EXT_MSG;
511
512#define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
513#define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
514#define wdtr_width u_ext_msg.wdtr.wdtr_width
515#define mdp_b3 u_ext_msg.mdp_b3
516#define mdp_b2 u_ext_msg.mdp_b2
517#define mdp_b1 u_ext_msg.mdp_b1
518#define mdp_b0 u_ext_msg.mdp_b0
519
520typedef struct asc_dvc_cfg {
27c868c2
MW		 521 ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
522 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
523 ASC_SCSI_BIT_ID_TYPE disc_enable;
524 ASC_SCSI_BIT_ID_TYPE sdtr_enable;
525 uchar chip_scsi_id;
526 uchar isa_dma_speed;
527 uchar isa_dma_channel;
528 uchar chip_version;
27c868c2
MW		 529 ushort mcode_date;
530 ushort mcode_version;
531 uchar max_tag_qng[ASC_MAX_TID + 1];
27c868c2 532 uchar sdtr_period_offset[ASC_MAX_TID + 1];
27c868c2 533 uchar adapter_info[6];
1da177e4
LT		 534} ASC_DVC_CFG;
535
536#define ASC_DEF_DVC_CNTL 0xFFFF
537#define ASC_DEF_CHIP_SCSI_ID 7
538#define ASC_DEF_ISA_DMA_SPEED 4
1da177e4
LT		 539#define ASC_INIT_STATE_BEG_GET_CFG 0x0001
540#define ASC_INIT_STATE_END_GET_CFG 0x0002
541#define ASC_INIT_STATE_BEG_SET_CFG 0x0004
542#define ASC_INIT_STATE_END_SET_CFG 0x0008
543#define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
544#define ASC_INIT_STATE_END_LOAD_MC 0x0020
545#define ASC_INIT_STATE_BEG_INQUIRY 0x0040
546#define ASC_INIT_STATE_END_INQUIRY 0x0080
547#define ASC_INIT_RESET_SCSI_DONE 0x0100
548#define ASC_INIT_STATE_WITHOUT_EEP 0x8000
1da177e4
LT		 549#define ASC_BUG_FIX_IF_NOT_DWB 0x0001
550#define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
1da177e4
LT		 551#define ASC_MIN_TAGGED_CMD 7
552#define ASC_MAX_SCSI_RESET_WAIT 30
d10fb2c7 553#define ASC_OVERRUN_BSIZE 64
1da177e4 554
27c868c2 555struct asc_dvc_var; /* Forward Declaration. */
1da177e4 556
1da177e4 557typedef struct asc_dvc_var {
27c868c2
MW		 558 PortAddr iop_base;
559 ushort err_code;
560 ushort dvc_cntl;
561 ushort bug_fix_cntl;
562 ushort bus_type;
27c868c2
MW		 563 ASC_SCSI_BIT_ID_TYPE init_sdtr;
564 ASC_SCSI_BIT_ID_TYPE sdtr_done;
565 ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
566 ASC_SCSI_BIT_ID_TYPE unit_not_ready;
567 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
568 ASC_SCSI_BIT_ID_TYPE start_motor;
7d5d408c 569 uchar *overrun_buf;
d10fb2c7 570 dma_addr_t overrun_dma;
27c868c2
MW		 571 uchar scsi_reset_wait;
572 uchar chip_no;
573 char is_in_int;
574 uchar max_total_qng;
575 uchar cur_total_qng;
576 uchar in_critical_cnt;
27c868c2
MW		 577 uchar last_q_shortage;
578 ushort init_state;
579 uchar cur_dvc_qng[ASC_MAX_TID + 1];
580 uchar max_dvc_qng[ASC_MAX_TID + 1];
581 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
582 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
afbb68c3 583 const uchar *sdtr_period_tbl;
27c868c2
MW		 584 ASC_DVC_CFG *cfg;
585 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
586 char redo_scam;
587 ushort res2;
588 uchar dos_int13_table[ASC_MAX_TID + 1];
589 ASC_DCNT max_dma_count;
590 ASC_SCSI_BIT_ID_TYPE no_scam;
591 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
afbb68c3 592 uchar min_sdtr_index;
27c868c2 593 uchar max_sdtr_index;
27c868c2
MW		 594 struct asc_board *drv_ptr;
595 ASC_DCNT uc_break;
1da177e4
LT		 596} ASC_DVC_VAR;
597
598typedef struct asc_dvc_inq_info {
27c868c2 599 uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
1da177e4
LT		 600} ASC_DVC_INQ_INFO;
601
602typedef struct asc_cap_info {
27c868c2
MW		 603 ASC_DCNT lba;
604 ASC_DCNT blk_size;
1da177e4
LT		 605} ASC_CAP_INFO;
606
607typedef struct asc_cap_info_array {
27c868c2 608 ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
1da177e4
LT		 609} ASC_CAP_INFO_ARRAY;
610
611#define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
612#define ASC_MCNTL_NULL_TARGET (ushort)0x0002
613#define ASC_CNTL_INITIATOR (ushort)0x0001
614#define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
615#define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
616#define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
617#define ASC_CNTL_NO_SCAM (ushort)0x0010
618#define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
619#define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
620#define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
621#define ASC_CNTL_RESET_SCSI (ushort)0x0200
622#define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
623#define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
624#define ASC_CNTL_SCSI_PARITY (ushort)0x1000
625#define ASC_CNTL_BURST_MODE (ushort)0x2000
626#define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
627#define ASC_EEP_DVC_CFG_BEG_VL 2
628#define ASC_EEP_MAX_DVC_ADDR_VL 15
629#define ASC_EEP_DVC_CFG_BEG 32
630#define ASC_EEP_MAX_DVC_ADDR 45
1da177e4 631#define ASC_EEP_MAX_RETRY 20
1da177e4
LT		 632
633/*
634 * These macros keep the chip SCSI id and ISA DMA speed
635 * bitfields in board order. C bitfields aren't portable
636 * between big and little-endian platforms so they are
637 * not used.
638 */
639
640#define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
641#define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
642#define ASC_EEP_SET_CHIP_ID(cfg, sid) \
643 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
644#define ASC_EEP_SET_DMA_SPD(cfg, spd) \
645 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
646
647typedef struct asceep_config {
27c868c2
MW		 648 ushort cfg_lsw;
649 ushort cfg_msw;
650 uchar init_sdtr;
651 uchar disc_enable;
652 uchar use_cmd_qng;
653 uchar start_motor;
654 uchar max_total_qng;
655 uchar max_tag_qng;
656 uchar bios_scan;
657 uchar power_up_wait;
658 uchar no_scam;
659 uchar id_speed; /* low order 4 bits is chip scsi id */
660 /* high order 4 bits is isa dma speed */
661 uchar dos_int13_table[ASC_MAX_TID + 1];
662 uchar adapter_info[6];
663 ushort cntl;
664 ushort chksum;
1da177e4
LT		 665} ASCEEP_CONFIG;
666
1da177e4
LT		 667#define ASC_EEP_CMD_READ 0x80
668#define ASC_EEP_CMD_WRITE 0x40
669#define ASC_EEP_CMD_WRITE_ABLE 0x30
670#define ASC_EEP_CMD_WRITE_DISABLE 0x00
1da177e4
LT		 671#define ASCV_MSGOUT_BEG 0x0000
672#define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
673#define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
674#define ASCV_BREAK_SAVED_CODE (ushort)0x0006
675#define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
676#define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
677#define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
678#define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
679#define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
680#define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
681#define ASCV_BREAK_ADDR (ushort)0x0028
682#define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
683#define ASCV_BREAK_CONTROL (ushort)0x002C
684#define ASCV_BREAK_HIT_COUNT (ushort)0x002E
685
686#define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
687#define ASCV_MCODE_CHKSUM_W (ushort)0x0032
688#define ASCV_MCODE_SIZE_W (ushort)0x0034
689#define ASCV_STOP_CODE_B (ushort)0x0036
690#define ASCV_DVC_ERR_CODE_B (ushort)0x0037
691#define ASCV_OVERRUN_PADDR_D (ushort)0x0038
692#define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
693#define ASCV_HALTCODE_W (ushort)0x0040
694#define ASCV_CHKSUM_W (ushort)0x0042
695#define ASCV_MC_DATE_W (ushort)0x0044
696#define ASCV_MC_VER_W (ushort)0x0046
697#define ASCV_NEXTRDY_B (ushort)0x0048
698#define ASCV_DONENEXT_B (ushort)0x0049
699#define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
700#define ASCV_SCSIBUSY_B (ushort)0x004B
701#define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
702#define ASCV_CURCDB_B (ushort)0x004D
703#define ASCV_RCLUN_B (ushort)0x004E
704#define ASCV_BUSY_QHEAD_B (ushort)0x004F
705#define ASCV_DISC1_QHEAD_B (ushort)0x0050
706#define ASCV_DISC_ENABLE_B (ushort)0x0052
707#define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
708#define ASCV_HOSTSCSI_ID_B (ushort)0x0055
709#define ASCV_MCODE_CNTL_B (ushort)0x0056
710#define ASCV_NULL_TARGET_B (ushort)0x0057
711#define ASCV_FREE_Q_HEAD_W (ushort)0x0058
712#define ASCV_DONE_Q_TAIL_W (ushort)0x005A
713#define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
714#define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
715#define ASCV_HOST_FLAG_B (ushort)0x005D
716#define ASCV_TOTAL_READY_Q_B (ushort)0x0064
717#define ASCV_VER_SERIAL_B (ushort)0x0065
718#define ASCV_HALTCODE_SAVED_W (ushort)0x0066
719#define ASCV_WTM_FLAG_B (ushort)0x0068
720#define ASCV_RISC_FLAG_B (ushort)0x006A
721#define ASCV_REQ_SG_LIST_QP (ushort)0x006B
722#define ASC_HOST_FLAG_IN_ISR 0x01
723#define ASC_HOST_FLAG_ACK_INT 0x02
724#define ASC_RISC_FLAG_GEN_INT 0x01
725#define ASC_RISC_FLAG_REQ_SG_LIST 0x02
726#define IOP_CTRL (0x0F)
727#define IOP_STATUS (0x0E)
728#define IOP_INT_ACK IOP_STATUS
729#define IOP_REG_IFC (0x0D)
730#define IOP_SYN_OFFSET (0x0B)
731#define IOP_EXTRA_CONTROL (0x0D)
732#define IOP_REG_PC (0x0C)
733#define IOP_RAM_ADDR (0x0A)
734#define IOP_RAM_DATA (0x08)
735#define IOP_EEP_DATA (0x06)
736#define IOP_EEP_CMD (0x07)
737#define IOP_VERSION (0x03)
738#define IOP_CONFIG_HIGH (0x04)
739#define IOP_CONFIG_LOW (0x02)
740#define IOP_SIG_BYTE (0x01)
741#define IOP_SIG_WORD (0x00)
742#define IOP_REG_DC1 (0x0E)
743#define IOP_REG_DC0 (0x0C)
744#define IOP_REG_SB (0x0B)
745#define IOP_REG_DA1 (0x0A)
746#define IOP_REG_DA0 (0x08)
747#define IOP_REG_SC (0x09)
748#define IOP_DMA_SPEED (0x07)
749#define IOP_REG_FLAG (0x07)
750#define IOP_FIFO_H (0x06)
751#define IOP_FIFO_L (0x04)
752#define IOP_REG_ID (0x05)
753#define IOP_REG_QP (0x03)
754#define IOP_REG_IH (0x02)
755#define IOP_REG_IX (0x01)
756#define IOP_REG_AX (0x00)
757#define IFC_REG_LOCK (0x00)
758#define IFC_REG_UNLOCK (0x09)
759#define IFC_WR_EN_FILTER (0x10)
760#define IFC_RD_NO_EEPROM (0x10)
761#define IFC_SLEW_RATE (0x20)
762#define IFC_ACT_NEG (0x40)
763#define IFC_INP_FILTER (0x80)
764#define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
765#define SC_SEL (uchar)(0x80)
766#define SC_BSY (uchar)(0x40)
767#define SC_ACK (uchar)(0x20)
768#define SC_REQ (uchar)(0x10)
769#define SC_ATN (uchar)(0x08)
770#define SC_IO (uchar)(0x04)
771#define SC_CD (uchar)(0x02)
772#define SC_MSG (uchar)(0x01)
773#define SEC_SCSI_CTL (uchar)(0x80)
774#define SEC_ACTIVE_NEGATE (uchar)(0x40)
775#define SEC_SLEW_RATE (uchar)(0x20)
776#define SEC_ENABLE_FILTER (uchar)(0x10)
777#define ASC_HALT_EXTMSG_IN (ushort)0x8000
778#define ASC_HALT_CHK_CONDITION (ushort)0x8100
779#define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
780#define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
781#define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
782#define ASC_HALT_SDTR_REJECTED (ushort)0x4000
783#define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
784#define ASC_MAX_QNO 0xF8
785#define ASC_DATA_SEC_BEG (ushort)0x0080
786#define ASC_DATA_SEC_END (ushort)0x0080
787#define ASC_CODE_SEC_BEG (ushort)0x0080
788#define ASC_CODE_SEC_END (ushort)0x0080
789#define ASC_QADR_BEG (0x4000)
790#define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
791#define ASC_QADR_END (ushort)0x7FFF
792#define ASC_QLAST_ADR (ushort)0x7FC0
793#define ASC_QBLK_SIZE 0x40
794#define ASC_BIOS_DATA_QBEG 0xF8
795#define ASC_MIN_ACTIVE_QNO 0x01
796#define ASC_QLINK_END 0xFF
797#define ASC_EEPROM_WORDS 0x10
798#define ASC_MAX_MGS_LEN 0x10
799#define ASC_BIOS_ADDR_DEF 0xDC00
800#define ASC_BIOS_SIZE 0x3800
801#define ASC_BIOS_RAM_OFF 0x3800
802#define ASC_BIOS_RAM_SIZE 0x800
803#define ASC_BIOS_MIN_ADDR 0xC000
804#define ASC_BIOS_MAX_ADDR 0xEC00
805#define ASC_BIOS_BANK_SIZE 0x0400
806#define ASC_MCODE_START_ADDR 0x0080
807#define ASC_CFG0_HOST_INT_ON 0x0020
808#define ASC_CFG0_BIOS_ON 0x0040
809#define ASC_CFG0_VERA_BURST_ON 0x0080
810#define ASC_CFG0_SCSI_PARITY_ON 0x0800
811#define ASC_CFG1_SCSI_TARGET_ON 0x0080
812#define ASC_CFG1_LRAM_8BITS_ON 0x0800
813#define ASC_CFG_MSW_CLR_MASK 0x3080
814#define CSW_TEST1 (ASC_CS_TYPE)0x8000
815#define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
816#define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
817#define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
818#define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
819#define CSW_TEST2 (ASC_CS_TYPE)0x0400
820#define CSW_TEST3 (ASC_CS_TYPE)0x0200
821#define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
822#define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
823#define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
824#define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
825#define CSW_HALTED (ASC_CS_TYPE)0x0010
826#define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
827#define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
828#define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
829#define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
830#define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
831#define CIW_INT_ACK (ASC_CS_TYPE)0x0100
832#define CIW_TEST1 (ASC_CS_TYPE)0x0200
833#define CIW_TEST2 (ASC_CS_TYPE)0x0400
834#define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
835#define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
836#define CC_CHIP_RESET (uchar)0x80
837#define CC_SCSI_RESET (uchar)0x40
838#define CC_HALT (uchar)0x20
839#define CC_SINGLE_STEP (uchar)0x10
840#define CC_DMA_ABLE (uchar)0x08
841#define CC_TEST (uchar)0x04
842#define CC_BANK_ONE (uchar)0x02
843#define CC_DIAG (uchar)0x01
844#define ASC_1000_ID0W 0x04C1
845#define ASC_1000_ID0W_FIX 0x00C1
846#define ASC_1000_ID1B 0x25
1da177e4 847#define ASC_EISA_REV_IOP_MASK (0x0C83)
1da177e4
LT		 848#define ASC_EISA_CFG_IOP_MASK (0x0C86)
849#define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
1da177e4
LT		 850#define INS_HALTINT (ushort)0x6281
851#define INS_HALT (ushort)0x6280
852#define INS_SINT (ushort)0x6200
853#define INS_RFLAG_WTM (ushort)0x7380
854#define ASC_MC_SAVE_CODE_WSIZE 0x500
855#define ASC_MC_SAVE_DATA_WSIZE 0x40
856
857typedef struct asc_mc_saved {
27c868c2
MW		 858 ushort data[ASC_MC_SAVE_DATA_WSIZE];
859 ushort code[ASC_MC_SAVE_CODE_WSIZE];
1da177e4
LT		 860} ASC_MC_SAVED;
861
862#define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
863#define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
864#define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
865#define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
866#define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
867#define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
868#define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
869#define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
870#define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
871#define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
51219358
MW		 872#define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
873#define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
874#define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
875#define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
1da177e4
LT		 876#define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
877#define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
878#define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
879#define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
880#define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
881#define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
882#define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
883#define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
884#define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
885#define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
886#define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
887#define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
888#define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
889#define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
890#define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
891#define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
892#define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
893#define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
894#define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
895#define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
896#define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
897#define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
898#define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
899#define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
900#define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
901#define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
902#define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
903#define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
904#define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
905#define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
906#define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
907#define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
908#define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
909#define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
910#define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
911#define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
912#define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
913#define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
914#define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
915#define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
916#define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
917#define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
918#define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
919#define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
920#define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
921#define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
922#define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
923#define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
924#define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
925#define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
926#define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
927#define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
928#define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
929
1da177e4
LT		 930/*
931 * Portable Data Types
932 *
933 * Any instance where a 32-bit long or pointer type is assumed
934 * for precision or HW defined structures, the following define
935 * types must be used. In Linux the char, short, and int types
936 * are all consistent at 8, 16, and 32 bits respectively. Pointers
937 * and long types are 64 bits on Alpha and UltraSPARC.
938 */
27c868c2
MW		 939#define ADV_PADDR __u32 /* Physical address data type. */
940#define ADV_VADDR __u32 /* Virtual address data type. */
941#define ADV_DCNT __u32 /* Unsigned Data count type. */
942#define ADV_SDCNT __s32 /* Signed Data count type. */
1da177e4
LT		 943
944/*
945 * These macros are used to convert a virtual address to a
946 * 32-bit value. This currently can be used on Linux Alpha
947 * which uses 64-bit virtual address but a 32-bit bus address.
948 * This is likely to break in the future, but doing this now
949 * will give us time to change the HW and FW to handle 64-bit
950 * addresses.
951 */
952#define ADV_VADDR_TO_U32 virt_to_bus
953#define ADV_U32_TO_VADDR bus_to_virt
954
27c868c2 955#define AdvPortAddr void __iomem * /* Virtual memory address size */
1da177e4
LT		 956
957/*
958 * Define Adv Library required memory access macros.
959 */
960#define ADV_MEM_READB(addr) readb(addr)
961#define ADV_MEM_READW(addr) readw(addr)
962#define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
963#define ADV_MEM_WRITEW(addr, word) writew(word, addr)
964#define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
965
966#define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 15)
967
1da177e4
LT		 968/*
969 * Define total number of simultaneous maximum element scatter-gather
970 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
971 * maximum number of outstanding commands per wide host adapter. Each
972 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
973 * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
974 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
975 * structures or 255 scatter-gather elements.
1da177e4
LT		 976 */
977#define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
978
979/*
98d41c29 980 * Define maximum number of scatter-gather elements per request.
1da177e4
LT		 981 */
982#define ADV_MAX_SG_LIST 255
98d41c29 983#define NO_OF_SG_PER_BLOCK 15
1da177e4 984
1da177e4
LT		 985#define ADV_EEP_DVC_CFG_BEGIN (0x00)
986#define ADV_EEP_DVC_CFG_END (0x15)
27c868c2 987#define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
1da177e4
LT		 988#define ADV_EEP_MAX_WORD_ADDR (0x1E)
989
990#define ADV_EEP_DELAY_MS 100
991
27c868c2
MW		 992#define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
993#define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
1da177e4
LT		 994/*
995 * For the ASC3550 Bit 13 is Termination Polarity control bit.
996 * For later ICs Bit 13 controls whether the CIS (Card Information
997 * Service Section) is loaded from EEPROM.
998 */
27c868c2
MW		 999#define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
1000#define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
1da177e4
LT		 1001/*
1002 * ASC38C1600 Bit 11
1003 *
1004 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
1005 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
1006 * Function 0 will specify INT B.
1007 *
1008 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
1009 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
1010 * Function 1 will specify INT A.
1011 */
27c868c2
MW		 1012#define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
1013
1014typedef struct adveep_3550_config {
1015 /* Word Offset, Description */
1016
1017 ushort cfg_lsw; /* 00 power up initialization */
1018 /* bit 13 set - Term Polarity Control */
1019 /* bit 14 set - BIOS Enable */
1020 /* bit 15 set - Big Endian Mode */
1021 ushort cfg_msw; /* 01 unused */
1022 ushort disc_enable; /* 02 disconnect enable */
1023 ushort wdtr_able; /* 03 Wide DTR able */
1024 ushort sdtr_able; /* 04 Synchronous DTR able */
1025 ushort start_motor; /* 05 send start up motor */
1026 ushort tagqng_able; /* 06 tag queuing able */
1027 ushort bios_scan; /* 07 BIOS device control */
1028 ushort scam_tolerant; /* 08 no scam */
1029
1030 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1031 uchar bios_boot_delay; /* power up wait */
1032
1033 uchar scsi_reset_delay; /* 10 reset delay */
1034 uchar bios_id_lun; /* first boot device scsi id & lun */
1035 /* high nibble is lun */
1036 /* low nibble is scsi id */
1037
1038 uchar termination; /* 11 0 - automatic */
1039 /* 1 - low off / high off */
1040 /* 2 - low off / high on */
1041 /* 3 - low on / high on */
1042 /* There is no low on / high off */
1043
1044 uchar reserved1; /* reserved byte (not used) */
1045
1046 ushort bios_ctrl; /* 12 BIOS control bits */
1047 /* bit 0 BIOS don't act as initiator. */
1048 /* bit 1 BIOS > 1 GB support */
1049 /* bit 2 BIOS > 2 Disk Support */
1050 /* bit 3 BIOS don't support removables */
1051 /* bit 4 BIOS support bootable CD */
1052 /* bit 5 BIOS scan enabled */
1053 /* bit 6 BIOS support multiple LUNs */
1054 /* bit 7 BIOS display of message */
1055 /* bit 8 SCAM disabled */
1056 /* bit 9 Reset SCSI bus during init. */
1057 /* bit 10 */
1058 /* bit 11 No verbose initialization. */
1059 /* bit 12 SCSI parity enabled */
1060 /* bit 13 */
1061 /* bit 14 */
1062 /* bit 15 */
1063 ushort ultra_able; /* 13 ULTRA speed able */
1064 ushort reserved2; /* 14 reserved */
1065 uchar max_host_qng; /* 15 maximum host queuing */
1066 uchar max_dvc_qng; /* maximum per device queuing */
1067 ushort dvc_cntl; /* 16 control bit for driver */
1068 ushort bug_fix; /* 17 control bit for bug fix */
1069 ushort serial_number_word1; /* 18 Board serial number word 1 */
1070 ushort serial_number_word2; /* 19 Board serial number word 2 */
1071 ushort serial_number_word3; /* 20 Board serial number word 3 */
1072 ushort check_sum; /* 21 EEP check sum */
1073 uchar oem_name[16]; /* 22 OEM name */
1074 ushort dvc_err_code; /* 30 last device driver error code */
1075 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1076 ushort adv_err_addr; /* 32 last uc error address */
1077 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1078 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1079 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1080 ushort num_of_err; /* 36 number of error */
1da177e4
LT		 1081} ADVEEP_3550_CONFIG;
1082
27c868c2
MW		 1083typedef struct adveep_38C0800_config {
1084 /* Word Offset, Description */
1085
1086 ushort cfg_lsw; /* 00 power up initialization */
1087 /* bit 13 set - Load CIS */
1088 /* bit 14 set - BIOS Enable */
1089 /* bit 15 set - Big Endian Mode */
1090 ushort cfg_msw; /* 01 unused */
1091 ushort disc_enable; /* 02 disconnect enable */
1092 ushort wdtr_able; /* 03 Wide DTR able */
1093 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1094 ushort start_motor; /* 05 send start up motor */
1095 ushort tagqng_able; /* 06 tag queuing able */
1096 ushort bios_scan; /* 07 BIOS device control */
1097 ushort scam_tolerant; /* 08 no scam */
1098
1099 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1100 uchar bios_boot_delay; /* power up wait */
1101
1102 uchar scsi_reset_delay; /* 10 reset delay */
1103 uchar bios_id_lun; /* first boot device scsi id & lun */
1104 /* high nibble is lun */
1105 /* low nibble is scsi id */
1106
1107 uchar termination_se; /* 11 0 - automatic */
1108 /* 1 - low off / high off */
1109 /* 2 - low off / high on */
1110 /* 3 - low on / high on */
1111 /* There is no low on / high off */
1112
1113 uchar termination_lvd; /* 11 0 - automatic */
1114 /* 1 - low off / high off */
1115 /* 2 - low off / high on */
1116 /* 3 - low on / high on */
1117 /* There is no low on / high off */
1118
1119 ushort bios_ctrl; /* 12 BIOS control bits */
1120 /* bit 0 BIOS don't act as initiator. */
1121 /* bit 1 BIOS > 1 GB support */
1122 /* bit 2 BIOS > 2 Disk Support */
1123 /* bit 3 BIOS don't support removables */
1124 /* bit 4 BIOS support bootable CD */
1125 /* bit 5 BIOS scan enabled */
1126 /* bit 6 BIOS support multiple LUNs */
1127 /* bit 7 BIOS display of message */
1128 /* bit 8 SCAM disabled */
1129 /* bit 9 Reset SCSI bus during init. */
1130 /* bit 10 */
1131 /* bit 11 No verbose initialization. */
1132 /* bit 12 SCSI parity enabled */
1133 /* bit 13 */
1134 /* bit 14 */
1135 /* bit 15 */
1136 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1137 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1138 uchar max_host_qng; /* 15 maximum host queueing */
1139 uchar max_dvc_qng; /* maximum per device queuing */
1140 ushort dvc_cntl; /* 16 control bit for driver */
1141 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1142 ushort serial_number_word1; /* 18 Board serial number word 1 */
1143 ushort serial_number_word2; /* 19 Board serial number word 2 */
1144 ushort serial_number_word3; /* 20 Board serial number word 3 */
1145 ushort check_sum; /* 21 EEP check sum */
1146 uchar oem_name[16]; /* 22 OEM name */
1147 ushort dvc_err_code; /* 30 last device driver error code */
1148 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1149 ushort adv_err_addr; /* 32 last uc error address */
1150 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1151 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1152 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1153 ushort reserved36; /* 36 reserved */
1154 ushort reserved37; /* 37 reserved */
1155 ushort reserved38; /* 38 reserved */
1156 ushort reserved39; /* 39 reserved */
1157 ushort reserved40; /* 40 reserved */
1158 ushort reserved41; /* 41 reserved */
1159 ushort reserved42; /* 42 reserved */
1160 ushort reserved43; /* 43 reserved */
1161 ushort reserved44; /* 44 reserved */
1162 ushort reserved45; /* 45 reserved */
1163 ushort reserved46; /* 46 reserved */
1164 ushort reserved47; /* 47 reserved */
1165 ushort reserved48; /* 48 reserved */
1166 ushort reserved49; /* 49 reserved */
1167 ushort reserved50; /* 50 reserved */
1168 ushort reserved51; /* 51 reserved */
1169 ushort reserved52; /* 52 reserved */
1170 ushort reserved53; /* 53 reserved */
1171 ushort reserved54; /* 54 reserved */
1172 ushort reserved55; /* 55 reserved */
1173 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1174 ushort cisprt_msw; /* 57 CIS PTR MSW */
1175 ushort subsysvid; /* 58 SubSystem Vendor ID */
1176 ushort subsysid; /* 59 SubSystem ID */
1177 ushort reserved60; /* 60 reserved */
1178 ushort reserved61; /* 61 reserved */
1179 ushort reserved62; /* 62 reserved */
1180 ushort reserved63; /* 63 reserved */
1da177e4
LT		 1181} ADVEEP_38C0800_CONFIG;
1182
27c868c2
MW		 1183typedef struct adveep_38C1600_config {
1184 /* Word Offset, Description */
1185
1186 ushort cfg_lsw; /* 00 power up initialization */
1187 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */
1188 /* clear - Func. 0 INTA, Func. 1 INTB */
1189 /* bit 13 set - Load CIS */
1190 /* bit 14 set - BIOS Enable */
1191 /* bit 15 set - Big Endian Mode */
1192 ushort cfg_msw; /* 01 unused */
1193 ushort disc_enable; /* 02 disconnect enable */
1194 ushort wdtr_able; /* 03 Wide DTR able */
1195 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1196 ushort start_motor; /* 05 send start up motor */
1197 ushort tagqng_able; /* 06 tag queuing able */
1198 ushort bios_scan; /* 07 BIOS device control */
1199 ushort scam_tolerant; /* 08 no scam */
1200
1201 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1202 uchar bios_boot_delay; /* power up wait */
1203
1204 uchar scsi_reset_delay; /* 10 reset delay */
1205 uchar bios_id_lun; /* first boot device scsi id & lun */
1206 /* high nibble is lun */
1207 /* low nibble is scsi id */
1208
1209 uchar termination_se; /* 11 0 - automatic */
1210 /* 1 - low off / high off */
1211 /* 2 - low off / high on */
1212 /* 3 - low on / high on */
1213 /* There is no low on / high off */
1214
1215 uchar termination_lvd; /* 11 0 - automatic */
1216 /* 1 - low off / high off */
1217 /* 2 - low off / high on */
1218 /* 3 - low on / high on */
1219 /* There is no low on / high off */
1220
1221 ushort bios_ctrl; /* 12 BIOS control bits */
1222 /* bit 0 BIOS don't act as initiator. */
1223 /* bit 1 BIOS > 1 GB support */
1224 /* bit 2 BIOS > 2 Disk Support */
1225 /* bit 3 BIOS don't support removables */
1226 /* bit 4 BIOS support bootable CD */
1227 /* bit 5 BIOS scan enabled */
1228 /* bit 6 BIOS support multiple LUNs */
1229 /* bit 7 BIOS display of message */
1230 /* bit 8 SCAM disabled */
1231 /* bit 9 Reset SCSI bus during init. */
1232 /* bit 10 Basic Integrity Checking disabled */
1233 /* bit 11 No verbose initialization. */
1234 /* bit 12 SCSI parity enabled */
1235 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
1236 /* bit 14 */
1237 /* bit 15 */
1238 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1239 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1240 uchar max_host_qng; /* 15 maximum host queueing */
1241 uchar max_dvc_qng; /* maximum per device queuing */
1242 ushort dvc_cntl; /* 16 control bit for driver */
1243 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1244 ushort serial_number_word1; /* 18 Board serial number word 1 */
1245 ushort serial_number_word2; /* 19 Board serial number word 2 */
1246 ushort serial_number_word3; /* 20 Board serial number word 3 */
1247 ushort check_sum; /* 21 EEP check sum */
1248 uchar oem_name[16]; /* 22 OEM name */
1249 ushort dvc_err_code; /* 30 last device driver error code */
1250 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1251 ushort adv_err_addr; /* 32 last uc error address */
1252 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1253 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1254 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1255 ushort reserved36; /* 36 reserved */
1256 ushort reserved37; /* 37 reserved */
1257 ushort reserved38; /* 38 reserved */
1258 ushort reserved39; /* 39 reserved */
1259 ushort reserved40; /* 40 reserved */
1260 ushort reserved41; /* 41 reserved */
1261 ushort reserved42; /* 42 reserved */
1262 ushort reserved43; /* 43 reserved */
1263 ushort reserved44; /* 44 reserved */
1264 ushort reserved45; /* 45 reserved */
1265 ushort reserved46; /* 46 reserved */
1266 ushort reserved47; /* 47 reserved */
1267 ushort reserved48; /* 48 reserved */
1268 ushort reserved49; /* 49 reserved */
1269 ushort reserved50; /* 50 reserved */
1270 ushort reserved51; /* 51 reserved */
1271 ushort reserved52; /* 52 reserved */
1272 ushort reserved53; /* 53 reserved */
1273 ushort reserved54; /* 54 reserved */
1274 ushort reserved55; /* 55 reserved */
1275 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1276 ushort cisprt_msw; /* 57 CIS PTR MSW */
1277 ushort subsysvid; /* 58 SubSystem Vendor ID */
1278 ushort subsysid; /* 59 SubSystem ID */
1279 ushort reserved60; /* 60 reserved */
1280 ushort reserved61; /* 61 reserved */
1281 ushort reserved62; /* 62 reserved */
1282 ushort reserved63; /* 63 reserved */
1da177e4
LT		 1283} ADVEEP_38C1600_CONFIG;
1284
1285/*
1286 * EEPROM Commands
1287 */
1288#define ASC_EEP_CMD_DONE 0x0200
1da177e4
LT		 1289
1290/* bios_ctrl */
1291#define BIOS_CTRL_BIOS 0x0001
1292#define BIOS_CTRL_EXTENDED_XLAT 0x0002
1293#define BIOS_CTRL_GT_2_DISK 0x0004
1294#define BIOS_CTRL_BIOS_REMOVABLE 0x0008
1295#define BIOS_CTRL_BOOTABLE_CD 0x0010
1296#define BIOS_CTRL_MULTIPLE_LUN 0x0040
1297#define BIOS_CTRL_DISPLAY_MSG 0x0080
1298#define BIOS_CTRL_NO_SCAM 0x0100
1299#define BIOS_CTRL_RESET_SCSI_BUS 0x0200
1300#define BIOS_CTRL_INIT_VERBOSE 0x0800
1301#define BIOS_CTRL_SCSI_PARITY 0x1000
1302#define BIOS_CTRL_AIPP_DIS 0x2000
1303
27c868c2 1304#define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
1da177e4 1305
27c868c2 1306#define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1da177e4
LT		 1307
1308/*
1309 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
1310 * a special 16K Adv Library and Microcode version. After the issue is
1311 * resolved, should restore 32K support.
1312 *
1313 * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
1314 */
27c868c2 1315#define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1da177e4
LT		 1316
1317/*
1318 * Byte I/O register address from base of 'iop_base'.
1319 */
1320#define IOPB_INTR_STATUS_REG 0x00
1321#define IOPB_CHIP_ID_1 0x01
1322#define IOPB_INTR_ENABLES 0x02
1323#define IOPB_CHIP_TYPE_REV 0x03
1324#define IOPB_RES_ADDR_4 0x04
1325#define IOPB_RES_ADDR_5 0x05
1326#define IOPB_RAM_DATA 0x06
1327#define IOPB_RES_ADDR_7 0x07
1328#define IOPB_FLAG_REG 0x08
1329#define IOPB_RES_ADDR_9 0x09
1330#define IOPB_RISC_CSR 0x0A
1331#define IOPB_RES_ADDR_B 0x0B
1332#define IOPB_RES_ADDR_C 0x0C
1333#define IOPB_RES_ADDR_D 0x0D
1334#define IOPB_SOFT_OVER_WR 0x0E
1335#define IOPB_RES_ADDR_F 0x0F
1336#define IOPB_MEM_CFG 0x10
1337#define IOPB_RES_ADDR_11 0x11
1338#define IOPB_GPIO_DATA 0x12
1339#define IOPB_RES_ADDR_13 0x13
1340#define IOPB_FLASH_PAGE 0x14
1341#define IOPB_RES_ADDR_15 0x15
1342#define IOPB_GPIO_CNTL 0x16
1343#define IOPB_RES_ADDR_17 0x17
1344#define IOPB_FLASH_DATA 0x18
1345#define IOPB_RES_ADDR_19 0x19
1346#define IOPB_RES_ADDR_1A 0x1A
1347#define IOPB_RES_ADDR_1B 0x1B
1348#define IOPB_RES_ADDR_1C 0x1C
1349#define IOPB_RES_ADDR_1D 0x1D
1350#define IOPB_RES_ADDR_1E 0x1E
1351#define IOPB_RES_ADDR_1F 0x1F
1352#define IOPB_DMA_CFG0 0x20
1353#define IOPB_DMA_CFG1 0x21
1354#define IOPB_TICKLE 0x22
1355#define IOPB_DMA_REG_WR 0x23
1356#define IOPB_SDMA_STATUS 0x24
1357#define IOPB_SCSI_BYTE_CNT 0x25
1358#define IOPB_HOST_BYTE_CNT 0x26
1359#define IOPB_BYTE_LEFT_TO_XFER 0x27
1360#define IOPB_BYTE_TO_XFER_0 0x28
1361#define IOPB_BYTE_TO_XFER_1 0x29
1362#define IOPB_BYTE_TO_XFER_2 0x2A
1363#define IOPB_BYTE_TO_XFER_3 0x2B
1364#define IOPB_ACC_GRP 0x2C
1365#define IOPB_RES_ADDR_2D 0x2D
1366#define IOPB_DEV_ID 0x2E
1367#define IOPB_RES_ADDR_2F 0x2F
1368#define IOPB_SCSI_DATA 0x30
1369#define IOPB_RES_ADDR_31 0x31
1370#define IOPB_RES_ADDR_32 0x32
1371#define IOPB_SCSI_DATA_HSHK 0x33
1372#define IOPB_SCSI_CTRL 0x34
1373#define IOPB_RES_ADDR_35 0x35
1374#define IOPB_RES_ADDR_36 0x36
1375#define IOPB_RES_ADDR_37 0x37
1376#define IOPB_RAM_BIST 0x38
1377#define IOPB_PLL_TEST 0x39
1378#define IOPB_PCI_INT_CFG 0x3A
1379#define IOPB_RES_ADDR_3B 0x3B
1380#define IOPB_RFIFO_CNT 0x3C
1381#define IOPB_RES_ADDR_3D 0x3D
1382#define IOPB_RES_ADDR_3E 0x3E
1383#define IOPB_RES_ADDR_3F 0x3F
1384
1385/*
1386 * Word I/O register address from base of 'iop_base'.
1387 */
27c868c2
MW		 1388#define IOPW_CHIP_ID_0 0x00 /* CID0 */
1389#define IOPW_CTRL_REG 0x02 /* CC */
1390#define IOPW_RAM_ADDR 0x04 /* LA */
1391#define IOPW_RAM_DATA 0x06 /* LD */
1da177e4 1392#define IOPW_RES_ADDR_08 0x08
27c868c2
MW		 1393#define IOPW_RISC_CSR 0x0A /* CSR */
1394#define IOPW_SCSI_CFG0 0x0C /* CFG0 */
1395#define IOPW_SCSI_CFG1 0x0E /* CFG1 */
1da177e4 1396#define IOPW_RES_ADDR_10 0x10
27c868c2 1397#define IOPW_SEL_MASK 0x12 /* SM */
1da177e4 1398#define IOPW_RES_ADDR_14 0x14
27c868c2 1399#define IOPW_FLASH_ADDR 0x16 /* FA */
1da177e4 1400#define IOPW_RES_ADDR_18 0x18
27c868c2
MW		 1401#define IOPW_EE_CMD 0x1A /* EC */
1402#define IOPW_EE_DATA 0x1C /* ED */
1403#define IOPW_SFIFO_CNT 0x1E /* SFC */
1da177e4 1404#define IOPW_RES_ADDR_20 0x20
27c868c2
MW		 1405#define IOPW_Q_BASE 0x22 /* QB */
1406#define IOPW_QP 0x24 /* QP */
1407#define IOPW_IX 0x26 /* IX */
1408#define IOPW_SP 0x28 /* SP */
1409#define IOPW_PC 0x2A /* PC */
1da177e4
LT		 1410#define IOPW_RES_ADDR_2C 0x2C
1411#define IOPW_RES_ADDR_2E 0x2E
27c868c2
MW		 1412#define IOPW_SCSI_DATA 0x30 /* SD */
1413#define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
1414#define IOPW_SCSI_CTRL 0x34 /* SC */
1415#define IOPW_HSHK_CFG 0x36 /* HCFG */
1416#define IOPW_SXFR_STATUS 0x36 /* SXS */
1417#define IOPW_SXFR_CNTL 0x38 /* SXL */
1418#define IOPW_SXFR_CNTH 0x3A /* SXH */
1da177e4 1419#define IOPW_RES_ADDR_3C 0x3C
27c868c2 1420#define IOPW_RFIFO_DATA 0x3E /* RFD */
1da177e4
LT		 1421
1422/*
1423 * Doubleword I/O register address from base of 'iop_base'.
1424 */
1425#define IOPDW_RES_ADDR_0 0x00
1426#define IOPDW_RAM_DATA 0x04
1427#define IOPDW_RES_ADDR_8 0x08
1428#define IOPDW_RES_ADDR_C 0x0C
1429#define IOPDW_RES_ADDR_10 0x10
1430#define IOPDW_COMMA 0x14
1431#define IOPDW_COMMB 0x18
1432#define IOPDW_RES_ADDR_1C 0x1C
1433#define IOPDW_SDMA_ADDR0 0x20
1434#define IOPDW_SDMA_ADDR1 0x24
1435#define IOPDW_SDMA_COUNT 0x28
1436#define IOPDW_SDMA_ERROR 0x2C
1437#define IOPDW_RDMA_ADDR0 0x30
1438#define IOPDW_RDMA_ADDR1 0x34
1439#define IOPDW_RDMA_COUNT 0x38
1440#define IOPDW_RDMA_ERROR 0x3C
1441
1442#define ADV_CHIP_ID_BYTE 0x25
1443#define ADV_CHIP_ID_WORD 0x04C1
1444
1da177e4
LT		 1445#define ADV_INTR_ENABLE_HOST_INTR 0x01
1446#define ADV_INTR_ENABLE_SEL_INTR 0x02
1447#define ADV_INTR_ENABLE_DPR_INTR 0x04
1448#define ADV_INTR_ENABLE_RTA_INTR 0x08
1449#define ADV_INTR_ENABLE_RMA_INTR 0x10
1450#define ADV_INTR_ENABLE_RST_INTR 0x20
1451#define ADV_INTR_ENABLE_DPE_INTR 0x40
1452#define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
1453
1454#define ADV_INTR_STATUS_INTRA 0x01
1455#define ADV_INTR_STATUS_INTRB 0x02
1456#define ADV_INTR_STATUS_INTRC 0x04
1457
1458#define ADV_RISC_CSR_STOP (0x0000)
1459#define ADV_RISC_TEST_COND (0x2000)
1460#define ADV_RISC_CSR_RUN (0x4000)
1461#define ADV_RISC_CSR_SINGLE_STEP (0x8000)
1462
1463#define ADV_CTRL_REG_HOST_INTR 0x0100
1464#define ADV_CTRL_REG_SEL_INTR 0x0200
1465#define ADV_CTRL_REG_DPR_INTR 0x0400
1466#define ADV_CTRL_REG_RTA_INTR 0x0800
1467#define ADV_CTRL_REG_RMA_INTR 0x1000
1468#define ADV_CTRL_REG_RES_BIT14 0x2000
1469#define ADV_CTRL_REG_DPE_INTR 0x4000
1470#define ADV_CTRL_REG_POWER_DONE 0x8000
1471#define ADV_CTRL_REG_ANY_INTR 0xFF00
1472
1473#define ADV_CTRL_REG_CMD_RESET 0x00C6
1474#define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
1475#define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
1476#define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
1477#define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
1478
1479#define ADV_TICKLE_NOP 0x00
1480#define ADV_TICKLE_A 0x01
1481#define ADV_TICKLE_B 0x02
1482#define ADV_TICKLE_C 0x03
1483
1da177e4
LT		 1484#define AdvIsIntPending(port) \
1485 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
1486
1487/*
1488 * SCSI_CFG0 Register bit definitions
1489 */
27c868c2
MW		 1490#define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
1491#define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
1492#define EVEN_PARITY 0x1000 /* Select Even Parity */
1493#define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
1494#define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
1495#define PRIM_MODE 0x0100 /* Primitive SCSI mode */
1496#define SCAM_EN 0x0080 /* Enable SCAM selection */
1497#define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
1498#define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
1499#define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
1500#define OUR_ID 0x000F /* SCSI ID */
1da177e4
LT		 1501
1502/*
1503 * SCSI_CFG1 Register bit definitions
1504 */
27c868c2
MW		 1505#define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
1506#define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
1507#define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
1508#define FILTER_SEL 0x0C00 /* Filter Period Selection */
1509#define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
1510#define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
1511#define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
1512#define ACTIVE_DBL 0x0200 /* Disable Active Negation */
1513#define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
1514#define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
1515#define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
1516#define TERM_CTL 0x0030 /* External SCSI Termination Bits */
1517#define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
1518#define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
1519#define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
1da177e4
LT		 1520
1521/*
1522 * Addendum for ASC-38C0800 Chip
1523 *
1524 * The ASC-38C1600 Chip uses the same definitions except that the
1525 * bus mode override bits [12:10] have been moved to byte register
1526 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
1527 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
1528 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
1529 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
1530 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
1531 */
27c868c2
MW		 1532#define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
1533#define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
1534#define HVD 0x1000 /* HVD Device Detect */
1535#define LVD 0x0800 /* LVD Device Detect */
1536#define SE 0x0400 /* SE Device Detect */
1537#define TERM_LVD 0x00C0 /* LVD Termination Bits */
1538#define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
1539#define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
1540#define TERM_SE 0x0030 /* SE Termination Bits */
1541#define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
1542#define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
1543#define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
1544#define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
1545#define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
1546#define C_DET_SE 0x0003 /* SE Cable Detect Bits */
1547#define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
1548#define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
1da177e4
LT		 1549
1550#define CABLE_ILLEGAL_A 0x7
1551 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
1552
1553#define CABLE_ILLEGAL_B 0xB
1554 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
1555
1556/*
1557 * MEM_CFG Register bit definitions
1558 */
27c868c2
MW		 1559#define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
1560#define FAST_EE_CLK 0x20 /* Diagnostic Bit */
1561#define RAM_SZ 0x1C /* Specify size of RAM to RISC */
1562#define RAM_SZ_2KB 0x00 /* 2 KB */
1563#define RAM_SZ_4KB 0x04 /* 4 KB */
1564#define RAM_SZ_8KB 0x08 /* 8 KB */
1565#define RAM_SZ_16KB 0x0C /* 16 KB */
1566#define RAM_SZ_32KB 0x10 /* 32 KB */
1567#define RAM_SZ_64KB 0x14 /* 64 KB */
1da177e4
LT		 1568
1569/*
1570 * DMA_CFG0 Register bit definitions
1571 *
1572 * This register is only accessible to the host.
1573 */
27c868c2
MW		 1574#define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
1575#define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
1576#define FIFO_THRESH_16B 0x00 /* 16 bytes */
1577#define FIFO_THRESH_32B 0x20 /* 32 bytes */
1578#define FIFO_THRESH_48B 0x30 /* 48 bytes */
1579#define FIFO_THRESH_64B 0x40 /* 64 bytes */
1580#define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
1581#define FIFO_THRESH_96B 0x60 /* 96 bytes */
1582#define FIFO_THRESH_112B 0x70 /* 112 bytes */
1583#define START_CTL 0x0C /* DMA start conditions */
1584#define START_CTL_TH 0x00 /* Wait threshold level (default) */
1585#define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
1586#define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
1587#define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
1588#define READ_CMD 0x03 /* Memory Read Method */
1589#define READ_CMD_MR 0x00 /* Memory Read */
1590#define READ_CMD_MRL 0x02 /* Memory Read Long */
1591#define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
1da177e4
LT		 1592
1593/*
1594 * ASC-38C0800 RAM BIST Register bit definitions
1595 */
1596#define RAM_TEST_MODE 0x80
1597#define PRE_TEST_MODE 0x40
1598#define NORMAL_MODE 0x00
1599#define RAM_TEST_DONE 0x10
1600#define RAM_TEST_STATUS 0x0F
1601#define RAM_TEST_HOST_ERROR 0x08
1602#define RAM_TEST_INTRAM_ERROR 0x04
1603#define RAM_TEST_RISC_ERROR 0x02
1604#define RAM_TEST_SCSI_ERROR 0x01
1605#define RAM_TEST_SUCCESS 0x00
1606#define PRE_TEST_VALUE 0x05
1607#define NORMAL_VALUE 0x00
1608
1609/*
1610 * ASC38C1600 Definitions
1611 *
1612 * IOPB_PCI_INT_CFG Bit Field Definitions
1613 */
1614
27c868c2 1615#define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
1da177e4
LT		 1616
1617/*
1618 * Bit 1 can be set to change the interrupt for the Function to operate in
1619 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
1620 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
1621 * mode, otherwise the operating mode is undefined.
1622 */
1623#define TOTEMPOLE 0x02
1624
1625/*
1626 * Bit 0 can be used to change the Int Pin for the Function. The value is
1627 * 0 by default for both Functions with Function 0 using INT A and Function
1628 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
1629 * INT A is used.
1630 *
1631 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
1632 * value specified in the PCI Configuration Space.
1633 */
1634#define INTAB 0x01
1635
1da177e4
LT		 1636/*
1637 * Adv Library Status Definitions
1638 */
1639#define ADV_TRUE 1
1640#define ADV_FALSE 0
1da177e4
LT		 1641#define ADV_SUCCESS 1
1642#define ADV_BUSY 0
1643#define ADV_ERROR (-1)
1644
1da177e4
LT		 1645/*
1646 * ADV_DVC_VAR 'warn_code' values
1647 */
27c868c2
MW		 1648#define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
1649#define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
1650#define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
27c868c2 1651#define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
1da177e4 1652
27c868c2
MW		 1653#define ADV_MAX_TID 15 /* max. target identifier */
1654#define ADV_MAX_LUN 7 /* max. logical unit number */
1da177e4 1655
1da177e4
LT		 1656/*
1657 * Fixed locations of microcode operating variables.
1658 */
27c868c2
MW		 1659#define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
1660#define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
1661#define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
1662#define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
1663#define ASC_MC_VERSION_NUM 0x003A /* microcode number */
1664#define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
1665#define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
1666#define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
1667#define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
1668#define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
1669#define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
1670#define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
1671#define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
1da177e4
LT		 1672#define ASC_MC_CHIP_TYPE 0x009A
1673#define ASC_MC_INTRB_CODE 0x009B
1674#define ASC_MC_WDTR_ABLE 0x009C
1675#define ASC_MC_SDTR_ABLE 0x009E
1676#define ASC_MC_TAGQNG_ABLE 0x00A0
1677#define ASC_MC_DISC_ENABLE 0x00A2
1678#define ASC_MC_IDLE_CMD_STATUS 0x00A4
1679#define ASC_MC_IDLE_CMD 0x00A6
1680#define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
1681#define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
1682#define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
1683#define ASC_MC_DEFAULT_MEM_CFG 0x00B0
1684#define ASC_MC_DEFAULT_SEL_MASK 0x00B2
1685#define ASC_MC_SDTR_DONE 0x00B6
1686#define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
1687#define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
1688#define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
27c868c2 1689#define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
1da177e4 1690#define ASC_MC_WDTR_DONE 0x0124
27c868c2 1691#define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
1da177e4
LT		 1692#define ASC_MC_ICQ 0x0160
1693#define ASC_MC_IRQ 0x0164
1694#define ASC_MC_PPR_ABLE 0x017A
1695
1696/*
1697 * BIOS LRAM variable absolute offsets.
1698 */
1699#define BIOS_CODESEG 0x54
1700#define BIOS_CODELEN 0x56
1701#define BIOS_SIGNATURE 0x58
1702#define BIOS_VERSION 0x5A
1703
1704/*
1705 * Microcode Control Flags
1706 *
1707 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
1708 * and handled by the microcode.
1709 */
27c868c2
MW		 1710#define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
1711#define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
1da177e4
LT		 1712
1713/*
1714 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
1715 */
1716#define HSHK_CFG_WIDE_XFR 0x8000
1717#define HSHK_CFG_RATE 0x0F00
1718#define HSHK_CFG_OFFSET 0x001F
1719
27c868c2
MW		 1720#define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
1721#define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
1722#define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
1723#define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
1724
1725#define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
1726#define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
1727#define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
1728#define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
1729#define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
1730
1731#define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
1732#define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
1733#define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
1734#define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
1735#define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
1da177e4
LT		 1736/*
1737 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
1738 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
1739 */
27c868c2
MW		 1740#define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
1741#define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
1da177e4
LT		 1742
1743/*
1744 * All fields here are accessed by the board microcode and need to be
1745 * little-endian.
1746 */
27c868c2
MW		 1747typedef struct adv_carr_t {
1748 ADV_VADDR carr_va; /* Carrier Virtual Address */
1749 ADV_PADDR carr_pa; /* Carrier Physical Address */
1750 ADV_VADDR areq_vpa; /* ASC_SCSI_REQ_Q Virtual or Physical Address */
1751 /*
1752 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer
1753 *
1754 * next_vpa [3:1] Reserved Bits
1755 * next_vpa [0] Done Flag set in Response Queue.
1756 */
1757 ADV_VADDR next_vpa;
1da177e4
LT		 1758} ADV_CARR_T;
1759
1760/*
1761 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
1762 */
1763#define ASC_NEXT_VPA_MASK 0xFFFFFFF0
1764
1765#define ASC_RQ_DONE 0x00000001
1766#define ASC_RQ_GOOD 0x00000002
1767#define ASC_CQ_STOPPER 0x00000000
1768
1769#define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
1770
1771#define ADV_CARRIER_NUM_PAGE_CROSSING \
fd625f47 1772 (((ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) + (PAGE_SIZE - 1))/PAGE_SIZE)
1da177e4
LT		 1773
1774#define ADV_CARRIER_BUFSIZE \
1775 ((ADV_CARRIER_COUNT + ADV_CARRIER_NUM_PAGE_CROSSING) * sizeof(ADV_CARR_T))
1776
1777/*
1778 * ASC_SCSI_REQ_Q 'a_flag' definitions
1779 *
1780 * The Adv Library should limit use to the lower nibble (4 bits) of
1781 * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
1782 */
27c868c2
MW		 1783#define ADV_POLL_REQUEST 0x01 /* poll for request completion */
1784#define ADV_SCSIQ_DONE 0x02 /* request done */
1785#define ADV_DONT_RETRY 0x08 /* don't do retry */
1da177e4 1786
27c868c2
MW		 1787#define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
1788#define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
1789#define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
1da177e4
LT		 1790
1791/*
1792 * Adapter temporary configuration structure
1793 *
1794 * This structure can be discarded after initialization. Don't add
1795 * fields here needed after initialization.
1796 *
1797 * Field naming convention:
1798 *
1799 * *_enable indicates the field enables or disables a feature. The
1800 * value of the field is never reset.
1801 */
1802typedef struct adv_dvc_cfg {
27c868c2
MW		 1803 ushort disc_enable; /* enable disconnection */
1804 uchar chip_version; /* chip version */
1805 uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
27c868c2
MW		 1806 ushort control_flag; /* Microcode Control Flag */
1807 ushort mcode_date; /* Microcode date */
1808 ushort mcode_version; /* Microcode version */
27c868c2
MW		 1809 ushort serial1; /* EEPROM serial number word 1 */
1810 ushort serial2; /* EEPROM serial number word 2 */
1811 ushort serial3; /* EEPROM serial number word 3 */
1da177e4
LT		 1812} ADV_DVC_CFG;
1813
1814struct adv_dvc_var;
1815struct adv_scsi_req_q;
1816
1da177e4 1817typedef struct asc_sg_block {
27c868c2
MW		 1818 uchar reserved1;
1819 uchar reserved2;
1820 uchar reserved3;
1821 uchar sg_cnt; /* Valid entries in block. */
1822 ADV_PADDR sg_ptr; /* Pointer to next sg block. */
1823 struct {
1824 ADV_PADDR sg_addr; /* SG element address. */
1825 ADV_DCNT sg_count; /* SG element count. */
1826 } sg_list[NO_OF_SG_PER_BLOCK];
1da177e4
LT		 1827} ADV_SG_BLOCK;
1828
1829/*
1830 * ADV_SCSI_REQ_Q - microcode request structure
1831 *
1832 * All fields in this structure up to byte 60 are used by the microcode.
1833 * The microcode makes assumptions about the size and ordering of fields
1834 * in this structure. Do not change the structure definition here without
1835 * coordinating the change with the microcode.
1836 *
1837 * All fields accessed by microcode must be maintained in little_endian
1838 * order.
1839 */
1840typedef struct adv_scsi_req_q {
27c868c2
MW		 1841 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
1842 uchar target_cmd;
1843 uchar target_id; /* Device target identifier. */
1844 uchar target_lun; /* Device target logical unit number. */
1845 ADV_PADDR data_addr; /* Data buffer physical address. */
1846 ADV_DCNT data_cnt; /* Data count. Ucode sets to residual. */
1847 ADV_PADDR sense_addr;
1848 ADV_PADDR carr_pa;
1849 uchar mflag;
1850 uchar sense_len;
1851 uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
1852 uchar scsi_cntl;
1853 uchar done_status; /* Completion status. */
1854 uchar scsi_status; /* SCSI status byte. */
1855 uchar host_status; /* Ucode host status. */
1856 uchar sg_working_ix;
1857 uchar cdb[12]; /* SCSI CDB bytes 0-11. */
1858 ADV_PADDR sg_real_addr; /* SG list physical address. */
1859 ADV_PADDR scsiq_rptr;
1860 uchar cdb16[4]; /* SCSI CDB bytes 12-15. */
1861 ADV_VADDR scsiq_ptr;
1862 ADV_VADDR carr_va;
1863 /*
1864 * End of microcode structure - 60 bytes. The rest of the structure
1865 * is used by the Adv Library and ignored by the microcode.
1866 */
9c17c62a 1867 u32 srb_tag;
27c868c2
MW		 1868 ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
1869 char *vdata_addr; /* Data buffer virtual address. */
1870 uchar a_flag;
1871 uchar pad[2]; /* Pad out to a word boundary. */
1da177e4
LT		 1872} ADV_SCSI_REQ_Q;
1873
98d41c29
MW		 1874/*
1875 * The following two structures are used to process Wide Board requests.
1876 *
1877 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
9c17c62a
HR		 1878 * and microcode with the ADV_SCSI_REQ_Q field 'srb_tag' set to the
1879 * SCSI request tag. The adv_req_t structure 'cmndp' field in turn points
1880 * to the Mid-Level SCSI request structure.
98d41c29
MW		 1881 *
1882 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
1883 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
1884 * up to 255 scatter-gather elements may be used per request or
1885 * ADV_SCSI_REQ_Q.
1886 *
1887 * Both structures must be 32 byte aligned.
1888 */
1889typedef struct adv_sgblk {
1890 ADV_SG_BLOCK sg_block; /* Sgblock structure. */
1891 uchar align[32]; /* Sgblock structure padding. */
1892 struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */
1893} adv_sgblk_t;
1894
1895typedef struct adv_req {
1896 ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */
1897 uchar align[32]; /* Request structure padding. */
1898 struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */
1899 adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */
1900 struct adv_req *next_reqp; /* Next Request Structure. */
1901} adv_req_t;
1902
1903/*
1904 * Adapter operation variable structure.
1905 *
1906 * One structure is required per host adapter.
1907 *
1908 * Field naming convention:
1909 *
1910 * *_able indicates both whether a feature should be enabled or disabled
1911 * and whether a device isi capable of the feature. At initialization
1912 * this field may be set, but later if a device is found to be incapable
1913 * of the feature, the field is cleared.
1914 */
1915typedef struct adv_dvc_var {
1916 AdvPortAddr iop_base; /* I/O port address */
1917 ushort err_code; /* fatal error code */
1918 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
1919 ushort wdtr_able; /* try WDTR for a device */
1920 ushort sdtr_able; /* try SDTR for a device */
1921 ushort ultra_able; /* try SDTR Ultra speed for a device */
1922 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
1923 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
1924 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
1925 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
1926 ushort tagqng_able; /* try tagged queuing with a device */
1927 ushort ppr_able; /* PPR message capable per TID bitmask. */
1928 uchar max_dvc_qng; /* maximum number of tagged commands per device */
1929 ushort start_motor; /* start motor command allowed */
1930 uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */
1931 uchar chip_no; /* should be assigned by caller */
1932 uchar max_host_qng; /* maximum number of Q'ed command allowed */
1933 ushort no_scam; /* scam_tolerant of EEPROM */
1934 struct asc_board *drv_ptr; /* driver pointer to private structure */
1935 uchar chip_scsi_id; /* chip SCSI target ID */
1936 uchar chip_type;
1937 uchar bist_err_code;
1938 ADV_CARR_T *carrier_buf;
1939 ADV_CARR_T *carr_freelist; /* Carrier free list. */
1940 ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */
1941 ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */
1942 ushort carr_pending_cnt; /* Count of pending carriers. */
98d41c29
MW		 1943 /*
1944 * Note: The following fields will not be used after initialization. The
1945 * driver may discard the buffer after initialization is done.
1946 */
1947 ADV_DVC_CFG *cfg; /* temporary configuration structure */
1948} ADV_DVC_VAR;
1949
1da177e4
LT		 1950/*
1951 * Microcode idle loop commands
1952 */
1953#define IDLE_CMD_COMPLETED 0
1954#define IDLE_CMD_STOP_CHIP 0x0001
1955#define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
1956#define IDLE_CMD_SEND_INT 0x0004
1957#define IDLE_CMD_ABORT 0x0008
1958#define IDLE_CMD_DEVICE_RESET 0x0010
27c868c2
MW		 1959#define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
1960#define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
1da177e4
LT		 1961#define IDLE_CMD_SCSIREQ 0x0080
1962
1963#define IDLE_CMD_STATUS_SUCCESS 0x0001
1964#define IDLE_CMD_STATUS_FAILURE 0x0002
1965
1966/*
1967 * AdvSendIdleCmd() flag definitions.
1968 */
1969#define ADV_NOWAIT 0x01
1970
1971/*
1972 * Wait loop time out values.
1973 */
27c868c2
MW		 1974#define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
1975#define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
27c868c2 1976#define SCSI_MAX_RETRY 10 /* retry count */
1da177e4 1977
27c868c2
MW		 1978#define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
1979#define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
1980#define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
1981#define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
1da177e4 1982
27c868c2 1983#define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
1da177e4 1984
1da177e4
LT		 1985/* Read byte from a register. */
1986#define AdvReadByteRegister(iop_base, reg_off) \
1987 (ADV_MEM_READB((iop_base) + (reg_off)))
1988
1989/* Write byte to a register. */
1990#define AdvWriteByteRegister(iop_base, reg_off, byte) \
1991 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
1992
1993/* Read word (2 bytes) from a register. */
1994#define AdvReadWordRegister(iop_base, reg_off) \
1995 (ADV_MEM_READW((iop_base) + (reg_off)))
1996
1997/* Write word (2 bytes) to a register. */
1998#define AdvWriteWordRegister(iop_base, reg_off, word) \
1999 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
2000
2001/* Write dword (4 bytes) to a register. */
2002#define AdvWriteDWordRegister(iop_base, reg_off, dword) \
2003 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
2004
2005/* Read byte from LRAM. */
2006#define AdvReadByteLram(iop_base, addr, byte) \
2007do { \
2008 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2009 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
2010} while (0)
2011
2012/* Write byte to LRAM. */
2013#define AdvWriteByteLram(iop_base, addr, byte) \
2014 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2015 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
2016
2017/* Read word (2 bytes) from LRAM. */
2018#define AdvReadWordLram(iop_base, addr, word) \
2019do { \
2020 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2021 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
2022} while (0)
2023
2024/* Write word (2 bytes) to LRAM. */
2025#define AdvWriteWordLram(iop_base, addr, word) \
2026 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2027 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2028
2029/* Write little-endian double word (4 bytes) to LRAM */
2030/* Because of unspecified C language ordering don't use auto-increment. */
2031#define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
2032 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2033 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2034 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
2035 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
2036 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2037 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
2038
2039/* Read word (2 bytes) from LRAM assuming that the address is already set. */
2040#define AdvReadWordAutoIncLram(iop_base) \
2041 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
2042
2043/* Write word (2 bytes) to LRAM assuming that the address is already set. */
2044#define AdvWriteWordAutoIncLram(iop_base, word) \
2045 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2046
1da177e4
LT		 2047/*
2048 * Define macro to check for Condor signature.
2049 *
2050 * Evaluate to ADV_TRUE if a Condor chip is found the specified port
2051 * address 'iop_base'. Otherwise evalue to ADV_FALSE.
2052 */
2053#define AdvFindSignature(iop_base) \
2054 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
2055 ADV_CHIP_ID_BYTE) && \
2056 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
2057 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
2058
2059/*
2060 * Define macro to Return the version number of the chip at 'iop_base'.
2061 *
2062 * The second parameter 'bus_type' is currently unused.
2063 */
2064#define AdvGetChipVersion(iop_base, bus_type) \
2065 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
2066
2067/*
9c17c62a
HR		 2068 * Abort an SRB in the chip's RISC Memory. The 'srb_tag' argument must
2069 * match the ASC_SCSI_REQ_Q 'srb_tag' field.
1da177e4
LT		 2070 *
2071 * If the request has not yet been sent to the device it will simply be
2072 * aborted from RISC memory. If the request is disconnected it will be
2073 * aborted on reselection by sending an Abort Message to the target ID.
2074 *
2075 * Return value:
2076 * ADV_TRUE(1) - Queue was successfully aborted.
2077 * ADV_FALSE(0) - Queue was not found on the active queue list.
2078 */
9c17c62a
HR		 2079#define AdvAbortQueue(asc_dvc, srb_tag) \
2080 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
2081 (ADV_DCNT) (srb_tag))
1da177e4
LT		 2082
2083/*
2084 * Send a Bus Device Reset Message to the specified target ID.
2085 *
2086 * All outstanding commands will be purged if sending the
2087 * Bus Device Reset Message is successful.
2088 *
2089 * Return Value:
2090 * ADV_TRUE(1) - All requests on the target are purged.
2091 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
2092 * are not purged.
2093 */
2094#define AdvResetDevice(asc_dvc, target_id) \
9c17c62a
HR		 2095 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
2096 (ADV_DCNT) (target_id))
1da177e4
LT		 2097
2098/*
2099 * SCSI Wide Type definition.
2100 */
2101#define ADV_SCSI_BIT_ID_TYPE ushort
2102
2103/*
2104 * AdvInitScsiTarget() 'cntl_flag' options.
2105 */
2106#define ADV_SCAN_LUN 0x01
2107#define ADV_CAPINFO_NOLUN 0x02
2108
2109/*
2110 * Convert target id to target id bit mask.
2111 */
2112#define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
2113
2114/*
2115 * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
2116 */
2117
27c868c2 2118#define QD_NO_STATUS 0x00 /* Request not completed yet. */
1da177e4
LT		 2119#define QD_NO_ERROR 0x01
2120#define QD_ABORTED_BY_HOST 0x02
2121#define QD_WITH_ERROR 0x04
2122
2123#define QHSTA_NO_ERROR 0x00
2124#define QHSTA_M_SEL_TIMEOUT 0x11
2125#define QHSTA_M_DATA_OVER_RUN 0x12
2126#define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
2127#define QHSTA_M_QUEUE_ABORTED 0x15
27c868c2
MW		 2128#define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
2129#define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
2130#define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
2131#define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
2132#define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
2133#define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
2134#define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
1da177e4 2135/* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
27c868c2
MW		 2136#define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
2137#define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
2138#define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
2139#define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
2140#define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
2141#define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
2142#define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
2143#define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
1da177e4
LT		 2144#define QHSTA_M_WTM_TIMEOUT 0x41
2145#define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
2146#define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
2147#define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
27c868c2
MW		 2148#define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
2149#define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
2150#define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
1da177e4 2151
1da177e4
LT		 2152/* Return the address that is aligned at the next doubleword >= to 'addr'. */
2153#define ADV_8BALIGN(addr) (((ulong) (addr) + 0x7) & ~0x7)
2154#define ADV_16BALIGN(addr) (((ulong) (addr) + 0xF) & ~0xF)
2155#define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F)
2156
2157/*
2158 * Total contiguous memory needed for driver SG blocks.
2159 *
2160 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
2161 * number of scatter-gather elements the driver supports in a
2162 * single request.
2163 */
2164
2165#define ADV_SG_LIST_MAX_BYTE_SIZE \
2166 (sizeof(ADV_SG_BLOCK) * \
2167 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
2168
d2411495 2169/* struct asc_board flags */
27c868c2 2170#define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */
1da177e4
LT		 2171
2172#define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
1da177e4 2173
27c868c2 2174#define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */
1da177e4 2175
27c868c2 2176#define ASC_INFO_SIZE 128 /* advansys_info() line size */
1da177e4 2177
1da177e4
LT		 2178/* Asc Library return codes */
2179#define ASC_TRUE 1
2180#define ASC_FALSE 0
2181#define ASC_NOERROR 1
2182#define ASC_BUSY 0
2183#define ASC_ERROR (-1)
2184
2185/* struct scsi_cmnd function return codes */
2186#define STATUS_BYTE(byte) (byte)
2187#define MSG_BYTE(byte) ((byte) << 8)
2188#define HOST_BYTE(byte) ((byte) << 16)
2189#define DRIVER_BYTE(byte) ((byte) << 24)
2190
d2411495 2191#define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1)
1da177e4 2192#ifndef ADVANSYS_STATS
27c868c2 2193#define ASC_STATS_ADD(shost, counter, count)
1da177e4 2194#else /* ADVANSYS_STATS */
27c868c2 2195#define ASC_STATS_ADD(shost, counter, count) \
d2411495 2196 (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count))
1da177e4
LT		 2197#endif /* ADVANSYS_STATS */
2198
1da177e4
LT		 2199/* If the result wraps when calculating tenths, return 0. */
2200#define ASC_TENTHS(num, den) \
2201 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
2202 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
2203
2204/*
2205 * Display a message to the console.
2206 */
2207#define ASC_PRINT(s) \
2208 { \
2209 printk("advansys: "); \
2210 printk(s); \
2211 }
2212
2213#define ASC_PRINT1(s, a1) \
2214 { \
2215 printk("advansys: "); \
2216 printk((s), (a1)); \
2217 }
2218
2219#define ASC_PRINT2(s, a1, a2) \
2220 { \
2221 printk("advansys: "); \
2222 printk((s), (a1), (a2)); \
2223 }
2224
2225#define ASC_PRINT3(s, a1, a2, a3) \
2226 { \
2227 printk("advansys: "); \
2228 printk((s), (a1), (a2), (a3)); \
2229 }
2230
2231#define ASC_PRINT4(s, a1, a2, a3, a4) \
2232 { \
2233 printk("advansys: "); \
2234 printk((s), (a1), (a2), (a3), (a4)); \
2235 }
2236
1da177e4
LT		 2237#ifndef ADVANSYS_DEBUG
2238
b352f923 2239#define ASC_DBG(lvl, s...)
1da177e4 2240#define ASC_DBG_PRT_SCSI_HOST(lvl, s)
1da177e4
LT		 2241#define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
2242#define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2243#define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
2244#define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2245#define ASC_DBG_PRT_HEX(lvl, name, start, length)
2246#define ASC_DBG_PRT_CDB(lvl, cdb, len)
2247#define ASC_DBG_PRT_SENSE(lvl, sense, len)
2248#define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
2249
2250#else /* ADVANSYS_DEBUG */
2251
2252/*
2253 * Debugging Message Levels:
2254 * 0: Errors Only
2255 * 1: High-Level Tracing
2256 * 2-N: Verbose Tracing
2257 */
2258
b352f923
MW		 2259#define ASC_DBG(lvl, format, arg...) { \
2260 if (asc_dbglvl >= (lvl)) \
2261 printk(KERN_DEBUG "%s: %s: " format, DRV_NAME, \
cadbd4a5 2262 __func__ , ## arg); \
b352f923 2263}
1da177e4
LT		 2264
2265#define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
2266 { \
2267 if (asc_dbglvl >= (lvl)) { \
2268 asc_prt_scsi_host(s); \
2269 } \
2270 }
2271
1da177e4
LT		 2272#define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
2273 { \
2274 if (asc_dbglvl >= (lvl)) { \
2275 asc_prt_asc_scsi_q(scsiqp); \
2276 } \
2277 }
2278
2279#define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
2280 { \
2281 if (asc_dbglvl >= (lvl)) { \
2282 asc_prt_asc_qdone_info(qdone); \
2283 } \
2284 }
2285
2286#define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
2287 { \
2288 if (asc_dbglvl >= (lvl)) { \
2289 asc_prt_adv_scsi_req_q(scsiqp); \
2290 } \
2291 }
2292
2293#define ASC_DBG_PRT_HEX(lvl, name, start, length) \
2294 { \
2295 if (asc_dbglvl >= (lvl)) { \
2296 asc_prt_hex((name), (start), (length)); \
2297 } \
2298 }
2299
2300#define ASC_DBG_PRT_CDB(lvl, cdb, len) \
2301 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
2302
2303#define ASC_DBG_PRT_SENSE(lvl, sense, len) \
2304 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
2305
2306#define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
2307 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
2308#endif /* ADVANSYS_DEBUG */
2309
1da177e4
LT		 2310#ifdef ADVANSYS_STATS
2311
2312/* Per board statistics structure */
2313struct asc_stats {
27c868c2
MW		 2314 /* Driver Entrypoint Statistics */
2315 ADV_DCNT queuecommand; /* # calls to advansys_queuecommand() */
2316 ADV_DCNT reset; /* # calls to advansys_eh_bus_reset() */
2317 ADV_DCNT biosparam; /* # calls to advansys_biosparam() */
2318 ADV_DCNT interrupt; /* # advansys_interrupt() calls */
2319 ADV_DCNT callback; /* # calls to asc/adv_isr_callback() */
2320 ADV_DCNT done; /* # calls to request's scsi_done function */
2321 ADV_DCNT build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
2322 ADV_DCNT adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
2323 ADV_DCNT adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
2324 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
2325 ADV_DCNT exe_noerror; /* # ASC_NOERROR returns. */
2326 ADV_DCNT exe_busy; /* # ASC_BUSY returns. */
2327 ADV_DCNT exe_error; /* # ASC_ERROR returns. */
2328 ADV_DCNT exe_unknown; /* # unknown returns. */
2329 /* Data Transfer Statistics */
52c334e9
MW		 2330 ADV_DCNT xfer_cnt; /* # I/O requests received */
2331 ADV_DCNT xfer_elem; /* # scatter-gather elements */
2332 ADV_DCNT xfer_sect; /* # 512-byte blocks */
1da177e4
LT		 2333};
2334#endif /* ADVANSYS_STATS */
2335
1da177e4
LT		 2336/*
2337 * Structure allocated for each board.
2338 *
8dfb5379 2339 * This structure is allocated by scsi_host_alloc() at the end
1da177e4
LT		 2340 * of the 'Scsi_Host' structure starting at the 'hostdata'
2341 * field. It is guaranteed to be allocated from DMA-able memory.
2342 */
d2411495 2343struct asc_board {
394dbf3f 2344 struct device *dev;
9c17c62a 2345 struct Scsi_Host *shost;
27c868c2 2346 uint flags; /* Board flags */
d361db48 2347 unsigned int irq;
27c868c2
MW		 2348 union {
2349 ASC_DVC_VAR asc_dvc_var; /* Narrow board */
2350 ADV_DVC_VAR adv_dvc_var; /* Wide board */
2351 } dvc_var;
2352 union {
2353 ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */
2354 ADV_DVC_CFG adv_dvc_cfg; /* Wide board */
2355 } dvc_cfg;
2356 ushort asc_n_io_port; /* Number I/O ports. */
27c868c2 2357 ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */
27c868c2
MW		 2358 ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
2359 ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */
2360 ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
2361 union {
2362 ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */
2363 ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */
2364 ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */
2365 ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */
2366 } eep_config;
27c868c2 2367 /* /proc/scsi/advansys/[0...] */
1da177e4 2368#ifdef ADVANSYS_STATS
27c868c2
MW		 2369 struct asc_stats asc_stats; /* Board statistics */
2370#endif /* ADVANSYS_STATS */
2371 /*
2372 * The following fields are used only for Narrow Boards.
2373 */
27c868c2
MW		 2374 uchar sdtr_data[ASC_MAX_TID + 1]; /* SDTR information */
2375 /*
2376 * The following fields are used only for Wide Boards.
2377 */
2378 void __iomem *ioremap_addr; /* I/O Memory remap address. */
2379 ushort ioport; /* I/O Port address. */
27c868c2
MW		 2380 adv_req_t *adv_reqp; /* Request structures. */
2381 adv_sgblk_t *adv_sgblkp; /* Scatter-gather structures. */
2382 ushort bios_signature; /* BIOS Signature. */
2383 ushort bios_version; /* BIOS Version. */
2384 ushort bios_codeseg; /* BIOS Code Segment. */
2385 ushort bios_codelen; /* BIOS Code Segment Length. */
d2411495 2386};
1da177e4 2387
d10fb2c7
MW		 2388#define asc_dvc_to_board(asc_dvc) container_of(asc_dvc, struct asc_board, \
2389 dvc_var.asc_dvc_var)
13ac2d9c
MW		 2390#define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
2391 dvc_var.adv_dvc_var)
2392#define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
2393
1da177e4 2394#ifdef ADVANSYS_DEBUG
27c868c2 2395static int asc_dbglvl = 3;
1da177e4 2396
1da177e4 2397/*
51219358 2398 * asc_prt_asc_dvc_var()
1da177e4 2399 */
51219358 2400static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
1da177e4 2401{
51219358 2402 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
27c868c2 2403
51219358
MW		 2404 printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
2405 "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
2406
2407 printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
2408 (unsigned)h->init_sdtr);
2409
2410 printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
2411 "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
2412 (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
2413 (unsigned)h->chip_no);
2414
2415 printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
2416 "%u,\n", (unsigned)h->queue_full_or_busy,
2417 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2418
2419 printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
2420 "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
2421 (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
2422 (unsigned)h->in_critical_cnt);
2423
2424 printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
2425 "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
2426 (unsigned)h->init_state, (unsigned)h->no_scam,
2427 (unsigned)h->pci_fix_asyn_xfer);
2428
d361db48 2429 printk(" cfg 0x%lx\n", (ulong)h->cfg);
1da177e4
LT		 2430}
2431
51219358
MW		 2432/*
2433 * asc_prt_asc_dvc_cfg()
2434 */
2435static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
6ed1ef07 2436{
51219358 2437 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
6ed1ef07 2438
51219358
MW		 2439 printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
2440 h->can_tagged_qng, h->cmd_qng_enabled);
2441 printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
2442 h->disc_enable, h->sdtr_enable);
6ed1ef07 2443
b08fc565
MW		 2444 printk(" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, "
2445 "chip_version %d,\n", h->chip_scsi_id, h->isa_dma_speed,
2446 h->isa_dma_channel, h->chip_version);
51219358 2447
d10fb2c7
MW		 2448 printk(" mcode_date 0x%x, mcode_version %d\n",
2449 h->mcode_date, h->mcode_version);
6ed1ef07
MW		 2450}
2451
1da177e4 2452/*
51219358 2453 * asc_prt_adv_dvc_var()
1da177e4 2454 *
51219358 2455 * Display an ADV_DVC_VAR structure.
1da177e4 2456 */
51219358 2457static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
1da177e4 2458{
51219358 2459 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
27c868c2 2460
51219358
MW		 2461 printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
2462 (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
1da177e4 2463
b352f923
MW		 2464 printk(" sdtr_able 0x%x, wdtr_able 0x%x\n",
2465 (unsigned)h->sdtr_able, (unsigned)h->wdtr_able);
1da177e4 2466
d361db48
MW		 2467 printk(" start_motor 0x%x, scsi_reset_wait 0x%x\n",
2468 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
1da177e4 2469
51219358
MW		 2470 printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%lxn\n",
2471 (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
2472 (ulong)h->carr_freelist);
1da177e4 2473
51219358
MW		 2474 printk(" icq_sp 0x%lx, irq_sp 0x%lx\n",
2475 (ulong)h->icq_sp, (ulong)h->irq_sp);
1da177e4 2476
51219358
MW		 2477 printk(" no_scam 0x%x, tagqng_able 0x%x\n",
2478 (unsigned)h->no_scam, (unsigned)h->tagqng_able);
1da177e4 2479
51219358
MW		 2480 printk(" chip_scsi_id 0x%x, cfg 0x%lx\n",
2481 (unsigned)h->chip_scsi_id, (ulong)h->cfg);
2482}
1da177e4 2483
51219358
MW		 2484/*
2485 * asc_prt_adv_dvc_cfg()
2486 *
2487 * Display an ADV_DVC_CFG structure.
2488 */
2489static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
2490{
2491 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
27c868c2 2492
51219358
MW		 2493 printk(" disc_enable 0x%x, termination 0x%x\n",
2494 h->disc_enable, h->termination);
1da177e4 2495
51219358
MW		 2496 printk(" chip_version 0x%x, mcode_date 0x%x\n",
2497 h->chip_version, h->mcode_date);
27c868c2 2498
b352f923
MW		 2499 printk(" mcode_version 0x%x, control_flag 0x%x\n",
2500 h->mcode_version, h->control_flag);
1da177e4
LT		 2501}
2502
2503/*
b352f923 2504 * asc_prt_scsi_host()
1da177e4 2505 */
b352f923 2506static void asc_prt_scsi_host(struct Scsi_Host *s)
1da177e4 2507{
b352f923 2508 struct asc_board *boardp = shost_priv(s);
51219358 2509
71610f55 2510 printk("Scsi_Host at addr 0x%p, device %s\n", s, dev_name(boardp->dev));
50d14a70 2511 printk(" host_busy %u, host_no %d,\n",
74665016 2512 atomic_read(&s->host_busy), s->host_no);
51219358 2513
b352f923
MW		 2514 printk(" base 0x%lx, io_port 0x%lx, irq %d,\n",
2515 (ulong)s->base, (ulong)s->io_port, boardp->irq);
51219358 2516
b352f923
MW		 2517 printk(" dma_channel %d, this_id %d, can_queue %d,\n",
2518 s->dma_channel, s->this_id, s->can_queue);
1da177e4 2519
b352f923
MW		 2520 printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
2521 s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
27c868c2 2522
b352f923
MW		 2523 if (ASC_NARROW_BOARD(boardp)) {
2524 asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var);
2525 asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg);
2526 } else {
2527 asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var);
2528 asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg);
074c8fe4 2529 }
1da177e4
LT		 2530}
2531
51219358
MW		 2532/*
2533 * asc_prt_hex()
2534 *
2535 * Print hexadecimal output in 4 byte groupings 32 bytes
2536 * or 8 double-words per line.
2537 */
2538static void asc_prt_hex(char *f, uchar *s, int l)
47d853cc 2539{
51219358
MW		 2540 int i;
2541 int j;
2542 int k;
2543 int m;
47d853cc 2544
51219358
MW		 2545 printk("%s: (%d bytes)\n", f, l);
2546
2547 for (i = 0; i < l; i += 32) {
2548
2549 /* Display a maximum of 8 double-words per line. */
2550 if ((k = (l - i) / 4) >= 8) {
2551 k = 8;
2552 m = 0;
47d853cc 2553 } else {
51219358 2554 m = (l - i) % 4;
47d853cc
MW		 2555 }
2556
51219358
MW		 2557 for (j = 0; j < k; j++) {
2558 printk(" %2.2X%2.2X%2.2X%2.2X",
2559 (unsigned)s[i + (j * 4)],
2560 (unsigned)s[i + (j * 4) + 1],
2561 (unsigned)s[i + (j * 4) + 2],
2562 (unsigned)s[i + (j * 4) + 3]);
47d853cc 2563 }
47d853cc 2564
51219358
MW		 2565 switch (m) {
2566 case 0:
2567 default:
2568 break;
2569 case 1:
2570 printk(" %2.2X", (unsigned)s[i + (j * 4)]);
2571 break;
2572 case 2:
2573 printk(" %2.2X%2.2X",
2574 (unsigned)s[i + (j * 4)],
2575 (unsigned)s[i + (j * 4) + 1]);
2576 break;
2577 case 3:
2578 printk(" %2.2X%2.2X%2.2X",
2579 (unsigned)s[i + (j * 4) + 1],
2580 (unsigned)s[i + (j * 4) + 2],
2581 (unsigned)s[i + (j * 4) + 3]);
2582 break;
2583 }
47d853cc 2584
51219358 2585 printk("\n");
47d853cc
MW		 2586 }
2587}
b352f923
MW		 2588
2589/*
2590 * asc_prt_asc_scsi_q()
2591 */
2592static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
2593{
2594 ASC_SG_HEAD *sgp;
2595 int i;
2596
2597 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
2598
2599 printk
9c17c62a
HR		 2600 (" target_ix 0x%x, target_lun %u, srb_tag 0x%x, tag_code 0x%x,\n",
2601 q->q2.target_ix, q->q1.target_lun, q->q2.srb_tag,
b352f923
MW		 2602 q->q2.tag_code);
2603
2604 printk
2605 (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2606 (ulong)le32_to_cpu(q->q1.data_addr),
2607 (ulong)le32_to_cpu(q->q1.data_cnt),
2608 (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
2609
2610 printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
2611 (ulong)q->cdbptr, q->q2.cdb_len,
2612 (ulong)q->sg_head, q->q1.sg_queue_cnt);
2613
2614 if (q->sg_head) {
2615 sgp = q->sg_head;
2616 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
2617 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
2618 sgp->queue_cnt);
2619 for (i = 0; i < sgp->entry_cnt; i++) {
2620 printk(" [%u]: addr 0x%lx, bytes %lu\n",
2621 i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
2622 (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
2623 }
2624
2625 }
2626}
2627
2628/*
2629 * asc_prt_asc_qdone_info()
2630 */
2631static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
2632{
2633 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
9c17c62a
HR		 2634 printk(" srb_tag 0x%x, target_ix %u, cdb_len %u, tag_code %u,\n",
2635 q->d2.srb_tag, q->d2.target_ix, q->d2.cdb_len,
b352f923
MW		 2636 q->d2.tag_code);
2637 printk
2638 (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
2639 q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
2640}
2641
2642/*
2643 * asc_prt_adv_sgblock()
2644 *
2645 * Display an ADV_SG_BLOCK structure.
2646 */
2647static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
2648{
2649 int i;
2650
2651 printk(" ASC_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
2652 (ulong)b, sgblockno);
2653 printk(" sg_cnt %u, sg_ptr 0x%lx\n",
2654 b->sg_cnt, (ulong)le32_to_cpu(b->sg_ptr));
2655 BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
2656 if (b->sg_ptr != 0)
2657 BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
2658 for (i = 0; i < b->sg_cnt; i++) {
2659 printk(" [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
2660 i, (ulong)b->sg_list[i].sg_addr,
2661 (ulong)b->sg_list[i].sg_count);
2662 }
2663}
2664
2665/*
2666 * asc_prt_adv_scsi_req_q()
2667 *
2668 * Display an ADV_SCSI_REQ_Q structure.
2669 */
2670static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
2671{
2672 int sg_blk_cnt;
2673 struct asc_sg_block *sg_ptr;
2674
2675 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
2676
9c17c62a
HR		 2677 printk(" target_id %u, target_lun %u, srb_tag 0x%x, a_flag 0x%x\n",
2678 q->target_id, q->target_lun, q->srb_tag, q->a_flag);
b352f923
MW		 2679
2680 printk(" cntl 0x%x, data_addr 0x%lx, vdata_addr 0x%lx\n",
2681 q->cntl, (ulong)le32_to_cpu(q->data_addr), (ulong)q->vdata_addr);
2682
2683 printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2684 (ulong)le32_to_cpu(q->data_cnt),
2685 (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
2686
2687 printk
2688 (" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
2689 q->cdb_len, q->done_status, q->host_status, q->scsi_status);
2690
2691 printk(" sg_working_ix 0x%x, target_cmd %u\n",
2692 q->sg_working_ix, q->target_cmd);
2693
2694 printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
2695 (ulong)le32_to_cpu(q->scsiq_rptr),
2696 (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
2697
2698 /* Display the request's ADV_SG_BLOCK structures. */
2699 if (q->sg_list_ptr != NULL) {
2700 sg_blk_cnt = 0;
2701 while (1) {
2702 /*
2703 * 'sg_ptr' is a physical address. Convert it to a virtual
2704 * address by indexing 'sg_blk_cnt' into the virtual address
2705 * array 'sg_list_ptr'.
2706 *
2707 * XXX - Assumes all SG physical blocks are virtually contiguous.
2708 */
2709 sg_ptr =
2710 &(((ADV_SG_BLOCK *)(q->sg_list_ptr))[sg_blk_cnt]);
2711 asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
2712 if (sg_ptr->sg_ptr == 0) {
2713 break;
2714 }
2715 sg_blk_cnt++;
2716 }
2717 }
2718}
51219358 2719#endif /* ADVANSYS_DEBUG */
47d853cc 2720
1da177e4 2721/*
51219358 2722 * advansys_info()
47d853cc 2723 *
51219358
MW		 2724 * Return suitable for printing on the console with the argument
2725 * adapter's configuration information.
2726 *
2727 * Note: The information line should not exceed ASC_INFO_SIZE bytes,
2728 * otherwise the static 'info' array will be overrun.
1da177e4 2729 */
51219358 2730static const char *advansys_info(struct Scsi_Host *shost)
1da177e4 2731{
51219358 2732 static char info[ASC_INFO_SIZE];
d2411495 2733 struct asc_board *boardp = shost_priv(shost);
51219358
MW		 2734 ASC_DVC_VAR *asc_dvc_varp;
2735 ADV_DVC_VAR *adv_dvc_varp;
2736 char *busname;
2737 char *widename = NULL;
1da177e4 2738
51219358
MW		 2739 if (ASC_NARROW_BOARD(boardp)) {
2740 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
b352f923 2741 ASC_DBG(1, "begin\n");
51219358
MW		 2742 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2743 if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
2744 ASC_IS_ISAPNP) {
2745 busname = "ISA PnP";
2746 } else {
2747 busname = "ISA";
2748 }
2749 sprintf(info,
2750 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
2751 ASC_VERSION, busname,
2752 (ulong)shost->io_port,
2753 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
d361db48 2754 boardp->irq, shost->dma_channel);
51219358
MW		 2755 } else {
2756 if (asc_dvc_varp->bus_type & ASC_IS_VL) {
2757 busname = "VL";
2758 } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
2759 busname = "EISA";
2760 } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
2761 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
2762 == ASC_IS_PCI_ULTRA) {
2763 busname = "PCI Ultra";
2764 } else {
2765 busname = "PCI";
2766 }
2767 } else {
2768 busname = "?";
9d0e96eb
MW		 2769 shost_printk(KERN_ERR, shost, "unknown bus "
2770 "type %d\n", asc_dvc_varp->bus_type);
51219358
MW		 2771 }
2772 sprintf(info,
2773 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
2774 ASC_VERSION, busname, (ulong)shost->io_port,
2775 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
d361db48 2776 boardp->irq);
51219358
MW		 2777 }
2778 } else {
2779 /*
2780 * Wide Adapter Information
2781 *
2782 * Memory-mapped I/O is used instead of I/O space to access
2783 * the adapter, but display the I/O Port range. The Memory
2784 * I/O address is displayed through the driver /proc file.
2785 */
2786 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2787 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2788 widename = "Ultra-Wide";
2789 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2790 widename = "Ultra2-Wide";
2791 } else {
2792 widename = "Ultra3-Wide";
2793 }
2794 sprintf(info,
2795 "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
2796 ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
d361db48 2797 (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq);
51219358
MW		 2798 }
2799 BUG_ON(strlen(info) >= ASC_INFO_SIZE);
b352f923 2800 ASC_DBG(1, "end\n");
51219358 2801 return info;
47d853cc
MW		 2802}
2803
51219358 2804#ifdef CONFIG_PROC_FS
47d853cc
MW		 2805
2806/*
51219358 2807 * asc_prt_board_devices()
47d853cc 2808 *
51219358 2809 * Print driver information for devices attached to the board.
47d853cc 2810 */
b59fb6fd 2811static void asc_prt_board_devices(struct seq_file *m, struct Scsi_Host *shost)
47d853cc 2812{
d2411495 2813 struct asc_board *boardp = shost_priv(shost);
51219358
MW		 2814 int chip_scsi_id;
2815 int i;
47d853cc 2816
b59fb6fd
AV		 2817 seq_printf(m,
2818 "\nDevice Information for AdvanSys SCSI Host %d:\n",
2819 shost->host_no);
47d853cc 2820
51219358
MW		 2821 if (ASC_NARROW_BOARD(boardp)) {
2822 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
2823 } else {
2824 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
47d853cc
MW		 2825 }
2826
2f979427 2827 seq_puts(m, "Target IDs Detected:");
51219358 2828 for (i = 0; i <= ADV_MAX_TID; i++) {
b59fb6fd
AV		 2829 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i))
2830 seq_printf(m, " %X,", i);
27c868c2 2831 }
b59fb6fd 2832 seq_printf(m, " (%X=Host Adapter)\n", chip_scsi_id);
47d853cc
MW		 2833}
2834
2835/*
51219358 2836 * Display Wide Board BIOS Information.
47d853cc 2837 */
b59fb6fd 2838static void asc_prt_adv_bios(struct seq_file *m, struct Scsi_Host *shost)
47d853cc 2839{
d2411495 2840 struct asc_board *boardp = shost_priv(shost);
51219358
MW		 2841 ushort major, minor, letter;
2842
2f979427 2843 seq_puts(m, "\nROM BIOS Version: ");
47d853cc
MW		 2844
2845 /*
51219358
MW		 2846 * If the BIOS saved a valid signature, then fill in
2847 * the BIOS code segment base address.
47d853cc 2848 */
51219358 2849 if (boardp->bios_signature != 0x55AA) {
3d30079c
RV		 2850 seq_puts(m, "Disabled or Pre-3.1\n"
2851 "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n"
2852 "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
51219358
MW		 2853 } else {
2854 major = (boardp->bios_version >> 12) & 0xF;
2855 minor = (boardp->bios_version >> 8) & 0xF;
2856 letter = (boardp->bios_version & 0xFF);
47d853cc 2857
b59fb6fd 2858 seq_printf(m, "%d.%d%c\n",
51219358
MW		 2859 major, minor,
2860 letter >= 26 ? '?' : letter + 'A');
51219358
MW		 2861 /*
2862 * Current available ROM BIOS release is 3.1I for UW
2863 * and 3.2I for U2W. This code doesn't differentiate
2864 * UW and U2W boards.
2865 */
2866 if (major < 3 || (major <= 3 && minor < 1) ||
2867 (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
3d30079c
RV		 2868 seq_puts(m, "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n"
2869 "ftp://ftp.connectcom.net/pub\n");
51219358
MW		 2870 }
2871 }
1da177e4
LT		 2872}
2873
1da177e4 2874/*
51219358
MW		 2875 * Add serial number to information bar if signature AAh
2876 * is found in at bit 15-9 (7 bits) of word 1.
1da177e4 2877 *
51219358 2878 * Serial Number consists fo 12 alpha-numeric digits.
1da177e4 2879 *
51219358
MW		 2880 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits)
2881 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits)
2882 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits)
2883 * 5 - Product revision (A-J) Word0: " "
1da177e4 2884 *
51219358
MW		 2885 * Signature Word1: 15-9 (7 bits)
2886 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
2887 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits)
1da177e4 2888 *
51219358 2889 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
1da177e4 2890 *
51219358 2891 * Note 1: Only production cards will have a serial number.
1da177e4 2892 *
51219358 2893 * Note 2: Signature is most significant 7 bits (0xFE).
1da177e4 2894 *
51219358 2895 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
1da177e4 2896 */
51219358 2897static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
1da177e4 2898{
51219358 2899 ushort w, num;
27c868c2 2900
51219358
MW		 2901 if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
2902 return ASC_FALSE;
2903 } else {
2904 /*
2905 * First word - 6 digits.
2906 */
2907 w = serialnum[0];
27c868c2 2908
51219358
MW		 2909 /* Product type - 1st digit. */
2910 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
2911 /* Product type is P=Prototype */
2912 *cp += 0x8;
2913 }
2914 cp++;
2915
2916 /* Manufacturing location - 2nd digit. */
2917 *cp++ = 'A' + ((w & 0x1C00) >> 10);
2918
2919 /* Product ID - 3rd, 4th digits. */
2920 num = w & 0x3FF;
2921 *cp++ = '0' + (num / 100);
2922 num %= 100;
2923 *cp++ = '0' + (num / 10);
2924
2925 /* Product revision - 5th digit. */
2926 *cp++ = 'A' + (num % 10);
27c868c2 2927
27c868c2 2928 /*
51219358 2929 * Second word
27c868c2 2930 */
51219358 2931 w = serialnum[1];
27c868c2
MW		 2932
2933 /*
51219358 2934 * Year - 6th digit.
27c868c2 2935 *
51219358
MW		 2936 * If bit 15 of third word is set, then the
2937 * last digit of the year is greater than 7.
27c868c2 2938 */
51219358
MW		 2939 if (serialnum[2] & 0x8000) {
2940 *cp++ = '8' + ((w & 0x1C0) >> 6);
2941 } else {
2942 *cp++ = '0' + ((w & 0x1C0) >> 6);
27c868c2
MW		 2943 }
2944
51219358
MW		 2945 /* Week of year - 7th, 8th digits. */
2946 num = w & 0x003F;
2947 *cp++ = '0' + num / 10;
2948 num %= 10;
2949 *cp++ = '0' + num;
27c868c2
MW		 2950
2951 /*
51219358 2952 * Third word
27c868c2 2953 */
51219358 2954 w = serialnum[2] & 0x7FFF;
1da177e4 2955
51219358
MW		 2956 /* Serial number - 9th digit. */
2957 *cp++ = 'A' + (w / 1000);
27c868c2 2958
51219358
MW		 2959 /* 10th, 11th, 12th digits. */
2960 num = w % 1000;
2961 *cp++ = '0' + num / 100;
2962 num %= 100;
2963 *cp++ = '0' + num / 10;
2964 num %= 10;
2965 *cp++ = '0' + num;
2966
2967 *cp = '\0'; /* Null Terminate the string. */
2968 return ASC_TRUE;
2969 }
1da177e4
LT		 2970}
2971
2972/*
51219358 2973 * asc_prt_asc_board_eeprom()
1da177e4 2974 *
51219358 2975 * Print board EEPROM configuration.
1da177e4 2976 */
b59fb6fd 2977static void asc_prt_asc_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 2978{
d2411495 2979 struct asc_board *boardp = shost_priv(shost);
51219358 2980 ASC_DVC_VAR *asc_dvc_varp;
51219358
MW		 2981 ASCEEP_CONFIG *ep;
2982 int i;
2983#ifdef CONFIG_ISA
2984 int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
2985#endif /* CONFIG_ISA */
2986 uchar serialstr[13];
27c868c2 2987
51219358
MW		 2988 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2989 ep = &boardp->eep_config.asc_eep;
27c868c2 2990
b59fb6fd
AV		 2991 seq_printf(m,
2992 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
2993 shost->host_no);
1da177e4 2994
51219358 2995 if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
b59fb6fd
AV		 2996 == ASC_TRUE)
2997 seq_printf(m, " Serial Number: %s\n", serialstr);
2998 else if (ep->adapter_info[5] == 0xBB)
2f979427
RV		 2999 seq_puts(m,
3000 " Default Settings Used for EEPROM-less Adapter.\n");
b59fb6fd 3001 else
2f979427 3002 seq_puts(m, " Serial Number Signature Not Present.\n");
b59fb6fd
AV		 3003
3004 seq_printf(m,
3005 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3006 ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
3007 ep->max_tag_qng);
3008
3009 seq_printf(m,
3010 " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
3011
2f979427 3012 seq_puts(m, " Target ID: ");
b59fb6fd
AV		 3013 for (i = 0; i <= ASC_MAX_TID; i++)
3014 seq_printf(m, " %d", i);
b59fb6fd 3015
3d30079c 3016 seq_puts(m, "\n Disconnects: ");
b59fb6fd
AV		 3017 for (i = 0; i <= ASC_MAX_TID; i++)
3018 seq_printf(m, " %c",
3019 (ep->disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
b59fb6fd 3020
3d30079c 3021 seq_puts(m, "\n Command Queuing: ");
b59fb6fd
AV		 3022 for (i = 0; i <= ASC_MAX_TID; i++)
3023 seq_printf(m, " %c",
3024 (ep->use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
b59fb6fd 3025
3d30079c 3026 seq_puts(m, "\n Start Motor: ");
b59fb6fd
AV		 3027 for (i = 0; i <= ASC_MAX_TID; i++)
3028 seq_printf(m, " %c",
3029 (ep->start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
b59fb6fd 3030
3d30079c 3031 seq_puts(m, "\n Synchronous Transfer:");
b59fb6fd
AV		 3032 for (i = 0; i <= ASC_MAX_TID; i++)
3033 seq_printf(m, " %c",
3034 (ep->init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
f50332ff 3035 seq_putc(m, '\n');
51219358
MW		 3036
3037#ifdef CONFIG_ISA
3038 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
b59fb6fd
AV		 3039 seq_printf(m,
3040 " Host ISA DMA speed: %d MB/S\n",
3041 isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
51219358
MW		 3042 }
3043#endif /* CONFIG_ISA */
1da177e4
LT		 3044}
3045
3046/*
51219358 3047 * asc_prt_adv_board_eeprom()
1da177e4 3048 *
51219358 3049 * Print board EEPROM configuration.
1da177e4 3050 */
b59fb6fd 3051static void asc_prt_adv_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 3052{
d2411495 3053 struct asc_board *boardp = shost_priv(shost);
51219358 3054 ADV_DVC_VAR *adv_dvc_varp;
27c868c2 3055 int i;
51219358
MW		 3056 char *termstr;
3057 uchar serialstr[13];
3058 ADVEEP_3550_CONFIG *ep_3550 = NULL;
3059 ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
3060 ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
3061 ushort word;
3062 ushort *wordp;
3063 ushort sdtr_speed = 0;
27c868c2 3064
51219358
MW		 3065 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
3066 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3067 ep_3550 = &boardp->eep_config.adv_3550_eep;
3068 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3069 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
27c868c2 3070 } else {
51219358 3071 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
27c868c2 3072 }
1da177e4 3073
b59fb6fd
AV		 3074 seq_printf(m,
3075 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3076 shost->host_no);
27c868c2 3077
51219358
MW		 3078 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3079 wordp = &ep_3550->serial_number_word1;
3080 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3081 wordp = &ep_38C0800->serial_number_word1;
3082 } else {
3083 wordp = &ep_38C1600->serial_number_word1;
3084 }
27c868c2 3085
b59fb6fd
AV		 3086 if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE)
3087 seq_printf(m, " Serial Number: %s\n", serialstr);
3088 else
2f979427 3089 seq_puts(m, " Serial Number Signature Not Present.\n");
27c868c2 3090
b59fb6fd
AV		 3091 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3092 seq_printf(m,
3093 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3094 ep_3550->adapter_scsi_id,
3095 ep_3550->max_host_qng, ep_3550->max_dvc_qng);
3096 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3097 seq_printf(m,
3098 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3099 ep_38C0800->adapter_scsi_id,
3100 ep_38C0800->max_host_qng,
3101 ep_38C0800->max_dvc_qng);
3102 else
3103 seq_printf(m,
3104 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3105 ep_38C1600->adapter_scsi_id,
3106 ep_38C1600->max_host_qng,
3107 ep_38C1600->max_dvc_qng);
51219358
MW		 3108 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3109 word = ep_3550->termination;
3110 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3111 word = ep_38C0800->termination_lvd;
3112 } else {
3113 word = ep_38C1600->termination_lvd;
3114 }
3115 switch (word) {
3116 case 1:
3117 termstr = "Low Off/High Off";
3118 break;
3119 case 2:
3120 termstr = "Low Off/High On";
3121 break;
3122 case 3:
3123 termstr = "Low On/High On";
3124 break;
3125 default:
3126 case 0:
3127 termstr = "Automatic";
3128 break;
27c868c2 3129 }
1da177e4 3130
b59fb6fd
AV		 3131 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3132 seq_printf(m,
3133 " termination: %u (%s), bios_ctrl: 0x%x\n",
3134 ep_3550->termination, termstr,
3135 ep_3550->bios_ctrl);
3136 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3137 seq_printf(m,
3138 " termination: %u (%s), bios_ctrl: 0x%x\n",
3139 ep_38C0800->termination_lvd, termstr,
3140 ep_38C0800->bios_ctrl);
3141 else
3142 seq_printf(m,
3143 " termination: %u (%s), bios_ctrl: 0x%x\n",
3144 ep_38C1600->termination_lvd, termstr,
3145 ep_38C1600->bios_ctrl);
1da177e4 3146
2f979427 3147 seq_puts(m, " Target ID: ");
b59fb6fd
AV		 3148 for (i = 0; i <= ADV_MAX_TID; i++)
3149 seq_printf(m, " %X", i);
f50332ff 3150 seq_putc(m, '\n');
1da177e4 3151
51219358
MW		 3152 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3153 word = ep_3550->disc_enable;
3154 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3155 word = ep_38C0800->disc_enable;
3156 } else {
3157 word = ep_38C1600->disc_enable;
3158 }
2f979427 3159 seq_puts(m, " Disconnects: ");
b59fb6fd
AV		 3160 for (i = 0; i <= ADV_MAX_TID; i++)
3161 seq_printf(m, " %c",
3162 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
f50332ff 3163 seq_putc(m, '\n');
1da177e4 3164
51219358
MW		 3165 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3166 word = ep_3550->tagqng_able;
3167 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3168 word = ep_38C0800->tagqng_able;
3169 } else {
3170 word = ep_38C1600->tagqng_able;
3171 }
2f979427 3172 seq_puts(m, " Command Queuing: ");
b59fb6fd
AV		 3173 for (i = 0; i <= ADV_MAX_TID; i++)
3174 seq_printf(m, " %c",
3175 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
f50332ff 3176 seq_putc(m, '\n');
1da177e4 3177
51219358
MW		 3178 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3179 word = ep_3550->start_motor;
3180 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3181 word = ep_38C0800->start_motor;
27c868c2 3182 } else {
51219358
MW		 3183 word = ep_38C1600->start_motor;
3184 }
2f979427 3185 seq_puts(m, " Start Motor: ");
b59fb6fd
AV		 3186 for (i = 0; i <= ADV_MAX_TID; i++)
3187 seq_printf(m, " %c",
3188 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
f50332ff 3189 seq_putc(m, '\n');
27c868c2 3190
51219358 3191 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2f979427 3192 seq_puts(m, " Synchronous Transfer:");
b59fb6fd
AV		 3193 for (i = 0; i <= ADV_MAX_TID; i++)
3194 seq_printf(m, " %c",
3195 (ep_3550->sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
3196 'Y' : 'N');
f50332ff 3197 seq_putc(m, '\n');
51219358 3198 }
27c868c2 3199
51219358 3200 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2f979427 3201 seq_puts(m, " Ultra Transfer: ");
b59fb6fd
AV		 3202 for (i = 0; i <= ADV_MAX_TID; i++)
3203 seq_printf(m, " %c",
3204 (ep_3550->ultra_able & ADV_TID_TO_TIDMASK(i))
3205 ? 'Y' : 'N');
f50332ff 3206 seq_putc(m, '\n');
51219358 3207 }
27c868c2 3208
51219358
MW		 3209 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3210 word = ep_3550->wdtr_able;
3211 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3212 word = ep_38C0800->wdtr_able;
3213 } else {
3214 word = ep_38C1600->wdtr_able;
3215 }
2f979427 3216 seq_puts(m, " Wide Transfer: ");
b59fb6fd
AV		 3217 for (i = 0; i <= ADV_MAX_TID; i++)
3218 seq_printf(m, " %c",
3219 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
f50332ff 3220 seq_putc(m, '\n');
1da177e4 3221
51219358
MW		 3222 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
3223 adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
2f979427 3224 seq_puts(m, " Synchronous Transfer Speed (Mhz):\n ");
51219358
MW		 3225 for (i = 0; i <= ADV_MAX_TID; i++) {
3226 char *speed_str;
1da177e4 3227
51219358
MW		 3228 if (i == 0) {
3229 sdtr_speed = adv_dvc_varp->sdtr_speed1;
3230 } else if (i == 4) {
3231 sdtr_speed = adv_dvc_varp->sdtr_speed2;
3232 } else if (i == 8) {
3233 sdtr_speed = adv_dvc_varp->sdtr_speed3;
3234 } else if (i == 12) {
3235 sdtr_speed = adv_dvc_varp->sdtr_speed4;
3236 }
3237 switch (sdtr_speed & ADV_MAX_TID) {
3238 case 0:
3239 speed_str = "Off";
3240 break;
3241 case 1:
3242 speed_str = " 5";
3243 break;
3244 case 2:
3245 speed_str = " 10";
3246 break;
3247 case 3:
3248 speed_str = " 20";
3249 break;
3250 case 4:
3251 speed_str = " 40";
3252 break;
3253 case 5:
3254 speed_str = " 80";
3255 break;
3256 default:
3257 speed_str = "Unk";
3258 break;
3259 }
b59fb6fd
AV		 3260 seq_printf(m, "%X:%s ", i, speed_str);
3261 if (i == 7)
2f979427 3262 seq_puts(m, "\n ");
51219358
MW		 3263 sdtr_speed >>= 4;
3264 }
f50332ff 3265 seq_putc(m, '\n');
51219358 3266 }
1da177e4
LT		 3267}
3268
3269/*
51219358 3270 * asc_prt_driver_conf()
1da177e4 3271 */
b59fb6fd 3272static void asc_prt_driver_conf(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 3273{
d2411495 3274 struct asc_board *boardp = shost_priv(shost);
51219358 3275 int chip_scsi_id;
27c868c2 3276
b59fb6fd
AV		 3277 seq_printf(m,
3278 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
3279 shost->host_no);
27c868c2 3280
b59fb6fd 3281 seq_printf(m,
1abf635d 3282 " host_busy %u, max_id %u, max_lun %llu, max_channel %u\n",
74665016 3283 atomic_read(&shost->host_busy), shost->max_id,
b59fb6fd 3284 shost->max_lun, shost->max_channel);
95c9f162 3285
b59fb6fd
AV		 3286 seq_printf(m,
3287 " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
3288 shost->unique_id, shost->can_queue, shost->this_id,
3289 shost->sg_tablesize, shost->cmd_per_lun);
95c9f162 3290
b59fb6fd
AV		 3291 seq_printf(m,
3292 " unchecked_isa_dma %d, use_clustering %d\n",
3293 shost->unchecked_isa_dma, shost->use_clustering);
95c9f162 3294
b59fb6fd 3295 seq_printf(m,
31491e1a 3296 " flags 0x%x, last_reset 0x%lx, jiffies 0x%lx, asc_n_io_port 0x%x\n",
eac0b0c7 3297 boardp->flags, shost->last_reset, jiffies,
b59fb6fd 3298 boardp->asc_n_io_port);
27c868c2 3299
31491e1a 3300 seq_printf(m, " io_port 0x%lx\n", shost->io_port);
27c868c2 3301
51219358
MW		 3302 if (ASC_NARROW_BOARD(boardp)) {
3303 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
3304 } else {
3305 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
27c868c2 3306 }
1da177e4
LT		 3307}
3308
3309/*
51219358 3310 * asc_prt_asc_board_info()
1da177e4 3311 *
51219358 3312 * Print dynamic board configuration information.
1da177e4 3313 */
b59fb6fd 3314static void asc_prt_asc_board_info(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 3315{
d2411495 3316 struct asc_board *boardp = shost_priv(shost);
51219358 3317 int chip_scsi_id;
51219358
MW		 3318 ASC_DVC_VAR *v;
3319 ASC_DVC_CFG *c;
3320 int i;
3321 int renegotiate = 0;
27c868c2 3322
51219358
MW		 3323 v = &boardp->dvc_var.asc_dvc_var;
3324 c = &boardp->dvc_cfg.asc_dvc_cfg;
3325 chip_scsi_id = c->chip_scsi_id;
27c868c2 3326
b59fb6fd
AV		 3327 seq_printf(m,
3328 "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3329 shost->host_no);
27c868c2 3330
b59fb6fd
AV		 3331 seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3332 "mcode_version 0x%x, err_code %u\n",
3333 c->chip_version, c->mcode_date, c->mcode_version,
3334 v->err_code);
1da177e4 3335
51219358 3336 /* Current number of commands waiting for the host. */
b59fb6fd
AV		 3337 seq_printf(m,
3338 " Total Command Pending: %d\n", v->cur_total_qng);
1da177e4 3339
2f979427 3340 seq_puts(m, " Command Queuing:");
51219358
MW		 3341 for (i = 0; i <= ASC_MAX_TID; i++) {
3342 if ((chip_scsi_id == i) ||
3343 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3344 continue;
27c868c2 3345 }
b59fb6fd
AV		 3346 seq_printf(m, " %X:%c",
3347 i,
3348 (v->use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
51219358 3349 }
27c868c2 3350
51219358 3351 /* Current number of commands waiting for a device. */
3d30079c 3352 seq_puts(m, "\n Command Queue Pending:");
51219358
MW		 3353 for (i = 0; i <= ASC_MAX_TID; i++) {
3354 if ((chip_scsi_id == i) ||
3355 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3356 continue;
27c868c2 3357 }
b59fb6fd 3358 seq_printf(m, " %X:%u", i, v->cur_dvc_qng[i]);
27c868c2 3359 }
1da177e4 3360
51219358 3361 /* Current limit on number of commands that can be sent to a device. */
3d30079c 3362 seq_puts(m, "\n Command Queue Limit:");
51219358
MW		 3363 for (i = 0; i <= ASC_MAX_TID; i++) {
3364 if ((chip_scsi_id == i) ||
3365 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3366 continue;
3367 }
b59fb6fd 3368 seq_printf(m, " %X:%u", i, v->max_dvc_qng[i]);
27c868c2 3369 }
1da177e4 3370
51219358 3371 /* Indicate whether the device has returned queue full status. */
3d30079c 3372 seq_puts(m, "\n Command Queue Full:");
51219358
MW		 3373 for (i = 0; i <= ASC_MAX_TID; i++) {
3374 if ((chip_scsi_id == i) ||
3375 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3376 continue;
3377 }
b59fb6fd
AV		 3378 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i))
3379 seq_printf(m, " %X:Y-%d",
3380 i, boardp->queue_full_cnt[i]);
3381 else
3382 seq_printf(m, " %X:N", i);
51219358 3383 }
1da177e4 3384
3d30079c 3385 seq_puts(m, "\n Synchronous Transfer:");
51219358
MW		 3386 for (i = 0; i <= ASC_MAX_TID; i++) {
3387 if ((chip_scsi_id == i) ||
3388 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3389 continue;
3390 }
b59fb6fd
AV		 3391 seq_printf(m, " %X:%c",
3392 i,
3393 (v->sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
27c868c2 3394 }
f50332ff 3395 seq_putc(m, '\n');
1da177e4 3396
51219358
MW		 3397 for (i = 0; i <= ASC_MAX_TID; i++) {
3398 uchar syn_period_ix;
1da177e4 3399
51219358
MW		 3400 if ((chip_scsi_id == i) ||
3401 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3402 ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
3403 continue;
27c868c2 3404 }
27c868c2 3405
b59fb6fd 3406 seq_printf(m, " %X:", i);
27c868c2 3407
51219358 3408 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
2f979427 3409 seq_puts(m, " Asynchronous");
51219358
MW		 3410 } else {
3411 syn_period_ix =
3412 (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
3413 1);
27c868c2 3414
b59fb6fd
AV		 3415 seq_printf(m,
3416 " Transfer Period Factor: %d (%d.%d Mhz),",
3417 v->sdtr_period_tbl[syn_period_ix],
3418 250 / v->sdtr_period_tbl[syn_period_ix],
3419 ASC_TENTHS(250,
3420 v->sdtr_period_tbl[syn_period_ix]));
27c868c2 3421
b59fb6fd
AV		 3422 seq_printf(m, " REQ/ACK Offset: %d",
3423 boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET);
51219358 3424 }
1da177e4 3425
51219358 3426 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
2f979427 3427 seq_puts(m, "*\n");
51219358
MW		 3428 renegotiate = 1;
3429 } else {
f50332ff 3430 seq_putc(m, '\n');
51219358 3431 }
27c868c2 3432 }
1da177e4 3433
51219358 3434 if (renegotiate) {
2f979427 3435 seq_puts(m, " * = Re-negotiation pending before next command.\n");
27c868c2 3436 }
1da177e4
LT		 3437}
3438
1da177e4 3439/*
51219358 3440 * asc_prt_adv_board_info()
1da177e4 3441 *
51219358 3442 * Print dynamic board configuration information.
1da177e4 3443 */
b59fb6fd 3444static void asc_prt_adv_board_info(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 3445{
d2411495 3446 struct asc_board *boardp = shost_priv(shost);
27c868c2 3447 int i;
51219358
MW		 3448 ADV_DVC_VAR *v;
3449 ADV_DVC_CFG *c;
3450 AdvPortAddr iop_base;
3451 ushort chip_scsi_id;
3452 ushort lramword;
3453 uchar lrambyte;
3454 ushort tagqng_able;
3455 ushort sdtr_able, wdtr_able;
3456 ushort wdtr_done, sdtr_done;
3457 ushort period = 0;
3458 int renegotiate = 0;
27c868c2 3459
51219358
MW		 3460 v = &boardp->dvc_var.adv_dvc_var;
3461 c = &boardp->dvc_cfg.adv_dvc_cfg;
3462 iop_base = v->iop_base;
3463 chip_scsi_id = v->chip_scsi_id;
3464
b59fb6fd
AV		 3465 seq_printf(m,
3466 "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3467 shost->host_no);
27c868c2 3468
b59fb6fd
AV		 3469 seq_printf(m,
3470 " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
31491e1a 3471 (unsigned long)v->iop_base,
b59fb6fd
AV		 3472 AdvReadWordRegister(iop_base,IOPW_SCSI_CFG1) & CABLE_DETECT,
3473 v->err_code);
1da177e4 3474
b59fb6fd
AV		 3475 seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3476 "mcode_version 0x%x\n", c->chip_version,
3477 c->mcode_date, c->mcode_version);
51219358
MW		 3478
3479 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
2f979427 3480 seq_puts(m, " Queuing Enabled:");
27c868c2 3481 for (i = 0; i <= ADV_MAX_TID; i++) {
51219358
MW		 3482 if ((chip_scsi_id == i) ||
3483 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3484 continue;
27c868c2 3485 }
51219358 3486
b59fb6fd
AV		 3487 seq_printf(m, " %X:%c",
3488 i,
3489 (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
27c868c2 3490 }
1da177e4 3491
3d30079c 3492 seq_puts(m, "\n Queue Limit:");
51219358
MW		 3493 for (i = 0; i <= ADV_MAX_TID; i++) {
3494 if ((chip_scsi_id == i) ||
3495 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3496 continue;
3497 }
1da177e4 3498
51219358
MW		 3499 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
3500 lrambyte);
27c868c2 3501
b59fb6fd 3502 seq_printf(m, " %X:%d", i, lrambyte);
51219358 3503 }
27c868c2 3504
3d30079c 3505 seq_puts(m, "\n Command Pending:");
51219358
MW		 3506 for (i = 0; i <= ADV_MAX_TID; i++) {
3507 if ((chip_scsi_id == i) ||
3508 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3509 continue;
3510 }
27c868c2 3511
51219358
MW		 3512 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
3513 lrambyte);
1da177e4 3514
b59fb6fd 3515 seq_printf(m, " %X:%d", i, lrambyte);
51219358 3516 }
f50332ff 3517 seq_putc(m, '\n');
1da177e4 3518
51219358 3519 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
2f979427 3520 seq_puts(m, " Wide Enabled:");
51219358
MW		 3521 for (i = 0; i <= ADV_MAX_TID; i++) {
3522 if ((chip_scsi_id == i) ||
3523 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3524 continue;
27c868c2 3525 }
51219358 3526
b59fb6fd
AV		 3527 seq_printf(m, " %X:%c",
3528 i,
3529 (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
27c868c2 3530 }
f50332ff 3531 seq_putc(m, '\n');
1da177e4 3532
51219358 3533 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
2f979427 3534 seq_puts(m, " Transfer Bit Width:");
51219358
MW		 3535 for (i = 0; i <= ADV_MAX_TID; i++) {
3536 if ((chip_scsi_id == i) ||
3537 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3538 continue;
3539 }
1da177e4 3540
51219358
MW		 3541 AdvReadWordLram(iop_base,
3542 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3543 lramword);
27c868c2 3544
b59fb6fd
AV		 3545 seq_printf(m, " %X:%d",
3546 i, (lramword & 0x8000) ? 16 : 8);
27c868c2 3547
51219358
MW		 3548 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
3549 (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
f50332ff 3550 seq_putc(m, '*');
51219358 3551 renegotiate = 1;
27c868c2 3552 }
51219358 3553 }
f50332ff 3554 seq_putc(m, '\n');
27c868c2 3555
51219358 3556 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
2f979427 3557 seq_puts(m, " Synchronous Enabled:");
51219358
MW		 3558 for (i = 0; i <= ADV_MAX_TID; i++) {
3559 if ((chip_scsi_id == i) ||
3560 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3561 continue;
3562 }
27c868c2 3563
b59fb6fd
AV		 3564 seq_printf(m, " %X:%c",
3565 i,
3566 (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
51219358 3567 }
f50332ff 3568 seq_putc(m, '\n');
27c868c2 3569
51219358
MW		 3570 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
3571 for (i = 0; i <= ADV_MAX_TID; i++) {
27c868c2 3572
51219358
MW		 3573 AdvReadWordLram(iop_base,
3574 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3575 lramword);
3576 lramword &= ~0x8000;
27c868c2 3577
51219358
MW		 3578 if ((chip_scsi_id == i) ||
3579 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3580 ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
3581 continue;
27c868c2
MW		 3582 }
3583
b59fb6fd 3584 seq_printf(m, " %X:", i);
27c868c2 3585
51219358 3586 if ((lramword & 0x1F) == 0) { /* Check for REQ/ACK Offset 0. */
2f979427 3587 seq_puts(m, " Asynchronous");
51219358 3588 } else {
2f979427 3589 seq_puts(m, " Transfer Period Factor: ");
27c868c2 3590
51219358 3591 if ((lramword & 0x1F00) == 0x1100) { /* 80 Mhz */
2f979427 3592 seq_puts(m, "9 (80.0 Mhz),");
51219358 3593 } else if ((lramword & 0x1F00) == 0x1000) { /* 40 Mhz */
2f979427 3594 seq_puts(m, "10 (40.0 Mhz),");
51219358 3595 } else { /* 20 Mhz or below. */
27c868c2 3596
51219358
MW		 3597 period = (((lramword >> 8) * 25) + 50) / 4;
3598
3599 if (period == 0) { /* Should never happen. */
31491e1a 3600 seq_printf(m, "%d (? Mhz), ", period);
51219358 3601 } else {
b59fb6fd
AV		 3602 seq_printf(m,
3603 "%d (%d.%d Mhz),",
3604 period, 250 / period,
3605 ASC_TENTHS(250, period));
51219358
MW		 3606 }
3607 }
3608
b59fb6fd
AV		 3609 seq_printf(m, " REQ/ACK Offset: %d",
3610 lramword & 0x1F);
51219358
MW		 3611 }
3612
3613 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
2f979427 3614 seq_puts(m, "*\n");
51219358
MW		 3615 renegotiate = 1;
3616 } else {
f50332ff 3617 seq_putc(m, '\n');
51219358 3618 }
27c868c2 3619 }
51219358
MW		 3620
3621 if (renegotiate) {
2f979427 3622 seq_puts(m, " * = Re-negotiation pending before next command.\n");
51219358 3623 }
51219358
MW		 3624}
3625
3626#ifdef ADVANSYS_STATS
3627/*
3628 * asc_prt_board_stats()
1da177e4 3629 */
b59fb6fd 3630static void asc_prt_board_stats(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 3631{
d2411495
MW		 3632 struct asc_board *boardp = shost_priv(shost);
3633 struct asc_stats *s = &boardp->asc_stats;
27c868c2 3634
b59fb6fd
AV		 3635 seq_printf(m,
3636 "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
3637 shost->host_no);
51219358 3638
b59fb6fd 3639 seq_printf(m,
31491e1a 3640 " queuecommand %u, reset %u, biosparam %u, interrupt %u\n",
b59fb6fd
AV		 3641 s->queuecommand, s->reset, s->biosparam,
3642 s->interrupt);
27c868c2 3643
b59fb6fd 3644 seq_printf(m,
31491e1a 3645 " callback %u, done %u, build_error %u, build_noreq %u, build_nosg %u\n",
b59fb6fd
AV		 3646 s->callback, s->done, s->build_error,
3647 s->adv_build_noreq, s->adv_build_nosg);
27c868c2 3648
b59fb6fd 3649 seq_printf(m,
31491e1a 3650 " exe_noerror %u, exe_busy %u, exe_error %u, exe_unknown %u\n",
b59fb6fd
AV		 3651 s->exe_noerror, s->exe_busy, s->exe_error,
3652 s->exe_unknown);
51219358
MW		 3653
3654 /*
3655 * Display data transfer statistics.
3656 */
52c334e9 3657 if (s->xfer_cnt > 0) {
31491e1a 3658 seq_printf(m, " xfer_cnt %u, xfer_elem %u, ",
b59fb6fd 3659 s->xfer_cnt, s->xfer_elem);
27c868c2 3660
31491e1a 3661 seq_printf(m, "xfer_bytes %u.%01u kb\n",
b59fb6fd 3662 s->xfer_sect / 2, ASC_TENTHS(s->xfer_sect, 2));
1da177e4 3663
51219358 3664 /* Scatter gather transfer statistics */
31491e1a 3665 seq_printf(m, " avg_num_elem %u.%01u, ",
b59fb6fd
AV		 3666 s->xfer_elem / s->xfer_cnt,
3667 ASC_TENTHS(s->xfer_elem, s->xfer_cnt));
51219358 3668
31491e1a 3669 seq_printf(m, "avg_elem_size %u.%01u kb, ",
b59fb6fd
AV		 3670 (s->xfer_sect / 2) / s->xfer_elem,
3671 ASC_TENTHS((s->xfer_sect / 2), s->xfer_elem));
51219358 3672
31491e1a 3673 seq_printf(m, "avg_xfer_size %u.%01u kb\n",
b59fb6fd
AV		 3674 (s->xfer_sect / 2) / s->xfer_cnt,
3675 ASC_TENTHS((s->xfer_sect / 2), s->xfer_cnt));
27c868c2 3676 }
1da177e4 3677}
51219358 3678#endif /* ADVANSYS_STATS */
1da177e4
LT		 3679
3680/*
b59fb6fd 3681 * advansys_show_info() - /proc/scsi/advansys/{0,1,2,3,...}
1da177e4 3682 *
b59fb6fd
AV		 3683 * m: seq_file to print into
3684 * shost: Scsi_Host
1da177e4 3685 *
51219358
MW		 3686 * Return the number of bytes read from or written to a
3687 * /proc/scsi/advansys/[0...] file.
1da177e4 3688 */
51219358 3689static int
b59fb6fd 3690advansys_show_info(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 3691{
d2411495 3692 struct asc_board *boardp = shost_priv(shost);
27c868c2 3693
b352f923 3694 ASC_DBG(1, "begin\n");
51219358 3695
51219358
MW		 3696 /*
3697 * User read of /proc/scsi/advansys/[0...] file.
3698 */
1da177e4 3699
51219358
MW		 3700 /*
3701 * Get board configuration information.
3702 *
3703 * advansys_info() returns the board string from its own static buffer.
3704 */
51219358 3705 /* Copy board information. */
b59fb6fd 3706 seq_printf(m, "%s\n", (char *)advansys_info(shost));
51219358
MW		 3707 /*
3708 * Display Wide Board BIOS Information.
3709 */
b59fb6fd
AV		 3710 if (!ASC_NARROW_BOARD(boardp))
3711 asc_prt_adv_bios(m, shost);
1da177e4 3712
51219358
MW		 3713 /*
3714 * Display driver information for each device attached to the board.
3715 */
b59fb6fd 3716 asc_prt_board_devices(m, shost);
51219358
MW		 3717
3718 /*
3719 * Display EEPROM configuration for the board.
3720 */
b59fb6fd
AV		 3721 if (ASC_NARROW_BOARD(boardp))
3722 asc_prt_asc_board_eeprom(m, shost);
3723 else
3724 asc_prt_adv_board_eeprom(m, shost);
1da177e4 3725
51219358
MW		 3726 /*
3727 * Display driver configuration and information for the board.
3728 */
b59fb6fd 3729 asc_prt_driver_conf(m, shost);
1da177e4 3730
51219358
MW		 3731#ifdef ADVANSYS_STATS
3732 /*
3733 * Display driver statistics for the board.
3734 */
b59fb6fd 3735 asc_prt_board_stats(m, shost);
51219358 3736#endif /* ADVANSYS_STATS */
1da177e4 3737
51219358
MW		 3738 /*
3739 * Display Asc Library dynamic configuration information
3740 * for the board.
3741 */
b59fb6fd
AV		 3742 if (ASC_NARROW_BOARD(boardp))
3743 asc_prt_asc_board_info(m, shost);
3744 else
3745 asc_prt_adv_board_info(m, shost);
3746 return 0;
51219358
MW		 3747}
3748#endif /* CONFIG_PROC_FS */
3749
3750static void asc_scsi_done(struct scsi_cmnd *scp)
3751{
52c334e9 3752 scsi_dma_unmap(scp);
51219358 3753 ASC_STATS(scp->device->host, done);
51219358
MW		 3754 scp->scsi_done(scp);
3755}
3756
3757static void AscSetBank(PortAddr iop_base, uchar bank)
3758{
3759 uchar val;
3760
3761 val = AscGetChipControl(iop_base) &
3762 (~
3763 (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
3764 CC_CHIP_RESET));
3765 if (bank == 1) {
3766 val |= CC_BANK_ONE;
3767 } else if (bank == 2) {
3768 val |= CC_DIAG | CC_BANK_ONE;
27c868c2 3769 } else {
51219358 3770 val &= ~CC_BANK_ONE;
27c868c2 3771 }
51219358 3772 AscSetChipControl(iop_base, val);
51219358
MW		 3773}
3774
3775static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
3776{
3777 AscSetBank(iop_base, 1);
3778 AscWriteChipIH(iop_base, ins_code);
3779 AscSetBank(iop_base, 0);
51219358
MW		 3780}
3781
3782static int AscStartChip(PortAddr iop_base)
3783{
3784 AscSetChipControl(iop_base, 0);
3785 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3786 return (0);
27c868c2 3787 }
51219358
MW		 3788 return (1);
3789}
27c868c2 3790
51219358
MW		 3791static int AscStopChip(PortAddr iop_base)
3792{
3793 uchar cc_val;
3794
3795 cc_val =
3796 AscGetChipControl(iop_base) &
3797 (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
3798 AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
3799 AscSetChipIH(iop_base, INS_HALT);
3800 AscSetChipIH(iop_base, INS_RFLAG_WTM);
3801 if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
3802 return (0);
27c868c2 3803 }
51219358
MW		 3804 return (1);
3805}
27c868c2 3806
51219358
MW		 3807static int AscIsChipHalted(PortAddr iop_base)
3808{
3809 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3810 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
3811 return (1);
27c868c2 3812 }
27c868c2 3813 }
51219358
MW		 3814 return (0);
3815}
27c868c2 3816
51219358
MW		 3817static int AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
3818{
3819 PortAddr iop_base;
3820 int i = 10;
3821
3822 iop_base = asc_dvc->iop_base;
3823 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
3824 && (i-- > 0)) {
3825 mdelay(100);
27c868c2 3826 }
51219358
MW		 3827 AscStopChip(iop_base);
3828 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
3829 udelay(60);
3830 AscSetChipIH(iop_base, INS_RFLAG_WTM);
3831 AscSetChipIH(iop_base, INS_HALT);
3832 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
3833 AscSetChipControl(iop_base, CC_HALT);
3834 mdelay(200);
3835 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
3836 AscSetChipStatus(iop_base, 0);
3837 return (AscIsChipHalted(iop_base));
3838}
27c868c2 3839
51219358
MW		 3840static int AscFindSignature(PortAddr iop_base)
3841{
3842 ushort sig_word;
27c868c2 3843
b352f923 3844 ASC_DBG(1, "AscGetChipSignatureByte(0x%x) 0x%x\n",
51219358
MW		 3845 iop_base, AscGetChipSignatureByte(iop_base));
3846 if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
b352f923 3847 ASC_DBG(1, "AscGetChipSignatureWord(0x%x) 0x%x\n",
51219358
MW		 3848 iop_base, AscGetChipSignatureWord(iop_base));
3849 sig_word = AscGetChipSignatureWord(iop_base);
3850 if ((sig_word == (ushort)ASC_1000_ID0W) ||
3851 (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
3852 return (1);
27c868c2 3853 }
27c868c2 3854 }
51219358 3855 return (0);
27c868c2
MW		 3856}
3857
51219358 3858static void AscEnableInterrupt(PortAddr iop_base)
1da177e4 3859{
51219358 3860 ushort cfg;
27c868c2 3861
51219358
MW		 3862 cfg = AscGetChipCfgLsw(iop_base);
3863 AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
51219358 3864}
27c868c2 3865
51219358
MW		 3866static void AscDisableInterrupt(PortAddr iop_base)
3867{
3868 ushort cfg;
27c868c2 3869
51219358
MW		 3870 cfg = AscGetChipCfgLsw(iop_base);
3871 AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
51219358 3872}
27c868c2 3873
51219358
MW		 3874static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
3875{
3876 unsigned char byte_data;
3877 unsigned short word_data;
27c868c2 3878
51219358
MW		 3879 if (isodd_word(addr)) {
3880 AscSetChipLramAddr(iop_base, addr - 1);
3881 word_data = AscGetChipLramData(iop_base);
3882 byte_data = (word_data >> 8) & 0xFF;
3883 } else {
3884 AscSetChipLramAddr(iop_base, addr);
3885 word_data = AscGetChipLramData(iop_base);
3886 byte_data = word_data & 0xFF;
3887 }
3888 return byte_data;
3889}
27c868c2 3890
51219358
MW		 3891static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
3892{
3893 ushort word_data;
27c868c2 3894
51219358
MW		 3895 AscSetChipLramAddr(iop_base, addr);
3896 word_data = AscGetChipLramData(iop_base);
3897 return (word_data);
3898}
27c868c2 3899
51219358
MW		 3900#if CC_VERY_LONG_SG_LIST
3901static ASC_DCNT AscReadLramDWord(PortAddr iop_base, ushort addr)
3902{
3903 ushort val_low, val_high;
3904 ASC_DCNT dword_data;
27c868c2 3905
51219358
MW		 3906 AscSetChipLramAddr(iop_base, addr);
3907 val_low = AscGetChipLramData(iop_base);
3908 val_high = AscGetChipLramData(iop_base);
3909 dword_data = ((ASC_DCNT) val_high << 16) | (ASC_DCNT) val_low;
3910 return (dword_data);
3911}
3912#endif /* CC_VERY_LONG_SG_LIST */
3913
3914static void
3915AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
3916{
3917 int i;
3918
3919 AscSetChipLramAddr(iop_base, s_addr);
3920 for (i = 0; i < words; i++) {
3921 AscSetChipLramData(iop_base, set_wval);
27c868c2 3922 }
51219358 3923}
1da177e4 3924
51219358
MW		 3925static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
3926{
3927 AscSetChipLramAddr(iop_base, addr);
3928 AscSetChipLramData(iop_base, word_val);
51219358
MW		 3929}
3930
3931static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
3932{
3933 ushort word_data;
3934
3935 if (isodd_word(addr)) {
3936 addr--;
3937 word_data = AscReadLramWord(iop_base, addr);
3938 word_data &= 0x00FF;
3939 word_data |= (((ushort)byte_val << 8) & 0xFF00);
3940 } else {
3941 word_data = AscReadLramWord(iop_base, addr);
3942 word_data &= 0xFF00;
3943 word_data |= ((ushort)byte_val & 0x00FF);
3944 }
3945 AscWriteLramWord(iop_base, addr, word_data);
1da177e4
LT		 3946}
3947
3948/*
51219358 3949 * Copy 2 bytes to LRAM.
1da177e4 3950 *
51219358
MW		 3951 * The source data is assumed to be in little-endian order in memory
3952 * and is maintained in little-endian order when written to LRAM.
1da177e4 3953 */
51219358 3954static void
989bb5f5
JSR		 3955AscMemWordCopyPtrToLram(PortAddr iop_base, ushort s_addr,
3956 const uchar *s_buffer, int words)
1da177e4 3957{
27c868c2 3958 int i;
27c868c2 3959
51219358
MW		 3960 AscSetChipLramAddr(iop_base, s_addr);
3961 for (i = 0; i < 2 * words; i += 2) {
3962 /*
3963 * On a little-endian system the second argument below
3964 * produces a little-endian ushort which is written to
3965 * LRAM in little-endian order. On a big-endian system
3966 * the second argument produces a big-endian ushort which
3967 * is "transparently" byte-swapped by outpw() and written
3968 * in little-endian order to LRAM.
3969 */
3970 outpw(iop_base + IOP_RAM_DATA,
3971 ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
3972 }
51219358 3973}
27c868c2 3974
51219358
MW		 3975/*
3976 * Copy 4 bytes to LRAM.
3977 *
3978 * The source data is assumed to be in little-endian order in memory
25985edc 3979 * and is maintained in little-endian order when written to LRAM.
51219358
MW		 3980 */
3981static void
3982AscMemDWordCopyPtrToLram(PortAddr iop_base,
3983 ushort s_addr, uchar *s_buffer, int dwords)
3984{
3985 int i;
27c868c2 3986
51219358
MW		 3987 AscSetChipLramAddr(iop_base, s_addr);
3988 for (i = 0; i < 4 * dwords; i += 4) {
3989 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */
3990 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */
3991 }
51219358 3992}
27c868c2 3993
51219358
MW		 3994/*
3995 * Copy 2 bytes from LRAM.
3996 *
3997 * The source data is assumed to be in little-endian order in LRAM
3998 * and is maintained in little-endian order when written to memory.
3999 */
4000static void
4001AscMemWordCopyPtrFromLram(PortAddr iop_base,
4002 ushort s_addr, uchar *d_buffer, int words)
4003{
4004 int i;
4005 ushort word;
27c868c2 4006
51219358
MW		 4007 AscSetChipLramAddr(iop_base, s_addr);
4008 for (i = 0; i < 2 * words; i += 2) {
4009 word = inpw(iop_base + IOP_RAM_DATA);
4010 d_buffer[i] = word & 0xff;
4011 d_buffer[i + 1] = (word >> 8) & 0xff;
27c868c2 4012 }
51219358 4013}
27c868c2 4014
51219358
MW		 4015static ASC_DCNT AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
4016{
4017 ASC_DCNT sum;
4018 int i;
27c868c2 4019
51219358
MW		 4020 sum = 0L;
4021 for (i = 0; i < words; i++, s_addr += 2) {
4022 sum += AscReadLramWord(iop_base, s_addr);
27c868c2 4023 }
51219358
MW		 4024 return (sum);
4025}
27c868c2 4026
51219358
MW		 4027static ushort AscInitLram(ASC_DVC_VAR *asc_dvc)
4028{
4029 uchar i;
4030 ushort s_addr;
4031 PortAddr iop_base;
4032 ushort warn_code;
27c868c2 4033
51219358
MW		 4034 iop_base = asc_dvc->iop_base;
4035 warn_code = 0;
4036 AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
4037 (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
4038 64) >> 1));
4039 i = ASC_MIN_ACTIVE_QNO;
4040 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
4041 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4042 (uchar)(i + 1));
4043 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4044 (uchar)(asc_dvc->max_total_qng));
4045 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4046 (uchar)i);
4047 i++;
4048 s_addr += ASC_QBLK_SIZE;
4049 for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
4050 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4051 (uchar)(i + 1));
4052 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4053 (uchar)(i - 1));
4054 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4055 (uchar)i);
27c868c2 4056 }
51219358
MW		 4057 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4058 (uchar)ASC_QLINK_END);
4059 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4060 (uchar)(asc_dvc->max_total_qng - 1));
4061 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4062 (uchar)asc_dvc->max_total_qng);
4063 i++;
4064 s_addr += ASC_QBLK_SIZE;
4065 for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
4066 i++, s_addr += ASC_QBLK_SIZE) {
4067 AscWriteLramByte(iop_base,
4068 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
4069 AscWriteLramByte(iop_base,
4070 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
4071 AscWriteLramByte(iop_base,
4072 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
27c868c2 4073 }
51219358 4074 return warn_code;
1da177e4
LT		 4075}
4076
51219358 4077static ASC_DCNT
989bb5f5
JSR		 4078AscLoadMicroCode(PortAddr iop_base, ushort s_addr,
4079 const uchar *mcode_buf, ushort mcode_size)
1da177e4 4080{
51219358
MW		 4081 ASC_DCNT chksum;
4082 ushort mcode_word_size;
4083 ushort mcode_chksum;
27c868c2 4084
51219358
MW		 4085 /* Write the microcode buffer starting at LRAM address 0. */
4086 mcode_word_size = (ushort)(mcode_size >> 1);
4087 AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
4088 AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
27c868c2 4089
51219358 4090 chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
b352f923 4091 ASC_DBG(1, "chksum 0x%lx\n", (ulong)chksum);
51219358
MW		 4092 mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
4093 (ushort)ASC_CODE_SEC_BEG,
4094 (ushort)((mcode_size -
4095 s_addr - (ushort)
4096 ASC_CODE_SEC_BEG) /
4097 2));
b352f923 4098 ASC_DBG(1, "mcode_chksum 0x%lx\n", (ulong)mcode_chksum);
51219358
MW		 4099 AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
4100 AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
b352f923 4101 return chksum;
51219358 4102}
27c868c2 4103
51219358
MW		 4104static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
4105{
4106 PortAddr iop_base;
4107 int i;
4108 ushort lram_addr;
4109
4110 iop_base = asc_dvc->iop_base;
4111 AscPutRiscVarFreeQHead(iop_base, 1);
4112 AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4113 AscPutVarFreeQHead(iop_base, 1);
4114 AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4115 AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
4116 (uchar)((int)asc_dvc->max_total_qng + 1));
4117 AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
4118 (uchar)((int)asc_dvc->max_total_qng + 2));
4119 AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
4120 asc_dvc->max_total_qng);
4121 AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
4122 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
4123 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
4124 AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
4125 AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
4126 AscPutQDoneInProgress(iop_base, 0);
4127 lram_addr = ASC_QADR_BEG;
4128 for (i = 0; i < 32; i++, lram_addr += 2) {
4129 AscWriteLramWord(iop_base, lram_addr, 0);
4130 }
4131}
4132
4133static ushort AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
4134{
4135 int i;
4136 ushort warn_code;
4137 PortAddr iop_base;
4138 ASC_PADDR phy_addr;
4139 ASC_DCNT phy_size;
d10fb2c7 4140 struct asc_board *board = asc_dvc_to_board(asc_dvc);
51219358
MW		 4141
4142 iop_base = asc_dvc->iop_base;
4143 warn_code = 0;
4144 for (i = 0; i <= ASC_MAX_TID; i++) {
4145 AscPutMCodeInitSDTRAtID(iop_base, i,
4146 asc_dvc->cfg->sdtr_period_offset[i]);
4147 }
4148
4149 AscInitQLinkVar(asc_dvc);
4150 AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
4151 asc_dvc->cfg->disc_enable);
4152 AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
4153 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
4154
d10fb2c7
MW		 4155 /* Ensure overrun buffer is aligned on an 8 byte boundary. */
4156 BUG_ON((unsigned long)asc_dvc->overrun_buf & 7);
4157 asc_dvc->overrun_dma = dma_map_single(board->dev, asc_dvc->overrun_buf,
4158 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
9a908c1a
HRK		 4159 if (dma_mapping_error(board->dev, asc_dvc->overrun_dma)) {
4160 warn_code = -ENOMEM;
4161 goto err_dma_map;
4162 }
d10fb2c7 4163 phy_addr = cpu_to_le32(asc_dvc->overrun_dma);
51219358
MW		 4164 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
4165 (uchar *)&phy_addr, 1);
d10fb2c7 4166 phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE);
51219358
MW		 4167 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
4168 (uchar *)&phy_size, 1);
4169
4170 asc_dvc->cfg->mcode_date =
4171 AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
4172 asc_dvc->cfg->mcode_version =
4173 AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
4174
4175 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
4176 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
4177 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
9a908c1a
HRK		 4178 warn_code = UW_ERR;
4179 goto err_mcode_start;
51219358
MW		 4180 }
4181 if (AscStartChip(iop_base) != 1) {
4182 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
9a908c1a
HRK		 4183 warn_code = UW_ERR;
4184 goto err_mcode_start;
51219358
MW		 4185 }
4186
4187 return warn_code;
9a908c1a
HRK		 4188
4189err_mcode_start:
4190 dma_unmap_single(board->dev, asc_dvc->overrun_dma,
4191 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4192err_dma_map:
4193 asc_dvc->overrun_dma = 0;
4194 return warn_code;
51219358
MW		 4195}
4196
4197static ushort AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
4198{
989bb5f5
JSR		 4199 const struct firmware *fw;
4200 const char fwname[] = "advansys/mcode.bin";
4201 int err;
4202 unsigned long chksum;
51219358
MW		 4203 ushort warn_code;
4204 PortAddr iop_base;
4205
4206 iop_base = asc_dvc->iop_base;
4207 warn_code = 0;
4208 if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
4209 !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
4210 AscResetChipAndScsiBus(asc_dvc);
4211 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4212 }
4213 asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
4214 if (asc_dvc->err_code != 0)
4215 return UW_ERR;
4216 if (!AscFindSignature(asc_dvc->iop_base)) {
4217 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
4218 return warn_code;
4219 }
4220 AscDisableInterrupt(iop_base);
4221 warn_code |= AscInitLram(asc_dvc);
4222 if (asc_dvc->err_code != 0)
4223 return UW_ERR;
989bb5f5
JSR		 4224
4225 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4226 if (err) {
4227 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4228 fwname, err);
cf747445 4229 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 4230 return err;
4231 }
4232 if (fw->size < 4) {
4233 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4234 fw->size, fwname);
4235 release_firmware(fw);
cf747445 4236 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 4237 return -EINVAL;
4238 }
4239 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4240 (fw->data[1] << 8) | fw->data[0];
4241 ASC_DBG(1, "_asc_mcode_chksum 0x%lx\n", (ulong)chksum);
4242 if (AscLoadMicroCode(iop_base, 0, &fw->data[4],
4243 fw->size - 4) != chksum) {
51219358 4244 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
989bb5f5 4245 release_firmware(fw);
51219358
MW		 4246 return warn_code;
4247 }
989bb5f5 4248 release_firmware(fw);
51219358 4249 warn_code |= AscInitMicroCodeVar(asc_dvc);
9a908c1a
HRK		 4250 if (!asc_dvc->overrun_dma)
4251 return warn_code;
51219358
MW		 4252 asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
4253 AscEnableInterrupt(iop_base);
4254 return warn_code;
4255}
4256
4257/*
4258 * Load the Microcode
4259 *
4260 * Write the microcode image to RISC memory starting at address 0.
4261 *
4262 * The microcode is stored compressed in the following format:
4263 *
4264 * 254 word (508 byte) table indexed by byte code followed
4265 * by the following byte codes:
4266 *
4267 * 1-Byte Code:
4268 * 00: Emit word 0 in table.
4269 * 01: Emit word 1 in table.
4270 * .
4271 * FD: Emit word 253 in table.
4272 *
4273 * Multi-Byte Code:
4274 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
4275 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
4276 *
4277 * Returns 0 or an error if the checksum doesn't match
4278 */
989bb5f5
JSR		 4279static int AdvLoadMicrocode(AdvPortAddr iop_base, const unsigned char *buf,
4280 int size, int memsize, int chksum)
51219358
MW		 4281{
4282 int i, j, end, len = 0;
4283 ADV_DCNT sum;
4284
4285 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4286
4287 for (i = 253 * 2; i < size; i++) {
4288 if (buf[i] == 0xff) {
4289 unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
4290 for (j = 0; j < buf[i + 1]; j++) {
4291 AdvWriteWordAutoIncLram(iop_base, word);
4292 len += 2;
4293 }
4294 i += 3;
4295 } else if (buf[i] == 0xfe) {
4296 unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
4297 AdvWriteWordAutoIncLram(iop_base, word);
4298 i += 2;
4299 len += 2;
4300 } else {
951b62c1 4301 unsigned int off = buf[i] * 2;
51219358
MW		 4302 unsigned short word = (buf[off + 1] << 8) | buf[off];
4303 AdvWriteWordAutoIncLram(iop_base, word);
4304 len += 2;
4305 }
4306 }
4307
4308 end = len;
4309
4310 while (len < memsize) {
4311 AdvWriteWordAutoIncLram(iop_base, 0);
4312 len += 2;
4313 }
4314
4315 /* Verify the microcode checksum. */
4316 sum = 0;
4317 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4318
4319 for (len = 0; len < end; len += 2) {
4320 sum += AdvReadWordAutoIncLram(iop_base);
4321 }
4322
4323 if (sum != chksum)
4324 return ASC_IERR_MCODE_CHKSUM;
4325
4326 return 0;
4327}
4328
51219358
MW		 4329static void AdvBuildCarrierFreelist(struct adv_dvc_var *asc_dvc)
4330{
4331 ADV_CARR_T *carrp;
4332 ADV_SDCNT buf_size;
4333 ADV_PADDR carr_paddr;
4334
51219358
MW		 4335 carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
4336 asc_dvc->carr_freelist = NULL;
4337 if (carrp == asc_dvc->carrier_buf) {
4338 buf_size = ADV_CARRIER_BUFSIZE;
4339 } else {
4340 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
4341 }
4342
4343 do {
4344 /* Get physical address of the carrier 'carrp'. */
fd625f47 4345 carr_paddr = cpu_to_le32(virt_to_bus(carrp));
51219358
MW		 4346
4347 buf_size -= sizeof(ADV_CARR_T);
4348
51219358
MW		 4349 carrp->carr_pa = carr_paddr;
4350 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
4351
4352 /*
4353 * Insert the carrier at the beginning of the freelist.
4354 */
4355 carrp->next_vpa =
4356 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
4357 asc_dvc->carr_freelist = carrp;
4358
4359 carrp++;
4360 } while (buf_size > 0);
4361}
4362
4363/*
4364 * Send an idle command to the chip and wait for completion.
4365 *
4366 * Command completion is polled for once per microsecond.
4367 *
4368 * The function can be called from anywhere including an interrupt handler.
4369 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
4370 * functions to prevent reentrancy.
4371 *
4372 * Return Values:
4373 * ADV_TRUE - command completed successfully
4374 * ADV_FALSE - command failed
4375 * ADV_ERROR - command timed out
4376 */
4377static int
4378AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
4379 ushort idle_cmd, ADV_DCNT idle_cmd_parameter)
4380{
4381 int result;
4382 ADV_DCNT i, j;
4383 AdvPortAddr iop_base;
4384
4385 iop_base = asc_dvc->iop_base;
4386
4387 /*
4388 * Clear the idle command status which is set by the microcode
4389 * to a non-zero value to indicate when the command is completed.
4390 * The non-zero result is one of the IDLE_CMD_STATUS_* values
4391 */
4392 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
4393
4394 /*
4395 * Write the idle command value after the idle command parameter
4396 * has been written to avoid a race condition. If the order is not
4397 * followed, the microcode may process the idle command before the
4398 * parameters have been written to LRAM.
4399 */
4400 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
4401 cpu_to_le32(idle_cmd_parameter));
4402 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
4403
4404 /*
4405 * Tickle the RISC to tell it to process the idle command.
4406 */
4407 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
4408 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
4409 /*
4410 * Clear the tickle value. In the ASC-3550 the RISC flag
4411 * command 'clr_tickle_b' does not work unless the host
4412 * value is cleared.
4413 */
4414 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
4415 }
4416
4417 /* Wait for up to 100 millisecond for the idle command to timeout. */
4418 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
4419 /* Poll once each microsecond for command completion. */
4420 for (j = 0; j < SCSI_US_PER_MSEC; j++) {
4421 AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
4422 result);
4423 if (result != 0)
4424 return result;
4425 udelay(1);
4426 }
4427 }
4428
4429 BUG(); /* The idle command should never timeout. */
4430 return ADV_ERROR;
4431}
4432
4433/*
4434 * Reset SCSI Bus and purge all outstanding requests.
4435 *
4436 * Return Value:
4437 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset.
4438 * ADV_FALSE(0) - Microcode command failed.
4439 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
4440 * may be hung which requires driver recovery.
4441 */
4442static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
4443{
4444 int status;
4445
4446 /*
4447 * Send the SCSI Bus Reset idle start idle command which asserts
4448 * the SCSI Bus Reset signal.
4449 */
4450 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
4451 if (status != ADV_TRUE) {
4452 return status;
4453 }
4454
4455 /*
4456 * Delay for the specified SCSI Bus Reset hold time.
4457 *
4458 * The hold time delay is done on the host because the RISC has no
4459 * microsecond accurate timer.
4460 */
4461 udelay(ASC_SCSI_RESET_HOLD_TIME_US);
4462
4463 /*
4464 * Send the SCSI Bus Reset end idle command which de-asserts
4465 * the SCSI Bus Reset signal and purges any pending requests.
4466 */
4467 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
4468 if (status != ADV_TRUE) {
4469 return status;
4470 }
4471
4472 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4473
4474 return status;
4475}
4476
4477/*
4478 * Initialize the ASC-3550.
4479 *
4480 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4481 *
4482 * For a non-fatal error return a warning code. If there are no warnings
4483 * then 0 is returned.
4484 *
4485 * Needed after initialization for error recovery.
4486 */
4487static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
4488{
989bb5f5
JSR		 4489 const struct firmware *fw;
4490 const char fwname[] = "advansys/3550.bin";
51219358
MW		 4491 AdvPortAddr iop_base;
4492 ushort warn_code;
4493 int begin_addr;
4494 int end_addr;
4495 ushort code_sum;
4496 int word;
4497 int i;
989bb5f5
JSR		 4498 int err;
4499 unsigned long chksum;
51219358
MW		 4500 ushort scsi_cfg1;
4501 uchar tid;
4502 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
4503 ushort wdtr_able = 0, sdtr_able, tagqng_able;
4504 uchar max_cmd[ADV_MAX_TID + 1];
4505
4506 /* If there is already an error, don't continue. */
4507 if (asc_dvc->err_code != 0)
4508 return ADV_ERROR;
4509
4510 /*
4511 * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
4512 */
4513 if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
4514 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
4515 return ADV_ERROR;
4516 }
4517
4518 warn_code = 0;
4519 iop_base = asc_dvc->iop_base;
4520
4521 /*
4522 * Save the RISC memory BIOS region before writing the microcode.
4523 * The BIOS may already be loaded and using its RISC LRAM region
4524 * so its region must be saved and restored.
4525 *
4526 * Note: This code makes the assumption, which is currently true,
4527 * that a chip reset does not clear RISC LRAM.
4528 */
4529 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4530 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4531 bios_mem[i]);
4532 }
4533
4534 /*
4535 * Save current per TID negotiated values.
4536 */
4537 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) {
4538 ushort bios_version, major, minor;
4539
4540 bios_version =
4541 bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2];
4542 major = (bios_version >> 12) & 0xF;
4543 minor = (bios_version >> 8) & 0xF;
4544 if (major < 3 || (major == 3 && minor == 1)) {
4545 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
4546 AdvReadWordLram(iop_base, 0x120, wdtr_able);
4547 } else {
4548 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4549 }
4550 }
4551 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4552 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
4553 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4554 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
4555 max_cmd[tid]);
4556 }
4557
989bb5f5
JSR		 4558 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4559 if (err) {
4560 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4561 fwname, err);
cf747445 4562 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 4563 return err;
4564 }
4565 if (fw->size < 4) {
4566 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4567 fw->size, fwname);
4568 release_firmware(fw);
cf747445 4569 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 4570 return -EINVAL;
4571 }
4572 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4573 (fw->data[1] << 8) | fw->data[0];
4574 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
4575 fw->size - 4, ADV_3550_MEMSIZE,
4576 chksum);
4577 release_firmware(fw);
51219358
MW		 4578 if (asc_dvc->err_code)
4579 return ADV_ERROR;
4580
4581 /*
4582 * Restore the RISC memory BIOS region.
4583 */
4584 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4585 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4586 bios_mem[i]);
4587 }
4588
4589 /*
4590 * Calculate and write the microcode code checksum to the microcode
4591 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
4592 */
4593 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
4594 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
4595 code_sum = 0;
4596 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
4597 for (word = begin_addr; word < end_addr; word += 2) {
4598 code_sum += AdvReadWordAutoIncLram(iop_base);
4599 }
4600 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
4601
4602 /*
4603 * Read and save microcode version and date.
4604 */
4605 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
4606 asc_dvc->cfg->mcode_date);
4607 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
4608 asc_dvc->cfg->mcode_version);
4609
4610 /*
4611 * Set the chip type to indicate the ASC3550.
4612 */
4613 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
4614
4615 /*
4616 * If the PCI Configuration Command Register "Parity Error Response
4617 * Control" Bit was clear (0), then set the microcode variable
4618 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
4619 * to ignore DMA parity errors.
4620 */
4621 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
4622 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4623 word |= CONTROL_FLAG_IGNORE_PERR;
4624 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4625 }
4626
4627 /*
4628 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
4629 * threshold of 128 bytes. This register is only accessible to the host.
4630 */
4631 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
4632 START_CTL_EMFU | READ_CMD_MRM);
4633
4634 /*
4635 * Microcode operating variables for WDTR, SDTR, and command tag
4636 * queuing will be set in slave_configure() based on what a
4637 * device reports it is capable of in Inquiry byte 7.
4638 *
4639 * If SCSI Bus Resets have been disabled, then directly set
4640 * SDTR and WDTR from the EEPROM configuration. This will allow
4641 * the BIOS and warm boot to work without a SCSI bus hang on
4642 * the Inquiry caused by host and target mismatched DTR values.
4643 * Without the SCSI Bus Reset, before an Inquiry a device can't
4644 * be assumed to be in Asynchronous, Narrow mode.
4645 */
4646 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
4647 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
4648 asc_dvc->wdtr_able);
4649 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
4650 asc_dvc->sdtr_able);
4651 }
4652
4653 /*
4654 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
4655 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
4656 * bitmask. These values determine the maximum SDTR speed negotiated
4657 * with a device.
4658 *
4659 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
4660 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
4661 * without determining here whether the device supports SDTR.
4662 *
4663 * 4-bit speed SDTR speed name
4664 * =========== ===============
4665 * 0000b (0x0) SDTR disabled
4666 * 0001b (0x1) 5 Mhz
4667 * 0010b (0x2) 10 Mhz
4668 * 0011b (0x3) 20 Mhz (Ultra)
4669 * 0100b (0x4) 40 Mhz (LVD/Ultra2)
4670 * 0101b (0x5) 80 Mhz (LVD2/Ultra3)
4671 * 0110b (0x6) Undefined
4672 * .
4673 * 1111b (0xF) Undefined
4674 */
4675 word = 0;
4676 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4677 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) {
4678 /* Set Ultra speed for TID 'tid'. */
4679 word |= (0x3 << (4 * (tid % 4)));
4680 } else {
4681 /* Set Fast speed for TID 'tid'. */
4682 word |= (0x2 << (4 * (tid % 4)));
4683 }
4684 if (tid == 3) { /* Check if done with sdtr_speed1. */
4685 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
4686 word = 0;
4687 } else if (tid == 7) { /* Check if done with sdtr_speed2. */
4688 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
4689 word = 0;
4690 } else if (tid == 11) { /* Check if done with sdtr_speed3. */
4691 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
4692 word = 0;
4693 } else if (tid == 15) { /* Check if done with sdtr_speed4. */
4694 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
4695 /* End of loop. */
4696 }
4697 }
4698
4699 /*
4700 * Set microcode operating variable for the disconnect per TID bitmask.
4701 */
4702 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
4703 asc_dvc->cfg->disc_enable);
4704
4705 /*
4706 * Set SCSI_CFG0 Microcode Default Value.
4707 *
4708 * The microcode will set the SCSI_CFG0 register using this value
4709 * after it is started below.
4710 */
4711 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
4712 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
4713 asc_dvc->chip_scsi_id);
4714
4715 /*
4716 * Determine SCSI_CFG1 Microcode Default Value.
4717 *
4718 * The microcode will set the SCSI_CFG1 register using this value
4719 * after it is started below.
4720 */
4721
4722 /* Read current SCSI_CFG1 Register value. */
4723 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
4724
4725 /*
4726 * If all three connectors are in use, return an error.
4727 */
4728 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
4729 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
4730 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
4731 return ADV_ERROR;
4732 }
4733
4734 /*
4735 * If the internal narrow cable is reversed all of the SCSI_CTRL
4736 * register signals will be set. Check for and return an error if
4737 * this condition is found.
4738 */
4739 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
4740 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
4741 return ADV_ERROR;
4742 }
4743
4744 /*
4745 * If this is a differential board and a single-ended device
4746 * is attached to one of the connectors, return an error.
4747 */
4748 if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) {
4749 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
4750 return ADV_ERROR;
4751 }
4752
4753 /*
4754 * If automatic termination control is enabled, then set the
4755 * termination value based on a table listed in a_condor.h.
4756 *
4757 * If manual termination was specified with an EEPROM setting
4758 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
4759 * is ready to be 'ored' into SCSI_CFG1.
4760 */
4761 if (asc_dvc->cfg->termination == 0) {
4762 /*
4763 * The software always controls termination by setting TERM_CTL_SEL.
4764 * If TERM_CTL_SEL were set to 0, the hardware would set termination.
4765 */
4766 asc_dvc->cfg->termination |= TERM_CTL_SEL;
4767
4768 switch (scsi_cfg1 & CABLE_DETECT) {
4769 /* TERM_CTL_H: on, TERM_CTL_L: on */
4770 case 0x3:
4771 case 0x7:
4772 case 0xB:
4773 case 0xD:
4774 case 0xE:
4775 case 0xF:
4776 asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
4777 break;
4778
4779 /* TERM_CTL_H: on, TERM_CTL_L: off */
4780 case 0x1:
4781 case 0x5:
4782 case 0x9:
4783 case 0xA:
4784 case 0xC:
4785 asc_dvc->cfg->termination |= TERM_CTL_H;
4786 break;
4787
4788 /* TERM_CTL_H: off, TERM_CTL_L: off */
4789 case 0x2:
4790 case 0x6:
4791 break;
4792 }
4793 }
4794
4795 /*
4796 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
4797 */
4798 scsi_cfg1 &= ~TERM_CTL;
4799
4800 /*
4801 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
4802 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
4803 * referenced, because the hardware internally inverts
4804 * the Termination High and Low bits if TERM_POL is set.
4805 */
4806 scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
4807
4808 /*
4809 * Set SCSI_CFG1 Microcode Default Value
4810 *
4811 * Set filter value and possibly modified termination control
4812 * bits in the Microcode SCSI_CFG1 Register Value.
4813 *
4814 * The microcode will set the SCSI_CFG1 register using this value
4815 * after it is started below.
4816 */
4817 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
4818 FLTR_DISABLE | scsi_cfg1);
4819
4820 /*
4821 * Set MEM_CFG Microcode Default Value
4822 *
4823 * The microcode will set the MEM_CFG register using this value
4824 * after it is started below.
4825 *
4826 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
4827 * are defined.
4828 *
4829 * ASC-3550 has 8KB internal memory.
4830 */
4831 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
4832 BIOS_EN | RAM_SZ_8KB);
4833
4834 /*
4835 * Set SEL_MASK Microcode Default Value
4836 *
4837 * The microcode will set the SEL_MASK register using this value
4838 * after it is started below.
4839 */
4840 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
4841 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
4842
4843 AdvBuildCarrierFreelist(asc_dvc);
4844
4845 /*
4846 * Set-up the Host->RISC Initiator Command Queue (ICQ).
4847 */
4848
4849 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
4850 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4851 return ADV_ERROR;
4852 }
4853 asc_dvc->carr_freelist = (ADV_CARR_T *)
4854 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
4855
4856 /*
4857 * The first command issued will be placed in the stopper carrier.
4858 */
4859 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
4860
4861 /*
4862 * Set RISC ICQ physical address start value.
4863 */
4864 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
4865
4866 /*
4867 * Set-up the RISC->Host Initiator Response Queue (IRQ).
4868 */
4869 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
4870 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4871 return ADV_ERROR;
4872 }
4873 asc_dvc->carr_freelist = (ADV_CARR_T *)
4874 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
4875
4876 /*
4877 * The first command completed by the RISC will be placed in
4878 * the stopper.
4879 *
4880 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
4881 * completed the RISC will set the ASC_RQ_STOPPER bit.
4882 */
4883 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
4884
4885 /*
4886 * Set RISC IRQ physical address start value.
4887 */
4888 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
4889 asc_dvc->carr_pending_cnt = 0;
4890
4891 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
4892 (ADV_INTR_ENABLE_HOST_INTR |
4893 ADV_INTR_ENABLE_GLOBAL_INTR));
4894
4895 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
4896 AdvWriteWordRegister(iop_base, IOPW_PC, word);
4897
4898 /* finally, finally, gentlemen, start your engine */
4899 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
4900
4901 /*
4902 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
4903 * Resets should be performed. The RISC has to be running
4904 * to issue a SCSI Bus Reset.
4905 */
4906 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
4907 /*
4908 * If the BIOS Signature is present in memory, restore the
4909 * BIOS Handshake Configuration Table and do not perform
4910 * a SCSI Bus Reset.
4911 */
4912 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
4913 0x55AA) {
4914 /*
4915 * Restore per TID negotiated values.
4916 */
4917 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4918 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4919 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
4920 tagqng_able);
4921 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4922 AdvWriteByteLram(iop_base,
4923 ASC_MC_NUMBER_OF_MAX_CMD + tid,
4924 max_cmd[tid]);
4925 }
4926 } else {
4927 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
4928 warn_code = ASC_WARN_BUSRESET_ERROR;
4929 }
4930 }
4931 }
4932
4933 return warn_code;
4934}
4935
4936/*
4937 * Initialize the ASC-38C0800.
4938 *
4939 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4940 *
4941 * For a non-fatal error return a warning code. If there are no warnings
4942 * then 0 is returned.
4943 *
4944 * Needed after initialization for error recovery.
4945 */
4946static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
4947{
989bb5f5
JSR		 4948 const struct firmware *fw;
4949 const char fwname[] = "advansys/38C0800.bin";
51219358
MW		 4950 AdvPortAddr iop_base;
4951 ushort warn_code;
4952 int begin_addr;
4953 int end_addr;
4954 ushort code_sum;
4955 int word;
4956 int i;
989bb5f5
JSR		 4957 int err;
4958 unsigned long chksum;
51219358
MW		 4959 ushort scsi_cfg1;
4960 uchar byte;
4961 uchar tid;
4962 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
4963 ushort wdtr_able, sdtr_able, tagqng_able;
4964 uchar max_cmd[ADV_MAX_TID + 1];
4965
4966 /* If there is already an error, don't continue. */
4967 if (asc_dvc->err_code != 0)
4968 return ADV_ERROR;
4969
4970 /*
4971 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
4972 */
4973 if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) {
4974 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
4975 return ADV_ERROR;
4976 }
4977
4978 warn_code = 0;
4979 iop_base = asc_dvc->iop_base;
4980
4981 /*
4982 * Save the RISC memory BIOS region before writing the microcode.
4983 * The BIOS may already be loaded and using its RISC LRAM region
4984 * so its region must be saved and restored.
4985 *
4986 * Note: This code makes the assumption, which is currently true,
4987 * that a chip reset does not clear RISC LRAM.
4988 */
4989 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4990 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4991 bios_mem[i]);
4992 }
4993
4994 /*
4995 * Save current per TID negotiated values.
4996 */
4997 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4998 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4999 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5000 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5001 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5002 max_cmd[tid]);
5003 }
5004
5005 /*
5006 * RAM BIST (RAM Built-In Self Test)
5007 *
5008 * Address : I/O base + offset 0x38h register (byte).
5009 * Function: Bit 7-6(RW) : RAM mode
5010 * Normal Mode : 0x00
5011 * Pre-test Mode : 0x40
5012 * RAM Test Mode : 0x80
5013 * Bit 5 : unused
5014 * Bit 4(RO) : Done bit
5015 * Bit 3-0(RO) : Status
5016 * Host Error : 0x08
5017 * Int_RAM Error : 0x04
5018 * RISC Error : 0x02
5019 * SCSI Error : 0x01
5020 * No Error : 0x00
5021 *
5022 * Note: RAM BIST code should be put right here, before loading the
5023 * microcode and after saving the RISC memory BIOS region.
5024 */
5025
5026 /*
5027 * LRAM Pre-test
5028 *
5029 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
5030 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
5031 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
5032 * to NORMAL_MODE, return an error too.
5033 */
5034 for (i = 0; i < 2; i++) {
5035 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
5036 mdelay(10); /* Wait for 10ms before reading back. */
5037 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5038 if ((byte & RAM_TEST_DONE) == 0
5039 || (byte & 0x0F) != PRE_TEST_VALUE) {
5040 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5041 return ADV_ERROR;
5042 }
5043
5044 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5045 mdelay(10); /* Wait for 10ms before reading back. */
5046 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
5047 != NORMAL_VALUE) {
5048 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5049 return ADV_ERROR;
5050 }
5051 }
5052
5053 /*
5054 * LRAM Test - It takes about 1.5 ms to run through the test.
5055 *
5056 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
5057 * If Done bit not set or Status not 0, save register byte, set the
5058 * err_code, and return an error.
5059 */
5060 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
5061 mdelay(10); /* Wait for 10ms before checking status. */
5062
5063 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5064 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
5065 /* Get here if Done bit not set or Status not 0. */
5066 asc_dvc->bist_err_code = byte; /* for BIOS display message */
5067 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
5068 return ADV_ERROR;
5069 }
5070
5071 /* We need to reset back to normal mode after LRAM test passes. */
5072 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5073
989bb5f5
JSR		 5074 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5075 if (err) {
5076 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5077 fwname, err);
cf747445 5078 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 5079 return err;
5080 }
5081 if (fw->size < 4) {
5082 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5083 fw->size, fwname);
5084 release_firmware(fw);
cf747445 5085 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 5086 return -EINVAL;
5087 }
5088 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5089 (fw->data[1] << 8) | fw->data[0];
5090 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5091 fw->size - 4, ADV_38C0800_MEMSIZE,
5092 chksum);
5093 release_firmware(fw);
51219358
MW		 5094 if (asc_dvc->err_code)
5095 return ADV_ERROR;
5096
5097 /*
5098 * Restore the RISC memory BIOS region.
5099 */
5100 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5101 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5102 bios_mem[i]);
5103 }
5104
5105 /*
5106 * Calculate and write the microcode code checksum to the microcode
5107 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5108 */
5109 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5110 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5111 code_sum = 0;
5112 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5113 for (word = begin_addr; word < end_addr; word += 2) {
5114 code_sum += AdvReadWordAutoIncLram(iop_base);
5115 }
5116 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5117
5118 /*
5119 * Read microcode version and date.
5120 */
5121 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5122 asc_dvc->cfg->mcode_date);
5123 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5124 asc_dvc->cfg->mcode_version);
5125
5126 /*
5127 * Set the chip type to indicate the ASC38C0800.
5128 */
5129 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
5130
5131 /*
5132 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5133 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5134 * cable detection and then we are able to read C_DET[3:0].
5135 *
5136 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5137 * Microcode Default Value' section below.
5138 */
5139 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5140 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5141 scsi_cfg1 | DIS_TERM_DRV);
5142
5143 /*
5144 * If the PCI Configuration Command Register "Parity Error Response
5145 * Control" Bit was clear (0), then set the microcode variable
5146 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5147 * to ignore DMA parity errors.
5148 */
5149 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5150 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5151 word |= CONTROL_FLAG_IGNORE_PERR;
5152 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5153 }
5154
5155 /*
5156 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
5157 * bits for the default FIFO threshold.
5158 *
5159 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
5160 *
5161 * For DMA Errata #4 set the BC_THRESH_ENB bit.
5162 */
5163 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5164 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH |
5165 READ_CMD_MRM);
5166
5167 /*
5168 * Microcode operating variables for WDTR, SDTR, and command tag
5169 * queuing will be set in slave_configure() based on what a
5170 * device reports it is capable of in Inquiry byte 7.
5171 *
5172 * If SCSI Bus Resets have been disabled, then directly set
5173 * SDTR and WDTR from the EEPROM configuration. This will allow
5174 * the BIOS and warm boot to work without a SCSI bus hang on
5175 * the Inquiry caused by host and target mismatched DTR values.
5176 * Without the SCSI Bus Reset, before an Inquiry a device can't
5177 * be assumed to be in Asynchronous, Narrow mode.
5178 */
5179 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5180 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5181 asc_dvc->wdtr_able);
5182 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5183 asc_dvc->sdtr_able);
5184 }
5185
5186 /*
5187 * Set microcode operating variables for DISC and SDTR_SPEED1,
5188 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5189 * configuration values.
5190 *
5191 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5192 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5193 * without determining here whether the device supports SDTR.
5194 */
5195 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5196 asc_dvc->cfg->disc_enable);
5197 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5198 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5199 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5200 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5201
5202 /*
5203 * Set SCSI_CFG0 Microcode Default Value.
5204 *
5205 * The microcode will set the SCSI_CFG0 register using this value
5206 * after it is started below.
5207 */
5208 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5209 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5210 asc_dvc->chip_scsi_id);
5211
5212 /*
5213 * Determine SCSI_CFG1 Microcode Default Value.
5214 *
5215 * The microcode will set the SCSI_CFG1 register using this value
5216 * after it is started below.
5217 */
5218
5219 /* Read current SCSI_CFG1 Register value. */
5220 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5221
5222 /*
5223 * If the internal narrow cable is reversed all of the SCSI_CTRL
5224 * register signals will be set. Check for and return an error if
5225 * this condition is found.
5226 */
5227 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5228 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5229 return ADV_ERROR;
5230 }
5231
5232 /*
5233 * All kind of combinations of devices attached to one of four
5234 * connectors are acceptable except HVD device attached. For example,
5235 * LVD device can be attached to SE connector while SE device attached
5236 * to LVD connector. If LVD device attached to SE connector, it only
5237 * runs up to Ultra speed.
5238 *
5239 * If an HVD device is attached to one of LVD connectors, return an
5240 * error. However, there is no way to detect HVD device attached to
5241 * SE connectors.
5242 */
5243 if (scsi_cfg1 & HVD) {
5244 asc_dvc->err_code = ASC_IERR_HVD_DEVICE;
5245 return ADV_ERROR;
5246 }
5247
5248 /*
5249 * If either SE or LVD automatic termination control is enabled, then
5250 * set the termination value based on a table listed in a_condor.h.
5251 *
5252 * If manual termination was specified with an EEPROM setting then
5253 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready
5254 * to be 'ored' into SCSI_CFG1.
5255 */
5256 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5257 /* SE automatic termination control is enabled. */
5258 switch (scsi_cfg1 & C_DET_SE) {
5259 /* TERM_SE_HI: on, TERM_SE_LO: on */
5260 case 0x1:
5261 case 0x2:
5262 case 0x3:
5263 asc_dvc->cfg->termination |= TERM_SE;
5264 break;
5265
5266 /* TERM_SE_HI: on, TERM_SE_LO: off */
5267 case 0x0:
5268 asc_dvc->cfg->termination |= TERM_SE_HI;
5269 break;
5270 }
5271 }
5272
5273 if ((asc_dvc->cfg->termination & TERM_LVD) == 0) {
5274 /* LVD automatic termination control is enabled. */
5275 switch (scsi_cfg1 & C_DET_LVD) {
5276 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
5277 case 0x4:
5278 case 0x8:
5279 case 0xC:
5280 asc_dvc->cfg->termination |= TERM_LVD;
5281 break;
5282
5283 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
5284 case 0x0:
5285 break;
5286 }
5287 }
5288
5289 /*
5290 * Clear any set TERM_SE and TERM_LVD bits.
5291 */
5292 scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
5293
5294 /*
5295 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
5296 */
5297 scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
5298
5299 /*
5300 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE
5301 * bits and set possibly modified termination control bits in the
5302 * Microcode SCSI_CFG1 Register Value.
5303 */
5304 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
5305
5306 /*
5307 * Set SCSI_CFG1 Microcode Default Value
5308 *
5309 * Set possibly modified termination control and reset DIS_TERM_DRV
5310 * bits in the Microcode SCSI_CFG1 Register Value.
5311 *
5312 * The microcode will set the SCSI_CFG1 register using this value
5313 * after it is started below.
5314 */
5315 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5316
5317 /*
5318 * Set MEM_CFG Microcode Default Value
5319 *
5320 * The microcode will set the MEM_CFG register using this value
5321 * after it is started below.
5322 *
5323 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5324 * are defined.
5325 *
5326 * ASC-38C0800 has 16KB internal memory.
5327 */
5328 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5329 BIOS_EN | RAM_SZ_16KB);
5330
5331 /*
5332 * Set SEL_MASK Microcode Default Value
5333 *
5334 * The microcode will set the SEL_MASK register using this value
5335 * after it is started below.
5336 */
5337 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5338 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5339
5340 AdvBuildCarrierFreelist(asc_dvc);
5341
5342 /*
5343 * Set-up the Host->RISC Initiator Command Queue (ICQ).
5344 */
5345
5346 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
5347 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5348 return ADV_ERROR;
5349 }
5350 asc_dvc->carr_freelist = (ADV_CARR_T *)
5351 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
5352
5353 /*
5354 * The first command issued will be placed in the stopper carrier.
5355 */
5356 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
5357
5358 /*
5359 * Set RISC ICQ physical address start value.
5360 * carr_pa is LE, must be native before write
5361 */
5362 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5363
5364 /*
5365 * Set-up the RISC->Host Initiator Response Queue (IRQ).
5366 */
5367 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
5368 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5369 return ADV_ERROR;
5370 }
5371 asc_dvc->carr_freelist = (ADV_CARR_T *)
5372 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
5373
5374 /*
5375 * The first command completed by the RISC will be placed in
5376 * the stopper.
5377 *
5378 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
5379 * completed the RISC will set the ASC_RQ_STOPPER bit.
5380 */
5381 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
5382
5383 /*
5384 * Set RISC IRQ physical address start value.
5385 *
5386 * carr_pa is LE, must be native before write *
5387 */
5388 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5389 asc_dvc->carr_pending_cnt = 0;
5390
5391 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5392 (ADV_INTR_ENABLE_HOST_INTR |
5393 ADV_INTR_ENABLE_GLOBAL_INTR));
5394
5395 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5396 AdvWriteWordRegister(iop_base, IOPW_PC, word);
5397
5398 /* finally, finally, gentlemen, start your engine */
5399 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5400
5401 /*
5402 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5403 * Resets should be performed. The RISC has to be running
5404 * to issue a SCSI Bus Reset.
5405 */
5406 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5407 /*
5408 * If the BIOS Signature is present in memory, restore the
5409 * BIOS Handshake Configuration Table and do not perform
5410 * a SCSI Bus Reset.
5411 */
5412 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5413 0x55AA) {
5414 /*
5415 * Restore per TID negotiated values.
5416 */
5417 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5418 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5419 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5420 tagqng_able);
5421 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5422 AdvWriteByteLram(iop_base,
5423 ASC_MC_NUMBER_OF_MAX_CMD + tid,
5424 max_cmd[tid]);
5425 }
5426 } else {
5427 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5428 warn_code = ASC_WARN_BUSRESET_ERROR;
5429 }
5430 }
5431 }
5432
5433 return warn_code;
5434}
5435
5436/*
5437 * Initialize the ASC-38C1600.
5438 *
5439 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
5440 *
5441 * For a non-fatal error return a warning code. If there are no warnings
5442 * then 0 is returned.
5443 *
5444 * Needed after initialization for error recovery.
5445 */
5446static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
5447{
989bb5f5
JSR		 5448 const struct firmware *fw;
5449 const char fwname[] = "advansys/38C1600.bin";
51219358
MW		 5450 AdvPortAddr iop_base;
5451 ushort warn_code;
5452 int begin_addr;
5453 int end_addr;
5454 ushort code_sum;
5455 long word;
5456 int i;
989bb5f5
JSR		 5457 int err;
5458 unsigned long chksum;
51219358
MW		 5459 ushort scsi_cfg1;
5460 uchar byte;
5461 uchar tid;
5462 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
5463 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
5464 uchar max_cmd[ASC_MAX_TID + 1];
5465
5466 /* If there is already an error, don't continue. */
5467 if (asc_dvc->err_code != 0) {
5468 return ADV_ERROR;
5469 }
5470
5471 /*
5472 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
5473 */
5474 if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
5475 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
5476 return ADV_ERROR;
5477 }
5478
5479 warn_code = 0;
5480 iop_base = asc_dvc->iop_base;
5481
5482 /*
5483 * Save the RISC memory BIOS region before writing the microcode.
5484 * The BIOS may already be loaded and using its RISC LRAM region
5485 * so its region must be saved and restored.
5486 *
5487 * Note: This code makes the assumption, which is currently true,
5488 * that a chip reset does not clear RISC LRAM.
5489 */
5490 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5491 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5492 bios_mem[i]);
5493 }
5494
5495 /*
5496 * Save current per TID negotiated values.
5497 */
5498 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5499 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5500 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5501 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5502 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
5503 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5504 max_cmd[tid]);
5505 }
5506
5507 /*
5508 * RAM BIST (Built-In Self Test)
5509 *
5510 * Address : I/O base + offset 0x38h register (byte).
5511 * Function: Bit 7-6(RW) : RAM mode
5512 * Normal Mode : 0x00
5513 * Pre-test Mode : 0x40
5514 * RAM Test Mode : 0x80
5515 * Bit 5 : unused
5516 * Bit 4(RO) : Done bit
5517 * Bit 3-0(RO) : Status
5518 * Host Error : 0x08
5519 * Int_RAM Error : 0x04
5520 * RISC Error : 0x02
5521 * SCSI Error : 0x01
5522 * No Error : 0x00
5523 *
5524 * Note: RAM BIST code should be put right here, before loading the
5525 * microcode and after saving the RISC memory BIOS region.
5526 */
5527
5528 /*
5529 * LRAM Pre-test
5530 *
5531 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
5532 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
5533 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
5534 * to NORMAL_MODE, return an error too.
5535 */
5536 for (i = 0; i < 2; i++) {
5537 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
5538 mdelay(10); /* Wait for 10ms before reading back. */
5539 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5540 if ((byte & RAM_TEST_DONE) == 0
5541 || (byte & 0x0F) != PRE_TEST_VALUE) {
5542 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5543 return ADV_ERROR;
5544 }
5545
5546 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5547 mdelay(10); /* Wait for 10ms before reading back. */
5548 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
5549 != NORMAL_VALUE) {
5550 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5551 return ADV_ERROR;
5552 }
5553 }
5554
5555 /*
5556 * LRAM Test - It takes about 1.5 ms to run through the test.
5557 *
5558 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
5559 * If Done bit not set or Status not 0, save register byte, set the
5560 * err_code, and return an error.
5561 */
5562 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
5563 mdelay(10); /* Wait for 10ms before checking status. */
5564
5565 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5566 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
5567 /* Get here if Done bit not set or Status not 0. */
5568 asc_dvc->bist_err_code = byte; /* for BIOS display message */
5569 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
5570 return ADV_ERROR;
5571 }
5572
5573 /* We need to reset back to normal mode after LRAM test passes. */
5574 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5575
989bb5f5
JSR		 5576 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5577 if (err) {
5578 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5579 fwname, err);
cf747445 5580 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 5581 return err;
5582 }
5583 if (fw->size < 4) {
5584 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5585 fw->size, fwname);
5586 release_firmware(fw);
cf747445 5587 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 5588 return -EINVAL;
5589 }
5590 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5591 (fw->data[1] << 8) | fw->data[0];
5592 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5593 fw->size - 4, ADV_38C1600_MEMSIZE,
5594 chksum);
5595 release_firmware(fw);
51219358
MW		 5596 if (asc_dvc->err_code)
5597 return ADV_ERROR;
5598
5599 /*
5600 * Restore the RISC memory BIOS region.
5601 */
5602 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5603 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5604 bios_mem[i]);
5605 }
5606
5607 /*
5608 * Calculate and write the microcode code checksum to the microcode
5609 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5610 */
5611 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5612 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5613 code_sum = 0;
5614 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5615 for (word = begin_addr; word < end_addr; word += 2) {
5616 code_sum += AdvReadWordAutoIncLram(iop_base);
5617 }
5618 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5619
5620 /*
5621 * Read microcode version and date.
5622 */
5623 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5624 asc_dvc->cfg->mcode_date);
5625 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5626 asc_dvc->cfg->mcode_version);
5627
5628 /*
5629 * Set the chip type to indicate the ASC38C1600.
5630 */
5631 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
5632
5633 /*
5634 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5635 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5636 * cable detection and then we are able to read C_DET[3:0].
5637 *
5638 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5639 * Microcode Default Value' section below.
5640 */
5641 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5642 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5643 scsi_cfg1 | DIS_TERM_DRV);
5644
5645 /*
5646 * If the PCI Configuration Command Register "Parity Error Response
5647 * Control" Bit was clear (0), then set the microcode variable
5648 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5649 * to ignore DMA parity errors.
5650 */
5651 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5652 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5653 word |= CONTROL_FLAG_IGNORE_PERR;
5654 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5655 }
5656
5657 /*
5658 * If the BIOS control flag AIPP (Asynchronous Information
5659 * Phase Protection) disable bit is not set, then set the firmware
5660 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
5661 * AIPP checking and encoding.
5662 */
5663 if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
5664 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5665 word |= CONTROL_FLAG_ENABLE_AIPP;
5666 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5667 }
5668
5669 /*
5670 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
5671 * and START_CTL_TH [3:2].
5672 */
5673 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5674 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
5675
5676 /*
5677 * Microcode operating variables for WDTR, SDTR, and command tag
5678 * queuing will be set in slave_configure() based on what a
5679 * device reports it is capable of in Inquiry byte 7.
5680 *
5681 * If SCSI Bus Resets have been disabled, then directly set
5682 * SDTR and WDTR from the EEPROM configuration. This will allow
5683 * the BIOS and warm boot to work without a SCSI bus hang on
5684 * the Inquiry caused by host and target mismatched DTR values.
5685 * Without the SCSI Bus Reset, before an Inquiry a device can't
5686 * be assumed to be in Asynchronous, Narrow mode.
5687 */
5688 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5689 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5690 asc_dvc->wdtr_able);
5691 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5692 asc_dvc->sdtr_able);
5693 }
5694
5695 /*
5696 * Set microcode operating variables for DISC and SDTR_SPEED1,
5697 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5698 * configuration values.
5699 *
5700 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5701 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5702 * without determining here whether the device supports SDTR.
5703 */
5704 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5705 asc_dvc->cfg->disc_enable);
5706 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5707 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5708 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5709 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5710
5711 /*
5712 * Set SCSI_CFG0 Microcode Default Value.
5713 *
5714 * The microcode will set the SCSI_CFG0 register using this value
5715 * after it is started below.
5716 */
5717 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5718 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5719 asc_dvc->chip_scsi_id);
5720
5721 /*
5722 * Calculate SCSI_CFG1 Microcode Default Value.
5723 *
5724 * The microcode will set the SCSI_CFG1 register using this value
5725 * after it is started below.
5726 *
5727 * Each ASC-38C1600 function has only two cable detect bits.
5728 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
5729 */
5730 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5731
5732 /*
5733 * If the cable is reversed all of the SCSI_CTRL register signals
5734 * will be set. Check for and return an error if this condition is
5735 * found.
5736 */
5737 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5738 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5739 return ADV_ERROR;
5740 }
5741
5742 /*
5743 * Each ASC-38C1600 function has two connectors. Only an HVD device
5744 * can not be connected to either connector. An LVD device or SE device
5745 * may be connected to either connecor. If an SE device is connected,
5746 * then at most Ultra speed (20 Mhz) can be used on both connectors.
5747 *
5748 * If an HVD device is attached, return an error.
5749 */
5750 if (scsi_cfg1 & HVD) {
5751 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
5752 return ADV_ERROR;
5753 }
5754
5755 /*
5756 * Each function in the ASC-38C1600 uses only the SE cable detect and
5757 * termination because there are two connectors for each function. Each
5758 * function may use either LVD or SE mode. Corresponding the SE automatic
5759 * termination control EEPROM bits are used for each function. Each
5760 * function has its own EEPROM. If SE automatic control is enabled for
5761 * the function, then set the termination value based on a table listed
5762 * in a_condor.h.
5763 *
5764 * If manual termination is specified in the EEPROM for the function,
5765 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
5766 * ready to be 'ored' into SCSI_CFG1.
5767 */
5768 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5769 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
5770 /* SE automatic termination control is enabled. */
5771 switch (scsi_cfg1 & C_DET_SE) {
5772 /* TERM_SE_HI: on, TERM_SE_LO: on */
5773 case 0x1:
5774 case 0x2:
5775 case 0x3:
5776 asc_dvc->cfg->termination |= TERM_SE;
5777 break;
5778
5779 case 0x0:
5780 if (PCI_FUNC(pdev->devfn) == 0) {
5781 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
5782 } else {
5783 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
5784 asc_dvc->cfg->termination |= TERM_SE_HI;
5785 }
5786 break;
5787 }
5788 }
5789
5790 /*
5791 * Clear any set TERM_SE bits.
5792 */
5793 scsi_cfg1 &= ~TERM_SE;
5794
5795 /*
5796 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
5797 */
5798 scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
5799
5800 /*
5801 * Clear Big Endian and Terminator Polarity bits and set possibly
5802 * modified termination control bits in the Microcode SCSI_CFG1
5803 * Register Value.
5804 *
5805 * Big Endian bit is not used even on big endian machines.
5806 */
5807 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
5808
5809 /*
5810 * Set SCSI_CFG1 Microcode Default Value
5811 *
5812 * Set possibly modified termination control bits in the Microcode
5813 * SCSI_CFG1 Register Value.
5814 *
5815 * The microcode will set the SCSI_CFG1 register using this value
5816 * after it is started below.
5817 */
5818 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5819
5820 /*
5821 * Set MEM_CFG Microcode Default Value
5822 *
5823 * The microcode will set the MEM_CFG register using this value
5824 * after it is started below.
5825 *
5826 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5827 * are defined.
5828 *
5829 * ASC-38C1600 has 32KB internal memory.
5830 *
5831 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
5832 * out a special 16K Adv Library and Microcode version. After the issue
5833 * resolved, we should turn back to the 32K support. Both a_condor.h and
5834 * mcode.sas files also need to be updated.
5835 *
5836 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5837 * BIOS_EN | RAM_SZ_32KB);
5838 */
5839 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5840 BIOS_EN | RAM_SZ_16KB);
5841
5842 /*
5843 * Set SEL_MASK Microcode Default Value
5844 *
5845 * The microcode will set the SEL_MASK register using this value
5846 * after it is started below.
5847 */
5848 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5849 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5850
5851 AdvBuildCarrierFreelist(asc_dvc);
5852
5853 /*
5854 * Set-up the Host->RISC Initiator Command Queue (ICQ).
5855 */
5856 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
5857 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5858 return ADV_ERROR;
5859 }
5860 asc_dvc->carr_freelist = (ADV_CARR_T *)
5861 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
5862
5863 /*
5864 * The first command issued will be placed in the stopper carrier.
5865 */
5866 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
5867
5868 /*
5869 * Set RISC ICQ physical address start value. Initialize the
5870 * COMMA register to the same value otherwise the RISC will
5871 * prematurely detect a command is available.
5872 */
5873 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5874 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
5875 le32_to_cpu(asc_dvc->icq_sp->carr_pa));
5876
5877 /*
5878 * Set-up the RISC->Host Initiator Response Queue (IRQ).
5879 */
5880 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
5881 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5882 return ADV_ERROR;
5883 }
5884 asc_dvc->carr_freelist = (ADV_CARR_T *)
5885 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
5886
5887 /*
5888 * The first command completed by the RISC will be placed in
5889 * the stopper.
5890 *
5891 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
5892 * completed the RISC will set the ASC_RQ_STOPPER bit.
5893 */
5894 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
5895
5896 /*
5897 * Set RISC IRQ physical address start value.
5898 */
5899 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5900 asc_dvc->carr_pending_cnt = 0;
5901
5902 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5903 (ADV_INTR_ENABLE_HOST_INTR |
5904 ADV_INTR_ENABLE_GLOBAL_INTR));
5905 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5906 AdvWriteWordRegister(iop_base, IOPW_PC, word);
5907
5908 /* finally, finally, gentlemen, start your engine */
5909 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5910
5911 /*
5912 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5913 * Resets should be performed. The RISC has to be running
5914 * to issue a SCSI Bus Reset.
5915 */
5916 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5917 /*
5918 * If the BIOS Signature is present in memory, restore the
5919 * per TID microcode operating variables.
5920 */
5921 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5922 0x55AA) {
5923 /*
5924 * Restore per TID negotiated values.
5925 */
5926 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5927 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5928 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5929 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5930 tagqng_able);
5931 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
5932 AdvWriteByteLram(iop_base,
5933 ASC_MC_NUMBER_OF_MAX_CMD + tid,
5934 max_cmd[tid]);
5935 }
5936 } else {
5937 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5938 warn_code = ASC_WARN_BUSRESET_ERROR;
5939 }
5940 }
5941 }
5942
5943 return warn_code;
5944}
5945
5946/*
5947 * Reset chip and SCSI Bus.
5948 *
5949 * Return Value:
5950 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
5951 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
5952 */
5953static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
5954{
5955 int status;
5956 ushort wdtr_able, sdtr_able, tagqng_able;
5957 ushort ppr_able = 0;
5958 uchar tid, max_cmd[ADV_MAX_TID + 1];
5959 AdvPortAddr iop_base;
5960 ushort bios_sig;
5961
5962 iop_base = asc_dvc->iop_base;
5963
5964 /*
5965 * Save current per TID negotiated values.
5966 */
5967 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5968 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5969 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5970 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5971 }
5972 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5973 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5974 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5975 max_cmd[tid]);
5976 }
5977
5978 /*
5979 * Force the AdvInitAsc3550/38C0800Driver() function to
5980 * perform a SCSI Bus Reset by clearing the BIOS signature word.
5981 * The initialization functions assumes a SCSI Bus Reset is not
5982 * needed if the BIOS signature word is present.
5983 */
5984 AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
5985 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
5986
5987 /*
5988 * Stop chip and reset it.
5989 */
5990 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
5991 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
5992 mdelay(100);
5993 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
5994 ADV_CTRL_REG_CMD_WR_IO_REG);
5995
5996 /*
5997 * Reset Adv Library error code, if any, and try
5998 * re-initializing the chip.
5999 */
6000 asc_dvc->err_code = 0;
6001 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
6002 status = AdvInitAsc38C1600Driver(asc_dvc);
6003 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
6004 status = AdvInitAsc38C0800Driver(asc_dvc);
6005 } else {
6006 status = AdvInitAsc3550Driver(asc_dvc);
6007 }
6008
6009 /* Translate initialization return value to status value. */
6010 if (status == 0) {
6011 status = ADV_TRUE;
6012 } else {
6013 status = ADV_FALSE;
6014 }
6015
6016 /*
6017 * Restore the BIOS signature word.
6018 */
6019 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
6020
6021 /*
6022 * Restore per TID negotiated values.
6023 */
6024 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
6025 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
6026 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
6027 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
6028 }
6029 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
6030 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
6031 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
6032 max_cmd[tid]);
6033 }
6034
6035 return status;
6036}
6037
6038/*
6039 * adv_async_callback() - Adv Library asynchronous event callback function.
6040 */
6041static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
6042{
6043 switch (code) {
6044 case ADV_ASYNC_SCSI_BUS_RESET_DET:
6045 /*
6046 * The firmware detected a SCSI Bus reset.
6047 */
b352f923 6048 ASC_DBG(0, "ADV_ASYNC_SCSI_BUS_RESET_DET\n");
51219358
MW		 6049 break;
6050
6051 case ADV_ASYNC_RDMA_FAILURE:
6052 /*
6053 * Handle RDMA failure by resetting the SCSI Bus and
6054 * possibly the chip if it is unresponsive. Log the error
6055 * with a unique code.
6056 */
b352f923 6057 ASC_DBG(0, "ADV_ASYNC_RDMA_FAILURE\n");
51219358
MW		 6058 AdvResetChipAndSB(adv_dvc_varp);
6059 break;
6060
6061 case ADV_HOST_SCSI_BUS_RESET:
6062 /*
6063 * Host generated SCSI bus reset occurred.
6064 */
b352f923 6065 ASC_DBG(0, "ADV_HOST_SCSI_BUS_RESET\n");
51219358
MW		 6066 break;
6067
6068 default:
b352f923 6069 ASC_DBG(0, "unknown code 0x%x\n", code);
51219358
MW		 6070 break;
6071 }
6072}
6073
6074/*
6075 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
6076 *
6077 * Callback function for the Wide SCSI Adv Library.
6078 */
6079static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
6080{
9c17c62a
HR		 6081 struct asc_board *boardp = adv_dvc_varp->drv_ptr;
6082 u32 srb_tag;
51219358
MW		 6083 adv_req_t *reqp;
6084 adv_sgblk_t *sgblkp;
6085 struct scsi_cmnd *scp;
51219358
MW		 6086 ADV_DCNT resid_cnt;
6087
9c17c62a
HR		 6088 ASC_DBG(1, "adv_dvc_varp 0x%p, scsiqp 0x%p\n",
6089 adv_dvc_varp, scsiqp);
51219358
MW		 6090 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
6091
6092 /*
6093 * Get the adv_req_t structure for the command that has been
6094 * completed. The adv_req_t structure actually contains the
6095 * completed ADV_SCSI_REQ_Q structure.
6096 */
9c17c62a
HR		 6097 srb_tag = le32_to_cpu(scsiqp->srb_tag);
6098 scp = scsi_host_find_tag(boardp->shost, scsiqp->srb_tag);
51219358 6099
b352f923 6100 ASC_DBG(1, "scp 0x%p\n", scp);
51219358
MW		 6101 if (scp == NULL) {
6102 ASC_PRINT
6103 ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
6104 return;
6105 }
6106 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
6107
9c17c62a
HR		 6108 reqp = (adv_req_t *)scp->host_scribble;
6109 ASC_DBG(1, "reqp 0x%lx\n", (ulong)reqp);
6110 if (reqp == NULL) {
6111 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
6112 return;
6113 }
6114 /*
6115 * Remove backreferences to avoid duplicate
6116 * command completions.
6117 */
6118 scp->host_scribble = NULL;
6119 reqp->cmndp = NULL;
51219358 6120
9c17c62a
HR		 6121 ASC_STATS(boardp->shost, callback);
6122 ASC_DBG(1, "shost 0x%p\n", boardp->shost);
51219358
MW		 6123
6124 /*
6125 * 'done_status' contains the command's ending status.
6126 */
6127 switch (scsiqp->done_status) {
6128 case QD_NO_ERROR:
b352f923 6129 ASC_DBG(2, "QD_NO_ERROR\n");
51219358
MW		 6130 scp->result = 0;
6131
6132 /*
6133 * Check for an underrun condition.
6134 *
6135 * If there was no error and an underrun condition, then
6136 * then return the number of underrun bytes.
6137 */
6138 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
52c334e9
MW		 6139 if (scsi_bufflen(scp) != 0 && resid_cnt != 0 &&
6140 resid_cnt <= scsi_bufflen(scp)) {
b352f923 6141 ASC_DBG(1, "underrun condition %lu bytes\n",
51219358 6142 (ulong)resid_cnt);
52c334e9 6143 scsi_set_resid(scp, resid_cnt);
51219358
MW		 6144 }
6145 break;
6146
6147 case QD_WITH_ERROR:
b352f923 6148 ASC_DBG(2, "QD_WITH_ERROR\n");
51219358
MW		 6149 switch (scsiqp->host_status) {
6150 case QHSTA_NO_ERROR:
6151 if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
b352f923 6152 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
51219358 6153 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
b80ca4f7 6154 SCSI_SENSE_BUFFERSIZE);
51219358
MW		 6155 /*
6156 * Note: The 'status_byte()' macro used by
6157 * target drivers defined in scsi.h shifts the
6158 * status byte returned by host drivers right
6159 * by 1 bit. This is why target drivers also
6160 * use right shifted status byte definitions.
6161 * For instance target drivers use
6162 * CHECK_CONDITION, defined to 0x1, instead of
6163 * the SCSI defined check condition value of
6164 * 0x2. Host drivers are supposed to return
6165 * the status byte as it is defined by SCSI.
6166 */
6167 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
6168 STATUS_BYTE(scsiqp->scsi_status);
6169 } else {
6170 scp->result = STATUS_BYTE(scsiqp->scsi_status);
6171 }
6172 break;
6173
6174 default:
6175 /* Some other QHSTA error occurred. */
b352f923 6176 ASC_DBG(1, "host_status 0x%x\n", scsiqp->host_status);
51219358
MW		 6177 scp->result = HOST_BYTE(DID_BAD_TARGET);
6178 break;
6179 }
6180 break;
6181
6182 case QD_ABORTED_BY_HOST:
b352f923 6183 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
51219358
MW		 6184 scp->result =
6185 HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
6186 break;
6187
6188 default:
b352f923 6189 ASC_DBG(1, "done_status 0x%x\n", scsiqp->done_status);
51219358
MW		 6190 scp->result =
6191 HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
6192 break;
6193 }
6194
6195 /*
6196 * If the 'init_tidmask' bit isn't already set for the target and the
6197 * current request finished normally, then set the bit for the target
6198 * to indicate that a device is present.
6199 */
6200 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
6201 scsiqp->done_status == QD_NO_ERROR &&
6202 scsiqp->host_status == QHSTA_NO_ERROR) {
6203 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
6204 }
6205
6206 asc_scsi_done(scp);
6207
6208 /*
6209 * Free all 'adv_sgblk_t' structures allocated for the request.
6210 */
6211 while ((sgblkp = reqp->sgblkp) != NULL) {
6212 /* Remove 'sgblkp' from the request list. */
6213 reqp->sgblkp = sgblkp->next_sgblkp;
6214
6215 /* Add 'sgblkp' to the board free list. */
6216 sgblkp->next_sgblkp = boardp->adv_sgblkp;
6217 boardp->adv_sgblkp = sgblkp;
6218 }
6219
b352f923 6220 ASC_DBG(1, "done\n");
51219358
MW		 6221}
6222
6223/*
6224 * Adv Library Interrupt Service Routine
6225 *
6226 * This function is called by a driver's interrupt service routine.
6227 * The function disables and re-enables interrupts.
6228 *
6229 * When a microcode idle command is completed, the ADV_DVC_VAR
6230 * 'idle_cmd_done' field is set to ADV_TRUE.
6231 *
6232 * Note: AdvISR() can be called when interrupts are disabled or even
6233 * when there is no hardware interrupt condition present. It will
6234 * always check for completed idle commands and microcode requests.
6235 * This is an important feature that shouldn't be changed because it
6236 * allows commands to be completed from polling mode loops.
6237 *
6238 * Return:
6239 * ADV_TRUE(1) - interrupt was pending
6240 * ADV_FALSE(0) - no interrupt was pending
6241 */
6242static int AdvISR(ADV_DVC_VAR *asc_dvc)
6243{
6244 AdvPortAddr iop_base;
6245 uchar int_stat;
6246 ushort target_bit;
6247 ADV_CARR_T *free_carrp;
6248 ADV_VADDR irq_next_vpa;
6249 ADV_SCSI_REQ_Q *scsiq;
6250
6251 iop_base = asc_dvc->iop_base;
6252
6253 /* Reading the register clears the interrupt. */
6254 int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
6255
6256 if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
6257 ADV_INTR_STATUS_INTRC)) == 0) {
6258 return ADV_FALSE;
6259 }
6260
6261 /*
6262 * Notify the driver of an asynchronous microcode condition by
6263 * calling the adv_async_callback function. The function
6264 * is passed the microcode ASC_MC_INTRB_CODE byte value.
6265 */
6266 if (int_stat & ADV_INTR_STATUS_INTRB) {
6267 uchar intrb_code;
6268
6269 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
6270
6271 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
6272 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
6273 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
6274 asc_dvc->carr_pending_cnt != 0) {
6275 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
6276 ADV_TICKLE_A);
6277 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
6278 AdvWriteByteRegister(iop_base,
6279 IOPB_TICKLE,
6280 ADV_TICKLE_NOP);
6281 }
6282 }
6283 }
6284
6285 adv_async_callback(asc_dvc, intrb_code);
6286 }
6287
6288 /*
6289 * Check if the IRQ stopper carrier contains a completed request.
6290 */
6291 while (((irq_next_vpa =
6292 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0) {
6293 /*
6294 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
6295 * The RISC will have set 'areq_vpa' to a virtual address.
6296 *
6297 * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr
6298 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
6299 * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr'
6300 * in AdvExeScsiQueue().
6301 */
6302 scsiq = (ADV_SCSI_REQ_Q *)
6303 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->areq_vpa));
6304
6305 /*
6306 * Request finished with good status and the queue was not
6307 * DMAed to host memory by the firmware. Set all status fields
6308 * to indicate good status.
6309 */
6310 if ((irq_next_vpa & ASC_RQ_GOOD) != 0) {
6311 scsiq->done_status = QD_NO_ERROR;
6312 scsiq->host_status = scsiq->scsi_status = 0;
6313 scsiq->data_cnt = 0L;
6314 }
6315
6316 /*
6317 * Advance the stopper pointer to the next carrier
6318 * ignoring the lower four bits. Free the previous
6319 * stopper carrier.
6320 */
6321 free_carrp = asc_dvc->irq_sp;
6322 asc_dvc->irq_sp = (ADV_CARR_T *)
6323 ADV_U32_TO_VADDR(ASC_GET_CARRP(irq_next_vpa));
6324
6325 free_carrp->next_vpa =
6326 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
6327 asc_dvc->carr_freelist = free_carrp;
6328 asc_dvc->carr_pending_cnt--;
6329
6330 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
6331
6332 /*
6333 * Clear request microcode control flag.
6334 */
6335 scsiq->cntl = 0;
6336
6337 /*
6338 * Notify the driver of the completed request by passing
6339 * the ADV_SCSI_REQ_Q pointer to its callback function.
6340 */
6341 scsiq->a_flag |= ADV_SCSIQ_DONE;
6342 adv_isr_callback(asc_dvc, scsiq);
6343 /*
6344 * Note: After the driver callback function is called, 'scsiq'
6345 * can no longer be referenced.
6346 *
6347 * Fall through and continue processing other completed
6348 * requests...
6349 */
6350 }
6351 return ADV_TRUE;
6352}
6353
6354static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code)
6355{
6356 if (asc_dvc->err_code == 0) {
6357 asc_dvc->err_code = err_code;
6358 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
6359 err_code);
6360 }
6361 return err_code;
6362}
6363
6364static void AscAckInterrupt(PortAddr iop_base)
6365{
6366 uchar host_flag;
6367 uchar risc_flag;
6368 ushort loop;
6369
6370 loop = 0;
6371 do {
6372 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
6373 if (loop++ > 0x7FFF) {
6374 break;
6375 }
6376 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
6377 host_flag =
6378 AscReadLramByte(iop_base,
6379 ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
6380 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
6381 (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT));
6382 AscSetChipStatus(iop_base, CIW_INT_ACK);
6383 loop = 0;
6384 while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
6385 AscSetChipStatus(iop_base, CIW_INT_ACK);
6386 if (loop++ > 3) {
6387 break;
6388 }
6389 }
6390 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
51219358
MW		 6391}
6392
6393static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
6394{
afbb68c3 6395 const uchar *period_table;
51219358
MW		 6396 int max_index;
6397 int min_index;
6398 int i;
6399
6400 period_table = asc_dvc->sdtr_period_tbl;
6401 max_index = (int)asc_dvc->max_sdtr_index;
afbb68c3 6402 min_index = (int)asc_dvc->min_sdtr_index;
51219358
MW		 6403 if ((syn_time <= period_table[max_index])) {
6404 for (i = min_index; i < (max_index - 1); i++) {
6405 if (syn_time <= period_table[i]) {
6406 return (uchar)i;
6407 }
6408 }
6409 return (uchar)max_index;
6410 } else {
6411 return (uchar)(max_index + 1);
6412 }
6413}
6414
6415static uchar
6416AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset)
6417{
6418 EXT_MSG sdtr_buf;
6419 uchar sdtr_period_index;
6420 PortAddr iop_base;
6421
6422 iop_base = asc_dvc->iop_base;
6423 sdtr_buf.msg_type = EXTENDED_MESSAGE;
6424 sdtr_buf.msg_len = MS_SDTR_LEN;
6425 sdtr_buf.msg_req = EXTENDED_SDTR;
6426 sdtr_buf.xfer_period = sdtr_period;
6427 sdtr_offset &= ASC_SYN_MAX_OFFSET;
6428 sdtr_buf.req_ack_offset = sdtr_offset;
6429 sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
6430 if (sdtr_period_index <= asc_dvc->max_sdtr_index) {
6431 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6432 (uchar *)&sdtr_buf,
6433 sizeof(EXT_MSG) >> 1);
6434 return ((sdtr_period_index << 4) | sdtr_offset);
6435 } else {
6436 sdtr_buf.req_ack_offset = 0;
6437 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6438 (uchar *)&sdtr_buf,
6439 sizeof(EXT_MSG) >> 1);
6440 return 0;
6441 }
6442}
6443
6444static uchar
6445AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
6446{
6447 uchar byte;
6448 uchar sdtr_period_ix;
6449
6450 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
afbb68c3 6451 if (sdtr_period_ix > asc_dvc->max_sdtr_index)
51219358 6452 return 0xFF;
51219358
MW		 6453 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
6454 return byte;
6455}
6456
6457static int AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data)
6458{
6459 ASC_SCSI_BIT_ID_TYPE org_id;
6460 int i;
6461 int sta = TRUE;
6462
6463 AscSetBank(iop_base, 1);
6464 org_id = AscReadChipDvcID(iop_base);
6465 for (i = 0; i <= ASC_MAX_TID; i++) {
6466 if (org_id == (0x01 << i))
6467 break;
6468 }
6469 org_id = (ASC_SCSI_BIT_ID_TYPE) i;
6470 AscWriteChipDvcID(iop_base, id);
6471 if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
6472 AscSetBank(iop_base, 0);
6473 AscSetChipSyn(iop_base, sdtr_data);
6474 if (AscGetChipSyn(iop_base) != sdtr_data) {
6475 sta = FALSE;
6476 }
6477 } else {
6478 sta = FALSE;
6479 }
6480 AscSetBank(iop_base, 1);
6481 AscWriteChipDvcID(iop_base, org_id);
6482 AscSetBank(iop_base, 0);
6483 return (sta);
6484}
6485
6486static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no)
6487{
6488 AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
6489 AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
6490}
6491
6492static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
6493{
6494 EXT_MSG ext_msg;
6495 EXT_MSG out_msg;
6496 ushort halt_q_addr;
6497 int sdtr_accept;
6498 ushort int_halt_code;
6499 ASC_SCSI_BIT_ID_TYPE scsi_busy;
6500 ASC_SCSI_BIT_ID_TYPE target_id;
6501 PortAddr iop_base;
6502 uchar tag_code;
6503 uchar q_status;
6504 uchar halt_qp;
6505 uchar sdtr_data;
6506 uchar target_ix;
6507 uchar q_cntl, tid_no;
6508 uchar cur_dvc_qng;
6509 uchar asyn_sdtr;
6510 uchar scsi_status;
d2411495 6511 struct asc_board *boardp;
51219358
MW		 6512
6513 BUG_ON(!asc_dvc->drv_ptr);
6514 boardp = asc_dvc->drv_ptr;
6515
6516 iop_base = asc_dvc->iop_base;
6517 int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
6518
6519 halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
6520 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
6521 target_ix = AscReadLramByte(iop_base,
6522 (ushort)(halt_q_addr +
6523 (ushort)ASC_SCSIQ_B_TARGET_IX));
6524 q_cntl = AscReadLramByte(iop_base,
6525 (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL));
6526 tid_no = ASC_TIX_TO_TID(target_ix);
6527 target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no);
6528 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6529 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
6530 } else {
6531 asyn_sdtr = 0;
6532 }
6533 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
6534 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6535 AscSetChipSDTR(iop_base, 0, tid_no);
6536 boardp->sdtr_data[tid_no] = 0;
6537 }
6538 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6539 return (0);
6540 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
6541 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6542 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6543 boardp->sdtr_data[tid_no] = asyn_sdtr;
6544 }
6545 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6546 return (0);
6547 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
6548 AscMemWordCopyPtrFromLram(iop_base,
6549 ASCV_MSGIN_BEG,
6550 (uchar *)&ext_msg,
6551 sizeof(EXT_MSG) >> 1);
6552
6553 if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6554 ext_msg.msg_req == EXTENDED_SDTR &&
6555 ext_msg.msg_len == MS_SDTR_LEN) {
6556 sdtr_accept = TRUE;
6557 if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
6558
6559 sdtr_accept = FALSE;
6560 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
6561 }
6562 if ((ext_msg.xfer_period <
afbb68c3 6563 asc_dvc->sdtr_period_tbl[asc_dvc->min_sdtr_index])
51219358
MW		 6564 || (ext_msg.xfer_period >
6565 asc_dvc->sdtr_period_tbl[asc_dvc->
6566 max_sdtr_index])) {
6567 sdtr_accept = FALSE;
6568 ext_msg.xfer_period =
6569 asc_dvc->sdtr_period_tbl[asc_dvc->
afbb68c3 6570 min_sdtr_index];
51219358
MW		 6571 }
6572 if (sdtr_accept) {
6573 sdtr_data =
6574 AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
6575 ext_msg.req_ack_offset);
6576 if ((sdtr_data == 0xFF)) {
6577
6578 q_cntl |= QC_MSG_OUT;
6579 asc_dvc->init_sdtr &= ~target_id;
6580 asc_dvc->sdtr_done &= ~target_id;
6581 AscSetChipSDTR(iop_base, asyn_sdtr,
6582 tid_no);
6583 boardp->sdtr_data[tid_no] = asyn_sdtr;
6584 }
6585 }
6586 if (ext_msg.req_ack_offset == 0) {
6587
6588 q_cntl &= ~QC_MSG_OUT;
6589 asc_dvc->init_sdtr &= ~target_id;
6590 asc_dvc->sdtr_done &= ~target_id;
6591 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6592 } else {
6593 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
51219358
MW		 6594 q_cntl &= ~QC_MSG_OUT;
6595 asc_dvc->sdtr_done |= target_id;
6596 asc_dvc->init_sdtr |= target_id;
6597 asc_dvc->pci_fix_asyn_xfer &=
6598 ~target_id;
6599 sdtr_data =
6600 AscCalSDTRData(asc_dvc,
6601 ext_msg.xfer_period,
6602 ext_msg.
6603 req_ack_offset);
6604 AscSetChipSDTR(iop_base, sdtr_data,
6605 tid_no);
6606 boardp->sdtr_data[tid_no] = sdtr_data;
6607 } else {
51219358
MW		 6608 q_cntl |= QC_MSG_OUT;
6609 AscMsgOutSDTR(asc_dvc,
6610 ext_msg.xfer_period,
6611 ext_msg.req_ack_offset);
6612 asc_dvc->pci_fix_asyn_xfer &=
6613 ~target_id;
6614 sdtr_data =
6615 AscCalSDTRData(asc_dvc,
6616 ext_msg.xfer_period,
6617 ext_msg.
6618 req_ack_offset);
6619 AscSetChipSDTR(iop_base, sdtr_data,
6620 tid_no);
6621 boardp->sdtr_data[tid_no] = sdtr_data;
6622 asc_dvc->sdtr_done |= target_id;
6623 asc_dvc->init_sdtr |= target_id;
6624 }
6625 }
6626
6627 AscWriteLramByte(iop_base,
6628 (ushort)(halt_q_addr +
6629 (ushort)ASC_SCSIQ_B_CNTL),
6630 q_cntl);
6631 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6632 return (0);
6633 } else if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6634 ext_msg.msg_req == EXTENDED_WDTR &&
6635 ext_msg.msg_len == MS_WDTR_LEN) {
6636
6637 ext_msg.wdtr_width = 0;
6638 AscMemWordCopyPtrToLram(iop_base,
6639 ASCV_MSGOUT_BEG,
6640 (uchar *)&ext_msg,
6641 sizeof(EXT_MSG) >> 1);
6642 q_cntl |= QC_MSG_OUT;
6643 AscWriteLramByte(iop_base,
6644 (ushort)(halt_q_addr +
6645 (ushort)ASC_SCSIQ_B_CNTL),
6646 q_cntl);
6647 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6648 return (0);
6649 } else {
6650
6651 ext_msg.msg_type = MESSAGE_REJECT;
6652 AscMemWordCopyPtrToLram(iop_base,
6653 ASCV_MSGOUT_BEG,
6654 (uchar *)&ext_msg,
6655 sizeof(EXT_MSG) >> 1);
6656 q_cntl |= QC_MSG_OUT;
6657 AscWriteLramByte(iop_base,
6658 (ushort)(halt_q_addr +
6659 (ushort)ASC_SCSIQ_B_CNTL),
6660 q_cntl);
6661 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6662 return (0);
6663 }
6664 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
6665
6666 q_cntl |= QC_REQ_SENSE;
6667
6668 if ((asc_dvc->init_sdtr & target_id) != 0) {
6669
6670 asc_dvc->sdtr_done &= ~target_id;
6671
6672 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
6673 q_cntl |= QC_MSG_OUT;
6674 AscMsgOutSDTR(asc_dvc,
6675 asc_dvc->
6676 sdtr_period_tbl[(sdtr_data >> 4) &
6677 (uchar)(asc_dvc->
6678 max_sdtr_index -
6679 1)],
6680 (uchar)(sdtr_data & (uchar)
6681 ASC_SYN_MAX_OFFSET));
6682 }
6683
6684 AscWriteLramByte(iop_base,
6685 (ushort)(halt_q_addr +
6686 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6687
6688 tag_code = AscReadLramByte(iop_base,
6689 (ushort)(halt_q_addr + (ushort)
6690 ASC_SCSIQ_B_TAG_CODE));
6691 tag_code &= 0xDC;
6692 if ((asc_dvc->pci_fix_asyn_xfer & target_id)
6693 && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
6694 ) {
6695
6696 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
6697 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
6698
6699 }
6700 AscWriteLramByte(iop_base,
6701 (ushort)(halt_q_addr +
6702 (ushort)ASC_SCSIQ_B_TAG_CODE),
6703 tag_code);
6704
6705 q_status = AscReadLramByte(iop_base,
6706 (ushort)(halt_q_addr + (ushort)
6707 ASC_SCSIQ_B_STATUS));
6708 q_status |= (QS_READY | QS_BUSY);
6709 AscWriteLramByte(iop_base,
6710 (ushort)(halt_q_addr +
6711 (ushort)ASC_SCSIQ_B_STATUS),
6712 q_status);
6713
6714 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B);
6715 scsi_busy &= ~target_id;
6716 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6717
6718 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6719 return (0);
6720 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
6721
6722 AscMemWordCopyPtrFromLram(iop_base,
6723 ASCV_MSGOUT_BEG,
6724 (uchar *)&out_msg,
6725 sizeof(EXT_MSG) >> 1);
6726
6727 if ((out_msg.msg_type == EXTENDED_MESSAGE) &&
6728 (out_msg.msg_len == MS_SDTR_LEN) &&
6729 (out_msg.msg_req == EXTENDED_SDTR)) {
6730
6731 asc_dvc->init_sdtr &= ~target_id;
6732 asc_dvc->sdtr_done &= ~target_id;
6733 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6734 boardp->sdtr_data[tid_no] = asyn_sdtr;
6735 }
6736 q_cntl &= ~QC_MSG_OUT;
6737 AscWriteLramByte(iop_base,
6738 (ushort)(halt_q_addr +
6739 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6740 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6741 return (0);
6742 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
6743
6744 scsi_status = AscReadLramByte(iop_base,
6745 (ushort)((ushort)halt_q_addr +
6746 (ushort)
6747 ASC_SCSIQ_SCSI_STATUS));
6748 cur_dvc_qng =
6749 AscReadLramByte(iop_base,
6750 (ushort)((ushort)ASC_QADR_BEG +
6751 (ushort)target_ix));
6752 if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
6753
6754 scsi_busy = AscReadLramByte(iop_base,
6755 (ushort)ASCV_SCSIBUSY_B);
6756 scsi_busy |= target_id;
6757 AscWriteLramByte(iop_base,
6758 (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6759 asc_dvc->queue_full_or_busy |= target_id;
6760
6761 if (scsi_status == SAM_STAT_TASK_SET_FULL) {
6762 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
6763 cur_dvc_qng -= 1;
6764 asc_dvc->max_dvc_qng[tid_no] =
6765 cur_dvc_qng;
6766
6767 AscWriteLramByte(iop_base,
6768 (ushort)((ushort)
6769 ASCV_MAX_DVC_QNG_BEG
6770 + (ushort)
6771 tid_no),
6772 cur_dvc_qng);
6773
6774 /*
6775 * Set the device queue depth to the
6776 * number of active requests when the
6777 * QUEUE FULL condition was encountered.
6778 */
6779 boardp->queue_full |= target_id;
6780 boardp->queue_full_cnt[tid_no] =
6781 cur_dvc_qng;
6782 }
6783 }
6784 }
6785 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6786 return (0);
6787 }
6788#if CC_VERY_LONG_SG_LIST
6789 else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC) {
6790 uchar q_no;
6791 ushort q_addr;
6792 uchar sg_wk_q_no;
6793 uchar first_sg_wk_q_no;
6794 ASC_SCSI_Q *scsiq; /* Ptr to driver request. */
6795 ASC_SG_HEAD *sg_head; /* Ptr to driver SG request. */
6796 ASC_SG_LIST_Q scsi_sg_q; /* Structure written to queue. */
6797 ushort sg_list_dwords;
6798 ushort sg_entry_cnt;
6799 uchar next_qp;
6800 int i;
6801
6802 q_no = AscReadLramByte(iop_base, (ushort)ASCV_REQ_SG_LIST_QP);
6803 if (q_no == ASC_QLINK_END)
6804 return 0;
6805
6806 q_addr = ASC_QNO_TO_QADDR(q_no);
6807
6808 /*
6809 * Convert the request's SRB pointer to a host ASC_SCSI_REQ
6810 * structure pointer using a macro provided by the driver.
6811 * The ASC_SCSI_REQ pointer provides a pointer to the
6812 * host ASC_SG_HEAD structure.
6813 */
6814 /* Read request's SRB pointer. */
6815 scsiq = (ASC_SCSI_Q *)
6816 ASC_SRB2SCSIQ(ASC_U32_TO_VADDR(AscReadLramDWord(iop_base,
6817 (ushort)
6818 (q_addr +
6819 ASC_SCSIQ_D_SRBPTR))));
6820
6821 /*
6822 * Get request's first and working SG queue.
6823 */
6824 sg_wk_q_no = AscReadLramByte(iop_base,
6825 (ushort)(q_addr +
6826 ASC_SCSIQ_B_SG_WK_QP));
6827
6828 first_sg_wk_q_no = AscReadLramByte(iop_base,
6829 (ushort)(q_addr +
6830 ASC_SCSIQ_B_FIRST_SG_WK_QP));
6831
6832 /*
6833 * Reset request's working SG queue back to the
6834 * first SG queue.
6835 */
6836 AscWriteLramByte(iop_base,
6837 (ushort)(q_addr +
6838 (ushort)ASC_SCSIQ_B_SG_WK_QP),
6839 first_sg_wk_q_no);
6840
6841 sg_head = scsiq->sg_head;
6842
6843 /*
6844 * Set sg_entry_cnt to the number of SG elements
6845 * that will be completed on this interrupt.
6846 *
6847 * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
6848 * SG elements. The data_cnt and data_addr fields which
6849 * add 1 to the SG element capacity are not used when
6850 * restarting SG handling after a halt.
6851 */
6852 if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1)) {
6853 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
6854
6855 /*
6856 * Keep track of remaining number of SG elements that
6857 * will need to be handled on the next interrupt.
6858 */
6859 scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1);
6860 } else {
6861 sg_entry_cnt = scsiq->remain_sg_entry_cnt;
6862 scsiq->remain_sg_entry_cnt = 0;
6863 }
6864
6865 /*
6866 * Copy SG elements into the list of allocated SG queues.
6867 *
6868 * Last index completed is saved in scsiq->next_sg_index.
6869 */
6870 next_qp = first_sg_wk_q_no;
6871 q_addr = ASC_QNO_TO_QADDR(next_qp);
6872 scsi_sg_q.sg_head_qp = q_no;
6873 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
6874 for (i = 0; i < sg_head->queue_cnt; i++) {
6875 scsi_sg_q.seq_no = i + 1;
6876 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
6877 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
6878 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
6879 /*
6880 * After very first SG queue RISC FW uses next
6881 * SG queue first element then checks sg_list_cnt
6882 * against zero and then decrements, so set
6883 * sg_list_cnt 1 less than number of SG elements
6884 * in each SG queue.
6885 */
6886 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
6887 scsi_sg_q.sg_cur_list_cnt =
6888 ASC_SG_LIST_PER_Q - 1;
6889 } else {
6890 /*
6891 * This is the last SG queue in the list of
6892 * allocated SG queues. If there are more
6893 * SG elements than will fit in the allocated
6894 * queues, then set the QCSG_SG_XFER_MORE flag.
6895 */
6896 if (scsiq->remain_sg_entry_cnt != 0) {
6897 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
6898 } else {
6899 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
6900 }
6901 /* equals sg_entry_cnt * 2 */
6902 sg_list_dwords = sg_entry_cnt << 1;
6903 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
6904 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
6905 sg_entry_cnt = 0;
6906 }
6907
6908 scsi_sg_q.q_no = next_qp;
6909 AscMemWordCopyPtrToLram(iop_base,
6910 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
6911 (uchar *)&scsi_sg_q,
6912 sizeof(ASC_SG_LIST_Q) >> 1);
6913
6914 AscMemDWordCopyPtrToLram(iop_base,
6915 q_addr + ASC_SGQ_LIST_BEG,
6916 (uchar *)&sg_head->
6917 sg_list[scsiq->next_sg_index],
6918 sg_list_dwords);
6919
6920 scsiq->next_sg_index += ASC_SG_LIST_PER_Q;
6921
6922 /*
6923 * If the just completed SG queue contained the
6924 * last SG element, then no more SG queues need
6925 * to be written.
6926 */
6927 if (scsi_sg_q.cntl & QCSG_SG_XFER_END) {
6928 break;
6929 }
6930
6931 next_qp = AscReadLramByte(iop_base,
6932 (ushort)(q_addr +
6933 ASC_SCSIQ_B_FWD));
6934 q_addr = ASC_QNO_TO_QADDR(next_qp);
6935 }
6936
6937 /*
6938 * Clear the halt condition so the RISC will be restarted
6939 * after the return.
6940 */
6941 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6942 return (0);
6943 }
6944#endif /* CC_VERY_LONG_SG_LIST */
6945 return (0);
6946}
1da177e4 6947
1da177e4 6948/*
51219358
MW		 6949 * void
6950 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
1da177e4 6951 *
51219358
MW		 6952 * Calling/Exit State:
6953 * none
1da177e4 6954 *
51219358
MW		 6955 * Description:
6956 * Input an ASC_QDONE_INFO structure from the chip
1da177e4 6957 */
51219358
MW		 6958static void
6959DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
6960{
6961 int i;
6962 ushort word;
6963
6964 AscSetChipLramAddr(iop_base, s_addr);
6965 for (i = 0; i < 2 * words; i += 2) {
6966 if (i == 10) {
6967 continue;
6968 }
6969 word = inpw(iop_base + IOP_RAM_DATA);
6970 inbuf[i] = word & 0xff;
6971 inbuf[i + 1] = (word >> 8) & 0xff;
6972 }
6973 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
6974}
6975
6976static uchar
6977_AscCopyLramScsiDoneQ(PortAddr iop_base,
6978 ushort q_addr,
6979 ASC_QDONE_INFO *scsiq, ASC_DCNT max_dma_count)
6980{
6981 ushort _val;
6982 uchar sg_queue_cnt;
6983
6984 DvcGetQinfo(iop_base,
6985 q_addr + ASC_SCSIQ_DONE_INFO_BEG,
6986 (uchar *)scsiq,
6987 (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2);
6988
6989 _val = AscReadLramWord(iop_base,
6990 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS));
6991 scsiq->q_status = (uchar)_val;
6992 scsiq->q_no = (uchar)(_val >> 8);
6993 _val = AscReadLramWord(iop_base,
6994 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL));
6995 scsiq->cntl = (uchar)_val;
6996 sg_queue_cnt = (uchar)(_val >> 8);
6997 _val = AscReadLramWord(iop_base,
6998 (ushort)(q_addr +
6999 (ushort)ASC_SCSIQ_B_SENSE_LEN));
7000 scsiq->sense_len = (uchar)_val;
7001 scsiq->extra_bytes = (uchar)(_val >> 8);
7002
7003 /*
7004 * Read high word of remain bytes from alternate location.
7005 */
7006 scsiq->remain_bytes = (((ADV_DCNT)AscReadLramWord(iop_base,
7007 (ushort)(q_addr +
7008 (ushort)
7009 ASC_SCSIQ_W_ALT_DC1)))
7010 << 16);
7011 /*
7012 * Read low word of remain bytes from original location.
7013 */
7014 scsiq->remain_bytes += AscReadLramWord(iop_base,
7015 (ushort)(q_addr + (ushort)
7016 ASC_SCSIQ_DW_REMAIN_XFER_CNT));
7017
7018 scsiq->remain_bytes &= max_dma_count;
7019 return sg_queue_cnt;
7020}
7021
7022/*
7023 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
7024 *
7025 * Interrupt callback function for the Narrow SCSI Asc Library.
7026 */
7027static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
7028{
9c17c62a
HR		 7029 struct asc_board *boardp = asc_dvc_varp->drv_ptr;
7030 u32 srb_tag;
51219358 7031 struct scsi_cmnd *scp;
51219358 7032
b352f923 7033 ASC_DBG(1, "asc_dvc_varp 0x%p, qdonep 0x%p\n", asc_dvc_varp, qdonep);
51219358
MW		 7034 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
7035
9c17c62a
HR		 7036 /*
7037 * Decrease the srb_tag by 1 to find the SCSI command
7038 */
7039 srb_tag = qdonep->d2.srb_tag - 1;
7040 scp = scsi_host_find_tag(boardp->shost, srb_tag);
b249c7fd 7041 if (!scp)
51219358 7042 return;
b249c7fd 7043
51219358
MW		 7044 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
7045
9c17c62a 7046 ASC_STATS(boardp->shost, callback);
51219358 7047
b249c7fd 7048 dma_unmap_single(boardp->dev, scp->SCp.dma_handle,
b80ca4f7 7049 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
51219358
MW		 7050 /*
7051 * 'qdonep' contains the command's ending status.
7052 */
7053 switch (qdonep->d3.done_stat) {
7054 case QD_NO_ERROR:
b352f923 7055 ASC_DBG(2, "QD_NO_ERROR\n");
51219358
MW		 7056 scp->result = 0;
7057
7058 /*
7059 * Check for an underrun condition.
7060 *
7061 * If there was no error and an underrun condition, then
7062 * return the number of underrun bytes.
7063 */
52c334e9
MW		 7064 if (scsi_bufflen(scp) != 0 && qdonep->remain_bytes != 0 &&
7065 qdonep->remain_bytes <= scsi_bufflen(scp)) {
b352f923 7066 ASC_DBG(1, "underrun condition %u bytes\n",
51219358 7067 (unsigned)qdonep->remain_bytes);
52c334e9 7068 scsi_set_resid(scp, qdonep->remain_bytes);
51219358
MW		 7069 }
7070 break;
7071
7072 case QD_WITH_ERROR:
b352f923 7073 ASC_DBG(2, "QD_WITH_ERROR\n");
51219358
MW		 7074 switch (qdonep->d3.host_stat) {
7075 case QHSTA_NO_ERROR:
7076 if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
b352f923 7077 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
51219358 7078 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
b80ca4f7 7079 SCSI_SENSE_BUFFERSIZE);
51219358
MW		 7080 /*
7081 * Note: The 'status_byte()' macro used by
7082 * target drivers defined in scsi.h shifts the
7083 * status byte returned by host drivers right
7084 * by 1 bit. This is why target drivers also
7085 * use right shifted status byte definitions.
7086 * For instance target drivers use
7087 * CHECK_CONDITION, defined to 0x1, instead of
7088 * the SCSI defined check condition value of
7089 * 0x2. Host drivers are supposed to return
7090 * the status byte as it is defined by SCSI.
7091 */
7092 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
7093 STATUS_BYTE(qdonep->d3.scsi_stat);
7094 } else {
7095 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
7096 }
7097 break;
7098
7099 default:
7100 /* QHSTA error occurred */
b352f923 7101 ASC_DBG(1, "host_stat 0x%x\n", qdonep->d3.host_stat);
51219358
MW		 7102 scp->result = HOST_BYTE(DID_BAD_TARGET);
7103 break;
7104 }
7105 break;
7106
7107 case QD_ABORTED_BY_HOST:
b352f923 7108 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
51219358
MW		 7109 scp->result =
7110 HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.
7111 scsi_msg) |
7112 STATUS_BYTE(qdonep->d3.scsi_stat);
7113 break;
7114
7115 default:
b352f923 7116 ASC_DBG(1, "done_stat 0x%x\n", qdonep->d3.done_stat);
51219358
MW		 7117 scp->result =
7118 HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.
7119 scsi_msg) |
7120 STATUS_BYTE(qdonep->d3.scsi_stat);
7121 break;
7122 }
7123
7124 /*
7125 * If the 'init_tidmask' bit isn't already set for the target and the
7126 * current request finished normally, then set the bit for the target
7127 * to indicate that a device is present.
7128 */
7129 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
7130 qdonep->d3.done_stat == QD_NO_ERROR &&
7131 qdonep->d3.host_stat == QHSTA_NO_ERROR) {
7132 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
7133 }
1da177e4 7134
51219358 7135 asc_scsi_done(scp);
51219358
MW		 7136}
7137
7138static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
7139{
7140 uchar next_qp;
7141 uchar n_q_used;
7142 uchar sg_list_qp;
7143 uchar sg_queue_cnt;
7144 uchar q_cnt;
7145 uchar done_q_tail;
7146 uchar tid_no;
7147 ASC_SCSI_BIT_ID_TYPE scsi_busy;
7148 ASC_SCSI_BIT_ID_TYPE target_id;
7149 PortAddr iop_base;
7150 ushort q_addr;
7151 ushort sg_q_addr;
7152 uchar cur_target_qng;
7153 ASC_QDONE_INFO scsiq_buf;
7154 ASC_QDONE_INFO *scsiq;
7155 int false_overrun;
7156
7157 iop_base = asc_dvc->iop_base;
7158 n_q_used = 1;
7159 scsiq = (ASC_QDONE_INFO *)&scsiq_buf;
7160 done_q_tail = (uchar)AscGetVarDoneQTail(iop_base);
7161 q_addr = ASC_QNO_TO_QADDR(done_q_tail);
7162 next_qp = AscReadLramByte(iop_base,
7163 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD));
7164 if (next_qp != ASC_QLINK_END) {
7165 AscPutVarDoneQTail(iop_base, next_qp);
7166 q_addr = ASC_QNO_TO_QADDR(next_qp);
7167 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
7168 asc_dvc->max_dma_count);
7169 AscWriteLramByte(iop_base,
7170 (ushort)(q_addr +
7171 (ushort)ASC_SCSIQ_B_STATUS),
7172 (uchar)(scsiq->
7173 q_status & (uchar)~(QS_READY |
7174 QS_ABORTED)));
7175 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
7176 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
7177 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
7178 sg_q_addr = q_addr;
7179 sg_list_qp = next_qp;
7180 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
7181 sg_list_qp = AscReadLramByte(iop_base,
7182 (ushort)(sg_q_addr
7183 + (ushort)
7184 ASC_SCSIQ_B_FWD));
7185 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
7186 if (sg_list_qp == ASC_QLINK_END) {
7187 AscSetLibErrorCode(asc_dvc,
7188 ASCQ_ERR_SG_Q_LINKS);
7189 scsiq->d3.done_stat = QD_WITH_ERROR;
7190 scsiq->d3.host_stat =
7191 QHSTA_D_QDONE_SG_LIST_CORRUPTED;
7192 goto FATAL_ERR_QDONE;
7193 }
7194 AscWriteLramByte(iop_base,
7195 (ushort)(sg_q_addr + (ushort)
7196 ASC_SCSIQ_B_STATUS),
7197 QS_FREE);
7198 }
7199 n_q_used = sg_queue_cnt + 1;
7200 AscPutVarDoneQTail(iop_base, sg_list_qp);
7201 }
7202 if (asc_dvc->queue_full_or_busy & target_id) {
7203 cur_target_qng = AscReadLramByte(iop_base,
7204 (ushort)((ushort)
7205 ASC_QADR_BEG
7206 + (ushort)
7207 scsiq->d2.
7208 target_ix));
7209 if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
7210 scsi_busy = AscReadLramByte(iop_base, (ushort)
7211 ASCV_SCSIBUSY_B);
7212 scsi_busy &= ~target_id;
7213 AscWriteLramByte(iop_base,
7214 (ushort)ASCV_SCSIBUSY_B,
7215 scsi_busy);
7216 asc_dvc->queue_full_or_busy &= ~target_id;
7217 }
7218 }
7219 if (asc_dvc->cur_total_qng >= n_q_used) {
7220 asc_dvc->cur_total_qng -= n_q_used;
7221 if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
7222 asc_dvc->cur_dvc_qng[tid_no]--;
7223 }
7224 } else {
7225 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
7226 scsiq->d3.done_stat = QD_WITH_ERROR;
7227 goto FATAL_ERR_QDONE;
7228 }
9c17c62a 7229 if ((scsiq->d2.srb_tag == 0UL) ||
51219358
MW		 7230 ((scsiq->q_status & QS_ABORTED) != 0)) {
7231 return (0x11);
7232 } else if (scsiq->q_status == QS_DONE) {
7233 false_overrun = FALSE;
7234 if (scsiq->extra_bytes != 0) {
7235 scsiq->remain_bytes +=
7236 (ADV_DCNT)scsiq->extra_bytes;
7237 }
7238 if (scsiq->d3.done_stat == QD_WITH_ERROR) {
7239 if (scsiq->d3.host_stat ==
7240 QHSTA_M_DATA_OVER_RUN) {
7241 if ((scsiq->
7242 cntl & (QC_DATA_IN | QC_DATA_OUT))
7243 == 0) {
7244 scsiq->d3.done_stat =
7245 QD_NO_ERROR;
7246 scsiq->d3.host_stat =
7247 QHSTA_NO_ERROR;
7248 } else if (false_overrun) {
7249 scsiq->d3.done_stat =
7250 QD_NO_ERROR;
7251 scsiq->d3.host_stat =
7252 QHSTA_NO_ERROR;
7253 }
7254 } else if (scsiq->d3.host_stat ==
7255 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
7256 AscStopChip(iop_base);
7257 AscSetChipControl(iop_base,
7258 (uchar)(CC_SCSI_RESET
7259 | CC_HALT));
7260 udelay(60);
7261 AscSetChipControl(iop_base, CC_HALT);
7262 AscSetChipStatus(iop_base,
7263 CIW_CLR_SCSI_RESET_INT);
7264 AscSetChipStatus(iop_base, 0);
7265 AscSetChipControl(iop_base, 0);
7266 }
7267 }
7268 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7269 asc_isr_callback(asc_dvc, scsiq);
7270 } else {
7271 if ((AscReadLramByte(iop_base,
7272 (ushort)(q_addr + (ushort)
7273 ASC_SCSIQ_CDB_BEG))
7274 == START_STOP)) {
7275 asc_dvc->unit_not_ready &= ~target_id;
7276 if (scsiq->d3.done_stat != QD_NO_ERROR) {
7277 asc_dvc->start_motor &=
7278 ~target_id;
7279 }
7280 }
7281 }
7282 return (1);
7283 } else {
7284 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
7285 FATAL_ERR_QDONE:
7286 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7287 asc_isr_callback(asc_dvc, scsiq);
7288 }
7289 return (0x80);
7290 }
7291 }
7292 return (0);
7293}
1da177e4 7294
51219358
MW		 7295static int AscISR(ASC_DVC_VAR *asc_dvc)
7296{
7297 ASC_CS_TYPE chipstat;
7298 PortAddr iop_base;
7299 ushort saved_ram_addr;
7300 uchar ctrl_reg;
7301 uchar saved_ctrl_reg;
7302 int int_pending;
7303 int status;
7304 uchar host_flag;
1da177e4 7305
51219358
MW		 7306 iop_base = asc_dvc->iop_base;
7307 int_pending = FALSE;
1da177e4 7308
51219358
MW		 7309 if (AscIsIntPending(iop_base) == 0)
7310 return int_pending;
7311
7312 if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) {
7313 return ERR;
7314 }
7315 if (asc_dvc->in_critical_cnt != 0) {
7316 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
7317 return ERR;
7318 }
7319 if (asc_dvc->is_in_int) {
7320 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
7321 return ERR;
7322 }
7323 asc_dvc->is_in_int = TRUE;
7324 ctrl_reg = AscGetChipControl(iop_base);
7325 saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
7326 CC_SINGLE_STEP | CC_DIAG | CC_TEST));
7327 chipstat = AscGetChipStatus(iop_base);
7328 if (chipstat & CSW_SCSI_RESET_LATCH) {
7329 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
7330 int i = 10;
7331 int_pending = TRUE;
7332 asc_dvc->sdtr_done = 0;
7333 saved_ctrl_reg &= (uchar)(~CC_HALT);
7334 while ((AscGetChipStatus(iop_base) &
7335 CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) {
7336 mdelay(100);
7337 }
7338 AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
7339 AscSetChipControl(iop_base, CC_HALT);
7340 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
7341 AscSetChipStatus(iop_base, 0);
7342 chipstat = AscGetChipStatus(iop_base);
7343 }
7344 }
7345 saved_ram_addr = AscGetChipLramAddr(iop_base);
7346 host_flag = AscReadLramByte(iop_base,
7347 ASCV_HOST_FLAG_B) &
7348 (uchar)(~ASC_HOST_FLAG_IN_ISR);
7349 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
7350 (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR));
7351 if ((chipstat & CSW_INT_PENDING) || (int_pending)) {
7352 AscAckInterrupt(iop_base);
7353 int_pending = TRUE;
7354 if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {
7355 if (AscIsrChipHalted(asc_dvc) == ERR) {
7356 goto ISR_REPORT_QDONE_FATAL_ERROR;
7357 } else {
7358 saved_ctrl_reg &= (uchar)(~CC_HALT);
7359 }
7360 } else {
7361 ISR_REPORT_QDONE_FATAL_ERROR:
7362 if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
7363 while (((status =
7364 AscIsrQDone(asc_dvc)) & 0x01) != 0) {
7365 }
7366 } else {
7367 do {
7368 if ((status =
7369 AscIsrQDone(asc_dvc)) == 1) {
7370 break;
7371 }
7372 } while (status == 0x11);
7373 }
7374 if ((status & 0x80) != 0)
7375 int_pending = ERR;
7376 }
7377 }
7378 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
7379 AscSetChipLramAddr(iop_base, saved_ram_addr);
7380 AscSetChipControl(iop_base, saved_ctrl_reg);
7381 asc_dvc->is_in_int = FALSE;
7382 return int_pending;
7383}
1da177e4
LT		 7384
7385/*
51219358 7386 * advansys_reset()
1da177e4 7387 *
eac0b0c7 7388 * Reset the host associated with the command 'scp'.
1da177e4 7389 *
51219358
MW		 7390 * This function runs its own thread. Interrupts must be blocked but
7391 * sleeping is allowed and no locking other than for host structures is
7392 * required. Returns SUCCESS or FAILED.
1da177e4 7393 */
51219358 7394static int advansys_reset(struct scsi_cmnd *scp)
1da177e4 7395{
52fa0777 7396 struct Scsi_Host *shost = scp->device->host;
d2411495 7397 struct asc_board *boardp = shost_priv(shost);
52fa0777 7398 unsigned long flags;
27c868c2 7399 int status;
51219358 7400 int ret = SUCCESS;
27c868c2 7401
b352f923 7402 ASC_DBG(1, "0x%p\n", scp);
27c868c2 7403
52fa0777 7404 ASC_STATS(shost, reset);
27c868c2 7405
eac0b0c7 7406 scmd_printk(KERN_INFO, scp, "SCSI host reset started...\n");
51219358
MW		 7407
7408 if (ASC_NARROW_BOARD(boardp)) {
52fa0777 7409 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
1da177e4 7410
52fa0777 7411 /* Reset the chip and SCSI bus. */
b352f923 7412 ASC_DBG(1, "before AscInitAsc1000Driver()\n");
52fa0777 7413 status = AscInitAsc1000Driver(asc_dvc);
27c868c2 7414
6070d81e 7415 /* Refer to ASC_IERR_* definitions for meaning of 'err_code'. */
9a908c1a 7416 if (asc_dvc->err_code || !asc_dvc->overrun_dma) {
eac0b0c7 7417 scmd_printk(KERN_INFO, scp, "SCSI host reset error: "
9a908c1a
HRK		 7418 "0x%x, status: 0x%x\n", asc_dvc->err_code,
7419 status);
51219358
MW		 7420 ret = FAILED;
7421 } else if (status) {
eac0b0c7 7422 scmd_printk(KERN_INFO, scp, "SCSI host reset warning: "
52fa0777 7423 "0x%x\n", status);
27c868c2 7424 } else {
eac0b0c7 7425 scmd_printk(KERN_INFO, scp, "SCSI host reset "
52fa0777 7426 "successful\n");
27c868c2 7427 }
a9f4a59a 7428
b352f923 7429 ASC_DBG(1, "after AscInitAsc1000Driver()\n");
a9f4a59a 7430 } else {
a9f4a59a 7431 /*
51219358
MW		 7432 * If the suggest reset bus flags are set, then reset the bus.
7433 * Otherwise only reset the device.
a9f4a59a 7434 */
52fa0777 7435 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
a9f4a59a
MW		 7436
7437 /*
eac0b0c7 7438 * Reset the chip and SCSI bus.
a9f4a59a 7439 */
b352f923 7440 ASC_DBG(1, "before AdvResetChipAndSB()\n");
52fa0777 7441 switch (AdvResetChipAndSB(adv_dvc)) {
51219358 7442 case ASC_TRUE:
eac0b0c7 7443 scmd_printk(KERN_INFO, scp, "SCSI host reset "
52fa0777 7444 "successful\n");
51219358
MW		 7445 break;
7446 case ASC_FALSE:
7447 default:
eac0b0c7 7448 scmd_printk(KERN_INFO, scp, "SCSI host reset error\n");
51219358
MW		 7449 ret = FAILED;
7450 break;
b9d96614 7451 }
f092d229 7452 spin_lock_irqsave(shost->host_lock, flags);
52fa0777 7453 AdvISR(adv_dvc);
eac0b0c7 7454 spin_unlock_irqrestore(shost->host_lock, flags);
b9d96614
MW		 7455 }
7456
b352f923 7457 ASC_DBG(1, "ret %d\n", ret);
b9d96614 7458
51219358 7459 return ret;
b9d96614
MW		 7460}
7461
1da177e4 7462/*
51219358 7463 * advansys_biosparam()
1da177e4 7464 *
51219358
MW		 7465 * Translate disk drive geometry if the "BIOS greater than 1 GB"
7466 * support is enabled for a drive.
1da177e4 7467 *
51219358
MW		 7468 * ip (information pointer) is an int array with the following definition:
7469 * ip[0]: heads
7470 * ip[1]: sectors
7471 * ip[2]: cylinders
1da177e4 7472 */
51219358
MW		 7473static int
7474advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
7475 sector_t capacity, int ip[])
1da177e4 7476{
d2411495 7477 struct asc_board *boardp = shost_priv(sdev->host);
1da177e4 7478
b352f923 7479 ASC_DBG(1, "begin\n");
51219358 7480 ASC_STATS(sdev->host, biosparam);
51219358
MW		 7481 if (ASC_NARROW_BOARD(boardp)) {
7482 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
7483 ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
7484 ip[0] = 255;
7485 ip[1] = 63;
7486 } else {
7487 ip[0] = 64;
7488 ip[1] = 32;
7489 }
7490 } else {
7491 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
7492 BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
7493 ip[0] = 255;
7494 ip[1] = 63;
7495 } else {
7496 ip[0] = 64;
7497 ip[1] = 32;
7498 }
27c868c2 7499 }
51219358 7500 ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
b352f923 7501 ASC_DBG(1, "end\n");
51219358
MW		 7502 return 0;
7503}
1da177e4 7504
51219358
MW		 7505/*
7506 * First-level interrupt handler.
7507 *
7508 * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host.
7509 */
7510static irqreturn_t advansys_interrupt(int irq, void *dev_id)
7511{
51219358 7512 struct Scsi_Host *shost = dev_id;
d2411495 7513 struct asc_board *boardp = shost_priv(shost);
51219358 7514 irqreturn_t result = IRQ_NONE;
27c868c2 7515
b352f923 7516 ASC_DBG(2, "boardp 0x%p\n", boardp);
f092d229 7517 spin_lock(shost->host_lock);
51219358
MW		 7518 if (ASC_NARROW_BOARD(boardp)) {
7519 if (AscIsIntPending(shost->io_port)) {
7520 result = IRQ_HANDLED;
7521 ASC_STATS(shost, interrupt);
b352f923 7522 ASC_DBG(1, "before AscISR()\n");
51219358
MW		 7523 AscISR(&boardp->dvc_var.asc_dvc_var);
7524 }
7525 } else {
b352f923 7526 ASC_DBG(1, "before AdvISR()\n");
51219358
MW		 7527 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
7528 result = IRQ_HANDLED;
7529 ASC_STATS(shost, interrupt);
7530 }
27c868c2 7531 }
f092d229 7532 spin_unlock(shost->host_lock);
1da177e4 7533
b352f923 7534 ASC_DBG(1, "end\n");
51219358
MW		 7535 return result;
7536}
27c868c2 7537
51219358
MW		 7538static int AscHostReqRiscHalt(PortAddr iop_base)
7539{
7540 int count = 0;
7541 int sta = 0;
7542 uchar saved_stop_code;
7543
7544 if (AscIsChipHalted(iop_base))
7545 return (1);
7546 saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
7547 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
7548 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP);
7549 do {
7550 if (AscIsChipHalted(iop_base)) {
7551 sta = 1;
7552 break;
27c868c2 7553 }
51219358
MW		 7554 mdelay(100);
7555 } while (count++ < 20);
7556 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
7557 return (sta);
7558}
1da177e4 7559
51219358
MW		 7560static int
7561AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data)
7562{
7563 int sta = FALSE;
1da177e4 7564
51219358
MW		 7565 if (AscHostReqRiscHalt(iop_base)) {
7566 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
7567 AscStartChip(iop_base);
27c868c2 7568 }
51219358
MW		 7569 return sta;
7570}
1da177e4 7571
51219358
MW		 7572static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev)
7573{
7574 char type = sdev->type;
7575 ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id;
27c868c2 7576
51219358
MW		 7577 if (!(asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN))
7578 return;
7579 if (asc_dvc->init_sdtr & tid_bits)
7580 return;
27c868c2 7581
51219358
MW		 7582 if ((type == TYPE_ROM) && (strncmp(sdev->vendor, "HP ", 3) == 0))
7583 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
27c868c2 7584
51219358
MW		 7585 asc_dvc->pci_fix_asyn_xfer |= tid_bits;
7586 if ((type == TYPE_PROCESSOR) || (type == TYPE_SCANNER) ||
7587 (type == TYPE_ROM) || (type == TYPE_TAPE))
7588 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
7589
7590 if (asc_dvc->pci_fix_asyn_xfer & tid_bits)
7591 AscSetRunChipSynRegAtID(asc_dvc->iop_base, sdev->id,
7592 ASYN_SDTR_DATA_FIX_PCI_REV_AB);
7593}
1da177e4 7594
51219358
MW		 7595static void
7596advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc)
7597{
7598 ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id;
7599 ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng;
27c868c2 7600
51219358
MW		 7601 if (sdev->lun == 0) {
7602 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr;
7603 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) {
7604 asc_dvc->init_sdtr |= tid_bit;
7605 } else {
7606 asc_dvc->init_sdtr &= ~tid_bit;
7607 }
7608
7609 if (orig_init_sdtr != asc_dvc->init_sdtr)
7610 AscAsyncFix(asc_dvc, sdev);
27c868c2 7611 }
1da177e4 7612
51219358
MW		 7613 if (sdev->tagged_supported) {
7614 if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) {
7615 if (sdev->lun == 0) {
7616 asc_dvc->cfg->can_tagged_qng |= tid_bit;
7617 asc_dvc->use_tagged_qng |= tid_bit;
7618 }
db5ed4df 7619 scsi_change_queue_depth(sdev,
51219358 7620 asc_dvc->max_dvc_qng[sdev->id]);
27c868c2 7621 }
51219358
MW		 7622 } else {
7623 if (sdev->lun == 0) {
7624 asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
7625 asc_dvc->use_tagged_qng &= ~tid_bit;
27c868c2
MW		 7626 }
7627 }
1da177e4 7628
51219358
MW		 7629 if ((sdev->lun == 0) &&
7630 (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) {
7631 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
7632 asc_dvc->cfg->disc_enable);
7633 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
7634 asc_dvc->use_tagged_qng);
7635 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
7636 asc_dvc->cfg->can_tagged_qng);
27c868c2 7637
51219358
MW		 7638 asc_dvc->max_dvc_qng[sdev->id] =
7639 asc_dvc->cfg->max_tag_qng[sdev->id];
7640 AscWriteLramByte(asc_dvc->iop_base,
7641 (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id),
7642 asc_dvc->max_dvc_qng[sdev->id]);
7643 }
7644}
27c868c2 7645
51219358
MW		 7646/*
7647 * Wide Transfers
7648 *
7649 * If the EEPROM enabled WDTR for the device and the device supports wide
7650 * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and
7651 * write the new value to the microcode.
7652 */
7653static void
7654advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask)
7655{
7656 unsigned short cfg_word;
7657 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
7658 if ((cfg_word & tidmask) != 0)
7659 return;
27c868c2 7660
51219358
MW		 7661 cfg_word |= tidmask;
7662 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
27c868c2
MW		 7663
7664 /*
51219358
MW		 7665 * Clear the microcode SDTR and WDTR negotiation done indicators for
7666 * the target to cause it to negotiate with the new setting set above.
7667 * WDTR when accepted causes the target to enter asynchronous mode, so
7668 * SDTR must be negotiated.
27c868c2 7669 */
51219358
MW		 7670 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7671 cfg_word &= ~tidmask;
7672 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7673 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
7674 cfg_word &= ~tidmask;
7675 AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
7676}
1da177e4 7677
51219358
MW		 7678/*
7679 * Synchronous Transfers
7680 *
7681 * If the EEPROM enabled SDTR for the device and the device
7682 * supports synchronous transfers, then turn on the device's
7683 * 'sdtr_able' bit. Write the new value to the microcode.
7684 */
7685static void
7686advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask)
7687{
7688 unsigned short cfg_word;
7689 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
7690 if ((cfg_word & tidmask) != 0)
7691 return;
1da177e4 7692
51219358
MW		 7693 cfg_word |= tidmask;
7694 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
1da177e4 7695
27c868c2 7696 /*
51219358
MW		 7697 * Clear the microcode "SDTR negotiation" done indicator for the
7698 * target to cause it to negotiate with the new setting set above.
27c868c2 7699 */
51219358
MW		 7700 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7701 cfg_word &= ~tidmask;
7702 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7703}
27c868c2 7704
51219358
MW		 7705/*
7706 * PPR (Parallel Protocol Request) Capable
7707 *
7708 * If the device supports DT mode, then it must be PPR capable.
7709 * The PPR message will be used in place of the SDTR and WDTR
7710 * messages to negotiate synchronous speed and offset, transfer
7711 * width, and protocol options.
7712 */
7713static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc,
7714 AdvPortAddr iop_base, unsigned short tidmask)
7715{
7716 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
7717 adv_dvc->ppr_able |= tidmask;
7718 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
7719}
27c868c2 7720
51219358
MW		 7721static void
7722advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc)
7723{
7724 AdvPortAddr iop_base = adv_dvc->iop_base;
7725 unsigned short tidmask = 1 << sdev->id;
7726
7727 if (sdev->lun == 0) {
7728 /*
7729 * Handle WDTR, SDTR, and Tag Queuing. If the feature
7730 * is enabled in the EEPROM and the device supports the
7731 * feature, then enable it in the microcode.
7732 */
27c868c2 7733
51219358
MW		 7734 if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr)
7735 advansys_wide_enable_wdtr(iop_base, tidmask);
7736 if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr)
7737 advansys_wide_enable_sdtr(iop_base, tidmask);
7738 if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr)
7739 advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask);
7740
7741 /*
7742 * Tag Queuing is disabled for the BIOS which runs in polled
7743 * mode and would see no benefit from Tag Queuing. Also by
7744 * disabling Tag Queuing in the BIOS devices with Tag Queuing
7745 * bugs will at least work with the BIOS.
7746 */
7747 if ((adv_dvc->tagqng_able & tidmask) &&
7748 sdev->tagged_supported) {
7749 unsigned short cfg_word;
7750 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
7751 cfg_word |= tidmask;
7752 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
7753 cfg_word);
7754 AdvWriteByteLram(iop_base,
7755 ASC_MC_NUMBER_OF_MAX_CMD + sdev->id,
7756 adv_dvc->max_dvc_qng);
27c868c2
MW		 7757 }
7758 }
1da177e4 7759
db5ed4df
CH		 7760 if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported)
7761 scsi_change_queue_depth(sdev, adv_dvc->max_dvc_qng);
51219358 7762}
27c868c2 7763
51219358
MW		 7764/*
7765 * Set the number of commands to queue per device for the
7766 * specified host adapter.
7767 */
7768static int advansys_slave_configure(struct scsi_device *sdev)
7769{
d2411495 7770 struct asc_board *boardp = shost_priv(sdev->host);
27c868c2 7771
51219358
MW		 7772 if (ASC_NARROW_BOARD(boardp))
7773 advansys_narrow_slave_configure(sdev,
7774 &boardp->dvc_var.asc_dvc_var);
7775 else
7776 advansys_wide_slave_configure(sdev,
7777 &boardp->dvc_var.adv_dvc_var);
1da177e4 7778
51219358
MW		 7779 return 0;
7780}
27c868c2 7781
b249c7fd
MW		 7782static __le32 advansys_get_sense_buffer_dma(struct scsi_cmnd *scp)
7783{
7784 struct asc_board *board = shost_priv(scp->device->host);
7785 scp->SCp.dma_handle = dma_map_single(board->dev, scp->sense_buffer,
b80ca4f7 7786 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
b249c7fd 7787 dma_cache_sync(board->dev, scp->sense_buffer,
b80ca4f7 7788 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
b249c7fd
MW		 7789 return cpu_to_le32(scp->SCp.dma_handle);
7790}
7791
d2411495 7792static int asc_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
05848b6e 7793 struct asc_scsi_q *asc_scsi_q)
51219358 7794{
b249c7fd 7795 struct asc_dvc_var *asc_dvc = &boardp->dvc_var.asc_dvc_var;
52c334e9 7796 int use_sg;
9c17c62a 7797 u32 srb_tag;
52c334e9 7798
05848b6e 7799 memset(asc_scsi_q, 0, sizeof(*asc_scsi_q));
27c868c2
MW		 7800
7801 /*
9c17c62a
HR		 7802 * Set the srb_tag to the command tag + 1, as
7803 * srb_tag '0' is used internally by the chip.
27c868c2 7804 */
9c17c62a
HR		 7805 srb_tag = scp->request->tag + 1;
7806 asc_scsi_q->q2.srb_tag = srb_tag;
27c868c2
MW		 7807
7808 /*
51219358 7809 * Build the ASC_SCSI_Q request.
27c868c2 7810 */
05848b6e
MW		 7811 asc_scsi_q->cdbptr = &scp->cmnd[0];
7812 asc_scsi_q->q2.cdb_len = scp->cmd_len;
7813 asc_scsi_q->q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
7814 asc_scsi_q->q1.target_lun = scp->device->lun;
7815 asc_scsi_q->q2.target_ix =
51219358 7816 ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
b249c7fd 7817 asc_scsi_q->q1.sense_addr = advansys_get_sense_buffer_dma(scp);
b80ca4f7 7818 asc_scsi_q->q1.sense_len = SCSI_SENSE_BUFFERSIZE;
27c868c2
MW		 7819
7820 /*
51219358
MW		 7821 * If there are any outstanding requests for the current target,
7822 * then every 255th request send an ORDERED request. This heuristic
7823 * tries to retain the benefit of request sorting while preventing
7824 * request starvation. 255 is the max number of tags or pending commands
7825 * a device may have outstanding.
7826 *
7827 * The request count is incremented below for every successfully
7828 * started request.
27c868c2 7829 *
27c868c2 7830 */
b249c7fd 7831 if ((asc_dvc->cur_dvc_qng[scp->device->id] > 0) &&
51219358 7832 (boardp->reqcnt[scp->device->id] % 255) == 0) {
68d81f40 7833 asc_scsi_q->q2.tag_code = ORDERED_QUEUE_TAG;
51219358 7834 } else {
68d81f40 7835 asc_scsi_q->q2.tag_code = SIMPLE_QUEUE_TAG;
51219358 7836 }
27c868c2 7837
52c334e9
MW		 7838 /* Build ASC_SCSI_Q */
7839 use_sg = scsi_dma_map(scp);
7840 if (use_sg != 0) {
51219358 7841 int sgcnt;
51219358 7842 struct scatterlist *slp;
05848b6e 7843 struct asc_sg_head *asc_sg_head;
27c868c2 7844
51219358 7845 if (use_sg > scp->device->host->sg_tablesize) {
9d0e96eb
MW		 7846 scmd_printk(KERN_ERR, scp, "use_sg %d > "
7847 "sg_tablesize %d\n", use_sg,
7848 scp->device->host->sg_tablesize);
52c334e9 7849 scsi_dma_unmap(scp);
51219358
MW		 7850 scp->result = HOST_BYTE(DID_ERROR);
7851 return ASC_ERROR;
7852 }
27c868c2 7853
05848b6e
MW		 7854 asc_sg_head = kzalloc(sizeof(asc_scsi_q->sg_head) +
7855 use_sg * sizeof(struct asc_sg_list), GFP_ATOMIC);
7856 if (!asc_sg_head) {
52c334e9 7857 scsi_dma_unmap(scp);
05848b6e
MW		 7858 scp->result = HOST_BYTE(DID_SOFT_ERROR);
7859 return ASC_ERROR;
7860 }
51219358 7861
05848b6e
MW		 7862 asc_scsi_q->q1.cntl |= QC_SG_HEAD;
7863 asc_scsi_q->sg_head = asc_sg_head;
7864 asc_scsi_q->q1.data_cnt = 0;
7865 asc_scsi_q->q1.data_addr = 0;
51219358 7866 /* This is a byte value, otherwise it would need to be swapped. */
05848b6e 7867 asc_sg_head->entry_cnt = asc_scsi_q->q1.sg_queue_cnt = use_sg;
52c334e9 7868 ASC_STATS_ADD(scp->device->host, xfer_elem,
05848b6e 7869 asc_sg_head->entry_cnt);
51219358
MW		 7870
7871 /*
7872 * Convert scatter-gather list into ASC_SG_HEAD list.
7873 */
52c334e9 7874 scsi_for_each_sg(scp, slp, use_sg, sgcnt) {
05848b6e 7875 asc_sg_head->sg_list[sgcnt].addr =
51219358 7876 cpu_to_le32(sg_dma_address(slp));
05848b6e 7877 asc_sg_head->sg_list[sgcnt].bytes =
51219358 7878 cpu_to_le32(sg_dma_len(slp));
52c334e9
MW		 7879 ASC_STATS_ADD(scp->device->host, xfer_sect,
7880 DIV_ROUND_UP(sg_dma_len(slp), 512));
27c868c2
MW		 7881 }
7882 }
1da177e4 7883
52c334e9
MW		 7884 ASC_STATS(scp->device->host, xfer_cnt);
7885
b352f923 7886 ASC_DBG_PRT_ASC_SCSI_Q(2, asc_scsi_q);
51219358
MW		 7887 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
7888
7889 return ASC_NOERROR;
27c868c2 7890}
1da177e4 7891
27c868c2 7892/*
51219358 7893 * Build scatter-gather list for Adv Library (Wide Board).
27c868c2 7894 *
51219358
MW		 7895 * Additional ADV_SG_BLOCK structures will need to be allocated
7896 * if the total number of scatter-gather elements exceeds
7897 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
7898 * assumed to be physically contiguous.
27c868c2 7899 *
51219358
MW		 7900 * Return:
7901 * ADV_SUCCESS(1) - SG List successfully created
7902 * ADV_ERROR(-1) - SG List creation failed
27c868c2 7903 */
51219358 7904static int
d2411495 7905adv_get_sglist(struct asc_board *boardp, adv_req_t *reqp, struct scsi_cmnd *scp,
51219358 7906 int use_sg)
27c868c2 7907{
51219358
MW		 7908 adv_sgblk_t *sgblkp;
7909 ADV_SCSI_REQ_Q *scsiqp;
7910 struct scatterlist *slp;
7911 int sg_elem_cnt;
7912 ADV_SG_BLOCK *sg_block, *prev_sg_block;
7913 ADV_PADDR sg_block_paddr;
27c868c2 7914 int i;
27c868c2 7915
51219358 7916 scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
52c334e9 7917 slp = scsi_sglist(scp);
51219358
MW		 7918 sg_elem_cnt = use_sg;
7919 prev_sg_block = NULL;
7920 reqp->sgblkp = NULL;
1da177e4 7921
51219358
MW		 7922 for (;;) {
7923 /*
7924 * Allocate a 'adv_sgblk_t' structure from the board free
7925 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
7926 * (15) scatter-gather elements.
7927 */
7928 if ((sgblkp = boardp->adv_sgblkp) == NULL) {
b352f923 7929 ASC_DBG(1, "no free adv_sgblk_t\n");
51219358 7930 ASC_STATS(scp->device->host, adv_build_nosg);
1da177e4 7931
51219358
MW		 7932 /*
7933 * Allocation failed. Free 'adv_sgblk_t' structures
7934 * already allocated for the request.
7935 */
7936 while ((sgblkp = reqp->sgblkp) != NULL) {
7937 /* Remove 'sgblkp' from the request list. */
7938 reqp->sgblkp = sgblkp->next_sgblkp;
27c868c2 7939
51219358
MW		 7940 /* Add 'sgblkp' to the board free list. */
7941 sgblkp->next_sgblkp = boardp->adv_sgblkp;
7942 boardp->adv_sgblkp = sgblkp;
7943 }
7944 return ASC_BUSY;
7945 }
1da177e4 7946
51219358
MW		 7947 /* Complete 'adv_sgblk_t' board allocation. */
7948 boardp->adv_sgblkp = sgblkp->next_sgblkp;
7949 sgblkp->next_sgblkp = NULL;
1da177e4 7950
51219358
MW		 7951 /*
7952 * Get 8 byte aligned virtual and physical addresses
7953 * for the allocated ADV_SG_BLOCK structure.
7954 */
7955 sg_block = (ADV_SG_BLOCK *)ADV_8BALIGN(&sgblkp->sg_block);
7956 sg_block_paddr = virt_to_bus(sg_block);
27c868c2 7957
51219358
MW		 7958 /*
7959 * Check if this is the first 'adv_sgblk_t' for the
7960 * request.
7961 */
7962 if (reqp->sgblkp == NULL) {
7963 /* Request's first scatter-gather block. */
7964 reqp->sgblkp = sgblkp;
27c868c2 7965
51219358
MW		 7966 /*
7967 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
7968 * address pointers.
7969 */
7970 scsiqp->sg_list_ptr = sg_block;
7971 scsiqp->sg_real_addr = cpu_to_le32(sg_block_paddr);
7972 } else {
7973 /* Request's second or later scatter-gather block. */
7974 sgblkp->next_sgblkp = reqp->sgblkp;
7975 reqp->sgblkp = sgblkp;
7976
7977 /*
7978 * Point the previous ADV_SG_BLOCK structure to
7979 * the newly allocated ADV_SG_BLOCK structure.
7980 */
7981 prev_sg_block->sg_ptr = cpu_to_le32(sg_block_paddr);
27c868c2 7982 }
1da177e4 7983
51219358
MW		 7984 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
7985 sg_block->sg_list[i].sg_addr =
7986 cpu_to_le32(sg_dma_address(slp));
7987 sg_block->sg_list[i].sg_count =
7988 cpu_to_le32(sg_dma_len(slp));
52c334e9
MW		 7989 ASC_STATS_ADD(scp->device->host, xfer_sect,
7990 DIV_ROUND_UP(sg_dma_len(slp), 512));
27c868c2 7991
51219358
MW		 7992 if (--sg_elem_cnt == 0) { /* Last ADV_SG_BLOCK and scatter-gather entry. */
7993 sg_block->sg_cnt = i + 1;
7994 sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */
7995 return ADV_SUCCESS;
7996 }
7997 slp++;
7998 }
7999 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
8000 prev_sg_block = sg_block;
27c868c2 8001 }
51219358 8002}
1da177e4 8003
51219358
MW		 8004/*
8005 * Build a request structure for the Adv Library (Wide Board).
8006 *
8007 * If an adv_req_t can not be allocated to issue the request,
8008 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
8009 *
8010 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the
8011 * microcode for DMA addresses or math operations are byte swapped
8012 * to little-endian order.
8013 */
8014static int
d2411495 8015adv_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
51219358
MW		 8016 ADV_SCSI_REQ_Q **adv_scsiqpp)
8017{
9c17c62a 8018 u32 srb_tag = scp->request->tag;
51219358
MW		 8019 adv_req_t *reqp;
8020 ADV_SCSI_REQ_Q *scsiqp;
8021 int i;
8022 int ret;
52c334e9 8023 int use_sg;
1da177e4 8024
27c868c2 8025 /*
51219358
MW		 8026 * Allocate an adv_req_t structure from the board to execute
8027 * the command.
27c868c2 8028 */
9c17c62a
HR		 8029 reqp = &boardp->adv_reqp[srb_tag];
8030 if (reqp->cmndp && reqp->cmndp != scp ) {
b352f923 8031 ASC_DBG(1, "no free adv_req_t\n");
51219358
MW		 8032 ASC_STATS(scp->device->host, adv_build_noreq);
8033 return ASC_BUSY;
27c868c2 8034 }
1da177e4 8035
27c868c2 8036 /*
51219358 8037 * Get 32-byte aligned ADV_SCSI_REQ_Q and ADV_SG_BLOCK pointers.
27c868c2 8038 */
51219358 8039 scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
27c868c2
MW		 8040
8041 /*
51219358 8042 * Initialize the structure.
27c868c2 8043 */
51219358 8044 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
27c868c2
MW		 8045
8046 /*
9c17c62a 8047 * Set the srb_tag to the command tag.
27c868c2 8048 */
9c17c62a 8049 scsiqp->srb_tag = srb_tag;
27c868c2
MW		 8050
8051 /*
51219358 8052 * Set the adv_req_t 'cmndp' to point to the struct scsi_cmnd structure.
27c868c2 8053 */
51219358 8054 reqp->cmndp = scp;
9c17c62a 8055 scp->host_scribble = (void *)reqp;
27c868c2
MW		 8056
8057 /*
51219358 8058 * Build the ADV_SCSI_REQ_Q request.
27c868c2 8059 */
51219358
MW		 8060
8061 /* Set CDB length and copy it to the request structure. */
8062 scsiqp->cdb_len = scp->cmd_len;
8063 /* Copy first 12 CDB bytes to cdb[]. */
8064 for (i = 0; i < scp->cmd_len && i < 12; i++) {
8065 scsiqp->cdb[i] = scp->cmnd[i];
8066 }
8067 /* Copy last 4 CDB bytes, if present, to cdb16[]. */
8068 for (; i < scp->cmd_len; i++) {
8069 scsiqp->cdb16[i - 12] = scp->cmnd[i];
27c868c2 8070 }
1da177e4 8071
51219358
MW		 8072 scsiqp->target_id = scp->device->id;
8073 scsiqp->target_lun = scp->device->lun;
8074
8075 scsiqp->sense_addr = cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
b80ca4f7 8076 scsiqp->sense_len = SCSI_SENSE_BUFFERSIZE;
27c868c2 8077
52c334e9 8078 /* Build ADV_SCSI_REQ_Q */
51219358 8079
52c334e9
MW		 8080 use_sg = scsi_dma_map(scp);
8081 if (use_sg == 0) {
8082 /* Zero-length transfer */
51219358 8083 reqp->sgblkp = NULL;
52c334e9
MW		 8084 scsiqp->data_cnt = 0;
8085 scsiqp->vdata_addr = NULL;
8086
8087 scsiqp->data_addr = 0;
51219358
MW		 8088 scsiqp->sg_list_ptr = NULL;
8089 scsiqp->sg_real_addr = 0;
51219358 8090 } else {
51219358 8091 if (use_sg > ADV_MAX_SG_LIST) {
9d0e96eb
MW		 8092 scmd_printk(KERN_ERR, scp, "use_sg %d > "
8093 "ADV_MAX_SG_LIST %d\n", use_sg,
51219358 8094 scp->device->host->sg_tablesize);
52c334e9 8095 scsi_dma_unmap(scp);
51219358 8096 scp->result = HOST_BYTE(DID_ERROR);
9c17c62a
HR		 8097 reqp->cmndp = NULL;
8098 scp->host_scribble = NULL;
51219358
MW		 8099
8100 return ASC_ERROR;
8101 }
8102
52c334e9
MW		 8103 scsiqp->data_cnt = cpu_to_le32(scsi_bufflen(scp));
8104
51219358
MW		 8105 ret = adv_get_sglist(boardp, reqp, scp, use_sg);
8106 if (ret != ADV_SUCCESS) {
9c17c62a
HR		 8107 scsi_dma_unmap(scp);
8108 scp->result = HOST_BYTE(DID_ERROR);
8109 reqp->cmndp = NULL;
8110 scp->host_scribble = NULL;
51219358
MW		 8111
8112 return ret;
8113 }
8114
52c334e9 8115 ASC_STATS_ADD(scp->device->host, xfer_elem, use_sg);
27c868c2 8116 }
1da177e4 8117
52c334e9
MW		 8118 ASC_STATS(scp->device->host, xfer_cnt);
8119
51219358
MW		 8120 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
8121 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
27c868c2 8122
51219358 8123 *adv_scsiqpp = scsiqp;
27c868c2 8124
51219358
MW		 8125 return ASC_NOERROR;
8126}
8127
8128static int AscSgListToQueue(int sg_list)
8129{
8130 int n_sg_list_qs;
8131
8132 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
8133 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
8134 n_sg_list_qs++;
8135 return n_sg_list_qs + 1;
8136}
8137
8138static uint
8139AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs)
8140{
8141 uint cur_used_qs;
8142 uint cur_free_qs;
8143 ASC_SCSI_BIT_ID_TYPE target_id;
8144 uchar tid_no;
8145
8146 target_id = ASC_TIX_TO_TARGET_ID(target_ix);
8147 tid_no = ASC_TIX_TO_TID(target_ix);
8148 if ((asc_dvc->unit_not_ready & target_id) ||
8149 (asc_dvc->queue_full_or_busy & target_id)) {
8150 return 0;
8151 }
8152 if (n_qs == 1) {
8153 cur_used_qs = (uint) asc_dvc->cur_total_qng +
8154 (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q;
8155 } else {
8156 cur_used_qs = (uint) asc_dvc->cur_total_qng +
8157 (uint) ASC_MIN_FREE_Q;
8158 }
8159 if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
8160 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
8161 if (asc_dvc->cur_dvc_qng[tid_no] >=
8162 asc_dvc->max_dvc_qng[tid_no]) {
8163 return 0;
8164 }
8165 return cur_free_qs;
8166 }
8167 if (n_qs > 1) {
8168 if ((n_qs > asc_dvc->last_q_shortage)
8169 && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
8170 asc_dvc->last_q_shortage = n_qs;
8171 }
8172 }
8173 return 0;
8174}
8175
8176static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head)
8177{
8178 ushort q_addr;
8179 uchar next_qp;
8180 uchar q_status;
8181
8182 q_addr = ASC_QNO_TO_QADDR(free_q_head);
8183 q_status = (uchar)AscReadLramByte(iop_base,
8184 (ushort)(q_addr +
8185 ASC_SCSIQ_B_STATUS));
8186 next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD));
8187 if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END))
8188 return next_qp;
8189 return ASC_QLINK_END;
8190}
8191
8192static uchar
8193AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q)
8194{
8195 uchar i;
27c868c2 8196
51219358
MW		 8197 for (i = 0; i < n_free_q; i++) {
8198 free_q_head = AscAllocFreeQueue(iop_base, free_q_head);
8199 if (free_q_head == ASC_QLINK_END)
8200 break;
8201 }
8202 return free_q_head;
8203}
27c868c2 8204
51219358
MW		 8205/*
8206 * void
8207 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8208 *
8209 * Calling/Exit State:
8210 * none
8211 *
8212 * Description:
8213 * Output an ASC_SCSI_Q structure to the chip
8214 */
8215static void
8216DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8217{
8218 int i;
8219
8220 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
8221 AscSetChipLramAddr(iop_base, s_addr);
8222 for (i = 0; i < 2 * words; i += 2) {
8223 if (i == 4 || i == 20) {
8224 continue;
8225 }
8226 outpw(iop_base + IOP_RAM_DATA,
8227 ((ushort)outbuf[i + 1] << 8) | outbuf[i]);
27c868c2 8228 }
51219358 8229}
1da177e4 8230
51219358
MW		 8231static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
8232{
8233 ushort q_addr;
8234 uchar tid_no;
8235 uchar sdtr_data;
8236 uchar syn_period_ix;
8237 uchar syn_offset;
8238 PortAddr iop_base;
8239
8240 iop_base = asc_dvc->iop_base;
8241 if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
8242 ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
8243 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
8244 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8245 syn_period_ix =
8246 (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
8247 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
8248 AscMsgOutSDTR(asc_dvc,
8249 asc_dvc->sdtr_period_tbl[syn_period_ix],
8250 syn_offset);
8251 scsiq->q1.cntl |= QC_MSG_OUT;
8252 }
8253 q_addr = ASC_QNO_TO_QADDR(q_no);
8254 if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
68d81f40 8255 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG;
27c868c2 8256 }
51219358
MW		 8257 scsiq->q1.status = QS_FREE;
8258 AscMemWordCopyPtrToLram(iop_base,
8259 q_addr + ASC_SCSIQ_CDB_BEG,
8260 (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1);
8261
8262 DvcPutScsiQ(iop_base,
8263 q_addr + ASC_SCSIQ_CPY_BEG,
8264 (uchar *)&scsiq->q1.cntl,
8265 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
8266 AscWriteLramWord(iop_base,
8267 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS),
8268 (ushort)(((ushort)scsiq->q1.
8269 q_no << 8) | (ushort)QS_READY));
8270 return 1;
8271}
8272
8273static int
8274AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
8275{
8276 int sta;
8277 int i;
8278 ASC_SG_HEAD *sg_head;
8279 ASC_SG_LIST_Q scsi_sg_q;
8280 ASC_DCNT saved_data_addr;
8281 ASC_DCNT saved_data_cnt;
8282 PortAddr iop_base;
8283 ushort sg_list_dwords;
8284 ushort sg_index;
8285 ushort sg_entry_cnt;
8286 ushort q_addr;
8287 uchar next_qp;
1da177e4 8288
51219358
MW		 8289 iop_base = asc_dvc->iop_base;
8290 sg_head = scsiq->sg_head;
8291 saved_data_addr = scsiq->q1.data_addr;
8292 saved_data_cnt = scsiq->q1.data_cnt;
8293 scsiq->q1.data_addr = (ASC_PADDR) sg_head->sg_list[0].addr;
8294 scsiq->q1.data_cnt = (ASC_DCNT) sg_head->sg_list[0].bytes;
8295#if CC_VERY_LONG_SG_LIST
27c868c2 8296 /*
51219358
MW		 8297 * If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST
8298 * then not all SG elements will fit in the allocated queues.
8299 * The rest of the SG elements will be copied when the RISC
8300 * completes the SG elements that fit and halts.
27c868c2 8301 */
51219358
MW		 8302 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
8303 /*
8304 * Set sg_entry_cnt to be the number of SG elements that
8305 * will fit in the allocated SG queues. It is minus 1, because
8306 * the first SG element is handled above. ASC_MAX_SG_LIST is
8307 * already inflated by 1 to account for this. For example it
8308 * may be 50 which is 1 + 7 queues * 7 SG elements.
8309 */
8310 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
27c868c2 8311
51219358
MW		 8312 /*
8313 * Keep track of remaining number of SG elements that will
8314 * need to be handled from a_isr.c.
8315 */
8316 scsiq->remain_sg_entry_cnt =
8317 sg_head->entry_cnt - ASC_MAX_SG_LIST;
8318 } else {
8319#endif /* CC_VERY_LONG_SG_LIST */
8320 /*
8321 * Set sg_entry_cnt to be the number of SG elements that
8322 * will fit in the allocated SG queues. It is minus 1, because
8323 * the first SG element is handled above.
8324 */
8325 sg_entry_cnt = sg_head->entry_cnt - 1;
8326#if CC_VERY_LONG_SG_LIST
8327 }
8328#endif /* CC_VERY_LONG_SG_LIST */
8329 if (sg_entry_cnt != 0) {
8330 scsiq->q1.cntl |= QC_SG_HEAD;
8331 q_addr = ASC_QNO_TO_QADDR(q_no);
8332 sg_index = 1;
8333 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
8334 scsi_sg_q.sg_head_qp = q_no;
8335 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
8336 for (i = 0; i < sg_head->queue_cnt; i++) {
8337 scsi_sg_q.seq_no = i + 1;
8338 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
8339 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
8340 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
8341 if (i == 0) {
8342 scsi_sg_q.sg_list_cnt =
8343 ASC_SG_LIST_PER_Q;
8344 scsi_sg_q.sg_cur_list_cnt =
8345 ASC_SG_LIST_PER_Q;
8346 } else {
8347 scsi_sg_q.sg_list_cnt =
8348 ASC_SG_LIST_PER_Q - 1;
8349 scsi_sg_q.sg_cur_list_cnt =
8350 ASC_SG_LIST_PER_Q - 1;
8351 }
8352 } else {
8353#if CC_VERY_LONG_SG_LIST
8354 /*
8355 * This is the last SG queue in the list of
8356 * allocated SG queues. If there are more
8357 * SG elements than will fit in the allocated
8358 * queues, then set the QCSG_SG_XFER_MORE flag.
8359 */
8360 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
8361 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
8362 } else {
8363#endif /* CC_VERY_LONG_SG_LIST */
8364 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
8365#if CC_VERY_LONG_SG_LIST
8366 }
8367#endif /* CC_VERY_LONG_SG_LIST */
8368 sg_list_dwords = sg_entry_cnt << 1;
8369 if (i == 0) {
8370 scsi_sg_q.sg_list_cnt = sg_entry_cnt;
8371 scsi_sg_q.sg_cur_list_cnt =
8372 sg_entry_cnt;
8373 } else {
8374 scsi_sg_q.sg_list_cnt =
8375 sg_entry_cnt - 1;
8376 scsi_sg_q.sg_cur_list_cnt =
8377 sg_entry_cnt - 1;
8378 }
8379 sg_entry_cnt = 0;
8380 }
8381 next_qp = AscReadLramByte(iop_base,
8382 (ushort)(q_addr +
8383 ASC_SCSIQ_B_FWD));
8384 scsi_sg_q.q_no = next_qp;
8385 q_addr = ASC_QNO_TO_QADDR(next_qp);
8386 AscMemWordCopyPtrToLram(iop_base,
8387 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
8388 (uchar *)&scsi_sg_q,
8389 sizeof(ASC_SG_LIST_Q) >> 1);
8390 AscMemDWordCopyPtrToLram(iop_base,
8391 q_addr + ASC_SGQ_LIST_BEG,
8392 (uchar *)&sg_head->
8393 sg_list[sg_index],
8394 sg_list_dwords);
8395 sg_index += ASC_SG_LIST_PER_Q;
8396 scsiq->next_sg_index = sg_index;
27c868c2 8397 }
51219358
MW		 8398 } else {
8399 scsiq->q1.cntl &= ~QC_SG_HEAD;
27c868c2 8400 }
51219358
MW		 8401 sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
8402 scsiq->q1.data_addr = saved_data_addr;
8403 scsiq->q1.data_cnt = saved_data_cnt;
8404 return (sta);
8405}
27c868c2 8406
51219358
MW		 8407static int
8408AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required)
8409{
8410 PortAddr iop_base;
8411 uchar free_q_head;
8412 uchar next_qp;
8413 uchar tid_no;
8414 uchar target_ix;
8415 int sta;
27c868c2 8416
51219358
MW		 8417 iop_base = asc_dvc->iop_base;
8418 target_ix = scsiq->q2.target_ix;
8419 tid_no = ASC_TIX_TO_TID(target_ix);
8420 sta = 0;
8421 free_q_head = (uchar)AscGetVarFreeQHead(iop_base);
8422 if (n_q_required > 1) {
8423 next_qp = AscAllocMultipleFreeQueue(iop_base, free_q_head,
8424 (uchar)n_q_required);
8425 if (next_qp != ASC_QLINK_END) {
8426 asc_dvc->last_q_shortage = 0;
8427 scsiq->sg_head->queue_cnt = n_q_required - 1;
8428 scsiq->q1.q_no = free_q_head;
8429 sta = AscPutReadySgListQueue(asc_dvc, scsiq,
8430 free_q_head);
8431 }
8432 } else if (n_q_required == 1) {
8433 next_qp = AscAllocFreeQueue(iop_base, free_q_head);
8434 if (next_qp != ASC_QLINK_END) {
8435 scsiq->q1.q_no = free_q_head;
8436 sta = AscPutReadyQueue(asc_dvc, scsiq, free_q_head);
27c868c2
MW		 8437 }
8438 }
51219358
MW		 8439 if (sta == 1) {
8440 AscPutVarFreeQHead(iop_base, next_qp);
8441 asc_dvc->cur_total_qng += n_q_required;
8442 asc_dvc->cur_dvc_qng[tid_no]++;
27c868c2 8443 }
51219358
MW		 8444 return sta;
8445}
27c868c2 8446
51219358
MW		 8447#define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16
8448static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = {
8449 INQUIRY,
8450 REQUEST_SENSE,
8451 READ_CAPACITY,
8452 READ_TOC,
8453 MODE_SELECT,
8454 MODE_SENSE,
8455 MODE_SELECT_10,
8456 MODE_SENSE_10,
8457 0xFF,
8458 0xFF,
8459 0xFF,
8460 0xFF,
8461 0xFF,
8462 0xFF,
8463 0xFF,
8464 0xFF
8465};
27c868c2 8466
51219358
MW		 8467static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
8468{
8469 PortAddr iop_base;
8470 int sta;
8471 int n_q_required;
8472 int disable_syn_offset_one_fix;
8473 int i;
8474 ASC_PADDR addr;
8475 ushort sg_entry_cnt = 0;
8476 ushort sg_entry_cnt_minus_one = 0;
8477 uchar target_ix;
8478 uchar tid_no;
8479 uchar sdtr_data;
8480 uchar extra_bytes;
8481 uchar scsi_cmd;
8482 uchar disable_cmd;
8483 ASC_SG_HEAD *sg_head;
8484 ASC_DCNT data_cnt;
27c868c2 8485
51219358
MW		 8486 iop_base = asc_dvc->iop_base;
8487 sg_head = scsiq->sg_head;
8488 if (asc_dvc->err_code != 0)
8489 return (ERR);
8490 scsiq->q1.q_no = 0;
8491 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
8492 scsiq->q1.extra_bytes = 0;
27c868c2 8493 }
51219358
MW		 8494 sta = 0;
8495 target_ix = scsiq->q2.target_ix;
8496 tid_no = ASC_TIX_TO_TID(target_ix);
8497 n_q_required = 1;
8498 if (scsiq->cdbptr[0] == REQUEST_SENSE) {
8499 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
8500 asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
8501 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8502 AscMsgOutSDTR(asc_dvc,
8503 asc_dvc->
8504 sdtr_period_tbl[(sdtr_data >> 4) &
8505 (uchar)(asc_dvc->
8506 max_sdtr_index -
8507 1)],
8508 (uchar)(sdtr_data & (uchar)
8509 ASC_SYN_MAX_OFFSET));
8510 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
8511 }
8512 }
8513 if (asc_dvc->in_critical_cnt != 0) {
8514 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
8515 return (ERR);
8516 }
8517 asc_dvc->in_critical_cnt++;
8518 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
8519 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
8520 asc_dvc->in_critical_cnt--;
8521 return (ERR);
8522 }
8523#if !CC_VERY_LONG_SG_LIST
8524 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
8525 asc_dvc->in_critical_cnt--;
8526 return (ERR);
8527 }
8528#endif /* !CC_VERY_LONG_SG_LIST */
8529 if (sg_entry_cnt == 1) {
8530 scsiq->q1.data_addr =
8531 (ADV_PADDR)sg_head->sg_list[0].addr;
8532 scsiq->q1.data_cnt =
8533 (ADV_DCNT)sg_head->sg_list[0].bytes;
8534 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
8535 }
8536 sg_entry_cnt_minus_one = sg_entry_cnt - 1;
8537 }
8538 scsi_cmd = scsiq->cdbptr[0];
8539 disable_syn_offset_one_fix = FALSE;
8540 if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
8541 !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
8542 if (scsiq->q1.cntl & QC_SG_HEAD) {
8543 data_cnt = 0;
8544 for (i = 0; i < sg_entry_cnt; i++) {
8545 data_cnt +=
8546 (ADV_DCNT)le32_to_cpu(sg_head->sg_list[i].
8547 bytes);
8548 }
8549 } else {
8550 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
8551 }
8552 if (data_cnt != 0UL) {
8553 if (data_cnt < 512UL) {
8554 disable_syn_offset_one_fix = TRUE;
8555 } else {
8556 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST;
8557 i++) {
8558 disable_cmd =
8559 _syn_offset_one_disable_cmd[i];
8560 if (disable_cmd == 0xFF) {
8561 break;
8562 }
8563 if (scsi_cmd == disable_cmd) {
8564 disable_syn_offset_one_fix =
8565 TRUE;
8566 break;
8567 }
8568 }
8569 }
8570 }
8571 }
8572 if (disable_syn_offset_one_fix) {
68d81f40 8573 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG;
51219358
MW		 8574 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
8575 ASC_TAG_FLAG_DISABLE_DISCONNECT);
8576 } else {
8577 scsiq->q2.tag_code &= 0x27;
8578 }
8579 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
8580 if (asc_dvc->bug_fix_cntl) {
8581 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
8582 if ((scsi_cmd == READ_6) ||
8583 (scsi_cmd == READ_10)) {
8584 addr =
8585 (ADV_PADDR)le32_to_cpu(sg_head->
8586 sg_list
8587 [sg_entry_cnt_minus_one].
8588 addr) +
8589 (ADV_DCNT)le32_to_cpu(sg_head->
8590 sg_list
8591 [sg_entry_cnt_minus_one].
8592 bytes);
8593 extra_bytes =
8594 (uchar)((ushort)addr & 0x0003);
8595 if ((extra_bytes != 0)
8596 &&
8597 ((scsiq->q2.
8598 tag_code &
8599 ASC_TAG_FLAG_EXTRA_BYTES)
8600 == 0)) {
8601 scsiq->q2.tag_code |=
8602 ASC_TAG_FLAG_EXTRA_BYTES;
8603 scsiq->q1.extra_bytes =
8604 extra_bytes;
8605 data_cnt =
8606 le32_to_cpu(sg_head->
8607 sg_list
8608 [sg_entry_cnt_minus_one].
8609 bytes);
8610 data_cnt -=
8611 (ASC_DCNT) extra_bytes;
8612 sg_head->
8613 sg_list
8614 [sg_entry_cnt_minus_one].
8615 bytes =
8616 cpu_to_le32(data_cnt);
8617 }
8618 }
8619 }
8620 }
8621 sg_head->entry_to_copy = sg_head->entry_cnt;
8622#if CC_VERY_LONG_SG_LIST
27c868c2 8623 /*
51219358
MW		 8624 * Set the sg_entry_cnt to the maximum possible. The rest of
8625 * the SG elements will be copied when the RISC completes the
8626 * SG elements that fit and halts.
27c868c2 8627 */
51219358
MW		 8628 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
8629 sg_entry_cnt = ASC_MAX_SG_LIST;
8630 }
8631#endif /* CC_VERY_LONG_SG_LIST */
8632 n_q_required = AscSgListToQueue(sg_entry_cnt);
8633 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
8634 (uint) n_q_required)
8635 || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
8636 if ((sta =
8637 AscSendScsiQueue(asc_dvc, scsiq,
8638 n_q_required)) == 1) {
8639 asc_dvc->in_critical_cnt--;
8640 return (sta);
27c868c2 8641 }
51219358
MW		 8642 }
8643 } else {
8644 if (asc_dvc->bug_fix_cntl) {
8645 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
8646 if ((scsi_cmd == READ_6) ||
8647 (scsi_cmd == READ_10)) {
8648 addr =
8649 le32_to_cpu(scsiq->q1.data_addr) +
8650 le32_to_cpu(scsiq->q1.data_cnt);
8651 extra_bytes =
8652 (uchar)((ushort)addr & 0x0003);
8653 if ((extra_bytes != 0)
8654 &&
8655 ((scsiq->q2.
8656 tag_code &
8657 ASC_TAG_FLAG_EXTRA_BYTES)
8658 == 0)) {
8659 data_cnt =
8660 le32_to_cpu(scsiq->q1.
8661 data_cnt);
8662 if (((ushort)data_cnt & 0x01FF)
8663 == 0) {
8664 scsiq->q2.tag_code |=
8665 ASC_TAG_FLAG_EXTRA_BYTES;
8666 data_cnt -= (ASC_DCNT)
8667 extra_bytes;
8668 scsiq->q1.data_cnt =
8669 cpu_to_le32
8670 (data_cnt);
8671 scsiq->q1.extra_bytes =
8672 extra_bytes;
8673 }
8674 }
8675 }
8676 }
8677 }
8678 n_q_required = 1;
8679 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
8680 ((scsiq->q1.cntl & QC_URGENT) != 0)) {
8681 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
8682 n_q_required)) == 1) {
8683 asc_dvc->in_critical_cnt--;
8684 return (sta);
27c868c2
MW		 8685 }
8686 }
8687 }
51219358
MW		 8688 asc_dvc->in_critical_cnt--;
8689 return (sta);
1da177e4
LT		 8690}
8691
8692/*
51219358 8693 * AdvExeScsiQueue() - Send a request to the RISC microcode program.
1da177e4 8694 *
51219358
MW		 8695 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
8696 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
8697 * RISC to notify it a new command is ready to be executed.
8698 *
8699 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
8700 * set to SCSI_MAX_RETRY.
8701 *
8702 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode
8703 * for DMA addresses or math operations are byte swapped to little-endian
8704 * order.
8705 *
8706 * Return:
8707 * ADV_SUCCESS(1) - The request was successfully queued.
8708 * ADV_BUSY(0) - Resource unavailable; Retry again after pending
8709 * request completes.
8710 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure
8711 * host IC error.
8712 */
8713static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq)
8714{
8715 AdvPortAddr iop_base;
51219358
MW		 8716 ADV_PADDR req_paddr;
8717 ADV_CARR_T *new_carrp;
1da177e4 8718
27c868c2 8719 /*
51219358 8720 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
27c868c2 8721 */
51219358
MW		 8722 if (scsiq->target_id > ADV_MAX_TID) {
8723 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
8724 scsiq->done_status = QD_WITH_ERROR;
27c868c2
MW		 8725 return ADV_ERROR;
8726 }
1da177e4 8727
51219358 8728 iop_base = asc_dvc->iop_base;
1da177e4 8729
27c868c2 8730 /*
51219358
MW		 8731 * Allocate a carrier ensuring at least one carrier always
8732 * remains on the freelist and initialize fields.
27c868c2 8733 */
51219358
MW		 8734 if ((new_carrp = asc_dvc->carr_freelist) == NULL) {
8735 return ADV_BUSY;
27c868c2 8736 }
51219358
MW		 8737 asc_dvc->carr_freelist = (ADV_CARR_T *)
8738 ADV_U32_TO_VADDR(le32_to_cpu(new_carrp->next_vpa));
8739 asc_dvc->carr_pending_cnt++;
1da177e4 8740
27c868c2 8741 /*
51219358
MW		 8742 * Set the carrier to be a stopper by setting 'next_vpa'
8743 * to the stopper value. The current stopper will be changed
8744 * below to point to the new stopper.
27c868c2 8745 */
51219358 8746 new_carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
27c868c2
MW		 8747
8748 /*
51219358 8749 * Clear the ADV_SCSI_REQ_Q done flag.
27c868c2 8750 */
51219358 8751 scsiq->a_flag &= ~ADV_SCSIQ_DONE;
27c868c2 8752
fd625f47 8753 req_paddr = virt_to_bus(scsiq);
51219358 8754 BUG_ON(req_paddr & 31);
51219358
MW		 8755 /* Wait for assertion before making little-endian */
8756 req_paddr = cpu_to_le32(req_paddr);
27c868c2 8757
51219358
MW		 8758 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
8759 scsiq->scsiq_ptr = cpu_to_le32(ADV_VADDR_TO_U32(scsiq));
8760 scsiq->scsiq_rptr = req_paddr;
8761
8762 scsiq->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->icq_sp));
27c868c2 8763 /*
51219358
MW		 8764 * Every ADV_CARR_T.carr_pa is byte swapped to little-endian
8765 * order during initialization.
27c868c2 8766 */
51219358 8767 scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
1da177e4 8768
27c868c2 8769 /*
51219358
MW		 8770 * Use the current stopper to send the ADV_SCSI_REQ_Q command to
8771 * the microcode. The newly allocated stopper will become the new
8772 * stopper.
27c868c2 8773 */
51219358 8774 asc_dvc->icq_sp->areq_vpa = req_paddr;
1da177e4 8775
27c868c2 8776 /*
51219358
MW		 8777 * Set the 'next_vpa' pointer for the old stopper to be the
8778 * physical address of the new stopper. The RISC can only
8779 * follow physical addresses.
27c868c2 8780 */
51219358 8781 asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
27c868c2
MW		 8782
8783 /*
51219358 8784 * Set the host adapter stopper pointer to point to the new carrier.
27c868c2 8785 */
51219358
MW		 8786 asc_dvc->icq_sp = new_carrp;
8787
8788 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
8789 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
8790 /*
8791 * Tickle the RISC to tell it to read its Command Queue Head pointer.
8792 */
8793 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
8794 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
8795 /*
8796 * Clear the tickle value. In the ASC-3550 the RISC flag
8797 * command 'clr_tickle_a' does not work unless the host
8798 * value is cleared.
8799 */
8800 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
8801 ADV_TICKLE_NOP);
8802 }
8803 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8804 /*
8805 * Notify the RISC a carrier is ready by writing the physical
8806 * address of the new carrier stopper to the COMMA register.
8807 */
8808 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
8809 le32_to_cpu(new_carrp->carr_pa));
27c868c2 8810 }
1da177e4 8811
51219358
MW		 8812 return ADV_SUCCESS;
8813}
8814
8815/*
8816 * Execute a single 'Scsi_Cmnd'.
51219358
MW		 8817 */
8818static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
8819{
41d2493d 8820 int ret, err_code;
d2411495 8821 struct asc_board *boardp = shost_priv(scp->device->host);
51219358 8822
b352f923 8823 ASC_DBG(1, "scp 0x%p\n", scp);
27c868c2 8824
51219358 8825 if (ASC_NARROW_BOARD(boardp)) {
41d2493d 8826 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
05848b6e 8827 struct asc_scsi_q asc_scsi_q;
27c868c2 8828
41d2493d 8829 /* asc_build_req() can not return ASC_BUSY. */
05848b6e
MW		 8830 ret = asc_build_req(boardp, scp, &asc_scsi_q);
8831 if (ret == ASC_ERROR) {
51219358
MW		 8832 ASC_STATS(scp->device->host, build_error);
8833 return ASC_ERROR;
8834 }
1da177e4 8835
41d2493d 8836 ret = AscExeScsiQueue(asc_dvc, &asc_scsi_q);
05848b6e 8837 kfree(asc_scsi_q.sg_head);
41d2493d 8838 err_code = asc_dvc->err_code;
51219358 8839 } else {
41d2493d
MW		 8840 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
8841 ADV_SCSI_REQ_Q *adv_scsiqp;
27c868c2 8842
51219358
MW		 8843 switch (adv_build_req(boardp, scp, &adv_scsiqp)) {
8844 case ASC_NOERROR:
b352f923 8845 ASC_DBG(3, "adv_build_req ASC_NOERROR\n");
51219358
MW		 8846 break;
8847 case ASC_BUSY:
b352f923 8848 ASC_DBG(1, "adv_build_req ASC_BUSY\n");
51219358
MW		 8849 /*
8850 * The asc_stats fields 'adv_build_noreq' and
8851 * 'adv_build_nosg' count wide board busy conditions.
8852 * They are updated in adv_build_req and
8853 * adv_get_sglist, respectively.
8854 */
8855 return ASC_BUSY;
8856 case ASC_ERROR:
8857 default:
b352f923 8858 ASC_DBG(1, "adv_build_req ASC_ERROR\n");
51219358
MW		 8859 ASC_STATS(scp->device->host, build_error);
8860 return ASC_ERROR;
8861 }
8862
41d2493d
MW		 8863 ret = AdvExeScsiQueue(adv_dvc, adv_scsiqp);
8864 err_code = adv_dvc->err_code;
8865 }
8866
8867 switch (ret) {
8868 case ASC_NOERROR:
8869 ASC_STATS(scp->device->host, exe_noerror);
8870 /*
8871 * Increment monotonically increasing per device
8872 * successful request counter. Wrapping doesn't matter.
8873 */
8874 boardp->reqcnt[scp->device->id]++;
b352f923 8875 ASC_DBG(1, "ExeScsiQueue() ASC_NOERROR\n");
41d2493d
MW		 8876 break;
8877 case ASC_BUSY:
8878 ASC_STATS(scp->device->host, exe_busy);
8879 break;
8880 case ASC_ERROR:
9d0e96eb
MW		 8881 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() ASC_ERROR, "
8882 "err_code 0x%x\n", err_code);
41d2493d
MW		 8883 ASC_STATS(scp->device->host, exe_error);
8884 scp->result = HOST_BYTE(DID_ERROR);
8885 break;
8886 default:
9d0e96eb
MW		 8887 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() unknown, "
8888 "err_code 0x%x\n", err_code);
41d2493d
MW		 8889 ASC_STATS(scp->device->host, exe_unknown);
8890 scp->result = HOST_BYTE(DID_ERROR);
8891 break;
27c868c2 8892 }
1da177e4 8893
b352f923 8894 ASC_DBG(1, "end\n");
51219358
MW		 8895 return ret;
8896}
27c868c2 8897
51219358
MW		 8898/*
8899 * advansys_queuecommand() - interrupt-driven I/O entrypoint.
8900 *
8901 * This function always returns 0. Command return status is saved
8902 * in the 'scp' result field.
8903 */
8904static int
f281233d 8905advansys_queuecommand_lck(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *))
51219358
MW		 8906{
8907 struct Scsi_Host *shost = scp->device->host;
51219358 8908 int asc_res, result = 0;
27c868c2 8909
51219358
MW		 8910 ASC_STATS(shost, queuecommand);
8911 scp->scsi_done = done;
27c868c2 8912
51219358 8913 asc_res = asc_execute_scsi_cmnd(scp);
51219358
MW		 8914
8915 switch (asc_res) {
8916 case ASC_NOERROR:
8917 break;
8918 case ASC_BUSY:
8919 result = SCSI_MLQUEUE_HOST_BUSY;
8920 break;
8921 case ASC_ERROR:
8922 default:
8923 asc_scsi_done(scp);
8924 break;
8925 }
8926
8927 return result;
8928}
8929
f281233d
JG		 8930static DEF_SCSI_QCMD(advansys_queuecommand)
8931
6f039790 8932static ushort AscGetEisaChipCfg(PortAddr iop_base)
51219358
MW		 8933{
8934 PortAddr eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
8935 (PortAddr) (ASC_EISA_CFG_IOP_MASK);
8936 return inpw(eisa_cfg_iop);
8937}
8938
8939/*
8940 * Return the BIOS address of the adapter at the specified
8941 * I/O port and with the specified bus type.
8942 */
6f039790
GKH		 8943static unsigned short AscGetChipBiosAddress(PortAddr iop_base,
8944 unsigned short bus_type)
51219358
MW		 8945{
8946 unsigned short cfg_lsw;
8947 unsigned short bios_addr;
27c868c2
MW		 8948
8949 /*
51219358
MW		 8950 * The PCI BIOS is re-located by the motherboard BIOS. Because
8951 * of this the driver can not determine where a PCI BIOS is
8952 * loaded and executes.
27c868c2 8953 */
51219358
MW		 8954 if (bus_type & ASC_IS_PCI)
8955 return 0;
27c868c2 8956
51219358
MW		 8957 if ((bus_type & ASC_IS_EISA) != 0) {
8958 cfg_lsw = AscGetEisaChipCfg(iop_base);
8959 cfg_lsw &= 0x000F;
8960 bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE;
8961 return bios_addr;
8962 }
27c868c2 8963
51219358 8964 cfg_lsw = AscGetChipCfgLsw(iop_base);
27c868c2
MW		 8965
8966 /*
51219358 8967 * ISA PnP uses the top bit as the 32K BIOS flag
27c868c2 8968 */
51219358
MW		 8969 if (bus_type == ASC_IS_ISAPNP)
8970 cfg_lsw &= 0x7FFF;
8971 bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE;
8972 return bios_addr;
8973}
8974
6f039790 8975static uchar AscSetChipScsiID(PortAddr iop_base, uchar new_host_id)
51219358
MW		 8976{
8977 ushort cfg_lsw;
8978
8979 if (AscGetChipScsiID(iop_base) == new_host_id) {
8980 return (new_host_id);
27c868c2 8981 }
51219358
MW		 8982 cfg_lsw = AscGetChipCfgLsw(iop_base);
8983 cfg_lsw &= 0xF8FF;
8984 cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8);
8985 AscSetChipCfgLsw(iop_base, cfg_lsw);
8986 return (AscGetChipScsiID(iop_base));
8987}
27c868c2 8988
6f039790 8989static unsigned char AscGetChipScsiCtrl(PortAddr iop_base)
51219358
MW		 8990{
8991 unsigned char sc;
27c868c2 8992
51219358
MW		 8993 AscSetBank(iop_base, 1);
8994 sc = inp(iop_base + IOP_REG_SC);
8995 AscSetBank(iop_base, 0);
8996 return sc;
8997}
27c868c2 8998
6f039790
GKH		 8999static unsigned char AscGetChipVersion(PortAddr iop_base,
9000 unsigned short bus_type)
51219358
MW		 9001{
9002 if (bus_type & ASC_IS_EISA) {
9003 PortAddr eisa_iop;
9004 unsigned char revision;
9005 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
9006 (PortAddr) ASC_EISA_REV_IOP_MASK;
9007 revision = inp(eisa_iop);
9008 return ASC_CHIP_MIN_VER_EISA - 1 + revision;
27c868c2 9009 }
51219358
MW		 9010 return AscGetChipVerNo(iop_base);
9011}
27c868c2 9012
51219358 9013#ifdef CONFIG_ISA
6f039790 9014static void AscEnableIsaDma(uchar dma_channel)
51219358
MW		 9015{
9016 if (dma_channel < 4) {
9017 outp(0x000B, (ushort)(0xC0 | dma_channel));
9018 outp(0x000A, dma_channel);
9019 } else if (dma_channel < 8) {
9020 outp(0x00D6, (ushort)(0xC0 | (dma_channel - 4)));
9021 outp(0x00D4, (ushort)(dma_channel - 4));
9022 }
51219358
MW		 9023}
9024#endif /* CONFIG_ISA */
9025
9026static int AscStopQueueExe(PortAddr iop_base)
9027{
9028 int count = 0;
9029
9030 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
9031 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
9032 ASC_STOP_REQ_RISC_STOP);
9033 do {
9034 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
9035 ASC_STOP_ACK_RISC_STOP) {
9036 return (1);
9037 }
9038 mdelay(100);
9039 } while (count++ < 20);
9040 }
9041 return (0);
9042}
9043
6f039790 9044static ASC_DCNT AscGetMaxDmaCount(ushort bus_type)
51219358
MW		 9045{
9046 if (bus_type & ASC_IS_ISA)
9047 return ASC_MAX_ISA_DMA_COUNT;
9048 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
9049 return ASC_MAX_VL_DMA_COUNT;
9050 return ASC_MAX_PCI_DMA_COUNT;
27c868c2 9051}
1da177e4 9052
51219358 9053#ifdef CONFIG_ISA
6f039790 9054static ushort AscGetIsaDmaChannel(PortAddr iop_base)
27c868c2 9055{
51219358 9056 ushort channel;
1da177e4 9057
51219358
MW		 9058 channel = AscGetChipCfgLsw(iop_base) & 0x0003;
9059 if (channel == 0x03)
9060 return (0);
9061 else if (channel == 0x00)
9062 return (7);
9063 return (channel + 4);
9064}
1da177e4 9065
6f039790 9066static ushort AscSetIsaDmaChannel(PortAddr iop_base, ushort dma_channel)
51219358
MW		 9067{
9068 ushort cfg_lsw;
9069 uchar value;
1da177e4 9070
51219358
MW		 9071 if ((dma_channel >= 5) && (dma_channel <= 7)) {
9072 if (dma_channel == 7)
9073 value = 0x00;
9074 else
9075 value = dma_channel - 4;
9076 cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
9077 cfg_lsw |= value;
9078 AscSetChipCfgLsw(iop_base, cfg_lsw);
9079 return (AscGetIsaDmaChannel(iop_base));
9080 }
9081 return 0;
9082}
1da177e4 9083
6f039790 9084static uchar AscGetIsaDmaSpeed(PortAddr iop_base)
51219358
MW		 9085{
9086 uchar speed_value;
1da177e4 9087
51219358
MW		 9088 AscSetBank(iop_base, 1);
9089 speed_value = AscReadChipDmaSpeed(iop_base);
9090 speed_value &= 0x07;
9091 AscSetBank(iop_base, 0);
9092 return speed_value;
9093}
1da177e4 9094
6f039790 9095static uchar AscSetIsaDmaSpeed(PortAddr iop_base, uchar speed_value)
51219358
MW		 9096{
9097 speed_value &= 0x07;
9098 AscSetBank(iop_base, 1);
9099 AscWriteChipDmaSpeed(iop_base, speed_value);
9100 AscSetBank(iop_base, 0);
9101 return AscGetIsaDmaSpeed(iop_base);
9102}
9103#endif /* CONFIG_ISA */
1da177e4 9104
6f039790 9105static ushort AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
51219358
MW		 9106{
9107 int i;
9108 PortAddr iop_base;
9109 ushort warn_code;
9110 uchar chip_version;
1da177e4 9111
51219358
MW		 9112 iop_base = asc_dvc->iop_base;
9113 warn_code = 0;
9114 asc_dvc->err_code = 0;
9115 if ((asc_dvc->bus_type &
9116 (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
9117 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
27c868c2 9118 }
51219358
MW		 9119 AscSetChipControl(iop_base, CC_HALT);
9120 AscSetChipStatus(iop_base, 0);
9121 asc_dvc->bug_fix_cntl = 0;
9122 asc_dvc->pci_fix_asyn_xfer = 0;
9123 asc_dvc->pci_fix_asyn_xfer_always = 0;
421f91d2 9124 /* asc_dvc->init_state initialized in AscInitGetConfig(). */
51219358
MW		 9125 asc_dvc->sdtr_done = 0;
9126 asc_dvc->cur_total_qng = 0;
9127 asc_dvc->is_in_int = 0;
9128 asc_dvc->in_critical_cnt = 0;
9129 asc_dvc->last_q_shortage = 0;
9130 asc_dvc->use_tagged_qng = 0;
9131 asc_dvc->no_scam = 0;
9132 asc_dvc->unit_not_ready = 0;
9133 asc_dvc->queue_full_or_busy = 0;
9134 asc_dvc->redo_scam = 0;
9135 asc_dvc->res2 = 0;
afbb68c3 9136 asc_dvc->min_sdtr_index = 0;
51219358
MW		 9137 asc_dvc->cfg->can_tagged_qng = 0;
9138 asc_dvc->cfg->cmd_qng_enabled = 0;
9139 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
9140 asc_dvc->init_sdtr = 0;
9141 asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
9142 asc_dvc->scsi_reset_wait = 3;
9143 asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
9144 asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
9145 asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
9146 asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
9147 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
51219358
MW		 9148 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
9149 asc_dvc->cfg->chip_version = chip_version;
afbb68c3 9150 asc_dvc->sdtr_period_tbl = asc_syn_xfer_period;
51219358
MW		 9151 asc_dvc->max_sdtr_index = 7;
9152 if ((asc_dvc->bus_type & ASC_IS_PCI) &&
9153 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
9154 asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
afbb68c3 9155 asc_dvc->sdtr_period_tbl = asc_syn_ultra_xfer_period;
51219358
MW		 9156 asc_dvc->max_sdtr_index = 15;
9157 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) {
9158 AscSetExtraControl(iop_base,
9159 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
9160 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
9161 AscSetExtraControl(iop_base,
9162 (SEC_ACTIVE_NEGATE |
9163 SEC_ENABLE_FILTER));
27c868c2
MW		 9164 }
9165 }
51219358
MW		 9166 if (asc_dvc->bus_type == ASC_IS_PCI) {
9167 AscSetExtraControl(iop_base,
9168 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
9169 }
1da177e4 9170
51219358
MW		 9171 asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
9172#ifdef CONFIG_ISA
9173 if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
9174 if (chip_version >= ASC_CHIP_MIN_VER_ISA_PNP) {
9175 AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
9176 asc_dvc->bus_type = ASC_IS_ISAPNP;
27c868c2 9177 }
51219358
MW		 9178 asc_dvc->cfg->isa_dma_channel =
9179 (uchar)AscGetIsaDmaChannel(iop_base);
27c868c2 9180 }
51219358
MW		 9181#endif /* CONFIG_ISA */
9182 for (i = 0; i <= ASC_MAX_TID; i++) {
9183 asc_dvc->cur_dvc_qng[i] = 0;
9184 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
9185 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L;
9186 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L;
9187 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
27c868c2 9188 }
51219358
MW		 9189 return warn_code;
9190}
1da177e4 9191
6f039790 9192static int AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg)
51219358
MW		 9193{
9194 int retry;
27c868c2 9195
51219358
MW		 9196 for (retry = 0; retry < ASC_EEP_MAX_RETRY; retry++) {
9197 unsigned char read_back;
9198 AscSetChipEEPCmd(iop_base, cmd_reg);
9199 mdelay(1);
9200 read_back = AscGetChipEEPCmd(iop_base);
9201 if (read_back == cmd_reg)
9202 return 1;
27c868c2 9203 }
51219358
MW		 9204 return 0;
9205}
1da177e4 9206
6f039790 9207static void AscWaitEEPRead(void)
51219358
MW		 9208{
9209 mdelay(1);
27c868c2 9210}
1da177e4 9211
6f039790 9212static ushort AscReadEEPWord(PortAddr iop_base, uchar addr)
27c868c2 9213{
51219358
MW		 9214 ushort read_wval;
9215 uchar cmd_reg;
27c868c2 9216
51219358
MW		 9217 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
9218 AscWaitEEPRead();
9219 cmd_reg = addr | ASC_EEP_CMD_READ;
9220 AscWriteEEPCmdReg(iop_base, cmd_reg);
9221 AscWaitEEPRead();
9222 read_wval = AscGetChipEEPData(iop_base);
9223 AscWaitEEPRead();
9224 return read_wval;
9225}
27c868c2 9226
6f039790
GKH		 9227static ushort AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9228 ushort bus_type)
51219358
MW		 9229{
9230 ushort wval;
9231 ushort sum;
9232 ushort *wbuf;
9233 int cfg_beg;
9234 int cfg_end;
9235 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
9236 int s_addr;
27c868c2 9237
51219358
MW		 9238 wbuf = (ushort *)cfg_buf;
9239 sum = 0;
9240 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
9241 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9242 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
9243 sum += *wbuf;
9244 }
9245 if (bus_type & ASC_IS_VL) {
9246 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9247 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9248 } else {
9249 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9250 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9251 }
9252 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9253 wval = AscReadEEPWord(iop_base, (uchar)s_addr);
9254 if (s_addr <= uchar_end_in_config) {
9255 /*
9256 * Swap all char fields - must unswap bytes already swapped
9257 * by AscReadEEPWord().
9258 */
9259 *wbuf = le16_to_cpu(wval);
9260 } else {
9261 /* Don't swap word field at the end - cntl field. */
9262 *wbuf = wval;
9263 }
9264 sum += wval; /* Checksum treats all EEPROM data as words. */
9265 }
27c868c2 9266 /*
51219358
MW		 9267 * Read the checksum word which will be compared against 'sum'
9268 * by the caller. Word field already swapped.
27c868c2 9269 */
51219358
MW		 9270 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
9271 return sum;
9272}
1da177e4 9273
6f039790 9274static int AscTestExternalLram(ASC_DVC_VAR *asc_dvc)
51219358
MW		 9275{
9276 PortAddr iop_base;
9277 ushort q_addr;
9278 ushort saved_word;
9279 int sta;
1da177e4 9280
51219358
MW		 9281 iop_base = asc_dvc->iop_base;
9282 sta = 0;
9283 q_addr = ASC_QNO_TO_QADDR(241);
9284 saved_word = AscReadLramWord(iop_base, q_addr);
9285 AscSetChipLramAddr(iop_base, q_addr);
9286 AscSetChipLramData(iop_base, 0x55AA);
9287 mdelay(10);
9288 AscSetChipLramAddr(iop_base, q_addr);
9289 if (AscGetChipLramData(iop_base) == 0x55AA) {
9290 sta = 1;
9291 AscWriteLramWord(iop_base, q_addr, saved_word);
9292 }
9293 return (sta);
9294}
1da177e4 9295
6f039790 9296static void AscWaitEEPWrite(void)
51219358
MW		 9297{
9298 mdelay(20);
51219358 9299}
1da177e4 9300
6f039790 9301static int AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg)
51219358
MW		 9302{
9303 ushort read_back;
9304 int retry;
1da177e4 9305
51219358
MW		 9306 retry = 0;
9307 while (TRUE) {
9308 AscSetChipEEPData(iop_base, data_reg);
9309 mdelay(1);
9310 read_back = AscGetChipEEPData(iop_base);
9311 if (read_back == data_reg) {
9312 return (1);
9313 }
9314 if (retry++ > ASC_EEP_MAX_RETRY) {
9315 return (0);
9316 }
27c868c2 9317 }
51219358 9318}
27c868c2 9319
6f039790 9320static ushort AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val)
51219358
MW		 9321{
9322 ushort read_wval;
9323
9324 read_wval = AscReadEEPWord(iop_base, addr);
9325 if (read_wval != word_val) {
9326 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
9327 AscWaitEEPRead();
9328 AscWriteEEPDataReg(iop_base, word_val);
9329 AscWaitEEPRead();
9330 AscWriteEEPCmdReg(iop_base,
9331 (uchar)((uchar)ASC_EEP_CMD_WRITE | addr));
9332 AscWaitEEPWrite();
9333 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
9334 AscWaitEEPRead();
9335 return (AscReadEEPWord(iop_base, addr));
9336 }
9337 return (read_wval);
9338}
9339
6f039790
GKH		 9340static int AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9341 ushort bus_type)
51219358
MW		 9342{
9343 int n_error;
9344 ushort *wbuf;
9345 ushort word;
9346 ushort sum;
9347 int s_addr;
9348 int cfg_beg;
9349 int cfg_end;
9350 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
9351
9352 wbuf = (ushort *)cfg_buf;
9353 n_error = 0;
9354 sum = 0;
9355 /* Write two config words; AscWriteEEPWord() will swap bytes. */
9356 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9357 sum += *wbuf;
9358 if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9359 n_error++;
27c868c2 9360 }
51219358
MW		 9361 }
9362 if (bus_type & ASC_IS_VL) {
9363 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9364 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9365 } else {
9366 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9367 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9368 }
9369 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9370 if (s_addr <= uchar_end_in_config) {
9371 /*
9372 * This is a char field. Swap char fields before they are
9373 * swapped again by AscWriteEEPWord().
9374 */
9375 word = cpu_to_le16(*wbuf);
9376 if (word !=
9377 AscWriteEEPWord(iop_base, (uchar)s_addr, word)) {
9378 n_error++;
9379 }
9380 } else {
9381 /* Don't swap word field at the end - cntl field. */
9382 if (*wbuf !=
9383 AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9384 n_error++;
9385 }
27c868c2 9386 }
51219358
MW		 9387 sum += *wbuf; /* Checksum calculated from word values. */
9388 }
9389 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
9390 *wbuf = sum;
9391 if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) {
9392 n_error++;
27c868c2 9393 }
1da177e4 9394
51219358
MW		 9395 /* Read EEPROM back again. */
9396 wbuf = (ushort *)cfg_buf;
27c868c2 9397 /*
51219358 9398 * Read two config words; Byte-swapping done by AscReadEEPWord().
27c868c2 9399 */
51219358
MW		 9400 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9401 if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) {
9402 n_error++;
27c868c2
MW		 9403 }
9404 }
51219358
MW		 9405 if (bus_type & ASC_IS_VL) {
9406 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9407 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9408 } else {
9409 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9410 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9411 }
9412 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9413 if (s_addr <= uchar_end_in_config) {
9414 /*
9415 * Swap all char fields. Must unswap bytes already swapped
9416 * by AscReadEEPWord().
9417 */
9418 word =
9419 le16_to_cpu(AscReadEEPWord
9420 (iop_base, (uchar)s_addr));
27c868c2 9421 } else {
51219358
MW		 9422 /* Don't swap word field at the end - cntl field. */
9423 word = AscReadEEPWord(iop_base, (uchar)s_addr);
9424 }
9425 if (*wbuf != word) {
9426 n_error++;
27c868c2
MW		 9427 }
9428 }
51219358
MW		 9429 /* Read checksum; Byte swapping not needed. */
9430 if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) {
9431 n_error++;
27c868c2 9432 }
51219358
MW		 9433 return n_error;
9434}
1da177e4 9435
6f039790
GKH		 9436static int AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9437 ushort bus_type)
51219358
MW		 9438{
9439 int retry;
9440 int n_error;
27c868c2 9441
51219358
MW		 9442 retry = 0;
9443 while (TRUE) {
9444 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
9445 bus_type)) == 0) {
9446 break;
9447 }
9448 if (++retry > ASC_EEP_MAX_RETRY) {
9449 break;
9450 }
9451 }
9452 return n_error;
9453}
27c868c2 9454
6f039790 9455static ushort AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
51219358
MW		 9456{
9457 ASCEEP_CONFIG eep_config_buf;
9458 ASCEEP_CONFIG *eep_config;
9459 PortAddr iop_base;
9460 ushort chksum;
9461 ushort warn_code;
9462 ushort cfg_msw, cfg_lsw;
9463 int i;
9464 int write_eep = 0;
27c868c2 9465
51219358
MW		 9466 iop_base = asc_dvc->iop_base;
9467 warn_code = 0;
9468 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
9469 AscStopQueueExe(iop_base);
9470 if ((AscStopChip(iop_base) == FALSE) ||
9471 (AscGetChipScsiCtrl(iop_base) != 0)) {
9472 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
9473 AscResetChipAndScsiBus(asc_dvc);
9474 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
9475 }
9476 if (AscIsChipHalted(iop_base) == FALSE) {
9477 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
9478 return (warn_code);
9479 }
9480 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
9481 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
9482 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
9483 return (warn_code);
9484 }
9485 eep_config = (ASCEEP_CONFIG *)&eep_config_buf;
9486 cfg_msw = AscGetChipCfgMsw(iop_base);
9487 cfg_lsw = AscGetChipCfgLsw(iop_base);
9488 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
9489 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9490 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
9491 AscSetChipCfgMsw(iop_base, cfg_msw);
9492 }
9493 chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
b352f923 9494 ASC_DBG(1, "chksum 0x%x\n", chksum);
51219358
MW		 9495 if (chksum == 0) {
9496 chksum = 0xaa55;
9497 }
9498 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
9499 warn_code |= ASC_WARN_AUTO_CONFIG;
9500 if (asc_dvc->cfg->chip_version == 3) {
9501 if (eep_config->cfg_lsw != cfg_lsw) {
9502 warn_code |= ASC_WARN_EEPROM_RECOVER;
9503 eep_config->cfg_lsw =
9504 AscGetChipCfgLsw(iop_base);
9505 }
9506 if (eep_config->cfg_msw != cfg_msw) {
9507 warn_code |= ASC_WARN_EEPROM_RECOVER;
9508 eep_config->cfg_msw =
9509 AscGetChipCfgMsw(iop_base);
9510 }
9511 }
9512 }
9513 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9514 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
b352f923 9515 ASC_DBG(1, "eep_config->chksum 0x%x\n", eep_config->chksum);
51219358
MW		 9516 if (chksum != eep_config->chksum) {
9517 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
9518 ASC_CHIP_VER_PCI_ULTRA_3050) {
b352f923 9519 ASC_DBG(1, "chksum error ignored; EEPROM-less board\n");
51219358
MW		 9520 eep_config->init_sdtr = 0xFF;
9521 eep_config->disc_enable = 0xFF;
9522 eep_config->start_motor = 0xFF;
9523 eep_config->use_cmd_qng = 0;
9524 eep_config->max_total_qng = 0xF0;
9525 eep_config->max_tag_qng = 0x20;
9526 eep_config->cntl = 0xBFFF;
9527 ASC_EEP_SET_CHIP_ID(eep_config, 7);
9528 eep_config->no_scam = 0;
9529 eep_config->adapter_info[0] = 0;
9530 eep_config->adapter_info[1] = 0;
9531 eep_config->adapter_info[2] = 0;
9532 eep_config->adapter_info[3] = 0;
9533 eep_config->adapter_info[4] = 0;
9534 /* Indicate EEPROM-less board. */
9535 eep_config->adapter_info[5] = 0xBB;
27c868c2 9536 } else {
51219358
MW		 9537 ASC_PRINT
9538 ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
9539 write_eep = 1;
9540 warn_code |= ASC_WARN_EEPROM_CHKSUM;
9541 }
9542 }
9543 asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
9544 asc_dvc->cfg->disc_enable = eep_config->disc_enable;
9545 asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
9546 asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
9547 asc_dvc->start_motor = eep_config->start_motor;
9548 asc_dvc->dvc_cntl = eep_config->cntl;
9549 asc_dvc->no_scam = eep_config->no_scam;
9550 asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
9551 asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
9552 asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
9553 asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
9554 asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
9555 asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
9556 if (!AscTestExternalLram(asc_dvc)) {
9557 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) ==
9558 ASC_IS_PCI_ULTRA)) {
9559 eep_config->max_total_qng =
9560 ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
9561 eep_config->max_tag_qng =
9562 ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
9563 } else {
9564 eep_config->cfg_msw |= 0x0800;
9565 cfg_msw |= 0x0800;
9566 AscSetChipCfgMsw(iop_base, cfg_msw);
9567 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
9568 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
27c868c2 9569 }
51219358
MW		 9570 } else {
9571 }
9572 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
9573 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
9574 }
9575 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
9576 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
9577 }
9578 if (eep_config->max_tag_qng > eep_config->max_total_qng) {
9579 eep_config->max_tag_qng = eep_config->max_total_qng;
9580 }
9581 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
9582 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
9583 }
9584 asc_dvc->max_total_qng = eep_config->max_total_qng;
9585 if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
9586 eep_config->use_cmd_qng) {
9587 eep_config->disc_enable = eep_config->use_cmd_qng;
9588 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
9589 }
51219358
MW		 9590 ASC_EEP_SET_CHIP_ID(eep_config,
9591 ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
9592 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
9593 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
9594 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
afbb68c3 9595 asc_dvc->min_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
27c868c2 9596 }
1da177e4 9597
51219358
MW		 9598 for (i = 0; i <= ASC_MAX_TID; i++) {
9599 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
9600 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
9601 asc_dvc->cfg->sdtr_period_offset[i] =
9602 (uchar)(ASC_DEF_SDTR_OFFSET |
afbb68c3 9603 (asc_dvc->min_sdtr_index << 4));
51219358
MW		 9604 }
9605 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
9606 if (write_eep) {
9607 if ((i = AscSetEEPConfig(iop_base, eep_config,
9608 asc_dvc->bus_type)) != 0) {
9609 ASC_PRINT1
9610 ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n",
9611 i);
27c868c2 9612 } else {
51219358
MW		 9613 ASC_PRINT
9614 ("AscInitFromEEP: Successfully re-wrote EEPROM.\n");
27c868c2
MW		 9615 }
9616 }
51219358 9617 return (warn_code);
1da177e4
LT		 9618}
9619
6f039790 9620static int AscInitGetConfig(struct Scsi_Host *shost)
1da177e4 9621{
9d0e96eb
MW		 9622 struct asc_board *board = shost_priv(shost);
9623 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
51219358 9624 unsigned short warn_code = 0;
27c868c2 9625
51219358
MW		 9626 asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
9627 if (asc_dvc->err_code != 0)
9628 return asc_dvc->err_code;
27c868c2 9629
51219358
MW		 9630 if (AscFindSignature(asc_dvc->iop_base)) {
9631 warn_code |= AscInitAscDvcVar(asc_dvc);
9632 warn_code |= AscInitFromEEP(asc_dvc);
9633 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
9634 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
9635 asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
9636 } else {
9637 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
9638 }
27c868c2 9639
51219358
MW		 9640 switch (warn_code) {
9641 case 0: /* No error */
9642 break;
9643 case ASC_WARN_IO_PORT_ROTATE:
9d0e96eb
MW		 9644 shost_printk(KERN_WARNING, shost, "I/O port address "
9645 "modified\n");
51219358
MW		 9646 break;
9647 case ASC_WARN_AUTO_CONFIG:
9d0e96eb
MW		 9648 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
9649 "enabled\n");
51219358
MW		 9650 break;
9651 case ASC_WARN_EEPROM_CHKSUM:
9d0e96eb 9652 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
51219358
MW		 9653 break;
9654 case ASC_WARN_IRQ_MODIFIED:
9d0e96eb 9655 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
51219358
MW		 9656 break;
9657 case ASC_WARN_CMD_QNG_CONFLICT:
9d0e96eb
MW		 9658 shost_printk(KERN_WARNING, shost, "tag queuing enabled w/o "
9659 "disconnects\n");
51219358
MW		 9660 break;
9661 default:
9d0e96eb
MW		 9662 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
9663 warn_code);
51219358
MW		 9664 break;
9665 }
1da177e4 9666
9d0e96eb
MW		 9667 if (asc_dvc->err_code != 0)
9668 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
9669 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
27c868c2 9670
51219358
MW		 9671 return asc_dvc->err_code;
9672}
1da177e4 9673
6f039790 9674static int AscInitSetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
51219358 9675{
9d0e96eb
MW		 9676 struct asc_board *board = shost_priv(shost);
9677 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
51219358
MW		 9678 PortAddr iop_base = asc_dvc->iop_base;
9679 unsigned short cfg_msw;
9680 unsigned short warn_code = 0;
1da177e4 9681
51219358
MW		 9682 asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
9683 if (asc_dvc->err_code != 0)
9684 return asc_dvc->err_code;
9685 if (!AscFindSignature(asc_dvc->iop_base)) {
9686 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
9687 return asc_dvc->err_code;
27c868c2 9688 }
1da177e4 9689
51219358
MW		 9690 cfg_msw = AscGetChipCfgMsw(iop_base);
9691 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
9692 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9693 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
9694 AscSetChipCfgMsw(iop_base, cfg_msw);
9695 }
9696 if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
9697 asc_dvc->cfg->cmd_qng_enabled) {
9698 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
9699 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
9700 }
9701 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
9702 warn_code |= ASC_WARN_AUTO_CONFIG;
9703 }
51219358
MW		 9704#ifdef CONFIG_PCI
9705 if (asc_dvc->bus_type & ASC_IS_PCI) {
9706 cfg_msw &= 0xFFC0;
9707 AscSetChipCfgMsw(iop_base, cfg_msw);
9708 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
27c868c2 9709 } else {
51219358
MW		 9710 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
9711 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
9712 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
9713 asc_dvc->bug_fix_cntl |=
9714 ASC_BUG_FIX_ASYN_USE_SYN;
9715 }
27c868c2 9716 }
51219358
MW		 9717 } else
9718#endif /* CONFIG_PCI */
9719 if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
9720 if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
9721 == ASC_CHIP_VER_ASYN_BUG) {
9722 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
27c868c2
MW		 9723 }
9724 }
51219358
MW		 9725 if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
9726 asc_dvc->cfg->chip_scsi_id) {
9727 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
9728 }
9729#ifdef CONFIG_ISA
9730 if (asc_dvc->bus_type & ASC_IS_ISA) {
9731 AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
9732 AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
9733 }
9734#endif /* CONFIG_ISA */
1da177e4 9735
51219358
MW		 9736 asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
9737
9738 switch (warn_code) {
9739 case 0: /* No error. */
9740 break;
9741 case ASC_WARN_IO_PORT_ROTATE:
9d0e96eb
MW		 9742 shost_printk(KERN_WARNING, shost, "I/O port address "
9743 "modified\n");
51219358
MW		 9744 break;
9745 case ASC_WARN_AUTO_CONFIG:
9d0e96eb
MW		 9746 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
9747 "enabled\n");
51219358
MW		 9748 break;
9749 case ASC_WARN_EEPROM_CHKSUM:
9d0e96eb 9750 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
51219358
MW		 9751 break;
9752 case ASC_WARN_IRQ_MODIFIED:
9d0e96eb 9753 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
51219358
MW		 9754 break;
9755 case ASC_WARN_CMD_QNG_CONFLICT:
9d0e96eb
MW		 9756 shost_printk(KERN_WARNING, shost, "tag queuing w/o "
9757 "disconnects\n");
51219358
MW		 9758 break;
9759 default:
9d0e96eb
MW		 9760 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
9761 warn_code);
51219358 9762 break;
27c868c2 9763 }
1da177e4 9764
9d0e96eb
MW		 9765 if (asc_dvc->err_code != 0)
9766 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
9767 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
27c868c2 9768
51219358
MW		 9769 return asc_dvc->err_code;
9770}
27c868c2 9771
51219358
MW		 9772/*
9773 * EEPROM Configuration.
9774 *
9775 * All drivers should use this structure to set the default EEPROM
9776 * configuration. The BIOS now uses this structure when it is built.
9777 * Additional structure information can be found in a_condor.h where
9778 * the structure is defined.
9779 *
9780 * The *_Field_IsChar structs are needed to correct for endianness.
9781 * These values are read from the board 16 bits at a time directly
9782 * into the structs. Because some fields are char, the values will be
9783 * in the wrong order. The *_Field_IsChar tells when to flip the
9784 * bytes. Data read and written to PCI memory is automatically swapped
9785 * on big-endian platforms so char fields read as words are actually being
9786 * unswapped on big-endian platforms.
9787 */
6f039790 9788static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config = {
51219358
MW		 9789 ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
9790 0x0000, /* cfg_msw */
9791 0xFFFF, /* disc_enable */
9792 0xFFFF, /* wdtr_able */
9793 0xFFFF, /* sdtr_able */
9794 0xFFFF, /* start_motor */
9795 0xFFFF, /* tagqng_able */
9796 0xFFFF, /* bios_scan */
9797 0, /* scam_tolerant */
9798 7, /* adapter_scsi_id */
9799 0, /* bios_boot_delay */
9800 3, /* scsi_reset_delay */
9801 0, /* bios_id_lun */
9802 0, /* termination */
9803 0, /* reserved1 */
9804 0xFFE7, /* bios_ctrl */
9805 0xFFFF, /* ultra_able */
9806 0, /* reserved2 */
9807 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */
9808 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9809 0, /* dvc_cntl */
9810 0, /* bug_fix */
9811 0, /* serial_number_word1 */
9812 0, /* serial_number_word2 */
9813 0, /* serial_number_word3 */
9814 0, /* check_sum */
9815 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9816 , /* oem_name[16] */
9817 0, /* dvc_err_code */
9818 0, /* adv_err_code */
9819 0, /* adv_err_addr */
9820 0, /* saved_dvc_err_code */
9821 0, /* saved_adv_err_code */
9822 0, /* saved_adv_err_addr */
9823 0 /* num_of_err */
9824};
27c868c2 9825
6f039790 9826static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar = {
51219358
MW		 9827 0, /* cfg_lsw */
9828 0, /* cfg_msw */
9829 0, /* -disc_enable */
9830 0, /* wdtr_able */
9831 0, /* sdtr_able */
9832 0, /* start_motor */
9833 0, /* tagqng_able */
9834 0, /* bios_scan */
9835 0, /* scam_tolerant */
9836 1, /* adapter_scsi_id */
9837 1, /* bios_boot_delay */
9838 1, /* scsi_reset_delay */
9839 1, /* bios_id_lun */
9840 1, /* termination */
9841 1, /* reserved1 */
9842 0, /* bios_ctrl */
9843 0, /* ultra_able */
9844 0, /* reserved2 */
9845 1, /* max_host_qng */
9846 1, /* max_dvc_qng */
9847 0, /* dvc_cntl */
9848 0, /* bug_fix */
9849 0, /* serial_number_word1 */
9850 0, /* serial_number_word2 */
9851 0, /* serial_number_word3 */
9852 0, /* check_sum */
9853 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
9854 , /* oem_name[16] */
9855 0, /* dvc_err_code */
9856 0, /* adv_err_code */
9857 0, /* adv_err_addr */
9858 0, /* saved_dvc_err_code */
9859 0, /* saved_adv_err_code */
9860 0, /* saved_adv_err_addr */
9861 0 /* num_of_err */
9862};
1da177e4 9863
6f039790 9864static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config = {
51219358
MW		 9865 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
9866 0x0000, /* 01 cfg_msw */
9867 0xFFFF, /* 02 disc_enable */
9868 0xFFFF, /* 03 wdtr_able */
9869 0x4444, /* 04 sdtr_speed1 */
9870 0xFFFF, /* 05 start_motor */
9871 0xFFFF, /* 06 tagqng_able */
9872 0xFFFF, /* 07 bios_scan */
9873 0, /* 08 scam_tolerant */
9874 7, /* 09 adapter_scsi_id */
9875 0, /* bios_boot_delay */
9876 3, /* 10 scsi_reset_delay */
9877 0, /* bios_id_lun */
9878 0, /* 11 termination_se */
9879 0, /* termination_lvd */
9880 0xFFE7, /* 12 bios_ctrl */
9881 0x4444, /* 13 sdtr_speed2 */
9882 0x4444, /* 14 sdtr_speed3 */
9883 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
9884 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9885 0, /* 16 dvc_cntl */
9886 0x4444, /* 17 sdtr_speed4 */
9887 0, /* 18 serial_number_word1 */
9888 0, /* 19 serial_number_word2 */
9889 0, /* 20 serial_number_word3 */
9890 0, /* 21 check_sum */
9891 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9892 , /* 22-29 oem_name[16] */
9893 0, /* 30 dvc_err_code */
9894 0, /* 31 adv_err_code */
9895 0, /* 32 adv_err_addr */
9896 0, /* 33 saved_dvc_err_code */
9897 0, /* 34 saved_adv_err_code */
9898 0, /* 35 saved_adv_err_addr */
9899 0, /* 36 reserved */
9900 0, /* 37 reserved */
9901 0, /* 38 reserved */
9902 0, /* 39 reserved */
9903 0, /* 40 reserved */
9904 0, /* 41 reserved */
9905 0, /* 42 reserved */
9906 0, /* 43 reserved */
9907 0, /* 44 reserved */
9908 0, /* 45 reserved */
9909 0, /* 46 reserved */
9910 0, /* 47 reserved */
9911 0, /* 48 reserved */
9912 0, /* 49 reserved */
9913 0, /* 50 reserved */
9914 0, /* 51 reserved */
9915 0, /* 52 reserved */
9916 0, /* 53 reserved */
9917 0, /* 54 reserved */
9918 0, /* 55 reserved */
9919 0, /* 56 cisptr_lsw */
9920 0, /* 57 cisprt_msw */
9921 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
9922 PCI_DEVICE_ID_38C0800_REV1, /* 59 subsysid */
9923 0, /* 60 reserved */
9924 0, /* 61 reserved */
9925 0, /* 62 reserved */
9926 0 /* 63 reserved */
9927};
27c868c2 9928
6f039790 9929static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar = {
51219358
MW		 9930 0, /* 00 cfg_lsw */
9931 0, /* 01 cfg_msw */
9932 0, /* 02 disc_enable */
9933 0, /* 03 wdtr_able */
9934 0, /* 04 sdtr_speed1 */
9935 0, /* 05 start_motor */
9936 0, /* 06 tagqng_able */
9937 0, /* 07 bios_scan */
9938 0, /* 08 scam_tolerant */
9939 1, /* 09 adapter_scsi_id */
9940 1, /* bios_boot_delay */
9941 1, /* 10 scsi_reset_delay */
9942 1, /* bios_id_lun */
9943 1, /* 11 termination_se */
9944 1, /* termination_lvd */
9945 0, /* 12 bios_ctrl */
9946 0, /* 13 sdtr_speed2 */
9947 0, /* 14 sdtr_speed3 */
9948 1, /* 15 max_host_qng */
9949 1, /* max_dvc_qng */
9950 0, /* 16 dvc_cntl */
9951 0, /* 17 sdtr_speed4 */
9952 0, /* 18 serial_number_word1 */
9953 0, /* 19 serial_number_word2 */
9954 0, /* 20 serial_number_word3 */
9955 0, /* 21 check_sum */
9956 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
9957 , /* 22-29 oem_name[16] */
9958 0, /* 30 dvc_err_code */
9959 0, /* 31 adv_err_code */
9960 0, /* 32 adv_err_addr */
9961 0, /* 33 saved_dvc_err_code */
9962 0, /* 34 saved_adv_err_code */
9963 0, /* 35 saved_adv_err_addr */
9964 0, /* 36 reserved */
9965 0, /* 37 reserved */
9966 0, /* 38 reserved */
9967 0, /* 39 reserved */
9968 0, /* 40 reserved */
9969 0, /* 41 reserved */
9970 0, /* 42 reserved */
9971 0, /* 43 reserved */
9972 0, /* 44 reserved */
9973 0, /* 45 reserved */
9974 0, /* 46 reserved */
9975 0, /* 47 reserved */
9976 0, /* 48 reserved */
9977 0, /* 49 reserved */
9978 0, /* 50 reserved */
9979 0, /* 51 reserved */
9980 0, /* 52 reserved */
9981 0, /* 53 reserved */
9982 0, /* 54 reserved */
9983 0, /* 55 reserved */
9984 0, /* 56 cisptr_lsw */
9985 0, /* 57 cisprt_msw */
9986 0, /* 58 subsysvid */
9987 0, /* 59 subsysid */
9988 0, /* 60 reserved */
9989 0, /* 61 reserved */
9990 0, /* 62 reserved */
9991 0 /* 63 reserved */
9992};
27c868c2 9993
6f039790 9994static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config = {
51219358
MW		 9995 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
9996 0x0000, /* 01 cfg_msw */
9997 0xFFFF, /* 02 disc_enable */
9998 0xFFFF, /* 03 wdtr_able */
9999 0x5555, /* 04 sdtr_speed1 */
10000 0xFFFF, /* 05 start_motor */
10001 0xFFFF, /* 06 tagqng_able */
10002 0xFFFF, /* 07 bios_scan */
10003 0, /* 08 scam_tolerant */
10004 7, /* 09 adapter_scsi_id */
10005 0, /* bios_boot_delay */
10006 3, /* 10 scsi_reset_delay */
10007 0, /* bios_id_lun */
10008 0, /* 11 termination_se */
10009 0, /* termination_lvd */
10010 0xFFE7, /* 12 bios_ctrl */
10011 0x5555, /* 13 sdtr_speed2 */
10012 0x5555, /* 14 sdtr_speed3 */
10013 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
10014 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
10015 0, /* 16 dvc_cntl */
10016 0x5555, /* 17 sdtr_speed4 */
10017 0, /* 18 serial_number_word1 */
10018 0, /* 19 serial_number_word2 */
10019 0, /* 20 serial_number_word3 */
10020 0, /* 21 check_sum */
10021 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
10022 , /* 22-29 oem_name[16] */
10023 0, /* 30 dvc_err_code */
10024 0, /* 31 adv_err_code */
10025 0, /* 32 adv_err_addr */
10026 0, /* 33 saved_dvc_err_code */
10027 0, /* 34 saved_adv_err_code */
10028 0, /* 35 saved_adv_err_addr */
10029 0, /* 36 reserved */
10030 0, /* 37 reserved */
10031 0, /* 38 reserved */
10032 0, /* 39 reserved */
10033 0, /* 40 reserved */
10034 0, /* 41 reserved */
10035 0, /* 42 reserved */
10036 0, /* 43 reserved */
10037 0, /* 44 reserved */
10038 0, /* 45 reserved */
10039 0, /* 46 reserved */
10040 0, /* 47 reserved */
10041 0, /* 48 reserved */
10042 0, /* 49 reserved */
10043 0, /* 50 reserved */
10044 0, /* 51 reserved */
10045 0, /* 52 reserved */
10046 0, /* 53 reserved */
10047 0, /* 54 reserved */
10048 0, /* 55 reserved */
10049 0, /* 56 cisptr_lsw */
10050 0, /* 57 cisprt_msw */
10051 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
10052 PCI_DEVICE_ID_38C1600_REV1, /* 59 subsysid */
10053 0, /* 60 reserved */
10054 0, /* 61 reserved */
10055 0, /* 62 reserved */
10056 0 /* 63 reserved */
10057};
1da177e4 10058
6f039790 10059static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar = {
51219358
MW		 10060 0, /* 00 cfg_lsw */
10061 0, /* 01 cfg_msw */
10062 0, /* 02 disc_enable */
10063 0, /* 03 wdtr_able */
10064 0, /* 04 sdtr_speed1 */
10065 0, /* 05 start_motor */
10066 0, /* 06 tagqng_able */
10067 0, /* 07 bios_scan */
10068 0, /* 08 scam_tolerant */
10069 1, /* 09 adapter_scsi_id */
10070 1, /* bios_boot_delay */
10071 1, /* 10 scsi_reset_delay */
10072 1, /* bios_id_lun */
10073 1, /* 11 termination_se */
10074 1, /* termination_lvd */
10075 0, /* 12 bios_ctrl */
10076 0, /* 13 sdtr_speed2 */
10077 0, /* 14 sdtr_speed3 */
10078 1, /* 15 max_host_qng */
10079 1, /* max_dvc_qng */
10080 0, /* 16 dvc_cntl */
10081 0, /* 17 sdtr_speed4 */
10082 0, /* 18 serial_number_word1 */
10083 0, /* 19 serial_number_word2 */
10084 0, /* 20 serial_number_word3 */
10085 0, /* 21 check_sum */
10086 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
10087 , /* 22-29 oem_name[16] */
10088 0, /* 30 dvc_err_code */
10089 0, /* 31 adv_err_code */
10090 0, /* 32 adv_err_addr */
10091 0, /* 33 saved_dvc_err_code */
10092 0, /* 34 saved_adv_err_code */
10093 0, /* 35 saved_adv_err_addr */
10094 0, /* 36 reserved */
10095 0, /* 37 reserved */
10096 0, /* 38 reserved */
10097 0, /* 39 reserved */
10098 0, /* 40 reserved */
10099 0, /* 41 reserved */
10100 0, /* 42 reserved */
10101 0, /* 43 reserved */
10102 0, /* 44 reserved */
10103 0, /* 45 reserved */
10104 0, /* 46 reserved */
10105 0, /* 47 reserved */
10106 0, /* 48 reserved */
10107 0, /* 49 reserved */
10108 0, /* 50 reserved */
10109 0, /* 51 reserved */
10110 0, /* 52 reserved */
10111 0, /* 53 reserved */
10112 0, /* 54 reserved */
10113 0, /* 55 reserved */
10114 0, /* 56 cisptr_lsw */
10115 0, /* 57 cisprt_msw */
10116 0, /* 58 subsysvid */
10117 0, /* 59 subsysid */
10118 0, /* 60 reserved */
10119 0, /* 61 reserved */
10120 0, /* 62 reserved */
10121 0 /* 63 reserved */
10122};
1da177e4 10123
51219358 10124#ifdef CONFIG_PCI
1da177e4 10125/*
51219358 10126 * Wait for EEPROM command to complete
1da177e4 10127 */
6f039790 10128static void AdvWaitEEPCmd(AdvPortAddr iop_base)
1da177e4 10129{
51219358 10130 int eep_delay_ms;
27c868c2 10131
51219358
MW		 10132 for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) {
10133 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) &
10134 ASC_EEP_CMD_DONE) {
10135 break;
27c868c2 10136 }
51219358 10137 mdelay(1);
27c868c2 10138 }
51219358
MW		 10139 if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) ==
10140 0)
10141 BUG();
1da177e4
LT		 10142}
10143
10144/*
51219358 10145 * Read the EEPROM from specified location
1da177e4 10146 */
6f039790 10147static ushort AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
51219358
MW		 10148{
10149 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10150 ASC_EEP_CMD_READ | eep_word_addr);
10151 AdvWaitEEPCmd(iop_base);
10152 return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
10153}
10154
10155/*
10156 * Write the EEPROM from 'cfg_buf'.
10157 */
6f039790
GKH		 10158static void AdvSet3550EEPConfig(AdvPortAddr iop_base,
10159 ADVEEP_3550_CONFIG *cfg_buf)
1da177e4 10160{
27c868c2 10161 ushort *wbuf;
51219358 10162 ushort addr, chksum;
27c868c2
MW		 10163 ushort *charfields;
10164
27c868c2 10165 wbuf = (ushort *)cfg_buf;
51219358 10166 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
27c868c2
MW		 10167 chksum = 0;
10168
51219358
MW		 10169 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10170 AdvWaitEEPCmd(iop_base);
10171
10172 /*
10173 * Write EEPROM from word 0 to word 20.
10174 */
10175 for (addr = ADV_EEP_DVC_CFG_BEGIN;
10176 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10177 ushort word;
10178
27c868c2 10179 if (*charfields++) {
51219358 10180 word = cpu_to_le16(*wbuf);
27c868c2 10181 } else {
51219358 10182 word = *wbuf;
27c868c2 10183 }
51219358
MW		 10184 chksum += *wbuf; /* Checksum is calculated from word values. */
10185 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10186 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10187 ASC_EEP_CMD_WRITE | addr);
10188 AdvWaitEEPCmd(iop_base);
10189 mdelay(ADV_EEP_DELAY_MS);
27c868c2 10190 }
51219358
MW		 10191
10192 /*
10193 * Write EEPROM checksum at word 21.
10194 */
10195 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10196 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10197 AdvWaitEEPCmd(iop_base);
27c868c2
MW		 10198 wbuf++;
10199 charfields++;
10200
51219358
MW		 10201 /*
10202 * Write EEPROM OEM name at words 22 to 29.
10203 */
10204 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10205 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10206 ushort word;
10207
27c868c2 10208 if (*charfields++) {
51219358
MW		 10209 word = cpu_to_le16(*wbuf);
10210 } else {
10211 word = *wbuf;
27c868c2 10212 }
51219358
MW		 10213 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10214 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10215 ASC_EEP_CMD_WRITE | addr);
10216 AdvWaitEEPCmd(iop_base);
27c868c2 10217 }
51219358
MW		 10218 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10219 AdvWaitEEPCmd(iop_base);
1da177e4
LT		 10220}
10221
10222/*
51219358 10223 * Write the EEPROM from 'cfg_buf'.
1da177e4 10224 */
6f039790
GKH		 10225static void AdvSet38C0800EEPConfig(AdvPortAddr iop_base,
10226 ADVEEP_38C0800_CONFIG *cfg_buf)
1da177e4 10227{
27c868c2 10228 ushort *wbuf;
27c868c2 10229 ushort *charfields;
51219358 10230 ushort addr, chksum;
27c868c2 10231
27c868c2 10232 wbuf = (ushort *)cfg_buf;
51219358 10233 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
27c868c2
MW		 10234 chksum = 0;
10235
51219358
MW		 10236 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10237 AdvWaitEEPCmd(iop_base);
10238
10239 /*
10240 * Write EEPROM from word 0 to word 20.
10241 */
10242 for (addr = ADV_EEP_DVC_CFG_BEGIN;
10243 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10244 ushort word;
10245
27c868c2 10246 if (*charfields++) {
51219358 10247 word = cpu_to_le16(*wbuf);
27c868c2 10248 } else {
51219358 10249 word = *wbuf;
27c868c2 10250 }
51219358
MW		 10251 chksum += *wbuf; /* Checksum is calculated from word values. */
10252 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10253 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10254 ASC_EEP_CMD_WRITE | addr);
10255 AdvWaitEEPCmd(iop_base);
10256 mdelay(ADV_EEP_DELAY_MS);
27c868c2 10257 }
51219358
MW		 10258
10259 /*
10260 * Write EEPROM checksum at word 21.
10261 */
10262 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10263 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10264 AdvWaitEEPCmd(iop_base);
27c868c2
MW		 10265 wbuf++;
10266 charfields++;
10267
51219358
MW		 10268 /*
10269 * Write EEPROM OEM name at words 22 to 29.
10270 */
10271 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10272 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10273 ushort word;
10274
27c868c2 10275 if (*charfields++) {
51219358
MW		 10276 word = cpu_to_le16(*wbuf);
10277 } else {
10278 word = *wbuf;
27c868c2 10279 }
51219358
MW		 10280 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10281 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10282 ASC_EEP_CMD_WRITE | addr);
10283 AdvWaitEEPCmd(iop_base);
27c868c2 10284 }
51219358 10285 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
27c868c2 10286 AdvWaitEEPCmd(iop_base);
1da177e4
LT		 10287}
10288
10289/*
10290 * Write the EEPROM from 'cfg_buf'.
10291 */
6f039790
GKH		 10292static void AdvSet38C1600EEPConfig(AdvPortAddr iop_base,
10293 ADVEEP_38C1600_CONFIG *cfg_buf)
1da177e4 10294{
27c868c2 10295 ushort *wbuf;
27c868c2 10296 ushort *charfields;
51219358 10297 ushort addr, chksum;
27c868c2
MW		 10298
10299 wbuf = (ushort *)cfg_buf;
51219358 10300 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
27c868c2
MW		 10301 chksum = 0;
10302
10303 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10304 AdvWaitEEPCmd(iop_base);
10305
10306 /*
10307 * Write EEPROM from word 0 to word 20.
10308 */
10309 for (addr = ADV_EEP_DVC_CFG_BEGIN;
10310 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10311 ushort word;
10312
10313 if (*charfields++) {
10314 word = cpu_to_le16(*wbuf);
10315 } else {
10316 word = *wbuf;
10317 }
10318 chksum += *wbuf; /* Checksum is calculated from word values. */
10319 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10320 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10321 ASC_EEP_CMD_WRITE | addr);
10322 AdvWaitEEPCmd(iop_base);
b009bef6 10323 mdelay(ADV_EEP_DELAY_MS);
27c868c2 10324 }
1da177e4 10325
27c868c2
MW		 10326 /*
10327 * Write EEPROM checksum at word 21.
10328 */
10329 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10330 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10331 AdvWaitEEPCmd(iop_base);
10332 wbuf++;
10333 charfields++;
10334
10335 /*
10336 * Write EEPROM OEM name at words 22 to 29.
10337 */
10338 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10339 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10340 ushort word;
10341
10342 if (*charfields++) {
10343 word = cpu_to_le16(*wbuf);
10344 } else {
10345 word = *wbuf;
10346 }
10347 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10348 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10349 ASC_EEP_CMD_WRITE | addr);
10350 AdvWaitEEPCmd(iop_base);
10351 }
10352 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10353 AdvWaitEEPCmd(iop_base);
1da177e4
LT		 10354}
10355
10356/*
51219358
MW		 10357 * Read EEPROM configuration into the specified buffer.
10358 *
10359 * Return a checksum based on the EEPROM configuration read.
1da177e4 10360 */
6f039790
GKH		 10361static ushort AdvGet3550EEPConfig(AdvPortAddr iop_base,
10362 ADVEEP_3550_CONFIG *cfg_buf)
1da177e4 10363{
51219358 10364 ushort wval, chksum;
27c868c2 10365 ushort *wbuf;
51219358 10366 int eep_addr;
27c868c2 10367 ushort *charfields;
27c868c2 10368
51219358 10369 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
27c868c2 10370 wbuf = (ushort *)cfg_buf;
27c868c2
MW		 10371 chksum = 0;
10372
51219358
MW		 10373 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10374 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10375 wval = AdvReadEEPWord(iop_base, eep_addr);
10376 chksum += wval; /* Checksum is calculated from word values. */
10377 if (*charfields++) {
10378 *wbuf = le16_to_cpu(wval);
10379 } else {
10380 *wbuf = wval;
10381 }
10382 }
10383 /* Read checksum word. */
10384 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10385 wbuf++;
10386 charfields++;
27c868c2 10387
51219358
MW		 10388 /* Read rest of EEPROM not covered by the checksum. */
10389 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10390 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10391 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10392 if (*charfields++) {
10393 *wbuf = le16_to_cpu(*wbuf);
10394 }
10395 }
10396 return chksum;
10397}
10398
10399/*
10400 * Read EEPROM configuration into the specified buffer.
10401 *
10402 * Return a checksum based on the EEPROM configuration read.
10403 */
6f039790
GKH		 10404static ushort AdvGet38C0800EEPConfig(AdvPortAddr iop_base,
10405 ADVEEP_38C0800_CONFIG *cfg_buf)
51219358
MW		 10406{
10407 ushort wval, chksum;
10408 ushort *wbuf;
10409 int eep_addr;
10410 ushort *charfields;
27c868c2 10411
51219358
MW		 10412 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
10413 wbuf = (ushort *)cfg_buf;
10414 chksum = 0;
10415
10416 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10417 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10418 wval = AdvReadEEPWord(iop_base, eep_addr);
10419 chksum += wval; /* Checksum is calculated from word values. */
27c868c2 10420 if (*charfields++) {
51219358 10421 *wbuf = le16_to_cpu(wval);
27c868c2 10422 } else {
51219358 10423 *wbuf = wval;
27c868c2 10424 }
27c868c2 10425 }
51219358
MW		 10426 /* Read checksum word. */
10427 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
27c868c2
MW		 10428 wbuf++;
10429 charfields++;
10430
51219358
MW		 10431 /* Read rest of EEPROM not covered by the checksum. */
10432 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10433 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10434 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
27c868c2 10435 if (*charfields++) {
51219358 10436 *wbuf = le16_to_cpu(*wbuf);
27c868c2 10437 }
27c868c2 10438 }
51219358 10439 return chksum;
1da177e4
LT		 10440}
10441
10442/*
51219358
MW		 10443 * Read EEPROM configuration into the specified buffer.
10444 *
10445 * Return a checksum based on the EEPROM configuration read.
1da177e4 10446 */
6f039790
GKH		 10447static ushort AdvGet38C1600EEPConfig(AdvPortAddr iop_base,
10448 ADVEEP_38C1600_CONFIG *cfg_buf)
1da177e4 10449{
51219358 10450 ushort wval, chksum;
27c868c2 10451 ushort *wbuf;
51219358 10452 int eep_addr;
27c868c2 10453 ushort *charfields;
27c868c2 10454
27c868c2 10455 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
51219358 10456 wbuf = (ushort *)cfg_buf;
27c868c2
MW		 10457 chksum = 0;
10458
51219358
MW		 10459 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10460 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10461 wval = AdvReadEEPWord(iop_base, eep_addr);
10462 chksum += wval; /* Checksum is calculated from word values. */
27c868c2 10463 if (*charfields++) {
51219358 10464 *wbuf = le16_to_cpu(wval);
27c868c2 10465 } else {
51219358 10466 *wbuf = wval;
27c868c2 10467 }
27c868c2 10468 }
51219358
MW		 10469 /* Read checksum word. */
10470 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
27c868c2
MW		 10471 wbuf++;
10472 charfields++;
10473
51219358
MW		 10474 /* Read rest of EEPROM not covered by the checksum. */
10475 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10476 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10477 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
27c868c2 10478 if (*charfields++) {
51219358 10479 *wbuf = le16_to_cpu(*wbuf);
27c868c2 10480 }
27c868c2 10481 }
51219358 10482 return chksum;
1da177e4
LT		 10483}
10484
1da177e4 10485/*
51219358
MW		 10486 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
10487 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
10488 * all of this is done.
1da177e4 10489 *
51219358 10490 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
1da177e4 10491 *
51219358
MW		 10492 * For a non-fatal error return a warning code. If there are no warnings
10493 * then 0 is returned.
1da177e4 10494 *
51219358 10495 * Note: Chip is stopped on entry.
1da177e4 10496 */
6f039790 10497static int AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
1da177e4 10498{
27c868c2 10499 AdvPortAddr iop_base;
51219358
MW		 10500 ushort warn_code;
10501 ADVEEP_3550_CONFIG eep_config;
1da177e4 10502
27c868c2 10503 iop_base = asc_dvc->iop_base;
1da177e4 10504
51219358 10505 warn_code = 0;
27c868c2
MW		 10506
10507 /*
51219358
MW		 10508 * Read the board's EEPROM configuration.
10509 *
10510 * Set default values if a bad checksum is found.
27c868c2 10511 */
51219358
MW		 10512 if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) {
10513 warn_code |= ASC_WARN_EEPROM_CHKSUM;
27c868c2 10514
51219358
MW		 10515 /*
10516 * Set EEPROM default values.
10517 */
10518 memcpy(&eep_config, &Default_3550_EEPROM_Config,
10519 sizeof(ADVEEP_3550_CONFIG));
27c868c2 10520
51219358
MW		 10521 /*
10522 * Assume the 6 byte board serial number that was read from
10523 * EEPROM is correct even if the EEPROM checksum failed.
10524 */
10525 eep_config.serial_number_word3 =
10526 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
27c868c2 10527
51219358
MW		 10528 eep_config.serial_number_word2 =
10529 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
27c868c2 10530
51219358
MW		 10531 eep_config.serial_number_word1 =
10532 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
27c868c2 10533
51219358
MW		 10534 AdvSet3550EEPConfig(iop_base, &eep_config);
10535 }
10536 /*
10537 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
10538 * EEPROM configuration that was read.
10539 *
10540 * This is the mapping of EEPROM fields to Adv Library fields.
10541 */
10542 asc_dvc->wdtr_able = eep_config.wdtr_able;
10543 asc_dvc->sdtr_able = eep_config.sdtr_able;
10544 asc_dvc->ultra_able = eep_config.ultra_able;
10545 asc_dvc->tagqng_able = eep_config.tagqng_able;
10546 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10547 asc_dvc->max_host_qng = eep_config.max_host_qng;
10548 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10549 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
10550 asc_dvc->start_motor = eep_config.start_motor;
10551 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10552 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10553 asc_dvc->no_scam = eep_config.scam_tolerant;
10554 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
10555 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
10556 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
27c868c2 10557
27c868c2 10558 /*
51219358
MW		 10559 * Set the host maximum queuing (max. 253, min. 16) and the per device
10560 * maximum queuing (max. 63, min. 4).
27c868c2 10561 */
51219358
MW		 10562 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10563 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10564 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10565 /* If the value is zero, assume it is uninitialized. */
10566 if (eep_config.max_host_qng == 0) {
10567 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10568 } else {
10569 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10570 }
10571 }
10572
10573 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10574 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10575 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10576 /* If the value is zero, assume it is uninitialized. */
10577 if (eep_config.max_dvc_qng == 0) {
10578 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10579 } else {
10580 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10581 }
10582 }
27c868c2
MW		 10583
10584 /*
51219358
MW		 10585 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10586 * set 'max_dvc_qng' to 'max_host_qng'.
27c868c2 10587 */
51219358
MW		 10588 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10589 eep_config.max_dvc_qng = eep_config.max_host_qng;
10590 }
27c868c2
MW		 10591
10592 /*
51219358
MW		 10593 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
10594 * values based on possibly adjusted EEPROM values.
27c868c2 10595 */
51219358
MW		 10596 asc_dvc->max_host_qng = eep_config.max_host_qng;
10597 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
27c868c2
MW		 10598
10599 /*
51219358
MW		 10600 * If the EEPROM 'termination' field is set to automatic (0), then set
10601 * the ADV_DVC_CFG 'termination' field to automatic also.
10602 *
10603 * If the termination is specified with a non-zero 'termination'
10604 * value check that a legal value is set and set the ADV_DVC_CFG
10605 * 'termination' field appropriately.
27c868c2 10606 */
51219358
MW		 10607 if (eep_config.termination == 0) {
10608 asc_dvc->cfg->termination = 0; /* auto termination */
10609 } else {
10610 /* Enable manual control with low off / high off. */
10611 if (eep_config.termination == 1) {
10612 asc_dvc->cfg->termination = TERM_CTL_SEL;
27c868c2 10613
51219358
MW		 10614 /* Enable manual control with low off / high on. */
10615 } else if (eep_config.termination == 2) {
10616 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
10617
10618 /* Enable manual control with low on / high on. */
10619 } else if (eep_config.termination == 3) {
10620 asc_dvc->cfg->termination =
10621 TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
10622 } else {
27c868c2 10623 /*
51219358
MW		 10624 * The EEPROM 'termination' field contains a bad value. Use
10625 * automatic termination instead.
27c868c2 10626 */
51219358
MW		 10627 asc_dvc->cfg->termination = 0;
10628 warn_code |= ASC_WARN_EEPROM_TERMINATION;
27c868c2 10629 }
27c868c2 10630 }
1da177e4 10631
51219358 10632 return warn_code;
1da177e4
LT		 10633}
10634
10635/*
51219358
MW		 10636 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
10637 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
10638 * all of this is done.
1da177e4 10639 *
51219358
MW		 10640 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
10641 *
10642 * For a non-fatal error return a warning code. If there are no warnings
10643 * then 0 is returned.
10644 *
10645 * Note: Chip is stopped on entry.
1da177e4 10646 */
6f039790 10647static int AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
1da177e4 10648{
51219358
MW		 10649 AdvPortAddr iop_base;
10650 ushort warn_code;
10651 ADVEEP_38C0800_CONFIG eep_config;
10652 uchar tid, termination;
10653 ushort sdtr_speed = 0;
27c868c2 10654
51219358 10655 iop_base = asc_dvc->iop_base;
1da177e4 10656
51219358 10657 warn_code = 0;
27c868c2
MW		 10658
10659 /*
51219358
MW		 10660 * Read the board's EEPROM configuration.
10661 *
10662 * Set default values if a bad checksum is found.
27c868c2 10663 */
51219358
MW		 10664 if (AdvGet38C0800EEPConfig(iop_base, &eep_config) !=
10665 eep_config.check_sum) {
10666 warn_code |= ASC_WARN_EEPROM_CHKSUM;
27c868c2 10667
51219358
MW		 10668 /*
10669 * Set EEPROM default values.
10670 */
10671 memcpy(&eep_config, &Default_38C0800_EEPROM_Config,
10672 sizeof(ADVEEP_38C0800_CONFIG));
1da177e4 10673
51219358
MW		 10674 /*
10675 * Assume the 6 byte board serial number that was read from
10676 * EEPROM is correct even if the EEPROM checksum failed.
10677 */
10678 eep_config.serial_number_word3 =
10679 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
1da177e4 10680
51219358
MW		 10681 eep_config.serial_number_word2 =
10682 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
27c868c2 10683
51219358
MW		 10684 eep_config.serial_number_word1 =
10685 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
27c868c2 10686
51219358 10687 AdvSet38C0800EEPConfig(iop_base, &eep_config);
27c868c2 10688 }
27c868c2 10689 /*
51219358
MW		 10690 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
10691 * EEPROM configuration that was read.
10692 *
10693 * This is the mapping of EEPROM fields to Adv Library fields.
27c868c2 10694 */
51219358
MW		 10695 asc_dvc->wdtr_able = eep_config.wdtr_able;
10696 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
10697 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
10698 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
10699 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
10700 asc_dvc->tagqng_able = eep_config.tagqng_able;
10701 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10702 asc_dvc->max_host_qng = eep_config.max_host_qng;
10703 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10704 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
10705 asc_dvc->start_motor = eep_config.start_motor;
10706 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10707 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10708 asc_dvc->no_scam = eep_config.scam_tolerant;
10709 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
10710 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
10711 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
27c868c2
MW		 10712
10713 /*
51219358
MW		 10714 * For every Target ID if any of its 'sdtr_speed[1234]' bits
10715 * are set, then set an 'sdtr_able' bit for it.
27c868c2 10716 */
51219358
MW		 10717 asc_dvc->sdtr_able = 0;
10718 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
10719 if (tid == 0) {
10720 sdtr_speed = asc_dvc->sdtr_speed1;
10721 } else if (tid == 4) {
10722 sdtr_speed = asc_dvc->sdtr_speed2;
10723 } else if (tid == 8) {
10724 sdtr_speed = asc_dvc->sdtr_speed3;
10725 } else if (tid == 12) {
10726 sdtr_speed = asc_dvc->sdtr_speed4;
10727 }
10728 if (sdtr_speed & ADV_MAX_TID) {
10729 asc_dvc->sdtr_able |= (1 << tid);
10730 }
10731 sdtr_speed >>= 4;
10732 }
27c868c2
MW		 10733
10734 /*
51219358
MW		 10735 * Set the host maximum queuing (max. 253, min. 16) and the per device
10736 * maximum queuing (max. 63, min. 4).
27c868c2 10737 */
51219358
MW		 10738 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10739 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10740 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10741 /* If the value is zero, assume it is uninitialized. */
10742 if (eep_config.max_host_qng == 0) {
10743 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10744 } else {
10745 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10746 }
27c868c2 10747 }
1da177e4 10748
51219358
MW		 10749 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10750 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10751 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10752 /* If the value is zero, assume it is uninitialized. */
10753 if (eep_config.max_dvc_qng == 0) {
10754 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10755 } else {
10756 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10757 }
10758 }
10759
10760 /*
10761 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10762 * set 'max_dvc_qng' to 'max_host_qng'.
10763 */
10764 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10765 eep_config.max_dvc_qng = eep_config.max_host_qng;
27c868c2 10766 }
1da177e4 10767
27c868c2 10768 /*
51219358
MW		 10769 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
10770 * values based on possibly adjusted EEPROM values.
27c868c2 10771 */
51219358
MW		 10772 asc_dvc->max_host_qng = eep_config.max_host_qng;
10773 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
27c868c2
MW		 10774
10775 /*
51219358
MW		 10776 * If the EEPROM 'termination' field is set to automatic (0), then set
10777 * the ADV_DVC_CFG 'termination' field to automatic also.
10778 *
10779 * If the termination is specified with a non-zero 'termination'
10780 * value check that a legal value is set and set the ADV_DVC_CFG
10781 * 'termination' field appropriately.
27c868c2 10782 */
51219358
MW		 10783 if (eep_config.termination_se == 0) {
10784 termination = 0; /* auto termination for SE */
10785 } else {
10786 /* Enable manual control with low off / high off. */
10787 if (eep_config.termination_se == 1) {
10788 termination = 0;
10789
10790 /* Enable manual control with low off / high on. */
10791 } else if (eep_config.termination_se == 2) {
10792 termination = TERM_SE_HI;
10793
10794 /* Enable manual control with low on / high on. */
10795 } else if (eep_config.termination_se == 3) {
10796 termination = TERM_SE;
10797 } else {
10798 /*
10799 * The EEPROM 'termination_se' field contains a bad value.
10800 * Use automatic termination instead.
10801 */
10802 termination = 0;
10803 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10804 }
27c868c2 10805 }
51219358
MW		 10806
10807 if (eep_config.termination_lvd == 0) {
10808 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
10809 } else {
10810 /* Enable manual control with low off / high off. */
10811 if (eep_config.termination_lvd == 1) {
10812 asc_dvc->cfg->termination = termination;
10813
10814 /* Enable manual control with low off / high on. */
10815 } else if (eep_config.termination_lvd == 2) {
10816 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
10817
10818 /* Enable manual control with low on / high on. */
10819 } else if (eep_config.termination_lvd == 3) {
10820 asc_dvc->cfg->termination = termination | TERM_LVD;
10821 } else {
10822 /*
10823 * The EEPROM 'termination_lvd' field contains a bad value.
10824 * Use automatic termination instead.
10825 */
10826 asc_dvc->cfg->termination = termination;
10827 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10828 }
27c868c2 10829 }
1da177e4 10830
51219358 10831 return warn_code;
1da177e4
LT		 10832}
10833
10834/*
51219358
MW		 10835 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
10836 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
10837 * all of this is done.
1da177e4 10838 *
51219358 10839 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
1da177e4 10840 *
51219358
MW		 10841 * For a non-fatal error return a warning code. If there are no warnings
10842 * then 0 is returned.
1da177e4 10843 *
51219358 10844 * Note: Chip is stopped on entry.
1da177e4 10845 */
6f039790 10846static int AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
1da177e4 10847{
27c868c2 10848 AdvPortAddr iop_base;
51219358
MW		 10849 ushort warn_code;
10850 ADVEEP_38C1600_CONFIG eep_config;
10851 uchar tid, termination;
10852 ushort sdtr_speed = 0;
1da177e4 10853
27c868c2
MW		 10854 iop_base = asc_dvc->iop_base;
10855
51219358 10856 warn_code = 0;
27c868c2 10857
51219358
MW		 10858 /*
10859 * Read the board's EEPROM configuration.
10860 *
10861 * Set default values if a bad checksum is found.
10862 */
10863 if (AdvGet38C1600EEPConfig(iop_base, &eep_config) !=
10864 eep_config.check_sum) {
10865 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
10866 warn_code |= ASC_WARN_EEPROM_CHKSUM;
10867
10868 /*
10869 * Set EEPROM default values.
10870 */
10871 memcpy(&eep_config, &Default_38C1600_EEPROM_Config,
10872 sizeof(ADVEEP_38C1600_CONFIG));
10873
10874 if (PCI_FUNC(pdev->devfn) != 0) {
10875 u8 ints;
10876 /*
10877 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60
10878 * and old Mac system booting problem. The Expansion
10879 * ROM must be disabled in Function 1 for these systems
10880 */
10881 eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE;
10882 /*
10883 * Clear the INTAB (bit 11) if the GPIO 0 input
10884 * indicates the Function 1 interrupt line is wired
10885 * to INTB.
10886 *
10887 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
10888 * 1 - Function 1 interrupt line wired to INT A.
10889 * 0 - Function 1 interrupt line wired to INT B.
10890 *
10891 * Note: Function 0 is always wired to INTA.
10892 * Put all 5 GPIO bits in input mode and then read
10893 * their input values.
10894 */
10895 AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
10896 ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA);
10897 if ((ints & 0x01) == 0)
10898 eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB;
10899 }
10900
10901 /*
10902 * Assume the 6 byte board serial number that was read from
10903 * EEPROM is correct even if the EEPROM checksum failed.
10904 */
10905 eep_config.serial_number_word3 =
10906 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
10907 eep_config.serial_number_word2 =
10908 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
10909 eep_config.serial_number_word1 =
10910 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
10911
10912 AdvSet38C1600EEPConfig(iop_base, &eep_config);
27c868c2
MW		 10913 }
10914
10915 /*
51219358
MW		 10916 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
10917 * EEPROM configuration that was read.
10918 *
10919 * This is the mapping of EEPROM fields to Adv Library fields.
27c868c2 10920 */
51219358
MW		 10921 asc_dvc->wdtr_able = eep_config.wdtr_able;
10922 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
10923 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
10924 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
10925 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
10926 asc_dvc->ppr_able = 0;
10927 asc_dvc->tagqng_able = eep_config.tagqng_able;
10928 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10929 asc_dvc->max_host_qng = eep_config.max_host_qng;
10930 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10931 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
10932 asc_dvc->start_motor = eep_config.start_motor;
10933 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10934 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10935 asc_dvc->no_scam = eep_config.scam_tolerant;
27c868c2 10936
51219358
MW		 10937 /*
10938 * For every Target ID if any of its 'sdtr_speed[1234]' bits
10939 * are set, then set an 'sdtr_able' bit for it.
10940 */
10941 asc_dvc->sdtr_able = 0;
10942 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
10943 if (tid == 0) {
10944 sdtr_speed = asc_dvc->sdtr_speed1;
10945 } else if (tid == 4) {
10946 sdtr_speed = asc_dvc->sdtr_speed2;
10947 } else if (tid == 8) {
10948 sdtr_speed = asc_dvc->sdtr_speed3;
10949 } else if (tid == 12) {
10950 sdtr_speed = asc_dvc->sdtr_speed4;
10951 }
10952 if (sdtr_speed & ASC_MAX_TID) {
10953 asc_dvc->sdtr_able |= (1 << tid);
10954 }
10955 sdtr_speed >>= 4;
10956 }
27c868c2 10957
51219358
MW		 10958 /*
10959 * Set the host maximum queuing (max. 253, min. 16) and the per device
10960 * maximum queuing (max. 63, min. 4).
10961 */
10962 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10963 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10964 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10965 /* If the value is zero, assume it is uninitialized. */
10966 if (eep_config.max_host_qng == 0) {
10967 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10968 } else {
10969 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
27c868c2 10970 }
51219358 10971 }
27c868c2 10972
51219358
MW		 10973 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10974 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10975 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10976 /* If the value is zero, assume it is uninitialized. */
10977 if (eep_config.max_dvc_qng == 0) {
10978 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10979 } else {
10980 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10981 }
10982 }
10983
10984 /*
10985 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10986 * set 'max_dvc_qng' to 'max_host_qng'.
10987 */
10988 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10989 eep_config.max_dvc_qng = eep_config.max_host_qng;
27c868c2
MW		 10990 }
10991
10992 /*
51219358
MW		 10993 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
10994 * values based on possibly adjusted EEPROM values.
10995 */
10996 asc_dvc->max_host_qng = eep_config.max_host_qng;
10997 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10998
10999 /*
11000 * If the EEPROM 'termination' field is set to automatic (0), then set
11001 * the ASC_DVC_CFG 'termination' field to automatic also.
11002 *
11003 * If the termination is specified with a non-zero 'termination'
11004 * value check that a legal value is set and set the ASC_DVC_CFG
11005 * 'termination' field appropriately.
27c868c2 11006 */
51219358
MW		 11007 if (eep_config.termination_se == 0) {
11008 termination = 0; /* auto termination for SE */
11009 } else {
11010 /* Enable manual control with low off / high off. */
11011 if (eep_config.termination_se == 1) {
11012 termination = 0;
27c868c2 11013
51219358
MW		 11014 /* Enable manual control with low off / high on. */
11015 } else if (eep_config.termination_se == 2) {
11016 termination = TERM_SE_HI;
27c868c2 11017
51219358
MW		 11018 /* Enable manual control with low on / high on. */
11019 } else if (eep_config.termination_se == 3) {
11020 termination = TERM_SE;
11021 } else {
11022 /*
11023 * The EEPROM 'termination_se' field contains a bad value.
11024 * Use automatic termination instead.
11025 */
11026 termination = 0;
11027 warn_code |= ASC_WARN_EEPROM_TERMINATION;
11028 }
11029 }
27c868c2 11030
51219358
MW		 11031 if (eep_config.termination_lvd == 0) {
11032 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
11033 } else {
11034 /* Enable manual control with low off / high off. */
11035 if (eep_config.termination_lvd == 1) {
11036 asc_dvc->cfg->termination = termination;
27c868c2 11037
51219358
MW		 11038 /* Enable manual control with low off / high on. */
11039 } else if (eep_config.termination_lvd == 2) {
11040 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
27c868c2 11041
51219358
MW		 11042 /* Enable manual control with low on / high on. */
11043 } else if (eep_config.termination_lvd == 3) {
11044 asc_dvc->cfg->termination = termination | TERM_LVD;
11045 } else {
11046 /*
11047 * The EEPROM 'termination_lvd' field contains a bad value.
11048 * Use automatic termination instead.
11049 */
11050 asc_dvc->cfg->termination = termination;
11051 warn_code |= ASC_WARN_EEPROM_TERMINATION;
11052 }
27c868c2 11053 }
51219358
MW		 11054
11055 return warn_code;
1da177e4
LT		 11056}
11057
11058/*
51219358 11059 * Initialize the ADV_DVC_VAR structure.
1da177e4 11060 *
51219358 11061 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
1da177e4 11062 *
51219358
MW		 11063 * For a non-fatal error return a warning code. If there are no warnings
11064 * then 0 is returned.
1da177e4 11065 */
6f039790 11066static int AdvInitGetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
1da177e4 11067{
9d0e96eb
MW		 11068 struct asc_board *board = shost_priv(shost);
11069 ADV_DVC_VAR *asc_dvc = &board->dvc_var.adv_dvc_var;
51219358
MW		 11070 unsigned short warn_code = 0;
11071 AdvPortAddr iop_base = asc_dvc->iop_base;
11072 u16 cmd;
11073 int status;
27c868c2 11074
51219358 11075 asc_dvc->err_code = 0;
27c868c2
MW		 11076
11077 /*
51219358
MW		 11078 * Save the state of the PCI Configuration Command Register
11079 * "Parity Error Response Control" Bit. If the bit is clear (0),
11080 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
11081 * DMA parity errors.
27c868c2 11082 */
51219358
MW		 11083 asc_dvc->cfg->control_flag = 0;
11084 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
11085 if ((cmd & PCI_COMMAND_PARITY) == 0)
11086 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
27c868c2 11087
51219358
MW		 11088 asc_dvc->cfg->chip_version =
11089 AdvGetChipVersion(iop_base, asc_dvc->bus_type);
11090
b352f923 11091 ASC_DBG(1, "iopb_chip_id_1: 0x%x 0x%x\n",
51219358
MW		 11092 (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
11093 (ushort)ADV_CHIP_ID_BYTE);
11094
b352f923 11095 ASC_DBG(1, "iopw_chip_id_0: 0x%x 0x%x\n",
51219358
MW		 11096 (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
11097 (ushort)ADV_CHIP_ID_WORD);
27c868c2
MW		 11098
11099 /*
51219358 11100 * Reset the chip to start and allow register writes.
27c868c2 11101 */
51219358
MW		 11102 if (AdvFindSignature(iop_base) == 0) {
11103 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
11104 return ADV_ERROR;
11105 } else {
27c868c2 11106 /*
51219358 11107 * The caller must set 'chip_type' to a valid setting.
27c868c2 11108 */
51219358
MW		 11109 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
11110 asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
11111 asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
11112 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
11113 return ADV_ERROR;
11114 }
1da177e4 11115
51219358
MW		 11116 /*
11117 * Reset Chip.
11118 */
11119 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
11120 ADV_CTRL_REG_CMD_RESET);
11121 mdelay(100);
11122 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
11123 ADV_CTRL_REG_CMD_WR_IO_REG);
11124
11125 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
11126 status = AdvInitFrom38C1600EEP(asc_dvc);
11127 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
11128 status = AdvInitFrom38C0800EEP(asc_dvc);
11129 } else {
11130 status = AdvInitFrom3550EEP(asc_dvc);
27c868c2 11131 }
51219358 11132 warn_code |= status;
27c868c2 11133 }
1da177e4 11134
9d0e96eb
MW		 11135 if (warn_code != 0)
11136 shost_printk(KERN_WARNING, shost, "warning: 0x%x\n", warn_code);
51219358 11137
9d0e96eb
MW		 11138 if (asc_dvc->err_code)
11139 shost_printk(KERN_ERR, shost, "error code 0x%x\n",
11140 asc_dvc->err_code);
51219358
MW		 11141
11142 return asc_dvc->err_code;
1da177e4 11143}
51219358
MW		 11144#endif
11145
11146static struct scsi_host_template advansys_template = {
11147 .proc_name = DRV_NAME,
11148#ifdef CONFIG_PROC_FS
b59fb6fd 11149 .show_info = advansys_show_info,
51219358
MW		 11150#endif
11151 .name = DRV_NAME,
11152 .info = advansys_info,
11153 .queuecommand = advansys_queuecommand,
eac0b0c7 11154 .eh_host_reset_handler = advansys_reset,
51219358
MW		 11155 .bios_param = advansys_biosparam,
11156 .slave_configure = advansys_slave_configure,
11157 /*
11158 * Because the driver may control an ISA adapter 'unchecked_isa_dma'
11159 * must be set. The flag will be cleared in advansys_board_found
11160 * for non-ISA adapters.
11161 */
11162 .unchecked_isa_dma = 1,
11163 /*
11164 * All adapters controlled by this driver are capable of large
11165 * scatter-gather lists. According to the mid-level SCSI documentation
11166 * this obviates any performance gain provided by setting
11167 * 'use_clustering'. But empirically while CPU utilization is increased
11168 * by enabling clustering, I/O throughput increases as well.
11169 */
11170 .use_clustering = ENABLE_CLUSTERING,
9c17c62a 11171 .use_blk_tags = 1,
51219358 11172};
1da177e4 11173
6f039790 11174static int advansys_wide_init_chip(struct Scsi_Host *shost)
b2c16f58 11175{
9d0e96eb
MW		 11176 struct asc_board *board = shost_priv(shost);
11177 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
b2c16f58
MW		 11178 int req_cnt = 0;
11179 adv_req_t *reqp = NULL;
11180 int sg_cnt = 0;
11181 adv_sgblk_t *sgp;
11182 int warn_code, err_code;
11183
11184 /*
11185 * Allocate buffer carrier structures. The total size
11186 * is about 4 KB, so allocate all at once.
11187 */
98d41c29
MW		 11188 adv_dvc->carrier_buf = kmalloc(ADV_CARRIER_BUFSIZE, GFP_KERNEL);
11189 ASC_DBG(1, "carrier_buf 0x%p\n", adv_dvc->carrier_buf);
b2c16f58 11190
98d41c29 11191 if (!adv_dvc->carrier_buf)
b2c16f58
MW		 11192 goto kmalloc_failed;
11193
11194 /*
11195 * Allocate up to 'max_host_qng' request structures for the Wide
11196 * board. The total size is about 16 KB, so allocate all at once.
11197 * If the allocation fails decrement and try again.
11198 */
9d0e96eb 11199 for (req_cnt = adv_dvc->max_host_qng; req_cnt > 0; req_cnt--) {
9c17c62a 11200 reqp = kzalloc(sizeof(adv_req_t) * req_cnt, GFP_KERNEL);
b2c16f58 11201
b352f923 11202 ASC_DBG(1, "reqp 0x%p, req_cnt %d, bytes %lu\n", reqp, req_cnt,
b2c16f58
MW		 11203 (ulong)sizeof(adv_req_t) * req_cnt);
11204
11205 if (reqp)
11206 break;
11207 }
11208
11209 if (!reqp)
11210 goto kmalloc_failed;
11211
9c17c62a 11212 board->adv_reqp = reqp;
b2c16f58
MW		 11213
11214 /*
11215 * Allocate up to ADV_TOT_SG_BLOCK request structures for
11216 * the Wide board. Each structure is about 136 bytes.
11217 */
9d0e96eb 11218 board->adv_sgblkp = NULL;
b2c16f58
MW		 11219 for (sg_cnt = 0; sg_cnt < ADV_TOT_SG_BLOCK; sg_cnt++) {
11220 sgp = kmalloc(sizeof(adv_sgblk_t), GFP_KERNEL);
11221
11222 if (!sgp)
11223 break;
11224
9d0e96eb
MW		 11225 sgp->next_sgblkp = board->adv_sgblkp;
11226 board->adv_sgblkp = sgp;
b2c16f58
MW		 11227
11228 }
11229
9d511a4b
MW		 11230 ASC_DBG(1, "sg_cnt %d * %lu = %lu bytes\n", sg_cnt, sizeof(adv_sgblk_t),
11231 sizeof(adv_sgblk_t) * sg_cnt);
b2c16f58 11232
9d0e96eb 11233 if (!board->adv_sgblkp)
b2c16f58
MW		 11234 goto kmalloc_failed;
11235
b2c16f58
MW		 11236 /*
11237 * Point 'adv_reqp' to the request structures and
11238 * link them together.
11239 */
11240 req_cnt--;
11241 reqp[req_cnt].next_reqp = NULL;
11242 for (; req_cnt > 0; req_cnt--) {
11243 reqp[req_cnt - 1].next_reqp = &reqp[req_cnt];
11244 }
b2c16f58 11245
9d0e96eb 11246 if (adv_dvc->chip_type == ADV_CHIP_ASC3550) {
b352f923 11247 ASC_DBG(2, "AdvInitAsc3550Driver()\n");
9d0e96eb
MW		 11248 warn_code = AdvInitAsc3550Driver(adv_dvc);
11249 } else if (adv_dvc->chip_type == ADV_CHIP_ASC38C0800) {
b352f923 11250 ASC_DBG(2, "AdvInitAsc38C0800Driver()\n");
9d0e96eb 11251 warn_code = AdvInitAsc38C0800Driver(adv_dvc);
b2c16f58 11252 } else {
b352f923 11253 ASC_DBG(2, "AdvInitAsc38C1600Driver()\n");
9d0e96eb 11254 warn_code = AdvInitAsc38C1600Driver(adv_dvc);
b2c16f58 11255 }
9d0e96eb 11256 err_code = adv_dvc->err_code;
b2c16f58
MW		 11257
11258 if (warn_code || err_code) {
9d0e96eb
MW		 11259 shost_printk(KERN_WARNING, shost, "error: warn 0x%x, error "
11260 "0x%x\n", warn_code, err_code);
b2c16f58
MW		 11261 }
11262
11263 goto exit;
11264
11265 kmalloc_failed:
9d0e96eb 11266 shost_printk(KERN_ERR, shost, "error: kmalloc() failed\n");
b2c16f58
MW		 11267 err_code = ADV_ERROR;
11268 exit:
11269 return err_code;
11270}
11271
98d41c29 11272static void advansys_wide_free_mem(struct asc_board *board)
b2c16f58 11273{
98d41c29
MW		 11274 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
11275 kfree(adv_dvc->carrier_buf);
11276 adv_dvc->carrier_buf = NULL;
9c17c62a
HR		 11277 kfree(board->adv_reqp);
11278 board->adv_reqp = NULL;
98d41c29
MW		 11279 while (board->adv_sgblkp) {
11280 adv_sgblk_t *sgp = board->adv_sgblkp;
11281 board->adv_sgblkp = sgp->next_sgblkp;
b2c16f58
MW		 11282 kfree(sgp);
11283 }
11284}
11285
6f039790
GKH		 11286static int advansys_board_found(struct Scsi_Host *shost, unsigned int iop,
11287 int bus_type)
27c868c2 11288{
d361db48 11289 struct pci_dev *pdev;
d2411495 11290 struct asc_board *boardp = shost_priv(shost);
27c868c2
MW		 11291 ASC_DVC_VAR *asc_dvc_varp = NULL;
11292 ADV_DVC_VAR *adv_dvc_varp = NULL;
d361db48 11293 int share_irq, warn_code, ret;
27c868c2 11294
d361db48 11295 pdev = (bus_type == ASC_IS_PCI) ? to_pci_dev(boardp->dev) : NULL;
27c868c2
MW		 11296
11297 if (ASC_NARROW_BOARD(boardp)) {
b352f923 11298 ASC_DBG(1, "narrow board\n");
27c868c2
MW		 11299 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
11300 asc_dvc_varp->bus_type = bus_type;
11301 asc_dvc_varp->drv_ptr = boardp;
11302 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
27c868c2 11303 asc_dvc_varp->iop_base = iop;
27c868c2 11304 } else {
57ba5fe9 11305#ifdef CONFIG_PCI
27c868c2
MW		 11306 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
11307 adv_dvc_varp->drv_ptr = boardp;
11308 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
27c868c2 11309 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) {
b352f923 11310 ASC_DBG(1, "wide board ASC-3550\n");
27c868c2
MW		 11311 adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
11312 } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) {
b352f923 11313 ASC_DBG(1, "wide board ASC-38C0800\n");
27c868c2
MW		 11314 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
11315 } else {
b352f923 11316 ASC_DBG(1, "wide board ASC-38C1600\n");
27c868c2
MW		 11317 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
11318 }
27c868c2 11319
57ba5fe9 11320 boardp->asc_n_io_port = pci_resource_len(pdev, 1);
25729a7f 11321 boardp->ioremap_addr = pci_ioremap_bar(pdev, 1);
57ba5fe9 11322 if (!boardp->ioremap_addr) {
9d511a4b 11323 shost_printk(KERN_ERR, shost, "ioremap(%lx, %d) "
9d0e96eb 11324 "returned NULL\n",
9d511a4b 11325 (long)pci_resource_start(pdev, 1),
9d0e96eb 11326 boardp->asc_n_io_port);
d361db48 11327 ret = -ENODEV;
b2c16f58 11328 goto err_shost;
27c868c2 11329 }
b352f923
MW		 11330 adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr;
11331 ASC_DBG(1, "iop_base: 0x%p\n", adv_dvc_varp->iop_base);
27c868c2
MW		 11332
11333 /*
11334 * Even though it isn't used to access wide boards, other
11335 * than for the debug line below, save I/O Port address so
11336 * that it can be reported.
11337 */
11338 boardp->ioport = iop;
11339
b352f923
MW		 11340 ASC_DBG(1, "iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n",
11341 (ushort)inp(iop + 1), (ushort)inpw(iop));
57ba5fe9 11342#endif /* CONFIG_PCI */
27c868c2
MW		 11343 }
11344
27c868c2 11345 if (ASC_NARROW_BOARD(boardp)) {
27c868c2
MW		 11346 /*
11347 * Set the board bus type and PCI IRQ before
11348 * calling AscInitGetConfig().
11349 */
11350 switch (asc_dvc_varp->bus_type) {
11351#ifdef CONFIG_ISA
11352 case ASC_IS_ISA:
11353 shost->unchecked_isa_dma = TRUE;
074c8fe4 11354 share_irq = 0;
27c868c2
MW		 11355 break;
11356 case ASC_IS_VL:
11357 shost->unchecked_isa_dma = FALSE;
074c8fe4 11358 share_irq = 0;
27c868c2
MW		 11359 break;
11360 case ASC_IS_EISA:
11361 shost->unchecked_isa_dma = FALSE;
074c8fe4 11362 share_irq = IRQF_SHARED;
27c868c2
MW		 11363 break;
11364#endif /* CONFIG_ISA */
11365#ifdef CONFIG_PCI
11366 case ASC_IS_PCI:
27c868c2 11367 shost->unchecked_isa_dma = FALSE;
074c8fe4 11368 share_irq = IRQF_SHARED;
27c868c2
MW		 11369 break;
11370#endif /* CONFIG_PCI */
11371 default:
9d0e96eb
MW		 11372 shost_printk(KERN_ERR, shost, "unknown adapter type: "
11373 "%d\n", asc_dvc_varp->bus_type);
27c868c2 11374 shost->unchecked_isa_dma = TRUE;
074c8fe4 11375 share_irq = 0;
27c868c2
MW		 11376 break;
11377 }
27c868c2 11378
27c868c2
MW		 11379 /*
11380 * NOTE: AscInitGetConfig() may change the board's
11381 * bus_type value. The bus_type value should no
11382 * longer be used. If the bus_type field must be
11383 * referenced only use the bit-wise AND operator "&".
11384 */
b352f923 11385 ASC_DBG(2, "AscInitGetConfig()\n");
9d0e96eb 11386 ret = AscInitGetConfig(shost) ? -ENODEV : 0;
27c868c2 11387 } else {
c2dce2fa
MW		 11388#ifdef CONFIG_PCI
11389 /*
11390 * For Wide boards set PCI information before calling
11391 * AdvInitGetConfig().
11392 */
c2dce2fa
MW		 11393 shost->unchecked_isa_dma = FALSE;
11394 share_irq = IRQF_SHARED;
b352f923 11395 ASC_DBG(2, "AdvInitGetConfig()\n");
394dbf3f 11396
9d0e96eb 11397 ret = AdvInitGetConfig(pdev, shost) ? -ENODEV : 0;
c2dce2fa 11398#endif /* CONFIG_PCI */
27c868c2
MW		 11399 }
11400
d361db48 11401 if (ret)
b59fb6fd 11402 goto err_unmap;
27c868c2
MW		 11403
11404 /*
11405 * Save the EEPROM configuration so that it can be displayed
11406 * from /proc/scsi/advansys/[0...].
11407 */
11408 if (ASC_NARROW_BOARD(boardp)) {
11409
11410 ASCEEP_CONFIG *ep;
11411
11412 /*
11413 * Set the adapter's target id bit in the 'init_tidmask' field.
11414 */
11415 boardp->init_tidmask |=
11416 ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
11417
11418 /*
11419 * Save EEPROM settings for the board.
11420 */
11421 ep = &boardp->eep_config.asc_eep;
11422
11423 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
11424 ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
11425 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
11426 ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
11427 ep->start_motor = asc_dvc_varp->start_motor;
11428 ep->cntl = asc_dvc_varp->dvc_cntl;
11429 ep->no_scam = asc_dvc_varp->no_scam;
11430 ep->max_total_qng = asc_dvc_varp->max_total_qng;
11431 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
11432 /* 'max_tag_qng' is set to the same value for every device. */
11433 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
11434 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
11435 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
11436 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
11437 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
11438 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
11439 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
11440
11441 /*
11442 * Modify board configuration.
11443 */
b352f923 11444 ASC_DBG(2, "AscInitSetConfig()\n");
9d0e96eb 11445 ret = AscInitSetConfig(pdev, shost) ? -ENODEV : 0;
d361db48 11446 if (ret)
b59fb6fd 11447 goto err_unmap;
27c868c2
MW		 11448 } else {
11449 ADVEEP_3550_CONFIG *ep_3550;
11450 ADVEEP_38C0800_CONFIG *ep_38C0800;
11451 ADVEEP_38C1600_CONFIG *ep_38C1600;
11452
11453 /*
11454 * Save Wide EEP Configuration Information.
11455 */
11456 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
11457 ep_3550 = &boardp->eep_config.adv_3550_eep;
11458
11459 ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
11460 ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
11461 ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11462 ep_3550->termination = adv_dvc_varp->cfg->termination;
11463 ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
11464 ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
11465 ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
11466 ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
11467 ep_3550->ultra_able = adv_dvc_varp->ultra_able;
11468 ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
11469 ep_3550->start_motor = adv_dvc_varp->start_motor;
11470 ep_3550->scsi_reset_delay =
11471 adv_dvc_varp->scsi_reset_wait;
11472 ep_3550->serial_number_word1 =
11473 adv_dvc_varp->cfg->serial1;
11474 ep_3550->serial_number_word2 =
11475 adv_dvc_varp->cfg->serial2;
11476 ep_3550->serial_number_word3 =
11477 adv_dvc_varp->cfg->serial3;
11478 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
11479 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
11480
11481 ep_38C0800->adapter_scsi_id =
11482 adv_dvc_varp->chip_scsi_id;
11483 ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
11484 ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11485 ep_38C0800->termination_lvd =
11486 adv_dvc_varp->cfg->termination;
11487 ep_38C0800->disc_enable =
11488 adv_dvc_varp->cfg->disc_enable;
11489 ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
11490 ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
11491 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
11492 ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
11493 ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
11494 ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
11495 ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
11496 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
11497 ep_38C0800->start_motor = adv_dvc_varp->start_motor;
11498 ep_38C0800->scsi_reset_delay =
11499 adv_dvc_varp->scsi_reset_wait;
11500 ep_38C0800->serial_number_word1 =
11501 adv_dvc_varp->cfg->serial1;
11502 ep_38C0800->serial_number_word2 =
11503 adv_dvc_varp->cfg->serial2;
11504 ep_38C0800->serial_number_word3 =
11505 adv_dvc_varp->cfg->serial3;
11506 } else {
11507 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
11508
11509 ep_38C1600->adapter_scsi_id =
11510 adv_dvc_varp->chip_scsi_id;
11511 ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
11512 ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11513 ep_38C1600->termination_lvd =
11514 adv_dvc_varp->cfg->termination;
11515 ep_38C1600->disc_enable =
11516 adv_dvc_varp->cfg->disc_enable;
11517 ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
11518 ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
11519 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
11520 ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
11521 ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
11522 ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
11523 ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
11524 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
11525 ep_38C1600->start_motor = adv_dvc_varp->start_motor;
11526 ep_38C1600->scsi_reset_delay =
11527 adv_dvc_varp->scsi_reset_wait;
11528 ep_38C1600->serial_number_word1 =
11529 adv_dvc_varp->cfg->serial1;
11530 ep_38C1600->serial_number_word2 =
11531 adv_dvc_varp->cfg->serial2;
11532 ep_38C1600->serial_number_word3 =
11533 adv_dvc_varp->cfg->serial3;
11534 }
11535
11536 /*
11537 * Set the adapter's target id bit in the 'init_tidmask' field.
11538 */
11539 boardp->init_tidmask |=
11540 ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
27c868c2
MW		 11541 }
11542
11543 /*
11544 * Channels are numbered beginning with 0. For AdvanSys one host
11545 * structure supports one channel. Multi-channel boards have a
11546 * separate host structure for each channel.
11547 */
11548 shost->max_channel = 0;
11549 if (ASC_NARROW_BOARD(boardp)) {
11550 shost->max_id = ASC_MAX_TID + 1;
11551 shost->max_lun = ASC_MAX_LUN + 1;
f05ec594 11552 shost->max_cmd_len = ASC_MAX_CDB_LEN;
27c868c2
MW		 11553
11554 shost->io_port = asc_dvc_varp->iop_base;
11555 boardp->asc_n_io_port = ASC_IOADR_GAP;
11556 shost->this_id = asc_dvc_varp->cfg->chip_scsi_id;
11557
11558 /* Set maximum number of queues the adapter can handle. */
11559 shost->can_queue = asc_dvc_varp->max_total_qng;
11560 } else {
11561 shost->max_id = ADV_MAX_TID + 1;
11562 shost->max_lun = ADV_MAX_LUN + 1;
f05ec594 11563 shost->max_cmd_len = ADV_MAX_CDB_LEN;
27c868c2
MW		 11564
11565 /*
11566 * Save the I/O Port address and length even though
11567 * I/O ports are not used to access Wide boards.
11568 * Instead the Wide boards are accessed with
11569 * PCI Memory Mapped I/O.
11570 */
11571 shost->io_port = iop;
27c868c2
MW		 11572
11573 shost->this_id = adv_dvc_varp->chip_scsi_id;
11574
11575 /* Set maximum number of queues the adapter can handle. */
11576 shost->can_queue = adv_dvc_varp->max_host_qng;
11577 }
9c17c62a
HR		 11578 ret = scsi_init_shared_tag_map(shost, shost->can_queue);
11579 if (ret) {
11580 shost_printk(KERN_ERR, shost, "init tag map failed\n");
11581 goto err_free_dma;
11582 }
27c868c2 11583
27c868c2
MW		 11584 /*
11585 * Following v1.3.89, 'cmd_per_lun' is no longer needed
11586 * and should be set to zero.
11587 *
11588 * But because of a bug introduced in v1.3.89 if the driver is
11589 * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level
11590 * SCSI function 'allocate_device' will panic. To allow the driver
11591 * to work as a module in these kernels set 'cmd_per_lun' to 1.
11592 *
11593 * Note: This is wrong. cmd_per_lun should be set to the depth
11594 * you want on untagged devices always.
11595 #ifdef MODULE
11596 */
11597 shost->cmd_per_lun = 1;
11598/* #else
11599 shost->cmd_per_lun = 0;
11600#endif */
11601
11602 /*
11603 * Set the maximum number of scatter-gather elements the
11604 * adapter can handle.
11605 */
11606 if (ASC_NARROW_BOARD(boardp)) {
11607 /*
11608 * Allow two commands with 'sg_tablesize' scatter-gather
11609 * elements to be executed simultaneously. This value is
11610 * the theoretical hardware limit. It may be decreased
11611 * below.
11612 */
11613 shost->sg_tablesize =
11614 (((asc_dvc_varp->max_total_qng - 2) / 2) *
11615 ASC_SG_LIST_PER_Q) + 1;
11616 } else {
11617 shost->sg_tablesize = ADV_MAX_SG_LIST;
11618 }
11619
11620 /*
11621 * The value of 'sg_tablesize' can not exceed the SCSI
11622 * mid-level driver definition of SG_ALL. SG_ALL also
11623 * must not be exceeded, because it is used to define the
11624 * size of the scatter-gather table in 'struct asc_sg_head'.
11625 */
11626 if (shost->sg_tablesize > SG_ALL) {
11627 shost->sg_tablesize = SG_ALL;
11628 }
11629
b352f923 11630 ASC_DBG(1, "sg_tablesize: %d\n", shost->sg_tablesize);
27c868c2
MW		 11631
11632 /* BIOS start address. */
11633 if (ASC_NARROW_BOARD(boardp)) {
b2c16f58
MW		 11634 shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base,
11635 asc_dvc_varp->bus_type);
27c868c2
MW		 11636 } else {
11637 /*
11638 * Fill-in BIOS board variables. The Wide BIOS saves
11639 * information in LRAM that is used by the driver.
11640 */
11641 AdvReadWordLram(adv_dvc_varp->iop_base,
11642 BIOS_SIGNATURE, boardp->bios_signature);
11643 AdvReadWordLram(adv_dvc_varp->iop_base,
11644 BIOS_VERSION, boardp->bios_version);
11645 AdvReadWordLram(adv_dvc_varp->iop_base,
11646 BIOS_CODESEG, boardp->bios_codeseg);
11647 AdvReadWordLram(adv_dvc_varp->iop_base,
11648 BIOS_CODELEN, boardp->bios_codelen);
11649
b352f923 11650 ASC_DBG(1, "bios_signature 0x%x, bios_version 0x%x\n",
27c868c2
MW		 11651 boardp->bios_signature, boardp->bios_version);
11652
b352f923 11653 ASC_DBG(1, "bios_codeseg 0x%x, bios_codelen 0x%x\n",
27c868c2
MW		 11654 boardp->bios_codeseg, boardp->bios_codelen);
11655
11656 /*
11657 * If the BIOS saved a valid signature, then fill in
11658 * the BIOS code segment base address.
11659 */
11660 if (boardp->bios_signature == 0x55AA) {
11661 /*
11662 * Convert x86 realmode code segment to a linear
11663 * address by shifting left 4.
11664 */
11665 shost->base = ((ulong)boardp->bios_codeseg << 4);
11666 } else {
11667 shost->base = 0;
11668 }
11669 }
11670
11671 /*
11672 * Register Board Resources - I/O Port, DMA, IRQ
11673 */
11674
27c868c2
MW		 11675 /* Register DMA Channel for Narrow boards. */
11676 shost->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */
11677#ifdef CONFIG_ISA
11678 if (ASC_NARROW_BOARD(boardp)) {
11679 /* Register DMA channel for ISA bus. */
11680 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
11681 shost->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
01fbfe0b 11682 ret = request_dma(shost->dma_channel, DRV_NAME);
b2c16f58 11683 if (ret) {
9d0e96eb
MW		 11684 shost_printk(KERN_ERR, shost, "request_dma() "
11685 "%d failed %d\n",
11686 shost->dma_channel, ret);
b59fb6fd 11687 goto err_unmap;
27c868c2
MW		 11688 }
11689 AscEnableIsaDma(shost->dma_channel);
11690 }
11691 }
11692#endif /* CONFIG_ISA */
11693
11694 /* Register IRQ Number. */
b352f923 11695 ASC_DBG(2, "request_irq(%d, %p)\n", boardp->irq, shost);
074c8fe4 11696
d361db48 11697 ret = request_irq(boardp->irq, advansys_interrupt, share_irq,
01fbfe0b 11698 DRV_NAME, shost);
074c8fe4
MW		 11699
11700 if (ret) {
27c868c2 11701 if (ret == -EBUSY) {
9d0e96eb
MW		 11702 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11703 "already in use\n", boardp->irq);
27c868c2 11704 } else if (ret == -EINVAL) {
9d0e96eb
MW		 11705 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11706 "not valid\n", boardp->irq);
27c868c2 11707 } else {
9d0e96eb
MW		 11708 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11709 "failed with %d\n", boardp->irq, ret);
27c868c2 11710 }
b2c16f58 11711 goto err_free_dma;
27c868c2
MW		 11712 }
11713
11714 /*
11715 * Initialize board RISC chip and enable interrupts.
11716 */
11717 if (ASC_NARROW_BOARD(boardp)) {
b352f923 11718 ASC_DBG(2, "AscInitAsc1000Driver()\n");
7d5d408c
FT		 11719
11720 asc_dvc_varp->overrun_buf = kzalloc(ASC_OVERRUN_BSIZE, GFP_KERNEL);
11721 if (!asc_dvc_varp->overrun_buf) {
11722 ret = -ENOMEM;
9a908c1a 11723 goto err_free_irq;
7d5d408c 11724 }
27c868c2 11725 warn_code = AscInitAsc1000Driver(asc_dvc_varp);
27c868c2 11726
d361db48 11727 if (warn_code || asc_dvc_varp->err_code) {
9d0e96eb
MW		 11728 shost_printk(KERN_ERR, shost, "error: init_state 0x%x, "
11729 "warn 0x%x, error 0x%x\n",
11730 asc_dvc_varp->init_state, warn_code,
11731 asc_dvc_varp->err_code);
9a908c1a 11732 if (!asc_dvc_varp->overrun_dma) {
d361db48 11733 ret = -ENODEV;
9a908c1a 11734 goto err_free_mem;
7d5d408c 11735 }
27c868c2
MW		 11736 }
11737 } else {
9a908c1a 11738 if (advansys_wide_init_chip(shost)) {
d361db48 11739 ret = -ENODEV;
9a908c1a
HRK		 11740 goto err_free_mem;
11741 }
27c868c2
MW		 11742 }
11743
27c868c2
MW		 11744 ASC_DBG_PRT_SCSI_HOST(2, shost);
11745
d361db48 11746 ret = scsi_add_host(shost, boardp->dev);
8dfb5379 11747 if (ret)
9a908c1a 11748 goto err_free_mem;
8dfb5379
MW		 11749
11750 scsi_scan_host(shost);
d361db48 11751 return 0;
b2c16f58 11752
9a908c1a
HRK		 11753 err_free_mem:
11754 if (ASC_NARROW_BOARD(boardp)) {
11755 if (asc_dvc_varp->overrun_dma)
11756 dma_unmap_single(boardp->dev, asc_dvc_varp->overrun_dma,
11757 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
11758 kfree(asc_dvc_varp->overrun_buf);
11759 } else
11760 advansys_wide_free_mem(boardp);
11761 err_free_irq:
d361db48 11762 free_irq(boardp->irq, shost);
b2c16f58 11763 err_free_dma:
30037818 11764#ifdef CONFIG_ISA
b2c16f58
MW		 11765 if (shost->dma_channel != NO_ISA_DMA)
11766 free_dma(shost->dma_channel);
30037818 11767#endif
b2c16f58
MW		 11768 err_unmap:
11769 if (boardp->ioremap_addr)
11770 iounmap(boardp->ioremap_addr);
11771 err_shost:
d361db48 11772 return ret;
27c868c2
MW		 11773}
11774
27c868c2
MW		 11775/*
11776 * advansys_release()
11777 *
11778 * Release resources allocated for a single AdvanSys adapter.
11779 */
11780static int advansys_release(struct Scsi_Host *shost)
11781{
d10fb2c7 11782 struct asc_board *board = shost_priv(shost);
b352f923 11783 ASC_DBG(1, "begin\n");
8dfb5379 11784 scsi_remove_host(shost);
d10fb2c7 11785 free_irq(board->irq, shost);
30037818 11786#ifdef CONFIG_ISA
27c868c2 11787 if (shost->dma_channel != NO_ISA_DMA) {
b352f923 11788 ASC_DBG(1, "free_dma()\n");
27c868c2
MW		 11789 free_dma(shost->dma_channel);
11790 }
30037818 11791#endif
d10fb2c7
MW		 11792 if (ASC_NARROW_BOARD(board)) {
11793 dma_unmap_single(board->dev,
11794 board->dvc_var.asc_dvc_var.overrun_dma,
11795 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
7d5d408c 11796 kfree(board->dvc_var.asc_dvc_var.overrun_buf);
d10fb2c7
MW		 11797 } else {
11798 iounmap(board->ioremap_addr);
11799 advansys_wide_free_mem(board);
27c868c2 11800 }
8dfb5379 11801 scsi_host_put(shost);
b352f923 11802 ASC_DBG(1, "end\n");
27c868c2
MW		 11803 return 0;
11804}
11805
95c9f162
MW		 11806#define ASC_IOADR_TABLE_MAX_IX 11
11807
747d016e 11808static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] = {
c304ec94
MW		 11809 0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190,
11810 0x0210, 0x0230, 0x0250, 0x0330
11811};
11812
d361db48
MW		 11813/*
11814 * The ISA IRQ number is found in bits 2 and 3 of the CfgLsw. It decodes as:
11815 * 00: 10
11816 * 01: 11
11817 * 10: 12
11818 * 11: 15
11819 */
6f039790 11820static unsigned int advansys_isa_irq_no(PortAddr iop_base)
d361db48
MW		 11821{
11822 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
11823 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x03) + 10;
11824 if (chip_irq == 13)
11825 chip_irq = 15;
11826 return chip_irq;
11827}
11828
6f039790 11829static int advansys_isa_probe(struct device *dev, unsigned int id)
c304ec94 11830{
d361db48 11831 int err = -ENODEV;
c304ec94
MW		 11832 PortAddr iop_base = _asc_def_iop_base[id];
11833 struct Scsi_Host *shost;
d361db48 11834 struct asc_board *board;
c304ec94 11835
01fbfe0b 11836 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
b352f923 11837 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
c304ec94
MW		 11838 return -ENODEV;
11839 }
b352f923 11840 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
c304ec94 11841 if (!AscFindSignature(iop_base))
d361db48 11842 goto release_region;
c304ec94 11843 if (!(AscGetChipVersion(iop_base, ASC_IS_ISA) & ASC_CHIP_VER_ISA_BIT))
d361db48 11844 goto release_region;
c304ec94 11845
d361db48
MW		 11846 err = -ENOMEM;
11847 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
c304ec94 11848 if (!shost)
d361db48
MW		 11849 goto release_region;
11850
d2411495 11851 board = shost_priv(shost);
d361db48
MW		 11852 board->irq = advansys_isa_irq_no(iop_base);
11853 board->dev = dev;
9c17c62a 11854 board->shost = shost;
d361db48
MW		 11855
11856 err = advansys_board_found(shost, iop_base, ASC_IS_ISA);
11857 if (err)
11858 goto free_host;
c304ec94
MW		 11859
11860 dev_set_drvdata(dev, shost);
11861 return 0;
11862
d361db48
MW		 11863 free_host:
11864 scsi_host_put(shost);
11865 release_region:
71f36115 11866 release_region(iop_base, ASC_IOADR_GAP);
d361db48 11867 return err;
c304ec94
MW		 11868}
11869
6f039790 11870static int advansys_isa_remove(struct device *dev, unsigned int id)
c304ec94 11871{
71f36115 11872 int ioport = _asc_def_iop_base[id];
c304ec94 11873 advansys_release(dev_get_drvdata(dev));
71f36115 11874 release_region(ioport, ASC_IOADR_GAP);
c304ec94
MW		 11875 return 0;
11876}
11877
11878static struct isa_driver advansys_isa_driver = {
11879 .probe = advansys_isa_probe,
6f039790 11880 .remove = advansys_isa_remove,
c304ec94
MW		 11881 .driver = {
11882 .owner = THIS_MODULE,
01fbfe0b 11883 .name = DRV_NAME,
c304ec94
MW		 11884 },
11885};
11886
d361db48
MW		 11887/*
11888 * The VLB IRQ number is found in bits 2 to 4 of the CfgLsw. It decodes as:
11889 * 000: invalid
11890 * 001: 10
11891 * 010: 11
11892 * 011: 12
11893 * 100: invalid
11894 * 101: 14
11895 * 110: 15
11896 * 111: invalid
11897 */
6f039790 11898static unsigned int advansys_vlb_irq_no(PortAddr iop_base)
d361db48
MW		 11899{
11900 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
11901 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x07) + 9;
11902 if ((chip_irq < 10) || (chip_irq == 13) || (chip_irq > 15))
11903 return 0;
11904 return chip_irq;
11905}
11906
6f039790 11907static int advansys_vlb_probe(struct device *dev, unsigned int id)
c304ec94 11908{
d361db48 11909 int err = -ENODEV;
c304ec94
MW		 11910 PortAddr iop_base = _asc_def_iop_base[id];
11911 struct Scsi_Host *shost;
d361db48 11912 struct asc_board *board;
c304ec94 11913
01fbfe0b 11914 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
b352f923 11915 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
c304ec94
MW		 11916 return -ENODEV;
11917 }
b352f923 11918 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
c304ec94 11919 if (!AscFindSignature(iop_base))
d361db48 11920 goto release_region;
c304ec94
MW		 11921 /*
11922 * I don't think this condition can actually happen, but the old
11923 * driver did it, and the chances of finding a VLB setup in 2007
11924 * to do testing with is slight to none.
11925 */
11926 if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL)
d361db48 11927 goto release_region;
c304ec94 11928
d361db48
MW		 11929 err = -ENOMEM;
11930 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
c304ec94 11931 if (!shost)
d361db48
MW		 11932 goto release_region;
11933
d2411495 11934 board = shost_priv(shost);
d361db48
MW		 11935 board->irq = advansys_vlb_irq_no(iop_base);
11936 board->dev = dev;
9c17c62a 11937 board->shost = shost;
d361db48
MW		 11938
11939 err = advansys_board_found(shost, iop_base, ASC_IS_VL);
11940 if (err)
11941 goto free_host;
c304ec94
MW		 11942
11943 dev_set_drvdata(dev, shost);
11944 return 0;
11945
d361db48
MW		 11946 free_host:
11947 scsi_host_put(shost);
11948 release_region:
71f36115 11949 release_region(iop_base, ASC_IOADR_GAP);
c304ec94
MW		 11950 return -ENODEV;
11951}
11952
11953static struct isa_driver advansys_vlb_driver = {
11954 .probe = advansys_vlb_probe,
6f039790 11955 .remove = advansys_isa_remove,
c304ec94
MW		 11956 .driver = {
11957 .owner = THIS_MODULE,
b8e5152b 11958 .name = "advansys_vlb",
c304ec94
MW		 11959 },
11960};
11961
6f039790 11962static struct eisa_device_id advansys_eisa_table[] = {
b09e05a7
MW		 11963 { "ABP7401" },
11964 { "ABP7501" },
11965 { "" }
11966};
11967
11968MODULE_DEVICE_TABLE(eisa, advansys_eisa_table);
11969
11970/*
11971 * EISA is a little more tricky than PCI; each EISA device may have two
11972 * channels, and this driver is written to make each channel its own Scsi_Host
11973 */
11974struct eisa_scsi_data {
11975 struct Scsi_Host *host[2];
11976};
11977
d361db48
MW		 11978/*
11979 * The EISA IRQ number is found in bits 8 to 10 of the CfgLsw. It decodes as:
11980 * 000: 10
11981 * 001: 11
11982 * 010: 12
11983 * 011: invalid
11984 * 100: 14
11985 * 101: 15
11986 * 110: invalid
11987 * 111: invalid
11988 */
6f039790 11989static unsigned int advansys_eisa_irq_no(struct eisa_device *edev)
d361db48
MW		 11990{
11991 unsigned short cfg_lsw = inw(edev->base_addr + 0xc86);
11992 unsigned int chip_irq = ((cfg_lsw >> 8) & 0x07) + 10;
11993 if ((chip_irq == 13) || (chip_irq > 15))
11994 return 0;
11995 return chip_irq;
11996}
11997
6f039790 11998static int advansys_eisa_probe(struct device *dev)
b09e05a7 11999{
d361db48 12000 int i, ioport, irq = 0;
b09e05a7
MW		 12001 int err;
12002 struct eisa_device *edev = to_eisa_device(dev);
12003 struct eisa_scsi_data *data;
12004
12005 err = -ENOMEM;
12006 data = kzalloc(sizeof(*data), GFP_KERNEL);
12007 if (!data)
12008 goto fail;
12009 ioport = edev->base_addr + 0xc30;
12010
12011 err = -ENODEV;
12012 for (i = 0; i < 2; i++, ioport += 0x20) {
d361db48
MW		 12013 struct asc_board *board;
12014 struct Scsi_Host *shost;
01fbfe0b 12015 if (!request_region(ioport, ASC_IOADR_GAP, DRV_NAME)) {
71f36115
MW		 12016 printk(KERN_WARNING "Region %x-%x busy\n", ioport,
12017 ioport + ASC_IOADR_GAP - 1);
12018 continue;
12019 }
12020 if (!AscFindSignature(ioport)) {
12021 release_region(ioport, ASC_IOADR_GAP);
b09e05a7 12022 continue;
71f36115
MW		 12023 }
12024
b09e05a7
MW		 12025 /*
12026 * I don't know why we need to do this for EISA chips, but
12027 * not for any others. It looks to be equivalent to
12028 * AscGetChipCfgMsw, but I may have overlooked something,
12029 * so I'm not converting it until I get an EISA board to
12030 * test with.
12031 */
12032 inw(ioport + 4);
d361db48
MW		 12033
12034 if (!irq)
12035 irq = advansys_eisa_irq_no(edev);
12036
12037 err = -ENOMEM;
12038 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
12039 if (!shost)
12040 goto release_region;
12041
d2411495 12042 board = shost_priv(shost);
d361db48
MW		 12043 board->irq = irq;
12044 board->dev = dev;
9c17c62a 12045 board->shost = shost;
d361db48
MW		 12046
12047 err = advansys_board_found(shost, ioport, ASC_IS_EISA);
12048 if (!err) {
12049 data->host[i] = shost;
12050 continue;
71f36115 12051 }
b09e05a7 12052
d361db48
MW		 12053 scsi_host_put(shost);
12054 release_region:
12055 release_region(ioport, ASC_IOADR_GAP);
12056 break;
b09e05a7
MW		 12057 }
12058
d361db48
MW		 12059 if (err)
12060 goto free_data;
12061 dev_set_drvdata(dev, data);
12062 return 0;
12063
12064 free_data:
12065 kfree(data->host[0]);
12066 kfree(data->host[1]);
12067 kfree(data);
b09e05a7
MW		 12068 fail:
12069 return err;
12070}
12071
6f039790 12072static int advansys_eisa_remove(struct device *dev)
b09e05a7
MW		 12073{
12074 int i;
12075 struct eisa_scsi_data *data = dev_get_drvdata(dev);
12076
12077 for (i = 0; i < 2; i++) {
71f36115 12078 int ioport;
b09e05a7
MW		 12079 struct Scsi_Host *shost = data->host[i];
12080 if (!shost)
12081 continue;
71f36115 12082 ioport = shost->io_port;
b09e05a7 12083 advansys_release(shost);
71f36115 12084 release_region(ioport, ASC_IOADR_GAP);
b09e05a7
MW		 12085 }
12086
12087 kfree(data);
12088 return 0;
12089}
12090
12091static struct eisa_driver advansys_eisa_driver = {
12092 .id_table = advansys_eisa_table,
12093 .driver = {
01fbfe0b 12094 .name = DRV_NAME,
b09e05a7 12095 .probe = advansys_eisa_probe,
6f039790 12096 .remove = advansys_eisa_remove,
b09e05a7
MW		 12097 }
12098};
12099
2672ea86 12100/* PCI Devices supported by this driver */
6f039790 12101static struct pci_device_id advansys_pci_tbl[] = {
27c868c2
MW		 12102 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A,
12103 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12104 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940,
12105 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12106 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U,
12107 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12108 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW,
12109 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12110 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1,
12111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12112 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1,
12113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12114 {}
2672ea86 12115};
27c868c2 12116
2672ea86 12117MODULE_DEVICE_TABLE(pci, advansys_pci_tbl);
78e77d8b 12118
6f039790 12119static void advansys_set_latency(struct pci_dev *pdev)
9649af39
MW		 12120{
12121 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
12122 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
12123 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0);
12124 } else {
12125 u8 latency;
12126 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency);
12127 if (latency < 0x20)
12128 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
12129 }
12130}
12131
6f039790
GKH		 12132static int advansys_pci_probe(struct pci_dev *pdev,
12133 const struct pci_device_id *ent)
78e77d8b
MW		 12134{
12135 int err, ioport;
12136 struct Scsi_Host *shost;
d361db48 12137 struct asc_board *board;
78e77d8b
MW		 12138
12139 err = pci_enable_device(pdev);
12140 if (err)
12141 goto fail;
01fbfe0b 12142 err = pci_request_regions(pdev, DRV_NAME);
71f36115
MW		 12143 if (err)
12144 goto disable_device;
9649af39
MW		 12145 pci_set_master(pdev);
12146 advansys_set_latency(pdev);
78e77d8b 12147
d361db48 12148 err = -ENODEV;
78e77d8b 12149 if (pci_resource_len(pdev, 0) == 0)
d361db48 12150 goto release_region;
78e77d8b
MW		 12151
12152 ioport = pci_resource_start(pdev, 0);
78e77d8b 12153
d361db48
MW		 12154 err = -ENOMEM;
12155 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
78e77d8b 12156 if (!shost)
d361db48
MW		 12157 goto release_region;
12158
d2411495 12159 board = shost_priv(shost);
d361db48
MW		 12160 board->irq = pdev->irq;
12161 board->dev = &pdev->dev;
9c17c62a 12162 board->shost = shost;
d361db48
MW		 12163
12164 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW ||
12165 pdev->device == PCI_DEVICE_ID_38C0800_REV1 ||
12166 pdev->device == PCI_DEVICE_ID_38C1600_REV1) {
12167 board->flags |= ASC_IS_WIDE_BOARD;
12168 }
12169
12170 err = advansys_board_found(shost, ioport, ASC_IS_PCI);
12171 if (err)
12172 goto free_host;
78e77d8b
MW		 12173
12174 pci_set_drvdata(pdev, shost);
12175 return 0;
12176
d361db48
MW		 12177 free_host:
12178 scsi_host_put(shost);
12179 release_region:
71f36115
MW		 12180 pci_release_regions(pdev);
12181 disable_device:
78e77d8b
MW		 12182 pci_disable_device(pdev);
12183 fail:
12184 return err;
12185}
12186
6f039790 12187static void advansys_pci_remove(struct pci_dev *pdev)
78e77d8b
MW		 12188{
12189 advansys_release(pci_get_drvdata(pdev));
71f36115 12190 pci_release_regions(pdev);
78e77d8b
MW		 12191 pci_disable_device(pdev);
12192}
12193
12194static struct pci_driver advansys_pci_driver = {
01fbfe0b 12195 .name = DRV_NAME,
78e77d8b
MW		 12196 .id_table = advansys_pci_tbl,
12197 .probe = advansys_pci_probe,
6f039790 12198 .remove = advansys_pci_remove,
78e77d8b 12199};
8c6af9e1 12200
8dfb5379
MW		 12201static int __init advansys_init(void)
12202{
c304ec94 12203 int error;
b09e05a7 12204
c304ec94
MW		 12205 error = isa_register_driver(&advansys_isa_driver,
12206 ASC_IOADR_TABLE_MAX_IX);
78e77d8b
MW		 12207 if (error)
12208 goto fail;
8dfb5379 12209
c304ec94
MW		 12210 error = isa_register_driver(&advansys_vlb_driver,
12211 ASC_IOADR_TABLE_MAX_IX);
12212 if (error)
12213 goto unregister_isa;
12214
12215 error = eisa_driver_register(&advansys_eisa_driver);
12216 if (error)
12217 goto unregister_vlb;
12218
b09e05a7
MW		 12219 error = pci_register_driver(&advansys_pci_driver);
12220 if (error)
12221 goto unregister_eisa;
12222
8dfb5379 12223 return 0;
78e77d8b 12224
b09e05a7
MW		 12225 unregister_eisa:
12226 eisa_driver_unregister(&advansys_eisa_driver);
c304ec94
MW		 12227 unregister_vlb:
12228 isa_unregister_driver(&advansys_vlb_driver);
12229 unregister_isa:
12230 isa_unregister_driver(&advansys_isa_driver);
78e77d8b 12231 fail:
78e77d8b 12232 return error;
8dfb5379
MW		 12233}
12234
12235static void __exit advansys_exit(void)
12236{
78e77d8b 12237 pci_unregister_driver(&advansys_pci_driver);
b09e05a7 12238 eisa_driver_unregister(&advansys_eisa_driver);
c304ec94
MW		 12239 isa_unregister_driver(&advansys_vlb_driver);
12240 isa_unregister_driver(&advansys_isa_driver);
8dfb5379
MW		 12241}
12242
12243module_init(advansys_init);
12244module_exit(advansys_exit);
12245
8c6af9e1 12246MODULE_LICENSE("GPL");
989bb5f5
JSR		 12247MODULE_FIRMWARE("advansys/mcode.bin");
12248MODULE_FIRMWARE("advansys/3550.bin");
12249MODULE_FIRMWARE("advansys/38C0800.bin");
12250MODULE_FIRMWARE("advansys/38C1600.bin");
Linux kernel - Deliverables
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