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advansys: use host_reset
[deliverable/linux.git] / drivers / scsi / advansys.c
CommitLineData
01fbfe0b 1#define DRV_NAME "advansys"
8c6af9e1 2#define ASC_VERSION "3.4" /* AdvanSys Driver Version */
1da177e4
LT		 3
4/*
5 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
6 *
7 * Copyright (c) 1995-2000 Advanced System Products, Inc.
8 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
8c6af9e1 9 * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
1da177e4
LT		 10 * All Rights Reserved.
11 *
8c6af9e1
MW		 12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 */
17
18/*
1da177e4
LT		 19 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
20 * changed its name to ConnectCom Solutions, Inc.
8c6af9e1 21 * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
1da177e4
LT		 22 */
23
1da177e4 24#include <linux/module.h>
1da177e4
LT		 25#include <linux/string.h>
26#include <linux/kernel.h>
27#include <linux/types.h>
28#include <linux/ioport.h>
29#include <linux/interrupt.h>
30#include <linux/delay.h>
31#include <linux/slab.h>
32#include <linux/mm.h>
33#include <linux/proc_fs.h>
34#include <linux/init.h>
35#include <linux/blkdev.h>
c304ec94 36#include <linux/isa.h>
b09e05a7 37#include <linux/eisa.h>
8c6af9e1 38#include <linux/pci.h>
1da177e4
LT		 39#include <linux/spinlock.h>
40#include <linux/dma-mapping.h>
989bb5f5 41#include <linux/firmware.h>
1da177e4
LT		 42
43#include <asm/io.h>
1da177e4
LT		 44#include <asm/dma.h>
45
8c6af9e1
MW		 46#include <scsi/scsi_cmnd.h>
47#include <scsi/scsi_device.h>
48#include <scsi/scsi_tcq.h>
49#include <scsi/scsi.h>
50#include <scsi/scsi_host.h>
51
4bd6d7f3 52/* FIXME:
1da177e4 53 *
4bd6d7f3
MW		 54 * 1. Although all of the necessary command mapping places have the
55 * appropriate dma_map.. APIs, the driver still processes its internal
56 * queue using bus_to_virt() and virt_to_bus() which are illegal under
57 * the API. The entire queue processing structure will need to be
58 * altered to fix this.
59 * 2. Need to add memory mapping workaround. Test the memory mapping.
60 * If it doesn't work revert to I/O port access. Can a test be done
61 * safely?
62 * 3. Handle an interrupt not working. Keep an interrupt counter in
63 * the interrupt handler. In the timeout function if the interrupt
64 * has not occurred then print a message and run in polled mode.
65 * 4. Need to add support for target mode commands, cf. CAM XPT.
66 * 5. check DMA mapping functions for failure
349d2c44
MW		 67 * 6. Use scsi_transport_spi
68 * 7. advansys_info is not safe against multiple simultaneous callers
9d0e96eb 69 * 8. Add module_param to override ISA/VLB ioport array
1da177e4
LT		 70 */
71#warning this driver is still not properly converted to the DMA API
72
1da177e4
LT		 73/* Enable driver /proc statistics. */
74#define ADVANSYS_STATS
75
76/* Enable driver tracing. */
b352f923 77#undef ADVANSYS_DEBUG
1da177e4 78
1da177e4
LT		 79/*
80 * Portable Data Types
81 *
82 * Any instance where a 32-bit long or pointer type is assumed
83 * for precision or HW defined structures, the following define
84 * types must be used. In Linux the char, short, and int types
85 * are all consistent at 8, 16, and 32 bits respectively. Pointers
86 * and long types are 64 bits on Alpha and UltraSPARC.
87 */
27c868c2
MW		 88#define ASC_PADDR __u32 /* Physical/Bus address data type. */
89#define ASC_VADDR __u32 /* Virtual address data type. */
90#define ASC_DCNT __u32 /* Unsigned Data count type. */
91#define ASC_SDCNT __s32 /* Signed Data count type. */
1da177e4 92
1da177e4
LT		 93typedef unsigned char uchar;
94
95#ifndef TRUE
96#define TRUE (1)
97#endif
98#ifndef FALSE
99#define FALSE (0)
100#endif
101
1da177e4
LT		 102#define ERR (-1)
103#define UW_ERR (uint)(0xFFFF)
104#define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
1da177e4 105
2672ea86
DJ		 106#define PCI_VENDOR_ID_ASP 0x10cd
107#define PCI_DEVICE_ID_ASP_1200A 0x1100
108#define PCI_DEVICE_ID_ASP_ABP940 0x1200
109#define PCI_DEVICE_ID_ASP_ABP940U 0x1300
110#define PCI_DEVICE_ID_ASP_ABP940UW 0x2300
111#define PCI_DEVICE_ID_38C0800_REV1 0x2500
112#define PCI_DEVICE_ID_38C1600_REV1 0x2700
113
1da177e4
LT		 114/*
115 * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
116 * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
117 * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
118 * SRB structure.
119 */
120#define CC_VERY_LONG_SG_LIST 0
121#define ASC_SRB2SCSIQ(srb_ptr) (srb_ptr)
122
9d511a4b 123#define PortAddr unsigned int /* port address size */
1da177e4
LT		 124#define inp(port) inb(port)
125#define outp(port, byte) outb((byte), (port))
126
127#define inpw(port) inw(port)
128#define outpw(port, word) outw((word), (port))
129
130#define ASC_MAX_SG_QUEUE 7
131#define ASC_MAX_SG_LIST 255
132
133#define ASC_CS_TYPE unsigned short
134
135#define ASC_IS_ISA (0x0001)
136#define ASC_IS_ISAPNP (0x0081)
137#define ASC_IS_EISA (0x0002)
138#define ASC_IS_PCI (0x0004)
139#define ASC_IS_PCI_ULTRA (0x0104)
140#define ASC_IS_PCMCIA (0x0008)
141#define ASC_IS_MCA (0x0020)
142#define ASC_IS_VL (0x0040)
1da177e4
LT		 143#define ASC_IS_WIDESCSI_16 (0x0100)
144#define ASC_IS_WIDESCSI_32 (0x0200)
145#define ASC_IS_BIG_ENDIAN (0x8000)
95c9f162 146
1da177e4
LT		 147#define ASC_CHIP_MIN_VER_VL (0x01)
148#define ASC_CHIP_MAX_VER_VL (0x07)
149#define ASC_CHIP_MIN_VER_PCI (0x09)
150#define ASC_CHIP_MAX_VER_PCI (0x0F)
151#define ASC_CHIP_VER_PCI_BIT (0x08)
152#define ASC_CHIP_MIN_VER_ISA (0x11)
153#define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
154#define ASC_CHIP_MAX_VER_ISA (0x27)
155#define ASC_CHIP_VER_ISA_BIT (0x30)
156#define ASC_CHIP_VER_ISAPNP_BIT (0x20)
157#define ASC_CHIP_VER_ASYN_BUG (0x21)
158#define ASC_CHIP_VER_PCI 0x08
159#define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
160#define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
161#define ASC_CHIP_MIN_VER_EISA (0x41)
162#define ASC_CHIP_MAX_VER_EISA (0x47)
163#define ASC_CHIP_VER_EISA_BIT (0x40)
164#define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
1da177e4 165#define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
1da177e4 166#define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
1da177e4 167#define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL)
1da177e4
LT		 168
169#define ASC_SCSI_ID_BITS 3
170#define ASC_SCSI_TIX_TYPE uchar
171#define ASC_ALL_DEVICE_BIT_SET 0xFF
172#define ASC_SCSI_BIT_ID_TYPE uchar
173#define ASC_MAX_TID 7
174#define ASC_MAX_LUN 7
175#define ASC_SCSI_WIDTH_BIT_SET 0xFF
176#define ASC_MAX_SENSE_LEN 32
177#define ASC_MIN_SENSE_LEN 14
1da177e4
LT		 178#define ASC_SCSI_RESET_HOLD_TIME_US 60
179
f05ec594
MW		 180/*
181 * Narrow boards only support 12-byte commands, while wide boards
182 * extend to 16-byte commands.
183 */
184#define ASC_MAX_CDB_LEN 12
185#define ADV_MAX_CDB_LEN 16
186
1da177e4 187#define MS_SDTR_LEN 0x03
1da177e4 188#define MS_WDTR_LEN 0x02
1da177e4
LT		 189
190#define ASC_SG_LIST_PER_Q 7
191#define QS_FREE 0x00
192#define QS_READY 0x01
193#define QS_DISC1 0x02
194#define QS_DISC2 0x04
195#define QS_BUSY 0x08
196#define QS_ABORTED 0x40
197#define QS_DONE 0x80
198#define QC_NO_CALLBACK 0x01
199#define QC_SG_SWAP_QUEUE 0x02
200#define QC_SG_HEAD 0x04
201#define QC_DATA_IN 0x08
202#define QC_DATA_OUT 0x10
203#define QC_URGENT 0x20
204#define QC_MSG_OUT 0x40
205#define QC_REQ_SENSE 0x80
206#define QCSG_SG_XFER_LIST 0x02
207#define QCSG_SG_XFER_MORE 0x04
208#define QCSG_SG_XFER_END 0x08
209#define QD_IN_PROGRESS 0x00
210#define QD_NO_ERROR 0x01
211#define QD_ABORTED_BY_HOST 0x02
212#define QD_WITH_ERROR 0x04
213#define QD_INVALID_REQUEST 0x80
214#define QD_INVALID_HOST_NUM 0x81
215#define QD_INVALID_DEVICE 0x82
216#define QD_ERR_INTERNAL 0xFF
217#define QHSTA_NO_ERROR 0x00
218#define QHSTA_M_SEL_TIMEOUT 0x11
219#define QHSTA_M_DATA_OVER_RUN 0x12
220#define QHSTA_M_DATA_UNDER_RUN 0x12
221#define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
222#define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
223#define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
224#define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
225#define QHSTA_D_HOST_ABORT_FAILED 0x23
226#define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
227#define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
228#define QHSTA_D_ASPI_NO_BUF_POOL 0x26
229#define QHSTA_M_WTM_TIMEOUT 0x41
230#define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
231#define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
232#define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
233#define QHSTA_M_TARGET_STATUS_BUSY 0x45
234#define QHSTA_M_BAD_TAG_CODE 0x46
235#define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
236#define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
237#define QHSTA_D_LRAM_CMP_ERROR 0x81
238#define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
239#define ASC_FLAG_SCSIQ_REQ 0x01
240#define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
241#define ASC_FLAG_BIOS_ASYNC_IO 0x04
242#define ASC_FLAG_SRB_LINEAR_ADDR 0x08
243#define ASC_FLAG_WIN16 0x10
244#define ASC_FLAG_WIN32 0x20
245#define ASC_FLAG_ISA_OVER_16MB 0x40
246#define ASC_FLAG_DOS_VM_CALLBACK 0x80
247#define ASC_TAG_FLAG_EXTRA_BYTES 0x10
248#define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
249#define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
250#define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
251#define ASC_SCSIQ_CPY_BEG 4
252#define ASC_SCSIQ_SGHD_CPY_BEG 2
253#define ASC_SCSIQ_B_FWD 0
254#define ASC_SCSIQ_B_BWD 1
255#define ASC_SCSIQ_B_STATUS 2
256#define ASC_SCSIQ_B_QNO 3
257#define ASC_SCSIQ_B_CNTL 4
258#define ASC_SCSIQ_B_SG_QUEUE_CNT 5
259#define ASC_SCSIQ_D_DATA_ADDR 8
260#define ASC_SCSIQ_D_DATA_CNT 12
261#define ASC_SCSIQ_B_SENSE_LEN 20
262#define ASC_SCSIQ_DONE_INFO_BEG 22
263#define ASC_SCSIQ_D_SRBPTR 22
264#define ASC_SCSIQ_B_TARGET_IX 26
265#define ASC_SCSIQ_B_CDB_LEN 28
266#define ASC_SCSIQ_B_TAG_CODE 29
267#define ASC_SCSIQ_W_VM_ID 30
268#define ASC_SCSIQ_DONE_STATUS 32
269#define ASC_SCSIQ_HOST_STATUS 33
270#define ASC_SCSIQ_SCSI_STATUS 34
271#define ASC_SCSIQ_CDB_BEG 36
272#define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
273#define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
274#define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
275#define ASC_SCSIQ_B_SG_WK_QP 49
276#define ASC_SCSIQ_B_SG_WK_IX 50
277#define ASC_SCSIQ_W_ALT_DC1 52
278#define ASC_SCSIQ_B_LIST_CNT 6
279#define ASC_SCSIQ_B_CUR_LIST_CNT 7
280#define ASC_SGQ_B_SG_CNTL 4
281#define ASC_SGQ_B_SG_HEAD_QP 5
282#define ASC_SGQ_B_SG_LIST_CNT 6
283#define ASC_SGQ_B_SG_CUR_LIST_CNT 7
284#define ASC_SGQ_LIST_BEG 8
285#define ASC_DEF_SCSI1_QNG 4
286#define ASC_MAX_SCSI1_QNG 4
287#define ASC_DEF_SCSI2_QNG 16
288#define ASC_MAX_SCSI2_QNG 32
289#define ASC_TAG_CODE_MASK 0x23
290#define ASC_STOP_REQ_RISC_STOP 0x01
291#define ASC_STOP_ACK_RISC_STOP 0x03
292#define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
293#define ASC_STOP_CLEAN_UP_DISC_Q 0x20
294#define ASC_STOP_HOST_REQ_RISC_HALT 0x40
295#define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
296#define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
297#define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
298#define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
299#define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
300#define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
301#define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
302
303typedef struct asc_scsiq_1 {
27c868c2
MW		 304 uchar status;
305 uchar q_no;
306 uchar cntl;
307 uchar sg_queue_cnt;
308 uchar target_id;
309 uchar target_lun;
310 ASC_PADDR data_addr;
311 ASC_DCNT data_cnt;
312 ASC_PADDR sense_addr;
313 uchar sense_len;
314 uchar extra_bytes;
1da177e4
LT		 315} ASC_SCSIQ_1;
316
317typedef struct asc_scsiq_2 {
27c868c2
MW		 318 ASC_VADDR srb_ptr;
319 uchar target_ix;
320 uchar flag;
321 uchar cdb_len;
322 uchar tag_code;
323 ushort vm_id;
1da177e4
LT		 324} ASC_SCSIQ_2;
325
326typedef struct asc_scsiq_3 {
27c868c2
MW		 327 uchar done_stat;
328 uchar host_stat;
329 uchar scsi_stat;
330 uchar scsi_msg;
1da177e4
LT		 331} ASC_SCSIQ_3;
332
333typedef struct asc_scsiq_4 {
27c868c2
MW		 334 uchar cdb[ASC_MAX_CDB_LEN];
335 uchar y_first_sg_list_qp;
336 uchar y_working_sg_qp;
337 uchar y_working_sg_ix;
338 uchar y_res;
339 ushort x_req_count;
340 ushort x_reconnect_rtn;
341 ASC_PADDR x_saved_data_addr;
342 ASC_DCNT x_saved_data_cnt;
1da177e4
LT		 343} ASC_SCSIQ_4;
344
345typedef struct asc_q_done_info {
27c868c2
MW		 346 ASC_SCSIQ_2 d2;
347 ASC_SCSIQ_3 d3;
348 uchar q_status;
349 uchar q_no;
350 uchar cntl;
351 uchar sense_len;
352 uchar extra_bytes;
353 uchar res;
354 ASC_DCNT remain_bytes;
1da177e4
LT		 355} ASC_QDONE_INFO;
356
357typedef struct asc_sg_list {
27c868c2
MW		 358 ASC_PADDR addr;
359 ASC_DCNT bytes;
1da177e4
LT		 360} ASC_SG_LIST;
361
362typedef struct asc_sg_head {
27c868c2
MW		 363 ushort entry_cnt;
364 ushort queue_cnt;
365 ushort entry_to_copy;
366 ushort res;
05848b6e 367 ASC_SG_LIST sg_list[0];
1da177e4
LT		 368} ASC_SG_HEAD;
369
1da177e4 370typedef struct asc_scsi_q {
27c868c2
MW		 371 ASC_SCSIQ_1 q1;
372 ASC_SCSIQ_2 q2;
373 uchar *cdbptr;
374 ASC_SG_HEAD *sg_head;
375 ushort remain_sg_entry_cnt;
376 ushort next_sg_index;
1da177e4
LT		 377} ASC_SCSI_Q;
378
379typedef struct asc_scsi_req_q {
27c868c2
MW		 380 ASC_SCSIQ_1 r1;
381 ASC_SCSIQ_2 r2;
382 uchar *cdbptr;
383 ASC_SG_HEAD *sg_head;
384 uchar *sense_ptr;
385 ASC_SCSIQ_3 r3;
386 uchar cdb[ASC_MAX_CDB_LEN];
387 uchar sense[ASC_MIN_SENSE_LEN];
1da177e4
LT		 388} ASC_SCSI_REQ_Q;
389
390typedef struct asc_scsi_bios_req_q {
27c868c2
MW		 391 ASC_SCSIQ_1 r1;
392 ASC_SCSIQ_2 r2;
393 uchar *cdbptr;
394 ASC_SG_HEAD *sg_head;
395 uchar *sense_ptr;
396 ASC_SCSIQ_3 r3;
397 uchar cdb[ASC_MAX_CDB_LEN];
398 uchar sense[ASC_MIN_SENSE_LEN];
1da177e4
LT		 399} ASC_SCSI_BIOS_REQ_Q;
400
401typedef struct asc_risc_q {
27c868c2
MW		 402 uchar fwd;
403 uchar bwd;
404 ASC_SCSIQ_1 i1;
405 ASC_SCSIQ_2 i2;
406 ASC_SCSIQ_3 i3;
407 ASC_SCSIQ_4 i4;
1da177e4
LT		 408} ASC_RISC_Q;
409
410typedef struct asc_sg_list_q {
27c868c2
MW		 411 uchar seq_no;
412 uchar q_no;
413 uchar cntl;
414 uchar sg_head_qp;
415 uchar sg_list_cnt;
416 uchar sg_cur_list_cnt;
1da177e4
LT		 417} ASC_SG_LIST_Q;
418
419typedef struct asc_risc_sg_list_q {
27c868c2
MW		 420 uchar fwd;
421 uchar bwd;
422 ASC_SG_LIST_Q sg;
423 ASC_SG_LIST sg_list[7];
1da177e4
LT		 424} ASC_RISC_SG_LIST_Q;
425
1da177e4 426#define ASCQ_ERR_Q_STATUS 0x0D
1da177e4
LT		 427#define ASCQ_ERR_CUR_QNG 0x17
428#define ASCQ_ERR_SG_Q_LINKS 0x18
1da177e4
LT		 429#define ASCQ_ERR_ISR_RE_ENTRY 0x1A
430#define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
431#define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
1da177e4
LT		 432
433/*
434 * Warning code values are set in ASC_DVC_VAR 'warn_code'.
435 */
436#define ASC_WARN_NO_ERROR 0x0000
437#define ASC_WARN_IO_PORT_ROTATE 0x0001
438#define ASC_WARN_EEPROM_CHKSUM 0x0002
439#define ASC_WARN_IRQ_MODIFIED 0x0004
440#define ASC_WARN_AUTO_CONFIG 0x0008
441#define ASC_WARN_CMD_QNG_CONFLICT 0x0010
442#define ASC_WARN_EEPROM_RECOVER 0x0020
443#define ASC_WARN_CFG_MSW_RECOVER 0x0040
1da177e4
LT		 444
445/*
720349a8 446 * Error code values are set in {ASC/ADV}_DVC_VAR 'err_code'.
1da177e4 447 */
720349a8
MW		 448#define ASC_IERR_NO_CARRIER 0x0001 /* No more carrier memory */
449#define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
450#define ASC_IERR_SET_PC_ADDR 0x0004
451#define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
452#define ASC_IERR_ILLEGAL_CONNECTION 0x0010 /* Illegal cable connection */
453#define ASC_IERR_SINGLE_END_DEVICE 0x0020 /* SE device on DIFF bus */
454#define ASC_IERR_REVERSED_CABLE 0x0040 /* Narrow flat cable reversed */
455#define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
456#define ASC_IERR_HVD_DEVICE 0x0100 /* HVD device on LVD port */
457#define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
458#define ASC_IERR_NO_BUS_TYPE 0x0400
459#define ASC_IERR_BIST_PRE_TEST 0x0800 /* BIST pre-test error */
460#define ASC_IERR_BIST_RAM_TEST 0x1000 /* BIST RAM test error */
461#define ASC_IERR_BAD_CHIPTYPE 0x2000 /* Invalid chip_type setting */
1da177e4 462
1da177e4
LT		 463#define ASC_DEF_MAX_TOTAL_QNG (0xF0)
464#define ASC_MIN_TAG_Q_PER_DVC (0x04)
95c9f162 465#define ASC_MIN_FREE_Q (0x02)
1da177e4
LT		 466#define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
467#define ASC_MAX_TOTAL_QNG 240
468#define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
469#define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
470#define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
471#define ASC_MAX_INRAM_TAG_QNG 16
1da177e4 472#define ASC_IOADR_GAP 0x10
1da177e4
LT		 473#define ASC_SYN_MAX_OFFSET 0x0F
474#define ASC_DEF_SDTR_OFFSET 0x0F
1da177e4 475#define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
afbb68c3
MW		 476#define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
477
478/* The narrow chip only supports a limited selection of transfer rates.
479 * These are encoded in the range 0..7 or 0..15 depending whether the chip
480 * is Ultra-capable or not. These tables let us convert from one to the other.
481 */
482static const unsigned char asc_syn_xfer_period[8] = {
483 25, 30, 35, 40, 50, 60, 70, 85
484};
485
486static const unsigned char asc_syn_ultra_xfer_period[16] = {
487 12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107
488};
1da177e4
LT		 489
490typedef struct ext_msg {
27c868c2
MW		 491 uchar msg_type;
492 uchar msg_len;
493 uchar msg_req;
494 union {
495 struct {
496 uchar sdtr_xfer_period;
497 uchar sdtr_req_ack_offset;
498 } sdtr;
499 struct {
500 uchar wdtr_width;
501 } wdtr;
502 struct {
503 uchar mdp_b3;
504 uchar mdp_b2;
505 uchar mdp_b1;
506 uchar mdp_b0;
507 } mdp;
508 } u_ext_msg;
509 uchar res;
1da177e4
LT		 510} EXT_MSG;
511
512#define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
513#define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
514#define wdtr_width u_ext_msg.wdtr.wdtr_width
515#define mdp_b3 u_ext_msg.mdp_b3
516#define mdp_b2 u_ext_msg.mdp_b2
517#define mdp_b1 u_ext_msg.mdp_b1
518#define mdp_b0 u_ext_msg.mdp_b0
519
520typedef struct asc_dvc_cfg {
27c868c2
MW		 521 ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
522 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
523 ASC_SCSI_BIT_ID_TYPE disc_enable;
524 ASC_SCSI_BIT_ID_TYPE sdtr_enable;
525 uchar chip_scsi_id;
526 uchar isa_dma_speed;
527 uchar isa_dma_channel;
528 uchar chip_version;
27c868c2
MW		 529 ushort mcode_date;
530 ushort mcode_version;
531 uchar max_tag_qng[ASC_MAX_TID + 1];
27c868c2 532 uchar sdtr_period_offset[ASC_MAX_TID + 1];
27c868c2 533 uchar adapter_info[6];
1da177e4
LT		 534} ASC_DVC_CFG;
535
536#define ASC_DEF_DVC_CNTL 0xFFFF
537#define ASC_DEF_CHIP_SCSI_ID 7
538#define ASC_DEF_ISA_DMA_SPEED 4
1da177e4
LT		 539#define ASC_INIT_STATE_BEG_GET_CFG 0x0001
540#define ASC_INIT_STATE_END_GET_CFG 0x0002
541#define ASC_INIT_STATE_BEG_SET_CFG 0x0004
542#define ASC_INIT_STATE_END_SET_CFG 0x0008
543#define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
544#define ASC_INIT_STATE_END_LOAD_MC 0x0020
545#define ASC_INIT_STATE_BEG_INQUIRY 0x0040
546#define ASC_INIT_STATE_END_INQUIRY 0x0080
547#define ASC_INIT_RESET_SCSI_DONE 0x0100
548#define ASC_INIT_STATE_WITHOUT_EEP 0x8000
1da177e4
LT		 549#define ASC_BUG_FIX_IF_NOT_DWB 0x0001
550#define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
1da177e4
LT		 551#define ASC_MIN_TAGGED_CMD 7
552#define ASC_MAX_SCSI_RESET_WAIT 30
d10fb2c7 553#define ASC_OVERRUN_BSIZE 64
1da177e4 554
27c868c2 555struct asc_dvc_var; /* Forward Declaration. */
1da177e4 556
1da177e4 557typedef struct asc_dvc_var {
27c868c2
MW		 558 PortAddr iop_base;
559 ushort err_code;
560 ushort dvc_cntl;
561 ushort bug_fix_cntl;
562 ushort bus_type;
27c868c2
MW		 563 ASC_SCSI_BIT_ID_TYPE init_sdtr;
564 ASC_SCSI_BIT_ID_TYPE sdtr_done;
565 ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
566 ASC_SCSI_BIT_ID_TYPE unit_not_ready;
567 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
568 ASC_SCSI_BIT_ID_TYPE start_motor;
7d5d408c 569 uchar *overrun_buf;
d10fb2c7 570 dma_addr_t overrun_dma;
27c868c2
MW		 571 uchar scsi_reset_wait;
572 uchar chip_no;
573 char is_in_int;
574 uchar max_total_qng;
575 uchar cur_total_qng;
576 uchar in_critical_cnt;
27c868c2
MW		 577 uchar last_q_shortage;
578 ushort init_state;
579 uchar cur_dvc_qng[ASC_MAX_TID + 1];
580 uchar max_dvc_qng[ASC_MAX_TID + 1];
581 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
582 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
afbb68c3 583 const uchar *sdtr_period_tbl;
27c868c2
MW		 584 ASC_DVC_CFG *cfg;
585 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
586 char redo_scam;
587 ushort res2;
588 uchar dos_int13_table[ASC_MAX_TID + 1];
589 ASC_DCNT max_dma_count;
590 ASC_SCSI_BIT_ID_TYPE no_scam;
591 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
afbb68c3 592 uchar min_sdtr_index;
27c868c2 593 uchar max_sdtr_index;
27c868c2 594 struct asc_board *drv_ptr;
b249c7fd
MW		 595 int ptr_map_count;
596 void **ptr_map;
27c868c2 597 ASC_DCNT uc_break;
1da177e4
LT		 598} ASC_DVC_VAR;
599
600typedef struct asc_dvc_inq_info {
27c868c2 601 uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
1da177e4
LT		 602} ASC_DVC_INQ_INFO;
603
604typedef struct asc_cap_info {
27c868c2
MW		 605 ASC_DCNT lba;
606 ASC_DCNT blk_size;
1da177e4
LT		 607} ASC_CAP_INFO;
608
609typedef struct asc_cap_info_array {
27c868c2 610 ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
1da177e4
LT		 611} ASC_CAP_INFO_ARRAY;
612
613#define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
614#define ASC_MCNTL_NULL_TARGET (ushort)0x0002
615#define ASC_CNTL_INITIATOR (ushort)0x0001
616#define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
617#define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
618#define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
619#define ASC_CNTL_NO_SCAM (ushort)0x0010
620#define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
621#define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
622#define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
623#define ASC_CNTL_RESET_SCSI (ushort)0x0200
624#define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
625#define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
626#define ASC_CNTL_SCSI_PARITY (ushort)0x1000
627#define ASC_CNTL_BURST_MODE (ushort)0x2000
628#define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
629#define ASC_EEP_DVC_CFG_BEG_VL 2
630#define ASC_EEP_MAX_DVC_ADDR_VL 15
631#define ASC_EEP_DVC_CFG_BEG 32
632#define ASC_EEP_MAX_DVC_ADDR 45
1da177e4 633#define ASC_EEP_MAX_RETRY 20
1da177e4
LT		 634
635/*
636 * These macros keep the chip SCSI id and ISA DMA speed
637 * bitfields in board order. C bitfields aren't portable
638 * between big and little-endian platforms so they are
639 * not used.
640 */
641
642#define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
643#define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
644#define ASC_EEP_SET_CHIP_ID(cfg, sid) \
645 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
646#define ASC_EEP_SET_DMA_SPD(cfg, spd) \
647 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
648
649typedef struct asceep_config {
27c868c2
MW		 650 ushort cfg_lsw;
651 ushort cfg_msw;
652 uchar init_sdtr;
653 uchar disc_enable;
654 uchar use_cmd_qng;
655 uchar start_motor;
656 uchar max_total_qng;
657 uchar max_tag_qng;
658 uchar bios_scan;
659 uchar power_up_wait;
660 uchar no_scam;
661 uchar id_speed; /* low order 4 bits is chip scsi id */
662 /* high order 4 bits is isa dma speed */
663 uchar dos_int13_table[ASC_MAX_TID + 1];
664 uchar adapter_info[6];
665 ushort cntl;
666 ushort chksum;
1da177e4
LT		 667} ASCEEP_CONFIG;
668
1da177e4
LT		 669#define ASC_EEP_CMD_READ 0x80
670#define ASC_EEP_CMD_WRITE 0x40
671#define ASC_EEP_CMD_WRITE_ABLE 0x30
672#define ASC_EEP_CMD_WRITE_DISABLE 0x00
1da177e4
LT		 673#define ASCV_MSGOUT_BEG 0x0000
674#define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
675#define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
676#define ASCV_BREAK_SAVED_CODE (ushort)0x0006
677#define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
678#define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
679#define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
680#define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
681#define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
682#define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
683#define ASCV_BREAK_ADDR (ushort)0x0028
684#define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
685#define ASCV_BREAK_CONTROL (ushort)0x002C
686#define ASCV_BREAK_HIT_COUNT (ushort)0x002E
687
688#define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
689#define ASCV_MCODE_CHKSUM_W (ushort)0x0032
690#define ASCV_MCODE_SIZE_W (ushort)0x0034
691#define ASCV_STOP_CODE_B (ushort)0x0036
692#define ASCV_DVC_ERR_CODE_B (ushort)0x0037
693#define ASCV_OVERRUN_PADDR_D (ushort)0x0038
694#define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
695#define ASCV_HALTCODE_W (ushort)0x0040
696#define ASCV_CHKSUM_W (ushort)0x0042
697#define ASCV_MC_DATE_W (ushort)0x0044
698#define ASCV_MC_VER_W (ushort)0x0046
699#define ASCV_NEXTRDY_B (ushort)0x0048
700#define ASCV_DONENEXT_B (ushort)0x0049
701#define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
702#define ASCV_SCSIBUSY_B (ushort)0x004B
703#define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
704#define ASCV_CURCDB_B (ushort)0x004D
705#define ASCV_RCLUN_B (ushort)0x004E
706#define ASCV_BUSY_QHEAD_B (ushort)0x004F
707#define ASCV_DISC1_QHEAD_B (ushort)0x0050
708#define ASCV_DISC_ENABLE_B (ushort)0x0052
709#define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
710#define ASCV_HOSTSCSI_ID_B (ushort)0x0055
711#define ASCV_MCODE_CNTL_B (ushort)0x0056
712#define ASCV_NULL_TARGET_B (ushort)0x0057
713#define ASCV_FREE_Q_HEAD_W (ushort)0x0058
714#define ASCV_DONE_Q_TAIL_W (ushort)0x005A
715#define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
716#define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
717#define ASCV_HOST_FLAG_B (ushort)0x005D
718#define ASCV_TOTAL_READY_Q_B (ushort)0x0064
719#define ASCV_VER_SERIAL_B (ushort)0x0065
720#define ASCV_HALTCODE_SAVED_W (ushort)0x0066
721#define ASCV_WTM_FLAG_B (ushort)0x0068
722#define ASCV_RISC_FLAG_B (ushort)0x006A
723#define ASCV_REQ_SG_LIST_QP (ushort)0x006B
724#define ASC_HOST_FLAG_IN_ISR 0x01
725#define ASC_HOST_FLAG_ACK_INT 0x02
726#define ASC_RISC_FLAG_GEN_INT 0x01
727#define ASC_RISC_FLAG_REQ_SG_LIST 0x02
728#define IOP_CTRL (0x0F)
729#define IOP_STATUS (0x0E)
730#define IOP_INT_ACK IOP_STATUS
731#define IOP_REG_IFC (0x0D)
732#define IOP_SYN_OFFSET (0x0B)
733#define IOP_EXTRA_CONTROL (0x0D)
734#define IOP_REG_PC (0x0C)
735#define IOP_RAM_ADDR (0x0A)
736#define IOP_RAM_DATA (0x08)
737#define IOP_EEP_DATA (0x06)
738#define IOP_EEP_CMD (0x07)
739#define IOP_VERSION (0x03)
740#define IOP_CONFIG_HIGH (0x04)
741#define IOP_CONFIG_LOW (0x02)
742#define IOP_SIG_BYTE (0x01)
743#define IOP_SIG_WORD (0x00)
744#define IOP_REG_DC1 (0x0E)
745#define IOP_REG_DC0 (0x0C)
746#define IOP_REG_SB (0x0B)
747#define IOP_REG_DA1 (0x0A)
748#define IOP_REG_DA0 (0x08)
749#define IOP_REG_SC (0x09)
750#define IOP_DMA_SPEED (0x07)
751#define IOP_REG_FLAG (0x07)
752#define IOP_FIFO_H (0x06)
753#define IOP_FIFO_L (0x04)
754#define IOP_REG_ID (0x05)
755#define IOP_REG_QP (0x03)
756#define IOP_REG_IH (0x02)
757#define IOP_REG_IX (0x01)
758#define IOP_REG_AX (0x00)
759#define IFC_REG_LOCK (0x00)
760#define IFC_REG_UNLOCK (0x09)
761#define IFC_WR_EN_FILTER (0x10)
762#define IFC_RD_NO_EEPROM (0x10)
763#define IFC_SLEW_RATE (0x20)
764#define IFC_ACT_NEG (0x40)
765#define IFC_INP_FILTER (0x80)
766#define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
767#define SC_SEL (uchar)(0x80)
768#define SC_BSY (uchar)(0x40)
769#define SC_ACK (uchar)(0x20)
770#define SC_REQ (uchar)(0x10)
771#define SC_ATN (uchar)(0x08)
772#define SC_IO (uchar)(0x04)
773#define SC_CD (uchar)(0x02)
774#define SC_MSG (uchar)(0x01)
775#define SEC_SCSI_CTL (uchar)(0x80)
776#define SEC_ACTIVE_NEGATE (uchar)(0x40)
777#define SEC_SLEW_RATE (uchar)(0x20)
778#define SEC_ENABLE_FILTER (uchar)(0x10)
779#define ASC_HALT_EXTMSG_IN (ushort)0x8000
780#define ASC_HALT_CHK_CONDITION (ushort)0x8100
781#define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
782#define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
783#define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
784#define ASC_HALT_SDTR_REJECTED (ushort)0x4000
785#define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
786#define ASC_MAX_QNO 0xF8
787#define ASC_DATA_SEC_BEG (ushort)0x0080
788#define ASC_DATA_SEC_END (ushort)0x0080
789#define ASC_CODE_SEC_BEG (ushort)0x0080
790#define ASC_CODE_SEC_END (ushort)0x0080
791#define ASC_QADR_BEG (0x4000)
792#define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
793#define ASC_QADR_END (ushort)0x7FFF
794#define ASC_QLAST_ADR (ushort)0x7FC0
795#define ASC_QBLK_SIZE 0x40
796#define ASC_BIOS_DATA_QBEG 0xF8
797#define ASC_MIN_ACTIVE_QNO 0x01
798#define ASC_QLINK_END 0xFF
799#define ASC_EEPROM_WORDS 0x10
800#define ASC_MAX_MGS_LEN 0x10
801#define ASC_BIOS_ADDR_DEF 0xDC00
802#define ASC_BIOS_SIZE 0x3800
803#define ASC_BIOS_RAM_OFF 0x3800
804#define ASC_BIOS_RAM_SIZE 0x800
805#define ASC_BIOS_MIN_ADDR 0xC000
806#define ASC_BIOS_MAX_ADDR 0xEC00
807#define ASC_BIOS_BANK_SIZE 0x0400
808#define ASC_MCODE_START_ADDR 0x0080
809#define ASC_CFG0_HOST_INT_ON 0x0020
810#define ASC_CFG0_BIOS_ON 0x0040
811#define ASC_CFG0_VERA_BURST_ON 0x0080
812#define ASC_CFG0_SCSI_PARITY_ON 0x0800
813#define ASC_CFG1_SCSI_TARGET_ON 0x0080
814#define ASC_CFG1_LRAM_8BITS_ON 0x0800
815#define ASC_CFG_MSW_CLR_MASK 0x3080
816#define CSW_TEST1 (ASC_CS_TYPE)0x8000
817#define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
818#define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
819#define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
820#define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
821#define CSW_TEST2 (ASC_CS_TYPE)0x0400
822#define CSW_TEST3 (ASC_CS_TYPE)0x0200
823#define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
824#define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
825#define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
826#define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
827#define CSW_HALTED (ASC_CS_TYPE)0x0010
828#define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
829#define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
830#define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
831#define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
832#define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
833#define CIW_INT_ACK (ASC_CS_TYPE)0x0100
834#define CIW_TEST1 (ASC_CS_TYPE)0x0200
835#define CIW_TEST2 (ASC_CS_TYPE)0x0400
836#define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
837#define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
838#define CC_CHIP_RESET (uchar)0x80
839#define CC_SCSI_RESET (uchar)0x40
840#define CC_HALT (uchar)0x20
841#define CC_SINGLE_STEP (uchar)0x10
842#define CC_DMA_ABLE (uchar)0x08
843#define CC_TEST (uchar)0x04
844#define CC_BANK_ONE (uchar)0x02
845#define CC_DIAG (uchar)0x01
846#define ASC_1000_ID0W 0x04C1
847#define ASC_1000_ID0W_FIX 0x00C1
848#define ASC_1000_ID1B 0x25
1da177e4 849#define ASC_EISA_REV_IOP_MASK (0x0C83)
1da177e4
LT		 850#define ASC_EISA_CFG_IOP_MASK (0x0C86)
851#define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
1da177e4
LT		 852#define INS_HALTINT (ushort)0x6281
853#define INS_HALT (ushort)0x6280
854#define INS_SINT (ushort)0x6200
855#define INS_RFLAG_WTM (ushort)0x7380
856#define ASC_MC_SAVE_CODE_WSIZE 0x500
857#define ASC_MC_SAVE_DATA_WSIZE 0x40
858
859typedef struct asc_mc_saved {
27c868c2
MW		 860 ushort data[ASC_MC_SAVE_DATA_WSIZE];
861 ushort code[ASC_MC_SAVE_CODE_WSIZE];
1da177e4
LT		 862} ASC_MC_SAVED;
863
864#define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
865#define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
866#define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
867#define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
868#define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
869#define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
870#define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
871#define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
872#define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
873#define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
51219358
MW		 874#define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
875#define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
876#define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
877#define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
1da177e4
LT		 878#define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
879#define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
880#define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
881#define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
882#define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
883#define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
884#define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
885#define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
886#define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
887#define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
888#define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
889#define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
890#define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
891#define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
892#define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
893#define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
894#define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
895#define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
896#define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
897#define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
898#define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
899#define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
900#define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
901#define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
902#define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
903#define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
904#define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
905#define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
906#define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
907#define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
908#define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
909#define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
910#define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
911#define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
912#define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
913#define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
914#define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
915#define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
916#define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
917#define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
918#define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
919#define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
920#define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
921#define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
922#define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
923#define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
924#define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
925#define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
926#define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
927#define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
928#define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
929#define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
930#define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
931
1da177e4
LT		 932/*
933 * Portable Data Types
934 *
935 * Any instance where a 32-bit long or pointer type is assumed
936 * for precision or HW defined structures, the following define
937 * types must be used. In Linux the char, short, and int types
938 * are all consistent at 8, 16, and 32 bits respectively. Pointers
939 * and long types are 64 bits on Alpha and UltraSPARC.
940 */
27c868c2
MW		 941#define ADV_PADDR __u32 /* Physical address data type. */
942#define ADV_VADDR __u32 /* Virtual address data type. */
943#define ADV_DCNT __u32 /* Unsigned Data count type. */
944#define ADV_SDCNT __s32 /* Signed Data count type. */
1da177e4
LT		 945
946/*
947 * These macros are used to convert a virtual address to a
948 * 32-bit value. This currently can be used on Linux Alpha
949 * which uses 64-bit virtual address but a 32-bit bus address.
950 * This is likely to break in the future, but doing this now
951 * will give us time to change the HW and FW to handle 64-bit
952 * addresses.
953 */
954#define ADV_VADDR_TO_U32 virt_to_bus
955#define ADV_U32_TO_VADDR bus_to_virt
956
27c868c2 957#define AdvPortAddr void __iomem * /* Virtual memory address size */
1da177e4
LT		 958
959/*
960 * Define Adv Library required memory access macros.
961 */
962#define ADV_MEM_READB(addr) readb(addr)
963#define ADV_MEM_READW(addr) readw(addr)
964#define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
965#define ADV_MEM_WRITEW(addr, word) writew(word, addr)
966#define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
967
968#define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 15)
969
1da177e4
LT		 970/*
971 * Define total number of simultaneous maximum element scatter-gather
972 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
973 * maximum number of outstanding commands per wide host adapter. Each
974 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
975 * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
976 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
977 * structures or 255 scatter-gather elements.
1da177e4
LT		 978 */
979#define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
980
981/*
98d41c29 982 * Define maximum number of scatter-gather elements per request.
1da177e4
LT		 983 */
984#define ADV_MAX_SG_LIST 255
98d41c29 985#define NO_OF_SG_PER_BLOCK 15
1da177e4 986
1da177e4
LT		 987#define ADV_EEP_DVC_CFG_BEGIN (0x00)
988#define ADV_EEP_DVC_CFG_END (0x15)
27c868c2 989#define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
1da177e4
LT		 990#define ADV_EEP_MAX_WORD_ADDR (0x1E)
991
992#define ADV_EEP_DELAY_MS 100
993
27c868c2
MW		 994#define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
995#define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
1da177e4
LT		 996/*
997 * For the ASC3550 Bit 13 is Termination Polarity control bit.
998 * For later ICs Bit 13 controls whether the CIS (Card Information
999 * Service Section) is loaded from EEPROM.
1000 */
27c868c2
MW		 1001#define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
1002#define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
1da177e4
LT		 1003/*
1004 * ASC38C1600 Bit 11
1005 *
1006 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
1007 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
1008 * Function 0 will specify INT B.
1009 *
1010 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
1011 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
1012 * Function 1 will specify INT A.
1013 */
27c868c2
MW		 1014#define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
1015
1016typedef struct adveep_3550_config {
1017 /* Word Offset, Description */
1018
1019 ushort cfg_lsw; /* 00 power up initialization */
1020 /* bit 13 set - Term Polarity Control */
1021 /* bit 14 set - BIOS Enable */
1022 /* bit 15 set - Big Endian Mode */
1023 ushort cfg_msw; /* 01 unused */
1024 ushort disc_enable; /* 02 disconnect enable */
1025 ushort wdtr_able; /* 03 Wide DTR able */
1026 ushort sdtr_able; /* 04 Synchronous DTR able */
1027 ushort start_motor; /* 05 send start up motor */
1028 ushort tagqng_able; /* 06 tag queuing able */
1029 ushort bios_scan; /* 07 BIOS device control */
1030 ushort scam_tolerant; /* 08 no scam */
1031
1032 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1033 uchar bios_boot_delay; /* power up wait */
1034
1035 uchar scsi_reset_delay; /* 10 reset delay */
1036 uchar bios_id_lun; /* first boot device scsi id & lun */
1037 /* high nibble is lun */
1038 /* low nibble is scsi id */
1039
1040 uchar termination; /* 11 0 - automatic */
1041 /* 1 - low off / high off */
1042 /* 2 - low off / high on */
1043 /* 3 - low on / high on */
1044 /* There is no low on / high off */
1045
1046 uchar reserved1; /* reserved byte (not used) */
1047
1048 ushort bios_ctrl; /* 12 BIOS control bits */
1049 /* bit 0 BIOS don't act as initiator. */
1050 /* bit 1 BIOS > 1 GB support */
1051 /* bit 2 BIOS > 2 Disk Support */
1052 /* bit 3 BIOS don't support removables */
1053 /* bit 4 BIOS support bootable CD */
1054 /* bit 5 BIOS scan enabled */
1055 /* bit 6 BIOS support multiple LUNs */
1056 /* bit 7 BIOS display of message */
1057 /* bit 8 SCAM disabled */
1058 /* bit 9 Reset SCSI bus during init. */
1059 /* bit 10 */
1060 /* bit 11 No verbose initialization. */
1061 /* bit 12 SCSI parity enabled */
1062 /* bit 13 */
1063 /* bit 14 */
1064 /* bit 15 */
1065 ushort ultra_able; /* 13 ULTRA speed able */
1066 ushort reserved2; /* 14 reserved */
1067 uchar max_host_qng; /* 15 maximum host queuing */
1068 uchar max_dvc_qng; /* maximum per device queuing */
1069 ushort dvc_cntl; /* 16 control bit for driver */
1070 ushort bug_fix; /* 17 control bit for bug fix */
1071 ushort serial_number_word1; /* 18 Board serial number word 1 */
1072 ushort serial_number_word2; /* 19 Board serial number word 2 */
1073 ushort serial_number_word3; /* 20 Board serial number word 3 */
1074 ushort check_sum; /* 21 EEP check sum */
1075 uchar oem_name[16]; /* 22 OEM name */
1076 ushort dvc_err_code; /* 30 last device driver error code */
1077 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1078 ushort adv_err_addr; /* 32 last uc error address */
1079 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1080 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1081 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1082 ushort num_of_err; /* 36 number of error */
1da177e4
LT		 1083} ADVEEP_3550_CONFIG;
1084
27c868c2
MW		 1085typedef struct adveep_38C0800_config {
1086 /* Word Offset, Description */
1087
1088 ushort cfg_lsw; /* 00 power up initialization */
1089 /* bit 13 set - Load CIS */
1090 /* bit 14 set - BIOS Enable */
1091 /* bit 15 set - Big Endian Mode */
1092 ushort cfg_msw; /* 01 unused */
1093 ushort disc_enable; /* 02 disconnect enable */
1094 ushort wdtr_able; /* 03 Wide DTR able */
1095 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1096 ushort start_motor; /* 05 send start up motor */
1097 ushort tagqng_able; /* 06 tag queuing able */
1098 ushort bios_scan; /* 07 BIOS device control */
1099 ushort scam_tolerant; /* 08 no scam */
1100
1101 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1102 uchar bios_boot_delay; /* power up wait */
1103
1104 uchar scsi_reset_delay; /* 10 reset delay */
1105 uchar bios_id_lun; /* first boot device scsi id & lun */
1106 /* high nibble is lun */
1107 /* low nibble is scsi id */
1108
1109 uchar termination_se; /* 11 0 - automatic */
1110 /* 1 - low off / high off */
1111 /* 2 - low off / high on */
1112 /* 3 - low on / high on */
1113 /* There is no low on / high off */
1114
1115 uchar termination_lvd; /* 11 0 - automatic */
1116 /* 1 - low off / high off */
1117 /* 2 - low off / high on */
1118 /* 3 - low on / high on */
1119 /* There is no low on / high off */
1120
1121 ushort bios_ctrl; /* 12 BIOS control bits */
1122 /* bit 0 BIOS don't act as initiator. */
1123 /* bit 1 BIOS > 1 GB support */
1124 /* bit 2 BIOS > 2 Disk Support */
1125 /* bit 3 BIOS don't support removables */
1126 /* bit 4 BIOS support bootable CD */
1127 /* bit 5 BIOS scan enabled */
1128 /* bit 6 BIOS support multiple LUNs */
1129 /* bit 7 BIOS display of message */
1130 /* bit 8 SCAM disabled */
1131 /* bit 9 Reset SCSI bus during init. */
1132 /* bit 10 */
1133 /* bit 11 No verbose initialization. */
1134 /* bit 12 SCSI parity enabled */
1135 /* bit 13 */
1136 /* bit 14 */
1137 /* bit 15 */
1138 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1139 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1140 uchar max_host_qng; /* 15 maximum host queueing */
1141 uchar max_dvc_qng; /* maximum per device queuing */
1142 ushort dvc_cntl; /* 16 control bit for driver */
1143 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1144 ushort serial_number_word1; /* 18 Board serial number word 1 */
1145 ushort serial_number_word2; /* 19 Board serial number word 2 */
1146 ushort serial_number_word3; /* 20 Board serial number word 3 */
1147 ushort check_sum; /* 21 EEP check sum */
1148 uchar oem_name[16]; /* 22 OEM name */
1149 ushort dvc_err_code; /* 30 last device driver error code */
1150 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1151 ushort adv_err_addr; /* 32 last uc error address */
1152 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1153 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1154 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1155 ushort reserved36; /* 36 reserved */
1156 ushort reserved37; /* 37 reserved */
1157 ushort reserved38; /* 38 reserved */
1158 ushort reserved39; /* 39 reserved */
1159 ushort reserved40; /* 40 reserved */
1160 ushort reserved41; /* 41 reserved */
1161 ushort reserved42; /* 42 reserved */
1162 ushort reserved43; /* 43 reserved */
1163 ushort reserved44; /* 44 reserved */
1164 ushort reserved45; /* 45 reserved */
1165 ushort reserved46; /* 46 reserved */
1166 ushort reserved47; /* 47 reserved */
1167 ushort reserved48; /* 48 reserved */
1168 ushort reserved49; /* 49 reserved */
1169 ushort reserved50; /* 50 reserved */
1170 ushort reserved51; /* 51 reserved */
1171 ushort reserved52; /* 52 reserved */
1172 ushort reserved53; /* 53 reserved */
1173 ushort reserved54; /* 54 reserved */
1174 ushort reserved55; /* 55 reserved */
1175 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1176 ushort cisprt_msw; /* 57 CIS PTR MSW */
1177 ushort subsysvid; /* 58 SubSystem Vendor ID */
1178 ushort subsysid; /* 59 SubSystem ID */
1179 ushort reserved60; /* 60 reserved */
1180 ushort reserved61; /* 61 reserved */
1181 ushort reserved62; /* 62 reserved */
1182 ushort reserved63; /* 63 reserved */
1da177e4
LT		 1183} ADVEEP_38C0800_CONFIG;
1184
27c868c2
MW		 1185typedef struct adveep_38C1600_config {
1186 /* Word Offset, Description */
1187
1188 ushort cfg_lsw; /* 00 power up initialization */
1189 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */
1190 /* clear - Func. 0 INTA, Func. 1 INTB */
1191 /* bit 13 set - Load CIS */
1192 /* bit 14 set - BIOS Enable */
1193 /* bit 15 set - Big Endian Mode */
1194 ushort cfg_msw; /* 01 unused */
1195 ushort disc_enable; /* 02 disconnect enable */
1196 ushort wdtr_able; /* 03 Wide DTR able */
1197 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1198 ushort start_motor; /* 05 send start up motor */
1199 ushort tagqng_able; /* 06 tag queuing able */
1200 ushort bios_scan; /* 07 BIOS device control */
1201 ushort scam_tolerant; /* 08 no scam */
1202
1203 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1204 uchar bios_boot_delay; /* power up wait */
1205
1206 uchar scsi_reset_delay; /* 10 reset delay */
1207 uchar bios_id_lun; /* first boot device scsi id & lun */
1208 /* high nibble is lun */
1209 /* low nibble is scsi id */
1210
1211 uchar termination_se; /* 11 0 - automatic */
1212 /* 1 - low off / high off */
1213 /* 2 - low off / high on */
1214 /* 3 - low on / high on */
1215 /* There is no low on / high off */
1216
1217 uchar termination_lvd; /* 11 0 - automatic */
1218 /* 1 - low off / high off */
1219 /* 2 - low off / high on */
1220 /* 3 - low on / high on */
1221 /* There is no low on / high off */
1222
1223 ushort bios_ctrl; /* 12 BIOS control bits */
1224 /* bit 0 BIOS don't act as initiator. */
1225 /* bit 1 BIOS > 1 GB support */
1226 /* bit 2 BIOS > 2 Disk Support */
1227 /* bit 3 BIOS don't support removables */
1228 /* bit 4 BIOS support bootable CD */
1229 /* bit 5 BIOS scan enabled */
1230 /* bit 6 BIOS support multiple LUNs */
1231 /* bit 7 BIOS display of message */
1232 /* bit 8 SCAM disabled */
1233 /* bit 9 Reset SCSI bus during init. */
1234 /* bit 10 Basic Integrity Checking disabled */
1235 /* bit 11 No verbose initialization. */
1236 /* bit 12 SCSI parity enabled */
1237 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
1238 /* bit 14 */
1239 /* bit 15 */
1240 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1241 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1242 uchar max_host_qng; /* 15 maximum host queueing */
1243 uchar max_dvc_qng; /* maximum per device queuing */
1244 ushort dvc_cntl; /* 16 control bit for driver */
1245 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1246 ushort serial_number_word1; /* 18 Board serial number word 1 */
1247 ushort serial_number_word2; /* 19 Board serial number word 2 */
1248 ushort serial_number_word3; /* 20 Board serial number word 3 */
1249 ushort check_sum; /* 21 EEP check sum */
1250 uchar oem_name[16]; /* 22 OEM name */
1251 ushort dvc_err_code; /* 30 last device driver error code */
1252 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1253 ushort adv_err_addr; /* 32 last uc error address */
1254 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1255 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1256 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1257 ushort reserved36; /* 36 reserved */
1258 ushort reserved37; /* 37 reserved */
1259 ushort reserved38; /* 38 reserved */
1260 ushort reserved39; /* 39 reserved */
1261 ushort reserved40; /* 40 reserved */
1262 ushort reserved41; /* 41 reserved */
1263 ushort reserved42; /* 42 reserved */
1264 ushort reserved43; /* 43 reserved */
1265 ushort reserved44; /* 44 reserved */
1266 ushort reserved45; /* 45 reserved */
1267 ushort reserved46; /* 46 reserved */
1268 ushort reserved47; /* 47 reserved */
1269 ushort reserved48; /* 48 reserved */
1270 ushort reserved49; /* 49 reserved */
1271 ushort reserved50; /* 50 reserved */
1272 ushort reserved51; /* 51 reserved */
1273 ushort reserved52; /* 52 reserved */
1274 ushort reserved53; /* 53 reserved */
1275 ushort reserved54; /* 54 reserved */
1276 ushort reserved55; /* 55 reserved */
1277 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1278 ushort cisprt_msw; /* 57 CIS PTR MSW */
1279 ushort subsysvid; /* 58 SubSystem Vendor ID */
1280 ushort subsysid; /* 59 SubSystem ID */
1281 ushort reserved60; /* 60 reserved */
1282 ushort reserved61; /* 61 reserved */
1283 ushort reserved62; /* 62 reserved */
1284 ushort reserved63; /* 63 reserved */
1da177e4
LT		 1285} ADVEEP_38C1600_CONFIG;
1286
1287/*
1288 * EEPROM Commands
1289 */
1290#define ASC_EEP_CMD_DONE 0x0200
1da177e4
LT		 1291
1292/* bios_ctrl */
1293#define BIOS_CTRL_BIOS 0x0001
1294#define BIOS_CTRL_EXTENDED_XLAT 0x0002
1295#define BIOS_CTRL_GT_2_DISK 0x0004
1296#define BIOS_CTRL_BIOS_REMOVABLE 0x0008
1297#define BIOS_CTRL_BOOTABLE_CD 0x0010
1298#define BIOS_CTRL_MULTIPLE_LUN 0x0040
1299#define BIOS_CTRL_DISPLAY_MSG 0x0080
1300#define BIOS_CTRL_NO_SCAM 0x0100
1301#define BIOS_CTRL_RESET_SCSI_BUS 0x0200
1302#define BIOS_CTRL_INIT_VERBOSE 0x0800
1303#define BIOS_CTRL_SCSI_PARITY 0x1000
1304#define BIOS_CTRL_AIPP_DIS 0x2000
1305
27c868c2 1306#define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
1da177e4 1307
27c868c2 1308#define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1da177e4
LT		 1309
1310/*
1311 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
1312 * a special 16K Adv Library and Microcode version. After the issue is
1313 * resolved, should restore 32K support.
1314 *
1315 * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
1316 */
27c868c2 1317#define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1da177e4
LT		 1318
1319/*
1320 * Byte I/O register address from base of 'iop_base'.
1321 */
1322#define IOPB_INTR_STATUS_REG 0x00
1323#define IOPB_CHIP_ID_1 0x01
1324#define IOPB_INTR_ENABLES 0x02
1325#define IOPB_CHIP_TYPE_REV 0x03
1326#define IOPB_RES_ADDR_4 0x04
1327#define IOPB_RES_ADDR_5 0x05
1328#define IOPB_RAM_DATA 0x06
1329#define IOPB_RES_ADDR_7 0x07
1330#define IOPB_FLAG_REG 0x08
1331#define IOPB_RES_ADDR_9 0x09
1332#define IOPB_RISC_CSR 0x0A
1333#define IOPB_RES_ADDR_B 0x0B
1334#define IOPB_RES_ADDR_C 0x0C
1335#define IOPB_RES_ADDR_D 0x0D
1336#define IOPB_SOFT_OVER_WR 0x0E
1337#define IOPB_RES_ADDR_F 0x0F
1338#define IOPB_MEM_CFG 0x10
1339#define IOPB_RES_ADDR_11 0x11
1340#define IOPB_GPIO_DATA 0x12
1341#define IOPB_RES_ADDR_13 0x13
1342#define IOPB_FLASH_PAGE 0x14
1343#define IOPB_RES_ADDR_15 0x15
1344#define IOPB_GPIO_CNTL 0x16
1345#define IOPB_RES_ADDR_17 0x17
1346#define IOPB_FLASH_DATA 0x18
1347#define IOPB_RES_ADDR_19 0x19
1348#define IOPB_RES_ADDR_1A 0x1A
1349#define IOPB_RES_ADDR_1B 0x1B
1350#define IOPB_RES_ADDR_1C 0x1C
1351#define IOPB_RES_ADDR_1D 0x1D
1352#define IOPB_RES_ADDR_1E 0x1E
1353#define IOPB_RES_ADDR_1F 0x1F
1354#define IOPB_DMA_CFG0 0x20
1355#define IOPB_DMA_CFG1 0x21
1356#define IOPB_TICKLE 0x22
1357#define IOPB_DMA_REG_WR 0x23
1358#define IOPB_SDMA_STATUS 0x24
1359#define IOPB_SCSI_BYTE_CNT 0x25
1360#define IOPB_HOST_BYTE_CNT 0x26
1361#define IOPB_BYTE_LEFT_TO_XFER 0x27
1362#define IOPB_BYTE_TO_XFER_0 0x28
1363#define IOPB_BYTE_TO_XFER_1 0x29
1364#define IOPB_BYTE_TO_XFER_2 0x2A
1365#define IOPB_BYTE_TO_XFER_3 0x2B
1366#define IOPB_ACC_GRP 0x2C
1367#define IOPB_RES_ADDR_2D 0x2D
1368#define IOPB_DEV_ID 0x2E
1369#define IOPB_RES_ADDR_2F 0x2F
1370#define IOPB_SCSI_DATA 0x30
1371#define IOPB_RES_ADDR_31 0x31
1372#define IOPB_RES_ADDR_32 0x32
1373#define IOPB_SCSI_DATA_HSHK 0x33
1374#define IOPB_SCSI_CTRL 0x34
1375#define IOPB_RES_ADDR_35 0x35
1376#define IOPB_RES_ADDR_36 0x36
1377#define IOPB_RES_ADDR_37 0x37
1378#define IOPB_RAM_BIST 0x38
1379#define IOPB_PLL_TEST 0x39
1380#define IOPB_PCI_INT_CFG 0x3A
1381#define IOPB_RES_ADDR_3B 0x3B
1382#define IOPB_RFIFO_CNT 0x3C
1383#define IOPB_RES_ADDR_3D 0x3D
1384#define IOPB_RES_ADDR_3E 0x3E
1385#define IOPB_RES_ADDR_3F 0x3F
1386
1387/*
1388 * Word I/O register address from base of 'iop_base'.
1389 */
27c868c2
MW		 1390#define IOPW_CHIP_ID_0 0x00 /* CID0 */
1391#define IOPW_CTRL_REG 0x02 /* CC */
1392#define IOPW_RAM_ADDR 0x04 /* LA */
1393#define IOPW_RAM_DATA 0x06 /* LD */
1da177e4 1394#define IOPW_RES_ADDR_08 0x08
27c868c2
MW		 1395#define IOPW_RISC_CSR 0x0A /* CSR */
1396#define IOPW_SCSI_CFG0 0x0C /* CFG0 */
1397#define IOPW_SCSI_CFG1 0x0E /* CFG1 */
1da177e4 1398#define IOPW_RES_ADDR_10 0x10
27c868c2 1399#define IOPW_SEL_MASK 0x12 /* SM */
1da177e4 1400#define IOPW_RES_ADDR_14 0x14
27c868c2 1401#define IOPW_FLASH_ADDR 0x16 /* FA */
1da177e4 1402#define IOPW_RES_ADDR_18 0x18
27c868c2
MW		 1403#define IOPW_EE_CMD 0x1A /* EC */
1404#define IOPW_EE_DATA 0x1C /* ED */
1405#define IOPW_SFIFO_CNT 0x1E /* SFC */
1da177e4 1406#define IOPW_RES_ADDR_20 0x20
27c868c2
MW		 1407#define IOPW_Q_BASE 0x22 /* QB */
1408#define IOPW_QP 0x24 /* QP */
1409#define IOPW_IX 0x26 /* IX */
1410#define IOPW_SP 0x28 /* SP */
1411#define IOPW_PC 0x2A /* PC */
1da177e4
LT		 1412#define IOPW_RES_ADDR_2C 0x2C
1413#define IOPW_RES_ADDR_2E 0x2E
27c868c2
MW		 1414#define IOPW_SCSI_DATA 0x30 /* SD */
1415#define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
1416#define IOPW_SCSI_CTRL 0x34 /* SC */
1417#define IOPW_HSHK_CFG 0x36 /* HCFG */
1418#define IOPW_SXFR_STATUS 0x36 /* SXS */
1419#define IOPW_SXFR_CNTL 0x38 /* SXL */
1420#define IOPW_SXFR_CNTH 0x3A /* SXH */
1da177e4 1421#define IOPW_RES_ADDR_3C 0x3C
27c868c2 1422#define IOPW_RFIFO_DATA 0x3E /* RFD */
1da177e4
LT		 1423
1424/*
1425 * Doubleword I/O register address from base of 'iop_base'.
1426 */
1427#define IOPDW_RES_ADDR_0 0x00
1428#define IOPDW_RAM_DATA 0x04
1429#define IOPDW_RES_ADDR_8 0x08
1430#define IOPDW_RES_ADDR_C 0x0C
1431#define IOPDW_RES_ADDR_10 0x10
1432#define IOPDW_COMMA 0x14
1433#define IOPDW_COMMB 0x18
1434#define IOPDW_RES_ADDR_1C 0x1C
1435#define IOPDW_SDMA_ADDR0 0x20
1436#define IOPDW_SDMA_ADDR1 0x24
1437#define IOPDW_SDMA_COUNT 0x28
1438#define IOPDW_SDMA_ERROR 0x2C
1439#define IOPDW_RDMA_ADDR0 0x30
1440#define IOPDW_RDMA_ADDR1 0x34
1441#define IOPDW_RDMA_COUNT 0x38
1442#define IOPDW_RDMA_ERROR 0x3C
1443
1444#define ADV_CHIP_ID_BYTE 0x25
1445#define ADV_CHIP_ID_WORD 0x04C1
1446
1da177e4
LT		 1447#define ADV_INTR_ENABLE_HOST_INTR 0x01
1448#define ADV_INTR_ENABLE_SEL_INTR 0x02
1449#define ADV_INTR_ENABLE_DPR_INTR 0x04
1450#define ADV_INTR_ENABLE_RTA_INTR 0x08
1451#define ADV_INTR_ENABLE_RMA_INTR 0x10
1452#define ADV_INTR_ENABLE_RST_INTR 0x20
1453#define ADV_INTR_ENABLE_DPE_INTR 0x40
1454#define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
1455
1456#define ADV_INTR_STATUS_INTRA 0x01
1457#define ADV_INTR_STATUS_INTRB 0x02
1458#define ADV_INTR_STATUS_INTRC 0x04
1459
1460#define ADV_RISC_CSR_STOP (0x0000)
1461#define ADV_RISC_TEST_COND (0x2000)
1462#define ADV_RISC_CSR_RUN (0x4000)
1463#define ADV_RISC_CSR_SINGLE_STEP (0x8000)
1464
1465#define ADV_CTRL_REG_HOST_INTR 0x0100
1466#define ADV_CTRL_REG_SEL_INTR 0x0200
1467#define ADV_CTRL_REG_DPR_INTR 0x0400
1468#define ADV_CTRL_REG_RTA_INTR 0x0800
1469#define ADV_CTRL_REG_RMA_INTR 0x1000
1470#define ADV_CTRL_REG_RES_BIT14 0x2000
1471#define ADV_CTRL_REG_DPE_INTR 0x4000
1472#define ADV_CTRL_REG_POWER_DONE 0x8000
1473#define ADV_CTRL_REG_ANY_INTR 0xFF00
1474
1475#define ADV_CTRL_REG_CMD_RESET 0x00C6
1476#define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
1477#define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
1478#define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
1479#define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
1480
1481#define ADV_TICKLE_NOP 0x00
1482#define ADV_TICKLE_A 0x01
1483#define ADV_TICKLE_B 0x02
1484#define ADV_TICKLE_C 0x03
1485
1da177e4
LT		 1486#define AdvIsIntPending(port) \
1487 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
1488
1489/*
1490 * SCSI_CFG0 Register bit definitions
1491 */
27c868c2
MW		 1492#define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
1493#define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
1494#define EVEN_PARITY 0x1000 /* Select Even Parity */
1495#define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
1496#define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
1497#define PRIM_MODE 0x0100 /* Primitive SCSI mode */
1498#define SCAM_EN 0x0080 /* Enable SCAM selection */
1499#define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
1500#define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
1501#define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
1502#define OUR_ID 0x000F /* SCSI ID */
1da177e4
LT		 1503
1504/*
1505 * SCSI_CFG1 Register bit definitions
1506 */
27c868c2
MW		 1507#define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
1508#define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
1509#define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
1510#define FILTER_SEL 0x0C00 /* Filter Period Selection */
1511#define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
1512#define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
1513#define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
1514#define ACTIVE_DBL 0x0200 /* Disable Active Negation */
1515#define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
1516#define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
1517#define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
1518#define TERM_CTL 0x0030 /* External SCSI Termination Bits */
1519#define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
1520#define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
1521#define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
1da177e4
LT		 1522
1523/*
1524 * Addendum for ASC-38C0800 Chip
1525 *
1526 * The ASC-38C1600 Chip uses the same definitions except that the
1527 * bus mode override bits [12:10] have been moved to byte register
1528 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
1529 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
1530 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
1531 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
1532 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
1533 */
27c868c2
MW		 1534#define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
1535#define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
1536#define HVD 0x1000 /* HVD Device Detect */
1537#define LVD 0x0800 /* LVD Device Detect */
1538#define SE 0x0400 /* SE Device Detect */
1539#define TERM_LVD 0x00C0 /* LVD Termination Bits */
1540#define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
1541#define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
1542#define TERM_SE 0x0030 /* SE Termination Bits */
1543#define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
1544#define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
1545#define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
1546#define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
1547#define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
1548#define C_DET_SE 0x0003 /* SE Cable Detect Bits */
1549#define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
1550#define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
1da177e4
LT		 1551
1552#define CABLE_ILLEGAL_A 0x7
1553 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
1554
1555#define CABLE_ILLEGAL_B 0xB
1556 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
1557
1558/*
1559 * MEM_CFG Register bit definitions
1560 */
27c868c2
MW		 1561#define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
1562#define FAST_EE_CLK 0x20 /* Diagnostic Bit */
1563#define RAM_SZ 0x1C /* Specify size of RAM to RISC */
1564#define RAM_SZ_2KB 0x00 /* 2 KB */
1565#define RAM_SZ_4KB 0x04 /* 4 KB */
1566#define RAM_SZ_8KB 0x08 /* 8 KB */
1567#define RAM_SZ_16KB 0x0C /* 16 KB */
1568#define RAM_SZ_32KB 0x10 /* 32 KB */
1569#define RAM_SZ_64KB 0x14 /* 64 KB */
1da177e4
LT		 1570
1571/*
1572 * DMA_CFG0 Register bit definitions
1573 *
1574 * This register is only accessible to the host.
1575 */
27c868c2
MW		 1576#define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
1577#define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
1578#define FIFO_THRESH_16B 0x00 /* 16 bytes */
1579#define FIFO_THRESH_32B 0x20 /* 32 bytes */
1580#define FIFO_THRESH_48B 0x30 /* 48 bytes */
1581#define FIFO_THRESH_64B 0x40 /* 64 bytes */
1582#define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
1583#define FIFO_THRESH_96B 0x60 /* 96 bytes */
1584#define FIFO_THRESH_112B 0x70 /* 112 bytes */
1585#define START_CTL 0x0C /* DMA start conditions */
1586#define START_CTL_TH 0x00 /* Wait threshold level (default) */
1587#define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
1588#define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
1589#define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
1590#define READ_CMD 0x03 /* Memory Read Method */
1591#define READ_CMD_MR 0x00 /* Memory Read */
1592#define READ_CMD_MRL 0x02 /* Memory Read Long */
1593#define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
1da177e4
LT		 1594
1595/*
1596 * ASC-38C0800 RAM BIST Register bit definitions
1597 */
1598#define RAM_TEST_MODE 0x80
1599#define PRE_TEST_MODE 0x40
1600#define NORMAL_MODE 0x00
1601#define RAM_TEST_DONE 0x10
1602#define RAM_TEST_STATUS 0x0F
1603#define RAM_TEST_HOST_ERROR 0x08
1604#define RAM_TEST_INTRAM_ERROR 0x04
1605#define RAM_TEST_RISC_ERROR 0x02
1606#define RAM_TEST_SCSI_ERROR 0x01
1607#define RAM_TEST_SUCCESS 0x00
1608#define PRE_TEST_VALUE 0x05
1609#define NORMAL_VALUE 0x00
1610
1611/*
1612 * ASC38C1600 Definitions
1613 *
1614 * IOPB_PCI_INT_CFG Bit Field Definitions
1615 */
1616
27c868c2 1617#define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
1da177e4
LT		 1618
1619/*
1620 * Bit 1 can be set to change the interrupt for the Function to operate in
1621 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
1622 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
1623 * mode, otherwise the operating mode is undefined.
1624 */
1625#define TOTEMPOLE 0x02
1626
1627/*
1628 * Bit 0 can be used to change the Int Pin for the Function. The value is
1629 * 0 by default for both Functions with Function 0 using INT A and Function
1630 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
1631 * INT A is used.
1632 *
1633 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
1634 * value specified in the PCI Configuration Space.
1635 */
1636#define INTAB 0x01
1637
1da177e4
LT		 1638/*
1639 * Adv Library Status Definitions
1640 */
1641#define ADV_TRUE 1
1642#define ADV_FALSE 0
1da177e4
LT		 1643#define ADV_SUCCESS 1
1644#define ADV_BUSY 0
1645#define ADV_ERROR (-1)
1646
1da177e4
LT		 1647/*
1648 * ADV_DVC_VAR 'warn_code' values
1649 */
27c868c2
MW		 1650#define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
1651#define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
1652#define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
27c868c2 1653#define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
1da177e4 1654
27c868c2
MW		 1655#define ADV_MAX_TID 15 /* max. target identifier */
1656#define ADV_MAX_LUN 7 /* max. logical unit number */
1da177e4 1657
1da177e4
LT		 1658/*
1659 * Fixed locations of microcode operating variables.
1660 */
27c868c2
MW		 1661#define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
1662#define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
1663#define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
1664#define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
1665#define ASC_MC_VERSION_NUM 0x003A /* microcode number */
1666#define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
1667#define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
1668#define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
1669#define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
1670#define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
1671#define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
1672#define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
1673#define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
1da177e4
LT		 1674#define ASC_MC_CHIP_TYPE 0x009A
1675#define ASC_MC_INTRB_CODE 0x009B
1676#define ASC_MC_WDTR_ABLE 0x009C
1677#define ASC_MC_SDTR_ABLE 0x009E
1678#define ASC_MC_TAGQNG_ABLE 0x00A0
1679#define ASC_MC_DISC_ENABLE 0x00A2
1680#define ASC_MC_IDLE_CMD_STATUS 0x00A4
1681#define ASC_MC_IDLE_CMD 0x00A6
1682#define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
1683#define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
1684#define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
1685#define ASC_MC_DEFAULT_MEM_CFG 0x00B0
1686#define ASC_MC_DEFAULT_SEL_MASK 0x00B2
1687#define ASC_MC_SDTR_DONE 0x00B6
1688#define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
1689#define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
1690#define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
27c868c2 1691#define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
1da177e4 1692#define ASC_MC_WDTR_DONE 0x0124
27c868c2 1693#define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
1da177e4
LT		 1694#define ASC_MC_ICQ 0x0160
1695#define ASC_MC_IRQ 0x0164
1696#define ASC_MC_PPR_ABLE 0x017A
1697
1698/*
1699 * BIOS LRAM variable absolute offsets.
1700 */
1701#define BIOS_CODESEG 0x54
1702#define BIOS_CODELEN 0x56
1703#define BIOS_SIGNATURE 0x58
1704#define BIOS_VERSION 0x5A
1705
1706/*
1707 * Microcode Control Flags
1708 *
1709 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
1710 * and handled by the microcode.
1711 */
27c868c2
MW		 1712#define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
1713#define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
1da177e4
LT		 1714
1715/*
1716 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
1717 */
1718#define HSHK_CFG_WIDE_XFR 0x8000
1719#define HSHK_CFG_RATE 0x0F00
1720#define HSHK_CFG_OFFSET 0x001F
1721
27c868c2
MW		 1722#define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
1723#define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
1724#define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
1725#define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
1726
1727#define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
1728#define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
1729#define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
1730#define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
1731#define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
1732
1733#define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
1734#define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
1735#define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
1736#define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
1737#define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
1da177e4
LT		 1738/*
1739 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
1740 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
1741 */
27c868c2
MW		 1742#define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
1743#define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
1da177e4
LT		 1744
1745/*
1746 * All fields here are accessed by the board microcode and need to be
1747 * little-endian.
1748 */
27c868c2
MW		 1749typedef struct adv_carr_t {
1750 ADV_VADDR carr_va; /* Carrier Virtual Address */
1751 ADV_PADDR carr_pa; /* Carrier Physical Address */
1752 ADV_VADDR areq_vpa; /* ASC_SCSI_REQ_Q Virtual or Physical Address */
1753 /*
1754 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer
1755 *
1756 * next_vpa [3:1] Reserved Bits
1757 * next_vpa [0] Done Flag set in Response Queue.
1758 */
1759 ADV_VADDR next_vpa;
1da177e4
LT		 1760} ADV_CARR_T;
1761
1762/*
1763 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
1764 */
1765#define ASC_NEXT_VPA_MASK 0xFFFFFFF0
1766
1767#define ASC_RQ_DONE 0x00000001
1768#define ASC_RQ_GOOD 0x00000002
1769#define ASC_CQ_STOPPER 0x00000000
1770
1771#define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
1772
1773#define ADV_CARRIER_NUM_PAGE_CROSSING \
fd625f47 1774 (((ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) + (PAGE_SIZE - 1))/PAGE_SIZE)
1da177e4
LT		 1775
1776#define ADV_CARRIER_BUFSIZE \
1777 ((ADV_CARRIER_COUNT + ADV_CARRIER_NUM_PAGE_CROSSING) * sizeof(ADV_CARR_T))
1778
1779/*
1780 * ASC_SCSI_REQ_Q 'a_flag' definitions
1781 *
1782 * The Adv Library should limit use to the lower nibble (4 bits) of
1783 * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
1784 */
27c868c2
MW		 1785#define ADV_POLL_REQUEST 0x01 /* poll for request completion */
1786#define ADV_SCSIQ_DONE 0x02 /* request done */
1787#define ADV_DONT_RETRY 0x08 /* don't do retry */
1da177e4 1788
27c868c2
MW		 1789#define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
1790#define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
1791#define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
1da177e4
LT		 1792
1793/*
1794 * Adapter temporary configuration structure
1795 *
1796 * This structure can be discarded after initialization. Don't add
1797 * fields here needed after initialization.
1798 *
1799 * Field naming convention:
1800 *
1801 * *_enable indicates the field enables or disables a feature. The
1802 * value of the field is never reset.
1803 */
1804typedef struct adv_dvc_cfg {
27c868c2
MW		 1805 ushort disc_enable; /* enable disconnection */
1806 uchar chip_version; /* chip version */
1807 uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
27c868c2
MW		 1808 ushort control_flag; /* Microcode Control Flag */
1809 ushort mcode_date; /* Microcode date */
1810 ushort mcode_version; /* Microcode version */
27c868c2
MW		 1811 ushort serial1; /* EEPROM serial number word 1 */
1812 ushort serial2; /* EEPROM serial number word 2 */
1813 ushort serial3; /* EEPROM serial number word 3 */
1da177e4
LT		 1814} ADV_DVC_CFG;
1815
1816struct adv_dvc_var;
1817struct adv_scsi_req_q;
1818
1da177e4 1819typedef struct asc_sg_block {
27c868c2
MW		 1820 uchar reserved1;
1821 uchar reserved2;
1822 uchar reserved3;
1823 uchar sg_cnt; /* Valid entries in block. */
1824 ADV_PADDR sg_ptr; /* Pointer to next sg block. */
1825 struct {
1826 ADV_PADDR sg_addr; /* SG element address. */
1827 ADV_DCNT sg_count; /* SG element count. */
1828 } sg_list[NO_OF_SG_PER_BLOCK];
1da177e4
LT		 1829} ADV_SG_BLOCK;
1830
1831/*
1832 * ADV_SCSI_REQ_Q - microcode request structure
1833 *
1834 * All fields in this structure up to byte 60 are used by the microcode.
1835 * The microcode makes assumptions about the size and ordering of fields
1836 * in this structure. Do not change the structure definition here without
1837 * coordinating the change with the microcode.
1838 *
1839 * All fields accessed by microcode must be maintained in little_endian
1840 * order.
1841 */
1842typedef struct adv_scsi_req_q {
27c868c2
MW		 1843 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
1844 uchar target_cmd;
1845 uchar target_id; /* Device target identifier. */
1846 uchar target_lun; /* Device target logical unit number. */
1847 ADV_PADDR data_addr; /* Data buffer physical address. */
1848 ADV_DCNT data_cnt; /* Data count. Ucode sets to residual. */
1849 ADV_PADDR sense_addr;
1850 ADV_PADDR carr_pa;
1851 uchar mflag;
1852 uchar sense_len;
1853 uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
1854 uchar scsi_cntl;
1855 uchar done_status; /* Completion status. */
1856 uchar scsi_status; /* SCSI status byte. */
1857 uchar host_status; /* Ucode host status. */
1858 uchar sg_working_ix;
1859 uchar cdb[12]; /* SCSI CDB bytes 0-11. */
1860 ADV_PADDR sg_real_addr; /* SG list physical address. */
1861 ADV_PADDR scsiq_rptr;
1862 uchar cdb16[4]; /* SCSI CDB bytes 12-15. */
1863 ADV_VADDR scsiq_ptr;
1864 ADV_VADDR carr_va;
1865 /*
1866 * End of microcode structure - 60 bytes. The rest of the structure
1867 * is used by the Adv Library and ignored by the microcode.
1868 */
1869 ADV_VADDR srb_ptr;
1870 ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
1871 char *vdata_addr; /* Data buffer virtual address. */
1872 uchar a_flag;
1873 uchar pad[2]; /* Pad out to a word boundary. */
1da177e4
LT		 1874} ADV_SCSI_REQ_Q;
1875
98d41c29
MW		 1876/*
1877 * The following two structures are used to process Wide Board requests.
1878 *
1879 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
1880 * and microcode with the ADV_SCSI_REQ_Q field 'srb_ptr' pointing to the
1881 * adv_req_t. The adv_req_t structure 'cmndp' field in turn points to the
1882 * Mid-Level SCSI request structure.
1883 *
1884 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
1885 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
1886 * up to 255 scatter-gather elements may be used per request or
1887 * ADV_SCSI_REQ_Q.
1888 *
1889 * Both structures must be 32 byte aligned.
1890 */
1891typedef struct adv_sgblk {
1892 ADV_SG_BLOCK sg_block; /* Sgblock structure. */
1893 uchar align[32]; /* Sgblock structure padding. */
1894 struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */
1895} adv_sgblk_t;
1896
1897typedef struct adv_req {
1898 ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */
1899 uchar align[32]; /* Request structure padding. */
1900 struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */
1901 adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */
1902 struct adv_req *next_reqp; /* Next Request Structure. */
1903} adv_req_t;
1904
1905/*
1906 * Adapter operation variable structure.
1907 *
1908 * One structure is required per host adapter.
1909 *
1910 * Field naming convention:
1911 *
1912 * *_able indicates both whether a feature should be enabled or disabled
1913 * and whether a device isi capable of the feature. At initialization
1914 * this field may be set, but later if a device is found to be incapable
1915 * of the feature, the field is cleared.
1916 */
1917typedef struct adv_dvc_var {
1918 AdvPortAddr iop_base; /* I/O port address */
1919 ushort err_code; /* fatal error code */
1920 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
1921 ushort wdtr_able; /* try WDTR for a device */
1922 ushort sdtr_able; /* try SDTR for a device */
1923 ushort ultra_able; /* try SDTR Ultra speed for a device */
1924 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
1925 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
1926 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
1927 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
1928 ushort tagqng_able; /* try tagged queuing with a device */
1929 ushort ppr_able; /* PPR message capable per TID bitmask. */
1930 uchar max_dvc_qng; /* maximum number of tagged commands per device */
1931 ushort start_motor; /* start motor command allowed */
1932 uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */
1933 uchar chip_no; /* should be assigned by caller */
1934 uchar max_host_qng; /* maximum number of Q'ed command allowed */
1935 ushort no_scam; /* scam_tolerant of EEPROM */
1936 struct asc_board *drv_ptr; /* driver pointer to private structure */
1937 uchar chip_scsi_id; /* chip SCSI target ID */
1938 uchar chip_type;
1939 uchar bist_err_code;
1940 ADV_CARR_T *carrier_buf;
1941 ADV_CARR_T *carr_freelist; /* Carrier free list. */
1942 ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */
1943 ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */
1944 ushort carr_pending_cnt; /* Count of pending carriers. */
1945 struct adv_req *orig_reqp; /* adv_req_t memory block. */
1946 /*
1947 * Note: The following fields will not be used after initialization. The
1948 * driver may discard the buffer after initialization is done.
1949 */
1950 ADV_DVC_CFG *cfg; /* temporary configuration structure */
1951} ADV_DVC_VAR;
1952
1da177e4
LT		 1953/*
1954 * Microcode idle loop commands
1955 */
1956#define IDLE_CMD_COMPLETED 0
1957#define IDLE_CMD_STOP_CHIP 0x0001
1958#define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
1959#define IDLE_CMD_SEND_INT 0x0004
1960#define IDLE_CMD_ABORT 0x0008
1961#define IDLE_CMD_DEVICE_RESET 0x0010
27c868c2
MW		 1962#define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
1963#define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
1da177e4
LT		 1964#define IDLE_CMD_SCSIREQ 0x0080
1965
1966#define IDLE_CMD_STATUS_SUCCESS 0x0001
1967#define IDLE_CMD_STATUS_FAILURE 0x0002
1968
1969/*
1970 * AdvSendIdleCmd() flag definitions.
1971 */
1972#define ADV_NOWAIT 0x01
1973
1974/*
1975 * Wait loop time out values.
1976 */
27c868c2
MW		 1977#define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
1978#define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
27c868c2 1979#define SCSI_MAX_RETRY 10 /* retry count */
1da177e4 1980
27c868c2
MW		 1981#define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
1982#define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
1983#define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
1984#define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
1da177e4 1985
27c868c2 1986#define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
1da177e4 1987
1da177e4
LT		 1988/* Read byte from a register. */
1989#define AdvReadByteRegister(iop_base, reg_off) \
1990 (ADV_MEM_READB((iop_base) + (reg_off)))
1991
1992/* Write byte to a register. */
1993#define AdvWriteByteRegister(iop_base, reg_off, byte) \
1994 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
1995
1996/* Read word (2 bytes) from a register. */
1997#define AdvReadWordRegister(iop_base, reg_off) \
1998 (ADV_MEM_READW((iop_base) + (reg_off)))
1999
2000/* Write word (2 bytes) to a register. */
2001#define AdvWriteWordRegister(iop_base, reg_off, word) \
2002 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
2003
2004/* Write dword (4 bytes) to a register. */
2005#define AdvWriteDWordRegister(iop_base, reg_off, dword) \
2006 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
2007
2008/* Read byte from LRAM. */
2009#define AdvReadByteLram(iop_base, addr, byte) \
2010do { \
2011 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2012 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
2013} while (0)
2014
2015/* Write byte to LRAM. */
2016#define AdvWriteByteLram(iop_base, addr, byte) \
2017 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2018 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
2019
2020/* Read word (2 bytes) from LRAM. */
2021#define AdvReadWordLram(iop_base, addr, word) \
2022do { \
2023 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
2024 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
2025} while (0)
2026
2027/* Write word (2 bytes) to LRAM. */
2028#define AdvWriteWordLram(iop_base, addr, word) \
2029 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2030 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2031
2032/* Write little-endian double word (4 bytes) to LRAM */
2033/* Because of unspecified C language ordering don't use auto-increment. */
2034#define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
2035 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
2036 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2037 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
2038 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
2039 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
2040 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
2041
2042/* Read word (2 bytes) from LRAM assuming that the address is already set. */
2043#define AdvReadWordAutoIncLram(iop_base) \
2044 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
2045
2046/* Write word (2 bytes) to LRAM assuming that the address is already set. */
2047#define AdvWriteWordAutoIncLram(iop_base, word) \
2048 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
2049
1da177e4
LT		 2050/*
2051 * Define macro to check for Condor signature.
2052 *
2053 * Evaluate to ADV_TRUE if a Condor chip is found the specified port
2054 * address 'iop_base'. Otherwise evalue to ADV_FALSE.
2055 */
2056#define AdvFindSignature(iop_base) \
2057 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
2058 ADV_CHIP_ID_BYTE) && \
2059 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
2060 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
2061
2062/*
2063 * Define macro to Return the version number of the chip at 'iop_base'.
2064 *
2065 * The second parameter 'bus_type' is currently unused.
2066 */
2067#define AdvGetChipVersion(iop_base, bus_type) \
2068 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
2069
2070/*
2071 * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must
2072 * match the ASC_SCSI_REQ_Q 'srb_ptr' field.
2073 *
2074 * If the request has not yet been sent to the device it will simply be
2075 * aborted from RISC memory. If the request is disconnected it will be
2076 * aborted on reselection by sending an Abort Message to the target ID.
2077 *
2078 * Return value:
2079 * ADV_TRUE(1) - Queue was successfully aborted.
2080 * ADV_FALSE(0) - Queue was not found on the active queue list.
2081 */
2082#define AdvAbortQueue(asc_dvc, scsiq) \
2083 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
2084 (ADV_DCNT) (scsiq))
2085
2086/*
2087 * Send a Bus Device Reset Message to the specified target ID.
2088 *
2089 * All outstanding commands will be purged if sending the
2090 * Bus Device Reset Message is successful.
2091 *
2092 * Return Value:
2093 * ADV_TRUE(1) - All requests on the target are purged.
2094 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
2095 * are not purged.
2096 */
2097#define AdvResetDevice(asc_dvc, target_id) \
2098 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
2099 (ADV_DCNT) (target_id))
2100
2101/*
2102 * SCSI Wide Type definition.
2103 */
2104#define ADV_SCSI_BIT_ID_TYPE ushort
2105
2106/*
2107 * AdvInitScsiTarget() 'cntl_flag' options.
2108 */
2109#define ADV_SCAN_LUN 0x01
2110#define ADV_CAPINFO_NOLUN 0x02
2111
2112/*
2113 * Convert target id to target id bit mask.
2114 */
2115#define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
2116
2117/*
2118 * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
2119 */
2120
27c868c2 2121#define QD_NO_STATUS 0x00 /* Request not completed yet. */
1da177e4
LT		 2122#define QD_NO_ERROR 0x01
2123#define QD_ABORTED_BY_HOST 0x02
2124#define QD_WITH_ERROR 0x04
2125
2126#define QHSTA_NO_ERROR 0x00
2127#define QHSTA_M_SEL_TIMEOUT 0x11
2128#define QHSTA_M_DATA_OVER_RUN 0x12
2129#define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
2130#define QHSTA_M_QUEUE_ABORTED 0x15
27c868c2
MW		 2131#define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
2132#define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
2133#define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
2134#define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
2135#define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
2136#define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
2137#define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
1da177e4 2138/* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
27c868c2
MW		 2139#define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
2140#define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
2141#define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
2142#define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
2143#define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
2144#define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
2145#define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
2146#define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
1da177e4
LT		 2147#define QHSTA_M_WTM_TIMEOUT 0x41
2148#define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
2149#define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
2150#define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
27c868c2
MW		 2151#define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
2152#define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
2153#define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
1da177e4 2154
1da177e4
LT		 2155/* Return the address that is aligned at the next doubleword >= to 'addr'. */
2156#define ADV_8BALIGN(addr) (((ulong) (addr) + 0x7) & ~0x7)
2157#define ADV_16BALIGN(addr) (((ulong) (addr) + 0xF) & ~0xF)
2158#define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F)
2159
2160/*
2161 * Total contiguous memory needed for driver SG blocks.
2162 *
2163 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
2164 * number of scatter-gather elements the driver supports in a
2165 * single request.
2166 */
2167
2168#define ADV_SG_LIST_MAX_BYTE_SIZE \
2169 (sizeof(ADV_SG_BLOCK) * \
2170 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
2171
d2411495 2172/* struct asc_board flags */
27c868c2 2173#define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */
1da177e4
LT		 2174
2175#define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
1da177e4 2176
27c868c2 2177#define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */
1da177e4 2178
27c868c2 2179#define ASC_INFO_SIZE 128 /* advansys_info() line size */
1da177e4 2180
1da177e4
LT		 2181/* Asc Library return codes */
2182#define ASC_TRUE 1
2183#define ASC_FALSE 0
2184#define ASC_NOERROR 1
2185#define ASC_BUSY 0
2186#define ASC_ERROR (-1)
2187
2188/* struct scsi_cmnd function return codes */
2189#define STATUS_BYTE(byte) (byte)
2190#define MSG_BYTE(byte) ((byte) << 8)
2191#define HOST_BYTE(byte) ((byte) << 16)
2192#define DRIVER_BYTE(byte) ((byte) << 24)
2193
d2411495 2194#define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1)
1da177e4 2195#ifndef ADVANSYS_STATS
27c868c2 2196#define ASC_STATS_ADD(shost, counter, count)
1da177e4 2197#else /* ADVANSYS_STATS */
27c868c2 2198#define ASC_STATS_ADD(shost, counter, count) \
d2411495 2199 (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count))
1da177e4
LT		 2200#endif /* ADVANSYS_STATS */
2201
1da177e4
LT		 2202/* If the result wraps when calculating tenths, return 0. */
2203#define ASC_TENTHS(num, den) \
2204 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
2205 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
2206
2207/*
2208 * Display a message to the console.
2209 */
2210#define ASC_PRINT(s) \
2211 { \
2212 printk("advansys: "); \
2213 printk(s); \
2214 }
2215
2216#define ASC_PRINT1(s, a1) \
2217 { \
2218 printk("advansys: "); \
2219 printk((s), (a1)); \
2220 }
2221
2222#define ASC_PRINT2(s, a1, a2) \
2223 { \
2224 printk("advansys: "); \
2225 printk((s), (a1), (a2)); \
2226 }
2227
2228#define ASC_PRINT3(s, a1, a2, a3) \
2229 { \
2230 printk("advansys: "); \
2231 printk((s), (a1), (a2), (a3)); \
2232 }
2233
2234#define ASC_PRINT4(s, a1, a2, a3, a4) \
2235 { \
2236 printk("advansys: "); \
2237 printk((s), (a1), (a2), (a3), (a4)); \
2238 }
2239
1da177e4
LT		 2240#ifndef ADVANSYS_DEBUG
2241
b352f923 2242#define ASC_DBG(lvl, s...)
1da177e4 2243#define ASC_DBG_PRT_SCSI_HOST(lvl, s)
1da177e4
LT		 2244#define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
2245#define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2246#define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
2247#define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2248#define ASC_DBG_PRT_HEX(lvl, name, start, length)
2249#define ASC_DBG_PRT_CDB(lvl, cdb, len)
2250#define ASC_DBG_PRT_SENSE(lvl, sense, len)
2251#define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
2252
2253#else /* ADVANSYS_DEBUG */
2254
2255/*
2256 * Debugging Message Levels:
2257 * 0: Errors Only
2258 * 1: High-Level Tracing
2259 * 2-N: Verbose Tracing
2260 */
2261
b352f923
MW		 2262#define ASC_DBG(lvl, format, arg...) { \
2263 if (asc_dbglvl >= (lvl)) \
2264 printk(KERN_DEBUG "%s: %s: " format, DRV_NAME, \
cadbd4a5 2265 __func__ , ## arg); \
b352f923 2266}
1da177e4
LT		 2267
2268#define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
2269 { \
2270 if (asc_dbglvl >= (lvl)) { \
2271 asc_prt_scsi_host(s); \
2272 } \
2273 }
2274
1da177e4
LT		 2275#define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
2276 { \
2277 if (asc_dbglvl >= (lvl)) { \
2278 asc_prt_asc_scsi_q(scsiqp); \
2279 } \
2280 }
2281
2282#define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
2283 { \
2284 if (asc_dbglvl >= (lvl)) { \
2285 asc_prt_asc_qdone_info(qdone); \
2286 } \
2287 }
2288
2289#define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
2290 { \
2291 if (asc_dbglvl >= (lvl)) { \
2292 asc_prt_adv_scsi_req_q(scsiqp); \
2293 } \
2294 }
2295
2296#define ASC_DBG_PRT_HEX(lvl, name, start, length) \
2297 { \
2298 if (asc_dbglvl >= (lvl)) { \
2299 asc_prt_hex((name), (start), (length)); \
2300 } \
2301 }
2302
2303#define ASC_DBG_PRT_CDB(lvl, cdb, len) \
2304 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
2305
2306#define ASC_DBG_PRT_SENSE(lvl, sense, len) \
2307 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
2308
2309#define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
2310 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
2311#endif /* ADVANSYS_DEBUG */
2312
1da177e4
LT		 2313#ifdef ADVANSYS_STATS
2314
2315/* Per board statistics structure */
2316struct asc_stats {
27c868c2
MW		 2317 /* Driver Entrypoint Statistics */
2318 ADV_DCNT queuecommand; /* # calls to advansys_queuecommand() */
2319 ADV_DCNT reset; /* # calls to advansys_eh_bus_reset() */
2320 ADV_DCNT biosparam; /* # calls to advansys_biosparam() */
2321 ADV_DCNT interrupt; /* # advansys_interrupt() calls */
2322 ADV_DCNT callback; /* # calls to asc/adv_isr_callback() */
2323 ADV_DCNT done; /* # calls to request's scsi_done function */
2324 ADV_DCNT build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
2325 ADV_DCNT adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
2326 ADV_DCNT adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
2327 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
2328 ADV_DCNT exe_noerror; /* # ASC_NOERROR returns. */
2329 ADV_DCNT exe_busy; /* # ASC_BUSY returns. */
2330 ADV_DCNT exe_error; /* # ASC_ERROR returns. */
2331 ADV_DCNT exe_unknown; /* # unknown returns. */
2332 /* Data Transfer Statistics */
52c334e9
MW		 2333 ADV_DCNT xfer_cnt; /* # I/O requests received */
2334 ADV_DCNT xfer_elem; /* # scatter-gather elements */
2335 ADV_DCNT xfer_sect; /* # 512-byte blocks */
1da177e4
LT		 2336};
2337#endif /* ADVANSYS_STATS */
2338
1da177e4
LT		 2339/*
2340 * Structure allocated for each board.
2341 *
8dfb5379 2342 * This structure is allocated by scsi_host_alloc() at the end
1da177e4
LT		 2343 * of the 'Scsi_Host' structure starting at the 'hostdata'
2344 * field. It is guaranteed to be allocated from DMA-able memory.
2345 */
d2411495 2346struct asc_board {
394dbf3f 2347 struct device *dev;
27c868c2 2348 uint flags; /* Board flags */
d361db48 2349 unsigned int irq;
27c868c2
MW		 2350 union {
2351 ASC_DVC_VAR asc_dvc_var; /* Narrow board */
2352 ADV_DVC_VAR adv_dvc_var; /* Wide board */
2353 } dvc_var;
2354 union {
2355 ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */
2356 ADV_DVC_CFG adv_dvc_cfg; /* Wide board */
2357 } dvc_cfg;
2358 ushort asc_n_io_port; /* Number I/O ports. */
27c868c2 2359 ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */
27c868c2
MW		 2360 ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
2361 ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */
2362 ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
2363 union {
2364 ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */
2365 ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */
2366 ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */
2367 ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */
2368 } eep_config;
27c868c2 2369 /* /proc/scsi/advansys/[0...] */
1da177e4 2370#ifdef ADVANSYS_STATS
27c868c2
MW		 2371 struct asc_stats asc_stats; /* Board statistics */
2372#endif /* ADVANSYS_STATS */
2373 /*
2374 * The following fields are used only for Narrow Boards.
2375 */
27c868c2
MW		 2376 uchar sdtr_data[ASC_MAX_TID + 1]; /* SDTR information */
2377 /*
2378 * The following fields are used only for Wide Boards.
2379 */
2380 void __iomem *ioremap_addr; /* I/O Memory remap address. */
2381 ushort ioport; /* I/O Port address. */
27c868c2
MW		 2382 adv_req_t *adv_reqp; /* Request structures. */
2383 adv_sgblk_t *adv_sgblkp; /* Scatter-gather structures. */
2384 ushort bios_signature; /* BIOS Signature. */
2385 ushort bios_version; /* BIOS Version. */
2386 ushort bios_codeseg; /* BIOS Code Segment. */
2387 ushort bios_codelen; /* BIOS Code Segment Length. */
d2411495 2388};
1da177e4 2389
d10fb2c7
MW		 2390#define asc_dvc_to_board(asc_dvc) container_of(asc_dvc, struct asc_board, \
2391 dvc_var.asc_dvc_var)
13ac2d9c
MW		 2392#define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
2393 dvc_var.adv_dvc_var)
2394#define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
2395
1da177e4 2396#ifdef ADVANSYS_DEBUG
27c868c2 2397static int asc_dbglvl = 3;
1da177e4 2398
1da177e4 2399/*
51219358 2400 * asc_prt_asc_dvc_var()
1da177e4 2401 */
51219358 2402static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
1da177e4 2403{
51219358 2404 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
27c868c2 2405
51219358
MW		 2406 printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
2407 "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
2408
2409 printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
2410 (unsigned)h->init_sdtr);
2411
2412 printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
2413 "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
2414 (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
2415 (unsigned)h->chip_no);
2416
2417 printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
2418 "%u,\n", (unsigned)h->queue_full_or_busy,
2419 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2420
2421 printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
2422 "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
2423 (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
2424 (unsigned)h->in_critical_cnt);
2425
2426 printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
2427 "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
2428 (unsigned)h->init_state, (unsigned)h->no_scam,
2429 (unsigned)h->pci_fix_asyn_xfer);
2430
d361db48 2431 printk(" cfg 0x%lx\n", (ulong)h->cfg);
1da177e4
LT		 2432}
2433
51219358
MW		 2434/*
2435 * asc_prt_asc_dvc_cfg()
2436 */
2437static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
6ed1ef07 2438{
51219358 2439 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
6ed1ef07 2440
51219358
MW		 2441 printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
2442 h->can_tagged_qng, h->cmd_qng_enabled);
2443 printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
2444 h->disc_enable, h->sdtr_enable);
6ed1ef07 2445
b08fc565
MW		 2446 printk(" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, "
2447 "chip_version %d,\n", h->chip_scsi_id, h->isa_dma_speed,
2448 h->isa_dma_channel, h->chip_version);
51219358 2449
d10fb2c7
MW		 2450 printk(" mcode_date 0x%x, mcode_version %d\n",
2451 h->mcode_date, h->mcode_version);
6ed1ef07
MW		 2452}
2453
1da177e4 2454/*
51219358 2455 * asc_prt_adv_dvc_var()
1da177e4 2456 *
51219358 2457 * Display an ADV_DVC_VAR structure.
1da177e4 2458 */
51219358 2459static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
1da177e4 2460{
51219358 2461 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
27c868c2 2462
51219358
MW		 2463 printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
2464 (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
1da177e4 2465
b352f923
MW		 2466 printk(" sdtr_able 0x%x, wdtr_able 0x%x\n",
2467 (unsigned)h->sdtr_able, (unsigned)h->wdtr_able);
1da177e4 2468
d361db48
MW		 2469 printk(" start_motor 0x%x, scsi_reset_wait 0x%x\n",
2470 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
1da177e4 2471
51219358
MW		 2472 printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%lxn\n",
2473 (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
2474 (ulong)h->carr_freelist);
1da177e4 2475
51219358
MW		 2476 printk(" icq_sp 0x%lx, irq_sp 0x%lx\n",
2477 (ulong)h->icq_sp, (ulong)h->irq_sp);
1da177e4 2478
51219358
MW		 2479 printk(" no_scam 0x%x, tagqng_able 0x%x\n",
2480 (unsigned)h->no_scam, (unsigned)h->tagqng_able);
1da177e4 2481
51219358
MW		 2482 printk(" chip_scsi_id 0x%x, cfg 0x%lx\n",
2483 (unsigned)h->chip_scsi_id, (ulong)h->cfg);
2484}
1da177e4 2485
51219358
MW		 2486/*
2487 * asc_prt_adv_dvc_cfg()
2488 *
2489 * Display an ADV_DVC_CFG structure.
2490 */
2491static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
2492{
2493 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
27c868c2 2494
51219358
MW		 2495 printk(" disc_enable 0x%x, termination 0x%x\n",
2496 h->disc_enable, h->termination);
1da177e4 2497
51219358
MW		 2498 printk(" chip_version 0x%x, mcode_date 0x%x\n",
2499 h->chip_version, h->mcode_date);
27c868c2 2500
b352f923
MW		 2501 printk(" mcode_version 0x%x, control_flag 0x%x\n",
2502 h->mcode_version, h->control_flag);
1da177e4
LT		 2503}
2504
2505/*
b352f923 2506 * asc_prt_scsi_host()
1da177e4 2507 */
b352f923 2508static void asc_prt_scsi_host(struct Scsi_Host *s)
1da177e4 2509{
b352f923 2510 struct asc_board *boardp = shost_priv(s);
51219358 2511
71610f55 2512 printk("Scsi_Host at addr 0x%p, device %s\n", s, dev_name(boardp->dev));
50d14a70 2513 printk(" host_busy %u, host_no %d,\n",
74665016 2514 atomic_read(&s->host_busy), s->host_no);
51219358 2515
b352f923
MW		 2516 printk(" base 0x%lx, io_port 0x%lx, irq %d,\n",
2517 (ulong)s->base, (ulong)s->io_port, boardp->irq);
51219358 2518
b352f923
MW		 2519 printk(" dma_channel %d, this_id %d, can_queue %d,\n",
2520 s->dma_channel, s->this_id, s->can_queue);
1da177e4 2521
b352f923
MW		 2522 printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
2523 s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
27c868c2 2524
b352f923
MW		 2525 if (ASC_NARROW_BOARD(boardp)) {
2526 asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var);
2527 asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg);
2528 } else {
2529 asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var);
2530 asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg);
074c8fe4 2531 }
1da177e4
LT		 2532}
2533
51219358
MW		 2534/*
2535 * asc_prt_hex()
2536 *
2537 * Print hexadecimal output in 4 byte groupings 32 bytes
2538 * or 8 double-words per line.
2539 */
2540static void asc_prt_hex(char *f, uchar *s, int l)
47d853cc 2541{
51219358
MW		 2542 int i;
2543 int j;
2544 int k;
2545 int m;
47d853cc 2546
51219358
MW		 2547 printk("%s: (%d bytes)\n", f, l);
2548
2549 for (i = 0; i < l; i += 32) {
2550
2551 /* Display a maximum of 8 double-words per line. */
2552 if ((k = (l - i) / 4) >= 8) {
2553 k = 8;
2554 m = 0;
47d853cc 2555 } else {
51219358 2556 m = (l - i) % 4;
47d853cc
MW		 2557 }
2558
51219358
MW		 2559 for (j = 0; j < k; j++) {
2560 printk(" %2.2X%2.2X%2.2X%2.2X",
2561 (unsigned)s[i + (j * 4)],
2562 (unsigned)s[i + (j * 4) + 1],
2563 (unsigned)s[i + (j * 4) + 2],
2564 (unsigned)s[i + (j * 4) + 3]);
47d853cc 2565 }
47d853cc 2566
51219358
MW		 2567 switch (m) {
2568 case 0:
2569 default:
2570 break;
2571 case 1:
2572 printk(" %2.2X", (unsigned)s[i + (j * 4)]);
2573 break;
2574 case 2:
2575 printk(" %2.2X%2.2X",
2576 (unsigned)s[i + (j * 4)],
2577 (unsigned)s[i + (j * 4) + 1]);
2578 break;
2579 case 3:
2580 printk(" %2.2X%2.2X%2.2X",
2581 (unsigned)s[i + (j * 4) + 1],
2582 (unsigned)s[i + (j * 4) + 2],
2583 (unsigned)s[i + (j * 4) + 3]);
2584 break;
2585 }
47d853cc 2586
51219358 2587 printk("\n");
47d853cc
MW		 2588 }
2589}
b352f923
MW		 2590
2591/*
2592 * asc_prt_asc_scsi_q()
2593 */
2594static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
2595{
2596 ASC_SG_HEAD *sgp;
2597 int i;
2598
2599 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
2600
2601 printk
2602 (" target_ix 0x%x, target_lun %u, srb_ptr 0x%lx, tag_code 0x%x,\n",
2603 q->q2.target_ix, q->q1.target_lun, (ulong)q->q2.srb_ptr,
2604 q->q2.tag_code);
2605
2606 printk
2607 (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2608 (ulong)le32_to_cpu(q->q1.data_addr),
2609 (ulong)le32_to_cpu(q->q1.data_cnt),
2610 (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
2611
2612 printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
2613 (ulong)q->cdbptr, q->q2.cdb_len,
2614 (ulong)q->sg_head, q->q1.sg_queue_cnt);
2615
2616 if (q->sg_head) {
2617 sgp = q->sg_head;
2618 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
2619 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
2620 sgp->queue_cnt);
2621 for (i = 0; i < sgp->entry_cnt; i++) {
2622 printk(" [%u]: addr 0x%lx, bytes %lu\n",
2623 i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
2624 (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
2625 }
2626
2627 }
2628}
2629
2630/*
2631 * asc_prt_asc_qdone_info()
2632 */
2633static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
2634{
2635 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
2636 printk(" srb_ptr 0x%lx, target_ix %u, cdb_len %u, tag_code %u,\n",
2637 (ulong)q->d2.srb_ptr, q->d2.target_ix, q->d2.cdb_len,
2638 q->d2.tag_code);
2639 printk
2640 (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
2641 q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
2642}
2643
2644/*
2645 * asc_prt_adv_sgblock()
2646 *
2647 * Display an ADV_SG_BLOCK structure.
2648 */
2649static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
2650{
2651 int i;
2652
2653 printk(" ASC_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
2654 (ulong)b, sgblockno);
2655 printk(" sg_cnt %u, sg_ptr 0x%lx\n",
2656 b->sg_cnt, (ulong)le32_to_cpu(b->sg_ptr));
2657 BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
2658 if (b->sg_ptr != 0)
2659 BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
2660 for (i = 0; i < b->sg_cnt; i++) {
2661 printk(" [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
2662 i, (ulong)b->sg_list[i].sg_addr,
2663 (ulong)b->sg_list[i].sg_count);
2664 }
2665}
2666
2667/*
2668 * asc_prt_adv_scsi_req_q()
2669 *
2670 * Display an ADV_SCSI_REQ_Q structure.
2671 */
2672static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
2673{
2674 int sg_blk_cnt;
2675 struct asc_sg_block *sg_ptr;
2676
2677 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
2678
2679 printk(" target_id %u, target_lun %u, srb_ptr 0x%lx, a_flag 0x%x\n",
2680 q->target_id, q->target_lun, (ulong)q->srb_ptr, q->a_flag);
2681
2682 printk(" cntl 0x%x, data_addr 0x%lx, vdata_addr 0x%lx\n",
2683 q->cntl, (ulong)le32_to_cpu(q->data_addr), (ulong)q->vdata_addr);
2684
2685 printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2686 (ulong)le32_to_cpu(q->data_cnt),
2687 (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
2688
2689 printk
2690 (" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
2691 q->cdb_len, q->done_status, q->host_status, q->scsi_status);
2692
2693 printk(" sg_working_ix 0x%x, target_cmd %u\n",
2694 q->sg_working_ix, q->target_cmd);
2695
2696 printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
2697 (ulong)le32_to_cpu(q->scsiq_rptr),
2698 (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
2699
2700 /* Display the request's ADV_SG_BLOCK structures. */
2701 if (q->sg_list_ptr != NULL) {
2702 sg_blk_cnt = 0;
2703 while (1) {
2704 /*
2705 * 'sg_ptr' is a physical address. Convert it to a virtual
2706 * address by indexing 'sg_blk_cnt' into the virtual address
2707 * array 'sg_list_ptr'.
2708 *
2709 * XXX - Assumes all SG physical blocks are virtually contiguous.
2710 */
2711 sg_ptr =
2712 &(((ADV_SG_BLOCK *)(q->sg_list_ptr))[sg_blk_cnt]);
2713 asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
2714 if (sg_ptr->sg_ptr == 0) {
2715 break;
2716 }
2717 sg_blk_cnt++;
2718 }
2719 }
2720}
51219358 2721#endif /* ADVANSYS_DEBUG */
47d853cc 2722
b249c7fd
MW		 2723/*
2724 * The advansys chip/microcode contains a 32-bit identifier for each command
2725 * known as the 'srb'. I don't know what it stands for. The driver used
2726 * to encode the scsi_cmnd pointer by calling virt_to_bus and retrieve it
2727 * with bus_to_virt. Now the driver keeps a per-host map of integers to
2728 * pointers. It auto-expands when full, unless it can't allocate memory.
2729 * Note that an srb of 0 is treated specially by the chip/firmware, hence
2730 * the return of i+1 in this routine, and the corresponding subtraction in
2731 * the inverse routine.
2732 */
2733#define BAD_SRB 0
2734static u32 advansys_ptr_to_srb(struct asc_dvc_var *asc_dvc, void *ptr)
2735{
2736 int i;
2737 void **new_ptr;
2738
2739 for (i = 0; i < asc_dvc->ptr_map_count; i++) {
2740 if (!asc_dvc->ptr_map[i])
2741 goto out;
2742 }
2743
2744 if (asc_dvc->ptr_map_count == 0)
2745 asc_dvc->ptr_map_count = 1;
2746 else
2747 asc_dvc->ptr_map_count *= 2;
2748
2749 new_ptr = krealloc(asc_dvc->ptr_map,
2750 asc_dvc->ptr_map_count * sizeof(void *), GFP_ATOMIC);
2751 if (!new_ptr)
2752 return BAD_SRB;
2753 asc_dvc->ptr_map = new_ptr;
2754 out:
2755 ASC_DBG(3, "Putting ptr %p into array offset %d\n", ptr, i);
2756 asc_dvc->ptr_map[i] = ptr;
2757 return i + 1;
2758}
2759
2760static void * advansys_srb_to_ptr(struct asc_dvc_var *asc_dvc, u32 srb)
2761{
2762 void *ptr;
2763
2764 srb--;
2765 if (srb >= asc_dvc->ptr_map_count) {
2766 printk("advansys: bad SRB %u, max %u\n", srb,
2767 asc_dvc->ptr_map_count);
2768 return NULL;
2769 }
2770 ptr = asc_dvc->ptr_map[srb];
2771 asc_dvc->ptr_map[srb] = NULL;
2772 ASC_DBG(3, "Returning ptr %p from array offset %d\n", ptr, srb);
2773 return ptr;
2774}
2775
1da177e4 2776/*
51219358 2777 * advansys_info()
47d853cc 2778 *
51219358
MW		 2779 * Return suitable for printing on the console with the argument
2780 * adapter's configuration information.
2781 *
2782 * Note: The information line should not exceed ASC_INFO_SIZE bytes,
2783 * otherwise the static 'info' array will be overrun.
1da177e4 2784 */
51219358 2785static const char *advansys_info(struct Scsi_Host *shost)
1da177e4 2786{
51219358 2787 static char info[ASC_INFO_SIZE];
d2411495 2788 struct asc_board *boardp = shost_priv(shost);
51219358
MW		 2789 ASC_DVC_VAR *asc_dvc_varp;
2790 ADV_DVC_VAR *adv_dvc_varp;
2791 char *busname;
2792 char *widename = NULL;
1da177e4 2793
51219358
MW		 2794 if (ASC_NARROW_BOARD(boardp)) {
2795 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
b352f923 2796 ASC_DBG(1, "begin\n");
51219358
MW		 2797 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2798 if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
2799 ASC_IS_ISAPNP) {
2800 busname = "ISA PnP";
2801 } else {
2802 busname = "ISA";
2803 }
2804 sprintf(info,
2805 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
2806 ASC_VERSION, busname,
2807 (ulong)shost->io_port,
2808 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
d361db48 2809 boardp->irq, shost->dma_channel);
51219358
MW		 2810 } else {
2811 if (asc_dvc_varp->bus_type & ASC_IS_VL) {
2812 busname = "VL";
2813 } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
2814 busname = "EISA";
2815 } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
2816 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
2817 == ASC_IS_PCI_ULTRA) {
2818 busname = "PCI Ultra";
2819 } else {
2820 busname = "PCI";
2821 }
2822 } else {
2823 busname = "?";
9d0e96eb
MW		 2824 shost_printk(KERN_ERR, shost, "unknown bus "
2825 "type %d\n", asc_dvc_varp->bus_type);
51219358
MW		 2826 }
2827 sprintf(info,
2828 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
2829 ASC_VERSION, busname, (ulong)shost->io_port,
2830 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
d361db48 2831 boardp->irq);
51219358
MW		 2832 }
2833 } else {
2834 /*
2835 * Wide Adapter Information
2836 *
2837 * Memory-mapped I/O is used instead of I/O space to access
2838 * the adapter, but display the I/O Port range. The Memory
2839 * I/O address is displayed through the driver /proc file.
2840 */
2841 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2842 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2843 widename = "Ultra-Wide";
2844 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2845 widename = "Ultra2-Wide";
2846 } else {
2847 widename = "Ultra3-Wide";
2848 }
2849 sprintf(info,
2850 "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
2851 ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
d361db48 2852 (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq);
51219358
MW		 2853 }
2854 BUG_ON(strlen(info) >= ASC_INFO_SIZE);
b352f923 2855 ASC_DBG(1, "end\n");
51219358 2856 return info;
47d853cc
MW		 2857}
2858
51219358 2859#ifdef CONFIG_PROC_FS
47d853cc
MW		 2860
2861/*
51219358 2862 * asc_prt_board_devices()
47d853cc 2863 *
51219358 2864 * Print driver information for devices attached to the board.
47d853cc 2865 */
b59fb6fd 2866static void asc_prt_board_devices(struct seq_file *m, struct Scsi_Host *shost)
47d853cc 2867{
d2411495 2868 struct asc_board *boardp = shost_priv(shost);
51219358
MW		 2869 int chip_scsi_id;
2870 int i;
47d853cc 2871
b59fb6fd
AV		 2872 seq_printf(m,
2873 "\nDevice Information for AdvanSys SCSI Host %d:\n",
2874 shost->host_no);
47d853cc 2875
51219358
MW		 2876 if (ASC_NARROW_BOARD(boardp)) {
2877 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
2878 } else {
2879 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
47d853cc
MW		 2880 }
2881
2f979427 2882 seq_puts(m, "Target IDs Detected:");
51219358 2883 for (i = 0; i <= ADV_MAX_TID; i++) {
b59fb6fd
AV		 2884 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i))
2885 seq_printf(m, " %X,", i);
27c868c2 2886 }
b59fb6fd 2887 seq_printf(m, " (%X=Host Adapter)\n", chip_scsi_id);
47d853cc
MW		 2888}
2889
2890/*
51219358 2891 * Display Wide Board BIOS Information.
47d853cc 2892 */
b59fb6fd 2893static void asc_prt_adv_bios(struct seq_file *m, struct Scsi_Host *shost)
47d853cc 2894{
d2411495 2895 struct asc_board *boardp = shost_priv(shost);
51219358
MW		 2896 ushort major, minor, letter;
2897
2f979427 2898 seq_puts(m, "\nROM BIOS Version: ");
47d853cc
MW		 2899
2900 /*
51219358
MW		 2901 * If the BIOS saved a valid signature, then fill in
2902 * the BIOS code segment base address.
47d853cc 2903 */
51219358 2904 if (boardp->bios_signature != 0x55AA) {
3d30079c
RV		 2905 seq_puts(m, "Disabled or Pre-3.1\n"
2906 "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n"
2907 "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
51219358
MW		 2908 } else {
2909 major = (boardp->bios_version >> 12) & 0xF;
2910 minor = (boardp->bios_version >> 8) & 0xF;
2911 letter = (boardp->bios_version & 0xFF);
47d853cc 2912
b59fb6fd 2913 seq_printf(m, "%d.%d%c\n",
51219358
MW		 2914 major, minor,
2915 letter >= 26 ? '?' : letter + 'A');
51219358
MW		 2916 /*
2917 * Current available ROM BIOS release is 3.1I for UW
2918 * and 3.2I for U2W. This code doesn't differentiate
2919 * UW and U2W boards.
2920 */
2921 if (major < 3 || (major <= 3 && minor < 1) ||
2922 (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
3d30079c
RV		 2923 seq_puts(m, "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n"
2924 "ftp://ftp.connectcom.net/pub\n");
51219358
MW		 2925 }
2926 }
1da177e4
LT		 2927}
2928
1da177e4 2929/*
51219358
MW		 2930 * Add serial number to information bar if signature AAh
2931 * is found in at bit 15-9 (7 bits) of word 1.
1da177e4 2932 *
51219358 2933 * Serial Number consists fo 12 alpha-numeric digits.
1da177e4 2934 *
51219358
MW		 2935 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits)
2936 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits)
2937 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits)
2938 * 5 - Product revision (A-J) Word0: " "
1da177e4 2939 *
51219358
MW		 2940 * Signature Word1: 15-9 (7 bits)
2941 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
2942 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits)
1da177e4 2943 *
51219358 2944 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
1da177e4 2945 *
51219358 2946 * Note 1: Only production cards will have a serial number.
1da177e4 2947 *
51219358 2948 * Note 2: Signature is most significant 7 bits (0xFE).
1da177e4 2949 *
51219358 2950 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
1da177e4 2951 */
51219358 2952static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
1da177e4 2953{
51219358 2954 ushort w, num;
27c868c2 2955
51219358
MW		 2956 if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
2957 return ASC_FALSE;
2958 } else {
2959 /*
2960 * First word - 6 digits.
2961 */
2962 w = serialnum[0];
27c868c2 2963
51219358
MW		 2964 /* Product type - 1st digit. */
2965 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
2966 /* Product type is P=Prototype */
2967 *cp += 0x8;
2968 }
2969 cp++;
2970
2971 /* Manufacturing location - 2nd digit. */
2972 *cp++ = 'A' + ((w & 0x1C00) >> 10);
2973
2974 /* Product ID - 3rd, 4th digits. */
2975 num = w & 0x3FF;
2976 *cp++ = '0' + (num / 100);
2977 num %= 100;
2978 *cp++ = '0' + (num / 10);
2979
2980 /* Product revision - 5th digit. */
2981 *cp++ = 'A' + (num % 10);
27c868c2 2982
27c868c2 2983 /*
51219358 2984 * Second word
27c868c2 2985 */
51219358 2986 w = serialnum[1];
27c868c2
MW		 2987
2988 /*
51219358 2989 * Year - 6th digit.
27c868c2 2990 *
51219358
MW		 2991 * If bit 15 of third word is set, then the
2992 * last digit of the year is greater than 7.
27c868c2 2993 */
51219358
MW		 2994 if (serialnum[2] & 0x8000) {
2995 *cp++ = '8' + ((w & 0x1C0) >> 6);
2996 } else {
2997 *cp++ = '0' + ((w & 0x1C0) >> 6);
27c868c2
MW		 2998 }
2999
51219358
MW		 3000 /* Week of year - 7th, 8th digits. */
3001 num = w & 0x003F;
3002 *cp++ = '0' + num / 10;
3003 num %= 10;
3004 *cp++ = '0' + num;
27c868c2
MW		 3005
3006 /*
51219358 3007 * Third word
27c868c2 3008 */
51219358 3009 w = serialnum[2] & 0x7FFF;
1da177e4 3010
51219358
MW		 3011 /* Serial number - 9th digit. */
3012 *cp++ = 'A' + (w / 1000);
27c868c2 3013
51219358
MW		 3014 /* 10th, 11th, 12th digits. */
3015 num = w % 1000;
3016 *cp++ = '0' + num / 100;
3017 num %= 100;
3018 *cp++ = '0' + num / 10;
3019 num %= 10;
3020 *cp++ = '0' + num;
3021
3022 *cp = '\0'; /* Null Terminate the string. */
3023 return ASC_TRUE;
3024 }
1da177e4
LT		 3025}
3026
3027/*
51219358 3028 * asc_prt_asc_board_eeprom()
1da177e4 3029 *
51219358 3030 * Print board EEPROM configuration.
1da177e4 3031 */
b59fb6fd 3032static void asc_prt_asc_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 3033{
d2411495 3034 struct asc_board *boardp = shost_priv(shost);
51219358 3035 ASC_DVC_VAR *asc_dvc_varp;
51219358
MW		 3036 ASCEEP_CONFIG *ep;
3037 int i;
3038#ifdef CONFIG_ISA
3039 int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
3040#endif /* CONFIG_ISA */
3041 uchar serialstr[13];
27c868c2 3042
51219358
MW		 3043 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
3044 ep = &boardp->eep_config.asc_eep;
27c868c2 3045
b59fb6fd
AV		 3046 seq_printf(m,
3047 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3048 shost->host_no);
1da177e4 3049
51219358 3050 if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
b59fb6fd
AV		 3051 == ASC_TRUE)
3052 seq_printf(m, " Serial Number: %s\n", serialstr);
3053 else if (ep->adapter_info[5] == 0xBB)
2f979427
RV		 3054 seq_puts(m,
3055 " Default Settings Used for EEPROM-less Adapter.\n");
b59fb6fd 3056 else
2f979427 3057 seq_puts(m, " Serial Number Signature Not Present.\n");
b59fb6fd
AV		 3058
3059 seq_printf(m,
3060 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3061 ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
3062 ep->max_tag_qng);
3063
3064 seq_printf(m,
3065 " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
3066
2f979427 3067 seq_puts(m, " Target ID: ");
b59fb6fd
AV		 3068 for (i = 0; i <= ASC_MAX_TID; i++)
3069 seq_printf(m, " %d", i);
b59fb6fd 3070
3d30079c 3071 seq_puts(m, "\n Disconnects: ");
b59fb6fd
AV		 3072 for (i = 0; i <= ASC_MAX_TID; i++)
3073 seq_printf(m, " %c",
3074 (ep->disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
b59fb6fd 3075
3d30079c 3076 seq_puts(m, "\n Command Queuing: ");
b59fb6fd
AV		 3077 for (i = 0; i <= ASC_MAX_TID; i++)
3078 seq_printf(m, " %c",
3079 (ep->use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
b59fb6fd 3080
3d30079c 3081 seq_puts(m, "\n Start Motor: ");
b59fb6fd
AV		 3082 for (i = 0; i <= ASC_MAX_TID; i++)
3083 seq_printf(m, " %c",
3084 (ep->start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
b59fb6fd 3085
3d30079c 3086 seq_puts(m, "\n Synchronous Transfer:");
b59fb6fd
AV		 3087 for (i = 0; i <= ASC_MAX_TID; i++)
3088 seq_printf(m, " %c",
3089 (ep->init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
f50332ff 3090 seq_putc(m, '\n');
51219358
MW		 3091
3092#ifdef CONFIG_ISA
3093 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
b59fb6fd
AV		 3094 seq_printf(m,
3095 " Host ISA DMA speed: %d MB/S\n",
3096 isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
51219358
MW		 3097 }
3098#endif /* CONFIG_ISA */
1da177e4
LT		 3099}
3100
3101/*
51219358 3102 * asc_prt_adv_board_eeprom()
1da177e4 3103 *
51219358 3104 * Print board EEPROM configuration.
1da177e4 3105 */
b59fb6fd 3106static void asc_prt_adv_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 3107{
d2411495 3108 struct asc_board *boardp = shost_priv(shost);
51219358 3109 ADV_DVC_VAR *adv_dvc_varp;
27c868c2 3110 int i;
51219358
MW		 3111 char *termstr;
3112 uchar serialstr[13];
3113 ADVEEP_3550_CONFIG *ep_3550 = NULL;
3114 ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
3115 ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
3116 ushort word;
3117 ushort *wordp;
3118 ushort sdtr_speed = 0;
27c868c2 3119
51219358
MW		 3120 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
3121 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3122 ep_3550 = &boardp->eep_config.adv_3550_eep;
3123 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3124 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
27c868c2 3125 } else {
51219358 3126 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
27c868c2 3127 }
1da177e4 3128
b59fb6fd
AV		 3129 seq_printf(m,
3130 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3131 shost->host_no);
27c868c2 3132
51219358
MW		 3133 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3134 wordp = &ep_3550->serial_number_word1;
3135 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3136 wordp = &ep_38C0800->serial_number_word1;
3137 } else {
3138 wordp = &ep_38C1600->serial_number_word1;
3139 }
27c868c2 3140
b59fb6fd
AV		 3141 if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE)
3142 seq_printf(m, " Serial Number: %s\n", serialstr);
3143 else
2f979427 3144 seq_puts(m, " Serial Number Signature Not Present.\n");
27c868c2 3145
b59fb6fd
AV		 3146 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3147 seq_printf(m,
3148 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3149 ep_3550->adapter_scsi_id,
3150 ep_3550->max_host_qng, ep_3550->max_dvc_qng);
3151 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3152 seq_printf(m,
3153 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3154 ep_38C0800->adapter_scsi_id,
3155 ep_38C0800->max_host_qng,
3156 ep_38C0800->max_dvc_qng);
3157 else
3158 seq_printf(m,
3159 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3160 ep_38C1600->adapter_scsi_id,
3161 ep_38C1600->max_host_qng,
3162 ep_38C1600->max_dvc_qng);
51219358
MW		 3163 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3164 word = ep_3550->termination;
3165 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3166 word = ep_38C0800->termination_lvd;
3167 } else {
3168 word = ep_38C1600->termination_lvd;
3169 }
3170 switch (word) {
3171 case 1:
3172 termstr = "Low Off/High Off";
3173 break;
3174 case 2:
3175 termstr = "Low Off/High On";
3176 break;
3177 case 3:
3178 termstr = "Low On/High On";
3179 break;
3180 default:
3181 case 0:
3182 termstr = "Automatic";
3183 break;
27c868c2 3184 }
1da177e4 3185
b59fb6fd
AV		 3186 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3187 seq_printf(m,
3188 " termination: %u (%s), bios_ctrl: 0x%x\n",
3189 ep_3550->termination, termstr,
3190 ep_3550->bios_ctrl);
3191 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3192 seq_printf(m,
3193 " termination: %u (%s), bios_ctrl: 0x%x\n",
3194 ep_38C0800->termination_lvd, termstr,
3195 ep_38C0800->bios_ctrl);
3196 else
3197 seq_printf(m,
3198 " termination: %u (%s), bios_ctrl: 0x%x\n",
3199 ep_38C1600->termination_lvd, termstr,
3200 ep_38C1600->bios_ctrl);
1da177e4 3201
2f979427 3202 seq_puts(m, " Target ID: ");
b59fb6fd
AV		 3203 for (i = 0; i <= ADV_MAX_TID; i++)
3204 seq_printf(m, " %X", i);
f50332ff 3205 seq_putc(m, '\n');
1da177e4 3206
51219358
MW		 3207 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3208 word = ep_3550->disc_enable;
3209 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3210 word = ep_38C0800->disc_enable;
3211 } else {
3212 word = ep_38C1600->disc_enable;
3213 }
2f979427 3214 seq_puts(m, " Disconnects: ");
b59fb6fd
AV		 3215 for (i = 0; i <= ADV_MAX_TID; i++)
3216 seq_printf(m, " %c",
3217 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
f50332ff 3218 seq_putc(m, '\n');
1da177e4 3219
51219358
MW		 3220 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3221 word = ep_3550->tagqng_able;
3222 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3223 word = ep_38C0800->tagqng_able;
3224 } else {
3225 word = ep_38C1600->tagqng_able;
3226 }
2f979427 3227 seq_puts(m, " Command Queuing: ");
b59fb6fd
AV		 3228 for (i = 0; i <= ADV_MAX_TID; i++)
3229 seq_printf(m, " %c",
3230 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
f50332ff 3231 seq_putc(m, '\n');
1da177e4 3232
51219358
MW		 3233 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3234 word = ep_3550->start_motor;
3235 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3236 word = ep_38C0800->start_motor;
27c868c2 3237 } else {
51219358
MW		 3238 word = ep_38C1600->start_motor;
3239 }
2f979427 3240 seq_puts(m, " Start Motor: ");
b59fb6fd
AV		 3241 for (i = 0; i <= ADV_MAX_TID; i++)
3242 seq_printf(m, " %c",
3243 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
f50332ff 3244 seq_putc(m, '\n');
27c868c2 3245
51219358 3246 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2f979427 3247 seq_puts(m, " Synchronous Transfer:");
b59fb6fd
AV		 3248 for (i = 0; i <= ADV_MAX_TID; i++)
3249 seq_printf(m, " %c",
3250 (ep_3550->sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
3251 'Y' : 'N');
f50332ff 3252 seq_putc(m, '\n');
51219358 3253 }
27c868c2 3254
51219358 3255 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2f979427 3256 seq_puts(m, " Ultra Transfer: ");
b59fb6fd
AV		 3257 for (i = 0; i <= ADV_MAX_TID; i++)
3258 seq_printf(m, " %c",
3259 (ep_3550->ultra_able & ADV_TID_TO_TIDMASK(i))
3260 ? 'Y' : 'N');
f50332ff 3261 seq_putc(m, '\n');
51219358 3262 }
27c868c2 3263
51219358
MW		 3264 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3265 word = ep_3550->wdtr_able;
3266 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3267 word = ep_38C0800->wdtr_able;
3268 } else {
3269 word = ep_38C1600->wdtr_able;
3270 }
2f979427 3271 seq_puts(m, " Wide Transfer: ");
b59fb6fd
AV		 3272 for (i = 0; i <= ADV_MAX_TID; i++)
3273 seq_printf(m, " %c",
3274 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
f50332ff 3275 seq_putc(m, '\n');
1da177e4 3276
51219358
MW		 3277 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
3278 adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
2f979427 3279 seq_puts(m, " Synchronous Transfer Speed (Mhz):\n ");
51219358
MW		 3280 for (i = 0; i <= ADV_MAX_TID; i++) {
3281 char *speed_str;
1da177e4 3282
51219358
MW		 3283 if (i == 0) {
3284 sdtr_speed = adv_dvc_varp->sdtr_speed1;
3285 } else if (i == 4) {
3286 sdtr_speed = adv_dvc_varp->sdtr_speed2;
3287 } else if (i == 8) {
3288 sdtr_speed = adv_dvc_varp->sdtr_speed3;
3289 } else if (i == 12) {
3290 sdtr_speed = adv_dvc_varp->sdtr_speed4;
3291 }
3292 switch (sdtr_speed & ADV_MAX_TID) {
3293 case 0:
3294 speed_str = "Off";
3295 break;
3296 case 1:
3297 speed_str = " 5";
3298 break;
3299 case 2:
3300 speed_str = " 10";
3301 break;
3302 case 3:
3303 speed_str = " 20";
3304 break;
3305 case 4:
3306 speed_str = " 40";
3307 break;
3308 case 5:
3309 speed_str = " 80";
3310 break;
3311 default:
3312 speed_str = "Unk";
3313 break;
3314 }
b59fb6fd
AV		 3315 seq_printf(m, "%X:%s ", i, speed_str);
3316 if (i == 7)
2f979427 3317 seq_puts(m, "\n ");
51219358
MW		 3318 sdtr_speed >>= 4;
3319 }
f50332ff 3320 seq_putc(m, '\n');
51219358 3321 }
1da177e4
LT		 3322}
3323
3324/*
51219358 3325 * asc_prt_driver_conf()
1da177e4 3326 */
b59fb6fd 3327static void asc_prt_driver_conf(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 3328{
d2411495 3329 struct asc_board *boardp = shost_priv(shost);
51219358 3330 int chip_scsi_id;
27c868c2 3331
b59fb6fd
AV		 3332 seq_printf(m,
3333 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
3334 shost->host_no);
27c868c2 3335
b59fb6fd 3336 seq_printf(m,
1abf635d 3337 " host_busy %u, max_id %u, max_lun %llu, max_channel %u\n",
74665016 3338 atomic_read(&shost->host_busy), shost->max_id,
b59fb6fd 3339 shost->max_lun, shost->max_channel);
95c9f162 3340
b59fb6fd
AV		 3341 seq_printf(m,
3342 " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
3343 shost->unique_id, shost->can_queue, shost->this_id,
3344 shost->sg_tablesize, shost->cmd_per_lun);
95c9f162 3345
b59fb6fd
AV		 3346 seq_printf(m,
3347 " unchecked_isa_dma %d, use_clustering %d\n",
3348 shost->unchecked_isa_dma, shost->use_clustering);
95c9f162 3349
b59fb6fd 3350 seq_printf(m,
31491e1a 3351 " flags 0x%x, last_reset 0x%lx, jiffies 0x%lx, asc_n_io_port 0x%x\n",
eac0b0c7 3352 boardp->flags, shost->last_reset, jiffies,
b59fb6fd 3353 boardp->asc_n_io_port);
27c868c2 3354
31491e1a 3355 seq_printf(m, " io_port 0x%lx\n", shost->io_port);
27c868c2 3356
51219358
MW		 3357 if (ASC_NARROW_BOARD(boardp)) {
3358 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
3359 } else {
3360 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
27c868c2 3361 }
1da177e4
LT		 3362}
3363
3364/*
51219358 3365 * asc_prt_asc_board_info()
1da177e4 3366 *
51219358 3367 * Print dynamic board configuration information.
1da177e4 3368 */
b59fb6fd 3369static void asc_prt_asc_board_info(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 3370{
d2411495 3371 struct asc_board *boardp = shost_priv(shost);
51219358 3372 int chip_scsi_id;
51219358
MW		 3373 ASC_DVC_VAR *v;
3374 ASC_DVC_CFG *c;
3375 int i;
3376 int renegotiate = 0;
27c868c2 3377
51219358
MW		 3378 v = &boardp->dvc_var.asc_dvc_var;
3379 c = &boardp->dvc_cfg.asc_dvc_cfg;
3380 chip_scsi_id = c->chip_scsi_id;
27c868c2 3381
b59fb6fd
AV		 3382 seq_printf(m,
3383 "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3384 shost->host_no);
27c868c2 3385
b59fb6fd
AV		 3386 seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3387 "mcode_version 0x%x, err_code %u\n",
3388 c->chip_version, c->mcode_date, c->mcode_version,
3389 v->err_code);
1da177e4 3390
51219358 3391 /* Current number of commands waiting for the host. */
b59fb6fd
AV		 3392 seq_printf(m,
3393 " Total Command Pending: %d\n", v->cur_total_qng);
1da177e4 3394
2f979427 3395 seq_puts(m, " Command Queuing:");
51219358
MW		 3396 for (i = 0; i <= ASC_MAX_TID; i++) {
3397 if ((chip_scsi_id == i) ||
3398 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3399 continue;
27c868c2 3400 }
b59fb6fd
AV		 3401 seq_printf(m, " %X:%c",
3402 i,
3403 (v->use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
51219358 3404 }
27c868c2 3405
51219358 3406 /* Current number of commands waiting for a device. */
3d30079c 3407 seq_puts(m, "\n Command Queue Pending:");
51219358
MW		 3408 for (i = 0; i <= ASC_MAX_TID; i++) {
3409 if ((chip_scsi_id == i) ||
3410 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3411 continue;
27c868c2 3412 }
b59fb6fd 3413 seq_printf(m, " %X:%u", i, v->cur_dvc_qng[i]);
27c868c2 3414 }
1da177e4 3415
51219358 3416 /* Current limit on number of commands that can be sent to a device. */
3d30079c 3417 seq_puts(m, "\n Command Queue Limit:");
51219358
MW		 3418 for (i = 0; i <= ASC_MAX_TID; i++) {
3419 if ((chip_scsi_id == i) ||
3420 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3421 continue;
3422 }
b59fb6fd 3423 seq_printf(m, " %X:%u", i, v->max_dvc_qng[i]);
27c868c2 3424 }
1da177e4 3425
51219358 3426 /* Indicate whether the device has returned queue full status. */
3d30079c 3427 seq_puts(m, "\n Command Queue Full:");
51219358
MW		 3428 for (i = 0; i <= ASC_MAX_TID; i++) {
3429 if ((chip_scsi_id == i) ||
3430 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3431 continue;
3432 }
b59fb6fd
AV		 3433 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i))
3434 seq_printf(m, " %X:Y-%d",
3435 i, boardp->queue_full_cnt[i]);
3436 else
3437 seq_printf(m, " %X:N", i);
51219358 3438 }
1da177e4 3439
3d30079c 3440 seq_puts(m, "\n Synchronous Transfer:");
51219358
MW		 3441 for (i = 0; i <= ASC_MAX_TID; i++) {
3442 if ((chip_scsi_id == i) ||
3443 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3444 continue;
3445 }
b59fb6fd
AV		 3446 seq_printf(m, " %X:%c",
3447 i,
3448 (v->sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
27c868c2 3449 }
f50332ff 3450 seq_putc(m, '\n');
1da177e4 3451
51219358
MW		 3452 for (i = 0; i <= ASC_MAX_TID; i++) {
3453 uchar syn_period_ix;
1da177e4 3454
51219358
MW		 3455 if ((chip_scsi_id == i) ||
3456 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3457 ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
3458 continue;
27c868c2 3459 }
27c868c2 3460
b59fb6fd 3461 seq_printf(m, " %X:", i);
27c868c2 3462
51219358 3463 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
2f979427 3464 seq_puts(m, " Asynchronous");
51219358
MW		 3465 } else {
3466 syn_period_ix =
3467 (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
3468 1);
27c868c2 3469
b59fb6fd
AV		 3470 seq_printf(m,
3471 " Transfer Period Factor: %d (%d.%d Mhz),",
3472 v->sdtr_period_tbl[syn_period_ix],
3473 250 / v->sdtr_period_tbl[syn_period_ix],
3474 ASC_TENTHS(250,
3475 v->sdtr_period_tbl[syn_period_ix]));
27c868c2 3476
b59fb6fd
AV		 3477 seq_printf(m, " REQ/ACK Offset: %d",
3478 boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET);
51219358 3479 }
1da177e4 3480
51219358 3481 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
2f979427 3482 seq_puts(m, "*\n");
51219358
MW		 3483 renegotiate = 1;
3484 } else {
f50332ff 3485 seq_putc(m, '\n');
51219358 3486 }
27c868c2 3487 }
1da177e4 3488
51219358 3489 if (renegotiate) {
2f979427 3490 seq_puts(m, " * = Re-negotiation pending before next command.\n");
27c868c2 3491 }
1da177e4
LT		 3492}
3493
1da177e4 3494/*
51219358 3495 * asc_prt_adv_board_info()
1da177e4 3496 *
51219358 3497 * Print dynamic board configuration information.
1da177e4 3498 */
b59fb6fd 3499static void asc_prt_adv_board_info(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 3500{
d2411495 3501 struct asc_board *boardp = shost_priv(shost);
27c868c2 3502 int i;
51219358
MW		 3503 ADV_DVC_VAR *v;
3504 ADV_DVC_CFG *c;
3505 AdvPortAddr iop_base;
3506 ushort chip_scsi_id;
3507 ushort lramword;
3508 uchar lrambyte;
3509 ushort tagqng_able;
3510 ushort sdtr_able, wdtr_able;
3511 ushort wdtr_done, sdtr_done;
3512 ushort period = 0;
3513 int renegotiate = 0;
27c868c2 3514
51219358
MW		 3515 v = &boardp->dvc_var.adv_dvc_var;
3516 c = &boardp->dvc_cfg.adv_dvc_cfg;
3517 iop_base = v->iop_base;
3518 chip_scsi_id = v->chip_scsi_id;
3519
b59fb6fd
AV		 3520 seq_printf(m,
3521 "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3522 shost->host_no);
27c868c2 3523
b59fb6fd
AV		 3524 seq_printf(m,
3525 " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
31491e1a 3526 (unsigned long)v->iop_base,
b59fb6fd
AV		 3527 AdvReadWordRegister(iop_base,IOPW_SCSI_CFG1) & CABLE_DETECT,
3528 v->err_code);
1da177e4 3529
b59fb6fd
AV		 3530 seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3531 "mcode_version 0x%x\n", c->chip_version,
3532 c->mcode_date, c->mcode_version);
51219358
MW		 3533
3534 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
2f979427 3535 seq_puts(m, " Queuing Enabled:");
27c868c2 3536 for (i = 0; i <= ADV_MAX_TID; i++) {
51219358
MW		 3537 if ((chip_scsi_id == i) ||
3538 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3539 continue;
27c868c2 3540 }
51219358 3541
b59fb6fd
AV		 3542 seq_printf(m, " %X:%c",
3543 i,
3544 (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
27c868c2 3545 }
1da177e4 3546
3d30079c 3547 seq_puts(m, "\n Queue Limit:");
51219358
MW		 3548 for (i = 0; i <= ADV_MAX_TID; i++) {
3549 if ((chip_scsi_id == i) ||
3550 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3551 continue;
3552 }
1da177e4 3553
51219358
MW		 3554 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
3555 lrambyte);
27c868c2 3556
b59fb6fd 3557 seq_printf(m, " %X:%d", i, lrambyte);
51219358 3558 }
27c868c2 3559
3d30079c 3560 seq_puts(m, "\n Command Pending:");
51219358
MW		 3561 for (i = 0; i <= ADV_MAX_TID; i++) {
3562 if ((chip_scsi_id == i) ||
3563 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3564 continue;
3565 }
27c868c2 3566
51219358
MW		 3567 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
3568 lrambyte);
1da177e4 3569
b59fb6fd 3570 seq_printf(m, " %X:%d", i, lrambyte);
51219358 3571 }
f50332ff 3572 seq_putc(m, '\n');
1da177e4 3573
51219358 3574 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
2f979427 3575 seq_puts(m, " Wide Enabled:");
51219358
MW		 3576 for (i = 0; i <= ADV_MAX_TID; i++) {
3577 if ((chip_scsi_id == i) ||
3578 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3579 continue;
27c868c2 3580 }
51219358 3581
b59fb6fd
AV		 3582 seq_printf(m, " %X:%c",
3583 i,
3584 (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
27c868c2 3585 }
f50332ff 3586 seq_putc(m, '\n');
1da177e4 3587
51219358 3588 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
2f979427 3589 seq_puts(m, " Transfer Bit Width:");
51219358
MW		 3590 for (i = 0; i <= ADV_MAX_TID; i++) {
3591 if ((chip_scsi_id == i) ||
3592 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3593 continue;
3594 }
1da177e4 3595
51219358
MW		 3596 AdvReadWordLram(iop_base,
3597 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3598 lramword);
27c868c2 3599
b59fb6fd
AV		 3600 seq_printf(m, " %X:%d",
3601 i, (lramword & 0x8000) ? 16 : 8);
27c868c2 3602
51219358
MW		 3603 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
3604 (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
f50332ff 3605 seq_putc(m, '*');
51219358 3606 renegotiate = 1;
27c868c2 3607 }
51219358 3608 }
f50332ff 3609 seq_putc(m, '\n');
27c868c2 3610
51219358 3611 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
2f979427 3612 seq_puts(m, " Synchronous Enabled:");
51219358
MW		 3613 for (i = 0; i <= ADV_MAX_TID; i++) {
3614 if ((chip_scsi_id == i) ||
3615 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3616 continue;
3617 }
27c868c2 3618
b59fb6fd
AV		 3619 seq_printf(m, " %X:%c",
3620 i,
3621 (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
51219358 3622 }
f50332ff 3623 seq_putc(m, '\n');
27c868c2 3624
51219358
MW		 3625 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
3626 for (i = 0; i <= ADV_MAX_TID; i++) {
27c868c2 3627
51219358
MW		 3628 AdvReadWordLram(iop_base,
3629 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3630 lramword);
3631 lramword &= ~0x8000;
27c868c2 3632
51219358
MW		 3633 if ((chip_scsi_id == i) ||
3634 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3635 ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
3636 continue;
27c868c2
MW		 3637 }
3638
b59fb6fd 3639 seq_printf(m, " %X:", i);
27c868c2 3640
51219358 3641 if ((lramword & 0x1F) == 0) { /* Check for REQ/ACK Offset 0. */
2f979427 3642 seq_puts(m, " Asynchronous");
51219358 3643 } else {
2f979427 3644 seq_puts(m, " Transfer Period Factor: ");
27c868c2 3645
51219358 3646 if ((lramword & 0x1F00) == 0x1100) { /* 80 Mhz */
2f979427 3647 seq_puts(m, "9 (80.0 Mhz),");
51219358 3648 } else if ((lramword & 0x1F00) == 0x1000) { /* 40 Mhz */
2f979427 3649 seq_puts(m, "10 (40.0 Mhz),");
51219358 3650 } else { /* 20 Mhz or below. */
27c868c2 3651
51219358
MW		 3652 period = (((lramword >> 8) * 25) + 50) / 4;
3653
3654 if (period == 0) { /* Should never happen. */
31491e1a 3655 seq_printf(m, "%d (? Mhz), ", period);
51219358 3656 } else {
b59fb6fd
AV		 3657 seq_printf(m,
3658 "%d (%d.%d Mhz),",
3659 period, 250 / period,
3660 ASC_TENTHS(250, period));
51219358
MW		 3661 }
3662 }
3663
b59fb6fd
AV		 3664 seq_printf(m, " REQ/ACK Offset: %d",
3665 lramword & 0x1F);
51219358
MW		 3666 }
3667
3668 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
2f979427 3669 seq_puts(m, "*\n");
51219358
MW		 3670 renegotiate = 1;
3671 } else {
f50332ff 3672 seq_putc(m, '\n');
51219358 3673 }
27c868c2 3674 }
51219358
MW		 3675
3676 if (renegotiate) {
2f979427 3677 seq_puts(m, " * = Re-negotiation pending before next command.\n");
51219358 3678 }
51219358
MW		 3679}
3680
3681#ifdef ADVANSYS_STATS
3682/*
3683 * asc_prt_board_stats()
1da177e4 3684 */
b59fb6fd 3685static void asc_prt_board_stats(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 3686{
d2411495
MW		 3687 struct asc_board *boardp = shost_priv(shost);
3688 struct asc_stats *s = &boardp->asc_stats;
27c868c2 3689
b59fb6fd
AV		 3690 seq_printf(m,
3691 "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
3692 shost->host_no);
51219358 3693
b59fb6fd 3694 seq_printf(m,
31491e1a 3695 " queuecommand %u, reset %u, biosparam %u, interrupt %u\n",
b59fb6fd
AV		 3696 s->queuecommand, s->reset, s->biosparam,
3697 s->interrupt);
27c868c2 3698
b59fb6fd 3699 seq_printf(m,
31491e1a 3700 " callback %u, done %u, build_error %u, build_noreq %u, build_nosg %u\n",
b59fb6fd
AV		 3701 s->callback, s->done, s->build_error,
3702 s->adv_build_noreq, s->adv_build_nosg);
27c868c2 3703
b59fb6fd 3704 seq_printf(m,
31491e1a 3705 " exe_noerror %u, exe_busy %u, exe_error %u, exe_unknown %u\n",
b59fb6fd
AV		 3706 s->exe_noerror, s->exe_busy, s->exe_error,
3707 s->exe_unknown);
51219358
MW		 3708
3709 /*
3710 * Display data transfer statistics.
3711 */
52c334e9 3712 if (s->xfer_cnt > 0) {
31491e1a 3713 seq_printf(m, " xfer_cnt %u, xfer_elem %u, ",
b59fb6fd 3714 s->xfer_cnt, s->xfer_elem);
27c868c2 3715
31491e1a 3716 seq_printf(m, "xfer_bytes %u.%01u kb\n",
b59fb6fd 3717 s->xfer_sect / 2, ASC_TENTHS(s->xfer_sect, 2));
1da177e4 3718
51219358 3719 /* Scatter gather transfer statistics */
31491e1a 3720 seq_printf(m, " avg_num_elem %u.%01u, ",
b59fb6fd
AV		 3721 s->xfer_elem / s->xfer_cnt,
3722 ASC_TENTHS(s->xfer_elem, s->xfer_cnt));
51219358 3723
31491e1a 3724 seq_printf(m, "avg_elem_size %u.%01u kb, ",
b59fb6fd
AV		 3725 (s->xfer_sect / 2) / s->xfer_elem,
3726 ASC_TENTHS((s->xfer_sect / 2), s->xfer_elem));
51219358 3727
31491e1a 3728 seq_printf(m, "avg_xfer_size %u.%01u kb\n",
b59fb6fd
AV		 3729 (s->xfer_sect / 2) / s->xfer_cnt,
3730 ASC_TENTHS((s->xfer_sect / 2), s->xfer_cnt));
27c868c2 3731 }
1da177e4 3732}
51219358 3733#endif /* ADVANSYS_STATS */
1da177e4
LT		 3734
3735/*
b59fb6fd 3736 * advansys_show_info() - /proc/scsi/advansys/{0,1,2,3,...}
1da177e4 3737 *
b59fb6fd
AV		 3738 * m: seq_file to print into
3739 * shost: Scsi_Host
1da177e4 3740 *
51219358
MW		 3741 * Return the number of bytes read from or written to a
3742 * /proc/scsi/advansys/[0...] file.
1da177e4 3743 */
51219358 3744static int
b59fb6fd 3745advansys_show_info(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 3746{
d2411495 3747 struct asc_board *boardp = shost_priv(shost);
27c868c2 3748
b352f923 3749 ASC_DBG(1, "begin\n");
51219358 3750
51219358
MW		 3751 /*
3752 * User read of /proc/scsi/advansys/[0...] file.
3753 */
1da177e4 3754
51219358
MW		 3755 /*
3756 * Get board configuration information.
3757 *
3758 * advansys_info() returns the board string from its own static buffer.
3759 */
51219358 3760 /* Copy board information. */
b59fb6fd 3761 seq_printf(m, "%s\n", (char *)advansys_info(shost));
51219358
MW		 3762 /*
3763 * Display Wide Board BIOS Information.
3764 */
b59fb6fd
AV		 3765 if (!ASC_NARROW_BOARD(boardp))
3766 asc_prt_adv_bios(m, shost);
1da177e4 3767
51219358
MW		 3768 /*
3769 * Display driver information for each device attached to the board.
3770 */
b59fb6fd 3771 asc_prt_board_devices(m, shost);
51219358
MW		 3772
3773 /*
3774 * Display EEPROM configuration for the board.
3775 */
b59fb6fd
AV		 3776 if (ASC_NARROW_BOARD(boardp))
3777 asc_prt_asc_board_eeprom(m, shost);
3778 else
3779 asc_prt_adv_board_eeprom(m, shost);
1da177e4 3780
51219358
MW		 3781 /*
3782 * Display driver configuration and information for the board.
3783 */
b59fb6fd 3784 asc_prt_driver_conf(m, shost);
1da177e4 3785
51219358
MW		 3786#ifdef ADVANSYS_STATS
3787 /*
3788 * Display driver statistics for the board.
3789 */
b59fb6fd 3790 asc_prt_board_stats(m, shost);
51219358 3791#endif /* ADVANSYS_STATS */
1da177e4 3792
51219358
MW		 3793 /*
3794 * Display Asc Library dynamic configuration information
3795 * for the board.
3796 */
b59fb6fd
AV		 3797 if (ASC_NARROW_BOARD(boardp))
3798 asc_prt_asc_board_info(m, shost);
3799 else
3800 asc_prt_adv_board_info(m, shost);
3801 return 0;
51219358
MW		 3802}
3803#endif /* CONFIG_PROC_FS */
3804
3805static void asc_scsi_done(struct scsi_cmnd *scp)
3806{
52c334e9 3807 scsi_dma_unmap(scp);
51219358 3808 ASC_STATS(scp->device->host, done);
51219358
MW		 3809 scp->scsi_done(scp);
3810}
3811
3812static void AscSetBank(PortAddr iop_base, uchar bank)
3813{
3814 uchar val;
3815
3816 val = AscGetChipControl(iop_base) &
3817 (~
3818 (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
3819 CC_CHIP_RESET));
3820 if (bank == 1) {
3821 val |= CC_BANK_ONE;
3822 } else if (bank == 2) {
3823 val |= CC_DIAG | CC_BANK_ONE;
27c868c2 3824 } else {
51219358 3825 val &= ~CC_BANK_ONE;
27c868c2 3826 }
51219358 3827 AscSetChipControl(iop_base, val);
51219358
MW		 3828}
3829
3830static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
3831{
3832 AscSetBank(iop_base, 1);
3833 AscWriteChipIH(iop_base, ins_code);
3834 AscSetBank(iop_base, 0);
51219358
MW		 3835}
3836
3837static int AscStartChip(PortAddr iop_base)
3838{
3839 AscSetChipControl(iop_base, 0);
3840 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3841 return (0);
27c868c2 3842 }
51219358
MW		 3843 return (1);
3844}
27c868c2 3845
51219358
MW		 3846static int AscStopChip(PortAddr iop_base)
3847{
3848 uchar cc_val;
3849
3850 cc_val =
3851 AscGetChipControl(iop_base) &
3852 (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
3853 AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
3854 AscSetChipIH(iop_base, INS_HALT);
3855 AscSetChipIH(iop_base, INS_RFLAG_WTM);
3856 if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
3857 return (0);
27c868c2 3858 }
51219358
MW		 3859 return (1);
3860}
27c868c2 3861
51219358
MW		 3862static int AscIsChipHalted(PortAddr iop_base)
3863{
3864 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3865 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
3866 return (1);
27c868c2 3867 }
27c868c2 3868 }
51219358
MW		 3869 return (0);
3870}
27c868c2 3871
51219358
MW		 3872static int AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
3873{
3874 PortAddr iop_base;
3875 int i = 10;
3876
3877 iop_base = asc_dvc->iop_base;
3878 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
3879 && (i-- > 0)) {
3880 mdelay(100);
27c868c2 3881 }
51219358
MW		 3882 AscStopChip(iop_base);
3883 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
3884 udelay(60);
3885 AscSetChipIH(iop_base, INS_RFLAG_WTM);
3886 AscSetChipIH(iop_base, INS_HALT);
3887 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
3888 AscSetChipControl(iop_base, CC_HALT);
3889 mdelay(200);
3890 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
3891 AscSetChipStatus(iop_base, 0);
3892 return (AscIsChipHalted(iop_base));
3893}
27c868c2 3894
51219358
MW		 3895static int AscFindSignature(PortAddr iop_base)
3896{
3897 ushort sig_word;
27c868c2 3898
b352f923 3899 ASC_DBG(1, "AscGetChipSignatureByte(0x%x) 0x%x\n",
51219358
MW		 3900 iop_base, AscGetChipSignatureByte(iop_base));
3901 if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
b352f923 3902 ASC_DBG(1, "AscGetChipSignatureWord(0x%x) 0x%x\n",
51219358
MW		 3903 iop_base, AscGetChipSignatureWord(iop_base));
3904 sig_word = AscGetChipSignatureWord(iop_base);
3905 if ((sig_word == (ushort)ASC_1000_ID0W) ||
3906 (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
3907 return (1);
27c868c2 3908 }
27c868c2 3909 }
51219358 3910 return (0);
27c868c2
MW		 3911}
3912
51219358 3913static void AscEnableInterrupt(PortAddr iop_base)
1da177e4 3914{
51219358 3915 ushort cfg;
27c868c2 3916
51219358
MW		 3917 cfg = AscGetChipCfgLsw(iop_base);
3918 AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
51219358 3919}
27c868c2 3920
51219358
MW		 3921static void AscDisableInterrupt(PortAddr iop_base)
3922{
3923 ushort cfg;
27c868c2 3924
51219358
MW		 3925 cfg = AscGetChipCfgLsw(iop_base);
3926 AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
51219358 3927}
27c868c2 3928
51219358
MW		 3929static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
3930{
3931 unsigned char byte_data;
3932 unsigned short word_data;
27c868c2 3933
51219358
MW		 3934 if (isodd_word(addr)) {
3935 AscSetChipLramAddr(iop_base, addr - 1);
3936 word_data = AscGetChipLramData(iop_base);
3937 byte_data = (word_data >> 8) & 0xFF;
3938 } else {
3939 AscSetChipLramAddr(iop_base, addr);
3940 word_data = AscGetChipLramData(iop_base);
3941 byte_data = word_data & 0xFF;
3942 }
3943 return byte_data;
3944}
27c868c2 3945
51219358
MW		 3946static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
3947{
3948 ushort word_data;
27c868c2 3949
51219358
MW		 3950 AscSetChipLramAddr(iop_base, addr);
3951 word_data = AscGetChipLramData(iop_base);
3952 return (word_data);
3953}
27c868c2 3954
51219358
MW		 3955#if CC_VERY_LONG_SG_LIST
3956static ASC_DCNT AscReadLramDWord(PortAddr iop_base, ushort addr)
3957{
3958 ushort val_low, val_high;
3959 ASC_DCNT dword_data;
27c868c2 3960
51219358
MW		 3961 AscSetChipLramAddr(iop_base, addr);
3962 val_low = AscGetChipLramData(iop_base);
3963 val_high = AscGetChipLramData(iop_base);
3964 dword_data = ((ASC_DCNT) val_high << 16) | (ASC_DCNT) val_low;
3965 return (dword_data);
3966}
3967#endif /* CC_VERY_LONG_SG_LIST */
3968
3969static void
3970AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
3971{
3972 int i;
3973
3974 AscSetChipLramAddr(iop_base, s_addr);
3975 for (i = 0; i < words; i++) {
3976 AscSetChipLramData(iop_base, set_wval);
27c868c2 3977 }
51219358 3978}
1da177e4 3979
51219358
MW		 3980static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
3981{
3982 AscSetChipLramAddr(iop_base, addr);
3983 AscSetChipLramData(iop_base, word_val);
51219358
MW		 3984}
3985
3986static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
3987{
3988 ushort word_data;
3989
3990 if (isodd_word(addr)) {
3991 addr--;
3992 word_data = AscReadLramWord(iop_base, addr);
3993 word_data &= 0x00FF;
3994 word_data |= (((ushort)byte_val << 8) & 0xFF00);
3995 } else {
3996 word_data = AscReadLramWord(iop_base, addr);
3997 word_data &= 0xFF00;
3998 word_data |= ((ushort)byte_val & 0x00FF);
3999 }
4000 AscWriteLramWord(iop_base, addr, word_data);
1da177e4
LT		 4001}
4002
4003/*
51219358 4004 * Copy 2 bytes to LRAM.
1da177e4 4005 *
51219358
MW		 4006 * The source data is assumed to be in little-endian order in memory
4007 * and is maintained in little-endian order when written to LRAM.
1da177e4 4008 */
51219358 4009static void
989bb5f5
JSR		 4010AscMemWordCopyPtrToLram(PortAddr iop_base, ushort s_addr,
4011 const uchar *s_buffer, int words)
1da177e4 4012{
27c868c2 4013 int i;
27c868c2 4014
51219358
MW		 4015 AscSetChipLramAddr(iop_base, s_addr);
4016 for (i = 0; i < 2 * words; i += 2) {
4017 /*
4018 * On a little-endian system the second argument below
4019 * produces a little-endian ushort which is written to
4020 * LRAM in little-endian order. On a big-endian system
4021 * the second argument produces a big-endian ushort which
4022 * is "transparently" byte-swapped by outpw() and written
4023 * in little-endian order to LRAM.
4024 */
4025 outpw(iop_base + IOP_RAM_DATA,
4026 ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
4027 }
51219358 4028}
27c868c2 4029
51219358
MW		 4030/*
4031 * Copy 4 bytes to LRAM.
4032 *
4033 * The source data is assumed to be in little-endian order in memory
25985edc 4034 * and is maintained in little-endian order when written to LRAM.
51219358
MW		 4035 */
4036static void
4037AscMemDWordCopyPtrToLram(PortAddr iop_base,
4038 ushort s_addr, uchar *s_buffer, int dwords)
4039{
4040 int i;
27c868c2 4041
51219358
MW		 4042 AscSetChipLramAddr(iop_base, s_addr);
4043 for (i = 0; i < 4 * dwords; i += 4) {
4044 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */
4045 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */
4046 }
51219358 4047}
27c868c2 4048
51219358
MW		 4049/*
4050 * Copy 2 bytes from LRAM.
4051 *
4052 * The source data is assumed to be in little-endian order in LRAM
4053 * and is maintained in little-endian order when written to memory.
4054 */
4055static void
4056AscMemWordCopyPtrFromLram(PortAddr iop_base,
4057 ushort s_addr, uchar *d_buffer, int words)
4058{
4059 int i;
4060 ushort word;
27c868c2 4061
51219358
MW		 4062 AscSetChipLramAddr(iop_base, s_addr);
4063 for (i = 0; i < 2 * words; i += 2) {
4064 word = inpw(iop_base + IOP_RAM_DATA);
4065 d_buffer[i] = word & 0xff;
4066 d_buffer[i + 1] = (word >> 8) & 0xff;
27c868c2 4067 }
51219358 4068}
27c868c2 4069
51219358
MW		 4070static ASC_DCNT AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
4071{
4072 ASC_DCNT sum;
4073 int i;
27c868c2 4074
51219358
MW		 4075 sum = 0L;
4076 for (i = 0; i < words; i++, s_addr += 2) {
4077 sum += AscReadLramWord(iop_base, s_addr);
27c868c2 4078 }
51219358
MW		 4079 return (sum);
4080}
27c868c2 4081
51219358
MW		 4082static ushort AscInitLram(ASC_DVC_VAR *asc_dvc)
4083{
4084 uchar i;
4085 ushort s_addr;
4086 PortAddr iop_base;
4087 ushort warn_code;
27c868c2 4088
51219358
MW		 4089 iop_base = asc_dvc->iop_base;
4090 warn_code = 0;
4091 AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
4092 (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
4093 64) >> 1));
4094 i = ASC_MIN_ACTIVE_QNO;
4095 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
4096 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4097 (uchar)(i + 1));
4098 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4099 (uchar)(asc_dvc->max_total_qng));
4100 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4101 (uchar)i);
4102 i++;
4103 s_addr += ASC_QBLK_SIZE;
4104 for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
4105 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4106 (uchar)(i + 1));
4107 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4108 (uchar)(i - 1));
4109 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4110 (uchar)i);
27c868c2 4111 }
51219358
MW		 4112 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4113 (uchar)ASC_QLINK_END);
4114 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4115 (uchar)(asc_dvc->max_total_qng - 1));
4116 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4117 (uchar)asc_dvc->max_total_qng);
4118 i++;
4119 s_addr += ASC_QBLK_SIZE;
4120 for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
4121 i++, s_addr += ASC_QBLK_SIZE) {
4122 AscWriteLramByte(iop_base,
4123 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
4124 AscWriteLramByte(iop_base,
4125 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
4126 AscWriteLramByte(iop_base,
4127 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
27c868c2 4128 }
51219358 4129 return warn_code;
1da177e4
LT		 4130}
4131
51219358 4132static ASC_DCNT
989bb5f5
JSR		 4133AscLoadMicroCode(PortAddr iop_base, ushort s_addr,
4134 const uchar *mcode_buf, ushort mcode_size)
1da177e4 4135{
51219358
MW		 4136 ASC_DCNT chksum;
4137 ushort mcode_word_size;
4138 ushort mcode_chksum;
27c868c2 4139
51219358
MW		 4140 /* Write the microcode buffer starting at LRAM address 0. */
4141 mcode_word_size = (ushort)(mcode_size >> 1);
4142 AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
4143 AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
27c868c2 4144
51219358 4145 chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
b352f923 4146 ASC_DBG(1, "chksum 0x%lx\n", (ulong)chksum);
51219358
MW		 4147 mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
4148 (ushort)ASC_CODE_SEC_BEG,
4149 (ushort)((mcode_size -
4150 s_addr - (ushort)
4151 ASC_CODE_SEC_BEG) /
4152 2));
b352f923 4153 ASC_DBG(1, "mcode_chksum 0x%lx\n", (ulong)mcode_chksum);
51219358
MW		 4154 AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
4155 AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
b352f923 4156 return chksum;
51219358 4157}
27c868c2 4158
51219358
MW		 4159static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
4160{
4161 PortAddr iop_base;
4162 int i;
4163 ushort lram_addr;
4164
4165 iop_base = asc_dvc->iop_base;
4166 AscPutRiscVarFreeQHead(iop_base, 1);
4167 AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4168 AscPutVarFreeQHead(iop_base, 1);
4169 AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4170 AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
4171 (uchar)((int)asc_dvc->max_total_qng + 1));
4172 AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
4173 (uchar)((int)asc_dvc->max_total_qng + 2));
4174 AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
4175 asc_dvc->max_total_qng);
4176 AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
4177 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
4178 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
4179 AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
4180 AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
4181 AscPutQDoneInProgress(iop_base, 0);
4182 lram_addr = ASC_QADR_BEG;
4183 for (i = 0; i < 32; i++, lram_addr += 2) {
4184 AscWriteLramWord(iop_base, lram_addr, 0);
4185 }
4186}
4187
4188static ushort AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
4189{
4190 int i;
4191 ushort warn_code;
4192 PortAddr iop_base;
4193 ASC_PADDR phy_addr;
4194 ASC_DCNT phy_size;
d10fb2c7 4195 struct asc_board *board = asc_dvc_to_board(asc_dvc);
51219358
MW		 4196
4197 iop_base = asc_dvc->iop_base;
4198 warn_code = 0;
4199 for (i = 0; i <= ASC_MAX_TID; i++) {
4200 AscPutMCodeInitSDTRAtID(iop_base, i,
4201 asc_dvc->cfg->sdtr_period_offset[i]);
4202 }
4203
4204 AscInitQLinkVar(asc_dvc);
4205 AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
4206 asc_dvc->cfg->disc_enable);
4207 AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
4208 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
4209
d10fb2c7
MW		 4210 /* Ensure overrun buffer is aligned on an 8 byte boundary. */
4211 BUG_ON((unsigned long)asc_dvc->overrun_buf & 7);
4212 asc_dvc->overrun_dma = dma_map_single(board->dev, asc_dvc->overrun_buf,
4213 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
9a908c1a
HRK		 4214 if (dma_mapping_error(board->dev, asc_dvc->overrun_dma)) {
4215 warn_code = -ENOMEM;
4216 goto err_dma_map;
4217 }
d10fb2c7 4218 phy_addr = cpu_to_le32(asc_dvc->overrun_dma);
51219358
MW		 4219 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
4220 (uchar *)&phy_addr, 1);
d10fb2c7 4221 phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE);
51219358
MW		 4222 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
4223 (uchar *)&phy_size, 1);
4224
4225 asc_dvc->cfg->mcode_date =
4226 AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
4227 asc_dvc->cfg->mcode_version =
4228 AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
4229
4230 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
4231 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
4232 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
9a908c1a
HRK		 4233 warn_code = UW_ERR;
4234 goto err_mcode_start;
51219358
MW		 4235 }
4236 if (AscStartChip(iop_base) != 1) {
4237 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
9a908c1a
HRK		 4238 warn_code = UW_ERR;
4239 goto err_mcode_start;
51219358
MW		 4240 }
4241
4242 return warn_code;
9a908c1a
HRK		 4243
4244err_mcode_start:
4245 dma_unmap_single(board->dev, asc_dvc->overrun_dma,
4246 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4247err_dma_map:
4248 asc_dvc->overrun_dma = 0;
4249 return warn_code;
51219358
MW		 4250}
4251
4252static ushort AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
4253{
989bb5f5
JSR		 4254 const struct firmware *fw;
4255 const char fwname[] = "advansys/mcode.bin";
4256 int err;
4257 unsigned long chksum;
51219358
MW		 4258 ushort warn_code;
4259 PortAddr iop_base;
4260
4261 iop_base = asc_dvc->iop_base;
4262 warn_code = 0;
4263 if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
4264 !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
4265 AscResetChipAndScsiBus(asc_dvc);
4266 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4267 }
4268 asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
4269 if (asc_dvc->err_code != 0)
4270 return UW_ERR;
4271 if (!AscFindSignature(asc_dvc->iop_base)) {
4272 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
4273 return warn_code;
4274 }
4275 AscDisableInterrupt(iop_base);
4276 warn_code |= AscInitLram(asc_dvc);
4277 if (asc_dvc->err_code != 0)
4278 return UW_ERR;
989bb5f5
JSR		 4279
4280 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4281 if (err) {
4282 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4283 fwname, err);
cf747445 4284 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 4285 return err;
4286 }
4287 if (fw->size < 4) {
4288 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4289 fw->size, fwname);
4290 release_firmware(fw);
cf747445 4291 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 4292 return -EINVAL;
4293 }
4294 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4295 (fw->data[1] << 8) | fw->data[0];
4296 ASC_DBG(1, "_asc_mcode_chksum 0x%lx\n", (ulong)chksum);
4297 if (AscLoadMicroCode(iop_base, 0, &fw->data[4],
4298 fw->size - 4) != chksum) {
51219358 4299 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
989bb5f5 4300 release_firmware(fw);
51219358
MW		 4301 return warn_code;
4302 }
989bb5f5 4303 release_firmware(fw);
51219358 4304 warn_code |= AscInitMicroCodeVar(asc_dvc);
9a908c1a
HRK		 4305 if (!asc_dvc->overrun_dma)
4306 return warn_code;
51219358
MW		 4307 asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
4308 AscEnableInterrupt(iop_base);
4309 return warn_code;
4310}
4311
4312/*
4313 * Load the Microcode
4314 *
4315 * Write the microcode image to RISC memory starting at address 0.
4316 *
4317 * The microcode is stored compressed in the following format:
4318 *
4319 * 254 word (508 byte) table indexed by byte code followed
4320 * by the following byte codes:
4321 *
4322 * 1-Byte Code:
4323 * 00: Emit word 0 in table.
4324 * 01: Emit word 1 in table.
4325 * .
4326 * FD: Emit word 253 in table.
4327 *
4328 * Multi-Byte Code:
4329 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
4330 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
4331 *
4332 * Returns 0 or an error if the checksum doesn't match
4333 */
989bb5f5
JSR		 4334static int AdvLoadMicrocode(AdvPortAddr iop_base, const unsigned char *buf,
4335 int size, int memsize, int chksum)
51219358
MW		 4336{
4337 int i, j, end, len = 0;
4338 ADV_DCNT sum;
4339
4340 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4341
4342 for (i = 253 * 2; i < size; i++) {
4343 if (buf[i] == 0xff) {
4344 unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
4345 for (j = 0; j < buf[i + 1]; j++) {
4346 AdvWriteWordAutoIncLram(iop_base, word);
4347 len += 2;
4348 }
4349 i += 3;
4350 } else if (buf[i] == 0xfe) {
4351 unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
4352 AdvWriteWordAutoIncLram(iop_base, word);
4353 i += 2;
4354 len += 2;
4355 } else {
951b62c1 4356 unsigned int off = buf[i] * 2;
51219358
MW		 4357 unsigned short word = (buf[off + 1] << 8) | buf[off];
4358 AdvWriteWordAutoIncLram(iop_base, word);
4359 len += 2;
4360 }
4361 }
4362
4363 end = len;
4364
4365 while (len < memsize) {
4366 AdvWriteWordAutoIncLram(iop_base, 0);
4367 len += 2;
4368 }
4369
4370 /* Verify the microcode checksum. */
4371 sum = 0;
4372 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4373
4374 for (len = 0; len < end; len += 2) {
4375 sum += AdvReadWordAutoIncLram(iop_base);
4376 }
4377
4378 if (sum != chksum)
4379 return ASC_IERR_MCODE_CHKSUM;
4380
4381 return 0;
4382}
4383
51219358
MW		 4384static void AdvBuildCarrierFreelist(struct adv_dvc_var *asc_dvc)
4385{
4386 ADV_CARR_T *carrp;
4387 ADV_SDCNT buf_size;
4388 ADV_PADDR carr_paddr;
4389
51219358
MW		 4390 carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
4391 asc_dvc->carr_freelist = NULL;
4392 if (carrp == asc_dvc->carrier_buf) {
4393 buf_size = ADV_CARRIER_BUFSIZE;
4394 } else {
4395 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
4396 }
4397
4398 do {
4399 /* Get physical address of the carrier 'carrp'. */
fd625f47 4400 carr_paddr = cpu_to_le32(virt_to_bus(carrp));
51219358
MW		 4401
4402 buf_size -= sizeof(ADV_CARR_T);
4403
51219358
MW		 4404 carrp->carr_pa = carr_paddr;
4405 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
4406
4407 /*
4408 * Insert the carrier at the beginning of the freelist.
4409 */
4410 carrp->next_vpa =
4411 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
4412 asc_dvc->carr_freelist = carrp;
4413
4414 carrp++;
4415 } while (buf_size > 0);
4416}
4417
4418/*
4419 * Send an idle command to the chip and wait for completion.
4420 *
4421 * Command completion is polled for once per microsecond.
4422 *
4423 * The function can be called from anywhere including an interrupt handler.
4424 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
4425 * functions to prevent reentrancy.
4426 *
4427 * Return Values:
4428 * ADV_TRUE - command completed successfully
4429 * ADV_FALSE - command failed
4430 * ADV_ERROR - command timed out
4431 */
4432static int
4433AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
4434 ushort idle_cmd, ADV_DCNT idle_cmd_parameter)
4435{
4436 int result;
4437 ADV_DCNT i, j;
4438 AdvPortAddr iop_base;
4439
4440 iop_base = asc_dvc->iop_base;
4441
4442 /*
4443 * Clear the idle command status which is set by the microcode
4444 * to a non-zero value to indicate when the command is completed.
4445 * The non-zero result is one of the IDLE_CMD_STATUS_* values
4446 */
4447 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
4448
4449 /*
4450 * Write the idle command value after the idle command parameter
4451 * has been written to avoid a race condition. If the order is not
4452 * followed, the microcode may process the idle command before the
4453 * parameters have been written to LRAM.
4454 */
4455 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
4456 cpu_to_le32(idle_cmd_parameter));
4457 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
4458
4459 /*
4460 * Tickle the RISC to tell it to process the idle command.
4461 */
4462 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
4463 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
4464 /*
4465 * Clear the tickle value. In the ASC-3550 the RISC flag
4466 * command 'clr_tickle_b' does not work unless the host
4467 * value is cleared.
4468 */
4469 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
4470 }
4471
4472 /* Wait for up to 100 millisecond for the idle command to timeout. */
4473 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
4474 /* Poll once each microsecond for command completion. */
4475 for (j = 0; j < SCSI_US_PER_MSEC; j++) {
4476 AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
4477 result);
4478 if (result != 0)
4479 return result;
4480 udelay(1);
4481 }
4482 }
4483
4484 BUG(); /* The idle command should never timeout. */
4485 return ADV_ERROR;
4486}
4487
4488/*
4489 * Reset SCSI Bus and purge all outstanding requests.
4490 *
4491 * Return Value:
4492 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset.
4493 * ADV_FALSE(0) - Microcode command failed.
4494 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
4495 * may be hung which requires driver recovery.
4496 */
4497static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
4498{
4499 int status;
4500
4501 /*
4502 * Send the SCSI Bus Reset idle start idle command which asserts
4503 * the SCSI Bus Reset signal.
4504 */
4505 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
4506 if (status != ADV_TRUE) {
4507 return status;
4508 }
4509
4510 /*
4511 * Delay for the specified SCSI Bus Reset hold time.
4512 *
4513 * The hold time delay is done on the host because the RISC has no
4514 * microsecond accurate timer.
4515 */
4516 udelay(ASC_SCSI_RESET_HOLD_TIME_US);
4517
4518 /*
4519 * Send the SCSI Bus Reset end idle command which de-asserts
4520 * the SCSI Bus Reset signal and purges any pending requests.
4521 */
4522 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
4523 if (status != ADV_TRUE) {
4524 return status;
4525 }
4526
4527 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4528
4529 return status;
4530}
4531
4532/*
4533 * Initialize the ASC-3550.
4534 *
4535 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4536 *
4537 * For a non-fatal error return a warning code. If there are no warnings
4538 * then 0 is returned.
4539 *
4540 * Needed after initialization for error recovery.
4541 */
4542static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
4543{
989bb5f5
JSR		 4544 const struct firmware *fw;
4545 const char fwname[] = "advansys/3550.bin";
51219358
MW		 4546 AdvPortAddr iop_base;
4547 ushort warn_code;
4548 int begin_addr;
4549 int end_addr;
4550 ushort code_sum;
4551 int word;
4552 int i;
989bb5f5
JSR		 4553 int err;
4554 unsigned long chksum;
51219358
MW		 4555 ushort scsi_cfg1;
4556 uchar tid;
4557 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
4558 ushort wdtr_able = 0, sdtr_able, tagqng_able;
4559 uchar max_cmd[ADV_MAX_TID + 1];
4560
4561 /* If there is already an error, don't continue. */
4562 if (asc_dvc->err_code != 0)
4563 return ADV_ERROR;
4564
4565 /*
4566 * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
4567 */
4568 if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
4569 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
4570 return ADV_ERROR;
4571 }
4572
4573 warn_code = 0;
4574 iop_base = asc_dvc->iop_base;
4575
4576 /*
4577 * Save the RISC memory BIOS region before writing the microcode.
4578 * The BIOS may already be loaded and using its RISC LRAM region
4579 * so its region must be saved and restored.
4580 *
4581 * Note: This code makes the assumption, which is currently true,
4582 * that a chip reset does not clear RISC LRAM.
4583 */
4584 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4585 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4586 bios_mem[i]);
4587 }
4588
4589 /*
4590 * Save current per TID negotiated values.
4591 */
4592 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) {
4593 ushort bios_version, major, minor;
4594
4595 bios_version =
4596 bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2];
4597 major = (bios_version >> 12) & 0xF;
4598 minor = (bios_version >> 8) & 0xF;
4599 if (major < 3 || (major == 3 && minor == 1)) {
4600 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
4601 AdvReadWordLram(iop_base, 0x120, wdtr_able);
4602 } else {
4603 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4604 }
4605 }
4606 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4607 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
4608 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4609 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
4610 max_cmd[tid]);
4611 }
4612
989bb5f5
JSR		 4613 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4614 if (err) {
4615 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4616 fwname, err);
cf747445 4617 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 4618 return err;
4619 }
4620 if (fw->size < 4) {
4621 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4622 fw->size, fwname);
4623 release_firmware(fw);
cf747445 4624 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 4625 return -EINVAL;
4626 }
4627 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4628 (fw->data[1] << 8) | fw->data[0];
4629 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
4630 fw->size - 4, ADV_3550_MEMSIZE,
4631 chksum);
4632 release_firmware(fw);
51219358
MW		 4633 if (asc_dvc->err_code)
4634 return ADV_ERROR;
4635
4636 /*
4637 * Restore the RISC memory BIOS region.
4638 */
4639 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4640 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4641 bios_mem[i]);
4642 }
4643
4644 /*
4645 * Calculate and write the microcode code checksum to the microcode
4646 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
4647 */
4648 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
4649 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
4650 code_sum = 0;
4651 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
4652 for (word = begin_addr; word < end_addr; word += 2) {
4653 code_sum += AdvReadWordAutoIncLram(iop_base);
4654 }
4655 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
4656
4657 /*
4658 * Read and save microcode version and date.
4659 */
4660 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
4661 asc_dvc->cfg->mcode_date);
4662 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
4663 asc_dvc->cfg->mcode_version);
4664
4665 /*
4666 * Set the chip type to indicate the ASC3550.
4667 */
4668 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
4669
4670 /*
4671 * If the PCI Configuration Command Register "Parity Error Response
4672 * Control" Bit was clear (0), then set the microcode variable
4673 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
4674 * to ignore DMA parity errors.
4675 */
4676 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
4677 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4678 word |= CONTROL_FLAG_IGNORE_PERR;
4679 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4680 }
4681
4682 /*
4683 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
4684 * threshold of 128 bytes. This register is only accessible to the host.
4685 */
4686 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
4687 START_CTL_EMFU | READ_CMD_MRM);
4688
4689 /*
4690 * Microcode operating variables for WDTR, SDTR, and command tag
4691 * queuing will be set in slave_configure() based on what a
4692 * device reports it is capable of in Inquiry byte 7.
4693 *
4694 * If SCSI Bus Resets have been disabled, then directly set
4695 * SDTR and WDTR from the EEPROM configuration. This will allow
4696 * the BIOS and warm boot to work without a SCSI bus hang on
4697 * the Inquiry caused by host and target mismatched DTR values.
4698 * Without the SCSI Bus Reset, before an Inquiry a device can't
4699 * be assumed to be in Asynchronous, Narrow mode.
4700 */
4701 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
4702 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
4703 asc_dvc->wdtr_able);
4704 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
4705 asc_dvc->sdtr_able);
4706 }
4707
4708 /*
4709 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
4710 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
4711 * bitmask. These values determine the maximum SDTR speed negotiated
4712 * with a device.
4713 *
4714 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
4715 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
4716 * without determining here whether the device supports SDTR.
4717 *
4718 * 4-bit speed SDTR speed name
4719 * =========== ===============
4720 * 0000b (0x0) SDTR disabled
4721 * 0001b (0x1) 5 Mhz
4722 * 0010b (0x2) 10 Mhz
4723 * 0011b (0x3) 20 Mhz (Ultra)
4724 * 0100b (0x4) 40 Mhz (LVD/Ultra2)
4725 * 0101b (0x5) 80 Mhz (LVD2/Ultra3)
4726 * 0110b (0x6) Undefined
4727 * .
4728 * 1111b (0xF) Undefined
4729 */
4730 word = 0;
4731 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4732 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) {
4733 /* Set Ultra speed for TID 'tid'. */
4734 word |= (0x3 << (4 * (tid % 4)));
4735 } else {
4736 /* Set Fast speed for TID 'tid'. */
4737 word |= (0x2 << (4 * (tid % 4)));
4738 }
4739 if (tid == 3) { /* Check if done with sdtr_speed1. */
4740 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
4741 word = 0;
4742 } else if (tid == 7) { /* Check if done with sdtr_speed2. */
4743 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
4744 word = 0;
4745 } else if (tid == 11) { /* Check if done with sdtr_speed3. */
4746 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
4747 word = 0;
4748 } else if (tid == 15) { /* Check if done with sdtr_speed4. */
4749 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
4750 /* End of loop. */
4751 }
4752 }
4753
4754 /*
4755 * Set microcode operating variable for the disconnect per TID bitmask.
4756 */
4757 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
4758 asc_dvc->cfg->disc_enable);
4759
4760 /*
4761 * Set SCSI_CFG0 Microcode Default Value.
4762 *
4763 * The microcode will set the SCSI_CFG0 register using this value
4764 * after it is started below.
4765 */
4766 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
4767 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
4768 asc_dvc->chip_scsi_id);
4769
4770 /*
4771 * Determine SCSI_CFG1 Microcode Default Value.
4772 *
4773 * The microcode will set the SCSI_CFG1 register using this value
4774 * after it is started below.
4775 */
4776
4777 /* Read current SCSI_CFG1 Register value. */
4778 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
4779
4780 /*
4781 * If all three connectors are in use, return an error.
4782 */
4783 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
4784 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
4785 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
4786 return ADV_ERROR;
4787 }
4788
4789 /*
4790 * If the internal narrow cable is reversed all of the SCSI_CTRL
4791 * register signals will be set. Check for and return an error if
4792 * this condition is found.
4793 */
4794 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
4795 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
4796 return ADV_ERROR;
4797 }
4798
4799 /*
4800 * If this is a differential board and a single-ended device
4801 * is attached to one of the connectors, return an error.
4802 */
4803 if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) {
4804 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
4805 return ADV_ERROR;
4806 }
4807
4808 /*
4809 * If automatic termination control is enabled, then set the
4810 * termination value based on a table listed in a_condor.h.
4811 *
4812 * If manual termination was specified with an EEPROM setting
4813 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
4814 * is ready to be 'ored' into SCSI_CFG1.
4815 */
4816 if (asc_dvc->cfg->termination == 0) {
4817 /*
4818 * The software always controls termination by setting TERM_CTL_SEL.
4819 * If TERM_CTL_SEL were set to 0, the hardware would set termination.
4820 */
4821 asc_dvc->cfg->termination |= TERM_CTL_SEL;
4822
4823 switch (scsi_cfg1 & CABLE_DETECT) {
4824 /* TERM_CTL_H: on, TERM_CTL_L: on */
4825 case 0x3:
4826 case 0x7:
4827 case 0xB:
4828 case 0xD:
4829 case 0xE:
4830 case 0xF:
4831 asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
4832 break;
4833
4834 /* TERM_CTL_H: on, TERM_CTL_L: off */
4835 case 0x1:
4836 case 0x5:
4837 case 0x9:
4838 case 0xA:
4839 case 0xC:
4840 asc_dvc->cfg->termination |= TERM_CTL_H;
4841 break;
4842
4843 /* TERM_CTL_H: off, TERM_CTL_L: off */
4844 case 0x2:
4845 case 0x6:
4846 break;
4847 }
4848 }
4849
4850 /*
4851 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
4852 */
4853 scsi_cfg1 &= ~TERM_CTL;
4854
4855 /*
4856 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
4857 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
4858 * referenced, because the hardware internally inverts
4859 * the Termination High and Low bits if TERM_POL is set.
4860 */
4861 scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
4862
4863 /*
4864 * Set SCSI_CFG1 Microcode Default Value
4865 *
4866 * Set filter value and possibly modified termination control
4867 * bits in the Microcode SCSI_CFG1 Register Value.
4868 *
4869 * The microcode will set the SCSI_CFG1 register using this value
4870 * after it is started below.
4871 */
4872 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
4873 FLTR_DISABLE | scsi_cfg1);
4874
4875 /*
4876 * Set MEM_CFG Microcode Default Value
4877 *
4878 * The microcode will set the MEM_CFG register using this value
4879 * after it is started below.
4880 *
4881 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
4882 * are defined.
4883 *
4884 * ASC-3550 has 8KB internal memory.
4885 */
4886 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
4887 BIOS_EN | RAM_SZ_8KB);
4888
4889 /*
4890 * Set SEL_MASK Microcode Default Value
4891 *
4892 * The microcode will set the SEL_MASK register using this value
4893 * after it is started below.
4894 */
4895 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
4896 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
4897
4898 AdvBuildCarrierFreelist(asc_dvc);
4899
4900 /*
4901 * Set-up the Host->RISC Initiator Command Queue (ICQ).
4902 */
4903
4904 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
4905 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4906 return ADV_ERROR;
4907 }
4908 asc_dvc->carr_freelist = (ADV_CARR_T *)
4909 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
4910
4911 /*
4912 * The first command issued will be placed in the stopper carrier.
4913 */
4914 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
4915
4916 /*
4917 * Set RISC ICQ physical address start value.
4918 */
4919 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
4920
4921 /*
4922 * Set-up the RISC->Host Initiator Response Queue (IRQ).
4923 */
4924 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
4925 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4926 return ADV_ERROR;
4927 }
4928 asc_dvc->carr_freelist = (ADV_CARR_T *)
4929 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
4930
4931 /*
4932 * The first command completed by the RISC will be placed in
4933 * the stopper.
4934 *
4935 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
4936 * completed the RISC will set the ASC_RQ_STOPPER bit.
4937 */
4938 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
4939
4940 /*
4941 * Set RISC IRQ physical address start value.
4942 */
4943 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
4944 asc_dvc->carr_pending_cnt = 0;
4945
4946 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
4947 (ADV_INTR_ENABLE_HOST_INTR |
4948 ADV_INTR_ENABLE_GLOBAL_INTR));
4949
4950 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
4951 AdvWriteWordRegister(iop_base, IOPW_PC, word);
4952
4953 /* finally, finally, gentlemen, start your engine */
4954 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
4955
4956 /*
4957 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
4958 * Resets should be performed. The RISC has to be running
4959 * to issue a SCSI Bus Reset.
4960 */
4961 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
4962 /*
4963 * If the BIOS Signature is present in memory, restore the
4964 * BIOS Handshake Configuration Table and do not perform
4965 * a SCSI Bus Reset.
4966 */
4967 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
4968 0x55AA) {
4969 /*
4970 * Restore per TID negotiated values.
4971 */
4972 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4973 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4974 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
4975 tagqng_able);
4976 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4977 AdvWriteByteLram(iop_base,
4978 ASC_MC_NUMBER_OF_MAX_CMD + tid,
4979 max_cmd[tid]);
4980 }
4981 } else {
4982 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
4983 warn_code = ASC_WARN_BUSRESET_ERROR;
4984 }
4985 }
4986 }
4987
4988 return warn_code;
4989}
4990
4991/*
4992 * Initialize the ASC-38C0800.
4993 *
4994 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4995 *
4996 * For a non-fatal error return a warning code. If there are no warnings
4997 * then 0 is returned.
4998 *
4999 * Needed after initialization for error recovery.
5000 */
5001static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
5002{
989bb5f5
JSR		 5003 const struct firmware *fw;
5004 const char fwname[] = "advansys/38C0800.bin";
51219358
MW		 5005 AdvPortAddr iop_base;
5006 ushort warn_code;
5007 int begin_addr;
5008 int end_addr;
5009 ushort code_sum;
5010 int word;
5011 int i;
989bb5f5
JSR		 5012 int err;
5013 unsigned long chksum;
51219358
MW		 5014 ushort scsi_cfg1;
5015 uchar byte;
5016 uchar tid;
5017 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
5018 ushort wdtr_able, sdtr_able, tagqng_able;
5019 uchar max_cmd[ADV_MAX_TID + 1];
5020
5021 /* If there is already an error, don't continue. */
5022 if (asc_dvc->err_code != 0)
5023 return ADV_ERROR;
5024
5025 /*
5026 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
5027 */
5028 if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) {
5029 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
5030 return ADV_ERROR;
5031 }
5032
5033 warn_code = 0;
5034 iop_base = asc_dvc->iop_base;
5035
5036 /*
5037 * Save the RISC memory BIOS region before writing the microcode.
5038 * The BIOS may already be loaded and using its RISC LRAM region
5039 * so its region must be saved and restored.
5040 *
5041 * Note: This code makes the assumption, which is currently true,
5042 * that a chip reset does not clear RISC LRAM.
5043 */
5044 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5045 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5046 bios_mem[i]);
5047 }
5048
5049 /*
5050 * Save current per TID negotiated values.
5051 */
5052 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5053 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5054 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5055 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5056 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5057 max_cmd[tid]);
5058 }
5059
5060 /*
5061 * RAM BIST (RAM Built-In Self Test)
5062 *
5063 * Address : I/O base + offset 0x38h register (byte).
5064 * Function: Bit 7-6(RW) : RAM mode
5065 * Normal Mode : 0x00
5066 * Pre-test Mode : 0x40
5067 * RAM Test Mode : 0x80
5068 * Bit 5 : unused
5069 * Bit 4(RO) : Done bit
5070 * Bit 3-0(RO) : Status
5071 * Host Error : 0x08
5072 * Int_RAM Error : 0x04
5073 * RISC Error : 0x02
5074 * SCSI Error : 0x01
5075 * No Error : 0x00
5076 *
5077 * Note: RAM BIST code should be put right here, before loading the
5078 * microcode and after saving the RISC memory BIOS region.
5079 */
5080
5081 /*
5082 * LRAM Pre-test
5083 *
5084 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
5085 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
5086 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
5087 * to NORMAL_MODE, return an error too.
5088 */
5089 for (i = 0; i < 2; i++) {
5090 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
5091 mdelay(10); /* Wait for 10ms before reading back. */
5092 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5093 if ((byte & RAM_TEST_DONE) == 0
5094 || (byte & 0x0F) != PRE_TEST_VALUE) {
5095 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5096 return ADV_ERROR;
5097 }
5098
5099 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5100 mdelay(10); /* Wait for 10ms before reading back. */
5101 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
5102 != NORMAL_VALUE) {
5103 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5104 return ADV_ERROR;
5105 }
5106 }
5107
5108 /*
5109 * LRAM Test - It takes about 1.5 ms to run through the test.
5110 *
5111 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
5112 * If Done bit not set or Status not 0, save register byte, set the
5113 * err_code, and return an error.
5114 */
5115 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
5116 mdelay(10); /* Wait for 10ms before checking status. */
5117
5118 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5119 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
5120 /* Get here if Done bit not set or Status not 0. */
5121 asc_dvc->bist_err_code = byte; /* for BIOS display message */
5122 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
5123 return ADV_ERROR;
5124 }
5125
5126 /* We need to reset back to normal mode after LRAM test passes. */
5127 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5128
989bb5f5
JSR		 5129 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5130 if (err) {
5131 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5132 fwname, err);
cf747445 5133 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 5134 return err;
5135 }
5136 if (fw->size < 4) {
5137 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5138 fw->size, fwname);
5139 release_firmware(fw);
cf747445 5140 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 5141 return -EINVAL;
5142 }
5143 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5144 (fw->data[1] << 8) | fw->data[0];
5145 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5146 fw->size - 4, ADV_38C0800_MEMSIZE,
5147 chksum);
5148 release_firmware(fw);
51219358
MW		 5149 if (asc_dvc->err_code)
5150 return ADV_ERROR;
5151
5152 /*
5153 * Restore the RISC memory BIOS region.
5154 */
5155 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5156 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5157 bios_mem[i]);
5158 }
5159
5160 /*
5161 * Calculate and write the microcode code checksum to the microcode
5162 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5163 */
5164 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5165 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5166 code_sum = 0;
5167 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5168 for (word = begin_addr; word < end_addr; word += 2) {
5169 code_sum += AdvReadWordAutoIncLram(iop_base);
5170 }
5171 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5172
5173 /*
5174 * Read microcode version and date.
5175 */
5176 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5177 asc_dvc->cfg->mcode_date);
5178 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5179 asc_dvc->cfg->mcode_version);
5180
5181 /*
5182 * Set the chip type to indicate the ASC38C0800.
5183 */
5184 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
5185
5186 /*
5187 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5188 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5189 * cable detection and then we are able to read C_DET[3:0].
5190 *
5191 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5192 * Microcode Default Value' section below.
5193 */
5194 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5195 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5196 scsi_cfg1 | DIS_TERM_DRV);
5197
5198 /*
5199 * If the PCI Configuration Command Register "Parity Error Response
5200 * Control" Bit was clear (0), then set the microcode variable
5201 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5202 * to ignore DMA parity errors.
5203 */
5204 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5205 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5206 word |= CONTROL_FLAG_IGNORE_PERR;
5207 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5208 }
5209
5210 /*
5211 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
5212 * bits for the default FIFO threshold.
5213 *
5214 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
5215 *
5216 * For DMA Errata #4 set the BC_THRESH_ENB bit.
5217 */
5218 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5219 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH |
5220 READ_CMD_MRM);
5221
5222 /*
5223 * Microcode operating variables for WDTR, SDTR, and command tag
5224 * queuing will be set in slave_configure() based on what a
5225 * device reports it is capable of in Inquiry byte 7.
5226 *
5227 * If SCSI Bus Resets have been disabled, then directly set
5228 * SDTR and WDTR from the EEPROM configuration. This will allow
5229 * the BIOS and warm boot to work without a SCSI bus hang on
5230 * the Inquiry caused by host and target mismatched DTR values.
5231 * Without the SCSI Bus Reset, before an Inquiry a device can't
5232 * be assumed to be in Asynchronous, Narrow mode.
5233 */
5234 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5235 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5236 asc_dvc->wdtr_able);
5237 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5238 asc_dvc->sdtr_able);
5239 }
5240
5241 /*
5242 * Set microcode operating variables for DISC and SDTR_SPEED1,
5243 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5244 * configuration values.
5245 *
5246 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5247 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5248 * without determining here whether the device supports SDTR.
5249 */
5250 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5251 asc_dvc->cfg->disc_enable);
5252 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5253 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5254 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5255 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5256
5257 /*
5258 * Set SCSI_CFG0 Microcode Default Value.
5259 *
5260 * The microcode will set the SCSI_CFG0 register using this value
5261 * after it is started below.
5262 */
5263 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5264 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5265 asc_dvc->chip_scsi_id);
5266
5267 /*
5268 * Determine SCSI_CFG1 Microcode Default Value.
5269 *
5270 * The microcode will set the SCSI_CFG1 register using this value
5271 * after it is started below.
5272 */
5273
5274 /* Read current SCSI_CFG1 Register value. */
5275 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5276
5277 /*
5278 * If the internal narrow cable is reversed all of the SCSI_CTRL
5279 * register signals will be set. Check for and return an error if
5280 * this condition is found.
5281 */
5282 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5283 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5284 return ADV_ERROR;
5285 }
5286
5287 /*
5288 * All kind of combinations of devices attached to one of four
5289 * connectors are acceptable except HVD device attached. For example,
5290 * LVD device can be attached to SE connector while SE device attached
5291 * to LVD connector. If LVD device attached to SE connector, it only
5292 * runs up to Ultra speed.
5293 *
5294 * If an HVD device is attached to one of LVD connectors, return an
5295 * error. However, there is no way to detect HVD device attached to
5296 * SE connectors.
5297 */
5298 if (scsi_cfg1 & HVD) {
5299 asc_dvc->err_code = ASC_IERR_HVD_DEVICE;
5300 return ADV_ERROR;
5301 }
5302
5303 /*
5304 * If either SE or LVD automatic termination control is enabled, then
5305 * set the termination value based on a table listed in a_condor.h.
5306 *
5307 * If manual termination was specified with an EEPROM setting then
5308 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready
5309 * to be 'ored' into SCSI_CFG1.
5310 */
5311 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5312 /* SE automatic termination control is enabled. */
5313 switch (scsi_cfg1 & C_DET_SE) {
5314 /* TERM_SE_HI: on, TERM_SE_LO: on */
5315 case 0x1:
5316 case 0x2:
5317 case 0x3:
5318 asc_dvc->cfg->termination |= TERM_SE;
5319 break;
5320
5321 /* TERM_SE_HI: on, TERM_SE_LO: off */
5322 case 0x0:
5323 asc_dvc->cfg->termination |= TERM_SE_HI;
5324 break;
5325 }
5326 }
5327
5328 if ((asc_dvc->cfg->termination & TERM_LVD) == 0) {
5329 /* LVD automatic termination control is enabled. */
5330 switch (scsi_cfg1 & C_DET_LVD) {
5331 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
5332 case 0x4:
5333 case 0x8:
5334 case 0xC:
5335 asc_dvc->cfg->termination |= TERM_LVD;
5336 break;
5337
5338 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
5339 case 0x0:
5340 break;
5341 }
5342 }
5343
5344 /*
5345 * Clear any set TERM_SE and TERM_LVD bits.
5346 */
5347 scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
5348
5349 /*
5350 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
5351 */
5352 scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
5353
5354 /*
5355 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE
5356 * bits and set possibly modified termination control bits in the
5357 * Microcode SCSI_CFG1 Register Value.
5358 */
5359 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
5360
5361 /*
5362 * Set SCSI_CFG1 Microcode Default Value
5363 *
5364 * Set possibly modified termination control and reset DIS_TERM_DRV
5365 * bits in the Microcode SCSI_CFG1 Register Value.
5366 *
5367 * The microcode will set the SCSI_CFG1 register using this value
5368 * after it is started below.
5369 */
5370 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5371
5372 /*
5373 * Set MEM_CFG Microcode Default Value
5374 *
5375 * The microcode will set the MEM_CFG register using this value
5376 * after it is started below.
5377 *
5378 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5379 * are defined.
5380 *
5381 * ASC-38C0800 has 16KB internal memory.
5382 */
5383 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5384 BIOS_EN | RAM_SZ_16KB);
5385
5386 /*
5387 * Set SEL_MASK Microcode Default Value
5388 *
5389 * The microcode will set the SEL_MASK register using this value
5390 * after it is started below.
5391 */
5392 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5393 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5394
5395 AdvBuildCarrierFreelist(asc_dvc);
5396
5397 /*
5398 * Set-up the Host->RISC Initiator Command Queue (ICQ).
5399 */
5400
5401 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
5402 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5403 return ADV_ERROR;
5404 }
5405 asc_dvc->carr_freelist = (ADV_CARR_T *)
5406 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
5407
5408 /*
5409 * The first command issued will be placed in the stopper carrier.
5410 */
5411 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
5412
5413 /*
5414 * Set RISC ICQ physical address start value.
5415 * carr_pa is LE, must be native before write
5416 */
5417 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5418
5419 /*
5420 * Set-up the RISC->Host Initiator Response Queue (IRQ).
5421 */
5422 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
5423 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5424 return ADV_ERROR;
5425 }
5426 asc_dvc->carr_freelist = (ADV_CARR_T *)
5427 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
5428
5429 /*
5430 * The first command completed by the RISC will be placed in
5431 * the stopper.
5432 *
5433 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
5434 * completed the RISC will set the ASC_RQ_STOPPER bit.
5435 */
5436 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
5437
5438 /*
5439 * Set RISC IRQ physical address start value.
5440 *
5441 * carr_pa is LE, must be native before write *
5442 */
5443 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5444 asc_dvc->carr_pending_cnt = 0;
5445
5446 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5447 (ADV_INTR_ENABLE_HOST_INTR |
5448 ADV_INTR_ENABLE_GLOBAL_INTR));
5449
5450 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5451 AdvWriteWordRegister(iop_base, IOPW_PC, word);
5452
5453 /* finally, finally, gentlemen, start your engine */
5454 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5455
5456 /*
5457 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5458 * Resets should be performed. The RISC has to be running
5459 * to issue a SCSI Bus Reset.
5460 */
5461 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5462 /*
5463 * If the BIOS Signature is present in memory, restore the
5464 * BIOS Handshake Configuration Table and do not perform
5465 * a SCSI Bus Reset.
5466 */
5467 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5468 0x55AA) {
5469 /*
5470 * Restore per TID negotiated values.
5471 */
5472 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5473 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5474 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5475 tagqng_able);
5476 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5477 AdvWriteByteLram(iop_base,
5478 ASC_MC_NUMBER_OF_MAX_CMD + tid,
5479 max_cmd[tid]);
5480 }
5481 } else {
5482 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5483 warn_code = ASC_WARN_BUSRESET_ERROR;
5484 }
5485 }
5486 }
5487
5488 return warn_code;
5489}
5490
5491/*
5492 * Initialize the ASC-38C1600.
5493 *
5494 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
5495 *
5496 * For a non-fatal error return a warning code. If there are no warnings
5497 * then 0 is returned.
5498 *
5499 * Needed after initialization for error recovery.
5500 */
5501static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
5502{
989bb5f5
JSR		 5503 const struct firmware *fw;
5504 const char fwname[] = "advansys/38C1600.bin";
51219358
MW		 5505 AdvPortAddr iop_base;
5506 ushort warn_code;
5507 int begin_addr;
5508 int end_addr;
5509 ushort code_sum;
5510 long word;
5511 int i;
989bb5f5
JSR		 5512 int err;
5513 unsigned long chksum;
51219358
MW		 5514 ushort scsi_cfg1;
5515 uchar byte;
5516 uchar tid;
5517 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
5518 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
5519 uchar max_cmd[ASC_MAX_TID + 1];
5520
5521 /* If there is already an error, don't continue. */
5522 if (asc_dvc->err_code != 0) {
5523 return ADV_ERROR;
5524 }
5525
5526 /*
5527 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
5528 */
5529 if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
5530 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
5531 return ADV_ERROR;
5532 }
5533
5534 warn_code = 0;
5535 iop_base = asc_dvc->iop_base;
5536
5537 /*
5538 * Save the RISC memory BIOS region before writing the microcode.
5539 * The BIOS may already be loaded and using its RISC LRAM region
5540 * so its region must be saved and restored.
5541 *
5542 * Note: This code makes the assumption, which is currently true,
5543 * that a chip reset does not clear RISC LRAM.
5544 */
5545 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5546 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5547 bios_mem[i]);
5548 }
5549
5550 /*
5551 * Save current per TID negotiated values.
5552 */
5553 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5554 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5555 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5556 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5557 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
5558 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5559 max_cmd[tid]);
5560 }
5561
5562 /*
5563 * RAM BIST (Built-In Self Test)
5564 *
5565 * Address : I/O base + offset 0x38h register (byte).
5566 * Function: Bit 7-6(RW) : RAM mode
5567 * Normal Mode : 0x00
5568 * Pre-test Mode : 0x40
5569 * RAM Test Mode : 0x80
5570 * Bit 5 : unused
5571 * Bit 4(RO) : Done bit
5572 * Bit 3-0(RO) : Status
5573 * Host Error : 0x08
5574 * Int_RAM Error : 0x04
5575 * RISC Error : 0x02
5576 * SCSI Error : 0x01
5577 * No Error : 0x00
5578 *
5579 * Note: RAM BIST code should be put right here, before loading the
5580 * microcode and after saving the RISC memory BIOS region.
5581 */
5582
5583 /*
5584 * LRAM Pre-test
5585 *
5586 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
5587 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
5588 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
5589 * to NORMAL_MODE, return an error too.
5590 */
5591 for (i = 0; i < 2; i++) {
5592 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
5593 mdelay(10); /* Wait for 10ms before reading back. */
5594 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5595 if ((byte & RAM_TEST_DONE) == 0
5596 || (byte & 0x0F) != PRE_TEST_VALUE) {
5597 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5598 return ADV_ERROR;
5599 }
5600
5601 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5602 mdelay(10); /* Wait for 10ms before reading back. */
5603 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
5604 != NORMAL_VALUE) {
5605 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5606 return ADV_ERROR;
5607 }
5608 }
5609
5610 /*
5611 * LRAM Test - It takes about 1.5 ms to run through the test.
5612 *
5613 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
5614 * If Done bit not set or Status not 0, save register byte, set the
5615 * err_code, and return an error.
5616 */
5617 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
5618 mdelay(10); /* Wait for 10ms before checking status. */
5619
5620 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5621 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
5622 /* Get here if Done bit not set or Status not 0. */
5623 asc_dvc->bist_err_code = byte; /* for BIOS display message */
5624 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
5625 return ADV_ERROR;
5626 }
5627
5628 /* We need to reset back to normal mode after LRAM test passes. */
5629 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5630
989bb5f5
JSR		 5631 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5632 if (err) {
5633 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5634 fwname, err);
cf747445 5635 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 5636 return err;
5637 }
5638 if (fw->size < 4) {
5639 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5640 fw->size, fwname);
5641 release_firmware(fw);
cf747445 5642 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 5643 return -EINVAL;
5644 }
5645 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5646 (fw->data[1] << 8) | fw->data[0];
5647 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5648 fw->size - 4, ADV_38C1600_MEMSIZE,
5649 chksum);
5650 release_firmware(fw);
51219358
MW		 5651 if (asc_dvc->err_code)
5652 return ADV_ERROR;
5653
5654 /*
5655 * Restore the RISC memory BIOS region.
5656 */
5657 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5658 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5659 bios_mem[i]);
5660 }
5661
5662 /*
5663 * Calculate and write the microcode code checksum to the microcode
5664 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5665 */
5666 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5667 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5668 code_sum = 0;
5669 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5670 for (word = begin_addr; word < end_addr; word += 2) {
5671 code_sum += AdvReadWordAutoIncLram(iop_base);
5672 }
5673 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5674
5675 /*
5676 * Read microcode version and date.
5677 */
5678 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5679 asc_dvc->cfg->mcode_date);
5680 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5681 asc_dvc->cfg->mcode_version);
5682
5683 /*
5684 * Set the chip type to indicate the ASC38C1600.
5685 */
5686 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
5687
5688 /*
5689 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5690 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5691 * cable detection and then we are able to read C_DET[3:0].
5692 *
5693 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5694 * Microcode Default Value' section below.
5695 */
5696 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5697 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5698 scsi_cfg1 | DIS_TERM_DRV);
5699
5700 /*
5701 * If the PCI Configuration Command Register "Parity Error Response
5702 * Control" Bit was clear (0), then set the microcode variable
5703 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5704 * to ignore DMA parity errors.
5705 */
5706 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5707 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5708 word |= CONTROL_FLAG_IGNORE_PERR;
5709 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5710 }
5711
5712 /*
5713 * If the BIOS control flag AIPP (Asynchronous Information
5714 * Phase Protection) disable bit is not set, then set the firmware
5715 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
5716 * AIPP checking and encoding.
5717 */
5718 if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
5719 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5720 word |= CONTROL_FLAG_ENABLE_AIPP;
5721 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5722 }
5723
5724 /*
5725 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
5726 * and START_CTL_TH [3:2].
5727 */
5728 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5729 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
5730
5731 /*
5732 * Microcode operating variables for WDTR, SDTR, and command tag
5733 * queuing will be set in slave_configure() based on what a
5734 * device reports it is capable of in Inquiry byte 7.
5735 *
5736 * If SCSI Bus Resets have been disabled, then directly set
5737 * SDTR and WDTR from the EEPROM configuration. This will allow
5738 * the BIOS and warm boot to work without a SCSI bus hang on
5739 * the Inquiry caused by host and target mismatched DTR values.
5740 * Without the SCSI Bus Reset, before an Inquiry a device can't
5741 * be assumed to be in Asynchronous, Narrow mode.
5742 */
5743 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5744 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5745 asc_dvc->wdtr_able);
5746 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5747 asc_dvc->sdtr_able);
5748 }
5749
5750 /*
5751 * Set microcode operating variables for DISC and SDTR_SPEED1,
5752 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5753 * configuration values.
5754 *
5755 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5756 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5757 * without determining here whether the device supports SDTR.
5758 */
5759 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5760 asc_dvc->cfg->disc_enable);
5761 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5762 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5763 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5764 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5765
5766 /*
5767 * Set SCSI_CFG0 Microcode Default Value.
5768 *
5769 * The microcode will set the SCSI_CFG0 register using this value
5770 * after it is started below.
5771 */
5772 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5773 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5774 asc_dvc->chip_scsi_id);
5775
5776 /*
5777 * Calculate SCSI_CFG1 Microcode Default Value.
5778 *
5779 * The microcode will set the SCSI_CFG1 register using this value
5780 * after it is started below.
5781 *
5782 * Each ASC-38C1600 function has only two cable detect bits.
5783 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
5784 */
5785 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5786
5787 /*
5788 * If the cable is reversed all of the SCSI_CTRL register signals
5789 * will be set. Check for and return an error if this condition is
5790 * found.
5791 */
5792 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5793 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5794 return ADV_ERROR;
5795 }
5796
5797 /*
5798 * Each ASC-38C1600 function has two connectors. Only an HVD device
5799 * can not be connected to either connector. An LVD device or SE device
5800 * may be connected to either connecor. If an SE device is connected,
5801 * then at most Ultra speed (20 Mhz) can be used on both connectors.
5802 *
5803 * If an HVD device is attached, return an error.
5804 */
5805 if (scsi_cfg1 & HVD) {
5806 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
5807 return ADV_ERROR;
5808 }
5809
5810 /*
5811 * Each function in the ASC-38C1600 uses only the SE cable detect and
5812 * termination because there are two connectors for each function. Each
5813 * function may use either LVD or SE mode. Corresponding the SE automatic
5814 * termination control EEPROM bits are used for each function. Each
5815 * function has its own EEPROM. If SE automatic control is enabled for
5816 * the function, then set the termination value based on a table listed
5817 * in a_condor.h.
5818 *
5819 * If manual termination is specified in the EEPROM for the function,
5820 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
5821 * ready to be 'ored' into SCSI_CFG1.
5822 */
5823 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5824 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
5825 /* SE automatic termination control is enabled. */
5826 switch (scsi_cfg1 & C_DET_SE) {
5827 /* TERM_SE_HI: on, TERM_SE_LO: on */
5828 case 0x1:
5829 case 0x2:
5830 case 0x3:
5831 asc_dvc->cfg->termination |= TERM_SE;
5832 break;
5833
5834 case 0x0:
5835 if (PCI_FUNC(pdev->devfn) == 0) {
5836 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
5837 } else {
5838 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
5839 asc_dvc->cfg->termination |= TERM_SE_HI;
5840 }
5841 break;
5842 }
5843 }
5844
5845 /*
5846 * Clear any set TERM_SE bits.
5847 */
5848 scsi_cfg1 &= ~TERM_SE;
5849
5850 /*
5851 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
5852 */
5853 scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
5854
5855 /*
5856 * Clear Big Endian and Terminator Polarity bits and set possibly
5857 * modified termination control bits in the Microcode SCSI_CFG1
5858 * Register Value.
5859 *
5860 * Big Endian bit is not used even on big endian machines.
5861 */
5862 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
5863
5864 /*
5865 * Set SCSI_CFG1 Microcode Default Value
5866 *
5867 * Set possibly modified termination control bits in the Microcode
5868 * SCSI_CFG1 Register Value.
5869 *
5870 * The microcode will set the SCSI_CFG1 register using this value
5871 * after it is started below.
5872 */
5873 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5874
5875 /*
5876 * Set MEM_CFG Microcode Default Value
5877 *
5878 * The microcode will set the MEM_CFG register using this value
5879 * after it is started below.
5880 *
5881 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5882 * are defined.
5883 *
5884 * ASC-38C1600 has 32KB internal memory.
5885 *
5886 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
5887 * out a special 16K Adv Library and Microcode version. After the issue
5888 * resolved, we should turn back to the 32K support. Both a_condor.h and
5889 * mcode.sas files also need to be updated.
5890 *
5891 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5892 * BIOS_EN | RAM_SZ_32KB);
5893 */
5894 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5895 BIOS_EN | RAM_SZ_16KB);
5896
5897 /*
5898 * Set SEL_MASK Microcode Default Value
5899 *
5900 * The microcode will set the SEL_MASK register using this value
5901 * after it is started below.
5902 */
5903 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5904 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5905
5906 AdvBuildCarrierFreelist(asc_dvc);
5907
5908 /*
5909 * Set-up the Host->RISC Initiator Command Queue (ICQ).
5910 */
5911 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) {
5912 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5913 return ADV_ERROR;
5914 }
5915 asc_dvc->carr_freelist = (ADV_CARR_T *)
5916 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
5917
5918 /*
5919 * The first command issued will be placed in the stopper carrier.
5920 */
5921 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
5922
5923 /*
5924 * Set RISC ICQ physical address start value. Initialize the
5925 * COMMA register to the same value otherwise the RISC will
5926 * prematurely detect a command is available.
5927 */
5928 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5929 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
5930 le32_to_cpu(asc_dvc->icq_sp->carr_pa));
5931
5932 /*
5933 * Set-up the RISC->Host Initiator Response Queue (IRQ).
5934 */
5935 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) {
5936 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5937 return ADV_ERROR;
5938 }
5939 asc_dvc->carr_freelist = (ADV_CARR_T *)
5940 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
5941
5942 /*
5943 * The first command completed by the RISC will be placed in
5944 * the stopper.
5945 *
5946 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
5947 * completed the RISC will set the ASC_RQ_STOPPER bit.
5948 */
5949 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
5950
5951 /*
5952 * Set RISC IRQ physical address start value.
5953 */
5954 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5955 asc_dvc->carr_pending_cnt = 0;
5956
5957 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5958 (ADV_INTR_ENABLE_HOST_INTR |
5959 ADV_INTR_ENABLE_GLOBAL_INTR));
5960 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5961 AdvWriteWordRegister(iop_base, IOPW_PC, word);
5962
5963 /* finally, finally, gentlemen, start your engine */
5964 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5965
5966 /*
5967 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5968 * Resets should be performed. The RISC has to be running
5969 * to issue a SCSI Bus Reset.
5970 */
5971 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5972 /*
5973 * If the BIOS Signature is present in memory, restore the
5974 * per TID microcode operating variables.
5975 */
5976 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5977 0x55AA) {
5978 /*
5979 * Restore per TID negotiated values.
5980 */
5981 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5982 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5983 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5984 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5985 tagqng_able);
5986 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
5987 AdvWriteByteLram(iop_base,
5988 ASC_MC_NUMBER_OF_MAX_CMD + tid,
5989 max_cmd[tid]);
5990 }
5991 } else {
5992 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5993 warn_code = ASC_WARN_BUSRESET_ERROR;
5994 }
5995 }
5996 }
5997
5998 return warn_code;
5999}
6000
6001/*
6002 * Reset chip and SCSI Bus.
6003 *
6004 * Return Value:
6005 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
6006 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
6007 */
6008static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
6009{
6010 int status;
6011 ushort wdtr_able, sdtr_able, tagqng_able;
6012 ushort ppr_able = 0;
6013 uchar tid, max_cmd[ADV_MAX_TID + 1];
6014 AdvPortAddr iop_base;
6015 ushort bios_sig;
6016
6017 iop_base = asc_dvc->iop_base;
6018
6019 /*
6020 * Save current per TID negotiated values.
6021 */
6022 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
6023 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
6024 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
6025 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
6026 }
6027 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
6028 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
6029 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
6030 max_cmd[tid]);
6031 }
6032
6033 /*
6034 * Force the AdvInitAsc3550/38C0800Driver() function to
6035 * perform a SCSI Bus Reset by clearing the BIOS signature word.
6036 * The initialization functions assumes a SCSI Bus Reset is not
6037 * needed if the BIOS signature word is present.
6038 */
6039 AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
6040 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
6041
6042 /*
6043 * Stop chip and reset it.
6044 */
6045 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
6046 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
6047 mdelay(100);
6048 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
6049 ADV_CTRL_REG_CMD_WR_IO_REG);
6050
6051 /*
6052 * Reset Adv Library error code, if any, and try
6053 * re-initializing the chip.
6054 */
6055 asc_dvc->err_code = 0;
6056 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
6057 status = AdvInitAsc38C1600Driver(asc_dvc);
6058 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
6059 status = AdvInitAsc38C0800Driver(asc_dvc);
6060 } else {
6061 status = AdvInitAsc3550Driver(asc_dvc);
6062 }
6063
6064 /* Translate initialization return value to status value. */
6065 if (status == 0) {
6066 status = ADV_TRUE;
6067 } else {
6068 status = ADV_FALSE;
6069 }
6070
6071 /*
6072 * Restore the BIOS signature word.
6073 */
6074 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
6075
6076 /*
6077 * Restore per TID negotiated values.
6078 */
6079 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
6080 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
6081 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
6082 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
6083 }
6084 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
6085 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
6086 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
6087 max_cmd[tid]);
6088 }
6089
6090 return status;
6091}
6092
6093/*
6094 * adv_async_callback() - Adv Library asynchronous event callback function.
6095 */
6096static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
6097{
6098 switch (code) {
6099 case ADV_ASYNC_SCSI_BUS_RESET_DET:
6100 /*
6101 * The firmware detected a SCSI Bus reset.
6102 */
b352f923 6103 ASC_DBG(0, "ADV_ASYNC_SCSI_BUS_RESET_DET\n");
51219358
MW		 6104 break;
6105
6106 case ADV_ASYNC_RDMA_FAILURE:
6107 /*
6108 * Handle RDMA failure by resetting the SCSI Bus and
6109 * possibly the chip if it is unresponsive. Log the error
6110 * with a unique code.
6111 */
b352f923 6112 ASC_DBG(0, "ADV_ASYNC_RDMA_FAILURE\n");
51219358
MW		 6113 AdvResetChipAndSB(adv_dvc_varp);
6114 break;
6115
6116 case ADV_HOST_SCSI_BUS_RESET:
6117 /*
6118 * Host generated SCSI bus reset occurred.
6119 */
b352f923 6120 ASC_DBG(0, "ADV_HOST_SCSI_BUS_RESET\n");
51219358
MW		 6121 break;
6122
6123 default:
b352f923 6124 ASC_DBG(0, "unknown code 0x%x\n", code);
51219358
MW		 6125 break;
6126 }
6127}
6128
6129/*
6130 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
6131 *
6132 * Callback function for the Wide SCSI Adv Library.
6133 */
6134static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
6135{
d2411495 6136 struct asc_board *boardp;
51219358
MW		 6137 adv_req_t *reqp;
6138 adv_sgblk_t *sgblkp;
6139 struct scsi_cmnd *scp;
6140 struct Scsi_Host *shost;
6141 ADV_DCNT resid_cnt;
6142
b352f923 6143 ASC_DBG(1, "adv_dvc_varp 0x%lx, scsiqp 0x%lx\n",
51219358
MW		 6144 (ulong)adv_dvc_varp, (ulong)scsiqp);
6145 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
6146
6147 /*
6148 * Get the adv_req_t structure for the command that has been
6149 * completed. The adv_req_t structure actually contains the
6150 * completed ADV_SCSI_REQ_Q structure.
6151 */
6152 reqp = (adv_req_t *)ADV_U32_TO_VADDR(scsiqp->srb_ptr);
b352f923 6153 ASC_DBG(1, "reqp 0x%lx\n", (ulong)reqp);
51219358
MW		 6154 if (reqp == NULL) {
6155 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
6156 return;
6157 }
6158
6159 /*
6160 * Get the struct scsi_cmnd structure and Scsi_Host structure for the
6161 * command that has been completed.
6162 *
6163 * Note: The adv_req_t request structure and adv_sgblk_t structure,
6164 * if any, are dropped, because a board structure pointer can not be
6165 * determined.
6166 */
6167 scp = reqp->cmndp;
b352f923 6168 ASC_DBG(1, "scp 0x%p\n", scp);
51219358
MW		 6169 if (scp == NULL) {
6170 ASC_PRINT
6171 ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
6172 return;
6173 }
6174 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
6175
6176 shost = scp->device->host;
6177 ASC_STATS(shost, callback);
b352f923 6178 ASC_DBG(1, "shost 0x%p\n", shost);
51219358 6179
d2411495 6180 boardp = shost_priv(shost);
51219358
MW		 6181 BUG_ON(adv_dvc_varp != &boardp->dvc_var.adv_dvc_var);
6182
6183 /*
6184 * 'done_status' contains the command's ending status.
6185 */
6186 switch (scsiqp->done_status) {
6187 case QD_NO_ERROR:
b352f923 6188 ASC_DBG(2, "QD_NO_ERROR\n");
51219358
MW		 6189 scp->result = 0;
6190
6191 /*
6192 * Check for an underrun condition.
6193 *
6194 * If there was no error and an underrun condition, then
6195 * then return the number of underrun bytes.
6196 */
6197 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
52c334e9
MW		 6198 if (scsi_bufflen(scp) != 0 && resid_cnt != 0 &&
6199 resid_cnt <= scsi_bufflen(scp)) {
b352f923 6200 ASC_DBG(1, "underrun condition %lu bytes\n",
51219358 6201 (ulong)resid_cnt);
52c334e9 6202 scsi_set_resid(scp, resid_cnt);
51219358
MW		 6203 }
6204 break;
6205
6206 case QD_WITH_ERROR:
b352f923 6207 ASC_DBG(2, "QD_WITH_ERROR\n");
51219358
MW		 6208 switch (scsiqp->host_status) {
6209 case QHSTA_NO_ERROR:
6210 if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
b352f923 6211 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
51219358 6212 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
b80ca4f7 6213 SCSI_SENSE_BUFFERSIZE);
51219358
MW		 6214 /*
6215 * Note: The 'status_byte()' macro used by
6216 * target drivers defined in scsi.h shifts the
6217 * status byte returned by host drivers right
6218 * by 1 bit. This is why target drivers also
6219 * use right shifted status byte definitions.
6220 * For instance target drivers use
6221 * CHECK_CONDITION, defined to 0x1, instead of
6222 * the SCSI defined check condition value of
6223 * 0x2. Host drivers are supposed to return
6224 * the status byte as it is defined by SCSI.
6225 */
6226 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
6227 STATUS_BYTE(scsiqp->scsi_status);
6228 } else {
6229 scp->result = STATUS_BYTE(scsiqp->scsi_status);
6230 }
6231 break;
6232
6233 default:
6234 /* Some other QHSTA error occurred. */
b352f923 6235 ASC_DBG(1, "host_status 0x%x\n", scsiqp->host_status);
51219358
MW		 6236 scp->result = HOST_BYTE(DID_BAD_TARGET);
6237 break;
6238 }
6239 break;
6240
6241 case QD_ABORTED_BY_HOST:
b352f923 6242 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
51219358
MW		 6243 scp->result =
6244 HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
6245 break;
6246
6247 default:
b352f923 6248 ASC_DBG(1, "done_status 0x%x\n", scsiqp->done_status);
51219358
MW		 6249 scp->result =
6250 HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
6251 break;
6252 }
6253
6254 /*
6255 * If the 'init_tidmask' bit isn't already set for the target and the
6256 * current request finished normally, then set the bit for the target
6257 * to indicate that a device is present.
6258 */
6259 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
6260 scsiqp->done_status == QD_NO_ERROR &&
6261 scsiqp->host_status == QHSTA_NO_ERROR) {
6262 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
6263 }
6264
6265 asc_scsi_done(scp);
6266
6267 /*
6268 * Free all 'adv_sgblk_t' structures allocated for the request.
6269 */
6270 while ((sgblkp = reqp->sgblkp) != NULL) {
6271 /* Remove 'sgblkp' from the request list. */
6272 reqp->sgblkp = sgblkp->next_sgblkp;
6273
6274 /* Add 'sgblkp' to the board free list. */
6275 sgblkp->next_sgblkp = boardp->adv_sgblkp;
6276 boardp->adv_sgblkp = sgblkp;
6277 }
6278
6279 /*
6280 * Free the adv_req_t structure used with the command by adding
6281 * it back to the board free list.
6282 */
6283 reqp->next_reqp = boardp->adv_reqp;
6284 boardp->adv_reqp = reqp;
6285
b352f923 6286 ASC_DBG(1, "done\n");
51219358
MW		 6287}
6288
6289/*
6290 * Adv Library Interrupt Service Routine
6291 *
6292 * This function is called by a driver's interrupt service routine.
6293 * The function disables and re-enables interrupts.
6294 *
6295 * When a microcode idle command is completed, the ADV_DVC_VAR
6296 * 'idle_cmd_done' field is set to ADV_TRUE.
6297 *
6298 * Note: AdvISR() can be called when interrupts are disabled or even
6299 * when there is no hardware interrupt condition present. It will
6300 * always check for completed idle commands and microcode requests.
6301 * This is an important feature that shouldn't be changed because it
6302 * allows commands to be completed from polling mode loops.
6303 *
6304 * Return:
6305 * ADV_TRUE(1) - interrupt was pending
6306 * ADV_FALSE(0) - no interrupt was pending
6307 */
6308static int AdvISR(ADV_DVC_VAR *asc_dvc)
6309{
6310 AdvPortAddr iop_base;
6311 uchar int_stat;
6312 ushort target_bit;
6313 ADV_CARR_T *free_carrp;
6314 ADV_VADDR irq_next_vpa;
6315 ADV_SCSI_REQ_Q *scsiq;
6316
6317 iop_base = asc_dvc->iop_base;
6318
6319 /* Reading the register clears the interrupt. */
6320 int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
6321
6322 if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
6323 ADV_INTR_STATUS_INTRC)) == 0) {
6324 return ADV_FALSE;
6325 }
6326
6327 /*
6328 * Notify the driver of an asynchronous microcode condition by
6329 * calling the adv_async_callback function. The function
6330 * is passed the microcode ASC_MC_INTRB_CODE byte value.
6331 */
6332 if (int_stat & ADV_INTR_STATUS_INTRB) {
6333 uchar intrb_code;
6334
6335 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
6336
6337 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
6338 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
6339 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
6340 asc_dvc->carr_pending_cnt != 0) {
6341 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
6342 ADV_TICKLE_A);
6343 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
6344 AdvWriteByteRegister(iop_base,
6345 IOPB_TICKLE,
6346 ADV_TICKLE_NOP);
6347 }
6348 }
6349 }
6350
6351 adv_async_callback(asc_dvc, intrb_code);
6352 }
6353
6354 /*
6355 * Check if the IRQ stopper carrier contains a completed request.
6356 */
6357 while (((irq_next_vpa =
6358 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0) {
6359 /*
6360 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
6361 * The RISC will have set 'areq_vpa' to a virtual address.
6362 *
6363 * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr
6364 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
6365 * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr'
6366 * in AdvExeScsiQueue().
6367 */
6368 scsiq = (ADV_SCSI_REQ_Q *)
6369 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->areq_vpa));
6370
6371 /*
6372 * Request finished with good status and the queue was not
6373 * DMAed to host memory by the firmware. Set all status fields
6374 * to indicate good status.
6375 */
6376 if ((irq_next_vpa & ASC_RQ_GOOD) != 0) {
6377 scsiq->done_status = QD_NO_ERROR;
6378 scsiq->host_status = scsiq->scsi_status = 0;
6379 scsiq->data_cnt = 0L;
6380 }
6381
6382 /*
6383 * Advance the stopper pointer to the next carrier
6384 * ignoring the lower four bits. Free the previous
6385 * stopper carrier.
6386 */
6387 free_carrp = asc_dvc->irq_sp;
6388 asc_dvc->irq_sp = (ADV_CARR_T *)
6389 ADV_U32_TO_VADDR(ASC_GET_CARRP(irq_next_vpa));
6390
6391 free_carrp->next_vpa =
6392 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
6393 asc_dvc->carr_freelist = free_carrp;
6394 asc_dvc->carr_pending_cnt--;
6395
6396 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
6397
6398 /*
6399 * Clear request microcode control flag.
6400 */
6401 scsiq->cntl = 0;
6402
6403 /*
6404 * Notify the driver of the completed request by passing
6405 * the ADV_SCSI_REQ_Q pointer to its callback function.
6406 */
6407 scsiq->a_flag |= ADV_SCSIQ_DONE;
6408 adv_isr_callback(asc_dvc, scsiq);
6409 /*
6410 * Note: After the driver callback function is called, 'scsiq'
6411 * can no longer be referenced.
6412 *
6413 * Fall through and continue processing other completed
6414 * requests...
6415 */
6416 }
6417 return ADV_TRUE;
6418}
6419
6420static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code)
6421{
6422 if (asc_dvc->err_code == 0) {
6423 asc_dvc->err_code = err_code;
6424 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
6425 err_code);
6426 }
6427 return err_code;
6428}
6429
6430static void AscAckInterrupt(PortAddr iop_base)
6431{
6432 uchar host_flag;
6433 uchar risc_flag;
6434 ushort loop;
6435
6436 loop = 0;
6437 do {
6438 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
6439 if (loop++ > 0x7FFF) {
6440 break;
6441 }
6442 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
6443 host_flag =
6444 AscReadLramByte(iop_base,
6445 ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
6446 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
6447 (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT));
6448 AscSetChipStatus(iop_base, CIW_INT_ACK);
6449 loop = 0;
6450 while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
6451 AscSetChipStatus(iop_base, CIW_INT_ACK);
6452 if (loop++ > 3) {
6453 break;
6454 }
6455 }
6456 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
51219358
MW		 6457}
6458
6459static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
6460{
afbb68c3 6461 const uchar *period_table;
51219358
MW		 6462 int max_index;
6463 int min_index;
6464 int i;
6465
6466 period_table = asc_dvc->sdtr_period_tbl;
6467 max_index = (int)asc_dvc->max_sdtr_index;
afbb68c3 6468 min_index = (int)asc_dvc->min_sdtr_index;
51219358
MW		 6469 if ((syn_time <= period_table[max_index])) {
6470 for (i = min_index; i < (max_index - 1); i++) {
6471 if (syn_time <= period_table[i]) {
6472 return (uchar)i;
6473 }
6474 }
6475 return (uchar)max_index;
6476 } else {
6477 return (uchar)(max_index + 1);
6478 }
6479}
6480
6481static uchar
6482AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset)
6483{
6484 EXT_MSG sdtr_buf;
6485 uchar sdtr_period_index;
6486 PortAddr iop_base;
6487
6488 iop_base = asc_dvc->iop_base;
6489 sdtr_buf.msg_type = EXTENDED_MESSAGE;
6490 sdtr_buf.msg_len = MS_SDTR_LEN;
6491 sdtr_buf.msg_req = EXTENDED_SDTR;
6492 sdtr_buf.xfer_period = sdtr_period;
6493 sdtr_offset &= ASC_SYN_MAX_OFFSET;
6494 sdtr_buf.req_ack_offset = sdtr_offset;
6495 sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
6496 if (sdtr_period_index <= asc_dvc->max_sdtr_index) {
6497 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6498 (uchar *)&sdtr_buf,
6499 sizeof(EXT_MSG) >> 1);
6500 return ((sdtr_period_index << 4) | sdtr_offset);
6501 } else {
6502 sdtr_buf.req_ack_offset = 0;
6503 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6504 (uchar *)&sdtr_buf,
6505 sizeof(EXT_MSG) >> 1);
6506 return 0;
6507 }
6508}
6509
6510static uchar
6511AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
6512{
6513 uchar byte;
6514 uchar sdtr_period_ix;
6515
6516 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
afbb68c3 6517 if (sdtr_period_ix > asc_dvc->max_sdtr_index)
51219358 6518 return 0xFF;
51219358
MW		 6519 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
6520 return byte;
6521}
6522
6523static int AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data)
6524{
6525 ASC_SCSI_BIT_ID_TYPE org_id;
6526 int i;
6527 int sta = TRUE;
6528
6529 AscSetBank(iop_base, 1);
6530 org_id = AscReadChipDvcID(iop_base);
6531 for (i = 0; i <= ASC_MAX_TID; i++) {
6532 if (org_id == (0x01 << i))
6533 break;
6534 }
6535 org_id = (ASC_SCSI_BIT_ID_TYPE) i;
6536 AscWriteChipDvcID(iop_base, id);
6537 if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
6538 AscSetBank(iop_base, 0);
6539 AscSetChipSyn(iop_base, sdtr_data);
6540 if (AscGetChipSyn(iop_base) != sdtr_data) {
6541 sta = FALSE;
6542 }
6543 } else {
6544 sta = FALSE;
6545 }
6546 AscSetBank(iop_base, 1);
6547 AscWriteChipDvcID(iop_base, org_id);
6548 AscSetBank(iop_base, 0);
6549 return (sta);
6550}
6551
6552static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no)
6553{
6554 AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
6555 AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
6556}
6557
6558static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
6559{
6560 EXT_MSG ext_msg;
6561 EXT_MSG out_msg;
6562 ushort halt_q_addr;
6563 int sdtr_accept;
6564 ushort int_halt_code;
6565 ASC_SCSI_BIT_ID_TYPE scsi_busy;
6566 ASC_SCSI_BIT_ID_TYPE target_id;
6567 PortAddr iop_base;
6568 uchar tag_code;
6569 uchar q_status;
6570 uchar halt_qp;
6571 uchar sdtr_data;
6572 uchar target_ix;
6573 uchar q_cntl, tid_no;
6574 uchar cur_dvc_qng;
6575 uchar asyn_sdtr;
6576 uchar scsi_status;
d2411495 6577 struct asc_board *boardp;
51219358
MW		 6578
6579 BUG_ON(!asc_dvc->drv_ptr);
6580 boardp = asc_dvc->drv_ptr;
6581
6582 iop_base = asc_dvc->iop_base;
6583 int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
6584
6585 halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
6586 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
6587 target_ix = AscReadLramByte(iop_base,
6588 (ushort)(halt_q_addr +
6589 (ushort)ASC_SCSIQ_B_TARGET_IX));
6590 q_cntl = AscReadLramByte(iop_base,
6591 (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL));
6592 tid_no = ASC_TIX_TO_TID(target_ix);
6593 target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no);
6594 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6595 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
6596 } else {
6597 asyn_sdtr = 0;
6598 }
6599 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
6600 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6601 AscSetChipSDTR(iop_base, 0, tid_no);
6602 boardp->sdtr_data[tid_no] = 0;
6603 }
6604 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6605 return (0);
6606 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
6607 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6608 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6609 boardp->sdtr_data[tid_no] = asyn_sdtr;
6610 }
6611 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6612 return (0);
6613 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
6614 AscMemWordCopyPtrFromLram(iop_base,
6615 ASCV_MSGIN_BEG,
6616 (uchar *)&ext_msg,
6617 sizeof(EXT_MSG) >> 1);
6618
6619 if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6620 ext_msg.msg_req == EXTENDED_SDTR &&
6621 ext_msg.msg_len == MS_SDTR_LEN) {
6622 sdtr_accept = TRUE;
6623 if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
6624
6625 sdtr_accept = FALSE;
6626 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
6627 }
6628 if ((ext_msg.xfer_period <
afbb68c3 6629 asc_dvc->sdtr_period_tbl[asc_dvc->min_sdtr_index])
51219358
MW		 6630 || (ext_msg.xfer_period >
6631 asc_dvc->sdtr_period_tbl[asc_dvc->
6632 max_sdtr_index])) {
6633 sdtr_accept = FALSE;
6634 ext_msg.xfer_period =
6635 asc_dvc->sdtr_period_tbl[asc_dvc->
afbb68c3 6636 min_sdtr_index];
51219358
MW		 6637 }
6638 if (sdtr_accept) {
6639 sdtr_data =
6640 AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
6641 ext_msg.req_ack_offset);
6642 if ((sdtr_data == 0xFF)) {
6643
6644 q_cntl |= QC_MSG_OUT;
6645 asc_dvc->init_sdtr &= ~target_id;
6646 asc_dvc->sdtr_done &= ~target_id;
6647 AscSetChipSDTR(iop_base, asyn_sdtr,
6648 tid_no);
6649 boardp->sdtr_data[tid_no] = asyn_sdtr;
6650 }
6651 }
6652 if (ext_msg.req_ack_offset == 0) {
6653
6654 q_cntl &= ~QC_MSG_OUT;
6655 asc_dvc->init_sdtr &= ~target_id;
6656 asc_dvc->sdtr_done &= ~target_id;
6657 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6658 } else {
6659 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
51219358
MW		 6660 q_cntl &= ~QC_MSG_OUT;
6661 asc_dvc->sdtr_done |= target_id;
6662 asc_dvc->init_sdtr |= target_id;
6663 asc_dvc->pci_fix_asyn_xfer &=
6664 ~target_id;
6665 sdtr_data =
6666 AscCalSDTRData(asc_dvc,
6667 ext_msg.xfer_period,
6668 ext_msg.
6669 req_ack_offset);
6670 AscSetChipSDTR(iop_base, sdtr_data,
6671 tid_no);
6672 boardp->sdtr_data[tid_no] = sdtr_data;
6673 } else {
51219358
MW		 6674 q_cntl |= QC_MSG_OUT;
6675 AscMsgOutSDTR(asc_dvc,
6676 ext_msg.xfer_period,
6677 ext_msg.req_ack_offset);
6678 asc_dvc->pci_fix_asyn_xfer &=
6679 ~target_id;
6680 sdtr_data =
6681 AscCalSDTRData(asc_dvc,
6682 ext_msg.xfer_period,
6683 ext_msg.
6684 req_ack_offset);
6685 AscSetChipSDTR(iop_base, sdtr_data,
6686 tid_no);
6687 boardp->sdtr_data[tid_no] = sdtr_data;
6688 asc_dvc->sdtr_done |= target_id;
6689 asc_dvc->init_sdtr |= target_id;
6690 }
6691 }
6692
6693 AscWriteLramByte(iop_base,
6694 (ushort)(halt_q_addr +
6695 (ushort)ASC_SCSIQ_B_CNTL),
6696 q_cntl);
6697 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6698 return (0);
6699 } else if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6700 ext_msg.msg_req == EXTENDED_WDTR &&
6701 ext_msg.msg_len == MS_WDTR_LEN) {
6702
6703 ext_msg.wdtr_width = 0;
6704 AscMemWordCopyPtrToLram(iop_base,
6705 ASCV_MSGOUT_BEG,
6706 (uchar *)&ext_msg,
6707 sizeof(EXT_MSG) >> 1);
6708 q_cntl |= QC_MSG_OUT;
6709 AscWriteLramByte(iop_base,
6710 (ushort)(halt_q_addr +
6711 (ushort)ASC_SCSIQ_B_CNTL),
6712 q_cntl);
6713 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6714 return (0);
6715 } else {
6716
6717 ext_msg.msg_type = MESSAGE_REJECT;
6718 AscMemWordCopyPtrToLram(iop_base,
6719 ASCV_MSGOUT_BEG,
6720 (uchar *)&ext_msg,
6721 sizeof(EXT_MSG) >> 1);
6722 q_cntl |= QC_MSG_OUT;
6723 AscWriteLramByte(iop_base,
6724 (ushort)(halt_q_addr +
6725 (ushort)ASC_SCSIQ_B_CNTL),
6726 q_cntl);
6727 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6728 return (0);
6729 }
6730 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
6731
6732 q_cntl |= QC_REQ_SENSE;
6733
6734 if ((asc_dvc->init_sdtr & target_id) != 0) {
6735
6736 asc_dvc->sdtr_done &= ~target_id;
6737
6738 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
6739 q_cntl |= QC_MSG_OUT;
6740 AscMsgOutSDTR(asc_dvc,
6741 asc_dvc->
6742 sdtr_period_tbl[(sdtr_data >> 4) &
6743 (uchar)(asc_dvc->
6744 max_sdtr_index -
6745 1)],
6746 (uchar)(sdtr_data & (uchar)
6747 ASC_SYN_MAX_OFFSET));
6748 }
6749
6750 AscWriteLramByte(iop_base,
6751 (ushort)(halt_q_addr +
6752 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6753
6754 tag_code = AscReadLramByte(iop_base,
6755 (ushort)(halt_q_addr + (ushort)
6756 ASC_SCSIQ_B_TAG_CODE));
6757 tag_code &= 0xDC;
6758 if ((asc_dvc->pci_fix_asyn_xfer & target_id)
6759 && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
6760 ) {
6761
6762 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
6763 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
6764
6765 }
6766 AscWriteLramByte(iop_base,
6767 (ushort)(halt_q_addr +
6768 (ushort)ASC_SCSIQ_B_TAG_CODE),
6769 tag_code);
6770
6771 q_status = AscReadLramByte(iop_base,
6772 (ushort)(halt_q_addr + (ushort)
6773 ASC_SCSIQ_B_STATUS));
6774 q_status |= (QS_READY | QS_BUSY);
6775 AscWriteLramByte(iop_base,
6776 (ushort)(halt_q_addr +
6777 (ushort)ASC_SCSIQ_B_STATUS),
6778 q_status);
6779
6780 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B);
6781 scsi_busy &= ~target_id;
6782 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6783
6784 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6785 return (0);
6786 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
6787
6788 AscMemWordCopyPtrFromLram(iop_base,
6789 ASCV_MSGOUT_BEG,
6790 (uchar *)&out_msg,
6791 sizeof(EXT_MSG) >> 1);
6792
6793 if ((out_msg.msg_type == EXTENDED_MESSAGE) &&
6794 (out_msg.msg_len == MS_SDTR_LEN) &&
6795 (out_msg.msg_req == EXTENDED_SDTR)) {
6796
6797 asc_dvc->init_sdtr &= ~target_id;
6798 asc_dvc->sdtr_done &= ~target_id;
6799 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6800 boardp->sdtr_data[tid_no] = asyn_sdtr;
6801 }
6802 q_cntl &= ~QC_MSG_OUT;
6803 AscWriteLramByte(iop_base,
6804 (ushort)(halt_q_addr +
6805 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6806 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6807 return (0);
6808 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
6809
6810 scsi_status = AscReadLramByte(iop_base,
6811 (ushort)((ushort)halt_q_addr +
6812 (ushort)
6813 ASC_SCSIQ_SCSI_STATUS));
6814 cur_dvc_qng =
6815 AscReadLramByte(iop_base,
6816 (ushort)((ushort)ASC_QADR_BEG +
6817 (ushort)target_ix));
6818 if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
6819
6820 scsi_busy = AscReadLramByte(iop_base,
6821 (ushort)ASCV_SCSIBUSY_B);
6822 scsi_busy |= target_id;
6823 AscWriteLramByte(iop_base,
6824 (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6825 asc_dvc->queue_full_or_busy |= target_id;
6826
6827 if (scsi_status == SAM_STAT_TASK_SET_FULL) {
6828 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
6829 cur_dvc_qng -= 1;
6830 asc_dvc->max_dvc_qng[tid_no] =
6831 cur_dvc_qng;
6832
6833 AscWriteLramByte(iop_base,
6834 (ushort)((ushort)
6835 ASCV_MAX_DVC_QNG_BEG
6836 + (ushort)
6837 tid_no),
6838 cur_dvc_qng);
6839
6840 /*
6841 * Set the device queue depth to the
6842 * number of active requests when the
6843 * QUEUE FULL condition was encountered.
6844 */
6845 boardp->queue_full |= target_id;
6846 boardp->queue_full_cnt[tid_no] =
6847 cur_dvc_qng;
6848 }
6849 }
6850 }
6851 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6852 return (0);
6853 }
6854#if CC_VERY_LONG_SG_LIST
6855 else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC) {
6856 uchar q_no;
6857 ushort q_addr;
6858 uchar sg_wk_q_no;
6859 uchar first_sg_wk_q_no;
6860 ASC_SCSI_Q *scsiq; /* Ptr to driver request. */
6861 ASC_SG_HEAD *sg_head; /* Ptr to driver SG request. */
6862 ASC_SG_LIST_Q scsi_sg_q; /* Structure written to queue. */
6863 ushort sg_list_dwords;
6864 ushort sg_entry_cnt;
6865 uchar next_qp;
6866 int i;
6867
6868 q_no = AscReadLramByte(iop_base, (ushort)ASCV_REQ_SG_LIST_QP);
6869 if (q_no == ASC_QLINK_END)
6870 return 0;
6871
6872 q_addr = ASC_QNO_TO_QADDR(q_no);
6873
6874 /*
6875 * Convert the request's SRB pointer to a host ASC_SCSI_REQ
6876 * structure pointer using a macro provided by the driver.
6877 * The ASC_SCSI_REQ pointer provides a pointer to the
6878 * host ASC_SG_HEAD structure.
6879 */
6880 /* Read request's SRB pointer. */
6881 scsiq = (ASC_SCSI_Q *)
6882 ASC_SRB2SCSIQ(ASC_U32_TO_VADDR(AscReadLramDWord(iop_base,
6883 (ushort)
6884 (q_addr +
6885 ASC_SCSIQ_D_SRBPTR))));
6886
6887 /*
6888 * Get request's first and working SG queue.
6889 */
6890 sg_wk_q_no = AscReadLramByte(iop_base,
6891 (ushort)(q_addr +
6892 ASC_SCSIQ_B_SG_WK_QP));
6893
6894 first_sg_wk_q_no = AscReadLramByte(iop_base,
6895 (ushort)(q_addr +
6896 ASC_SCSIQ_B_FIRST_SG_WK_QP));
6897
6898 /*
6899 * Reset request's working SG queue back to the
6900 * first SG queue.
6901 */
6902 AscWriteLramByte(iop_base,
6903 (ushort)(q_addr +
6904 (ushort)ASC_SCSIQ_B_SG_WK_QP),
6905 first_sg_wk_q_no);
6906
6907 sg_head = scsiq->sg_head;
6908
6909 /*
6910 * Set sg_entry_cnt to the number of SG elements
6911 * that will be completed on this interrupt.
6912 *
6913 * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
6914 * SG elements. The data_cnt and data_addr fields which
6915 * add 1 to the SG element capacity are not used when
6916 * restarting SG handling after a halt.
6917 */
6918 if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1)) {
6919 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
6920
6921 /*
6922 * Keep track of remaining number of SG elements that
6923 * will need to be handled on the next interrupt.
6924 */
6925 scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1);
6926 } else {
6927 sg_entry_cnt = scsiq->remain_sg_entry_cnt;
6928 scsiq->remain_sg_entry_cnt = 0;
6929 }
6930
6931 /*
6932 * Copy SG elements into the list of allocated SG queues.
6933 *
6934 * Last index completed is saved in scsiq->next_sg_index.
6935 */
6936 next_qp = first_sg_wk_q_no;
6937 q_addr = ASC_QNO_TO_QADDR(next_qp);
6938 scsi_sg_q.sg_head_qp = q_no;
6939 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
6940 for (i = 0; i < sg_head->queue_cnt; i++) {
6941 scsi_sg_q.seq_no = i + 1;
6942 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
6943 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
6944 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
6945 /*
6946 * After very first SG queue RISC FW uses next
6947 * SG queue first element then checks sg_list_cnt
6948 * against zero and then decrements, so set
6949 * sg_list_cnt 1 less than number of SG elements
6950 * in each SG queue.
6951 */
6952 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
6953 scsi_sg_q.sg_cur_list_cnt =
6954 ASC_SG_LIST_PER_Q - 1;
6955 } else {
6956 /*
6957 * This is the last SG queue in the list of
6958 * allocated SG queues. If there are more
6959 * SG elements than will fit in the allocated
6960 * queues, then set the QCSG_SG_XFER_MORE flag.
6961 */
6962 if (scsiq->remain_sg_entry_cnt != 0) {
6963 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
6964 } else {
6965 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
6966 }
6967 /* equals sg_entry_cnt * 2 */
6968 sg_list_dwords = sg_entry_cnt << 1;
6969 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
6970 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
6971 sg_entry_cnt = 0;
6972 }
6973
6974 scsi_sg_q.q_no = next_qp;
6975 AscMemWordCopyPtrToLram(iop_base,
6976 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
6977 (uchar *)&scsi_sg_q,
6978 sizeof(ASC_SG_LIST_Q) >> 1);
6979
6980 AscMemDWordCopyPtrToLram(iop_base,
6981 q_addr + ASC_SGQ_LIST_BEG,
6982 (uchar *)&sg_head->
6983 sg_list[scsiq->next_sg_index],
6984 sg_list_dwords);
6985
6986 scsiq->next_sg_index += ASC_SG_LIST_PER_Q;
6987
6988 /*
6989 * If the just completed SG queue contained the
6990 * last SG element, then no more SG queues need
6991 * to be written.
6992 */
6993 if (scsi_sg_q.cntl & QCSG_SG_XFER_END) {
6994 break;
6995 }
6996
6997 next_qp = AscReadLramByte(iop_base,
6998 (ushort)(q_addr +
6999 ASC_SCSIQ_B_FWD));
7000 q_addr = ASC_QNO_TO_QADDR(next_qp);
7001 }
7002
7003 /*
7004 * Clear the halt condition so the RISC will be restarted
7005 * after the return.
7006 */
7007 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
7008 return (0);
7009 }
7010#endif /* CC_VERY_LONG_SG_LIST */
7011 return (0);
7012}
1da177e4 7013
1da177e4 7014/*
51219358
MW		 7015 * void
7016 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
1da177e4 7017 *
51219358
MW		 7018 * Calling/Exit State:
7019 * none
1da177e4 7020 *
51219358
MW		 7021 * Description:
7022 * Input an ASC_QDONE_INFO structure from the chip
1da177e4 7023 */
51219358
MW		 7024static void
7025DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
7026{
7027 int i;
7028 ushort word;
7029
7030 AscSetChipLramAddr(iop_base, s_addr);
7031 for (i = 0; i < 2 * words; i += 2) {
7032 if (i == 10) {
7033 continue;
7034 }
7035 word = inpw(iop_base + IOP_RAM_DATA);
7036 inbuf[i] = word & 0xff;
7037 inbuf[i + 1] = (word >> 8) & 0xff;
7038 }
7039 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
7040}
7041
7042static uchar
7043_AscCopyLramScsiDoneQ(PortAddr iop_base,
7044 ushort q_addr,
7045 ASC_QDONE_INFO *scsiq, ASC_DCNT max_dma_count)
7046{
7047 ushort _val;
7048 uchar sg_queue_cnt;
7049
7050 DvcGetQinfo(iop_base,
7051 q_addr + ASC_SCSIQ_DONE_INFO_BEG,
7052 (uchar *)scsiq,
7053 (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2);
7054
7055 _val = AscReadLramWord(iop_base,
7056 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS));
7057 scsiq->q_status = (uchar)_val;
7058 scsiq->q_no = (uchar)(_val >> 8);
7059 _val = AscReadLramWord(iop_base,
7060 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL));
7061 scsiq->cntl = (uchar)_val;
7062 sg_queue_cnt = (uchar)(_val >> 8);
7063 _val = AscReadLramWord(iop_base,
7064 (ushort)(q_addr +
7065 (ushort)ASC_SCSIQ_B_SENSE_LEN));
7066 scsiq->sense_len = (uchar)_val;
7067 scsiq->extra_bytes = (uchar)(_val >> 8);
7068
7069 /*
7070 * Read high word of remain bytes from alternate location.
7071 */
7072 scsiq->remain_bytes = (((ADV_DCNT)AscReadLramWord(iop_base,
7073 (ushort)(q_addr +
7074 (ushort)
7075 ASC_SCSIQ_W_ALT_DC1)))
7076 << 16);
7077 /*
7078 * Read low word of remain bytes from original location.
7079 */
7080 scsiq->remain_bytes += AscReadLramWord(iop_base,
7081 (ushort)(q_addr + (ushort)
7082 ASC_SCSIQ_DW_REMAIN_XFER_CNT));
7083
7084 scsiq->remain_bytes &= max_dma_count;
7085 return sg_queue_cnt;
7086}
7087
7088/*
7089 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
7090 *
7091 * Interrupt callback function for the Narrow SCSI Asc Library.
7092 */
7093static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
7094{
d2411495 7095 struct asc_board *boardp;
51219358
MW		 7096 struct scsi_cmnd *scp;
7097 struct Scsi_Host *shost;
7098
b352f923 7099 ASC_DBG(1, "asc_dvc_varp 0x%p, qdonep 0x%p\n", asc_dvc_varp, qdonep);
51219358
MW		 7100 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
7101
b249c7fd
MW		 7102 scp = advansys_srb_to_ptr(asc_dvc_varp, qdonep->d2.srb_ptr);
7103 if (!scp)
51219358 7104 return;
b249c7fd 7105
51219358
MW		 7106 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
7107
7108 shost = scp->device->host;
7109 ASC_STATS(shost, callback);
b352f923 7110 ASC_DBG(1, "shost 0x%p\n", shost);
51219358 7111
d2411495 7112 boardp = shost_priv(shost);
51219358
MW		 7113 BUG_ON(asc_dvc_varp != &boardp->dvc_var.asc_dvc_var);
7114
b249c7fd 7115 dma_unmap_single(boardp->dev, scp->SCp.dma_handle,
b80ca4f7 7116 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
51219358
MW		 7117 /*
7118 * 'qdonep' contains the command's ending status.
7119 */
7120 switch (qdonep->d3.done_stat) {
7121 case QD_NO_ERROR:
b352f923 7122 ASC_DBG(2, "QD_NO_ERROR\n");
51219358
MW		 7123 scp->result = 0;
7124
7125 /*
7126 * Check for an underrun condition.
7127 *
7128 * If there was no error and an underrun condition, then
7129 * return the number of underrun bytes.
7130 */
52c334e9
MW		 7131 if (scsi_bufflen(scp) != 0 && qdonep->remain_bytes != 0 &&
7132 qdonep->remain_bytes <= scsi_bufflen(scp)) {
b352f923 7133 ASC_DBG(1, "underrun condition %u bytes\n",
51219358 7134 (unsigned)qdonep->remain_bytes);
52c334e9 7135 scsi_set_resid(scp, qdonep->remain_bytes);
51219358
MW		 7136 }
7137 break;
7138
7139 case QD_WITH_ERROR:
b352f923 7140 ASC_DBG(2, "QD_WITH_ERROR\n");
51219358
MW		 7141 switch (qdonep->d3.host_stat) {
7142 case QHSTA_NO_ERROR:
7143 if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
b352f923 7144 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
51219358 7145 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
b80ca4f7 7146 SCSI_SENSE_BUFFERSIZE);
51219358
MW		 7147 /*
7148 * Note: The 'status_byte()' macro used by
7149 * target drivers defined in scsi.h shifts the
7150 * status byte returned by host drivers right
7151 * by 1 bit. This is why target drivers also
7152 * use right shifted status byte definitions.
7153 * For instance target drivers use
7154 * CHECK_CONDITION, defined to 0x1, instead of
7155 * the SCSI defined check condition value of
7156 * 0x2. Host drivers are supposed to return
7157 * the status byte as it is defined by SCSI.
7158 */
7159 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
7160 STATUS_BYTE(qdonep->d3.scsi_stat);
7161 } else {
7162 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
7163 }
7164 break;
7165
7166 default:
7167 /* QHSTA error occurred */
b352f923 7168 ASC_DBG(1, "host_stat 0x%x\n", qdonep->d3.host_stat);
51219358
MW		 7169 scp->result = HOST_BYTE(DID_BAD_TARGET);
7170 break;
7171 }
7172 break;
7173
7174 case QD_ABORTED_BY_HOST:
b352f923 7175 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
51219358
MW		 7176 scp->result =
7177 HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.
7178 scsi_msg) |
7179 STATUS_BYTE(qdonep->d3.scsi_stat);
7180 break;
7181
7182 default:
b352f923 7183 ASC_DBG(1, "done_stat 0x%x\n", qdonep->d3.done_stat);
51219358
MW		 7184 scp->result =
7185 HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.
7186 scsi_msg) |
7187 STATUS_BYTE(qdonep->d3.scsi_stat);
7188 break;
7189 }
7190
7191 /*
7192 * If the 'init_tidmask' bit isn't already set for the target and the
7193 * current request finished normally, then set the bit for the target
7194 * to indicate that a device is present.
7195 */
7196 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
7197 qdonep->d3.done_stat == QD_NO_ERROR &&
7198 qdonep->d3.host_stat == QHSTA_NO_ERROR) {
7199 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
7200 }
1da177e4 7201
51219358 7202 asc_scsi_done(scp);
51219358
MW		 7203}
7204
7205static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
7206{
7207 uchar next_qp;
7208 uchar n_q_used;
7209 uchar sg_list_qp;
7210 uchar sg_queue_cnt;
7211 uchar q_cnt;
7212 uchar done_q_tail;
7213 uchar tid_no;
7214 ASC_SCSI_BIT_ID_TYPE scsi_busy;
7215 ASC_SCSI_BIT_ID_TYPE target_id;
7216 PortAddr iop_base;
7217 ushort q_addr;
7218 ushort sg_q_addr;
7219 uchar cur_target_qng;
7220 ASC_QDONE_INFO scsiq_buf;
7221 ASC_QDONE_INFO *scsiq;
7222 int false_overrun;
7223
7224 iop_base = asc_dvc->iop_base;
7225 n_q_used = 1;
7226 scsiq = (ASC_QDONE_INFO *)&scsiq_buf;
7227 done_q_tail = (uchar)AscGetVarDoneQTail(iop_base);
7228 q_addr = ASC_QNO_TO_QADDR(done_q_tail);
7229 next_qp = AscReadLramByte(iop_base,
7230 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD));
7231 if (next_qp != ASC_QLINK_END) {
7232 AscPutVarDoneQTail(iop_base, next_qp);
7233 q_addr = ASC_QNO_TO_QADDR(next_qp);
7234 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
7235 asc_dvc->max_dma_count);
7236 AscWriteLramByte(iop_base,
7237 (ushort)(q_addr +
7238 (ushort)ASC_SCSIQ_B_STATUS),
7239 (uchar)(scsiq->
7240 q_status & (uchar)~(QS_READY |
7241 QS_ABORTED)));
7242 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
7243 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
7244 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
7245 sg_q_addr = q_addr;
7246 sg_list_qp = next_qp;
7247 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
7248 sg_list_qp = AscReadLramByte(iop_base,
7249 (ushort)(sg_q_addr
7250 + (ushort)
7251 ASC_SCSIQ_B_FWD));
7252 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
7253 if (sg_list_qp == ASC_QLINK_END) {
7254 AscSetLibErrorCode(asc_dvc,
7255 ASCQ_ERR_SG_Q_LINKS);
7256 scsiq->d3.done_stat = QD_WITH_ERROR;
7257 scsiq->d3.host_stat =
7258 QHSTA_D_QDONE_SG_LIST_CORRUPTED;
7259 goto FATAL_ERR_QDONE;
7260 }
7261 AscWriteLramByte(iop_base,
7262 (ushort)(sg_q_addr + (ushort)
7263 ASC_SCSIQ_B_STATUS),
7264 QS_FREE);
7265 }
7266 n_q_used = sg_queue_cnt + 1;
7267 AscPutVarDoneQTail(iop_base, sg_list_qp);
7268 }
7269 if (asc_dvc->queue_full_or_busy & target_id) {
7270 cur_target_qng = AscReadLramByte(iop_base,
7271 (ushort)((ushort)
7272 ASC_QADR_BEG
7273 + (ushort)
7274 scsiq->d2.
7275 target_ix));
7276 if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
7277 scsi_busy = AscReadLramByte(iop_base, (ushort)
7278 ASCV_SCSIBUSY_B);
7279 scsi_busy &= ~target_id;
7280 AscWriteLramByte(iop_base,
7281 (ushort)ASCV_SCSIBUSY_B,
7282 scsi_busy);
7283 asc_dvc->queue_full_or_busy &= ~target_id;
7284 }
7285 }
7286 if (asc_dvc->cur_total_qng >= n_q_used) {
7287 asc_dvc->cur_total_qng -= n_q_used;
7288 if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
7289 asc_dvc->cur_dvc_qng[tid_no]--;
7290 }
7291 } else {
7292 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
7293 scsiq->d3.done_stat = QD_WITH_ERROR;
7294 goto FATAL_ERR_QDONE;
7295 }
7296 if ((scsiq->d2.srb_ptr == 0UL) ||
7297 ((scsiq->q_status & QS_ABORTED) != 0)) {
7298 return (0x11);
7299 } else if (scsiq->q_status == QS_DONE) {
7300 false_overrun = FALSE;
7301 if (scsiq->extra_bytes != 0) {
7302 scsiq->remain_bytes +=
7303 (ADV_DCNT)scsiq->extra_bytes;
7304 }
7305 if (scsiq->d3.done_stat == QD_WITH_ERROR) {
7306 if (scsiq->d3.host_stat ==
7307 QHSTA_M_DATA_OVER_RUN) {
7308 if ((scsiq->
7309 cntl & (QC_DATA_IN | QC_DATA_OUT))
7310 == 0) {
7311 scsiq->d3.done_stat =
7312 QD_NO_ERROR;
7313 scsiq->d3.host_stat =
7314 QHSTA_NO_ERROR;
7315 } else if (false_overrun) {
7316 scsiq->d3.done_stat =
7317 QD_NO_ERROR;
7318 scsiq->d3.host_stat =
7319 QHSTA_NO_ERROR;
7320 }
7321 } else if (scsiq->d3.host_stat ==
7322 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
7323 AscStopChip(iop_base);
7324 AscSetChipControl(iop_base,
7325 (uchar)(CC_SCSI_RESET
7326 | CC_HALT));
7327 udelay(60);
7328 AscSetChipControl(iop_base, CC_HALT);
7329 AscSetChipStatus(iop_base,
7330 CIW_CLR_SCSI_RESET_INT);
7331 AscSetChipStatus(iop_base, 0);
7332 AscSetChipControl(iop_base, 0);
7333 }
7334 }
7335 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7336 asc_isr_callback(asc_dvc, scsiq);
7337 } else {
7338 if ((AscReadLramByte(iop_base,
7339 (ushort)(q_addr + (ushort)
7340 ASC_SCSIQ_CDB_BEG))
7341 == START_STOP)) {
7342 asc_dvc->unit_not_ready &= ~target_id;
7343 if (scsiq->d3.done_stat != QD_NO_ERROR) {
7344 asc_dvc->start_motor &=
7345 ~target_id;
7346 }
7347 }
7348 }
7349 return (1);
7350 } else {
7351 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
7352 FATAL_ERR_QDONE:
7353 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7354 asc_isr_callback(asc_dvc, scsiq);
7355 }
7356 return (0x80);
7357 }
7358 }
7359 return (0);
7360}
1da177e4 7361
51219358
MW		 7362static int AscISR(ASC_DVC_VAR *asc_dvc)
7363{
7364 ASC_CS_TYPE chipstat;
7365 PortAddr iop_base;
7366 ushort saved_ram_addr;
7367 uchar ctrl_reg;
7368 uchar saved_ctrl_reg;
7369 int int_pending;
7370 int status;
7371 uchar host_flag;
1da177e4 7372
51219358
MW		 7373 iop_base = asc_dvc->iop_base;
7374 int_pending = FALSE;
1da177e4 7375
51219358
MW		 7376 if (AscIsIntPending(iop_base) == 0)
7377 return int_pending;
7378
7379 if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) {
7380 return ERR;
7381 }
7382 if (asc_dvc->in_critical_cnt != 0) {
7383 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
7384 return ERR;
7385 }
7386 if (asc_dvc->is_in_int) {
7387 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
7388 return ERR;
7389 }
7390 asc_dvc->is_in_int = TRUE;
7391 ctrl_reg = AscGetChipControl(iop_base);
7392 saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
7393 CC_SINGLE_STEP | CC_DIAG | CC_TEST));
7394 chipstat = AscGetChipStatus(iop_base);
7395 if (chipstat & CSW_SCSI_RESET_LATCH) {
7396 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
7397 int i = 10;
7398 int_pending = TRUE;
7399 asc_dvc->sdtr_done = 0;
7400 saved_ctrl_reg &= (uchar)(~CC_HALT);
7401 while ((AscGetChipStatus(iop_base) &
7402 CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) {
7403 mdelay(100);
7404 }
7405 AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
7406 AscSetChipControl(iop_base, CC_HALT);
7407 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
7408 AscSetChipStatus(iop_base, 0);
7409 chipstat = AscGetChipStatus(iop_base);
7410 }
7411 }
7412 saved_ram_addr = AscGetChipLramAddr(iop_base);
7413 host_flag = AscReadLramByte(iop_base,
7414 ASCV_HOST_FLAG_B) &
7415 (uchar)(~ASC_HOST_FLAG_IN_ISR);
7416 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
7417 (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR));
7418 if ((chipstat & CSW_INT_PENDING) || (int_pending)) {
7419 AscAckInterrupt(iop_base);
7420 int_pending = TRUE;
7421 if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {
7422 if (AscIsrChipHalted(asc_dvc) == ERR) {
7423 goto ISR_REPORT_QDONE_FATAL_ERROR;
7424 } else {
7425 saved_ctrl_reg &= (uchar)(~CC_HALT);
7426 }
7427 } else {
7428 ISR_REPORT_QDONE_FATAL_ERROR:
7429 if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
7430 while (((status =
7431 AscIsrQDone(asc_dvc)) & 0x01) != 0) {
7432 }
7433 } else {
7434 do {
7435 if ((status =
7436 AscIsrQDone(asc_dvc)) == 1) {
7437 break;
7438 }
7439 } while (status == 0x11);
7440 }
7441 if ((status & 0x80) != 0)
7442 int_pending = ERR;
7443 }
7444 }
7445 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
7446 AscSetChipLramAddr(iop_base, saved_ram_addr);
7447 AscSetChipControl(iop_base, saved_ctrl_reg);
7448 asc_dvc->is_in_int = FALSE;
7449 return int_pending;
7450}
1da177e4
LT		 7451
7452/*
51219358 7453 * advansys_reset()
1da177e4 7454 *
eac0b0c7 7455 * Reset the host associated with the command 'scp'.
1da177e4 7456 *
51219358
MW		 7457 * This function runs its own thread. Interrupts must be blocked but
7458 * sleeping is allowed and no locking other than for host structures is
7459 * required. Returns SUCCESS or FAILED.
1da177e4 7460 */
51219358 7461static int advansys_reset(struct scsi_cmnd *scp)
1da177e4 7462{
52fa0777 7463 struct Scsi_Host *shost = scp->device->host;
d2411495 7464 struct asc_board *boardp = shost_priv(shost);
52fa0777 7465 unsigned long flags;
27c868c2 7466 int status;
51219358 7467 int ret = SUCCESS;
27c868c2 7468
b352f923 7469 ASC_DBG(1, "0x%p\n", scp);
27c868c2 7470
52fa0777 7471 ASC_STATS(shost, reset);
27c868c2 7472
eac0b0c7 7473 scmd_printk(KERN_INFO, scp, "SCSI host reset started...\n");
51219358
MW		 7474
7475 if (ASC_NARROW_BOARD(boardp)) {
52fa0777 7476 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
1da177e4 7477
52fa0777 7478 /* Reset the chip and SCSI bus. */
b352f923 7479 ASC_DBG(1, "before AscInitAsc1000Driver()\n");
52fa0777 7480 status = AscInitAsc1000Driver(asc_dvc);
27c868c2 7481
6070d81e 7482 /* Refer to ASC_IERR_* definitions for meaning of 'err_code'. */
9a908c1a 7483 if (asc_dvc->err_code || !asc_dvc->overrun_dma) {
eac0b0c7 7484 scmd_printk(KERN_INFO, scp, "SCSI host reset error: "
9a908c1a
HRK		 7485 "0x%x, status: 0x%x\n", asc_dvc->err_code,
7486 status);
51219358
MW		 7487 ret = FAILED;
7488 } else if (status) {
eac0b0c7 7489 scmd_printk(KERN_INFO, scp, "SCSI host reset warning: "
52fa0777 7490 "0x%x\n", status);
27c868c2 7491 } else {
eac0b0c7 7492 scmd_printk(KERN_INFO, scp, "SCSI host reset "
52fa0777 7493 "successful\n");
27c868c2 7494 }
a9f4a59a 7495
b352f923 7496 ASC_DBG(1, "after AscInitAsc1000Driver()\n");
a9f4a59a 7497 } else {
a9f4a59a 7498 /*
51219358
MW		 7499 * If the suggest reset bus flags are set, then reset the bus.
7500 * Otherwise only reset the device.
a9f4a59a 7501 */
52fa0777 7502 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
a9f4a59a
MW		 7503
7504 /*
eac0b0c7 7505 * Reset the chip and SCSI bus.
a9f4a59a 7506 */
b352f923 7507 ASC_DBG(1, "before AdvResetChipAndSB()\n");
52fa0777 7508 switch (AdvResetChipAndSB(adv_dvc)) {
51219358 7509 case ASC_TRUE:
eac0b0c7 7510 scmd_printk(KERN_INFO, scp, "SCSI host reset "
52fa0777 7511 "successful\n");
51219358
MW		 7512 break;
7513 case ASC_FALSE:
7514 default:
eac0b0c7 7515 scmd_printk(KERN_INFO, scp, "SCSI host reset error\n");
51219358
MW		 7516 ret = FAILED;
7517 break;
b9d96614 7518 }
f092d229 7519 spin_lock_irqsave(shost->host_lock, flags);
52fa0777 7520 AdvISR(adv_dvc);
eac0b0c7 7521 spin_unlock_irqrestore(shost->host_lock, flags);
b9d96614
MW		 7522 }
7523
b352f923 7524 ASC_DBG(1, "ret %d\n", ret);
b9d96614 7525
51219358 7526 return ret;
b9d96614
MW		 7527}
7528
1da177e4 7529/*
51219358 7530 * advansys_biosparam()
1da177e4 7531 *
51219358
MW		 7532 * Translate disk drive geometry if the "BIOS greater than 1 GB"
7533 * support is enabled for a drive.
1da177e4 7534 *
51219358
MW		 7535 * ip (information pointer) is an int array with the following definition:
7536 * ip[0]: heads
7537 * ip[1]: sectors
7538 * ip[2]: cylinders
1da177e4 7539 */
51219358
MW		 7540static int
7541advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
7542 sector_t capacity, int ip[])
1da177e4 7543{
d2411495 7544 struct asc_board *boardp = shost_priv(sdev->host);
1da177e4 7545
b352f923 7546 ASC_DBG(1, "begin\n");
51219358 7547 ASC_STATS(sdev->host, biosparam);
51219358
MW		 7548 if (ASC_NARROW_BOARD(boardp)) {
7549 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
7550 ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
7551 ip[0] = 255;
7552 ip[1] = 63;
7553 } else {
7554 ip[0] = 64;
7555 ip[1] = 32;
7556 }
7557 } else {
7558 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
7559 BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
7560 ip[0] = 255;
7561 ip[1] = 63;
7562 } else {
7563 ip[0] = 64;
7564 ip[1] = 32;
7565 }
27c868c2 7566 }
51219358 7567 ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
b352f923 7568 ASC_DBG(1, "end\n");
51219358
MW		 7569 return 0;
7570}
1da177e4 7571
51219358
MW		 7572/*
7573 * First-level interrupt handler.
7574 *
7575 * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host.
7576 */
7577static irqreturn_t advansys_interrupt(int irq, void *dev_id)
7578{
51219358 7579 struct Scsi_Host *shost = dev_id;
d2411495 7580 struct asc_board *boardp = shost_priv(shost);
51219358 7581 irqreturn_t result = IRQ_NONE;
27c868c2 7582
b352f923 7583 ASC_DBG(2, "boardp 0x%p\n", boardp);
f092d229 7584 spin_lock(shost->host_lock);
51219358
MW		 7585 if (ASC_NARROW_BOARD(boardp)) {
7586 if (AscIsIntPending(shost->io_port)) {
7587 result = IRQ_HANDLED;
7588 ASC_STATS(shost, interrupt);
b352f923 7589 ASC_DBG(1, "before AscISR()\n");
51219358
MW		 7590 AscISR(&boardp->dvc_var.asc_dvc_var);
7591 }
7592 } else {
b352f923 7593 ASC_DBG(1, "before AdvISR()\n");
51219358
MW		 7594 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
7595 result = IRQ_HANDLED;
7596 ASC_STATS(shost, interrupt);
7597 }
27c868c2 7598 }
f092d229 7599 spin_unlock(shost->host_lock);
1da177e4 7600
b352f923 7601 ASC_DBG(1, "end\n");
51219358
MW		 7602 return result;
7603}
27c868c2 7604
51219358
MW		 7605static int AscHostReqRiscHalt(PortAddr iop_base)
7606{
7607 int count = 0;
7608 int sta = 0;
7609 uchar saved_stop_code;
7610
7611 if (AscIsChipHalted(iop_base))
7612 return (1);
7613 saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
7614 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
7615 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP);
7616 do {
7617 if (AscIsChipHalted(iop_base)) {
7618 sta = 1;
7619 break;
27c868c2 7620 }
51219358
MW		 7621 mdelay(100);
7622 } while (count++ < 20);
7623 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
7624 return (sta);
7625}
1da177e4 7626
51219358
MW		 7627static int
7628AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data)
7629{
7630 int sta = FALSE;
1da177e4 7631
51219358
MW		 7632 if (AscHostReqRiscHalt(iop_base)) {
7633 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
7634 AscStartChip(iop_base);
27c868c2 7635 }
51219358
MW		 7636 return sta;
7637}
1da177e4 7638
51219358
MW		 7639static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev)
7640{
7641 char type = sdev->type;
7642 ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id;
27c868c2 7643
51219358
MW		 7644 if (!(asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN))
7645 return;
7646 if (asc_dvc->init_sdtr & tid_bits)
7647 return;
27c868c2 7648
51219358
MW		 7649 if ((type == TYPE_ROM) && (strncmp(sdev->vendor, "HP ", 3) == 0))
7650 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
27c868c2 7651
51219358
MW		 7652 asc_dvc->pci_fix_asyn_xfer |= tid_bits;
7653 if ((type == TYPE_PROCESSOR) || (type == TYPE_SCANNER) ||
7654 (type == TYPE_ROM) || (type == TYPE_TAPE))
7655 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
7656
7657 if (asc_dvc->pci_fix_asyn_xfer & tid_bits)
7658 AscSetRunChipSynRegAtID(asc_dvc->iop_base, sdev->id,
7659 ASYN_SDTR_DATA_FIX_PCI_REV_AB);
7660}
1da177e4 7661
51219358
MW		 7662static void
7663advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc)
7664{
7665 ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id;
7666 ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng;
27c868c2 7667
51219358
MW		 7668 if (sdev->lun == 0) {
7669 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr;
7670 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) {
7671 asc_dvc->init_sdtr |= tid_bit;
7672 } else {
7673 asc_dvc->init_sdtr &= ~tid_bit;
7674 }
7675
7676 if (orig_init_sdtr != asc_dvc->init_sdtr)
7677 AscAsyncFix(asc_dvc, sdev);
27c868c2 7678 }
1da177e4 7679
51219358
MW		 7680 if (sdev->tagged_supported) {
7681 if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) {
7682 if (sdev->lun == 0) {
7683 asc_dvc->cfg->can_tagged_qng |= tid_bit;
7684 asc_dvc->use_tagged_qng |= tid_bit;
7685 }
db5ed4df 7686 scsi_change_queue_depth(sdev,
51219358 7687 asc_dvc->max_dvc_qng[sdev->id]);
27c868c2 7688 }
51219358
MW		 7689 } else {
7690 if (sdev->lun == 0) {
7691 asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
7692 asc_dvc->use_tagged_qng &= ~tid_bit;
27c868c2
MW		 7693 }
7694 }
1da177e4 7695
51219358
MW		 7696 if ((sdev->lun == 0) &&
7697 (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) {
7698 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
7699 asc_dvc->cfg->disc_enable);
7700 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
7701 asc_dvc->use_tagged_qng);
7702 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
7703 asc_dvc->cfg->can_tagged_qng);
27c868c2 7704
51219358
MW		 7705 asc_dvc->max_dvc_qng[sdev->id] =
7706 asc_dvc->cfg->max_tag_qng[sdev->id];
7707 AscWriteLramByte(asc_dvc->iop_base,
7708 (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id),
7709 asc_dvc->max_dvc_qng[sdev->id]);
7710 }
7711}
27c868c2 7712
51219358
MW		 7713/*
7714 * Wide Transfers
7715 *
7716 * If the EEPROM enabled WDTR for the device and the device supports wide
7717 * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and
7718 * write the new value to the microcode.
7719 */
7720static void
7721advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask)
7722{
7723 unsigned short cfg_word;
7724 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
7725 if ((cfg_word & tidmask) != 0)
7726 return;
27c868c2 7727
51219358
MW		 7728 cfg_word |= tidmask;
7729 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
27c868c2
MW		 7730
7731 /*
51219358
MW		 7732 * Clear the microcode SDTR and WDTR negotiation done indicators for
7733 * the target to cause it to negotiate with the new setting set above.
7734 * WDTR when accepted causes the target to enter asynchronous mode, so
7735 * SDTR must be negotiated.
27c868c2 7736 */
51219358
MW		 7737 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7738 cfg_word &= ~tidmask;
7739 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7740 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
7741 cfg_word &= ~tidmask;
7742 AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
7743}
1da177e4 7744
51219358
MW		 7745/*
7746 * Synchronous Transfers
7747 *
7748 * If the EEPROM enabled SDTR for the device and the device
7749 * supports synchronous transfers, then turn on the device's
7750 * 'sdtr_able' bit. Write the new value to the microcode.
7751 */
7752static void
7753advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask)
7754{
7755 unsigned short cfg_word;
7756 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
7757 if ((cfg_word & tidmask) != 0)
7758 return;
1da177e4 7759
51219358
MW		 7760 cfg_word |= tidmask;
7761 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
1da177e4 7762
27c868c2 7763 /*
51219358
MW		 7764 * Clear the microcode "SDTR negotiation" done indicator for the
7765 * target to cause it to negotiate with the new setting set above.
27c868c2 7766 */
51219358
MW		 7767 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7768 cfg_word &= ~tidmask;
7769 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7770}
27c868c2 7771
51219358
MW		 7772/*
7773 * PPR (Parallel Protocol Request) Capable
7774 *
7775 * If the device supports DT mode, then it must be PPR capable.
7776 * The PPR message will be used in place of the SDTR and WDTR
7777 * messages to negotiate synchronous speed and offset, transfer
7778 * width, and protocol options.
7779 */
7780static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc,
7781 AdvPortAddr iop_base, unsigned short tidmask)
7782{
7783 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
7784 adv_dvc->ppr_able |= tidmask;
7785 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
7786}
27c868c2 7787
51219358
MW		 7788static void
7789advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc)
7790{
7791 AdvPortAddr iop_base = adv_dvc->iop_base;
7792 unsigned short tidmask = 1 << sdev->id;
7793
7794 if (sdev->lun == 0) {
7795 /*
7796 * Handle WDTR, SDTR, and Tag Queuing. If the feature
7797 * is enabled in the EEPROM and the device supports the
7798 * feature, then enable it in the microcode.
7799 */
27c868c2 7800
51219358
MW		 7801 if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr)
7802 advansys_wide_enable_wdtr(iop_base, tidmask);
7803 if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr)
7804 advansys_wide_enable_sdtr(iop_base, tidmask);
7805 if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr)
7806 advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask);
7807
7808 /*
7809 * Tag Queuing is disabled for the BIOS which runs in polled
7810 * mode and would see no benefit from Tag Queuing. Also by
7811 * disabling Tag Queuing in the BIOS devices with Tag Queuing
7812 * bugs will at least work with the BIOS.
7813 */
7814 if ((adv_dvc->tagqng_able & tidmask) &&
7815 sdev->tagged_supported) {
7816 unsigned short cfg_word;
7817 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
7818 cfg_word |= tidmask;
7819 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
7820 cfg_word);
7821 AdvWriteByteLram(iop_base,
7822 ASC_MC_NUMBER_OF_MAX_CMD + sdev->id,
7823 adv_dvc->max_dvc_qng);
27c868c2
MW		 7824 }
7825 }
1da177e4 7826
db5ed4df
CH		 7827 if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported)
7828 scsi_change_queue_depth(sdev, adv_dvc->max_dvc_qng);
51219358 7829}
27c868c2 7830
51219358
MW		 7831/*
7832 * Set the number of commands to queue per device for the
7833 * specified host adapter.
7834 */
7835static int advansys_slave_configure(struct scsi_device *sdev)
7836{
d2411495 7837 struct asc_board *boardp = shost_priv(sdev->host);
27c868c2 7838
51219358
MW		 7839 if (ASC_NARROW_BOARD(boardp))
7840 advansys_narrow_slave_configure(sdev,
7841 &boardp->dvc_var.asc_dvc_var);
7842 else
7843 advansys_wide_slave_configure(sdev,
7844 &boardp->dvc_var.adv_dvc_var);
1da177e4 7845
51219358
MW		 7846 return 0;
7847}
27c868c2 7848
b249c7fd
MW		 7849static __le32 advansys_get_sense_buffer_dma(struct scsi_cmnd *scp)
7850{
7851 struct asc_board *board = shost_priv(scp->device->host);
7852 scp->SCp.dma_handle = dma_map_single(board->dev, scp->sense_buffer,
b80ca4f7 7853 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
b249c7fd 7854 dma_cache_sync(board->dev, scp->sense_buffer,
b80ca4f7 7855 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
b249c7fd
MW		 7856 return cpu_to_le32(scp->SCp.dma_handle);
7857}
7858
d2411495 7859static int asc_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
05848b6e 7860 struct asc_scsi_q *asc_scsi_q)
51219358 7861{
b249c7fd 7862 struct asc_dvc_var *asc_dvc = &boardp->dvc_var.asc_dvc_var;
52c334e9
MW		 7863 int use_sg;
7864
05848b6e 7865 memset(asc_scsi_q, 0, sizeof(*asc_scsi_q));
27c868c2
MW		 7866
7867 /*
51219358 7868 * Point the ASC_SCSI_Q to the 'struct scsi_cmnd'.
27c868c2 7869 */
b249c7fd
MW		 7870 asc_scsi_q->q2.srb_ptr = advansys_ptr_to_srb(asc_dvc, scp);
7871 if (asc_scsi_q->q2.srb_ptr == BAD_SRB) {
7872 scp->result = HOST_BYTE(DID_SOFT_ERROR);
7873 return ASC_ERROR;
7874 }
27c868c2
MW		 7875
7876 /*
51219358 7877 * Build the ASC_SCSI_Q request.
27c868c2 7878 */
05848b6e
MW		 7879 asc_scsi_q->cdbptr = &scp->cmnd[0];
7880 asc_scsi_q->q2.cdb_len = scp->cmd_len;
7881 asc_scsi_q->q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
7882 asc_scsi_q->q1.target_lun = scp->device->lun;
7883 asc_scsi_q->q2.target_ix =
51219358 7884 ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
b249c7fd 7885 asc_scsi_q->q1.sense_addr = advansys_get_sense_buffer_dma(scp);
b80ca4f7 7886 asc_scsi_q->q1.sense_len = SCSI_SENSE_BUFFERSIZE;
27c868c2
MW		 7887
7888 /*
51219358
MW		 7889 * If there are any outstanding requests for the current target,
7890 * then every 255th request send an ORDERED request. This heuristic
7891 * tries to retain the benefit of request sorting while preventing
7892 * request starvation. 255 is the max number of tags or pending commands
7893 * a device may have outstanding.
7894 *
7895 * The request count is incremented below for every successfully
7896 * started request.
27c868c2 7897 *
27c868c2 7898 */
b249c7fd 7899 if ((asc_dvc->cur_dvc_qng[scp->device->id] > 0) &&
51219358 7900 (boardp->reqcnt[scp->device->id] % 255) == 0) {
68d81f40 7901 asc_scsi_q->q2.tag_code = ORDERED_QUEUE_TAG;
51219358 7902 } else {
68d81f40 7903 asc_scsi_q->q2.tag_code = SIMPLE_QUEUE_TAG;
51219358 7904 }
27c868c2 7905
52c334e9
MW		 7906 /* Build ASC_SCSI_Q */
7907 use_sg = scsi_dma_map(scp);
7908 if (use_sg != 0) {
51219358 7909 int sgcnt;
51219358 7910 struct scatterlist *slp;
05848b6e 7911 struct asc_sg_head *asc_sg_head;
27c868c2 7912
51219358 7913 if (use_sg > scp->device->host->sg_tablesize) {
9d0e96eb
MW		 7914 scmd_printk(KERN_ERR, scp, "use_sg %d > "
7915 "sg_tablesize %d\n", use_sg,
7916 scp->device->host->sg_tablesize);
52c334e9 7917 scsi_dma_unmap(scp);
51219358
MW		 7918 scp->result = HOST_BYTE(DID_ERROR);
7919 return ASC_ERROR;
7920 }
27c868c2 7921
05848b6e
MW		 7922 asc_sg_head = kzalloc(sizeof(asc_scsi_q->sg_head) +
7923 use_sg * sizeof(struct asc_sg_list), GFP_ATOMIC);
7924 if (!asc_sg_head) {
52c334e9 7925 scsi_dma_unmap(scp);
05848b6e
MW		 7926 scp->result = HOST_BYTE(DID_SOFT_ERROR);
7927 return ASC_ERROR;
7928 }
51219358 7929
05848b6e
MW		 7930 asc_scsi_q->q1.cntl |= QC_SG_HEAD;
7931 asc_scsi_q->sg_head = asc_sg_head;
7932 asc_scsi_q->q1.data_cnt = 0;
7933 asc_scsi_q->q1.data_addr = 0;
51219358 7934 /* This is a byte value, otherwise it would need to be swapped. */
05848b6e 7935 asc_sg_head->entry_cnt = asc_scsi_q->q1.sg_queue_cnt = use_sg;
52c334e9 7936 ASC_STATS_ADD(scp->device->host, xfer_elem,
05848b6e 7937 asc_sg_head->entry_cnt);
51219358
MW		 7938
7939 /*
7940 * Convert scatter-gather list into ASC_SG_HEAD list.
7941 */
52c334e9 7942 scsi_for_each_sg(scp, slp, use_sg, sgcnt) {
05848b6e 7943 asc_sg_head->sg_list[sgcnt].addr =
51219358 7944 cpu_to_le32(sg_dma_address(slp));
05848b6e 7945 asc_sg_head->sg_list[sgcnt].bytes =
51219358 7946 cpu_to_le32(sg_dma_len(slp));
52c334e9
MW		 7947 ASC_STATS_ADD(scp->device->host, xfer_sect,
7948 DIV_ROUND_UP(sg_dma_len(slp), 512));
27c868c2
MW		 7949 }
7950 }
1da177e4 7951
52c334e9
MW		 7952 ASC_STATS(scp->device->host, xfer_cnt);
7953
b352f923 7954 ASC_DBG_PRT_ASC_SCSI_Q(2, asc_scsi_q);
51219358
MW		 7955 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
7956
7957 return ASC_NOERROR;
27c868c2 7958}
1da177e4 7959
27c868c2 7960/*
51219358 7961 * Build scatter-gather list for Adv Library (Wide Board).
27c868c2 7962 *
51219358
MW		 7963 * Additional ADV_SG_BLOCK structures will need to be allocated
7964 * if the total number of scatter-gather elements exceeds
7965 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
7966 * assumed to be physically contiguous.
27c868c2 7967 *
51219358
MW		 7968 * Return:
7969 * ADV_SUCCESS(1) - SG List successfully created
7970 * ADV_ERROR(-1) - SG List creation failed
27c868c2 7971 */
51219358 7972static int
d2411495 7973adv_get_sglist(struct asc_board *boardp, adv_req_t *reqp, struct scsi_cmnd *scp,
51219358 7974 int use_sg)
27c868c2 7975{
51219358
MW		 7976 adv_sgblk_t *sgblkp;
7977 ADV_SCSI_REQ_Q *scsiqp;
7978 struct scatterlist *slp;
7979 int sg_elem_cnt;
7980 ADV_SG_BLOCK *sg_block, *prev_sg_block;
7981 ADV_PADDR sg_block_paddr;
27c868c2 7982 int i;
27c868c2 7983
51219358 7984 scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
52c334e9 7985 slp = scsi_sglist(scp);
51219358
MW		 7986 sg_elem_cnt = use_sg;
7987 prev_sg_block = NULL;
7988 reqp->sgblkp = NULL;
1da177e4 7989
51219358
MW		 7990 for (;;) {
7991 /*
7992 * Allocate a 'adv_sgblk_t' structure from the board free
7993 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
7994 * (15) scatter-gather elements.
7995 */
7996 if ((sgblkp = boardp->adv_sgblkp) == NULL) {
b352f923 7997 ASC_DBG(1, "no free adv_sgblk_t\n");
51219358 7998 ASC_STATS(scp->device->host, adv_build_nosg);
1da177e4 7999
51219358
MW		 8000 /*
8001 * Allocation failed. Free 'adv_sgblk_t' structures
8002 * already allocated for the request.
8003 */
8004 while ((sgblkp = reqp->sgblkp) != NULL) {
8005 /* Remove 'sgblkp' from the request list. */
8006 reqp->sgblkp = sgblkp->next_sgblkp;
27c868c2 8007
51219358
MW		 8008 /* Add 'sgblkp' to the board free list. */
8009 sgblkp->next_sgblkp = boardp->adv_sgblkp;
8010 boardp->adv_sgblkp = sgblkp;
8011 }
8012 return ASC_BUSY;
8013 }
1da177e4 8014
51219358
MW		 8015 /* Complete 'adv_sgblk_t' board allocation. */
8016 boardp->adv_sgblkp = sgblkp->next_sgblkp;
8017 sgblkp->next_sgblkp = NULL;
1da177e4 8018
51219358
MW		 8019 /*
8020 * Get 8 byte aligned virtual and physical addresses
8021 * for the allocated ADV_SG_BLOCK structure.
8022 */
8023 sg_block = (ADV_SG_BLOCK *)ADV_8BALIGN(&sgblkp->sg_block);
8024 sg_block_paddr = virt_to_bus(sg_block);
27c868c2 8025
51219358
MW		 8026 /*
8027 * Check if this is the first 'adv_sgblk_t' for the
8028 * request.
8029 */
8030 if (reqp->sgblkp == NULL) {
8031 /* Request's first scatter-gather block. */
8032 reqp->sgblkp = sgblkp;
27c868c2 8033
51219358
MW		 8034 /*
8035 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
8036 * address pointers.
8037 */
8038 scsiqp->sg_list_ptr = sg_block;
8039 scsiqp->sg_real_addr = cpu_to_le32(sg_block_paddr);
8040 } else {
8041 /* Request's second or later scatter-gather block. */
8042 sgblkp->next_sgblkp = reqp->sgblkp;
8043 reqp->sgblkp = sgblkp;
8044
8045 /*
8046 * Point the previous ADV_SG_BLOCK structure to
8047 * the newly allocated ADV_SG_BLOCK structure.
8048 */
8049 prev_sg_block->sg_ptr = cpu_to_le32(sg_block_paddr);
27c868c2 8050 }
1da177e4 8051
51219358
MW		 8052 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
8053 sg_block->sg_list[i].sg_addr =
8054 cpu_to_le32(sg_dma_address(slp));
8055 sg_block->sg_list[i].sg_count =
8056 cpu_to_le32(sg_dma_len(slp));
52c334e9
MW		 8057 ASC_STATS_ADD(scp->device->host, xfer_sect,
8058 DIV_ROUND_UP(sg_dma_len(slp), 512));
27c868c2 8059
51219358
MW		 8060 if (--sg_elem_cnt == 0) { /* Last ADV_SG_BLOCK and scatter-gather entry. */
8061 sg_block->sg_cnt = i + 1;
8062 sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */
8063 return ADV_SUCCESS;
8064 }
8065 slp++;
8066 }
8067 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
8068 prev_sg_block = sg_block;
27c868c2 8069 }
51219358 8070}
1da177e4 8071
51219358
MW		 8072/*
8073 * Build a request structure for the Adv Library (Wide Board).
8074 *
8075 * If an adv_req_t can not be allocated to issue the request,
8076 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
8077 *
8078 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the
8079 * microcode for DMA addresses or math operations are byte swapped
8080 * to little-endian order.
8081 */
8082static int
d2411495 8083adv_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
51219358
MW		 8084 ADV_SCSI_REQ_Q **adv_scsiqpp)
8085{
8086 adv_req_t *reqp;
8087 ADV_SCSI_REQ_Q *scsiqp;
8088 int i;
8089 int ret;
52c334e9 8090 int use_sg;
1da177e4 8091
27c868c2 8092 /*
51219358
MW		 8093 * Allocate an adv_req_t structure from the board to execute
8094 * the command.
27c868c2 8095 */
51219358 8096 if (boardp->adv_reqp == NULL) {
b352f923 8097 ASC_DBG(1, "no free adv_req_t\n");
51219358
MW		 8098 ASC_STATS(scp->device->host, adv_build_noreq);
8099 return ASC_BUSY;
8100 } else {
8101 reqp = boardp->adv_reqp;
8102 boardp->adv_reqp = reqp->next_reqp;
8103 reqp->next_reqp = NULL;
27c868c2 8104 }
1da177e4 8105
27c868c2 8106 /*
51219358 8107 * Get 32-byte aligned ADV_SCSI_REQ_Q and ADV_SG_BLOCK pointers.
27c868c2 8108 */
51219358 8109 scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q);
27c868c2
MW		 8110
8111 /*
51219358 8112 * Initialize the structure.
27c868c2 8113 */
51219358 8114 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
27c868c2
MW		 8115
8116 /*
51219358 8117 * Set the ADV_SCSI_REQ_Q 'srb_ptr' to point to the adv_req_t structure.
27c868c2 8118 */
b249c7fd 8119 scsiqp->srb_ptr = ADV_VADDR_TO_U32(reqp);
27c868c2
MW		 8120
8121 /*
51219358 8122 * Set the adv_req_t 'cmndp' to point to the struct scsi_cmnd structure.
27c868c2 8123 */
51219358 8124 reqp->cmndp = scp;
27c868c2
MW		 8125
8126 /*
51219358 8127 * Build the ADV_SCSI_REQ_Q request.
27c868c2 8128 */
51219358
MW		 8129
8130 /* Set CDB length and copy it to the request structure. */
8131 scsiqp->cdb_len = scp->cmd_len;
8132 /* Copy first 12 CDB bytes to cdb[]. */
8133 for (i = 0; i < scp->cmd_len && i < 12; i++) {
8134 scsiqp->cdb[i] = scp->cmnd[i];
8135 }
8136 /* Copy last 4 CDB bytes, if present, to cdb16[]. */
8137 for (; i < scp->cmd_len; i++) {
8138 scsiqp->cdb16[i - 12] = scp->cmnd[i];
27c868c2 8139 }
1da177e4 8140
51219358
MW		 8141 scsiqp->target_id = scp->device->id;
8142 scsiqp->target_lun = scp->device->lun;
8143
8144 scsiqp->sense_addr = cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
b80ca4f7 8145 scsiqp->sense_len = SCSI_SENSE_BUFFERSIZE;
27c868c2 8146
52c334e9 8147 /* Build ADV_SCSI_REQ_Q */
51219358 8148
52c334e9
MW		 8149 use_sg = scsi_dma_map(scp);
8150 if (use_sg == 0) {
8151 /* Zero-length transfer */
51219358 8152 reqp->sgblkp = NULL;
52c334e9
MW		 8153 scsiqp->data_cnt = 0;
8154 scsiqp->vdata_addr = NULL;
8155
8156 scsiqp->data_addr = 0;
51219358
MW		 8157 scsiqp->sg_list_ptr = NULL;
8158 scsiqp->sg_real_addr = 0;
51219358 8159 } else {
51219358 8160 if (use_sg > ADV_MAX_SG_LIST) {
9d0e96eb
MW		 8161 scmd_printk(KERN_ERR, scp, "use_sg %d > "
8162 "ADV_MAX_SG_LIST %d\n", use_sg,
51219358 8163 scp->device->host->sg_tablesize);
52c334e9 8164 scsi_dma_unmap(scp);
51219358
MW		 8165 scp->result = HOST_BYTE(DID_ERROR);
8166
8167 /*
8168 * Free the 'adv_req_t' structure by adding it back
8169 * to the board free list.
8170 */
8171 reqp->next_reqp = boardp->adv_reqp;
8172 boardp->adv_reqp = reqp;
8173
8174 return ASC_ERROR;
8175 }
8176
52c334e9
MW		 8177 scsiqp->data_cnt = cpu_to_le32(scsi_bufflen(scp));
8178
51219358
MW		 8179 ret = adv_get_sglist(boardp, reqp, scp, use_sg);
8180 if (ret != ADV_SUCCESS) {
8181 /*
8182 * Free the adv_req_t structure by adding it back to
8183 * the board free list.
8184 */
8185 reqp->next_reqp = boardp->adv_reqp;
8186 boardp->adv_reqp = reqp;
8187
8188 return ret;
8189 }
8190
52c334e9 8191 ASC_STATS_ADD(scp->device->host, xfer_elem, use_sg);
27c868c2 8192 }
1da177e4 8193
52c334e9
MW		 8194 ASC_STATS(scp->device->host, xfer_cnt);
8195
51219358
MW		 8196 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
8197 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
27c868c2 8198
51219358 8199 *adv_scsiqpp = scsiqp;
27c868c2 8200
51219358
MW		 8201 return ASC_NOERROR;
8202}
8203
8204static int AscSgListToQueue(int sg_list)
8205{
8206 int n_sg_list_qs;
8207
8208 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
8209 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
8210 n_sg_list_qs++;
8211 return n_sg_list_qs + 1;
8212}
8213
8214static uint
8215AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs)
8216{
8217 uint cur_used_qs;
8218 uint cur_free_qs;
8219 ASC_SCSI_BIT_ID_TYPE target_id;
8220 uchar tid_no;
8221
8222 target_id = ASC_TIX_TO_TARGET_ID(target_ix);
8223 tid_no = ASC_TIX_TO_TID(target_ix);
8224 if ((asc_dvc->unit_not_ready & target_id) ||
8225 (asc_dvc->queue_full_or_busy & target_id)) {
8226 return 0;
8227 }
8228 if (n_qs == 1) {
8229 cur_used_qs = (uint) asc_dvc->cur_total_qng +
8230 (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q;
8231 } else {
8232 cur_used_qs = (uint) asc_dvc->cur_total_qng +
8233 (uint) ASC_MIN_FREE_Q;
8234 }
8235 if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
8236 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
8237 if (asc_dvc->cur_dvc_qng[tid_no] >=
8238 asc_dvc->max_dvc_qng[tid_no]) {
8239 return 0;
8240 }
8241 return cur_free_qs;
8242 }
8243 if (n_qs > 1) {
8244 if ((n_qs > asc_dvc->last_q_shortage)
8245 && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
8246 asc_dvc->last_q_shortage = n_qs;
8247 }
8248 }
8249 return 0;
8250}
8251
8252static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head)
8253{
8254 ushort q_addr;
8255 uchar next_qp;
8256 uchar q_status;
8257
8258 q_addr = ASC_QNO_TO_QADDR(free_q_head);
8259 q_status = (uchar)AscReadLramByte(iop_base,
8260 (ushort)(q_addr +
8261 ASC_SCSIQ_B_STATUS));
8262 next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD));
8263 if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END))
8264 return next_qp;
8265 return ASC_QLINK_END;
8266}
8267
8268static uchar
8269AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q)
8270{
8271 uchar i;
27c868c2 8272
51219358
MW		 8273 for (i = 0; i < n_free_q; i++) {
8274 free_q_head = AscAllocFreeQueue(iop_base, free_q_head);
8275 if (free_q_head == ASC_QLINK_END)
8276 break;
8277 }
8278 return free_q_head;
8279}
27c868c2 8280
51219358
MW		 8281/*
8282 * void
8283 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8284 *
8285 * Calling/Exit State:
8286 * none
8287 *
8288 * Description:
8289 * Output an ASC_SCSI_Q structure to the chip
8290 */
8291static void
8292DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8293{
8294 int i;
8295
8296 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
8297 AscSetChipLramAddr(iop_base, s_addr);
8298 for (i = 0; i < 2 * words; i += 2) {
8299 if (i == 4 || i == 20) {
8300 continue;
8301 }
8302 outpw(iop_base + IOP_RAM_DATA,
8303 ((ushort)outbuf[i + 1] << 8) | outbuf[i]);
27c868c2 8304 }
51219358 8305}
1da177e4 8306
51219358
MW		 8307static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
8308{
8309 ushort q_addr;
8310 uchar tid_no;
8311 uchar sdtr_data;
8312 uchar syn_period_ix;
8313 uchar syn_offset;
8314 PortAddr iop_base;
8315
8316 iop_base = asc_dvc->iop_base;
8317 if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
8318 ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
8319 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
8320 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8321 syn_period_ix =
8322 (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
8323 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
8324 AscMsgOutSDTR(asc_dvc,
8325 asc_dvc->sdtr_period_tbl[syn_period_ix],
8326 syn_offset);
8327 scsiq->q1.cntl |= QC_MSG_OUT;
8328 }
8329 q_addr = ASC_QNO_TO_QADDR(q_no);
8330 if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
68d81f40 8331 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG;
27c868c2 8332 }
51219358
MW		 8333 scsiq->q1.status = QS_FREE;
8334 AscMemWordCopyPtrToLram(iop_base,
8335 q_addr + ASC_SCSIQ_CDB_BEG,
8336 (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1);
8337
8338 DvcPutScsiQ(iop_base,
8339 q_addr + ASC_SCSIQ_CPY_BEG,
8340 (uchar *)&scsiq->q1.cntl,
8341 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
8342 AscWriteLramWord(iop_base,
8343 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS),
8344 (ushort)(((ushort)scsiq->q1.
8345 q_no << 8) | (ushort)QS_READY));
8346 return 1;
8347}
8348
8349static int
8350AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
8351{
8352 int sta;
8353 int i;
8354 ASC_SG_HEAD *sg_head;
8355 ASC_SG_LIST_Q scsi_sg_q;
8356 ASC_DCNT saved_data_addr;
8357 ASC_DCNT saved_data_cnt;
8358 PortAddr iop_base;
8359 ushort sg_list_dwords;
8360 ushort sg_index;
8361 ushort sg_entry_cnt;
8362 ushort q_addr;
8363 uchar next_qp;
1da177e4 8364
51219358
MW		 8365 iop_base = asc_dvc->iop_base;
8366 sg_head = scsiq->sg_head;
8367 saved_data_addr = scsiq->q1.data_addr;
8368 saved_data_cnt = scsiq->q1.data_cnt;
8369 scsiq->q1.data_addr = (ASC_PADDR) sg_head->sg_list[0].addr;
8370 scsiq->q1.data_cnt = (ASC_DCNT) sg_head->sg_list[0].bytes;
8371#if CC_VERY_LONG_SG_LIST
27c868c2 8372 /*
51219358
MW		 8373 * If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST
8374 * then not all SG elements will fit in the allocated queues.
8375 * The rest of the SG elements will be copied when the RISC
8376 * completes the SG elements that fit and halts.
27c868c2 8377 */
51219358
MW		 8378 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
8379 /*
8380 * Set sg_entry_cnt to be the number of SG elements that
8381 * will fit in the allocated SG queues. It is minus 1, because
8382 * the first SG element is handled above. ASC_MAX_SG_LIST is
8383 * already inflated by 1 to account for this. For example it
8384 * may be 50 which is 1 + 7 queues * 7 SG elements.
8385 */
8386 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
27c868c2 8387
51219358
MW		 8388 /*
8389 * Keep track of remaining number of SG elements that will
8390 * need to be handled from a_isr.c.
8391 */
8392 scsiq->remain_sg_entry_cnt =
8393 sg_head->entry_cnt - ASC_MAX_SG_LIST;
8394 } else {
8395#endif /* CC_VERY_LONG_SG_LIST */
8396 /*
8397 * Set sg_entry_cnt to be the number of SG elements that
8398 * will fit in the allocated SG queues. It is minus 1, because
8399 * the first SG element is handled above.
8400 */
8401 sg_entry_cnt = sg_head->entry_cnt - 1;
8402#if CC_VERY_LONG_SG_LIST
8403 }
8404#endif /* CC_VERY_LONG_SG_LIST */
8405 if (sg_entry_cnt != 0) {
8406 scsiq->q1.cntl |= QC_SG_HEAD;
8407 q_addr = ASC_QNO_TO_QADDR(q_no);
8408 sg_index = 1;
8409 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
8410 scsi_sg_q.sg_head_qp = q_no;
8411 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
8412 for (i = 0; i < sg_head->queue_cnt; i++) {
8413 scsi_sg_q.seq_no = i + 1;
8414 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
8415 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
8416 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
8417 if (i == 0) {
8418 scsi_sg_q.sg_list_cnt =
8419 ASC_SG_LIST_PER_Q;
8420 scsi_sg_q.sg_cur_list_cnt =
8421 ASC_SG_LIST_PER_Q;
8422 } else {
8423 scsi_sg_q.sg_list_cnt =
8424 ASC_SG_LIST_PER_Q - 1;
8425 scsi_sg_q.sg_cur_list_cnt =
8426 ASC_SG_LIST_PER_Q - 1;
8427 }
8428 } else {
8429#if CC_VERY_LONG_SG_LIST
8430 /*
8431 * This is the last SG queue in the list of
8432 * allocated SG queues. If there are more
8433 * SG elements than will fit in the allocated
8434 * queues, then set the QCSG_SG_XFER_MORE flag.
8435 */
8436 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
8437 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
8438 } else {
8439#endif /* CC_VERY_LONG_SG_LIST */
8440 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
8441#if CC_VERY_LONG_SG_LIST
8442 }
8443#endif /* CC_VERY_LONG_SG_LIST */
8444 sg_list_dwords = sg_entry_cnt << 1;
8445 if (i == 0) {
8446 scsi_sg_q.sg_list_cnt = sg_entry_cnt;
8447 scsi_sg_q.sg_cur_list_cnt =
8448 sg_entry_cnt;
8449 } else {
8450 scsi_sg_q.sg_list_cnt =
8451 sg_entry_cnt - 1;
8452 scsi_sg_q.sg_cur_list_cnt =
8453 sg_entry_cnt - 1;
8454 }
8455 sg_entry_cnt = 0;
8456 }
8457 next_qp = AscReadLramByte(iop_base,
8458 (ushort)(q_addr +
8459 ASC_SCSIQ_B_FWD));
8460 scsi_sg_q.q_no = next_qp;
8461 q_addr = ASC_QNO_TO_QADDR(next_qp);
8462 AscMemWordCopyPtrToLram(iop_base,
8463 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
8464 (uchar *)&scsi_sg_q,
8465 sizeof(ASC_SG_LIST_Q) >> 1);
8466 AscMemDWordCopyPtrToLram(iop_base,
8467 q_addr + ASC_SGQ_LIST_BEG,
8468 (uchar *)&sg_head->
8469 sg_list[sg_index],
8470 sg_list_dwords);
8471 sg_index += ASC_SG_LIST_PER_Q;
8472 scsiq->next_sg_index = sg_index;
27c868c2 8473 }
51219358
MW		 8474 } else {
8475 scsiq->q1.cntl &= ~QC_SG_HEAD;
27c868c2 8476 }
51219358
MW		 8477 sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
8478 scsiq->q1.data_addr = saved_data_addr;
8479 scsiq->q1.data_cnt = saved_data_cnt;
8480 return (sta);
8481}
27c868c2 8482
51219358
MW		 8483static int
8484AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required)
8485{
8486 PortAddr iop_base;
8487 uchar free_q_head;
8488 uchar next_qp;
8489 uchar tid_no;
8490 uchar target_ix;
8491 int sta;
27c868c2 8492
51219358
MW		 8493 iop_base = asc_dvc->iop_base;
8494 target_ix = scsiq->q2.target_ix;
8495 tid_no = ASC_TIX_TO_TID(target_ix);
8496 sta = 0;
8497 free_q_head = (uchar)AscGetVarFreeQHead(iop_base);
8498 if (n_q_required > 1) {
8499 next_qp = AscAllocMultipleFreeQueue(iop_base, free_q_head,
8500 (uchar)n_q_required);
8501 if (next_qp != ASC_QLINK_END) {
8502 asc_dvc->last_q_shortage = 0;
8503 scsiq->sg_head->queue_cnt = n_q_required - 1;
8504 scsiq->q1.q_no = free_q_head;
8505 sta = AscPutReadySgListQueue(asc_dvc, scsiq,
8506 free_q_head);
8507 }
8508 } else if (n_q_required == 1) {
8509 next_qp = AscAllocFreeQueue(iop_base, free_q_head);
8510 if (next_qp != ASC_QLINK_END) {
8511 scsiq->q1.q_no = free_q_head;
8512 sta = AscPutReadyQueue(asc_dvc, scsiq, free_q_head);
27c868c2
MW		 8513 }
8514 }
51219358
MW		 8515 if (sta == 1) {
8516 AscPutVarFreeQHead(iop_base, next_qp);
8517 asc_dvc->cur_total_qng += n_q_required;
8518 asc_dvc->cur_dvc_qng[tid_no]++;
27c868c2 8519 }
51219358
MW		 8520 return sta;
8521}
27c868c2 8522
51219358
MW		 8523#define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16
8524static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = {
8525 INQUIRY,
8526 REQUEST_SENSE,
8527 READ_CAPACITY,
8528 READ_TOC,
8529 MODE_SELECT,
8530 MODE_SENSE,
8531 MODE_SELECT_10,
8532 MODE_SENSE_10,
8533 0xFF,
8534 0xFF,
8535 0xFF,
8536 0xFF,
8537 0xFF,
8538 0xFF,
8539 0xFF,
8540 0xFF
8541};
27c868c2 8542
51219358
MW		 8543static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
8544{
8545 PortAddr iop_base;
8546 int sta;
8547 int n_q_required;
8548 int disable_syn_offset_one_fix;
8549 int i;
8550 ASC_PADDR addr;
8551 ushort sg_entry_cnt = 0;
8552 ushort sg_entry_cnt_minus_one = 0;
8553 uchar target_ix;
8554 uchar tid_no;
8555 uchar sdtr_data;
8556 uchar extra_bytes;
8557 uchar scsi_cmd;
8558 uchar disable_cmd;
8559 ASC_SG_HEAD *sg_head;
8560 ASC_DCNT data_cnt;
27c868c2 8561
51219358
MW		 8562 iop_base = asc_dvc->iop_base;
8563 sg_head = scsiq->sg_head;
8564 if (asc_dvc->err_code != 0)
8565 return (ERR);
8566 scsiq->q1.q_no = 0;
8567 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
8568 scsiq->q1.extra_bytes = 0;
27c868c2 8569 }
51219358
MW		 8570 sta = 0;
8571 target_ix = scsiq->q2.target_ix;
8572 tid_no = ASC_TIX_TO_TID(target_ix);
8573 n_q_required = 1;
8574 if (scsiq->cdbptr[0] == REQUEST_SENSE) {
8575 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
8576 asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
8577 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8578 AscMsgOutSDTR(asc_dvc,
8579 asc_dvc->
8580 sdtr_period_tbl[(sdtr_data >> 4) &
8581 (uchar)(asc_dvc->
8582 max_sdtr_index -
8583 1)],
8584 (uchar)(sdtr_data & (uchar)
8585 ASC_SYN_MAX_OFFSET));
8586 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
8587 }
8588 }
8589 if (asc_dvc->in_critical_cnt != 0) {
8590 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
8591 return (ERR);
8592 }
8593 asc_dvc->in_critical_cnt++;
8594 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
8595 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
8596 asc_dvc->in_critical_cnt--;
8597 return (ERR);
8598 }
8599#if !CC_VERY_LONG_SG_LIST
8600 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
8601 asc_dvc->in_critical_cnt--;
8602 return (ERR);
8603 }
8604#endif /* !CC_VERY_LONG_SG_LIST */
8605 if (sg_entry_cnt == 1) {
8606 scsiq->q1.data_addr =
8607 (ADV_PADDR)sg_head->sg_list[0].addr;
8608 scsiq->q1.data_cnt =
8609 (ADV_DCNT)sg_head->sg_list[0].bytes;
8610 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
8611 }
8612 sg_entry_cnt_minus_one = sg_entry_cnt - 1;
8613 }
8614 scsi_cmd = scsiq->cdbptr[0];
8615 disable_syn_offset_one_fix = FALSE;
8616 if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
8617 !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
8618 if (scsiq->q1.cntl & QC_SG_HEAD) {
8619 data_cnt = 0;
8620 for (i = 0; i < sg_entry_cnt; i++) {
8621 data_cnt +=
8622 (ADV_DCNT)le32_to_cpu(sg_head->sg_list[i].
8623 bytes);
8624 }
8625 } else {
8626 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
8627 }
8628 if (data_cnt != 0UL) {
8629 if (data_cnt < 512UL) {
8630 disable_syn_offset_one_fix = TRUE;
8631 } else {
8632 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST;
8633 i++) {
8634 disable_cmd =
8635 _syn_offset_one_disable_cmd[i];
8636 if (disable_cmd == 0xFF) {
8637 break;
8638 }
8639 if (scsi_cmd == disable_cmd) {
8640 disable_syn_offset_one_fix =
8641 TRUE;
8642 break;
8643 }
8644 }
8645 }
8646 }
8647 }
8648 if (disable_syn_offset_one_fix) {
68d81f40 8649 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG;
51219358
MW		 8650 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
8651 ASC_TAG_FLAG_DISABLE_DISCONNECT);
8652 } else {
8653 scsiq->q2.tag_code &= 0x27;
8654 }
8655 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
8656 if (asc_dvc->bug_fix_cntl) {
8657 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
8658 if ((scsi_cmd == READ_6) ||
8659 (scsi_cmd == READ_10)) {
8660 addr =
8661 (ADV_PADDR)le32_to_cpu(sg_head->
8662 sg_list
8663 [sg_entry_cnt_minus_one].
8664 addr) +
8665 (ADV_DCNT)le32_to_cpu(sg_head->
8666 sg_list
8667 [sg_entry_cnt_minus_one].
8668 bytes);
8669 extra_bytes =
8670 (uchar)((ushort)addr & 0x0003);
8671 if ((extra_bytes != 0)
8672 &&
8673 ((scsiq->q2.
8674 tag_code &
8675 ASC_TAG_FLAG_EXTRA_BYTES)
8676 == 0)) {
8677 scsiq->q2.tag_code |=
8678 ASC_TAG_FLAG_EXTRA_BYTES;
8679 scsiq->q1.extra_bytes =
8680 extra_bytes;
8681 data_cnt =
8682 le32_to_cpu(sg_head->
8683 sg_list
8684 [sg_entry_cnt_minus_one].
8685 bytes);
8686 data_cnt -=
8687 (ASC_DCNT) extra_bytes;
8688 sg_head->
8689 sg_list
8690 [sg_entry_cnt_minus_one].
8691 bytes =
8692 cpu_to_le32(data_cnt);
8693 }
8694 }
8695 }
8696 }
8697 sg_head->entry_to_copy = sg_head->entry_cnt;
8698#if CC_VERY_LONG_SG_LIST
27c868c2 8699 /*
51219358
MW		 8700 * Set the sg_entry_cnt to the maximum possible. The rest of
8701 * the SG elements will be copied when the RISC completes the
8702 * SG elements that fit and halts.
27c868c2 8703 */
51219358
MW		 8704 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
8705 sg_entry_cnt = ASC_MAX_SG_LIST;
8706 }
8707#endif /* CC_VERY_LONG_SG_LIST */
8708 n_q_required = AscSgListToQueue(sg_entry_cnt);
8709 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
8710 (uint) n_q_required)
8711 || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
8712 if ((sta =
8713 AscSendScsiQueue(asc_dvc, scsiq,
8714 n_q_required)) == 1) {
8715 asc_dvc->in_critical_cnt--;
8716 return (sta);
27c868c2 8717 }
51219358
MW		 8718 }
8719 } else {
8720 if (asc_dvc->bug_fix_cntl) {
8721 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
8722 if ((scsi_cmd == READ_6) ||
8723 (scsi_cmd == READ_10)) {
8724 addr =
8725 le32_to_cpu(scsiq->q1.data_addr) +
8726 le32_to_cpu(scsiq->q1.data_cnt);
8727 extra_bytes =
8728 (uchar)((ushort)addr & 0x0003);
8729 if ((extra_bytes != 0)
8730 &&
8731 ((scsiq->q2.
8732 tag_code &
8733 ASC_TAG_FLAG_EXTRA_BYTES)
8734 == 0)) {
8735 data_cnt =
8736 le32_to_cpu(scsiq->q1.
8737 data_cnt);
8738 if (((ushort)data_cnt & 0x01FF)
8739 == 0) {
8740 scsiq->q2.tag_code |=
8741 ASC_TAG_FLAG_EXTRA_BYTES;
8742 data_cnt -= (ASC_DCNT)
8743 extra_bytes;
8744 scsiq->q1.data_cnt =
8745 cpu_to_le32
8746 (data_cnt);
8747 scsiq->q1.extra_bytes =
8748 extra_bytes;
8749 }
8750 }
8751 }
8752 }
8753 }
8754 n_q_required = 1;
8755 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
8756 ((scsiq->q1.cntl & QC_URGENT) != 0)) {
8757 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
8758 n_q_required)) == 1) {
8759 asc_dvc->in_critical_cnt--;
8760 return (sta);
27c868c2
MW		 8761 }
8762 }
8763 }
51219358
MW		 8764 asc_dvc->in_critical_cnt--;
8765 return (sta);
1da177e4
LT		 8766}
8767
8768/*
51219358 8769 * AdvExeScsiQueue() - Send a request to the RISC microcode program.
1da177e4 8770 *
51219358
MW		 8771 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
8772 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
8773 * RISC to notify it a new command is ready to be executed.
8774 *
8775 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
8776 * set to SCSI_MAX_RETRY.
8777 *
8778 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode
8779 * for DMA addresses or math operations are byte swapped to little-endian
8780 * order.
8781 *
8782 * Return:
8783 * ADV_SUCCESS(1) - The request was successfully queued.
8784 * ADV_BUSY(0) - Resource unavailable; Retry again after pending
8785 * request completes.
8786 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure
8787 * host IC error.
8788 */
8789static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq)
8790{
8791 AdvPortAddr iop_base;
51219358
MW		 8792 ADV_PADDR req_paddr;
8793 ADV_CARR_T *new_carrp;
1da177e4 8794
27c868c2 8795 /*
51219358 8796 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
27c868c2 8797 */
51219358
MW		 8798 if (scsiq->target_id > ADV_MAX_TID) {
8799 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
8800 scsiq->done_status = QD_WITH_ERROR;
27c868c2
MW		 8801 return ADV_ERROR;
8802 }
1da177e4 8803
51219358 8804 iop_base = asc_dvc->iop_base;
1da177e4 8805
27c868c2 8806 /*
51219358
MW		 8807 * Allocate a carrier ensuring at least one carrier always
8808 * remains on the freelist and initialize fields.
27c868c2 8809 */
51219358
MW		 8810 if ((new_carrp = asc_dvc->carr_freelist) == NULL) {
8811 return ADV_BUSY;
27c868c2 8812 }
51219358
MW		 8813 asc_dvc->carr_freelist = (ADV_CARR_T *)
8814 ADV_U32_TO_VADDR(le32_to_cpu(new_carrp->next_vpa));
8815 asc_dvc->carr_pending_cnt++;
1da177e4 8816
27c868c2 8817 /*
51219358
MW		 8818 * Set the carrier to be a stopper by setting 'next_vpa'
8819 * to the stopper value. The current stopper will be changed
8820 * below to point to the new stopper.
27c868c2 8821 */
51219358 8822 new_carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
27c868c2
MW		 8823
8824 /*
51219358 8825 * Clear the ADV_SCSI_REQ_Q done flag.
27c868c2 8826 */
51219358 8827 scsiq->a_flag &= ~ADV_SCSIQ_DONE;
27c868c2 8828
fd625f47 8829 req_paddr = virt_to_bus(scsiq);
51219358 8830 BUG_ON(req_paddr & 31);
51219358
MW		 8831 /* Wait for assertion before making little-endian */
8832 req_paddr = cpu_to_le32(req_paddr);
27c868c2 8833
51219358
MW		 8834 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
8835 scsiq->scsiq_ptr = cpu_to_le32(ADV_VADDR_TO_U32(scsiq));
8836 scsiq->scsiq_rptr = req_paddr;
8837
8838 scsiq->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->icq_sp));
27c868c2 8839 /*
51219358
MW		 8840 * Every ADV_CARR_T.carr_pa is byte swapped to little-endian
8841 * order during initialization.
27c868c2 8842 */
51219358 8843 scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
1da177e4 8844
27c868c2 8845 /*
51219358
MW		 8846 * Use the current stopper to send the ADV_SCSI_REQ_Q command to
8847 * the microcode. The newly allocated stopper will become the new
8848 * stopper.
27c868c2 8849 */
51219358 8850 asc_dvc->icq_sp->areq_vpa = req_paddr;
1da177e4 8851
27c868c2 8852 /*
51219358
MW		 8853 * Set the 'next_vpa' pointer for the old stopper to be the
8854 * physical address of the new stopper. The RISC can only
8855 * follow physical addresses.
27c868c2 8856 */
51219358 8857 asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
27c868c2
MW		 8858
8859 /*
51219358 8860 * Set the host adapter stopper pointer to point to the new carrier.
27c868c2 8861 */
51219358
MW		 8862 asc_dvc->icq_sp = new_carrp;
8863
8864 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
8865 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
8866 /*
8867 * Tickle the RISC to tell it to read its Command Queue Head pointer.
8868 */
8869 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
8870 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
8871 /*
8872 * Clear the tickle value. In the ASC-3550 the RISC flag
8873 * command 'clr_tickle_a' does not work unless the host
8874 * value is cleared.
8875 */
8876 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
8877 ADV_TICKLE_NOP);
8878 }
8879 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8880 /*
8881 * Notify the RISC a carrier is ready by writing the physical
8882 * address of the new carrier stopper to the COMMA register.
8883 */
8884 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
8885 le32_to_cpu(new_carrp->carr_pa));
27c868c2 8886 }
1da177e4 8887
51219358
MW		 8888 return ADV_SUCCESS;
8889}
8890
8891/*
8892 * Execute a single 'Scsi_Cmnd'.
51219358
MW		 8893 */
8894static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
8895{
41d2493d 8896 int ret, err_code;
d2411495 8897 struct asc_board *boardp = shost_priv(scp->device->host);
51219358 8898
b352f923 8899 ASC_DBG(1, "scp 0x%p\n", scp);
27c868c2 8900
51219358 8901 if (ASC_NARROW_BOARD(boardp)) {
41d2493d 8902 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
05848b6e 8903 struct asc_scsi_q asc_scsi_q;
27c868c2 8904
41d2493d 8905 /* asc_build_req() can not return ASC_BUSY. */
05848b6e
MW		 8906 ret = asc_build_req(boardp, scp, &asc_scsi_q);
8907 if (ret == ASC_ERROR) {
51219358
MW		 8908 ASC_STATS(scp->device->host, build_error);
8909 return ASC_ERROR;
8910 }
1da177e4 8911
41d2493d 8912 ret = AscExeScsiQueue(asc_dvc, &asc_scsi_q);
05848b6e 8913 kfree(asc_scsi_q.sg_head);
41d2493d 8914 err_code = asc_dvc->err_code;
51219358 8915 } else {
41d2493d
MW		 8916 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
8917 ADV_SCSI_REQ_Q *adv_scsiqp;
27c868c2 8918
51219358
MW		 8919 switch (adv_build_req(boardp, scp, &adv_scsiqp)) {
8920 case ASC_NOERROR:
b352f923 8921 ASC_DBG(3, "adv_build_req ASC_NOERROR\n");
51219358
MW		 8922 break;
8923 case ASC_BUSY:
b352f923 8924 ASC_DBG(1, "adv_build_req ASC_BUSY\n");
51219358
MW		 8925 /*
8926 * The asc_stats fields 'adv_build_noreq' and
8927 * 'adv_build_nosg' count wide board busy conditions.
8928 * They are updated in adv_build_req and
8929 * adv_get_sglist, respectively.
8930 */
8931 return ASC_BUSY;
8932 case ASC_ERROR:
8933 default:
b352f923 8934 ASC_DBG(1, "adv_build_req ASC_ERROR\n");
51219358
MW		 8935 ASC_STATS(scp->device->host, build_error);
8936 return ASC_ERROR;
8937 }
8938
41d2493d
MW		 8939 ret = AdvExeScsiQueue(adv_dvc, adv_scsiqp);
8940 err_code = adv_dvc->err_code;
8941 }
8942
8943 switch (ret) {
8944 case ASC_NOERROR:
8945 ASC_STATS(scp->device->host, exe_noerror);
8946 /*
8947 * Increment monotonically increasing per device
8948 * successful request counter. Wrapping doesn't matter.
8949 */
8950 boardp->reqcnt[scp->device->id]++;
b352f923 8951 ASC_DBG(1, "ExeScsiQueue() ASC_NOERROR\n");
41d2493d
MW		 8952 break;
8953 case ASC_BUSY:
8954 ASC_STATS(scp->device->host, exe_busy);
8955 break;
8956 case ASC_ERROR:
9d0e96eb
MW		 8957 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() ASC_ERROR, "
8958 "err_code 0x%x\n", err_code);
41d2493d
MW		 8959 ASC_STATS(scp->device->host, exe_error);
8960 scp->result = HOST_BYTE(DID_ERROR);
8961 break;
8962 default:
9d0e96eb
MW		 8963 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() unknown, "
8964 "err_code 0x%x\n", err_code);
41d2493d
MW		 8965 ASC_STATS(scp->device->host, exe_unknown);
8966 scp->result = HOST_BYTE(DID_ERROR);
8967 break;
27c868c2 8968 }
1da177e4 8969
b352f923 8970 ASC_DBG(1, "end\n");
51219358
MW		 8971 return ret;
8972}
27c868c2 8973
51219358
MW		 8974/*
8975 * advansys_queuecommand() - interrupt-driven I/O entrypoint.
8976 *
8977 * This function always returns 0. Command return status is saved
8978 * in the 'scp' result field.
8979 */
8980static int
f281233d 8981advansys_queuecommand_lck(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *))
51219358
MW		 8982{
8983 struct Scsi_Host *shost = scp->device->host;
51219358 8984 int asc_res, result = 0;
27c868c2 8985
51219358
MW		 8986 ASC_STATS(shost, queuecommand);
8987 scp->scsi_done = done;
27c868c2 8988
51219358 8989 asc_res = asc_execute_scsi_cmnd(scp);
51219358
MW		 8990
8991 switch (asc_res) {
8992 case ASC_NOERROR:
8993 break;
8994 case ASC_BUSY:
8995 result = SCSI_MLQUEUE_HOST_BUSY;
8996 break;
8997 case ASC_ERROR:
8998 default:
8999 asc_scsi_done(scp);
9000 break;
9001 }
9002
9003 return result;
9004}
9005
f281233d
JG		 9006static DEF_SCSI_QCMD(advansys_queuecommand)
9007
6f039790 9008static ushort AscGetEisaChipCfg(PortAddr iop_base)
51219358
MW		 9009{
9010 PortAddr eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
9011 (PortAddr) (ASC_EISA_CFG_IOP_MASK);
9012 return inpw(eisa_cfg_iop);
9013}
9014
9015/*
9016 * Return the BIOS address of the adapter at the specified
9017 * I/O port and with the specified bus type.
9018 */
6f039790
GKH		 9019static unsigned short AscGetChipBiosAddress(PortAddr iop_base,
9020 unsigned short bus_type)
51219358
MW		 9021{
9022 unsigned short cfg_lsw;
9023 unsigned short bios_addr;
27c868c2
MW		 9024
9025 /*
51219358
MW		 9026 * The PCI BIOS is re-located by the motherboard BIOS. Because
9027 * of this the driver can not determine where a PCI BIOS is
9028 * loaded and executes.
27c868c2 9029 */
51219358
MW		 9030 if (bus_type & ASC_IS_PCI)
9031 return 0;
27c868c2 9032
51219358
MW		 9033 if ((bus_type & ASC_IS_EISA) != 0) {
9034 cfg_lsw = AscGetEisaChipCfg(iop_base);
9035 cfg_lsw &= 0x000F;
9036 bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE;
9037 return bios_addr;
9038 }
27c868c2 9039
51219358 9040 cfg_lsw = AscGetChipCfgLsw(iop_base);
27c868c2
MW		 9041
9042 /*
51219358 9043 * ISA PnP uses the top bit as the 32K BIOS flag
27c868c2 9044 */
51219358
MW		 9045 if (bus_type == ASC_IS_ISAPNP)
9046 cfg_lsw &= 0x7FFF;
9047 bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE;
9048 return bios_addr;
9049}
9050
6f039790 9051static uchar AscSetChipScsiID(PortAddr iop_base, uchar new_host_id)
51219358
MW		 9052{
9053 ushort cfg_lsw;
9054
9055 if (AscGetChipScsiID(iop_base) == new_host_id) {
9056 return (new_host_id);
27c868c2 9057 }
51219358
MW		 9058 cfg_lsw = AscGetChipCfgLsw(iop_base);
9059 cfg_lsw &= 0xF8FF;
9060 cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8);
9061 AscSetChipCfgLsw(iop_base, cfg_lsw);
9062 return (AscGetChipScsiID(iop_base));
9063}
27c868c2 9064
6f039790 9065static unsigned char AscGetChipScsiCtrl(PortAddr iop_base)
51219358
MW		 9066{
9067 unsigned char sc;
27c868c2 9068
51219358
MW		 9069 AscSetBank(iop_base, 1);
9070 sc = inp(iop_base + IOP_REG_SC);
9071 AscSetBank(iop_base, 0);
9072 return sc;
9073}
27c868c2 9074
6f039790
GKH		 9075static unsigned char AscGetChipVersion(PortAddr iop_base,
9076 unsigned short bus_type)
51219358
MW		 9077{
9078 if (bus_type & ASC_IS_EISA) {
9079 PortAddr eisa_iop;
9080 unsigned char revision;
9081 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
9082 (PortAddr) ASC_EISA_REV_IOP_MASK;
9083 revision = inp(eisa_iop);
9084 return ASC_CHIP_MIN_VER_EISA - 1 + revision;
27c868c2 9085 }
51219358
MW		 9086 return AscGetChipVerNo(iop_base);
9087}
27c868c2 9088
51219358 9089#ifdef CONFIG_ISA
6f039790 9090static void AscEnableIsaDma(uchar dma_channel)
51219358
MW		 9091{
9092 if (dma_channel < 4) {
9093 outp(0x000B, (ushort)(0xC0 | dma_channel));
9094 outp(0x000A, dma_channel);
9095 } else if (dma_channel < 8) {
9096 outp(0x00D6, (ushort)(0xC0 | (dma_channel - 4)));
9097 outp(0x00D4, (ushort)(dma_channel - 4));
9098 }
51219358
MW		 9099}
9100#endif /* CONFIG_ISA */
9101
9102static int AscStopQueueExe(PortAddr iop_base)
9103{
9104 int count = 0;
9105
9106 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
9107 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
9108 ASC_STOP_REQ_RISC_STOP);
9109 do {
9110 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
9111 ASC_STOP_ACK_RISC_STOP) {
9112 return (1);
9113 }
9114 mdelay(100);
9115 } while (count++ < 20);
9116 }
9117 return (0);
9118}
9119
6f039790 9120static ASC_DCNT AscGetMaxDmaCount(ushort bus_type)
51219358
MW		 9121{
9122 if (bus_type & ASC_IS_ISA)
9123 return ASC_MAX_ISA_DMA_COUNT;
9124 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
9125 return ASC_MAX_VL_DMA_COUNT;
9126 return ASC_MAX_PCI_DMA_COUNT;
27c868c2 9127}
1da177e4 9128
51219358 9129#ifdef CONFIG_ISA
6f039790 9130static ushort AscGetIsaDmaChannel(PortAddr iop_base)
27c868c2 9131{
51219358 9132 ushort channel;
1da177e4 9133
51219358
MW		 9134 channel = AscGetChipCfgLsw(iop_base) & 0x0003;
9135 if (channel == 0x03)
9136 return (0);
9137 else if (channel == 0x00)
9138 return (7);
9139 return (channel + 4);
9140}
1da177e4 9141
6f039790 9142static ushort AscSetIsaDmaChannel(PortAddr iop_base, ushort dma_channel)
51219358
MW		 9143{
9144 ushort cfg_lsw;
9145 uchar value;
1da177e4 9146
51219358
MW		 9147 if ((dma_channel >= 5) && (dma_channel <= 7)) {
9148 if (dma_channel == 7)
9149 value = 0x00;
9150 else
9151 value = dma_channel - 4;
9152 cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
9153 cfg_lsw |= value;
9154 AscSetChipCfgLsw(iop_base, cfg_lsw);
9155 return (AscGetIsaDmaChannel(iop_base));
9156 }
9157 return 0;
9158}
1da177e4 9159
6f039790 9160static uchar AscGetIsaDmaSpeed(PortAddr iop_base)
51219358
MW		 9161{
9162 uchar speed_value;
1da177e4 9163
51219358
MW		 9164 AscSetBank(iop_base, 1);
9165 speed_value = AscReadChipDmaSpeed(iop_base);
9166 speed_value &= 0x07;
9167 AscSetBank(iop_base, 0);
9168 return speed_value;
9169}
1da177e4 9170
6f039790 9171static uchar AscSetIsaDmaSpeed(PortAddr iop_base, uchar speed_value)
51219358
MW		 9172{
9173 speed_value &= 0x07;
9174 AscSetBank(iop_base, 1);
9175 AscWriteChipDmaSpeed(iop_base, speed_value);
9176 AscSetBank(iop_base, 0);
9177 return AscGetIsaDmaSpeed(iop_base);
9178}
9179#endif /* CONFIG_ISA */
1da177e4 9180
6f039790 9181static ushort AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
51219358
MW		 9182{
9183 int i;
9184 PortAddr iop_base;
9185 ushort warn_code;
9186 uchar chip_version;
1da177e4 9187
51219358
MW		 9188 iop_base = asc_dvc->iop_base;
9189 warn_code = 0;
9190 asc_dvc->err_code = 0;
9191 if ((asc_dvc->bus_type &
9192 (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
9193 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
27c868c2 9194 }
51219358
MW		 9195 AscSetChipControl(iop_base, CC_HALT);
9196 AscSetChipStatus(iop_base, 0);
9197 asc_dvc->bug_fix_cntl = 0;
9198 asc_dvc->pci_fix_asyn_xfer = 0;
9199 asc_dvc->pci_fix_asyn_xfer_always = 0;
421f91d2 9200 /* asc_dvc->init_state initialized in AscInitGetConfig(). */
51219358
MW		 9201 asc_dvc->sdtr_done = 0;
9202 asc_dvc->cur_total_qng = 0;
9203 asc_dvc->is_in_int = 0;
9204 asc_dvc->in_critical_cnt = 0;
9205 asc_dvc->last_q_shortage = 0;
9206 asc_dvc->use_tagged_qng = 0;
9207 asc_dvc->no_scam = 0;
9208 asc_dvc->unit_not_ready = 0;
9209 asc_dvc->queue_full_or_busy = 0;
9210 asc_dvc->redo_scam = 0;
9211 asc_dvc->res2 = 0;
afbb68c3 9212 asc_dvc->min_sdtr_index = 0;
51219358
MW		 9213 asc_dvc->cfg->can_tagged_qng = 0;
9214 asc_dvc->cfg->cmd_qng_enabled = 0;
9215 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
9216 asc_dvc->init_sdtr = 0;
9217 asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
9218 asc_dvc->scsi_reset_wait = 3;
9219 asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
9220 asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
9221 asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
9222 asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
9223 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
51219358
MW		 9224 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
9225 asc_dvc->cfg->chip_version = chip_version;
afbb68c3 9226 asc_dvc->sdtr_period_tbl = asc_syn_xfer_period;
51219358
MW		 9227 asc_dvc->max_sdtr_index = 7;
9228 if ((asc_dvc->bus_type & ASC_IS_PCI) &&
9229 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
9230 asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
afbb68c3 9231 asc_dvc->sdtr_period_tbl = asc_syn_ultra_xfer_period;
51219358
MW		 9232 asc_dvc->max_sdtr_index = 15;
9233 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) {
9234 AscSetExtraControl(iop_base,
9235 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
9236 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
9237 AscSetExtraControl(iop_base,
9238 (SEC_ACTIVE_NEGATE |
9239 SEC_ENABLE_FILTER));
27c868c2
MW		 9240 }
9241 }
51219358
MW		 9242 if (asc_dvc->bus_type == ASC_IS_PCI) {
9243 AscSetExtraControl(iop_base,
9244 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
9245 }
1da177e4 9246
51219358
MW		 9247 asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
9248#ifdef CONFIG_ISA
9249 if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
9250 if (chip_version >= ASC_CHIP_MIN_VER_ISA_PNP) {
9251 AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
9252 asc_dvc->bus_type = ASC_IS_ISAPNP;
27c868c2 9253 }
51219358
MW		 9254 asc_dvc->cfg->isa_dma_channel =
9255 (uchar)AscGetIsaDmaChannel(iop_base);
27c868c2 9256 }
51219358
MW		 9257#endif /* CONFIG_ISA */
9258 for (i = 0; i <= ASC_MAX_TID; i++) {
9259 asc_dvc->cur_dvc_qng[i] = 0;
9260 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
9261 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L;
9262 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L;
9263 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
27c868c2 9264 }
51219358
MW		 9265 return warn_code;
9266}
1da177e4 9267
6f039790 9268static int AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg)
51219358
MW		 9269{
9270 int retry;
27c868c2 9271
51219358
MW		 9272 for (retry = 0; retry < ASC_EEP_MAX_RETRY; retry++) {
9273 unsigned char read_back;
9274 AscSetChipEEPCmd(iop_base, cmd_reg);
9275 mdelay(1);
9276 read_back = AscGetChipEEPCmd(iop_base);
9277 if (read_back == cmd_reg)
9278 return 1;
27c868c2 9279 }
51219358
MW		 9280 return 0;
9281}
1da177e4 9282
6f039790 9283static void AscWaitEEPRead(void)
51219358
MW		 9284{
9285 mdelay(1);
27c868c2 9286}
1da177e4 9287
6f039790 9288static ushort AscReadEEPWord(PortAddr iop_base, uchar addr)
27c868c2 9289{
51219358
MW		 9290 ushort read_wval;
9291 uchar cmd_reg;
27c868c2 9292
51219358
MW		 9293 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
9294 AscWaitEEPRead();
9295 cmd_reg = addr | ASC_EEP_CMD_READ;
9296 AscWriteEEPCmdReg(iop_base, cmd_reg);
9297 AscWaitEEPRead();
9298 read_wval = AscGetChipEEPData(iop_base);
9299 AscWaitEEPRead();
9300 return read_wval;
9301}
27c868c2 9302
6f039790
GKH		 9303static ushort AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9304 ushort bus_type)
51219358
MW		 9305{
9306 ushort wval;
9307 ushort sum;
9308 ushort *wbuf;
9309 int cfg_beg;
9310 int cfg_end;
9311 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
9312 int s_addr;
27c868c2 9313
51219358
MW		 9314 wbuf = (ushort *)cfg_buf;
9315 sum = 0;
9316 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
9317 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9318 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
9319 sum += *wbuf;
9320 }
9321 if (bus_type & ASC_IS_VL) {
9322 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9323 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9324 } else {
9325 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9326 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9327 }
9328 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9329 wval = AscReadEEPWord(iop_base, (uchar)s_addr);
9330 if (s_addr <= uchar_end_in_config) {
9331 /*
9332 * Swap all char fields - must unswap bytes already swapped
9333 * by AscReadEEPWord().
9334 */
9335 *wbuf = le16_to_cpu(wval);
9336 } else {
9337 /* Don't swap word field at the end - cntl field. */
9338 *wbuf = wval;
9339 }
9340 sum += wval; /* Checksum treats all EEPROM data as words. */
9341 }
27c868c2 9342 /*
51219358
MW		 9343 * Read the checksum word which will be compared against 'sum'
9344 * by the caller. Word field already swapped.
27c868c2 9345 */
51219358
MW		 9346 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
9347 return sum;
9348}
1da177e4 9349
6f039790 9350static int AscTestExternalLram(ASC_DVC_VAR *asc_dvc)
51219358
MW		 9351{
9352 PortAddr iop_base;
9353 ushort q_addr;
9354 ushort saved_word;
9355 int sta;
1da177e4 9356
51219358
MW		 9357 iop_base = asc_dvc->iop_base;
9358 sta = 0;
9359 q_addr = ASC_QNO_TO_QADDR(241);
9360 saved_word = AscReadLramWord(iop_base, q_addr);
9361 AscSetChipLramAddr(iop_base, q_addr);
9362 AscSetChipLramData(iop_base, 0x55AA);
9363 mdelay(10);
9364 AscSetChipLramAddr(iop_base, q_addr);
9365 if (AscGetChipLramData(iop_base) == 0x55AA) {
9366 sta = 1;
9367 AscWriteLramWord(iop_base, q_addr, saved_word);
9368 }
9369 return (sta);
9370}
1da177e4 9371
6f039790 9372static void AscWaitEEPWrite(void)
51219358
MW		 9373{
9374 mdelay(20);
51219358 9375}
1da177e4 9376
6f039790 9377static int AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg)
51219358
MW		 9378{
9379 ushort read_back;
9380 int retry;
1da177e4 9381
51219358
MW		 9382 retry = 0;
9383 while (TRUE) {
9384 AscSetChipEEPData(iop_base, data_reg);
9385 mdelay(1);
9386 read_back = AscGetChipEEPData(iop_base);
9387 if (read_back == data_reg) {
9388 return (1);
9389 }
9390 if (retry++ > ASC_EEP_MAX_RETRY) {
9391 return (0);
9392 }
27c868c2 9393 }
51219358 9394}
27c868c2 9395
6f039790 9396static ushort AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val)
51219358
MW		 9397{
9398 ushort read_wval;
9399
9400 read_wval = AscReadEEPWord(iop_base, addr);
9401 if (read_wval != word_val) {
9402 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
9403 AscWaitEEPRead();
9404 AscWriteEEPDataReg(iop_base, word_val);
9405 AscWaitEEPRead();
9406 AscWriteEEPCmdReg(iop_base,
9407 (uchar)((uchar)ASC_EEP_CMD_WRITE | addr));
9408 AscWaitEEPWrite();
9409 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
9410 AscWaitEEPRead();
9411 return (AscReadEEPWord(iop_base, addr));
9412 }
9413 return (read_wval);
9414}
9415
6f039790
GKH		 9416static int AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9417 ushort bus_type)
51219358
MW		 9418{
9419 int n_error;
9420 ushort *wbuf;
9421 ushort word;
9422 ushort sum;
9423 int s_addr;
9424 int cfg_beg;
9425 int cfg_end;
9426 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
9427
9428 wbuf = (ushort *)cfg_buf;
9429 n_error = 0;
9430 sum = 0;
9431 /* Write two config words; AscWriteEEPWord() will swap bytes. */
9432 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9433 sum += *wbuf;
9434 if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9435 n_error++;
27c868c2 9436 }
51219358
MW		 9437 }
9438 if (bus_type & ASC_IS_VL) {
9439 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9440 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9441 } else {
9442 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9443 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9444 }
9445 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9446 if (s_addr <= uchar_end_in_config) {
9447 /*
9448 * This is a char field. Swap char fields before they are
9449 * swapped again by AscWriteEEPWord().
9450 */
9451 word = cpu_to_le16(*wbuf);
9452 if (word !=
9453 AscWriteEEPWord(iop_base, (uchar)s_addr, word)) {
9454 n_error++;
9455 }
9456 } else {
9457 /* Don't swap word field at the end - cntl field. */
9458 if (*wbuf !=
9459 AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9460 n_error++;
9461 }
27c868c2 9462 }
51219358
MW		 9463 sum += *wbuf; /* Checksum calculated from word values. */
9464 }
9465 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
9466 *wbuf = sum;
9467 if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) {
9468 n_error++;
27c868c2 9469 }
1da177e4 9470
51219358
MW		 9471 /* Read EEPROM back again. */
9472 wbuf = (ushort *)cfg_buf;
27c868c2 9473 /*
51219358 9474 * Read two config words; Byte-swapping done by AscReadEEPWord().
27c868c2 9475 */
51219358
MW		 9476 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9477 if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) {
9478 n_error++;
27c868c2
MW		 9479 }
9480 }
51219358
MW		 9481 if (bus_type & ASC_IS_VL) {
9482 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9483 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9484 } else {
9485 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9486 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9487 }
9488 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9489 if (s_addr <= uchar_end_in_config) {
9490 /*
9491 * Swap all char fields. Must unswap bytes already swapped
9492 * by AscReadEEPWord().
9493 */
9494 word =
9495 le16_to_cpu(AscReadEEPWord
9496 (iop_base, (uchar)s_addr));
27c868c2 9497 } else {
51219358
MW		 9498 /* Don't swap word field at the end - cntl field. */
9499 word = AscReadEEPWord(iop_base, (uchar)s_addr);
9500 }
9501 if (*wbuf != word) {
9502 n_error++;
27c868c2
MW		 9503 }
9504 }
51219358
MW		 9505 /* Read checksum; Byte swapping not needed. */
9506 if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) {
9507 n_error++;
27c868c2 9508 }
51219358
MW		 9509 return n_error;
9510}
1da177e4 9511
6f039790
GKH		 9512static int AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9513 ushort bus_type)
51219358
MW		 9514{
9515 int retry;
9516 int n_error;
27c868c2 9517
51219358
MW		 9518 retry = 0;
9519 while (TRUE) {
9520 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
9521 bus_type)) == 0) {
9522 break;
9523 }
9524 if (++retry > ASC_EEP_MAX_RETRY) {
9525 break;
9526 }
9527 }
9528 return n_error;
9529}
27c868c2 9530
6f039790 9531static ushort AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
51219358
MW		 9532{
9533 ASCEEP_CONFIG eep_config_buf;
9534 ASCEEP_CONFIG *eep_config;
9535 PortAddr iop_base;
9536 ushort chksum;
9537 ushort warn_code;
9538 ushort cfg_msw, cfg_lsw;
9539 int i;
9540 int write_eep = 0;
27c868c2 9541
51219358
MW		 9542 iop_base = asc_dvc->iop_base;
9543 warn_code = 0;
9544 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
9545 AscStopQueueExe(iop_base);
9546 if ((AscStopChip(iop_base) == FALSE) ||
9547 (AscGetChipScsiCtrl(iop_base) != 0)) {
9548 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
9549 AscResetChipAndScsiBus(asc_dvc);
9550 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
9551 }
9552 if (AscIsChipHalted(iop_base) == FALSE) {
9553 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
9554 return (warn_code);
9555 }
9556 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
9557 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
9558 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
9559 return (warn_code);
9560 }
9561 eep_config = (ASCEEP_CONFIG *)&eep_config_buf;
9562 cfg_msw = AscGetChipCfgMsw(iop_base);
9563 cfg_lsw = AscGetChipCfgLsw(iop_base);
9564 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
9565 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9566 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
9567 AscSetChipCfgMsw(iop_base, cfg_msw);
9568 }
9569 chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
b352f923 9570 ASC_DBG(1, "chksum 0x%x\n", chksum);
51219358
MW		 9571 if (chksum == 0) {
9572 chksum = 0xaa55;
9573 }
9574 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
9575 warn_code |= ASC_WARN_AUTO_CONFIG;
9576 if (asc_dvc->cfg->chip_version == 3) {
9577 if (eep_config->cfg_lsw != cfg_lsw) {
9578 warn_code |= ASC_WARN_EEPROM_RECOVER;
9579 eep_config->cfg_lsw =
9580 AscGetChipCfgLsw(iop_base);
9581 }
9582 if (eep_config->cfg_msw != cfg_msw) {
9583 warn_code |= ASC_WARN_EEPROM_RECOVER;
9584 eep_config->cfg_msw =
9585 AscGetChipCfgMsw(iop_base);
9586 }
9587 }
9588 }
9589 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9590 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
b352f923 9591 ASC_DBG(1, "eep_config->chksum 0x%x\n", eep_config->chksum);
51219358
MW		 9592 if (chksum != eep_config->chksum) {
9593 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
9594 ASC_CHIP_VER_PCI_ULTRA_3050) {
b352f923 9595 ASC_DBG(1, "chksum error ignored; EEPROM-less board\n");
51219358
MW		 9596 eep_config->init_sdtr = 0xFF;
9597 eep_config->disc_enable = 0xFF;
9598 eep_config->start_motor = 0xFF;
9599 eep_config->use_cmd_qng = 0;
9600 eep_config->max_total_qng = 0xF0;
9601 eep_config->max_tag_qng = 0x20;
9602 eep_config->cntl = 0xBFFF;
9603 ASC_EEP_SET_CHIP_ID(eep_config, 7);
9604 eep_config->no_scam = 0;
9605 eep_config->adapter_info[0] = 0;
9606 eep_config->adapter_info[1] = 0;
9607 eep_config->adapter_info[2] = 0;
9608 eep_config->adapter_info[3] = 0;
9609 eep_config->adapter_info[4] = 0;
9610 /* Indicate EEPROM-less board. */
9611 eep_config->adapter_info[5] = 0xBB;
27c868c2 9612 } else {
51219358
MW		 9613 ASC_PRINT
9614 ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
9615 write_eep = 1;
9616 warn_code |= ASC_WARN_EEPROM_CHKSUM;
9617 }
9618 }
9619 asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
9620 asc_dvc->cfg->disc_enable = eep_config->disc_enable;
9621 asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
9622 asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
9623 asc_dvc->start_motor = eep_config->start_motor;
9624 asc_dvc->dvc_cntl = eep_config->cntl;
9625 asc_dvc->no_scam = eep_config->no_scam;
9626 asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
9627 asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
9628 asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
9629 asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
9630 asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
9631 asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
9632 if (!AscTestExternalLram(asc_dvc)) {
9633 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) ==
9634 ASC_IS_PCI_ULTRA)) {
9635 eep_config->max_total_qng =
9636 ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
9637 eep_config->max_tag_qng =
9638 ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
9639 } else {
9640 eep_config->cfg_msw |= 0x0800;
9641 cfg_msw |= 0x0800;
9642 AscSetChipCfgMsw(iop_base, cfg_msw);
9643 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
9644 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
27c868c2 9645 }
51219358
MW		 9646 } else {
9647 }
9648 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
9649 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
9650 }
9651 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
9652 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
9653 }
9654 if (eep_config->max_tag_qng > eep_config->max_total_qng) {
9655 eep_config->max_tag_qng = eep_config->max_total_qng;
9656 }
9657 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
9658 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
9659 }
9660 asc_dvc->max_total_qng = eep_config->max_total_qng;
9661 if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
9662 eep_config->use_cmd_qng) {
9663 eep_config->disc_enable = eep_config->use_cmd_qng;
9664 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
9665 }
51219358
MW		 9666 ASC_EEP_SET_CHIP_ID(eep_config,
9667 ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
9668 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
9669 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
9670 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
afbb68c3 9671 asc_dvc->min_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
27c868c2 9672 }
1da177e4 9673
51219358
MW		 9674 for (i = 0; i <= ASC_MAX_TID; i++) {
9675 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
9676 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
9677 asc_dvc->cfg->sdtr_period_offset[i] =
9678 (uchar)(ASC_DEF_SDTR_OFFSET |
afbb68c3 9679 (asc_dvc->min_sdtr_index << 4));
51219358
MW		 9680 }
9681 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
9682 if (write_eep) {
9683 if ((i = AscSetEEPConfig(iop_base, eep_config,
9684 asc_dvc->bus_type)) != 0) {
9685 ASC_PRINT1
9686 ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n",
9687 i);
27c868c2 9688 } else {
51219358
MW		 9689 ASC_PRINT
9690 ("AscInitFromEEP: Successfully re-wrote EEPROM.\n");
27c868c2
MW		 9691 }
9692 }
51219358 9693 return (warn_code);
1da177e4
LT		 9694}
9695
6f039790 9696static int AscInitGetConfig(struct Scsi_Host *shost)
1da177e4 9697{
9d0e96eb
MW		 9698 struct asc_board *board = shost_priv(shost);
9699 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
51219358 9700 unsigned short warn_code = 0;
27c868c2 9701
51219358
MW		 9702 asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
9703 if (asc_dvc->err_code != 0)
9704 return asc_dvc->err_code;
27c868c2 9705
51219358
MW		 9706 if (AscFindSignature(asc_dvc->iop_base)) {
9707 warn_code |= AscInitAscDvcVar(asc_dvc);
9708 warn_code |= AscInitFromEEP(asc_dvc);
9709 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
9710 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
9711 asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
9712 } else {
9713 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
9714 }
27c868c2 9715
51219358
MW		 9716 switch (warn_code) {
9717 case 0: /* No error */
9718 break;
9719 case ASC_WARN_IO_PORT_ROTATE:
9d0e96eb
MW		 9720 shost_printk(KERN_WARNING, shost, "I/O port address "
9721 "modified\n");
51219358
MW		 9722 break;
9723 case ASC_WARN_AUTO_CONFIG:
9d0e96eb
MW		 9724 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
9725 "enabled\n");
51219358
MW		 9726 break;
9727 case ASC_WARN_EEPROM_CHKSUM:
9d0e96eb 9728 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
51219358
MW		 9729 break;
9730 case ASC_WARN_IRQ_MODIFIED:
9d0e96eb 9731 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
51219358
MW		 9732 break;
9733 case ASC_WARN_CMD_QNG_CONFLICT:
9d0e96eb
MW		 9734 shost_printk(KERN_WARNING, shost, "tag queuing enabled w/o "
9735 "disconnects\n");
51219358
MW		 9736 break;
9737 default:
9d0e96eb
MW		 9738 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
9739 warn_code);
51219358
MW		 9740 break;
9741 }
1da177e4 9742
9d0e96eb
MW		 9743 if (asc_dvc->err_code != 0)
9744 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
9745 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
27c868c2 9746
51219358
MW		 9747 return asc_dvc->err_code;
9748}
1da177e4 9749
6f039790 9750static int AscInitSetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
51219358 9751{
9d0e96eb
MW		 9752 struct asc_board *board = shost_priv(shost);
9753 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
51219358
MW		 9754 PortAddr iop_base = asc_dvc->iop_base;
9755 unsigned short cfg_msw;
9756 unsigned short warn_code = 0;
1da177e4 9757
51219358
MW		 9758 asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
9759 if (asc_dvc->err_code != 0)
9760 return asc_dvc->err_code;
9761 if (!AscFindSignature(asc_dvc->iop_base)) {
9762 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
9763 return asc_dvc->err_code;
27c868c2 9764 }
1da177e4 9765
51219358
MW		 9766 cfg_msw = AscGetChipCfgMsw(iop_base);
9767 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
9768 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9769 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
9770 AscSetChipCfgMsw(iop_base, cfg_msw);
9771 }
9772 if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
9773 asc_dvc->cfg->cmd_qng_enabled) {
9774 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
9775 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
9776 }
9777 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
9778 warn_code |= ASC_WARN_AUTO_CONFIG;
9779 }
51219358
MW		 9780#ifdef CONFIG_PCI
9781 if (asc_dvc->bus_type & ASC_IS_PCI) {
9782 cfg_msw &= 0xFFC0;
9783 AscSetChipCfgMsw(iop_base, cfg_msw);
9784 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
27c868c2 9785 } else {
51219358
MW		 9786 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
9787 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
9788 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
9789 asc_dvc->bug_fix_cntl |=
9790 ASC_BUG_FIX_ASYN_USE_SYN;
9791 }
27c868c2 9792 }
51219358
MW		 9793 } else
9794#endif /* CONFIG_PCI */
9795 if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
9796 if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
9797 == ASC_CHIP_VER_ASYN_BUG) {
9798 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
27c868c2
MW		 9799 }
9800 }
51219358
MW		 9801 if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
9802 asc_dvc->cfg->chip_scsi_id) {
9803 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
9804 }
9805#ifdef CONFIG_ISA
9806 if (asc_dvc->bus_type & ASC_IS_ISA) {
9807 AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
9808 AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
9809 }
9810#endif /* CONFIG_ISA */
1da177e4 9811
51219358
MW		 9812 asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
9813
9814 switch (warn_code) {
9815 case 0: /* No error. */
9816 break;
9817 case ASC_WARN_IO_PORT_ROTATE:
9d0e96eb
MW		 9818 shost_printk(KERN_WARNING, shost, "I/O port address "
9819 "modified\n");
51219358
MW		 9820 break;
9821 case ASC_WARN_AUTO_CONFIG:
9d0e96eb
MW		 9822 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
9823 "enabled\n");
51219358
MW		 9824 break;
9825 case ASC_WARN_EEPROM_CHKSUM:
9d0e96eb 9826 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
51219358
MW		 9827 break;
9828 case ASC_WARN_IRQ_MODIFIED:
9d0e96eb 9829 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
51219358
MW		 9830 break;
9831 case ASC_WARN_CMD_QNG_CONFLICT:
9d0e96eb
MW		 9832 shost_printk(KERN_WARNING, shost, "tag queuing w/o "
9833 "disconnects\n");
51219358
MW		 9834 break;
9835 default:
9d0e96eb
MW		 9836 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
9837 warn_code);
51219358 9838 break;
27c868c2 9839 }
1da177e4 9840
9d0e96eb
MW		 9841 if (asc_dvc->err_code != 0)
9842 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
9843 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
27c868c2 9844
51219358
MW		 9845 return asc_dvc->err_code;
9846}
27c868c2 9847
51219358
MW		 9848/*
9849 * EEPROM Configuration.
9850 *
9851 * All drivers should use this structure to set the default EEPROM
9852 * configuration. The BIOS now uses this structure when it is built.
9853 * Additional structure information can be found in a_condor.h where
9854 * the structure is defined.
9855 *
9856 * The *_Field_IsChar structs are needed to correct for endianness.
9857 * These values are read from the board 16 bits at a time directly
9858 * into the structs. Because some fields are char, the values will be
9859 * in the wrong order. The *_Field_IsChar tells when to flip the
9860 * bytes. Data read and written to PCI memory is automatically swapped
9861 * on big-endian platforms so char fields read as words are actually being
9862 * unswapped on big-endian platforms.
9863 */
6f039790 9864static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config = {
51219358
MW		 9865 ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
9866 0x0000, /* cfg_msw */
9867 0xFFFF, /* disc_enable */
9868 0xFFFF, /* wdtr_able */
9869 0xFFFF, /* sdtr_able */
9870 0xFFFF, /* start_motor */
9871 0xFFFF, /* tagqng_able */
9872 0xFFFF, /* bios_scan */
9873 0, /* scam_tolerant */
9874 7, /* adapter_scsi_id */
9875 0, /* bios_boot_delay */
9876 3, /* scsi_reset_delay */
9877 0, /* bios_id_lun */
9878 0, /* termination */
9879 0, /* reserved1 */
9880 0xFFE7, /* bios_ctrl */
9881 0xFFFF, /* ultra_able */
9882 0, /* reserved2 */
9883 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */
9884 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9885 0, /* dvc_cntl */
9886 0, /* bug_fix */
9887 0, /* serial_number_word1 */
9888 0, /* serial_number_word2 */
9889 0, /* serial_number_word3 */
9890 0, /* check_sum */
9891 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9892 , /* oem_name[16] */
9893 0, /* dvc_err_code */
9894 0, /* adv_err_code */
9895 0, /* adv_err_addr */
9896 0, /* saved_dvc_err_code */
9897 0, /* saved_adv_err_code */
9898 0, /* saved_adv_err_addr */
9899 0 /* num_of_err */
9900};
27c868c2 9901
6f039790 9902static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar = {
51219358
MW		 9903 0, /* cfg_lsw */
9904 0, /* cfg_msw */
9905 0, /* -disc_enable */
9906 0, /* wdtr_able */
9907 0, /* sdtr_able */
9908 0, /* start_motor */
9909 0, /* tagqng_able */
9910 0, /* bios_scan */
9911 0, /* scam_tolerant */
9912 1, /* adapter_scsi_id */
9913 1, /* bios_boot_delay */
9914 1, /* scsi_reset_delay */
9915 1, /* bios_id_lun */
9916 1, /* termination */
9917 1, /* reserved1 */
9918 0, /* bios_ctrl */
9919 0, /* ultra_able */
9920 0, /* reserved2 */
9921 1, /* max_host_qng */
9922 1, /* max_dvc_qng */
9923 0, /* dvc_cntl */
9924 0, /* bug_fix */
9925 0, /* serial_number_word1 */
9926 0, /* serial_number_word2 */
9927 0, /* serial_number_word3 */
9928 0, /* check_sum */
9929 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
9930 , /* oem_name[16] */
9931 0, /* dvc_err_code */
9932 0, /* adv_err_code */
9933 0, /* adv_err_addr */
9934 0, /* saved_dvc_err_code */
9935 0, /* saved_adv_err_code */
9936 0, /* saved_adv_err_addr */
9937 0 /* num_of_err */
9938};
1da177e4 9939
6f039790 9940static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config = {
51219358
MW		 9941 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
9942 0x0000, /* 01 cfg_msw */
9943 0xFFFF, /* 02 disc_enable */
9944 0xFFFF, /* 03 wdtr_able */
9945 0x4444, /* 04 sdtr_speed1 */
9946 0xFFFF, /* 05 start_motor */
9947 0xFFFF, /* 06 tagqng_able */
9948 0xFFFF, /* 07 bios_scan */
9949 0, /* 08 scam_tolerant */
9950 7, /* 09 adapter_scsi_id */
9951 0, /* bios_boot_delay */
9952 3, /* 10 scsi_reset_delay */
9953 0, /* bios_id_lun */
9954 0, /* 11 termination_se */
9955 0, /* termination_lvd */
9956 0xFFE7, /* 12 bios_ctrl */
9957 0x4444, /* 13 sdtr_speed2 */
9958 0x4444, /* 14 sdtr_speed3 */
9959 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
9960 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9961 0, /* 16 dvc_cntl */
9962 0x4444, /* 17 sdtr_speed4 */
9963 0, /* 18 serial_number_word1 */
9964 0, /* 19 serial_number_word2 */
9965 0, /* 20 serial_number_word3 */
9966 0, /* 21 check_sum */
9967 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9968 , /* 22-29 oem_name[16] */
9969 0, /* 30 dvc_err_code */
9970 0, /* 31 adv_err_code */
9971 0, /* 32 adv_err_addr */
9972 0, /* 33 saved_dvc_err_code */
9973 0, /* 34 saved_adv_err_code */
9974 0, /* 35 saved_adv_err_addr */
9975 0, /* 36 reserved */
9976 0, /* 37 reserved */
9977 0, /* 38 reserved */
9978 0, /* 39 reserved */
9979 0, /* 40 reserved */
9980 0, /* 41 reserved */
9981 0, /* 42 reserved */
9982 0, /* 43 reserved */
9983 0, /* 44 reserved */
9984 0, /* 45 reserved */
9985 0, /* 46 reserved */
9986 0, /* 47 reserved */
9987 0, /* 48 reserved */
9988 0, /* 49 reserved */
9989 0, /* 50 reserved */
9990 0, /* 51 reserved */
9991 0, /* 52 reserved */
9992 0, /* 53 reserved */
9993 0, /* 54 reserved */
9994 0, /* 55 reserved */
9995 0, /* 56 cisptr_lsw */
9996 0, /* 57 cisprt_msw */
9997 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
9998 PCI_DEVICE_ID_38C0800_REV1, /* 59 subsysid */
9999 0, /* 60 reserved */
10000 0, /* 61 reserved */
10001 0, /* 62 reserved */
10002 0 /* 63 reserved */
10003};
27c868c2 10004
6f039790 10005static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar = {
51219358
MW		 10006 0, /* 00 cfg_lsw */
10007 0, /* 01 cfg_msw */
10008 0, /* 02 disc_enable */
10009 0, /* 03 wdtr_able */
10010 0, /* 04 sdtr_speed1 */
10011 0, /* 05 start_motor */
10012 0, /* 06 tagqng_able */
10013 0, /* 07 bios_scan */
10014 0, /* 08 scam_tolerant */
10015 1, /* 09 adapter_scsi_id */
10016 1, /* bios_boot_delay */
10017 1, /* 10 scsi_reset_delay */
10018 1, /* bios_id_lun */
10019 1, /* 11 termination_se */
10020 1, /* termination_lvd */
10021 0, /* 12 bios_ctrl */
10022 0, /* 13 sdtr_speed2 */
10023 0, /* 14 sdtr_speed3 */
10024 1, /* 15 max_host_qng */
10025 1, /* max_dvc_qng */
10026 0, /* 16 dvc_cntl */
10027 0, /* 17 sdtr_speed4 */
10028 0, /* 18 serial_number_word1 */
10029 0, /* 19 serial_number_word2 */
10030 0, /* 20 serial_number_word3 */
10031 0, /* 21 check_sum */
10032 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
10033 , /* 22-29 oem_name[16] */
10034 0, /* 30 dvc_err_code */
10035 0, /* 31 adv_err_code */
10036 0, /* 32 adv_err_addr */
10037 0, /* 33 saved_dvc_err_code */
10038 0, /* 34 saved_adv_err_code */
10039 0, /* 35 saved_adv_err_addr */
10040 0, /* 36 reserved */
10041 0, /* 37 reserved */
10042 0, /* 38 reserved */
10043 0, /* 39 reserved */
10044 0, /* 40 reserved */
10045 0, /* 41 reserved */
10046 0, /* 42 reserved */
10047 0, /* 43 reserved */
10048 0, /* 44 reserved */
10049 0, /* 45 reserved */
10050 0, /* 46 reserved */
10051 0, /* 47 reserved */
10052 0, /* 48 reserved */
10053 0, /* 49 reserved */
10054 0, /* 50 reserved */
10055 0, /* 51 reserved */
10056 0, /* 52 reserved */
10057 0, /* 53 reserved */
10058 0, /* 54 reserved */
10059 0, /* 55 reserved */
10060 0, /* 56 cisptr_lsw */
10061 0, /* 57 cisprt_msw */
10062 0, /* 58 subsysvid */
10063 0, /* 59 subsysid */
10064 0, /* 60 reserved */
10065 0, /* 61 reserved */
10066 0, /* 62 reserved */
10067 0 /* 63 reserved */
10068};
27c868c2 10069
6f039790 10070static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config = {
51219358
MW		 10071 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
10072 0x0000, /* 01 cfg_msw */
10073 0xFFFF, /* 02 disc_enable */
10074 0xFFFF, /* 03 wdtr_able */
10075 0x5555, /* 04 sdtr_speed1 */
10076 0xFFFF, /* 05 start_motor */
10077 0xFFFF, /* 06 tagqng_able */
10078 0xFFFF, /* 07 bios_scan */
10079 0, /* 08 scam_tolerant */
10080 7, /* 09 adapter_scsi_id */
10081 0, /* bios_boot_delay */
10082 3, /* 10 scsi_reset_delay */
10083 0, /* bios_id_lun */
10084 0, /* 11 termination_se */
10085 0, /* termination_lvd */
10086 0xFFE7, /* 12 bios_ctrl */
10087 0x5555, /* 13 sdtr_speed2 */
10088 0x5555, /* 14 sdtr_speed3 */
10089 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
10090 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
10091 0, /* 16 dvc_cntl */
10092 0x5555, /* 17 sdtr_speed4 */
10093 0, /* 18 serial_number_word1 */
10094 0, /* 19 serial_number_word2 */
10095 0, /* 20 serial_number_word3 */
10096 0, /* 21 check_sum */
10097 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
10098 , /* 22-29 oem_name[16] */
10099 0, /* 30 dvc_err_code */
10100 0, /* 31 adv_err_code */
10101 0, /* 32 adv_err_addr */
10102 0, /* 33 saved_dvc_err_code */
10103 0, /* 34 saved_adv_err_code */
10104 0, /* 35 saved_adv_err_addr */
10105 0, /* 36 reserved */
10106 0, /* 37 reserved */
10107 0, /* 38 reserved */
10108 0, /* 39 reserved */
10109 0, /* 40 reserved */
10110 0, /* 41 reserved */
10111 0, /* 42 reserved */
10112 0, /* 43 reserved */
10113 0, /* 44 reserved */
10114 0, /* 45 reserved */
10115 0, /* 46 reserved */
10116 0, /* 47 reserved */
10117 0, /* 48 reserved */
10118 0, /* 49 reserved */
10119 0, /* 50 reserved */
10120 0, /* 51 reserved */
10121 0, /* 52 reserved */
10122 0, /* 53 reserved */
10123 0, /* 54 reserved */
10124 0, /* 55 reserved */
10125 0, /* 56 cisptr_lsw */
10126 0, /* 57 cisprt_msw */
10127 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
10128 PCI_DEVICE_ID_38C1600_REV1, /* 59 subsysid */
10129 0, /* 60 reserved */
10130 0, /* 61 reserved */
10131 0, /* 62 reserved */
10132 0 /* 63 reserved */
10133};
1da177e4 10134
6f039790 10135static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar = {
51219358
MW		 10136 0, /* 00 cfg_lsw */
10137 0, /* 01 cfg_msw */
10138 0, /* 02 disc_enable */
10139 0, /* 03 wdtr_able */
10140 0, /* 04 sdtr_speed1 */
10141 0, /* 05 start_motor */
10142 0, /* 06 tagqng_able */
10143 0, /* 07 bios_scan */
10144 0, /* 08 scam_tolerant */
10145 1, /* 09 adapter_scsi_id */
10146 1, /* bios_boot_delay */
10147 1, /* 10 scsi_reset_delay */
10148 1, /* bios_id_lun */
10149 1, /* 11 termination_se */
10150 1, /* termination_lvd */
10151 0, /* 12 bios_ctrl */
10152 0, /* 13 sdtr_speed2 */
10153 0, /* 14 sdtr_speed3 */
10154 1, /* 15 max_host_qng */
10155 1, /* max_dvc_qng */
10156 0, /* 16 dvc_cntl */
10157 0, /* 17 sdtr_speed4 */
10158 0, /* 18 serial_number_word1 */
10159 0, /* 19 serial_number_word2 */
10160 0, /* 20 serial_number_word3 */
10161 0, /* 21 check_sum */
10162 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
10163 , /* 22-29 oem_name[16] */
10164 0, /* 30 dvc_err_code */
10165 0, /* 31 adv_err_code */
10166 0, /* 32 adv_err_addr */
10167 0, /* 33 saved_dvc_err_code */
10168 0, /* 34 saved_adv_err_code */
10169 0, /* 35 saved_adv_err_addr */
10170 0, /* 36 reserved */
10171 0, /* 37 reserved */
10172 0, /* 38 reserved */
10173 0, /* 39 reserved */
10174 0, /* 40 reserved */
10175 0, /* 41 reserved */
10176 0, /* 42 reserved */
10177 0, /* 43 reserved */
10178 0, /* 44 reserved */
10179 0, /* 45 reserved */
10180 0, /* 46 reserved */
10181 0, /* 47 reserved */
10182 0, /* 48 reserved */
10183 0, /* 49 reserved */
10184 0, /* 50 reserved */
10185 0, /* 51 reserved */
10186 0, /* 52 reserved */
10187 0, /* 53 reserved */
10188 0, /* 54 reserved */
10189 0, /* 55 reserved */
10190 0, /* 56 cisptr_lsw */
10191 0, /* 57 cisprt_msw */
10192 0, /* 58 subsysvid */
10193 0, /* 59 subsysid */
10194 0, /* 60 reserved */
10195 0, /* 61 reserved */
10196 0, /* 62 reserved */
10197 0 /* 63 reserved */
10198};
1da177e4 10199
51219358 10200#ifdef CONFIG_PCI
1da177e4 10201/*
51219358 10202 * Wait for EEPROM command to complete
1da177e4 10203 */
6f039790 10204static void AdvWaitEEPCmd(AdvPortAddr iop_base)
1da177e4 10205{
51219358 10206 int eep_delay_ms;
27c868c2 10207
51219358
MW		 10208 for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) {
10209 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) &
10210 ASC_EEP_CMD_DONE) {
10211 break;
27c868c2 10212 }
51219358 10213 mdelay(1);
27c868c2 10214 }
51219358
MW		 10215 if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) ==
10216 0)
10217 BUG();
1da177e4
LT		 10218}
10219
10220/*
51219358 10221 * Read the EEPROM from specified location
1da177e4 10222 */
6f039790 10223static ushort AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
51219358
MW		 10224{
10225 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10226 ASC_EEP_CMD_READ | eep_word_addr);
10227 AdvWaitEEPCmd(iop_base);
10228 return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
10229}
10230
10231/*
10232 * Write the EEPROM from 'cfg_buf'.
10233 */
6f039790
GKH		 10234static void AdvSet3550EEPConfig(AdvPortAddr iop_base,
10235 ADVEEP_3550_CONFIG *cfg_buf)
1da177e4 10236{
27c868c2 10237 ushort *wbuf;
51219358 10238 ushort addr, chksum;
27c868c2
MW		 10239 ushort *charfields;
10240
27c868c2 10241 wbuf = (ushort *)cfg_buf;
51219358 10242 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
27c868c2
MW		 10243 chksum = 0;
10244
51219358
MW		 10245 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10246 AdvWaitEEPCmd(iop_base);
10247
10248 /*
10249 * Write EEPROM from word 0 to word 20.
10250 */
10251 for (addr = ADV_EEP_DVC_CFG_BEGIN;
10252 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10253 ushort word;
10254
27c868c2 10255 if (*charfields++) {
51219358 10256 word = cpu_to_le16(*wbuf);
27c868c2 10257 } else {
51219358 10258 word = *wbuf;
27c868c2 10259 }
51219358
MW		 10260 chksum += *wbuf; /* Checksum is calculated from word values. */
10261 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10262 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10263 ASC_EEP_CMD_WRITE | addr);
10264 AdvWaitEEPCmd(iop_base);
10265 mdelay(ADV_EEP_DELAY_MS);
27c868c2 10266 }
51219358
MW		 10267
10268 /*
10269 * Write EEPROM checksum at word 21.
10270 */
10271 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10272 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10273 AdvWaitEEPCmd(iop_base);
27c868c2
MW		 10274 wbuf++;
10275 charfields++;
10276
51219358
MW		 10277 /*
10278 * Write EEPROM OEM name at words 22 to 29.
10279 */
10280 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10281 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10282 ushort word;
10283
27c868c2 10284 if (*charfields++) {
51219358
MW		 10285 word = cpu_to_le16(*wbuf);
10286 } else {
10287 word = *wbuf;
27c868c2 10288 }
51219358
MW		 10289 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10290 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10291 ASC_EEP_CMD_WRITE | addr);
10292 AdvWaitEEPCmd(iop_base);
27c868c2 10293 }
51219358
MW		 10294 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10295 AdvWaitEEPCmd(iop_base);
1da177e4
LT		 10296}
10297
10298/*
51219358 10299 * Write the EEPROM from 'cfg_buf'.
1da177e4 10300 */
6f039790
GKH		 10301static void AdvSet38C0800EEPConfig(AdvPortAddr iop_base,
10302 ADVEEP_38C0800_CONFIG *cfg_buf)
1da177e4 10303{
27c868c2 10304 ushort *wbuf;
27c868c2 10305 ushort *charfields;
51219358 10306 ushort addr, chksum;
27c868c2 10307
27c868c2 10308 wbuf = (ushort *)cfg_buf;
51219358 10309 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
27c868c2
MW		 10310 chksum = 0;
10311
51219358
MW		 10312 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10313 AdvWaitEEPCmd(iop_base);
10314
10315 /*
10316 * Write EEPROM from word 0 to word 20.
10317 */
10318 for (addr = ADV_EEP_DVC_CFG_BEGIN;
10319 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10320 ushort word;
10321
27c868c2 10322 if (*charfields++) {
51219358 10323 word = cpu_to_le16(*wbuf);
27c868c2 10324 } else {
51219358 10325 word = *wbuf;
27c868c2 10326 }
51219358
MW		 10327 chksum += *wbuf; /* Checksum is calculated from word values. */
10328 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10329 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10330 ASC_EEP_CMD_WRITE | addr);
10331 AdvWaitEEPCmd(iop_base);
10332 mdelay(ADV_EEP_DELAY_MS);
27c868c2 10333 }
51219358
MW		 10334
10335 /*
10336 * Write EEPROM checksum at word 21.
10337 */
10338 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10339 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10340 AdvWaitEEPCmd(iop_base);
27c868c2
MW		 10341 wbuf++;
10342 charfields++;
10343
51219358
MW		 10344 /*
10345 * Write EEPROM OEM name at words 22 to 29.
10346 */
10347 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10348 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10349 ushort word;
10350
27c868c2 10351 if (*charfields++) {
51219358
MW		 10352 word = cpu_to_le16(*wbuf);
10353 } else {
10354 word = *wbuf;
27c868c2 10355 }
51219358
MW		 10356 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10357 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10358 ASC_EEP_CMD_WRITE | addr);
10359 AdvWaitEEPCmd(iop_base);
27c868c2 10360 }
51219358 10361 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
27c868c2 10362 AdvWaitEEPCmd(iop_base);
1da177e4
LT		 10363}
10364
10365/*
10366 * Write the EEPROM from 'cfg_buf'.
10367 */
6f039790
GKH		 10368static void AdvSet38C1600EEPConfig(AdvPortAddr iop_base,
10369 ADVEEP_38C1600_CONFIG *cfg_buf)
1da177e4 10370{
27c868c2 10371 ushort *wbuf;
27c868c2 10372 ushort *charfields;
51219358 10373 ushort addr, chksum;
27c868c2
MW		 10374
10375 wbuf = (ushort *)cfg_buf;
51219358 10376 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
27c868c2
MW		 10377 chksum = 0;
10378
10379 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10380 AdvWaitEEPCmd(iop_base);
10381
10382 /*
10383 * Write EEPROM from word 0 to word 20.
10384 */
10385 for (addr = ADV_EEP_DVC_CFG_BEGIN;
10386 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10387 ushort word;
10388
10389 if (*charfields++) {
10390 word = cpu_to_le16(*wbuf);
10391 } else {
10392 word = *wbuf;
10393 }
10394 chksum += *wbuf; /* Checksum is calculated from word values. */
10395 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10396 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10397 ASC_EEP_CMD_WRITE | addr);
10398 AdvWaitEEPCmd(iop_base);
b009bef6 10399 mdelay(ADV_EEP_DELAY_MS);
27c868c2 10400 }
1da177e4 10401
27c868c2
MW		 10402 /*
10403 * Write EEPROM checksum at word 21.
10404 */
10405 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10406 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10407 AdvWaitEEPCmd(iop_base);
10408 wbuf++;
10409 charfields++;
10410
10411 /*
10412 * Write EEPROM OEM name at words 22 to 29.
10413 */
10414 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10415 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10416 ushort word;
10417
10418 if (*charfields++) {
10419 word = cpu_to_le16(*wbuf);
10420 } else {
10421 word = *wbuf;
10422 }
10423 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10424 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10425 ASC_EEP_CMD_WRITE | addr);
10426 AdvWaitEEPCmd(iop_base);
10427 }
10428 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10429 AdvWaitEEPCmd(iop_base);
1da177e4
LT		 10430}
10431
10432/*
51219358
MW		 10433 * Read EEPROM configuration into the specified buffer.
10434 *
10435 * Return a checksum based on the EEPROM configuration read.
1da177e4 10436 */
6f039790
GKH		 10437static ushort AdvGet3550EEPConfig(AdvPortAddr iop_base,
10438 ADVEEP_3550_CONFIG *cfg_buf)
1da177e4 10439{
51219358 10440 ushort wval, chksum;
27c868c2 10441 ushort *wbuf;
51219358 10442 int eep_addr;
27c868c2 10443 ushort *charfields;
27c868c2 10444
51219358 10445 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
27c868c2 10446 wbuf = (ushort *)cfg_buf;
27c868c2
MW		 10447 chksum = 0;
10448
51219358
MW		 10449 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10450 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10451 wval = AdvReadEEPWord(iop_base, eep_addr);
10452 chksum += wval; /* Checksum is calculated from word values. */
10453 if (*charfields++) {
10454 *wbuf = le16_to_cpu(wval);
10455 } else {
10456 *wbuf = wval;
10457 }
10458 }
10459 /* Read checksum word. */
10460 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10461 wbuf++;
10462 charfields++;
27c868c2 10463
51219358
MW		 10464 /* Read rest of EEPROM not covered by the checksum. */
10465 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10466 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10467 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10468 if (*charfields++) {
10469 *wbuf = le16_to_cpu(*wbuf);
10470 }
10471 }
10472 return chksum;
10473}
10474
10475/*
10476 * Read EEPROM configuration into the specified buffer.
10477 *
10478 * Return a checksum based on the EEPROM configuration read.
10479 */
6f039790
GKH		 10480static ushort AdvGet38C0800EEPConfig(AdvPortAddr iop_base,
10481 ADVEEP_38C0800_CONFIG *cfg_buf)
51219358
MW		 10482{
10483 ushort wval, chksum;
10484 ushort *wbuf;
10485 int eep_addr;
10486 ushort *charfields;
27c868c2 10487
51219358
MW		 10488 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
10489 wbuf = (ushort *)cfg_buf;
10490 chksum = 0;
10491
10492 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10493 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10494 wval = AdvReadEEPWord(iop_base, eep_addr);
10495 chksum += wval; /* Checksum is calculated from word values. */
27c868c2 10496 if (*charfields++) {
51219358 10497 *wbuf = le16_to_cpu(wval);
27c868c2 10498 } else {
51219358 10499 *wbuf = wval;
27c868c2 10500 }
27c868c2 10501 }
51219358
MW		 10502 /* Read checksum word. */
10503 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
27c868c2
MW		 10504 wbuf++;
10505 charfields++;
10506
51219358
MW		 10507 /* Read rest of EEPROM not covered by the checksum. */
10508 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10509 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10510 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
27c868c2 10511 if (*charfields++) {
51219358 10512 *wbuf = le16_to_cpu(*wbuf);
27c868c2 10513 }
27c868c2 10514 }
51219358 10515 return chksum;
1da177e4
LT		 10516}
10517
10518/*
51219358
MW		 10519 * Read EEPROM configuration into the specified buffer.
10520 *
10521 * Return a checksum based on the EEPROM configuration read.
1da177e4 10522 */
6f039790
GKH		 10523static ushort AdvGet38C1600EEPConfig(AdvPortAddr iop_base,
10524 ADVEEP_38C1600_CONFIG *cfg_buf)
1da177e4 10525{
51219358 10526 ushort wval, chksum;
27c868c2 10527 ushort *wbuf;
51219358 10528 int eep_addr;
27c868c2 10529 ushort *charfields;
27c868c2 10530
27c868c2 10531 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
51219358 10532 wbuf = (ushort *)cfg_buf;
27c868c2
MW		 10533 chksum = 0;
10534
51219358
MW		 10535 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10536 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10537 wval = AdvReadEEPWord(iop_base, eep_addr);
10538 chksum += wval; /* Checksum is calculated from word values. */
27c868c2 10539 if (*charfields++) {
51219358 10540 *wbuf = le16_to_cpu(wval);
27c868c2 10541 } else {
51219358 10542 *wbuf = wval;
27c868c2 10543 }
27c868c2 10544 }
51219358
MW		 10545 /* Read checksum word. */
10546 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
27c868c2
MW		 10547 wbuf++;
10548 charfields++;
10549
51219358
MW		 10550 /* Read rest of EEPROM not covered by the checksum. */
10551 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10552 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10553 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
27c868c2 10554 if (*charfields++) {
51219358 10555 *wbuf = le16_to_cpu(*wbuf);
27c868c2 10556 }
27c868c2 10557 }
51219358 10558 return chksum;
1da177e4
LT		 10559}
10560
1da177e4 10561/*
51219358
MW		 10562 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
10563 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
10564 * all of this is done.
1da177e4 10565 *
51219358 10566 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
1da177e4 10567 *
51219358
MW		 10568 * For a non-fatal error return a warning code. If there are no warnings
10569 * then 0 is returned.
1da177e4 10570 *
51219358 10571 * Note: Chip is stopped on entry.
1da177e4 10572 */
6f039790 10573static int AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
1da177e4 10574{
27c868c2 10575 AdvPortAddr iop_base;
51219358
MW		 10576 ushort warn_code;
10577 ADVEEP_3550_CONFIG eep_config;
1da177e4 10578
27c868c2 10579 iop_base = asc_dvc->iop_base;
1da177e4 10580
51219358 10581 warn_code = 0;
27c868c2
MW		 10582
10583 /*
51219358
MW		 10584 * Read the board's EEPROM configuration.
10585 *
10586 * Set default values if a bad checksum is found.
27c868c2 10587 */
51219358
MW		 10588 if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) {
10589 warn_code |= ASC_WARN_EEPROM_CHKSUM;
27c868c2 10590
51219358
MW		 10591 /*
10592 * Set EEPROM default values.
10593 */
10594 memcpy(&eep_config, &Default_3550_EEPROM_Config,
10595 sizeof(ADVEEP_3550_CONFIG));
27c868c2 10596
51219358
MW		 10597 /*
10598 * Assume the 6 byte board serial number that was read from
10599 * EEPROM is correct even if the EEPROM checksum failed.
10600 */
10601 eep_config.serial_number_word3 =
10602 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
27c868c2 10603
51219358
MW		 10604 eep_config.serial_number_word2 =
10605 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
27c868c2 10606
51219358
MW		 10607 eep_config.serial_number_word1 =
10608 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
27c868c2 10609
51219358
MW		 10610 AdvSet3550EEPConfig(iop_base, &eep_config);
10611 }
10612 /*
10613 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
10614 * EEPROM configuration that was read.
10615 *
10616 * This is the mapping of EEPROM fields to Adv Library fields.
10617 */
10618 asc_dvc->wdtr_able = eep_config.wdtr_able;
10619 asc_dvc->sdtr_able = eep_config.sdtr_able;
10620 asc_dvc->ultra_able = eep_config.ultra_able;
10621 asc_dvc->tagqng_able = eep_config.tagqng_able;
10622 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10623 asc_dvc->max_host_qng = eep_config.max_host_qng;
10624 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10625 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
10626 asc_dvc->start_motor = eep_config.start_motor;
10627 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10628 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10629 asc_dvc->no_scam = eep_config.scam_tolerant;
10630 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
10631 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
10632 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
27c868c2 10633
27c868c2 10634 /*
51219358
MW		 10635 * Set the host maximum queuing (max. 253, min. 16) and the per device
10636 * maximum queuing (max. 63, min. 4).
27c868c2 10637 */
51219358
MW		 10638 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10639 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10640 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10641 /* If the value is zero, assume it is uninitialized. */
10642 if (eep_config.max_host_qng == 0) {
10643 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10644 } else {
10645 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10646 }
10647 }
10648
10649 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10650 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10651 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10652 /* If the value is zero, assume it is uninitialized. */
10653 if (eep_config.max_dvc_qng == 0) {
10654 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10655 } else {
10656 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10657 }
10658 }
27c868c2
MW		 10659
10660 /*
51219358
MW		 10661 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10662 * set 'max_dvc_qng' to 'max_host_qng'.
27c868c2 10663 */
51219358
MW		 10664 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10665 eep_config.max_dvc_qng = eep_config.max_host_qng;
10666 }
27c868c2
MW		 10667
10668 /*
51219358
MW		 10669 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
10670 * values based on possibly adjusted EEPROM values.
27c868c2 10671 */
51219358
MW		 10672 asc_dvc->max_host_qng = eep_config.max_host_qng;
10673 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
27c868c2
MW		 10674
10675 /*
51219358
MW		 10676 * If the EEPROM 'termination' field is set to automatic (0), then set
10677 * the ADV_DVC_CFG 'termination' field to automatic also.
10678 *
10679 * If the termination is specified with a non-zero 'termination'
10680 * value check that a legal value is set and set the ADV_DVC_CFG
10681 * 'termination' field appropriately.
27c868c2 10682 */
51219358
MW		 10683 if (eep_config.termination == 0) {
10684 asc_dvc->cfg->termination = 0; /* auto termination */
10685 } else {
10686 /* Enable manual control with low off / high off. */
10687 if (eep_config.termination == 1) {
10688 asc_dvc->cfg->termination = TERM_CTL_SEL;
27c868c2 10689
51219358
MW		 10690 /* Enable manual control with low off / high on. */
10691 } else if (eep_config.termination == 2) {
10692 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
10693
10694 /* Enable manual control with low on / high on. */
10695 } else if (eep_config.termination == 3) {
10696 asc_dvc->cfg->termination =
10697 TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
10698 } else {
27c868c2 10699 /*
51219358
MW		 10700 * The EEPROM 'termination' field contains a bad value. Use
10701 * automatic termination instead.
27c868c2 10702 */
51219358
MW		 10703 asc_dvc->cfg->termination = 0;
10704 warn_code |= ASC_WARN_EEPROM_TERMINATION;
27c868c2 10705 }
27c868c2 10706 }
1da177e4 10707
51219358 10708 return warn_code;
1da177e4
LT		 10709}
10710
10711/*
51219358
MW		 10712 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
10713 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
10714 * all of this is done.
1da177e4 10715 *
51219358
MW		 10716 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
10717 *
10718 * For a non-fatal error return a warning code. If there are no warnings
10719 * then 0 is returned.
10720 *
10721 * Note: Chip is stopped on entry.
1da177e4 10722 */
6f039790 10723static int AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
1da177e4 10724{
51219358
MW		 10725 AdvPortAddr iop_base;
10726 ushort warn_code;
10727 ADVEEP_38C0800_CONFIG eep_config;
10728 uchar tid, termination;
10729 ushort sdtr_speed = 0;
27c868c2 10730
51219358 10731 iop_base = asc_dvc->iop_base;
1da177e4 10732
51219358 10733 warn_code = 0;
27c868c2
MW		 10734
10735 /*
51219358
MW		 10736 * Read the board's EEPROM configuration.
10737 *
10738 * Set default values if a bad checksum is found.
27c868c2 10739 */
51219358
MW		 10740 if (AdvGet38C0800EEPConfig(iop_base, &eep_config) !=
10741 eep_config.check_sum) {
10742 warn_code |= ASC_WARN_EEPROM_CHKSUM;
27c868c2 10743
51219358
MW		 10744 /*
10745 * Set EEPROM default values.
10746 */
10747 memcpy(&eep_config, &Default_38C0800_EEPROM_Config,
10748 sizeof(ADVEEP_38C0800_CONFIG));
1da177e4 10749
51219358
MW		 10750 /*
10751 * Assume the 6 byte board serial number that was read from
10752 * EEPROM is correct even if the EEPROM checksum failed.
10753 */
10754 eep_config.serial_number_word3 =
10755 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
1da177e4 10756
51219358
MW		 10757 eep_config.serial_number_word2 =
10758 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
27c868c2 10759
51219358
MW		 10760 eep_config.serial_number_word1 =
10761 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
27c868c2 10762
51219358 10763 AdvSet38C0800EEPConfig(iop_base, &eep_config);
27c868c2 10764 }
27c868c2 10765 /*
51219358
MW		 10766 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
10767 * EEPROM configuration that was read.
10768 *
10769 * This is the mapping of EEPROM fields to Adv Library fields.
27c868c2 10770 */
51219358
MW		 10771 asc_dvc->wdtr_able = eep_config.wdtr_able;
10772 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
10773 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
10774 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
10775 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
10776 asc_dvc->tagqng_able = eep_config.tagqng_able;
10777 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10778 asc_dvc->max_host_qng = eep_config.max_host_qng;
10779 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10780 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
10781 asc_dvc->start_motor = eep_config.start_motor;
10782 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10783 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10784 asc_dvc->no_scam = eep_config.scam_tolerant;
10785 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
10786 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
10787 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
27c868c2
MW		 10788
10789 /*
51219358
MW		 10790 * For every Target ID if any of its 'sdtr_speed[1234]' bits
10791 * are set, then set an 'sdtr_able' bit for it.
27c868c2 10792 */
51219358
MW		 10793 asc_dvc->sdtr_able = 0;
10794 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
10795 if (tid == 0) {
10796 sdtr_speed = asc_dvc->sdtr_speed1;
10797 } else if (tid == 4) {
10798 sdtr_speed = asc_dvc->sdtr_speed2;
10799 } else if (tid == 8) {
10800 sdtr_speed = asc_dvc->sdtr_speed3;
10801 } else if (tid == 12) {
10802 sdtr_speed = asc_dvc->sdtr_speed4;
10803 }
10804 if (sdtr_speed & ADV_MAX_TID) {
10805 asc_dvc->sdtr_able |= (1 << tid);
10806 }
10807 sdtr_speed >>= 4;
10808 }
27c868c2
MW		 10809
10810 /*
51219358
MW		 10811 * Set the host maximum queuing (max. 253, min. 16) and the per device
10812 * maximum queuing (max. 63, min. 4).
27c868c2 10813 */
51219358
MW		 10814 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10815 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10816 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10817 /* If the value is zero, assume it is uninitialized. */
10818 if (eep_config.max_host_qng == 0) {
10819 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10820 } else {
10821 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10822 }
27c868c2 10823 }
1da177e4 10824
51219358
MW		 10825 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10826 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10827 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10828 /* If the value is zero, assume it is uninitialized. */
10829 if (eep_config.max_dvc_qng == 0) {
10830 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10831 } else {
10832 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10833 }
10834 }
10835
10836 /*
10837 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10838 * set 'max_dvc_qng' to 'max_host_qng'.
10839 */
10840 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10841 eep_config.max_dvc_qng = eep_config.max_host_qng;
27c868c2 10842 }
1da177e4 10843
27c868c2 10844 /*
51219358
MW		 10845 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
10846 * values based on possibly adjusted EEPROM values.
27c868c2 10847 */
51219358
MW		 10848 asc_dvc->max_host_qng = eep_config.max_host_qng;
10849 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
27c868c2
MW		 10850
10851 /*
51219358
MW		 10852 * If the EEPROM 'termination' field is set to automatic (0), then set
10853 * the ADV_DVC_CFG 'termination' field to automatic also.
10854 *
10855 * If the termination is specified with a non-zero 'termination'
10856 * value check that a legal value is set and set the ADV_DVC_CFG
10857 * 'termination' field appropriately.
27c868c2 10858 */
51219358
MW		 10859 if (eep_config.termination_se == 0) {
10860 termination = 0; /* auto termination for SE */
10861 } else {
10862 /* Enable manual control with low off / high off. */
10863 if (eep_config.termination_se == 1) {
10864 termination = 0;
10865
10866 /* Enable manual control with low off / high on. */
10867 } else if (eep_config.termination_se == 2) {
10868 termination = TERM_SE_HI;
10869
10870 /* Enable manual control with low on / high on. */
10871 } else if (eep_config.termination_se == 3) {
10872 termination = TERM_SE;
10873 } else {
10874 /*
10875 * The EEPROM 'termination_se' field contains a bad value.
10876 * Use automatic termination instead.
10877 */
10878 termination = 0;
10879 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10880 }
27c868c2 10881 }
51219358
MW		 10882
10883 if (eep_config.termination_lvd == 0) {
10884 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
10885 } else {
10886 /* Enable manual control with low off / high off. */
10887 if (eep_config.termination_lvd == 1) {
10888 asc_dvc->cfg->termination = termination;
10889
10890 /* Enable manual control with low off / high on. */
10891 } else if (eep_config.termination_lvd == 2) {
10892 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
10893
10894 /* Enable manual control with low on / high on. */
10895 } else if (eep_config.termination_lvd == 3) {
10896 asc_dvc->cfg->termination = termination | TERM_LVD;
10897 } else {
10898 /*
10899 * The EEPROM 'termination_lvd' field contains a bad value.
10900 * Use automatic termination instead.
10901 */
10902 asc_dvc->cfg->termination = termination;
10903 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10904 }
27c868c2 10905 }
1da177e4 10906
51219358 10907 return warn_code;
1da177e4
LT		 10908}
10909
10910/*
51219358
MW		 10911 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
10912 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
10913 * all of this is done.
1da177e4 10914 *
51219358 10915 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
1da177e4 10916 *
51219358
MW		 10917 * For a non-fatal error return a warning code. If there are no warnings
10918 * then 0 is returned.
1da177e4 10919 *
51219358 10920 * Note: Chip is stopped on entry.
1da177e4 10921 */
6f039790 10922static int AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
1da177e4 10923{
27c868c2 10924 AdvPortAddr iop_base;
51219358
MW		 10925 ushort warn_code;
10926 ADVEEP_38C1600_CONFIG eep_config;
10927 uchar tid, termination;
10928 ushort sdtr_speed = 0;
1da177e4 10929
27c868c2
MW		 10930 iop_base = asc_dvc->iop_base;
10931
51219358 10932 warn_code = 0;
27c868c2 10933
51219358
MW		 10934 /*
10935 * Read the board's EEPROM configuration.
10936 *
10937 * Set default values if a bad checksum is found.
10938 */
10939 if (AdvGet38C1600EEPConfig(iop_base, &eep_config) !=
10940 eep_config.check_sum) {
10941 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
10942 warn_code |= ASC_WARN_EEPROM_CHKSUM;
10943
10944 /*
10945 * Set EEPROM default values.
10946 */
10947 memcpy(&eep_config, &Default_38C1600_EEPROM_Config,
10948 sizeof(ADVEEP_38C1600_CONFIG));
10949
10950 if (PCI_FUNC(pdev->devfn) != 0) {
10951 u8 ints;
10952 /*
10953 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60
10954 * and old Mac system booting problem. The Expansion
10955 * ROM must be disabled in Function 1 for these systems
10956 */
10957 eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE;
10958 /*
10959 * Clear the INTAB (bit 11) if the GPIO 0 input
10960 * indicates the Function 1 interrupt line is wired
10961 * to INTB.
10962 *
10963 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
10964 * 1 - Function 1 interrupt line wired to INT A.
10965 * 0 - Function 1 interrupt line wired to INT B.
10966 *
10967 * Note: Function 0 is always wired to INTA.
10968 * Put all 5 GPIO bits in input mode and then read
10969 * their input values.
10970 */
10971 AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
10972 ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA);
10973 if ((ints & 0x01) == 0)
10974 eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB;
10975 }
10976
10977 /*
10978 * Assume the 6 byte board serial number that was read from
10979 * EEPROM is correct even if the EEPROM checksum failed.
10980 */
10981 eep_config.serial_number_word3 =
10982 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
10983 eep_config.serial_number_word2 =
10984 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
10985 eep_config.serial_number_word1 =
10986 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
10987
10988 AdvSet38C1600EEPConfig(iop_base, &eep_config);
27c868c2
MW		 10989 }
10990
10991 /*
51219358
MW		 10992 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
10993 * EEPROM configuration that was read.
10994 *
10995 * This is the mapping of EEPROM fields to Adv Library fields.
27c868c2 10996 */
51219358
MW		 10997 asc_dvc->wdtr_able = eep_config.wdtr_able;
10998 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
10999 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
11000 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
11001 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
11002 asc_dvc->ppr_able = 0;
11003 asc_dvc->tagqng_able = eep_config.tagqng_able;
11004 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
11005 asc_dvc->max_host_qng = eep_config.max_host_qng;
11006 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
11007 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
11008 asc_dvc->start_motor = eep_config.start_motor;
11009 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
11010 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
11011 asc_dvc->no_scam = eep_config.scam_tolerant;
27c868c2 11012
51219358
MW		 11013 /*
11014 * For every Target ID if any of its 'sdtr_speed[1234]' bits
11015 * are set, then set an 'sdtr_able' bit for it.
11016 */
11017 asc_dvc->sdtr_able = 0;
11018 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
11019 if (tid == 0) {
11020 sdtr_speed = asc_dvc->sdtr_speed1;
11021 } else if (tid == 4) {
11022 sdtr_speed = asc_dvc->sdtr_speed2;
11023 } else if (tid == 8) {
11024 sdtr_speed = asc_dvc->sdtr_speed3;
11025 } else if (tid == 12) {
11026 sdtr_speed = asc_dvc->sdtr_speed4;
11027 }
11028 if (sdtr_speed & ASC_MAX_TID) {
11029 asc_dvc->sdtr_able |= (1 << tid);
11030 }
11031 sdtr_speed >>= 4;
11032 }
27c868c2 11033
51219358
MW		 11034 /*
11035 * Set the host maximum queuing (max. 253, min. 16) and the per device
11036 * maximum queuing (max. 63, min. 4).
11037 */
11038 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
11039 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
11040 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
11041 /* If the value is zero, assume it is uninitialized. */
11042 if (eep_config.max_host_qng == 0) {
11043 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
11044 } else {
11045 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
27c868c2 11046 }
51219358 11047 }
27c868c2 11048
51219358
MW		 11049 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
11050 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
11051 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
11052 /* If the value is zero, assume it is uninitialized. */
11053 if (eep_config.max_dvc_qng == 0) {
11054 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
11055 } else {
11056 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
11057 }
11058 }
11059
11060 /*
11061 * If 'max_dvc_qng' is greater than 'max_host_qng', then
11062 * set 'max_dvc_qng' to 'max_host_qng'.
11063 */
11064 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
11065 eep_config.max_dvc_qng = eep_config.max_host_qng;
27c868c2
MW		 11066 }
11067
11068 /*
51219358
MW		 11069 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
11070 * values based on possibly adjusted EEPROM values.
11071 */
11072 asc_dvc->max_host_qng = eep_config.max_host_qng;
11073 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
11074
11075 /*
11076 * If the EEPROM 'termination' field is set to automatic (0), then set
11077 * the ASC_DVC_CFG 'termination' field to automatic also.
11078 *
11079 * If the termination is specified with a non-zero 'termination'
11080 * value check that a legal value is set and set the ASC_DVC_CFG
11081 * 'termination' field appropriately.
27c868c2 11082 */
51219358
MW		 11083 if (eep_config.termination_se == 0) {
11084 termination = 0; /* auto termination for SE */
11085 } else {
11086 /* Enable manual control with low off / high off. */
11087 if (eep_config.termination_se == 1) {
11088 termination = 0;
27c868c2 11089
51219358
MW		 11090 /* Enable manual control with low off / high on. */
11091 } else if (eep_config.termination_se == 2) {
11092 termination = TERM_SE_HI;
27c868c2 11093
51219358
MW		 11094 /* Enable manual control with low on / high on. */
11095 } else if (eep_config.termination_se == 3) {
11096 termination = TERM_SE;
11097 } else {
11098 /*
11099 * The EEPROM 'termination_se' field contains a bad value.
11100 * Use automatic termination instead.
11101 */
11102 termination = 0;
11103 warn_code |= ASC_WARN_EEPROM_TERMINATION;
11104 }
11105 }
27c868c2 11106
51219358
MW		 11107 if (eep_config.termination_lvd == 0) {
11108 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
11109 } else {
11110 /* Enable manual control with low off / high off. */
11111 if (eep_config.termination_lvd == 1) {
11112 asc_dvc->cfg->termination = termination;
27c868c2 11113
51219358
MW		 11114 /* Enable manual control with low off / high on. */
11115 } else if (eep_config.termination_lvd == 2) {
11116 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
27c868c2 11117
51219358
MW		 11118 /* Enable manual control with low on / high on. */
11119 } else if (eep_config.termination_lvd == 3) {
11120 asc_dvc->cfg->termination = termination | TERM_LVD;
11121 } else {
11122 /*
11123 * The EEPROM 'termination_lvd' field contains a bad value.
11124 * Use automatic termination instead.
11125 */
11126 asc_dvc->cfg->termination = termination;
11127 warn_code |= ASC_WARN_EEPROM_TERMINATION;
11128 }
27c868c2 11129 }
51219358
MW		 11130
11131 return warn_code;
1da177e4
LT		 11132}
11133
11134/*
51219358 11135 * Initialize the ADV_DVC_VAR structure.
1da177e4 11136 *
51219358 11137 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
1da177e4 11138 *
51219358
MW		 11139 * For a non-fatal error return a warning code. If there are no warnings
11140 * then 0 is returned.
1da177e4 11141 */
6f039790 11142static int AdvInitGetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
1da177e4 11143{
9d0e96eb
MW		 11144 struct asc_board *board = shost_priv(shost);
11145 ADV_DVC_VAR *asc_dvc = &board->dvc_var.adv_dvc_var;
51219358
MW		 11146 unsigned short warn_code = 0;
11147 AdvPortAddr iop_base = asc_dvc->iop_base;
11148 u16 cmd;
11149 int status;
27c868c2 11150
51219358 11151 asc_dvc->err_code = 0;
27c868c2
MW		 11152
11153 /*
51219358
MW		 11154 * Save the state of the PCI Configuration Command Register
11155 * "Parity Error Response Control" Bit. If the bit is clear (0),
11156 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
11157 * DMA parity errors.
27c868c2 11158 */
51219358
MW		 11159 asc_dvc->cfg->control_flag = 0;
11160 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
11161 if ((cmd & PCI_COMMAND_PARITY) == 0)
11162 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
27c868c2 11163
51219358
MW		 11164 asc_dvc->cfg->chip_version =
11165 AdvGetChipVersion(iop_base, asc_dvc->bus_type);
11166
b352f923 11167 ASC_DBG(1, "iopb_chip_id_1: 0x%x 0x%x\n",
51219358
MW		 11168 (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
11169 (ushort)ADV_CHIP_ID_BYTE);
11170
b352f923 11171 ASC_DBG(1, "iopw_chip_id_0: 0x%x 0x%x\n",
51219358
MW		 11172 (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
11173 (ushort)ADV_CHIP_ID_WORD);
27c868c2
MW		 11174
11175 /*
51219358 11176 * Reset the chip to start and allow register writes.
27c868c2 11177 */
51219358
MW		 11178 if (AdvFindSignature(iop_base) == 0) {
11179 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
11180 return ADV_ERROR;
11181 } else {
27c868c2 11182 /*
51219358 11183 * The caller must set 'chip_type' to a valid setting.
27c868c2 11184 */
51219358
MW		 11185 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
11186 asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
11187 asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
11188 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
11189 return ADV_ERROR;
11190 }
1da177e4 11191
51219358
MW		 11192 /*
11193 * Reset Chip.
11194 */
11195 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
11196 ADV_CTRL_REG_CMD_RESET);
11197 mdelay(100);
11198 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
11199 ADV_CTRL_REG_CMD_WR_IO_REG);
11200
11201 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
11202 status = AdvInitFrom38C1600EEP(asc_dvc);
11203 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
11204 status = AdvInitFrom38C0800EEP(asc_dvc);
11205 } else {
11206 status = AdvInitFrom3550EEP(asc_dvc);
27c868c2 11207 }
51219358 11208 warn_code |= status;
27c868c2 11209 }
1da177e4 11210
9d0e96eb
MW		 11211 if (warn_code != 0)
11212 shost_printk(KERN_WARNING, shost, "warning: 0x%x\n", warn_code);
51219358 11213
9d0e96eb
MW		 11214 if (asc_dvc->err_code)
11215 shost_printk(KERN_ERR, shost, "error code 0x%x\n",
11216 asc_dvc->err_code);
51219358
MW		 11217
11218 return asc_dvc->err_code;
1da177e4 11219}
51219358
MW		 11220#endif
11221
11222static struct scsi_host_template advansys_template = {
11223 .proc_name = DRV_NAME,
11224#ifdef CONFIG_PROC_FS
b59fb6fd 11225 .show_info = advansys_show_info,
51219358
MW		 11226#endif
11227 .name = DRV_NAME,
11228 .info = advansys_info,
11229 .queuecommand = advansys_queuecommand,
eac0b0c7 11230 .eh_host_reset_handler = advansys_reset,
51219358
MW		 11231 .bios_param = advansys_biosparam,
11232 .slave_configure = advansys_slave_configure,
11233 /*
11234 * Because the driver may control an ISA adapter 'unchecked_isa_dma'
11235 * must be set. The flag will be cleared in advansys_board_found
11236 * for non-ISA adapters.
11237 */
11238 .unchecked_isa_dma = 1,
11239 /*
11240 * All adapters controlled by this driver are capable of large
11241 * scatter-gather lists. According to the mid-level SCSI documentation
11242 * this obviates any performance gain provided by setting
11243 * 'use_clustering'. But empirically while CPU utilization is increased
11244 * by enabling clustering, I/O throughput increases as well.
11245 */
11246 .use_clustering = ENABLE_CLUSTERING,
11247};
1da177e4 11248
6f039790 11249static int advansys_wide_init_chip(struct Scsi_Host *shost)
b2c16f58 11250{
9d0e96eb
MW		 11251 struct asc_board *board = shost_priv(shost);
11252 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
b2c16f58
MW		 11253 int req_cnt = 0;
11254 adv_req_t *reqp = NULL;
11255 int sg_cnt = 0;
11256 adv_sgblk_t *sgp;
11257 int warn_code, err_code;
11258
11259 /*
11260 * Allocate buffer carrier structures. The total size
11261 * is about 4 KB, so allocate all at once.
11262 */
98d41c29
MW		 11263 adv_dvc->carrier_buf = kmalloc(ADV_CARRIER_BUFSIZE, GFP_KERNEL);
11264 ASC_DBG(1, "carrier_buf 0x%p\n", adv_dvc->carrier_buf);
b2c16f58 11265
98d41c29 11266 if (!adv_dvc->carrier_buf)
b2c16f58
MW		 11267 goto kmalloc_failed;
11268
11269 /*
11270 * Allocate up to 'max_host_qng' request structures for the Wide
11271 * board. The total size is about 16 KB, so allocate all at once.
11272 * If the allocation fails decrement and try again.
11273 */
9d0e96eb 11274 for (req_cnt = adv_dvc->max_host_qng; req_cnt > 0; req_cnt--) {
b2c16f58
MW		 11275 reqp = kmalloc(sizeof(adv_req_t) * req_cnt, GFP_KERNEL);
11276
b352f923 11277 ASC_DBG(1, "reqp 0x%p, req_cnt %d, bytes %lu\n", reqp, req_cnt,
b2c16f58
MW		 11278 (ulong)sizeof(adv_req_t) * req_cnt);
11279
11280 if (reqp)
11281 break;
11282 }
11283
11284 if (!reqp)
11285 goto kmalloc_failed;
11286
98d41c29 11287 adv_dvc->orig_reqp = reqp;
b2c16f58
MW		 11288
11289 /*
11290 * Allocate up to ADV_TOT_SG_BLOCK request structures for
11291 * the Wide board. Each structure is about 136 bytes.
11292 */
9d0e96eb 11293 board->adv_sgblkp = NULL;
b2c16f58
MW		 11294 for (sg_cnt = 0; sg_cnt < ADV_TOT_SG_BLOCK; sg_cnt++) {
11295 sgp = kmalloc(sizeof(adv_sgblk_t), GFP_KERNEL);
11296
11297 if (!sgp)
11298 break;
11299
9d0e96eb
MW		 11300 sgp->next_sgblkp = board->adv_sgblkp;
11301 board->adv_sgblkp = sgp;
b2c16f58
MW		 11302
11303 }
11304
9d511a4b
MW		 11305 ASC_DBG(1, "sg_cnt %d * %lu = %lu bytes\n", sg_cnt, sizeof(adv_sgblk_t),
11306 sizeof(adv_sgblk_t) * sg_cnt);
b2c16f58 11307
9d0e96eb 11308 if (!board->adv_sgblkp)
b2c16f58
MW		 11309 goto kmalloc_failed;
11310
b2c16f58
MW		 11311 /*
11312 * Point 'adv_reqp' to the request structures and
11313 * link them together.
11314 */
11315 req_cnt--;
11316 reqp[req_cnt].next_reqp = NULL;
11317 for (; req_cnt > 0; req_cnt--) {
11318 reqp[req_cnt - 1].next_reqp = &reqp[req_cnt];
11319 }
9d0e96eb 11320 board->adv_reqp = &reqp[0];
b2c16f58 11321
9d0e96eb 11322 if (adv_dvc->chip_type == ADV_CHIP_ASC3550) {
b352f923 11323 ASC_DBG(2, "AdvInitAsc3550Driver()\n");
9d0e96eb
MW		 11324 warn_code = AdvInitAsc3550Driver(adv_dvc);
11325 } else if (adv_dvc->chip_type == ADV_CHIP_ASC38C0800) {
b352f923 11326 ASC_DBG(2, "AdvInitAsc38C0800Driver()\n");
9d0e96eb 11327 warn_code = AdvInitAsc38C0800Driver(adv_dvc);
b2c16f58 11328 } else {
b352f923 11329 ASC_DBG(2, "AdvInitAsc38C1600Driver()\n");
9d0e96eb 11330 warn_code = AdvInitAsc38C1600Driver(adv_dvc);
b2c16f58 11331 }
9d0e96eb 11332 err_code = adv_dvc->err_code;
b2c16f58
MW		 11333
11334 if (warn_code || err_code) {
9d0e96eb
MW		 11335 shost_printk(KERN_WARNING, shost, "error: warn 0x%x, error "
11336 "0x%x\n", warn_code, err_code);
b2c16f58
MW		 11337 }
11338
11339 goto exit;
11340
11341 kmalloc_failed:
9d0e96eb 11342 shost_printk(KERN_ERR, shost, "error: kmalloc() failed\n");
b2c16f58
MW		 11343 err_code = ADV_ERROR;
11344 exit:
11345 return err_code;
11346}
11347
98d41c29 11348static void advansys_wide_free_mem(struct asc_board *board)
b2c16f58 11349{
98d41c29
MW		 11350 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
11351 kfree(adv_dvc->carrier_buf);
11352 adv_dvc->carrier_buf = NULL;
11353 kfree(adv_dvc->orig_reqp);
11354 adv_dvc->orig_reqp = board->adv_reqp = NULL;
11355 while (board->adv_sgblkp) {
11356 adv_sgblk_t *sgp = board->adv_sgblkp;
11357 board->adv_sgblkp = sgp->next_sgblkp;
b2c16f58
MW		 11358 kfree(sgp);
11359 }
11360}
11361
6f039790
GKH		 11362static int advansys_board_found(struct Scsi_Host *shost, unsigned int iop,
11363 int bus_type)
27c868c2 11364{
d361db48 11365 struct pci_dev *pdev;
d2411495 11366 struct asc_board *boardp = shost_priv(shost);
27c868c2
MW		 11367 ASC_DVC_VAR *asc_dvc_varp = NULL;
11368 ADV_DVC_VAR *adv_dvc_varp = NULL;
d361db48 11369 int share_irq, warn_code, ret;
27c868c2 11370
d361db48 11371 pdev = (bus_type == ASC_IS_PCI) ? to_pci_dev(boardp->dev) : NULL;
27c868c2
MW		 11372
11373 if (ASC_NARROW_BOARD(boardp)) {
b352f923 11374 ASC_DBG(1, "narrow board\n");
27c868c2
MW		 11375 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
11376 asc_dvc_varp->bus_type = bus_type;
11377 asc_dvc_varp->drv_ptr = boardp;
11378 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
27c868c2 11379 asc_dvc_varp->iop_base = iop;
27c868c2 11380 } else {
57ba5fe9 11381#ifdef CONFIG_PCI
27c868c2
MW		 11382 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
11383 adv_dvc_varp->drv_ptr = boardp;
11384 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
27c868c2 11385 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) {
b352f923 11386 ASC_DBG(1, "wide board ASC-3550\n");
27c868c2
MW		 11387 adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
11388 } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) {
b352f923 11389 ASC_DBG(1, "wide board ASC-38C0800\n");
27c868c2
MW		 11390 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
11391 } else {
b352f923 11392 ASC_DBG(1, "wide board ASC-38C1600\n");
27c868c2
MW		 11393 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
11394 }
27c868c2 11395
57ba5fe9 11396 boardp->asc_n_io_port = pci_resource_len(pdev, 1);
25729a7f 11397 boardp->ioremap_addr = pci_ioremap_bar(pdev, 1);
57ba5fe9 11398 if (!boardp->ioremap_addr) {
9d511a4b 11399 shost_printk(KERN_ERR, shost, "ioremap(%lx, %d) "
9d0e96eb 11400 "returned NULL\n",
9d511a4b 11401 (long)pci_resource_start(pdev, 1),
9d0e96eb 11402 boardp->asc_n_io_port);
d361db48 11403 ret = -ENODEV;
b2c16f58 11404 goto err_shost;
27c868c2 11405 }
b352f923
MW		 11406 adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr;
11407 ASC_DBG(1, "iop_base: 0x%p\n", adv_dvc_varp->iop_base);
27c868c2
MW		 11408
11409 /*
11410 * Even though it isn't used to access wide boards, other
11411 * than for the debug line below, save I/O Port address so
11412 * that it can be reported.
11413 */
11414 boardp->ioport = iop;
11415
b352f923
MW		 11416 ASC_DBG(1, "iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n",
11417 (ushort)inp(iop + 1), (ushort)inpw(iop));
57ba5fe9 11418#endif /* CONFIG_PCI */
27c868c2
MW		 11419 }
11420
27c868c2 11421 if (ASC_NARROW_BOARD(boardp)) {
27c868c2
MW		 11422 /*
11423 * Set the board bus type and PCI IRQ before
11424 * calling AscInitGetConfig().
11425 */
11426 switch (asc_dvc_varp->bus_type) {
11427#ifdef CONFIG_ISA
11428 case ASC_IS_ISA:
11429 shost->unchecked_isa_dma = TRUE;
074c8fe4 11430 share_irq = 0;
27c868c2
MW		 11431 break;
11432 case ASC_IS_VL:
11433 shost->unchecked_isa_dma = FALSE;
074c8fe4 11434 share_irq = 0;
27c868c2
MW		 11435 break;
11436 case ASC_IS_EISA:
11437 shost->unchecked_isa_dma = FALSE;
074c8fe4 11438 share_irq = IRQF_SHARED;
27c868c2
MW		 11439 break;
11440#endif /* CONFIG_ISA */
11441#ifdef CONFIG_PCI
11442 case ASC_IS_PCI:
27c868c2 11443 shost->unchecked_isa_dma = FALSE;
074c8fe4 11444 share_irq = IRQF_SHARED;
27c868c2
MW		 11445 break;
11446#endif /* CONFIG_PCI */
11447 default:
9d0e96eb
MW		 11448 shost_printk(KERN_ERR, shost, "unknown adapter type: "
11449 "%d\n", asc_dvc_varp->bus_type);
27c868c2 11450 shost->unchecked_isa_dma = TRUE;
074c8fe4 11451 share_irq = 0;
27c868c2
MW		 11452 break;
11453 }
27c868c2 11454
27c868c2
MW		 11455 /*
11456 * NOTE: AscInitGetConfig() may change the board's
11457 * bus_type value. The bus_type value should no
11458 * longer be used. If the bus_type field must be
11459 * referenced only use the bit-wise AND operator "&".
11460 */
b352f923 11461 ASC_DBG(2, "AscInitGetConfig()\n");
9d0e96eb 11462 ret = AscInitGetConfig(shost) ? -ENODEV : 0;
27c868c2 11463 } else {
c2dce2fa
MW		 11464#ifdef CONFIG_PCI
11465 /*
11466 * For Wide boards set PCI information before calling
11467 * AdvInitGetConfig().
11468 */
c2dce2fa
MW		 11469 shost->unchecked_isa_dma = FALSE;
11470 share_irq = IRQF_SHARED;
b352f923 11471 ASC_DBG(2, "AdvInitGetConfig()\n");
394dbf3f 11472
9d0e96eb 11473 ret = AdvInitGetConfig(pdev, shost) ? -ENODEV : 0;
c2dce2fa 11474#endif /* CONFIG_PCI */
27c868c2
MW		 11475 }
11476
d361db48 11477 if (ret)
b59fb6fd 11478 goto err_unmap;
27c868c2
MW		 11479
11480 /*
11481 * Save the EEPROM configuration so that it can be displayed
11482 * from /proc/scsi/advansys/[0...].
11483 */
11484 if (ASC_NARROW_BOARD(boardp)) {
11485
11486 ASCEEP_CONFIG *ep;
11487
11488 /*
11489 * Set the adapter's target id bit in the 'init_tidmask' field.
11490 */
11491 boardp->init_tidmask |=
11492 ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
11493
11494 /*
11495 * Save EEPROM settings for the board.
11496 */
11497 ep = &boardp->eep_config.asc_eep;
11498
11499 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
11500 ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
11501 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
11502 ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
11503 ep->start_motor = asc_dvc_varp->start_motor;
11504 ep->cntl = asc_dvc_varp->dvc_cntl;
11505 ep->no_scam = asc_dvc_varp->no_scam;
11506 ep->max_total_qng = asc_dvc_varp->max_total_qng;
11507 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
11508 /* 'max_tag_qng' is set to the same value for every device. */
11509 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
11510 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
11511 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
11512 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
11513 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
11514 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
11515 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
11516
11517 /*
11518 * Modify board configuration.
11519 */
b352f923 11520 ASC_DBG(2, "AscInitSetConfig()\n");
9d0e96eb 11521 ret = AscInitSetConfig(pdev, shost) ? -ENODEV : 0;
d361db48 11522 if (ret)
b59fb6fd 11523 goto err_unmap;
27c868c2
MW		 11524 } else {
11525 ADVEEP_3550_CONFIG *ep_3550;
11526 ADVEEP_38C0800_CONFIG *ep_38C0800;
11527 ADVEEP_38C1600_CONFIG *ep_38C1600;
11528
11529 /*
11530 * Save Wide EEP Configuration Information.
11531 */
11532 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
11533 ep_3550 = &boardp->eep_config.adv_3550_eep;
11534
11535 ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
11536 ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
11537 ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11538 ep_3550->termination = adv_dvc_varp->cfg->termination;
11539 ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
11540 ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
11541 ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
11542 ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
11543 ep_3550->ultra_able = adv_dvc_varp->ultra_able;
11544 ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
11545 ep_3550->start_motor = adv_dvc_varp->start_motor;
11546 ep_3550->scsi_reset_delay =
11547 adv_dvc_varp->scsi_reset_wait;
11548 ep_3550->serial_number_word1 =
11549 adv_dvc_varp->cfg->serial1;
11550 ep_3550->serial_number_word2 =
11551 adv_dvc_varp->cfg->serial2;
11552 ep_3550->serial_number_word3 =
11553 adv_dvc_varp->cfg->serial3;
11554 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
11555 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
11556
11557 ep_38C0800->adapter_scsi_id =
11558 adv_dvc_varp->chip_scsi_id;
11559 ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
11560 ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11561 ep_38C0800->termination_lvd =
11562 adv_dvc_varp->cfg->termination;
11563 ep_38C0800->disc_enable =
11564 adv_dvc_varp->cfg->disc_enable;
11565 ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
11566 ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
11567 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
11568 ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
11569 ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
11570 ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
11571 ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
11572 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
11573 ep_38C0800->start_motor = adv_dvc_varp->start_motor;
11574 ep_38C0800->scsi_reset_delay =
11575 adv_dvc_varp->scsi_reset_wait;
11576 ep_38C0800->serial_number_word1 =
11577 adv_dvc_varp->cfg->serial1;
11578 ep_38C0800->serial_number_word2 =
11579 adv_dvc_varp->cfg->serial2;
11580 ep_38C0800->serial_number_word3 =
11581 adv_dvc_varp->cfg->serial3;
11582 } else {
11583 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
11584
11585 ep_38C1600->adapter_scsi_id =
11586 adv_dvc_varp->chip_scsi_id;
11587 ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
11588 ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11589 ep_38C1600->termination_lvd =
11590 adv_dvc_varp->cfg->termination;
11591 ep_38C1600->disc_enable =
11592 adv_dvc_varp->cfg->disc_enable;
11593 ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
11594 ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
11595 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
11596 ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
11597 ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
11598 ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
11599 ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
11600 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
11601 ep_38C1600->start_motor = adv_dvc_varp->start_motor;
11602 ep_38C1600->scsi_reset_delay =
11603 adv_dvc_varp->scsi_reset_wait;
11604 ep_38C1600->serial_number_word1 =
11605 adv_dvc_varp->cfg->serial1;
11606 ep_38C1600->serial_number_word2 =
11607 adv_dvc_varp->cfg->serial2;
11608 ep_38C1600->serial_number_word3 =
11609 adv_dvc_varp->cfg->serial3;
11610 }
11611
11612 /*
11613 * Set the adapter's target id bit in the 'init_tidmask' field.
11614 */
11615 boardp->init_tidmask |=
11616 ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
27c868c2
MW		 11617 }
11618
11619 /*
11620 * Channels are numbered beginning with 0. For AdvanSys one host
11621 * structure supports one channel. Multi-channel boards have a
11622 * separate host structure for each channel.
11623 */
11624 shost->max_channel = 0;
11625 if (ASC_NARROW_BOARD(boardp)) {
11626 shost->max_id = ASC_MAX_TID + 1;
11627 shost->max_lun = ASC_MAX_LUN + 1;
f05ec594 11628 shost->max_cmd_len = ASC_MAX_CDB_LEN;
27c868c2
MW		 11629
11630 shost->io_port = asc_dvc_varp->iop_base;
11631 boardp->asc_n_io_port = ASC_IOADR_GAP;
11632 shost->this_id = asc_dvc_varp->cfg->chip_scsi_id;
11633
11634 /* Set maximum number of queues the adapter can handle. */
11635 shost->can_queue = asc_dvc_varp->max_total_qng;
11636 } else {
11637 shost->max_id = ADV_MAX_TID + 1;
11638 shost->max_lun = ADV_MAX_LUN + 1;
f05ec594 11639 shost->max_cmd_len = ADV_MAX_CDB_LEN;
27c868c2
MW		 11640
11641 /*
11642 * Save the I/O Port address and length even though
11643 * I/O ports are not used to access Wide boards.
11644 * Instead the Wide boards are accessed with
11645 * PCI Memory Mapped I/O.
11646 */
11647 shost->io_port = iop;
27c868c2
MW		 11648
11649 shost->this_id = adv_dvc_varp->chip_scsi_id;
11650
11651 /* Set maximum number of queues the adapter can handle. */
11652 shost->can_queue = adv_dvc_varp->max_host_qng;
11653 }
11654
27c868c2
MW		 11655 /*
11656 * Following v1.3.89, 'cmd_per_lun' is no longer needed
11657 * and should be set to zero.
11658 *
11659 * But because of a bug introduced in v1.3.89 if the driver is
11660 * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level
11661 * SCSI function 'allocate_device' will panic. To allow the driver
11662 * to work as a module in these kernels set 'cmd_per_lun' to 1.
11663 *
11664 * Note: This is wrong. cmd_per_lun should be set to the depth
11665 * you want on untagged devices always.
11666 #ifdef MODULE
11667 */
11668 shost->cmd_per_lun = 1;
11669/* #else
11670 shost->cmd_per_lun = 0;
11671#endif */
11672
11673 /*
11674 * Set the maximum number of scatter-gather elements the
11675 * adapter can handle.
11676 */
11677 if (ASC_NARROW_BOARD(boardp)) {
11678 /*
11679 * Allow two commands with 'sg_tablesize' scatter-gather
11680 * elements to be executed simultaneously. This value is
11681 * the theoretical hardware limit. It may be decreased
11682 * below.
11683 */
11684 shost->sg_tablesize =
11685 (((asc_dvc_varp->max_total_qng - 2) / 2) *
11686 ASC_SG_LIST_PER_Q) + 1;
11687 } else {
11688 shost->sg_tablesize = ADV_MAX_SG_LIST;
11689 }
11690
11691 /*
11692 * The value of 'sg_tablesize' can not exceed the SCSI
11693 * mid-level driver definition of SG_ALL. SG_ALL also
11694 * must not be exceeded, because it is used to define the
11695 * size of the scatter-gather table in 'struct asc_sg_head'.
11696 */
11697 if (shost->sg_tablesize > SG_ALL) {
11698 shost->sg_tablesize = SG_ALL;
11699 }
11700
b352f923 11701 ASC_DBG(1, "sg_tablesize: %d\n", shost->sg_tablesize);
27c868c2
MW		 11702
11703 /* BIOS start address. */
11704 if (ASC_NARROW_BOARD(boardp)) {
b2c16f58
MW		 11705 shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base,
11706 asc_dvc_varp->bus_type);
27c868c2
MW		 11707 } else {
11708 /*
11709 * Fill-in BIOS board variables. The Wide BIOS saves
11710 * information in LRAM that is used by the driver.
11711 */
11712 AdvReadWordLram(adv_dvc_varp->iop_base,
11713 BIOS_SIGNATURE, boardp->bios_signature);
11714 AdvReadWordLram(adv_dvc_varp->iop_base,
11715 BIOS_VERSION, boardp->bios_version);
11716 AdvReadWordLram(adv_dvc_varp->iop_base,
11717 BIOS_CODESEG, boardp->bios_codeseg);
11718 AdvReadWordLram(adv_dvc_varp->iop_base,
11719 BIOS_CODELEN, boardp->bios_codelen);
11720
b352f923 11721 ASC_DBG(1, "bios_signature 0x%x, bios_version 0x%x\n",
27c868c2
MW		 11722 boardp->bios_signature, boardp->bios_version);
11723
b352f923 11724 ASC_DBG(1, "bios_codeseg 0x%x, bios_codelen 0x%x\n",
27c868c2
MW		 11725 boardp->bios_codeseg, boardp->bios_codelen);
11726
11727 /*
11728 * If the BIOS saved a valid signature, then fill in
11729 * the BIOS code segment base address.
11730 */
11731 if (boardp->bios_signature == 0x55AA) {
11732 /*
11733 * Convert x86 realmode code segment to a linear
11734 * address by shifting left 4.
11735 */
11736 shost->base = ((ulong)boardp->bios_codeseg << 4);
11737 } else {
11738 shost->base = 0;
11739 }
11740 }
11741
11742 /*
11743 * Register Board Resources - I/O Port, DMA, IRQ
11744 */
11745
27c868c2
MW		 11746 /* Register DMA Channel for Narrow boards. */
11747 shost->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */
11748#ifdef CONFIG_ISA
11749 if (ASC_NARROW_BOARD(boardp)) {
11750 /* Register DMA channel for ISA bus. */
11751 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
11752 shost->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
01fbfe0b 11753 ret = request_dma(shost->dma_channel, DRV_NAME);
b2c16f58 11754 if (ret) {
9d0e96eb
MW		 11755 shost_printk(KERN_ERR, shost, "request_dma() "
11756 "%d failed %d\n",
11757 shost->dma_channel, ret);
b59fb6fd 11758 goto err_unmap;
27c868c2
MW		 11759 }
11760 AscEnableIsaDma(shost->dma_channel);
11761 }
11762 }
11763#endif /* CONFIG_ISA */
11764
11765 /* Register IRQ Number. */
b352f923 11766 ASC_DBG(2, "request_irq(%d, %p)\n", boardp->irq, shost);
074c8fe4 11767
d361db48 11768 ret = request_irq(boardp->irq, advansys_interrupt, share_irq,
01fbfe0b 11769 DRV_NAME, shost);
074c8fe4
MW		 11770
11771 if (ret) {
27c868c2 11772 if (ret == -EBUSY) {
9d0e96eb
MW		 11773 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11774 "already in use\n", boardp->irq);
27c868c2 11775 } else if (ret == -EINVAL) {
9d0e96eb
MW		 11776 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11777 "not valid\n", boardp->irq);
27c868c2 11778 } else {
9d0e96eb
MW		 11779 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11780 "failed with %d\n", boardp->irq, ret);
27c868c2 11781 }
b2c16f58 11782 goto err_free_dma;
27c868c2
MW		 11783 }
11784
11785 /*
11786 * Initialize board RISC chip and enable interrupts.
11787 */
11788 if (ASC_NARROW_BOARD(boardp)) {
b352f923 11789 ASC_DBG(2, "AscInitAsc1000Driver()\n");
7d5d408c
FT		 11790
11791 asc_dvc_varp->overrun_buf = kzalloc(ASC_OVERRUN_BSIZE, GFP_KERNEL);
11792 if (!asc_dvc_varp->overrun_buf) {
11793 ret = -ENOMEM;
9a908c1a 11794 goto err_free_irq;
7d5d408c 11795 }
27c868c2 11796 warn_code = AscInitAsc1000Driver(asc_dvc_varp);
27c868c2 11797
d361db48 11798 if (warn_code || asc_dvc_varp->err_code) {
9d0e96eb
MW		 11799 shost_printk(KERN_ERR, shost, "error: init_state 0x%x, "
11800 "warn 0x%x, error 0x%x\n",
11801 asc_dvc_varp->init_state, warn_code,
11802 asc_dvc_varp->err_code);
9a908c1a 11803 if (!asc_dvc_varp->overrun_dma) {
d361db48 11804 ret = -ENODEV;
9a908c1a 11805 goto err_free_mem;
7d5d408c 11806 }
27c868c2
MW		 11807 }
11808 } else {
9a908c1a 11809 if (advansys_wide_init_chip(shost)) {
d361db48 11810 ret = -ENODEV;
9a908c1a
HRK		 11811 goto err_free_mem;
11812 }
27c868c2
MW		 11813 }
11814
27c868c2
MW		 11815 ASC_DBG_PRT_SCSI_HOST(2, shost);
11816
d361db48 11817 ret = scsi_add_host(shost, boardp->dev);
8dfb5379 11818 if (ret)
9a908c1a 11819 goto err_free_mem;
8dfb5379
MW		 11820
11821 scsi_scan_host(shost);
d361db48 11822 return 0;
b2c16f58 11823
9a908c1a
HRK		 11824 err_free_mem:
11825 if (ASC_NARROW_BOARD(boardp)) {
11826 if (asc_dvc_varp->overrun_dma)
11827 dma_unmap_single(boardp->dev, asc_dvc_varp->overrun_dma,
11828 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
11829 kfree(asc_dvc_varp->overrun_buf);
11830 } else
11831 advansys_wide_free_mem(boardp);
11832 err_free_irq:
d361db48 11833 free_irq(boardp->irq, shost);
b2c16f58 11834 err_free_dma:
30037818 11835#ifdef CONFIG_ISA
b2c16f58
MW		 11836 if (shost->dma_channel != NO_ISA_DMA)
11837 free_dma(shost->dma_channel);
30037818 11838#endif
b2c16f58
MW		 11839 err_unmap:
11840 if (boardp->ioremap_addr)
11841 iounmap(boardp->ioremap_addr);
11842 err_shost:
d361db48 11843 return ret;
27c868c2
MW		 11844}
11845
27c868c2
MW		 11846/*
11847 * advansys_release()
11848 *
11849 * Release resources allocated for a single AdvanSys adapter.
11850 */
11851static int advansys_release(struct Scsi_Host *shost)
11852{
d10fb2c7 11853 struct asc_board *board = shost_priv(shost);
b352f923 11854 ASC_DBG(1, "begin\n");
8dfb5379 11855 scsi_remove_host(shost);
d10fb2c7 11856 free_irq(board->irq, shost);
30037818 11857#ifdef CONFIG_ISA
27c868c2 11858 if (shost->dma_channel != NO_ISA_DMA) {
b352f923 11859 ASC_DBG(1, "free_dma()\n");
27c868c2
MW		 11860 free_dma(shost->dma_channel);
11861 }
30037818 11862#endif
d10fb2c7
MW		 11863 if (ASC_NARROW_BOARD(board)) {
11864 dma_unmap_single(board->dev,
11865 board->dvc_var.asc_dvc_var.overrun_dma,
11866 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
7d5d408c 11867 kfree(board->dvc_var.asc_dvc_var.overrun_buf);
d10fb2c7
MW		 11868 } else {
11869 iounmap(board->ioremap_addr);
11870 advansys_wide_free_mem(board);
27c868c2 11871 }
8dfb5379 11872 scsi_host_put(shost);
b352f923 11873 ASC_DBG(1, "end\n");
27c868c2
MW		 11874 return 0;
11875}
11876
95c9f162
MW		 11877#define ASC_IOADR_TABLE_MAX_IX 11
11878
747d016e 11879static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] = {
c304ec94
MW		 11880 0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190,
11881 0x0210, 0x0230, 0x0250, 0x0330
11882};
11883
d361db48
MW		 11884/*
11885 * The ISA IRQ number is found in bits 2 and 3 of the CfgLsw. It decodes as:
11886 * 00: 10
11887 * 01: 11
11888 * 10: 12
11889 * 11: 15
11890 */
6f039790 11891static unsigned int advansys_isa_irq_no(PortAddr iop_base)
d361db48
MW		 11892{
11893 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
11894 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x03) + 10;
11895 if (chip_irq == 13)
11896 chip_irq = 15;
11897 return chip_irq;
11898}
11899
6f039790 11900static int advansys_isa_probe(struct device *dev, unsigned int id)
c304ec94 11901{
d361db48 11902 int err = -ENODEV;
c304ec94
MW		 11903 PortAddr iop_base = _asc_def_iop_base[id];
11904 struct Scsi_Host *shost;
d361db48 11905 struct asc_board *board;
c304ec94 11906
01fbfe0b 11907 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
b352f923 11908 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
c304ec94
MW		 11909 return -ENODEV;
11910 }
b352f923 11911 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
c304ec94 11912 if (!AscFindSignature(iop_base))
d361db48 11913 goto release_region;
c304ec94 11914 if (!(AscGetChipVersion(iop_base, ASC_IS_ISA) & ASC_CHIP_VER_ISA_BIT))
d361db48 11915 goto release_region;
c304ec94 11916
d361db48
MW		 11917 err = -ENOMEM;
11918 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
c304ec94 11919 if (!shost)
d361db48
MW		 11920 goto release_region;
11921
d2411495 11922 board = shost_priv(shost);
d361db48
MW		 11923 board->irq = advansys_isa_irq_no(iop_base);
11924 board->dev = dev;
11925
11926 err = advansys_board_found(shost, iop_base, ASC_IS_ISA);
11927 if (err)
11928 goto free_host;
c304ec94
MW		 11929
11930 dev_set_drvdata(dev, shost);
11931 return 0;
11932
d361db48
MW		 11933 free_host:
11934 scsi_host_put(shost);
11935 release_region:
71f36115 11936 release_region(iop_base, ASC_IOADR_GAP);
d361db48 11937 return err;
c304ec94
MW		 11938}
11939
6f039790 11940static int advansys_isa_remove(struct device *dev, unsigned int id)
c304ec94 11941{
71f36115 11942 int ioport = _asc_def_iop_base[id];
c304ec94 11943 advansys_release(dev_get_drvdata(dev));
71f36115 11944 release_region(ioport, ASC_IOADR_GAP);
c304ec94
MW		 11945 return 0;
11946}
11947
11948static struct isa_driver advansys_isa_driver = {
11949 .probe = advansys_isa_probe,
6f039790 11950 .remove = advansys_isa_remove,
c304ec94
MW		 11951 .driver = {
11952 .owner = THIS_MODULE,
01fbfe0b 11953 .name = DRV_NAME,
c304ec94
MW		 11954 },
11955};
11956
d361db48
MW		 11957/*
11958 * The VLB IRQ number is found in bits 2 to 4 of the CfgLsw. It decodes as:
11959 * 000: invalid
11960 * 001: 10
11961 * 010: 11
11962 * 011: 12
11963 * 100: invalid
11964 * 101: 14
11965 * 110: 15
11966 * 111: invalid
11967 */
6f039790 11968static unsigned int advansys_vlb_irq_no(PortAddr iop_base)
d361db48
MW		 11969{
11970 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
11971 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x07) + 9;
11972 if ((chip_irq < 10) || (chip_irq == 13) || (chip_irq > 15))
11973 return 0;
11974 return chip_irq;
11975}
11976
6f039790 11977static int advansys_vlb_probe(struct device *dev, unsigned int id)
c304ec94 11978{
d361db48 11979 int err = -ENODEV;
c304ec94
MW		 11980 PortAddr iop_base = _asc_def_iop_base[id];
11981 struct Scsi_Host *shost;
d361db48 11982 struct asc_board *board;
c304ec94 11983
01fbfe0b 11984 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
b352f923 11985 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
c304ec94
MW		 11986 return -ENODEV;
11987 }
b352f923 11988 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
c304ec94 11989 if (!AscFindSignature(iop_base))
d361db48 11990 goto release_region;
c304ec94
MW		 11991 /*
11992 * I don't think this condition can actually happen, but the old
11993 * driver did it, and the chances of finding a VLB setup in 2007
11994 * to do testing with is slight to none.
11995 */
11996 if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL)
d361db48 11997 goto release_region;
c304ec94 11998
d361db48
MW		 11999 err = -ENOMEM;
12000 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
c304ec94 12001 if (!shost)
d361db48
MW		 12002 goto release_region;
12003
d2411495 12004 board = shost_priv(shost);
d361db48
MW		 12005 board->irq = advansys_vlb_irq_no(iop_base);
12006 board->dev = dev;
12007
12008 err = advansys_board_found(shost, iop_base, ASC_IS_VL);
12009 if (err)
12010 goto free_host;
c304ec94
MW		 12011
12012 dev_set_drvdata(dev, shost);
12013 return 0;
12014
d361db48
MW		 12015 free_host:
12016 scsi_host_put(shost);
12017 release_region:
71f36115 12018 release_region(iop_base, ASC_IOADR_GAP);
c304ec94
MW		 12019 return -ENODEV;
12020}
12021
12022static struct isa_driver advansys_vlb_driver = {
12023 .probe = advansys_vlb_probe,
6f039790 12024 .remove = advansys_isa_remove,
c304ec94
MW		 12025 .driver = {
12026 .owner = THIS_MODULE,
b8e5152b 12027 .name = "advansys_vlb",
c304ec94
MW		 12028 },
12029};
12030
6f039790 12031static struct eisa_device_id advansys_eisa_table[] = {
b09e05a7
MW		 12032 { "ABP7401" },
12033 { "ABP7501" },
12034 { "" }
12035};
12036
12037MODULE_DEVICE_TABLE(eisa, advansys_eisa_table);
12038
12039/*
12040 * EISA is a little more tricky than PCI; each EISA device may have two
12041 * channels, and this driver is written to make each channel its own Scsi_Host
12042 */
12043struct eisa_scsi_data {
12044 struct Scsi_Host *host[2];
12045};
12046
d361db48
MW		 12047/*
12048 * The EISA IRQ number is found in bits 8 to 10 of the CfgLsw. It decodes as:
12049 * 000: 10
12050 * 001: 11
12051 * 010: 12
12052 * 011: invalid
12053 * 100: 14
12054 * 101: 15
12055 * 110: invalid
12056 * 111: invalid
12057 */
6f039790 12058static unsigned int advansys_eisa_irq_no(struct eisa_device *edev)
d361db48
MW		 12059{
12060 unsigned short cfg_lsw = inw(edev->base_addr + 0xc86);
12061 unsigned int chip_irq = ((cfg_lsw >> 8) & 0x07) + 10;
12062 if ((chip_irq == 13) || (chip_irq > 15))
12063 return 0;
12064 return chip_irq;
12065}
12066
6f039790 12067static int advansys_eisa_probe(struct device *dev)
b09e05a7 12068{
d361db48 12069 int i, ioport, irq = 0;
b09e05a7
MW		 12070 int err;
12071 struct eisa_device *edev = to_eisa_device(dev);
12072 struct eisa_scsi_data *data;
12073
12074 err = -ENOMEM;
12075 data = kzalloc(sizeof(*data), GFP_KERNEL);
12076 if (!data)
12077 goto fail;
12078 ioport = edev->base_addr + 0xc30;
12079
12080 err = -ENODEV;
12081 for (i = 0; i < 2; i++, ioport += 0x20) {
d361db48
MW		 12082 struct asc_board *board;
12083 struct Scsi_Host *shost;
01fbfe0b 12084 if (!request_region(ioport, ASC_IOADR_GAP, DRV_NAME)) {
71f36115
MW		 12085 printk(KERN_WARNING "Region %x-%x busy\n", ioport,
12086 ioport + ASC_IOADR_GAP - 1);
12087 continue;
12088 }
12089 if (!AscFindSignature(ioport)) {
12090 release_region(ioport, ASC_IOADR_GAP);
b09e05a7 12091 continue;
71f36115
MW		 12092 }
12093
b09e05a7
MW		 12094 /*
12095 * I don't know why we need to do this for EISA chips, but
12096 * not for any others. It looks to be equivalent to
12097 * AscGetChipCfgMsw, but I may have overlooked something,
12098 * so I'm not converting it until I get an EISA board to
12099 * test with.
12100 */
12101 inw(ioport + 4);
d361db48
MW		 12102
12103 if (!irq)
12104 irq = advansys_eisa_irq_no(edev);
12105
12106 err = -ENOMEM;
12107 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
12108 if (!shost)
12109 goto release_region;
12110
d2411495 12111 board = shost_priv(shost);
d361db48
MW		 12112 board->irq = irq;
12113 board->dev = dev;
12114
12115 err = advansys_board_found(shost, ioport, ASC_IS_EISA);
12116 if (!err) {
12117 data->host[i] = shost;
12118 continue;
71f36115 12119 }
b09e05a7 12120
d361db48
MW		 12121 scsi_host_put(shost);
12122 release_region:
12123 release_region(ioport, ASC_IOADR_GAP);
12124 break;
b09e05a7
MW		 12125 }
12126
d361db48
MW		 12127 if (err)
12128 goto free_data;
12129 dev_set_drvdata(dev, data);
12130 return 0;
12131
12132 free_data:
12133 kfree(data->host[0]);
12134 kfree(data->host[1]);
12135 kfree(data);
b09e05a7
MW		 12136 fail:
12137 return err;
12138}
12139
6f039790 12140static int advansys_eisa_remove(struct device *dev)
b09e05a7
MW		 12141{
12142 int i;
12143 struct eisa_scsi_data *data = dev_get_drvdata(dev);
12144
12145 for (i = 0; i < 2; i++) {
71f36115 12146 int ioport;
b09e05a7
MW		 12147 struct Scsi_Host *shost = data->host[i];
12148 if (!shost)
12149 continue;
71f36115 12150 ioport = shost->io_port;
b09e05a7 12151 advansys_release(shost);
71f36115 12152 release_region(ioport, ASC_IOADR_GAP);
b09e05a7
MW		 12153 }
12154
12155 kfree(data);
12156 return 0;
12157}
12158
12159static struct eisa_driver advansys_eisa_driver = {
12160 .id_table = advansys_eisa_table,
12161 .driver = {
01fbfe0b 12162 .name = DRV_NAME,
b09e05a7 12163 .probe = advansys_eisa_probe,
6f039790 12164 .remove = advansys_eisa_remove,
b09e05a7
MW		 12165 }
12166};
12167
2672ea86 12168/* PCI Devices supported by this driver */
6f039790 12169static struct pci_device_id advansys_pci_tbl[] = {
27c868c2
MW		 12170 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A,
12171 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12172 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940,
12173 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12174 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U,
12175 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12176 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW,
12177 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12178 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1,
12179 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12180 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1,
12181 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12182 {}
2672ea86 12183};
27c868c2 12184
2672ea86 12185MODULE_DEVICE_TABLE(pci, advansys_pci_tbl);
78e77d8b 12186
6f039790 12187static void advansys_set_latency(struct pci_dev *pdev)
9649af39
MW		 12188{
12189 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
12190 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
12191 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0);
12192 } else {
12193 u8 latency;
12194 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency);
12195 if (latency < 0x20)
12196 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
12197 }
12198}
12199
6f039790
GKH		 12200static int advansys_pci_probe(struct pci_dev *pdev,
12201 const struct pci_device_id *ent)
78e77d8b
MW		 12202{
12203 int err, ioport;
12204 struct Scsi_Host *shost;
d361db48 12205 struct asc_board *board;
78e77d8b
MW		 12206
12207 err = pci_enable_device(pdev);
12208 if (err)
12209 goto fail;
01fbfe0b 12210 err = pci_request_regions(pdev, DRV_NAME);
71f36115
MW		 12211 if (err)
12212 goto disable_device;
9649af39
MW		 12213 pci_set_master(pdev);
12214 advansys_set_latency(pdev);
78e77d8b 12215
d361db48 12216 err = -ENODEV;
78e77d8b 12217 if (pci_resource_len(pdev, 0) == 0)
d361db48 12218 goto release_region;
78e77d8b
MW		 12219
12220 ioport = pci_resource_start(pdev, 0);
78e77d8b 12221
d361db48
MW		 12222 err = -ENOMEM;
12223 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
78e77d8b 12224 if (!shost)
d361db48
MW		 12225 goto release_region;
12226
d2411495 12227 board = shost_priv(shost);
d361db48
MW		 12228 board->irq = pdev->irq;
12229 board->dev = &pdev->dev;
12230
12231 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW ||
12232 pdev->device == PCI_DEVICE_ID_38C0800_REV1 ||
12233 pdev->device == PCI_DEVICE_ID_38C1600_REV1) {
12234 board->flags |= ASC_IS_WIDE_BOARD;
12235 }
12236
12237 err = advansys_board_found(shost, ioport, ASC_IS_PCI);
12238 if (err)
12239 goto free_host;
78e77d8b
MW		 12240
12241 pci_set_drvdata(pdev, shost);
12242 return 0;
12243
d361db48
MW		 12244 free_host:
12245 scsi_host_put(shost);
12246 release_region:
71f36115
MW		 12247 pci_release_regions(pdev);
12248 disable_device:
78e77d8b
MW		 12249 pci_disable_device(pdev);
12250 fail:
12251 return err;
12252}
12253
6f039790 12254static void advansys_pci_remove(struct pci_dev *pdev)
78e77d8b
MW		 12255{
12256 advansys_release(pci_get_drvdata(pdev));
71f36115 12257 pci_release_regions(pdev);
78e77d8b
MW		 12258 pci_disable_device(pdev);
12259}
12260
12261static struct pci_driver advansys_pci_driver = {
01fbfe0b 12262 .name = DRV_NAME,
78e77d8b
MW		 12263 .id_table = advansys_pci_tbl,
12264 .probe = advansys_pci_probe,
6f039790 12265 .remove = advansys_pci_remove,
78e77d8b 12266};
8c6af9e1 12267
8dfb5379
MW		 12268static int __init advansys_init(void)
12269{
c304ec94 12270 int error;
b09e05a7 12271
c304ec94
MW		 12272 error = isa_register_driver(&advansys_isa_driver,
12273 ASC_IOADR_TABLE_MAX_IX);
78e77d8b
MW		 12274 if (error)
12275 goto fail;
8dfb5379 12276
c304ec94
MW		 12277 error = isa_register_driver(&advansys_vlb_driver,
12278 ASC_IOADR_TABLE_MAX_IX);
12279 if (error)
12280 goto unregister_isa;
12281
12282 error = eisa_driver_register(&advansys_eisa_driver);
12283 if (error)
12284 goto unregister_vlb;
12285
b09e05a7
MW		 12286 error = pci_register_driver(&advansys_pci_driver);
12287 if (error)
12288 goto unregister_eisa;
12289
8dfb5379 12290 return 0;
78e77d8b 12291
b09e05a7
MW		 12292 unregister_eisa:
12293 eisa_driver_unregister(&advansys_eisa_driver);
c304ec94
MW		 12294 unregister_vlb:
12295 isa_unregister_driver(&advansys_vlb_driver);
12296 unregister_isa:
12297 isa_unregister_driver(&advansys_isa_driver);
78e77d8b 12298 fail:
78e77d8b 12299 return error;
8dfb5379
MW		 12300}
12301
12302static void __exit advansys_exit(void)
12303{
78e77d8b 12304 pci_unregister_driver(&advansys_pci_driver);
b09e05a7 12305 eisa_driver_unregister(&advansys_eisa_driver);
c304ec94
MW		 12306 isa_unregister_driver(&advansys_vlb_driver);
12307 isa_unregister_driver(&advansys_isa_driver);
8dfb5379
MW		 12308}
12309
12310module_init(advansys_init);
12311module_exit(advansys_exit);
12312
8c6af9e1 12313MODULE_LICENSE("GPL");
989bb5f5
JSR		 12314MODULE_FIRMWARE("advansys/mcode.bin");
12315MODULE_FIRMWARE("advansys/3550.bin");
12316MODULE_FIRMWARE("advansys/38C0800.bin");
12317MODULE_FIRMWARE("advansys/38C1600.bin");
Linux kernel - Deliverables
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