projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] libata: kill @verbose from ata_reset_fn_t
[deliverable/linux.git] / drivers / scsi / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/sched.h>
87507cfd 43#include <linux/dma-mapping.h>
a9524a76 44#include <linux/device.h>
1da177e4 45#include <scsi/scsi_host.h>
193515d5 46#include <scsi/scsi_cmnd.h>
1da177e4
LT		 47#include <linux/libata.h>
48#include <asm/io.h>
49
50#define DRV_NAME "ahci"
af64371a 51#define DRV_VERSION "1.3"
1da177e4
LT		 52
53
54enum {
55 AHCI_PCI_BAR = 5,
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
59 AHCI_CMD_SLOT_SZ = 32 * 32,
60 AHCI_RX_FIS_SZ = 256,
61 AHCI_CMD_TBL_HDR = 0x80,
a0ea7328 62 AHCI_CMD_TBL_CDB = 0x40,
1da177e4
LT		 63 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16),
64 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ +
65 AHCI_RX_FIS_SZ,
66 AHCI_IRQ_ON_SG = (1 << 31),
67 AHCI_CMD_ATAPI = (1 << 5),
68 AHCI_CMD_WRITE = (1 << 6),
4b10e559 69 AHCI_CMD_PREFETCH = (1 << 7),
22b49985
TH		 70 AHCI_CMD_RESET = (1 << 8),
71 AHCI_CMD_CLR_BUSY = (1 << 10),
1da177e4
LT		 72
73 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
74
75 board_ahci = 0,
76
77 /* global controller registers */
78 HOST_CAP = 0x00, /* host capabilities */
79 HOST_CTL = 0x04, /* global host control */
80 HOST_IRQ_STAT = 0x08, /* interrupt status */
81 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
82 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
83
84 /* HOST_CTL bits */
85 HOST_RESET = (1 << 0), /* reset controller; self-clear */
86 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
87 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
88
89 /* HOST_CAP bits */
90 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
22b49985 91 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
1da177e4
LT		 92
93 /* registers for each SATA port */
94 PORT_LST_ADDR = 0x00, /* command list DMA addr */
95 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
96 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
97 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
98 PORT_IRQ_STAT = 0x10, /* interrupt status */
99 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
100 PORT_CMD = 0x18, /* port command */
101 PORT_TFDATA = 0x20, /* taskfile data */
102 PORT_SIG = 0x24, /* device TF signature */
103 PORT_CMD_ISSUE = 0x38, /* command issue */
104 PORT_SCR = 0x28, /* SATA phy register block */
105 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
106 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
107 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
108 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
109
110 /* PORT_IRQ_{STAT,MASK} bits */
111 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
112 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
113 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
114 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
115 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
116 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
117 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
118 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
119
120 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
121 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
122 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
123 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
124 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
125 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
126 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
127 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
128 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
129
130 PORT_IRQ_FATAL = PORT_IRQ_TF_ERR |
131 PORT_IRQ_HBUS_ERR |
132 PORT_IRQ_HBUS_DATA_ERR |
133 PORT_IRQ_IF_ERR,
134 DEF_PORT_IRQ = PORT_IRQ_FATAL | PORT_IRQ_PHYRDY |
135 PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE |
136 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS |
137 PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS |
138 PORT_IRQ_D2H_REG_FIS,
139
140 /* PORT_CMD bits */
02eaa666 141 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
1da177e4
LT		 142 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
143 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
144 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
22b49985 145 PORT_CMD_CLO = (1 << 3), /* Command list override */
1da177e4
LT		 146 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
147 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
148 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
149
150 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
151 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
152 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
4b0060f4
JG		 153
154 /* hpriv->flags bits */
155 AHCI_FLAG_MSI = (1 << 0),
1da177e4
LT		 156};
157
158struct ahci_cmd_hdr {
159 u32 opts;
160 u32 status;
161 u32 tbl_addr;
162 u32 tbl_addr_hi;
163 u32 reserved[4];
164};
165
166struct ahci_sg {
167 u32 addr;
168 u32 addr_hi;
169 u32 reserved;
170 u32 flags_size;
171};
172
173struct ahci_host_priv {
174 unsigned long flags;
175 u32 cap; /* cache of HOST_CAP register */
176 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
177};
178
179struct ahci_port_priv {
180 struct ahci_cmd_hdr *cmd_slot;
181 dma_addr_t cmd_slot_dma;
182 void *cmd_tbl;
183 dma_addr_t cmd_tbl_dma;
184 struct ahci_sg *cmd_tbl_sg;
185 void *rx_fis;
186 dma_addr_t rx_fis_dma;
187};
188
189static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
190static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
191static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
9a3d9eb0 192static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
1da177e4 193static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
4bd00f6a 194static int ahci_probe_reset(struct ata_port *ap, unsigned int *classes);
1da177e4
LT		 195static void ahci_irq_clear(struct ata_port *ap);
196static void ahci_eng_timeout(struct ata_port *ap);
197static int ahci_port_start(struct ata_port *ap);
198static void ahci_port_stop(struct ata_port *ap);
1da177e4
LT		 199static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
200static void ahci_qc_prep(struct ata_queued_cmd *qc);
201static u8 ahci_check_status(struct ata_port *ap);
1da177e4 202static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc);
907f4678 203static void ahci_remove_one (struct pci_dev *pdev);
1da177e4 204
193515d5 205static struct scsi_host_template ahci_sht = {
1da177e4
LT		 206 .module = THIS_MODULE,
207 .name = DRV_NAME,
208 .ioctl = ata_scsi_ioctl,
209 .queuecommand = ata_scsi_queuecmd,
1da177e4
LT		 210 .can_queue = ATA_DEF_QUEUE,
211 .this_id = ATA_SHT_THIS_ID,
212 .sg_tablesize = AHCI_MAX_SG,
1da177e4
LT		 213 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
214 .emulated = ATA_SHT_EMULATED,
215 .use_clustering = AHCI_USE_CLUSTERING,
216 .proc_name = DRV_NAME,
217 .dma_boundary = AHCI_DMA_BOUNDARY,
218 .slave_configure = ata_scsi_slave_config,
219 .bios_param = ata_std_bios_param,
1da177e4
LT		 220};
221
057ace5e 222static const struct ata_port_operations ahci_ops = {
1da177e4
LT		 223 .port_disable = ata_port_disable,
224
225 .check_status = ahci_check_status,
226 .check_altstatus = ahci_check_status,
1da177e4
LT		 227 .dev_select = ata_noop_dev_select,
228
229 .tf_read = ahci_tf_read,
230
4bd00f6a 231 .probe_reset = ahci_probe_reset,
1da177e4
LT		 232
233 .qc_prep = ahci_qc_prep,
234 .qc_issue = ahci_qc_issue,
235
236 .eng_timeout = ahci_eng_timeout,
237
238 .irq_handler = ahci_interrupt,
239 .irq_clear = ahci_irq_clear,
240
241 .scr_read = ahci_scr_read,
242 .scr_write = ahci_scr_write,
243
244 .port_start = ahci_port_start,
245 .port_stop = ahci_port_stop,
1da177e4
LT		 246};
247
98ac62de 248static const struct ata_port_info ahci_port_info[] = {
1da177e4
LT		 249 /* board_ahci */
250 {
251 .sht = &ahci_sht,
252 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
4bd00f6a 253 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
7da79312 254 .pio_mask = 0x1f, /* pio0-4 */
1da177e4
LT		 255 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
256 .port_ops = &ahci_ops,
257 },
258};
259
3b7d697d 260static const struct pci_device_id ahci_pci_tbl[] = {
1da177e4
LT		 261 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
262 board_ahci }, /* ICH6 */
263 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
264 board_ahci }, /* ICH6M */
265 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
266 board_ahci }, /* ICH7 */
267 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
268 board_ahci }, /* ICH7M */
269 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
270 board_ahci }, /* ICH7R */
271 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
272 board_ahci }, /* ULi M5288 */
680d3235
JG		 273 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
274 board_ahci }, /* ESB2 */
275 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
276 board_ahci }, /* ESB2 */
277 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
278 board_ahci }, /* ESB2 */
3db368f7
JG		 279 { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
280 board_ahci }, /* ICH7-M DH */
f285757c
JG		 281 { PCI_VENDOR_ID_INTEL, 0x2821, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
282 board_ahci }, /* ICH8 */
283 { PCI_VENDOR_ID_INTEL, 0x2822, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
284 board_ahci }, /* ICH8 */
285 { PCI_VENDOR_ID_INTEL, 0x2824, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
286 board_ahci }, /* ICH8 */
287 { PCI_VENDOR_ID_INTEL, 0x2829, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
288 board_ahci }, /* ICH8M */
289 { PCI_VENDOR_ID_INTEL, 0x282a, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
290 board_ahci }, /* ICH8M */
bd12097c
JG		 291 { 0x197b, 0x2360, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
292 board_ahci }, /* JMicron JMB360 */
9220a2d0
JG		 293 { 0x197b, 0x2363, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
294 board_ahci }, /* JMicron JMB363 */
8b316a39
JG		 295 { PCI_VENDOR_ID_ATI, 0x4380, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
296 board_ahci }, /* ATI SB600 non-raid */
297 { PCI_VENDOR_ID_ATI, 0x4381, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
298 board_ahci }, /* ATI SB600 raid */
1da177e4
LT		 299 { } /* terminate list */
300};
301
302
303static struct pci_driver ahci_pci_driver = {
304 .name = DRV_NAME,
305 .id_table = ahci_pci_tbl,
306 .probe = ahci_init_one,
907f4678 307 .remove = ahci_remove_one,
1da177e4
LT		 308};
309
310
311static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
312{
313 return base + 0x100 + (port * 0x80);
314}
315
ea6ba10b 316static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
1da177e4 317{
ea6ba10b 318 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
1da177e4
LT		 319}
320
1da177e4
LT		 321static int ahci_port_start(struct ata_port *ap)
322{
323 struct device *dev = ap->host_set->dev;
324 struct ahci_host_priv *hpriv = ap->host_set->private_data;
325 struct ahci_port_priv *pp;
ea6ba10b
JG		 326 void __iomem *mmio = ap->host_set->mmio_base;
327 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
328 void *mem;
1da177e4 329 dma_addr_t mem_dma;
6037d6bb 330 int rc;
1da177e4 331
1da177e4 332 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
0a139e79
TH		 333 if (!pp)
334 return -ENOMEM;
1da177e4
LT		 335 memset(pp, 0, sizeof(*pp));
336
6037d6bb
JG		 337 rc = ata_pad_alloc(ap, dev);
338 if (rc) {
cedc9a47 339 kfree(pp);
6037d6bb 340 return rc;
cedc9a47
JG		 341 }
342
1da177e4
LT		 343 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
344 if (!mem) {
6037d6bb 345 ata_pad_free(ap, dev);
0a139e79
TH		 346 kfree(pp);
347 return -ENOMEM;
1da177e4
LT		 348 }
349 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
350
351 /*
352 * First item in chunk of DMA memory: 32-slot command table,
353 * 32 bytes each in size
354 */
355 pp->cmd_slot = mem;
356 pp->cmd_slot_dma = mem_dma;
357
358 mem += AHCI_CMD_SLOT_SZ;
359 mem_dma += AHCI_CMD_SLOT_SZ;
360
361 /*
362 * Second item: Received-FIS area
363 */
364 pp->rx_fis = mem;
365 pp->rx_fis_dma = mem_dma;
366
367 mem += AHCI_RX_FIS_SZ;
368 mem_dma += AHCI_RX_FIS_SZ;
369
370 /*
371 * Third item: data area for storing a single command
372 * and its scatter-gather table
373 */
374 pp->cmd_tbl = mem;
375 pp->cmd_tbl_dma = mem_dma;
376
377 pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR;
378
379 ap->private_data = pp;
380
381 if (hpriv->cap & HOST_CAP_64)
382 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
383 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
384 readl(port_mmio + PORT_LST_ADDR); /* flush */
385
386 if (hpriv->cap & HOST_CAP_64)
387 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
388 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
389 readl(port_mmio + PORT_FIS_ADDR); /* flush */
390
391 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
392 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
393 PORT_CMD_START, port_mmio + PORT_CMD);
394 readl(port_mmio + PORT_CMD); /* flush */
395
396 return 0;
1da177e4
LT		 397}
398
399
400static void ahci_port_stop(struct ata_port *ap)
401{
402 struct device *dev = ap->host_set->dev;
403 struct ahci_port_priv *pp = ap->private_data;
ea6ba10b
JG		 404 void __iomem *mmio = ap->host_set->mmio_base;
405 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1da177e4
LT		 406 u32 tmp;
407
408 tmp = readl(port_mmio + PORT_CMD);
409 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
410 writel(tmp, port_mmio + PORT_CMD);
411 readl(port_mmio + PORT_CMD); /* flush */
412
413 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
414 * this is slightly incorrect.
415 */
416 msleep(500);
417
418 ap->private_data = NULL;
419 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
420 pp->cmd_slot, pp->cmd_slot_dma);
6037d6bb 421 ata_pad_free(ap, dev);
1da177e4 422 kfree(pp);
1da177e4
LT		 423}
424
425static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
426{
427 unsigned int sc_reg;
428
429 switch (sc_reg_in) {
430 case SCR_STATUS: sc_reg = 0; break;
431 case SCR_CONTROL: sc_reg = 1; break;
432 case SCR_ERROR: sc_reg = 2; break;
433 case SCR_ACTIVE: sc_reg = 3; break;
434 default:
435 return 0xffffffffU;
436 }
437
1e4f2a96 438 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT		 439}
440
441
442static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
443 u32 val)
444{
445 unsigned int sc_reg;
446
447 switch (sc_reg_in) {
448 case SCR_STATUS: sc_reg = 0; break;
449 case SCR_CONTROL: sc_reg = 1; break;
450 case SCR_ERROR: sc_reg = 2; break;
451 case SCR_ACTIVE: sc_reg = 3; break;
452 default:
453 return;
454 }
455
1e4f2a96 456 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT		 457}
458
7c76d1e8
TH		 459static int ahci_stop_engine(struct ata_port *ap)
460{
461 void __iomem *mmio = ap->host_set->mmio_base;
462 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
463 int work;
464 u32 tmp;
465
466 tmp = readl(port_mmio + PORT_CMD);
467 tmp &= ~PORT_CMD_START;
468 writel(tmp, port_mmio + PORT_CMD);
469
470 /* wait for engine to stop. TODO: this could be
471 * as long as 500 msec
472 */
473 work = 1000;
474 while (work-- > 0) {
475 tmp = readl(port_mmio + PORT_CMD);
476 if ((tmp & PORT_CMD_LIST_ON) == 0)
477 return 0;
478 udelay(10);
479 }
480
481 return -EIO;
482}
483
484static void ahci_start_engine(struct ata_port *ap)
485{
486 void __iomem *mmio = ap->host_set->mmio_base;
487 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
488 u32 tmp;
489
490 tmp = readl(port_mmio + PORT_CMD);
491 tmp |= PORT_CMD_START;
492 writel(tmp, port_mmio + PORT_CMD);
493 readl(port_mmio + PORT_CMD); /* flush */
494}
495
422b7595 496static unsigned int ahci_dev_classify(struct ata_port *ap)
1da177e4
LT		 497{
498 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
499 struct ata_taskfile tf;
422b7595
TH		 500 u32 tmp;
501
502 tmp = readl(port_mmio + PORT_SIG);
503 tf.lbah = (tmp >> 24) & 0xff;
504 tf.lbam = (tmp >> 16) & 0xff;
505 tf.lbal = (tmp >> 8) & 0xff;
506 tf.nsect = (tmp) & 0xff;
507
508 return ata_dev_classify(&tf);
509}
510
a42fc659 511static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, u32 opts)
cc9278ed 512{
cc9278ed
TH		 513 pp->cmd_slot[0].opts = cpu_to_le32(opts);
514 pp->cmd_slot[0].status = 0;
515 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
516 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
517}
518
4658f79b
TH		 519static int ahci_poll_register(void __iomem *reg, u32 mask, u32 val,
520 unsigned long interval_msec,
521 unsigned long timeout_msec)
522{
523 unsigned long timeout;
524 u32 tmp;
525
526 timeout = jiffies + (timeout_msec * HZ) / 1000;
527 do {
528 tmp = readl(reg);
529 if ((tmp & mask) == val)
530 return 0;
531 msleep(interval_msec);
532 } while (time_before(jiffies, timeout));
533
534 return -1;
535}
536
2bf2cb26 537static int ahci_softreset(struct ata_port *ap, unsigned int *class)
4658f79b
TH		 538{
539 struct ahci_host_priv *hpriv = ap->host_set->private_data;
540 struct ahci_port_priv *pp = ap->private_data;
541 void __iomem *mmio = ap->host_set->mmio_base;
542 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
543 const u32 cmd_fis_len = 5; /* five dwords */
544 const char *reason = NULL;
545 struct ata_taskfile tf;
546 u8 *fis;
547 int rc;
548
549 DPRINTK("ENTER\n");
550
c2a65852
TH		 551 if (!sata_dev_present(ap)) {
552 DPRINTK("PHY reports no device\n");
553 *class = ATA_DEV_NONE;
554 return 0;
555 }
556
4658f79b
TH		 557 /* prepare for SRST (AHCI-1.1 10.4.1) */
558 rc = ahci_stop_engine(ap);
559 if (rc) {
560 reason = "failed to stop engine";
561 goto fail_restart;
562 }
563
564 /* check BUSY/DRQ, perform Command List Override if necessary */
565 ahci_tf_read(ap, &tf);
566 if (tf.command & (ATA_BUSY | ATA_DRQ)) {
567 u32 tmp;
568
569 if (!(hpriv->cap & HOST_CAP_CLO)) {
570 rc = -EIO;
571 reason = "port busy but no CLO";
572 goto fail_restart;
573 }
574
575 tmp = readl(port_mmio + PORT_CMD);
576 tmp |= PORT_CMD_CLO;
577 writel(tmp, port_mmio + PORT_CMD);
578 readl(port_mmio + PORT_CMD); /* flush */
579
580 if (ahci_poll_register(port_mmio + PORT_CMD, PORT_CMD_CLO, 0x0,
581 1, 500)) {
582 rc = -EIO;
583 reason = "CLO failed";
584 goto fail_restart;
585 }
586 }
587
588 /* restart engine */
589 ahci_start_engine(ap);
590
591 ata_tf_init(ap, &tf, 0);
592 fis = pp->cmd_tbl;
593
594 /* issue the first D2H Register FIS */
595 ahci_fill_cmd_slot(pp, cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
596
597 tf.ctl |= ATA_SRST;
598 ata_tf_to_fis(&tf, fis, 0);
599 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
600
601 writel(1, port_mmio + PORT_CMD_ISSUE);
602 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
603
604 if (ahci_poll_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x0, 1, 500)) {
605 rc = -EIO;
606 reason = "1st FIS failed";
607 goto fail;
608 }
609
610 /* spec says at least 5us, but be generous and sleep for 1ms */
611 msleep(1);
612
613 /* issue the second D2H Register FIS */
614 ahci_fill_cmd_slot(pp, cmd_fis_len);
615
616 tf.ctl &= ~ATA_SRST;
617 ata_tf_to_fis(&tf, fis, 0);
618 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
619
620 writel(1, port_mmio + PORT_CMD_ISSUE);
621 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
622
623 /* spec mandates ">= 2ms" before checking status.
624 * We wait 150ms, because that was the magic delay used for
625 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
626 * between when the ATA command register is written, and then
627 * status is checked. Because waiting for "a while" before
628 * checking status is fine, post SRST, we perform this magic
629 * delay here as well.
630 */
631 msleep(150);
632
633 *class = ATA_DEV_NONE;
634 if (sata_dev_present(ap)) {
635 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
636 rc = -EIO;
637 reason = "device not ready";
638 goto fail;
639 }
640 *class = ahci_dev_classify(ap);
641 }
642
643 DPRINTK("EXIT, class=%u\n", *class);
644 return 0;
645
646 fail_restart:
647 ahci_start_engine(ap);
648 fail:
2bf2cb26
TH		 649 printk(KERN_ERR "ata%u: softreset failed (%s)\n",
650 ap->id, reason);
4658f79b
TH		 651 return rc;
652}
653
2bf2cb26 654static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
422b7595 655{
4bd00f6a
TH		 656 int rc;
657
658 DPRINTK("ENTER\n");
1da177e4 659
e0bfd149 660 ahci_stop_engine(ap);
2bf2cb26 661 rc = sata_std_hardreset(ap, class);
e0bfd149 662 ahci_start_engine(ap);
1da177e4 663
4bd00f6a
TH		 664 if (rc == 0)
665 *class = ahci_dev_classify(ap);
666 if (*class == ATA_DEV_UNKNOWN)
667 *class = ATA_DEV_NONE;
1da177e4 668
4bd00f6a
TH		 669 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
670 return rc;
671}
672
673static void ahci_postreset(struct ata_port *ap, unsigned int *class)
674{
675 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
676 u32 new_tmp, tmp;
677
678 ata_std_postreset(ap, class);
02eaa666
JG		 679
680 /* Make sure port's ATAPI bit is set appropriately */
681 new_tmp = tmp = readl(port_mmio + PORT_CMD);
4bd00f6a 682 if (*class == ATA_DEV_ATAPI)
02eaa666
JG		 683 new_tmp |= PORT_CMD_ATAPI;
684 else
685 new_tmp &= ~PORT_CMD_ATAPI;
686 if (new_tmp != tmp) {
687 writel(new_tmp, port_mmio + PORT_CMD);
688 readl(port_mmio + PORT_CMD); /* flush */
689 }
1da177e4
LT		 690}
691
4bd00f6a
TH		 692static int ahci_probe_reset(struct ata_port *ap, unsigned int *classes)
693{
4658f79b
TH		 694 return ata_drive_probe_reset(ap, ata_std_probeinit,
695 ahci_softreset, ahci_hardreset,
4bd00f6a
TH		 696 ahci_postreset, classes);
697}
698
1da177e4
LT		 699static u8 ahci_check_status(struct ata_port *ap)
700{
1e4f2a96 701 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1da177e4
LT		 702
703 return readl(mmio + PORT_TFDATA) & 0xFF;
704}
705
1da177e4
LT		 706static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
707{
708 struct ahci_port_priv *pp = ap->private_data;
709 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
710
711 ata_tf_from_fis(d2h_fis, tf);
712}
713
828d09de 714static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc)
1da177e4
LT		 715{
716 struct ahci_port_priv *pp = qc->ap->private_data;
cedc9a47
JG		 717 struct scatterlist *sg;
718 struct ahci_sg *ahci_sg;
828d09de 719 unsigned int n_sg = 0;
1da177e4
LT		 720
721 VPRINTK("ENTER\n");
722
723 /*
724 * Next, the S/G list.
725 */
cedc9a47
JG		 726 ahci_sg = pp->cmd_tbl_sg;
727 ata_for_each_sg(sg, qc) {
728 dma_addr_t addr = sg_dma_address(sg);
729 u32 sg_len = sg_dma_len(sg);
730
731 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
732 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
733 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
828d09de 734
cedc9a47 735 ahci_sg++;
828d09de 736 n_sg++;
1da177e4 737 }
828d09de
JG		 738
739 return n_sg;
1da177e4
LT		 740}
741
742static void ahci_qc_prep(struct ata_queued_cmd *qc)
743{
a0ea7328
JG		 744 struct ata_port *ap = qc->ap;
745 struct ahci_port_priv *pp = ap->private_data;
cc9278ed 746 int is_atapi = is_atapi_taskfile(&qc->tf);
1da177e4
LT		 747 u32 opts;
748 const u32 cmd_fis_len = 5; /* five dwords */
828d09de 749 unsigned int n_elem;
1da177e4 750
1da177e4
LT		 751 /*
752 * Fill in command table information. First, the header,
753 * a SATA Register - Host to Device command FIS.
754 */
755 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
cc9278ed 756 if (is_atapi) {
a0ea7328 757 memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
6e7846e9
TH		 758 memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb,
759 qc->dev->cdb_len);
a0ea7328 760 }
1da177e4 761
cc9278ed
TH		 762 n_elem = 0;
763 if (qc->flags & ATA_QCFLAG_DMAMAP)
764 n_elem = ahci_fill_sg(qc);
1da177e4 765
cc9278ed
TH		 766 /*
767 * Fill in command slot information.
768 */
769 opts = cmd_fis_len | n_elem << 16;
770 if (qc->tf.flags & ATA_TFLAG_WRITE)
771 opts |= AHCI_CMD_WRITE;
772 if (is_atapi)
4b10e559 773 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
828d09de 774
a42fc659 775 ahci_fill_cmd_slot(pp, opts);
1da177e4
LT		 776}
777
c2cd76ff 778static void ahci_restart_port(struct ata_port *ap, u32 irq_stat)
1da177e4 779{
ea6ba10b
JG		 780 void __iomem *mmio = ap->host_set->mmio_base;
781 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1da177e4 782 u32 tmp;
1da177e4 783
c2cd76ff
JG		 784 if ((ap->device[0].class != ATA_DEV_ATAPI) ||
785 ((irq_stat & PORT_IRQ_TF_ERR) == 0))
786 printk(KERN_WARNING "ata%u: port reset, "
787 "p_is %x is %x pis %x cmd %x tf %x ss %x se %x\n",
788 ap->id,
789 irq_stat,
790 readl(mmio + HOST_IRQ_STAT),
791 readl(port_mmio + PORT_IRQ_STAT),
792 readl(port_mmio + PORT_CMD),
793 readl(port_mmio + PORT_TFDATA),
794 readl(port_mmio + PORT_SCR_STAT),
795 readl(port_mmio + PORT_SCR_ERR));
9f68a248 796
1da177e4 797 /* stop DMA */
7c76d1e8 798 ahci_stop_engine(ap);
1da177e4
LT		 799
800 /* clear SATA phy error, if any */
801 tmp = readl(port_mmio + PORT_SCR_ERR);
802 writel(tmp, port_mmio + PORT_SCR_ERR);
803
804 /* if DRQ/BSY is set, device needs to be reset.
805 * if so, issue COMRESET
806 */
807 tmp = readl(port_mmio + PORT_TFDATA);
808 if (tmp & (ATA_BUSY | ATA_DRQ)) {
809 writel(0x301, port_mmio + PORT_SCR_CTL);
810 readl(port_mmio + PORT_SCR_CTL); /* flush */
811 udelay(10);
812 writel(0x300, port_mmio + PORT_SCR_CTL);
813 readl(port_mmio + PORT_SCR_CTL); /* flush */
814 }
815
816 /* re-start DMA */
7c76d1e8 817 ahci_start_engine(ap);
1da177e4
LT		 818}
819
820static void ahci_eng_timeout(struct ata_port *ap)
821{
b8f6153e 822 struct ata_host_set *host_set = ap->host_set;
ea6ba10b
JG		 823 void __iomem *mmio = host_set->mmio_base;
824 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1da177e4 825 struct ata_queued_cmd *qc;
b8f6153e 826 unsigned long flags;
1da177e4 827
9f68a248 828 printk(KERN_WARNING "ata%u: handling error/timeout\n", ap->id);
1da177e4 829
b8f6153e
JG		 830 spin_lock_irqsave(&host_set->lock, flags);
831
f6379020 832 ahci_restart_port(ap, readl(port_mmio + PORT_IRQ_STAT));
1da177e4 833 qc = ata_qc_from_tag(ap, ap->active_tag);
f6379020 834 qc->err_mask |= AC_ERR_TIMEOUT;
1da177e4 835
b8f6153e 836 spin_unlock_irqrestore(&host_set->lock, flags);
a72ec4ce 837
f6379020 838 ata_eh_qc_complete(qc);
1da177e4
LT		 839}
840
841static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
842{
ea6ba10b
JG		 843 void __iomem *mmio = ap->host_set->mmio_base;
844 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1da177e4
LT		 845 u32 status, serr, ci;
846
847 serr = readl(port_mmio + PORT_SCR_ERR);
848 writel(serr, port_mmio + PORT_SCR_ERR);
849
850 status = readl(port_mmio + PORT_IRQ_STAT);
851 writel(status, port_mmio + PORT_IRQ_STAT);
852
853 ci = readl(port_mmio + PORT_CMD_ISSUE);
854 if (likely((ci & 0x1) == 0)) {
855 if (qc) {
beec7dbc 856 WARN_ON(qc->err_mask);
a22e2eb0 857 ata_qc_complete(qc);
1da177e4
LT		 858 qc = NULL;
859 }
860 }
861
862 if (status & PORT_IRQ_FATAL) {
ad36d1a5
JG		 863 unsigned int err_mask;
864 if (status & PORT_IRQ_TF_ERR)
865 err_mask = AC_ERR_DEV;
866 else if (status & PORT_IRQ_IF_ERR)
867 err_mask = AC_ERR_ATA_BUS;
868 else
869 err_mask = AC_ERR_HOST_BUS;
870
9f68a248 871 /* command processing has stopped due to error; restart */
c2cd76ff 872 ahci_restart_port(ap, status);
9f68a248 873
a22e2eb0 874 if (qc) {
284b6481 875 qc->err_mask |= err_mask;
a22e2eb0
AL		 876 ata_qc_complete(qc);
877 }
1da177e4
LT		 878 }
879
880 return 1;
881}
882
883static void ahci_irq_clear(struct ata_port *ap)
884{
885 /* TODO */
886}
887
888static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
889{
890 struct ata_host_set *host_set = dev_instance;
891 struct ahci_host_priv *hpriv;
892 unsigned int i, handled = 0;
ea6ba10b 893 void __iomem *mmio;
1da177e4
LT		 894 u32 irq_stat, irq_ack = 0;
895
896 VPRINTK("ENTER\n");
897
898 hpriv = host_set->private_data;
899 mmio = host_set->mmio_base;
900
901 /* sigh. 0xffffffff is a valid return from h/w */
902 irq_stat = readl(mmio + HOST_IRQ_STAT);
903 irq_stat &= hpriv->port_map;
904 if (!irq_stat)
905 return IRQ_NONE;
906
907 spin_lock(&host_set->lock);
908
909 for (i = 0; i < host_set->n_ports; i++) {
910 struct ata_port *ap;
1da177e4 911
67846b30
JG		 912 if (!(irq_stat & (1 << i)))
913 continue;
914
1da177e4 915 ap = host_set->ports[i];
67846b30 916 if (ap) {
1da177e4
LT		 917 struct ata_queued_cmd *qc;
918 qc = ata_qc_from_tag(ap, ap->active_tag);
67846b30 919 if (!ahci_host_intr(ap, qc))
6971ed1f
TH		 920 if (ata_ratelimit())
921 dev_printk(KERN_WARNING, host_set->dev,
a9524a76
JG		 922 "unhandled interrupt on port %u\n",
923 i);
67846b30
JG		 924
925 VPRINTK("port %u\n", i);
926 } else {
927 VPRINTK("port %u (no irq)\n", i);
6971ed1f
TH		 928 if (ata_ratelimit())
929 dev_printk(KERN_WARNING, host_set->dev,
a9524a76 930 "interrupt on disabled port %u\n", i);
1da177e4 931 }
67846b30
JG		 932
933 irq_ack |= (1 << i);
1da177e4
LT		 934 }
935
936 if (irq_ack) {
937 writel(irq_ack, mmio + HOST_IRQ_STAT);
938 handled = 1;
939 }
940
941 spin_unlock(&host_set->lock);
942
943 VPRINTK("EXIT\n");
944
945 return IRQ_RETVAL(handled);
946}
947
9a3d9eb0 948static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 949{
950 struct ata_port *ap = qc->ap;
ea6ba10b 951 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1da177e4 952
1da177e4
LT		 953 writel(1, port_mmio + PORT_CMD_ISSUE);
954 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
955
956 return 0;
957}
958
959static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
960 unsigned int port_idx)
961{
962 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
963 base = ahci_port_base_ul(base, port_idx);
964 VPRINTK("base now==0x%lx\n", base);
965
966 port->cmd_addr = base;
967 port->scr_addr = base + PORT_SCR;
968
969 VPRINTK("EXIT\n");
970}
971
972static int ahci_host_init(struct ata_probe_ent *probe_ent)
973{
974 struct ahci_host_priv *hpriv = probe_ent->private_data;
975 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
976 void __iomem *mmio = probe_ent->mmio_base;
977 u32 tmp, cap_save;
1da177e4
LT		 978 unsigned int i, j, using_dac;
979 int rc;
980 void __iomem *port_mmio;
981
982 cap_save = readl(mmio + HOST_CAP);
983 cap_save &= ( (1<<28) | (1<<17) );
984 cap_save |= (1 << 27);
985
986 /* global controller reset */
987 tmp = readl(mmio + HOST_CTL);
988 if ((tmp & HOST_RESET) == 0) {
989 writel(tmp | HOST_RESET, mmio + HOST_CTL);
990 readl(mmio + HOST_CTL); /* flush */
991 }
992
993 /* reset must complete within 1 second, or
994 * the hardware should be considered fried.
995 */
996 ssleep(1);
997
998 tmp = readl(mmio + HOST_CTL);
999 if (tmp & HOST_RESET) {
a9524a76
JG		 1000 dev_printk(KERN_ERR, &pdev->dev,
1001 "controller reset failed (0x%x)\n", tmp);
1da177e4
LT		 1002 return -EIO;
1003 }
1004
1005 writel(HOST_AHCI_EN, mmio + HOST_CTL);
1006 (void) readl(mmio + HOST_CTL); /* flush */
1007 writel(cap_save, mmio + HOST_CAP);
1008 writel(0xf, mmio + HOST_PORTS_IMPL);
1009 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
1010
bd12097c
JG		 1011 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1012 u16 tmp16;
1013
1014 pci_read_config_word(pdev, 0x92, &tmp16);
1015 tmp16 |= 0xf;
1016 pci_write_config_word(pdev, 0x92, tmp16);
1017 }
1da177e4
LT		 1018
1019 hpriv->cap = readl(mmio + HOST_CAP);
1020 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
1021 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
1022
1023 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1024 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
1025
1026 using_dac = hpriv->cap & HOST_CAP_64;
1027 if (using_dac &&
1028 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1029 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1030 if (rc) {
1031 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1032 if (rc) {
a9524a76
JG		 1033 dev_printk(KERN_ERR, &pdev->dev,
1034 "64-bit DMA enable failed\n");
1da177e4
LT		 1035 return rc;
1036 }
1037 }
1da177e4
LT		 1038 } else {
1039 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1040 if (rc) {
a9524a76
JG		 1041 dev_printk(KERN_ERR, &pdev->dev,
1042 "32-bit DMA enable failed\n");
1da177e4
LT		 1043 return rc;
1044 }
1045 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1046 if (rc) {
a9524a76
JG		 1047 dev_printk(KERN_ERR, &pdev->dev,
1048 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 1049 return rc;
1050 }
1051 }
1052
1053 for (i = 0; i < probe_ent->n_ports; i++) {
1054#if 0 /* BIOSen initialize this incorrectly */
1055 if (!(hpriv->port_map & (1 << i)))
1056 continue;
1057#endif
1058
1059 port_mmio = ahci_port_base(mmio, i);
1060 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
1061
1062 ahci_setup_port(&probe_ent->port[i],
1063 (unsigned long) mmio, i);
1064
1065 /* make sure port is not active */
1066 tmp = readl(port_mmio + PORT_CMD);
1067 VPRINTK("PORT_CMD 0x%x\n", tmp);
1068 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
1069 PORT_CMD_FIS_RX | PORT_CMD_START)) {
1070 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
1071 PORT_CMD_FIS_RX | PORT_CMD_START);
1072 writel(tmp, port_mmio + PORT_CMD);
1073 readl(port_mmio + PORT_CMD); /* flush */
1074
1075 /* spec says 500 msecs for each bit, so
1076 * this is slightly incorrect.
1077 */
1078 msleep(500);
1079 }
1080
1081 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
1082
1083 j = 0;
1084 while (j < 100) {
1085 msleep(10);
1086 tmp = readl(port_mmio + PORT_SCR_STAT);
1087 if ((tmp & 0xf) == 0x3)
1088 break;
1089 j++;
1090 }
1091
1092 tmp = readl(port_mmio + PORT_SCR_ERR);
1093 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1094 writel(tmp, port_mmio + PORT_SCR_ERR);
1095
1096 /* ack any pending irq events for this port */
1097 tmp = readl(port_mmio + PORT_IRQ_STAT);
1098 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1099 if (tmp)
1100 writel(tmp, port_mmio + PORT_IRQ_STAT);
1101
1102 writel(1 << i, mmio + HOST_IRQ_STAT);
1103
1104 /* set irq mask (enables interrupts) */
1105 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1106 }
1107
1108 tmp = readl(mmio + HOST_CTL);
1109 VPRINTK("HOST_CTL 0x%x\n", tmp);
1110 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1111 tmp = readl(mmio + HOST_CTL);
1112 VPRINTK("HOST_CTL 0x%x\n", tmp);
1113
1114 pci_set_master(pdev);
1115
1116 return 0;
1117}
1118
1da177e4
LT		 1119static void ahci_print_info(struct ata_probe_ent *probe_ent)
1120{
1121 struct ahci_host_priv *hpriv = probe_ent->private_data;
1122 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
ea6ba10b 1123 void __iomem *mmio = probe_ent->mmio_base;
1da177e4
LT		 1124 u32 vers, cap, impl, speed;
1125 const char *speed_s;
1126 u16 cc;
1127 const char *scc_s;
1128
1129 vers = readl(mmio + HOST_VERSION);
1130 cap = hpriv->cap;
1131 impl = hpriv->port_map;
1132
1133 speed = (cap >> 20) & 0xf;
1134 if (speed == 1)
1135 speed_s = "1.5";
1136 else if (speed == 2)
1137 speed_s = "3";
1138 else
1139 speed_s = "?";
1140
1141 pci_read_config_word(pdev, 0x0a, &cc);
1142 if (cc == 0x0101)
1143 scc_s = "IDE";
1144 else if (cc == 0x0106)
1145 scc_s = "SATA";
1146 else if (cc == 0x0104)
1147 scc_s = "RAID";
1148 else
1149 scc_s = "unknown";
1150
a9524a76
JG		 1151 dev_printk(KERN_INFO, &pdev->dev,
1152 "AHCI %02x%02x.%02x%02x "
1da177e4
LT		 1153 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1154 ,
1da177e4
LT		 1155
1156 (vers >> 24) & 0xff,
1157 (vers >> 16) & 0xff,
1158 (vers >> 8) & 0xff,
1159 vers & 0xff,
1160
1161 ((cap >> 8) & 0x1f) + 1,
1162 (cap & 0x1f) + 1,
1163 speed_s,
1164 impl,
1165 scc_s);
1166
a9524a76
JG		 1167 dev_printk(KERN_INFO, &pdev->dev,
1168 "flags: "
1da177e4
LT		 1169 "%s%s%s%s%s%s"
1170 "%s%s%s%s%s%s%s\n"
1171 ,
1da177e4
LT		 1172
1173 cap & (1 << 31) ? "64bit " : "",
1174 cap & (1 << 30) ? "ncq " : "",
1175 cap & (1 << 28) ? "ilck " : "",
1176 cap & (1 << 27) ? "stag " : "",
1177 cap & (1 << 26) ? "pm " : "",
1178 cap & (1 << 25) ? "led " : "",
1179
1180 cap & (1 << 24) ? "clo " : "",
1181 cap & (1 << 19) ? "nz " : "",
1182 cap & (1 << 18) ? "only " : "",
1183 cap & (1 << 17) ? "pmp " : "",
1184 cap & (1 << 15) ? "pio " : "",
1185 cap & (1 << 14) ? "slum " : "",
1186 cap & (1 << 13) ? "part " : ""
1187 );
1188}
1189
1190static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1191{
1192 static int printed_version;
1193 struct ata_probe_ent *probe_ent = NULL;
1194 struct ahci_host_priv *hpriv;
1195 unsigned long base;
ea6ba10b 1196 void __iomem *mmio_base;
1da177e4 1197 unsigned int board_idx = (unsigned int) ent->driver_data;
907f4678 1198 int have_msi, pci_dev_busy = 0;
1da177e4
LT		 1199 int rc;
1200
1201 VPRINTK("ENTER\n");
1202
1203 if (!printed_version++)
a9524a76 1204 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4
LT		 1205
1206 rc = pci_enable_device(pdev);
1207 if (rc)
1208 return rc;
1209
1210 rc = pci_request_regions(pdev, DRV_NAME);
1211 if (rc) {
1212 pci_dev_busy = 1;
1213 goto err_out;
1214 }
1215
907f4678
JG		 1216 if (pci_enable_msi(pdev) == 0)
1217 have_msi = 1;
1218 else {
1219 pci_intx(pdev, 1);
1220 have_msi = 0;
1221 }
1da177e4
LT		 1222
1223 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1224 if (probe_ent == NULL) {
1225 rc = -ENOMEM;
907f4678 1226 goto err_out_msi;
1da177e4
LT		 1227 }
1228
1229 memset(probe_ent, 0, sizeof(*probe_ent));
1230 probe_ent->dev = pci_dev_to_dev(pdev);
1231 INIT_LIST_HEAD(&probe_ent->node);
1232
374b1873 1233 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1da177e4
LT		 1234 if (mmio_base == NULL) {
1235 rc = -ENOMEM;
1236 goto err_out_free_ent;
1237 }
1238 base = (unsigned long) mmio_base;
1239
1240 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1241 if (!hpriv) {
1242 rc = -ENOMEM;
1243 goto err_out_iounmap;
1244 }
1245 memset(hpriv, 0, sizeof(*hpriv));
1246
1247 probe_ent->sht = ahci_port_info[board_idx].sht;
1248 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1249 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1250 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1251 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1252
1253 probe_ent->irq = pdev->irq;
1254 probe_ent->irq_flags = SA_SHIRQ;
1255 probe_ent->mmio_base = mmio_base;
1256 probe_ent->private_data = hpriv;
1257
4b0060f4
JG		 1258 if (have_msi)
1259 hpriv->flags |= AHCI_FLAG_MSI;
907f4678 1260
bd12097c
JG		 1261 /* JMicron-specific fixup: make sure we're in AHCI mode */
1262 if (pdev->vendor == 0x197b)
1263 pci_write_config_byte(pdev, 0x41, 0xa1);
1264
1da177e4
LT		 1265 /* initialize adapter */
1266 rc = ahci_host_init(probe_ent);
1267 if (rc)
1268 goto err_out_hpriv;
1269
1270 ahci_print_info(probe_ent);
1271
1272 /* FIXME: check ata_device_add return value */
1273 ata_device_add(probe_ent);
1274 kfree(probe_ent);
1275
1276 return 0;
1277
1278err_out_hpriv:
1279 kfree(hpriv);
1280err_out_iounmap:
374b1873 1281 pci_iounmap(pdev, mmio_base);
1da177e4
LT		 1282err_out_free_ent:
1283 kfree(probe_ent);
907f4678
JG		 1284err_out_msi:
1285 if (have_msi)
1286 pci_disable_msi(pdev);
1287 else
1288 pci_intx(pdev, 0);
1da177e4
LT		 1289 pci_release_regions(pdev);
1290err_out:
1291 if (!pci_dev_busy)
1292 pci_disable_device(pdev);
1293 return rc;
1294}
1295
907f4678
JG		 1296static void ahci_remove_one (struct pci_dev *pdev)
1297{
1298 struct device *dev = pci_dev_to_dev(pdev);
1299 struct ata_host_set *host_set = dev_get_drvdata(dev);
1300 struct ahci_host_priv *hpriv = host_set->private_data;
1301 struct ata_port *ap;
1302 unsigned int i;
1303 int have_msi;
1304
1305 for (i = 0; i < host_set->n_ports; i++) {
1306 ap = host_set->ports[i];
1307
1308 scsi_remove_host(ap->host);
1309 }
1310
4b0060f4 1311 have_msi = hpriv->flags & AHCI_FLAG_MSI;
907f4678 1312 free_irq(host_set->irq, host_set);
907f4678
JG		 1313
1314 for (i = 0; i < host_set->n_ports; i++) {
1315 ap = host_set->ports[i];
1316
1317 ata_scsi_release(ap->host);
1318 scsi_host_put(ap->host);
1319 }
1320
e005f01d 1321 kfree(hpriv);
374b1873 1322 pci_iounmap(pdev, host_set->mmio_base);
ead5de99
JG		 1323 kfree(host_set);
1324
907f4678
JG		 1325 if (have_msi)
1326 pci_disable_msi(pdev);
1327 else
1328 pci_intx(pdev, 0);
1329 pci_release_regions(pdev);
907f4678
JG		 1330 pci_disable_device(pdev);
1331 dev_set_drvdata(dev, NULL);
1332}
1da177e4
LT		 1333
1334static int __init ahci_init(void)
1335{
1336 return pci_module_init(&ahci_pci_driver);
1337}
1338
1da177e4
LT		 1339static void __exit ahci_exit(void)
1340{
1341 pci_unregister_driver(&ahci_pci_driver);
1342}
1343
1344
1345MODULE_AUTHOR("Jeff Garzik");
1346MODULE_DESCRIPTION("AHCI SATA low-level driver");
1347MODULE_LICENSE("GPL");
1348MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1349MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 1350
1351module_init(ahci_init);
1352module_exit(ahci_exit);
Linux kernel - Deliverables
This page took 0.181096 seconds and 5 git commands to generate.