projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] libata: implement new SCR handling and port on/offline functions
[deliverable/linux.git] / drivers / scsi / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/sched.h>
87507cfd 43#include <linux/dma-mapping.h>
a9524a76 44#include <linux/device.h>
1da177e4 45#include <scsi/scsi_host.h>
193515d5 46#include <scsi/scsi_cmnd.h>
1da177e4
LT		 47#include <linux/libata.h>
48#include <asm/io.h>
49
50#define DRV_NAME "ahci"
af64371a 51#define DRV_VERSION "1.3"
1da177e4
LT		 52
53
54enum {
55 AHCI_PCI_BAR = 5,
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
59 AHCI_CMD_SLOT_SZ = 32 * 32,
60 AHCI_RX_FIS_SZ = 256,
61 AHCI_CMD_TBL_HDR = 0x80,
a0ea7328 62 AHCI_CMD_TBL_CDB = 0x40,
1da177e4
LT		 63 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16),
64 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ +
65 AHCI_RX_FIS_SZ,
66 AHCI_IRQ_ON_SG = (1 << 31),
67 AHCI_CMD_ATAPI = (1 << 5),
68 AHCI_CMD_WRITE = (1 << 6),
4b10e559 69 AHCI_CMD_PREFETCH = (1 << 7),
22b49985
TH		 70 AHCI_CMD_RESET = (1 << 8),
71 AHCI_CMD_CLR_BUSY = (1 << 10),
1da177e4
LT		 72
73 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
74
75 board_ahci = 0,
bf2af2a2 76 board_ahci_vt8251 = 1,
1da177e4
LT		 77
78 /* global controller registers */
79 HOST_CAP = 0x00, /* host capabilities */
80 HOST_CTL = 0x04, /* global host control */
81 HOST_IRQ_STAT = 0x08, /* interrupt status */
82 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
83 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
84
85 /* HOST_CTL bits */
86 HOST_RESET = (1 << 0), /* reset controller; self-clear */
87 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
88 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
89
90 /* HOST_CAP bits */
91 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
22b49985 92 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
1da177e4
LT		 93
94 /* registers for each SATA port */
95 PORT_LST_ADDR = 0x00, /* command list DMA addr */
96 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
97 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
98 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
99 PORT_IRQ_STAT = 0x10, /* interrupt status */
100 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
101 PORT_CMD = 0x18, /* port command */
102 PORT_TFDATA = 0x20, /* taskfile data */
103 PORT_SIG = 0x24, /* device TF signature */
104 PORT_CMD_ISSUE = 0x38, /* command issue */
105 PORT_SCR = 0x28, /* SATA phy register block */
106 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
107 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
108 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
109 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
110
111 /* PORT_IRQ_{STAT,MASK} bits */
112 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
113 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
114 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
115 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
116 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
117 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
118 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
119 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
120
121 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
122 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
123 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
124 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
125 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
126 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
127 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
128 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
129 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
130
131 PORT_IRQ_FATAL = PORT_IRQ_TF_ERR |
132 PORT_IRQ_HBUS_ERR |
133 PORT_IRQ_HBUS_DATA_ERR |
134 PORT_IRQ_IF_ERR,
135 DEF_PORT_IRQ = PORT_IRQ_FATAL | PORT_IRQ_PHYRDY |
136 PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE |
137 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS |
138 PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS |
139 PORT_IRQ_D2H_REG_FIS,
140
141 /* PORT_CMD bits */
02eaa666 142 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
1da177e4
LT		 143 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
144 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
145 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
22b49985 146 PORT_CMD_CLO = (1 << 3), /* Command list override */
1da177e4
LT		 147 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
148 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
149 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
150
151 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
152 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
153 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
4b0060f4
JG		 154
155 /* hpriv->flags bits */
156 AHCI_FLAG_MSI = (1 << 0),
bf2af2a2
BJ		 157
158 /* ap->flags bits */
159 AHCI_FLAG_RESET_NEEDS_CLO = (1 << 24),
1da177e4
LT		 160};
161
162struct ahci_cmd_hdr {
163 u32 opts;
164 u32 status;
165 u32 tbl_addr;
166 u32 tbl_addr_hi;
167 u32 reserved[4];
168};
169
170struct ahci_sg {
171 u32 addr;
172 u32 addr_hi;
173 u32 reserved;
174 u32 flags_size;
175};
176
177struct ahci_host_priv {
178 unsigned long flags;
179 u32 cap; /* cache of HOST_CAP register */
180 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
181};
182
183struct ahci_port_priv {
184 struct ahci_cmd_hdr *cmd_slot;
185 dma_addr_t cmd_slot_dma;
186 void *cmd_tbl;
187 dma_addr_t cmd_tbl_dma;
188 struct ahci_sg *cmd_tbl_sg;
189 void *rx_fis;
190 dma_addr_t rx_fis_dma;
191};
192
193static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
194static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
195static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
9a3d9eb0 196static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
1da177e4 197static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
4bd00f6a 198static int ahci_probe_reset(struct ata_port *ap, unsigned int *classes);
1da177e4
LT		 199static void ahci_irq_clear(struct ata_port *ap);
200static void ahci_eng_timeout(struct ata_port *ap);
201static int ahci_port_start(struct ata_port *ap);
202static void ahci_port_stop(struct ata_port *ap);
1da177e4
LT		 203static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
204static void ahci_qc_prep(struct ata_queued_cmd *qc);
205static u8 ahci_check_status(struct ata_port *ap);
1da177e4 206static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc);
907f4678 207static void ahci_remove_one (struct pci_dev *pdev);
1da177e4 208
193515d5 209static struct scsi_host_template ahci_sht = {
1da177e4
LT		 210 .module = THIS_MODULE,
211 .name = DRV_NAME,
212 .ioctl = ata_scsi_ioctl,
213 .queuecommand = ata_scsi_queuecmd,
1da177e4
LT		 214 .can_queue = ATA_DEF_QUEUE,
215 .this_id = ATA_SHT_THIS_ID,
216 .sg_tablesize = AHCI_MAX_SG,
1da177e4
LT		 217 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
218 .emulated = ATA_SHT_EMULATED,
219 .use_clustering = AHCI_USE_CLUSTERING,
220 .proc_name = DRV_NAME,
221 .dma_boundary = AHCI_DMA_BOUNDARY,
222 .slave_configure = ata_scsi_slave_config,
223 .bios_param = ata_std_bios_param,
1da177e4
LT		 224};
225
057ace5e 226static const struct ata_port_operations ahci_ops = {
1da177e4
LT		 227 .port_disable = ata_port_disable,
228
229 .check_status = ahci_check_status,
230 .check_altstatus = ahci_check_status,
1da177e4
LT		 231 .dev_select = ata_noop_dev_select,
232
233 .tf_read = ahci_tf_read,
234
4bd00f6a 235 .probe_reset = ahci_probe_reset,
1da177e4
LT		 236
237 .qc_prep = ahci_qc_prep,
238 .qc_issue = ahci_qc_issue,
239
240 .eng_timeout = ahci_eng_timeout,
241
242 .irq_handler = ahci_interrupt,
243 .irq_clear = ahci_irq_clear,
244
245 .scr_read = ahci_scr_read,
246 .scr_write = ahci_scr_write,
247
248 .port_start = ahci_port_start,
249 .port_stop = ahci_port_stop,
1da177e4
LT		 250};
251
98ac62de 252static const struct ata_port_info ahci_port_info[] = {
1da177e4
LT		 253 /* board_ahci */
254 {
255 .sht = &ahci_sht,
256 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
4bd00f6a 257 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
7da79312 258 .pio_mask = 0x1f, /* pio0-4 */
1da177e4
LT		 259 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
260 .port_ops = &ahci_ops,
261 },
bf2af2a2
BJ		 262 /* board_ahci_vt8251 */
263 {
264 .sht = &ahci_sht,
265 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
266 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
267 AHCI_FLAG_RESET_NEEDS_CLO,
268 .pio_mask = 0x1f, /* pio0-4 */
269 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
270 .port_ops = &ahci_ops,
271 },
1da177e4
LT		 272};
273
3b7d697d 274static const struct pci_device_id ahci_pci_tbl[] = {
1da177e4
LT		 275 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
276 board_ahci }, /* ICH6 */
277 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
278 board_ahci }, /* ICH6M */
279 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
280 board_ahci }, /* ICH7 */
281 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
282 board_ahci }, /* ICH7M */
283 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
284 board_ahci }, /* ICH7R */
285 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
286 board_ahci }, /* ULi M5288 */
680d3235
JG		 287 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
288 board_ahci }, /* ESB2 */
289 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
290 board_ahci }, /* ESB2 */
291 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
292 board_ahci }, /* ESB2 */
3db368f7
JG		 293 { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
294 board_ahci }, /* ICH7-M DH */
f285757c
JG		 295 { PCI_VENDOR_ID_INTEL, 0x2821, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
296 board_ahci }, /* ICH8 */
297 { PCI_VENDOR_ID_INTEL, 0x2822, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
298 board_ahci }, /* ICH8 */
299 { PCI_VENDOR_ID_INTEL, 0x2824, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
300 board_ahci }, /* ICH8 */
301 { PCI_VENDOR_ID_INTEL, 0x2829, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
302 board_ahci }, /* ICH8M */
303 { PCI_VENDOR_ID_INTEL, 0x282a, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
304 board_ahci }, /* ICH8M */
bd12097c
JG		 305 { 0x197b, 0x2360, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
306 board_ahci }, /* JMicron JMB360 */
9220a2d0
JG		 307 { 0x197b, 0x2363, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
308 board_ahci }, /* JMicron JMB363 */
8b316a39
JG		 309 { PCI_VENDOR_ID_ATI, 0x4380, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
310 board_ahci }, /* ATI SB600 non-raid */
311 { PCI_VENDOR_ID_ATI, 0x4381, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
312 board_ahci }, /* ATI SB600 raid */
bf2af2a2
BJ		 313 { PCI_VENDOR_ID_VIA, 0x3349, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
314 board_ahci_vt8251 }, /* VIA VT8251 */
1da177e4
LT		 315 { } /* terminate list */
316};
317
318
319static struct pci_driver ahci_pci_driver = {
320 .name = DRV_NAME,
321 .id_table = ahci_pci_tbl,
322 .probe = ahci_init_one,
907f4678 323 .remove = ahci_remove_one,
1da177e4
LT		 324};
325
326
327static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
328{
329 return base + 0x100 + (port * 0x80);
330}
331
ea6ba10b 332static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
1da177e4 333{
ea6ba10b 334 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
1da177e4
LT		 335}
336
1da177e4
LT		 337static int ahci_port_start(struct ata_port *ap)
338{
339 struct device *dev = ap->host_set->dev;
340 struct ahci_host_priv *hpriv = ap->host_set->private_data;
341 struct ahci_port_priv *pp;
ea6ba10b
JG		 342 void __iomem *mmio = ap->host_set->mmio_base;
343 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
344 void *mem;
1da177e4 345 dma_addr_t mem_dma;
6037d6bb 346 int rc;
1da177e4 347
1da177e4 348 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
0a139e79
TH		 349 if (!pp)
350 return -ENOMEM;
1da177e4
LT		 351 memset(pp, 0, sizeof(*pp));
352
6037d6bb
JG		 353 rc = ata_pad_alloc(ap, dev);
354 if (rc) {
cedc9a47 355 kfree(pp);
6037d6bb 356 return rc;
cedc9a47
JG		 357 }
358
1da177e4
LT		 359 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
360 if (!mem) {
6037d6bb 361 ata_pad_free(ap, dev);
0a139e79
TH		 362 kfree(pp);
363 return -ENOMEM;
1da177e4
LT		 364 }
365 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
366
367 /*
368 * First item in chunk of DMA memory: 32-slot command table,
369 * 32 bytes each in size
370 */
371 pp->cmd_slot = mem;
372 pp->cmd_slot_dma = mem_dma;
373
374 mem += AHCI_CMD_SLOT_SZ;
375 mem_dma += AHCI_CMD_SLOT_SZ;
376
377 /*
378 * Second item: Received-FIS area
379 */
380 pp->rx_fis = mem;
381 pp->rx_fis_dma = mem_dma;
382
383 mem += AHCI_RX_FIS_SZ;
384 mem_dma += AHCI_RX_FIS_SZ;
385
386 /*
387 * Third item: data area for storing a single command
388 * and its scatter-gather table
389 */
390 pp->cmd_tbl = mem;
391 pp->cmd_tbl_dma = mem_dma;
392
393 pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR;
394
395 ap->private_data = pp;
396
397 if (hpriv->cap & HOST_CAP_64)
398 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
399 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
400 readl(port_mmio + PORT_LST_ADDR); /* flush */
401
402 if (hpriv->cap & HOST_CAP_64)
403 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
404 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
405 readl(port_mmio + PORT_FIS_ADDR); /* flush */
406
407 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
408 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
409 PORT_CMD_START, port_mmio + PORT_CMD);
410 readl(port_mmio + PORT_CMD); /* flush */
411
412 return 0;
1da177e4
LT		 413}
414
415
416static void ahci_port_stop(struct ata_port *ap)
417{
418 struct device *dev = ap->host_set->dev;
419 struct ahci_port_priv *pp = ap->private_data;
ea6ba10b
JG		 420 void __iomem *mmio = ap->host_set->mmio_base;
421 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1da177e4
LT		 422 u32 tmp;
423
424 tmp = readl(port_mmio + PORT_CMD);
425 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
426 writel(tmp, port_mmio + PORT_CMD);
427 readl(port_mmio + PORT_CMD); /* flush */
428
429 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
430 * this is slightly incorrect.
431 */
432 msleep(500);
433
434 ap->private_data = NULL;
435 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
436 pp->cmd_slot, pp->cmd_slot_dma);
6037d6bb 437 ata_pad_free(ap, dev);
1da177e4 438 kfree(pp);
1da177e4
LT		 439}
440
441static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
442{
443 unsigned int sc_reg;
444
445 switch (sc_reg_in) {
446 case SCR_STATUS: sc_reg = 0; break;
447 case SCR_CONTROL: sc_reg = 1; break;
448 case SCR_ERROR: sc_reg = 2; break;
449 case SCR_ACTIVE: sc_reg = 3; break;
450 default:
451 return 0xffffffffU;
452 }
453
1e4f2a96 454 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT		 455}
456
457
458static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
459 u32 val)
460{
461 unsigned int sc_reg;
462
463 switch (sc_reg_in) {
464 case SCR_STATUS: sc_reg = 0; break;
465 case SCR_CONTROL: sc_reg = 1; break;
466 case SCR_ERROR: sc_reg = 2; break;
467 case SCR_ACTIVE: sc_reg = 3; break;
468 default:
469 return;
470 }
471
1e4f2a96 472 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT		 473}
474
7c76d1e8
TH		 475static int ahci_stop_engine(struct ata_port *ap)
476{
477 void __iomem *mmio = ap->host_set->mmio_base;
478 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
479 int work;
480 u32 tmp;
481
482 tmp = readl(port_mmio + PORT_CMD);
483 tmp &= ~PORT_CMD_START;
484 writel(tmp, port_mmio + PORT_CMD);
485
486 /* wait for engine to stop. TODO: this could be
487 * as long as 500 msec
488 */
489 work = 1000;
490 while (work-- > 0) {
491 tmp = readl(port_mmio + PORT_CMD);
492 if ((tmp & PORT_CMD_LIST_ON) == 0)
493 return 0;
494 udelay(10);
495 }
496
497 return -EIO;
498}
499
500static void ahci_start_engine(struct ata_port *ap)
501{
502 void __iomem *mmio = ap->host_set->mmio_base;
503 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
504 u32 tmp;
505
506 tmp = readl(port_mmio + PORT_CMD);
507 tmp |= PORT_CMD_START;
508 writel(tmp, port_mmio + PORT_CMD);
509 readl(port_mmio + PORT_CMD); /* flush */
510}
511
422b7595 512static unsigned int ahci_dev_classify(struct ata_port *ap)
1da177e4
LT		 513{
514 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
515 struct ata_taskfile tf;
422b7595
TH		 516 u32 tmp;
517
518 tmp = readl(port_mmio + PORT_SIG);
519 tf.lbah = (tmp >> 24) & 0xff;
520 tf.lbam = (tmp >> 16) & 0xff;
521 tf.lbal = (tmp >> 8) & 0xff;
522 tf.nsect = (tmp) & 0xff;
523
524 return ata_dev_classify(&tf);
525}
526
a42fc659 527static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, u32 opts)
cc9278ed 528{
cc9278ed
TH		 529 pp->cmd_slot[0].opts = cpu_to_le32(opts);
530 pp->cmd_slot[0].status = 0;
531 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
532 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
533}
534
bf2af2a2 535static int ahci_clo(struct ata_port *ap)
4658f79b 536{
bf2af2a2 537 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
4658f79b 538 struct ahci_host_priv *hpriv = ap->host_set->private_data;
bf2af2a2
BJ		 539 u32 tmp;
540
541 if (!(hpriv->cap & HOST_CAP_CLO))
542 return -EOPNOTSUPP;
543
544 tmp = readl(port_mmio + PORT_CMD);
545 tmp |= PORT_CMD_CLO;
546 writel(tmp, port_mmio + PORT_CMD);
547
548 tmp = ata_wait_register(port_mmio + PORT_CMD,
549 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
550 if (tmp & PORT_CMD_CLO)
551 return -EIO;
552
553 return 0;
554}
555
556static int ahci_softreset(struct ata_port *ap, unsigned int *class)
557{
4658f79b
TH		 558 struct ahci_port_priv *pp = ap->private_data;
559 void __iomem *mmio = ap->host_set->mmio_base;
560 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
561 const u32 cmd_fis_len = 5; /* five dwords */
562 const char *reason = NULL;
563 struct ata_taskfile tf;
75fe1806 564 u32 tmp;
4658f79b
TH		 565 u8 *fis;
566 int rc;
567
568 DPRINTK("ENTER\n");
569
c2a65852
TH		 570 if (!sata_dev_present(ap)) {
571 DPRINTK("PHY reports no device\n");
572 *class = ATA_DEV_NONE;
573 return 0;
574 }
575
4658f79b
TH		 576 /* prepare for SRST (AHCI-1.1 10.4.1) */
577 rc = ahci_stop_engine(ap);
578 if (rc) {
579 reason = "failed to stop engine";
580 goto fail_restart;
581 }
582
583 /* check BUSY/DRQ, perform Command List Override if necessary */
584 ahci_tf_read(ap, &tf);
585 if (tf.command & (ATA_BUSY | ATA_DRQ)) {
bf2af2a2 586 rc = ahci_clo(ap);
4658f79b 587
bf2af2a2
BJ		 588 if (rc == -EOPNOTSUPP) {
589 reason = "port busy but CLO unavailable";
590 goto fail_restart;
591 } else if (rc) {
592 reason = "port busy but CLO failed";
4658f79b
TH		 593 goto fail_restart;
594 }
595 }
596
597 /* restart engine */
598 ahci_start_engine(ap);
599
600 ata_tf_init(ap, &tf, 0);
601 fis = pp->cmd_tbl;
602
603 /* issue the first D2H Register FIS */
604 ahci_fill_cmd_slot(pp, cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
605
606 tf.ctl |= ATA_SRST;
607 ata_tf_to_fis(&tf, fis, 0);
608 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
609
610 writel(1, port_mmio + PORT_CMD_ISSUE);
4658f79b 611
75fe1806
TH		 612 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
613 if (tmp & 0x1) {
4658f79b
TH		 614 rc = -EIO;
615 reason = "1st FIS failed";
616 goto fail;
617 }
618
619 /* spec says at least 5us, but be generous and sleep for 1ms */
620 msleep(1);
621
622 /* issue the second D2H Register FIS */
623 ahci_fill_cmd_slot(pp, cmd_fis_len);
624
625 tf.ctl &= ~ATA_SRST;
626 ata_tf_to_fis(&tf, fis, 0);
627 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
628
629 writel(1, port_mmio + PORT_CMD_ISSUE);
630 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
631
632 /* spec mandates ">= 2ms" before checking status.
633 * We wait 150ms, because that was the magic delay used for
634 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
635 * between when the ATA command register is written, and then
636 * status is checked. Because waiting for "a while" before
637 * checking status is fine, post SRST, we perform this magic
638 * delay here as well.
639 */
640 msleep(150);
641
642 *class = ATA_DEV_NONE;
643 if (sata_dev_present(ap)) {
644 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
645 rc = -EIO;
646 reason = "device not ready";
647 goto fail;
648 }
649 *class = ahci_dev_classify(ap);
650 }
651
652 DPRINTK("EXIT, class=%u\n", *class);
653 return 0;
654
655 fail_restart:
656 ahci_start_engine(ap);
657 fail:
2bf2cb26
TH		 658 printk(KERN_ERR "ata%u: softreset failed (%s)\n",
659 ap->id, reason);
4658f79b
TH		 660 return rc;
661}
662
2bf2cb26 663static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
422b7595 664{
4bd00f6a
TH		 665 int rc;
666
667 DPRINTK("ENTER\n");
1da177e4 668
e0bfd149 669 ahci_stop_engine(ap);
2bf2cb26 670 rc = sata_std_hardreset(ap, class);
e0bfd149 671 ahci_start_engine(ap);
1da177e4 672
e4fac92a 673 if (rc == 0 && sata_dev_present(ap))
4bd00f6a
TH		 674 *class = ahci_dev_classify(ap);
675 if (*class == ATA_DEV_UNKNOWN)
676 *class = ATA_DEV_NONE;
1da177e4 677
4bd00f6a
TH		 678 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
679 return rc;
680}
681
682static void ahci_postreset(struct ata_port *ap, unsigned int *class)
683{
684 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
685 u32 new_tmp, tmp;
686
687 ata_std_postreset(ap, class);
02eaa666
JG		 688
689 /* Make sure port's ATAPI bit is set appropriately */
690 new_tmp = tmp = readl(port_mmio + PORT_CMD);
4bd00f6a 691 if (*class == ATA_DEV_ATAPI)
02eaa666
JG		 692 new_tmp |= PORT_CMD_ATAPI;
693 else
694 new_tmp &= ~PORT_CMD_ATAPI;
695 if (new_tmp != tmp) {
696 writel(new_tmp, port_mmio + PORT_CMD);
697 readl(port_mmio + PORT_CMD); /* flush */
698 }
1da177e4
LT		 699}
700
4bd00f6a
TH		 701static int ahci_probe_reset(struct ata_port *ap, unsigned int *classes)
702{
bf2af2a2
BJ		 703 if ((ap->flags & AHCI_FLAG_RESET_NEEDS_CLO) &&
704 (ata_busy_wait(ap, ATA_BUSY, 1000) & ATA_BUSY)) {
705 /* ATA_BUSY hasn't cleared, so send a CLO */
706 ahci_clo(ap);
707 }
708
4658f79b
TH		 709 return ata_drive_probe_reset(ap, ata_std_probeinit,
710 ahci_softreset, ahci_hardreset,
4bd00f6a
TH		 711 ahci_postreset, classes);
712}
713
1da177e4
LT		 714static u8 ahci_check_status(struct ata_port *ap)
715{
1e4f2a96 716 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1da177e4
LT		 717
718 return readl(mmio + PORT_TFDATA) & 0xFF;
719}
720
1da177e4
LT		 721static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
722{
723 struct ahci_port_priv *pp = ap->private_data;
724 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
725
726 ata_tf_from_fis(d2h_fis, tf);
727}
728
828d09de 729static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc)
1da177e4
LT		 730{
731 struct ahci_port_priv *pp = qc->ap->private_data;
cedc9a47
JG		 732 struct scatterlist *sg;
733 struct ahci_sg *ahci_sg;
828d09de 734 unsigned int n_sg = 0;
1da177e4
LT		 735
736 VPRINTK("ENTER\n");
737
738 /*
739 * Next, the S/G list.
740 */
cedc9a47
JG		 741 ahci_sg = pp->cmd_tbl_sg;
742 ata_for_each_sg(sg, qc) {
743 dma_addr_t addr = sg_dma_address(sg);
744 u32 sg_len = sg_dma_len(sg);
745
746 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
747 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
748 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
828d09de 749
cedc9a47 750 ahci_sg++;
828d09de 751 n_sg++;
1da177e4 752 }
828d09de
JG		 753
754 return n_sg;
1da177e4
LT		 755}
756
757static void ahci_qc_prep(struct ata_queued_cmd *qc)
758{
a0ea7328
JG		 759 struct ata_port *ap = qc->ap;
760 struct ahci_port_priv *pp = ap->private_data;
cc9278ed 761 int is_atapi = is_atapi_taskfile(&qc->tf);
1da177e4
LT		 762 u32 opts;
763 const u32 cmd_fis_len = 5; /* five dwords */
828d09de 764 unsigned int n_elem;
1da177e4 765
1da177e4
LT		 766 /*
767 * Fill in command table information. First, the header,
768 * a SATA Register - Host to Device command FIS.
769 */
770 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
cc9278ed 771 if (is_atapi) {
a0ea7328 772 memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
6e7846e9
TH		 773 memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb,
774 qc->dev->cdb_len);
a0ea7328 775 }
1da177e4 776
cc9278ed
TH		 777 n_elem = 0;
778 if (qc->flags & ATA_QCFLAG_DMAMAP)
779 n_elem = ahci_fill_sg(qc);
1da177e4 780
cc9278ed
TH		 781 /*
782 * Fill in command slot information.
783 */
784 opts = cmd_fis_len | n_elem << 16;
785 if (qc->tf.flags & ATA_TFLAG_WRITE)
786 opts |= AHCI_CMD_WRITE;
787 if (is_atapi)
4b10e559 788 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
828d09de 789
a42fc659 790 ahci_fill_cmd_slot(pp, opts);
1da177e4
LT		 791}
792
c2cd76ff 793static void ahci_restart_port(struct ata_port *ap, u32 irq_stat)
1da177e4 794{
ea6ba10b
JG		 795 void __iomem *mmio = ap->host_set->mmio_base;
796 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1da177e4 797 u32 tmp;
1da177e4 798
c2cd76ff
JG		 799 if ((ap->device[0].class != ATA_DEV_ATAPI) ||
800 ((irq_stat & PORT_IRQ_TF_ERR) == 0))
801 printk(KERN_WARNING "ata%u: port reset, "
802 "p_is %x is %x pis %x cmd %x tf %x ss %x se %x\n",
803 ap->id,
804 irq_stat,
805 readl(mmio + HOST_IRQ_STAT),
806 readl(port_mmio + PORT_IRQ_STAT),
807 readl(port_mmio + PORT_CMD),
808 readl(port_mmio + PORT_TFDATA),
809 readl(port_mmio + PORT_SCR_STAT),
810 readl(port_mmio + PORT_SCR_ERR));
9f68a248 811
1da177e4 812 /* stop DMA */
7c76d1e8 813 ahci_stop_engine(ap);
1da177e4
LT		 814
815 /* clear SATA phy error, if any */
816 tmp = readl(port_mmio + PORT_SCR_ERR);
817 writel(tmp, port_mmio + PORT_SCR_ERR);
818
819 /* if DRQ/BSY is set, device needs to be reset.
820 * if so, issue COMRESET
821 */
822 tmp = readl(port_mmio + PORT_TFDATA);
823 if (tmp & (ATA_BUSY | ATA_DRQ)) {
824 writel(0x301, port_mmio + PORT_SCR_CTL);
825 readl(port_mmio + PORT_SCR_CTL); /* flush */
826 udelay(10);
827 writel(0x300, port_mmio + PORT_SCR_CTL);
828 readl(port_mmio + PORT_SCR_CTL); /* flush */
829 }
830
831 /* re-start DMA */
7c76d1e8 832 ahci_start_engine(ap);
1da177e4
LT		 833}
834
835static void ahci_eng_timeout(struct ata_port *ap)
836{
b8f6153e 837 struct ata_host_set *host_set = ap->host_set;
ea6ba10b
JG		 838 void __iomem *mmio = host_set->mmio_base;
839 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1da177e4 840 struct ata_queued_cmd *qc;
b8f6153e 841 unsigned long flags;
1da177e4 842
9f68a248 843 printk(KERN_WARNING "ata%u: handling error/timeout\n", ap->id);
1da177e4 844
b8f6153e
JG		 845 spin_lock_irqsave(&host_set->lock, flags);
846
f6379020 847 ahci_restart_port(ap, readl(port_mmio + PORT_IRQ_STAT));
1da177e4 848 qc = ata_qc_from_tag(ap, ap->active_tag);
f6379020 849 qc->err_mask |= AC_ERR_TIMEOUT;
1da177e4 850
b8f6153e 851 spin_unlock_irqrestore(&host_set->lock, flags);
a72ec4ce 852
f6379020 853 ata_eh_qc_complete(qc);
1da177e4
LT		 854}
855
856static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
857{
ea6ba10b
JG		 858 void __iomem *mmio = ap->host_set->mmio_base;
859 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1da177e4
LT		 860 u32 status, serr, ci;
861
862 serr = readl(port_mmio + PORT_SCR_ERR);
863 writel(serr, port_mmio + PORT_SCR_ERR);
864
865 status = readl(port_mmio + PORT_IRQ_STAT);
866 writel(status, port_mmio + PORT_IRQ_STAT);
867
868 ci = readl(port_mmio + PORT_CMD_ISSUE);
869 if (likely((ci & 0x1) == 0)) {
870 if (qc) {
beec7dbc 871 WARN_ON(qc->err_mask);
a22e2eb0 872 ata_qc_complete(qc);
1da177e4
LT		 873 qc = NULL;
874 }
875 }
876
877 if (status & PORT_IRQ_FATAL) {
ad36d1a5
JG		 878 unsigned int err_mask;
879 if (status & PORT_IRQ_TF_ERR)
880 err_mask = AC_ERR_DEV;
881 else if (status & PORT_IRQ_IF_ERR)
882 err_mask = AC_ERR_ATA_BUS;
883 else
884 err_mask = AC_ERR_HOST_BUS;
885
9f68a248 886 /* command processing has stopped due to error; restart */
c2cd76ff 887 ahci_restart_port(ap, status);
9f68a248 888
a22e2eb0 889 if (qc) {
284b6481 890 qc->err_mask |= err_mask;
a22e2eb0
AL		 891 ata_qc_complete(qc);
892 }
1da177e4
LT		 893 }
894
895 return 1;
896}
897
898static void ahci_irq_clear(struct ata_port *ap)
899{
900 /* TODO */
901}
902
903static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
904{
905 struct ata_host_set *host_set = dev_instance;
906 struct ahci_host_priv *hpriv;
907 unsigned int i, handled = 0;
ea6ba10b 908 void __iomem *mmio;
1da177e4
LT		 909 u32 irq_stat, irq_ack = 0;
910
911 VPRINTK("ENTER\n");
912
913 hpriv = host_set->private_data;
914 mmio = host_set->mmio_base;
915
916 /* sigh. 0xffffffff is a valid return from h/w */
917 irq_stat = readl(mmio + HOST_IRQ_STAT);
918 irq_stat &= hpriv->port_map;
919 if (!irq_stat)
920 return IRQ_NONE;
921
922 spin_lock(&host_set->lock);
923
924 for (i = 0; i < host_set->n_ports; i++) {
925 struct ata_port *ap;
1da177e4 926
67846b30
JG		 927 if (!(irq_stat & (1 << i)))
928 continue;
929
1da177e4 930 ap = host_set->ports[i];
67846b30 931 if (ap) {
1da177e4
LT		 932 struct ata_queued_cmd *qc;
933 qc = ata_qc_from_tag(ap, ap->active_tag);
67846b30 934 if (!ahci_host_intr(ap, qc))
6971ed1f
TH		 935 if (ata_ratelimit())
936 dev_printk(KERN_WARNING, host_set->dev,
a9524a76
JG		 937 "unhandled interrupt on port %u\n",
938 i);
67846b30
JG		 939
940 VPRINTK("port %u\n", i);
941 } else {
942 VPRINTK("port %u (no irq)\n", i);
6971ed1f
TH		 943 if (ata_ratelimit())
944 dev_printk(KERN_WARNING, host_set->dev,
a9524a76 945 "interrupt on disabled port %u\n", i);
1da177e4 946 }
67846b30
JG		 947
948 irq_ack |= (1 << i);
1da177e4
LT		 949 }
950
951 if (irq_ack) {
952 writel(irq_ack, mmio + HOST_IRQ_STAT);
953 handled = 1;
954 }
955
956 spin_unlock(&host_set->lock);
957
958 VPRINTK("EXIT\n");
959
960 return IRQ_RETVAL(handled);
961}
962
9a3d9eb0 963static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 964{
965 struct ata_port *ap = qc->ap;
ea6ba10b 966 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1da177e4 967
1da177e4
LT		 968 writel(1, port_mmio + PORT_CMD_ISSUE);
969 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
970
971 return 0;
972}
973
974static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
975 unsigned int port_idx)
976{
977 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
978 base = ahci_port_base_ul(base, port_idx);
979 VPRINTK("base now==0x%lx\n", base);
980
981 port->cmd_addr = base;
982 port->scr_addr = base + PORT_SCR;
983
984 VPRINTK("EXIT\n");
985}
986
987static int ahci_host_init(struct ata_probe_ent *probe_ent)
988{
989 struct ahci_host_priv *hpriv = probe_ent->private_data;
990 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
991 void __iomem *mmio = probe_ent->mmio_base;
992 u32 tmp, cap_save;
1da177e4
LT		 993 unsigned int i, j, using_dac;
994 int rc;
995 void __iomem *port_mmio;
996
997 cap_save = readl(mmio + HOST_CAP);
998 cap_save &= ( (1<<28) | (1<<17) );
999 cap_save |= (1 << 27);
1000
1001 /* global controller reset */
1002 tmp = readl(mmio + HOST_CTL);
1003 if ((tmp & HOST_RESET) == 0) {
1004 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1005 readl(mmio + HOST_CTL); /* flush */
1006 }
1007
1008 /* reset must complete within 1 second, or
1009 * the hardware should be considered fried.
1010 */
1011 ssleep(1);
1012
1013 tmp = readl(mmio + HOST_CTL);
1014 if (tmp & HOST_RESET) {
a9524a76
JG		 1015 dev_printk(KERN_ERR, &pdev->dev,
1016 "controller reset failed (0x%x)\n", tmp);
1da177e4
LT		 1017 return -EIO;
1018 }
1019
1020 writel(HOST_AHCI_EN, mmio + HOST_CTL);
1021 (void) readl(mmio + HOST_CTL); /* flush */
1022 writel(cap_save, mmio + HOST_CAP);
1023 writel(0xf, mmio + HOST_PORTS_IMPL);
1024 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
1025
bd12097c
JG		 1026 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1027 u16 tmp16;
1028
1029 pci_read_config_word(pdev, 0x92, &tmp16);
1030 tmp16 |= 0xf;
1031 pci_write_config_word(pdev, 0x92, tmp16);
1032 }
1da177e4
LT		 1033
1034 hpriv->cap = readl(mmio + HOST_CAP);
1035 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
1036 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
1037
1038 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1039 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
1040
1041 using_dac = hpriv->cap & HOST_CAP_64;
1042 if (using_dac &&
1043 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1044 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1045 if (rc) {
1046 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1047 if (rc) {
a9524a76
JG		 1048 dev_printk(KERN_ERR, &pdev->dev,
1049 "64-bit DMA enable failed\n");
1da177e4
LT		 1050 return rc;
1051 }
1052 }
1da177e4
LT		 1053 } else {
1054 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1055 if (rc) {
a9524a76
JG		 1056 dev_printk(KERN_ERR, &pdev->dev,
1057 "32-bit DMA enable failed\n");
1da177e4
LT		 1058 return rc;
1059 }
1060 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1061 if (rc) {
a9524a76
JG		 1062 dev_printk(KERN_ERR, &pdev->dev,
1063 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 1064 return rc;
1065 }
1066 }
1067
1068 for (i = 0; i < probe_ent->n_ports; i++) {
1069#if 0 /* BIOSen initialize this incorrectly */
1070 if (!(hpriv->port_map & (1 << i)))
1071 continue;
1072#endif
1073
1074 port_mmio = ahci_port_base(mmio, i);
1075 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
1076
1077 ahci_setup_port(&probe_ent->port[i],
1078 (unsigned long) mmio, i);
1079
1080 /* make sure port is not active */
1081 tmp = readl(port_mmio + PORT_CMD);
1082 VPRINTK("PORT_CMD 0x%x\n", tmp);
1083 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
1084 PORT_CMD_FIS_RX | PORT_CMD_START)) {
1085 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
1086 PORT_CMD_FIS_RX | PORT_CMD_START);
1087 writel(tmp, port_mmio + PORT_CMD);
1088 readl(port_mmio + PORT_CMD); /* flush */
1089
1090 /* spec says 500 msecs for each bit, so
1091 * this is slightly incorrect.
1092 */
1093 msleep(500);
1094 }
1095
1096 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
1097
1098 j = 0;
1099 while (j < 100) {
1100 msleep(10);
1101 tmp = readl(port_mmio + PORT_SCR_STAT);
1102 if ((tmp & 0xf) == 0x3)
1103 break;
1104 j++;
1105 }
1106
1107 tmp = readl(port_mmio + PORT_SCR_ERR);
1108 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1109 writel(tmp, port_mmio + PORT_SCR_ERR);
1110
1111 /* ack any pending irq events for this port */
1112 tmp = readl(port_mmio + PORT_IRQ_STAT);
1113 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1114 if (tmp)
1115 writel(tmp, port_mmio + PORT_IRQ_STAT);
1116
1117 writel(1 << i, mmio + HOST_IRQ_STAT);
1118
1119 /* set irq mask (enables interrupts) */
1120 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1121 }
1122
1123 tmp = readl(mmio + HOST_CTL);
1124 VPRINTK("HOST_CTL 0x%x\n", tmp);
1125 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1126 tmp = readl(mmio + HOST_CTL);
1127 VPRINTK("HOST_CTL 0x%x\n", tmp);
1128
1129 pci_set_master(pdev);
1130
1131 return 0;
1132}
1133
1da177e4
LT		 1134static void ahci_print_info(struct ata_probe_ent *probe_ent)
1135{
1136 struct ahci_host_priv *hpriv = probe_ent->private_data;
1137 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
ea6ba10b 1138 void __iomem *mmio = probe_ent->mmio_base;
1da177e4
LT		 1139 u32 vers, cap, impl, speed;
1140 const char *speed_s;
1141 u16 cc;
1142 const char *scc_s;
1143
1144 vers = readl(mmio + HOST_VERSION);
1145 cap = hpriv->cap;
1146 impl = hpriv->port_map;
1147
1148 speed = (cap >> 20) & 0xf;
1149 if (speed == 1)
1150 speed_s = "1.5";
1151 else if (speed == 2)
1152 speed_s = "3";
1153 else
1154 speed_s = "?";
1155
1156 pci_read_config_word(pdev, 0x0a, &cc);
1157 if (cc == 0x0101)
1158 scc_s = "IDE";
1159 else if (cc == 0x0106)
1160 scc_s = "SATA";
1161 else if (cc == 0x0104)
1162 scc_s = "RAID";
1163 else
1164 scc_s = "unknown";
1165
a9524a76
JG		 1166 dev_printk(KERN_INFO, &pdev->dev,
1167 "AHCI %02x%02x.%02x%02x "
1da177e4
LT		 1168 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1169 ,
1da177e4
LT		 1170
1171 (vers >> 24) & 0xff,
1172 (vers >> 16) & 0xff,
1173 (vers >> 8) & 0xff,
1174 vers & 0xff,
1175
1176 ((cap >> 8) & 0x1f) + 1,
1177 (cap & 0x1f) + 1,
1178 speed_s,
1179 impl,
1180 scc_s);
1181
a9524a76
JG		 1182 dev_printk(KERN_INFO, &pdev->dev,
1183 "flags: "
1da177e4
LT		 1184 "%s%s%s%s%s%s"
1185 "%s%s%s%s%s%s%s\n"
1186 ,
1da177e4
LT		 1187
1188 cap & (1 << 31) ? "64bit " : "",
1189 cap & (1 << 30) ? "ncq " : "",
1190 cap & (1 << 28) ? "ilck " : "",
1191 cap & (1 << 27) ? "stag " : "",
1192 cap & (1 << 26) ? "pm " : "",
1193 cap & (1 << 25) ? "led " : "",
1194
1195 cap & (1 << 24) ? "clo " : "",
1196 cap & (1 << 19) ? "nz " : "",
1197 cap & (1 << 18) ? "only " : "",
1198 cap & (1 << 17) ? "pmp " : "",
1199 cap & (1 << 15) ? "pio " : "",
1200 cap & (1 << 14) ? "slum " : "",
1201 cap & (1 << 13) ? "part " : ""
1202 );
1203}
1204
1205static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1206{
1207 static int printed_version;
1208 struct ata_probe_ent *probe_ent = NULL;
1209 struct ahci_host_priv *hpriv;
1210 unsigned long base;
ea6ba10b 1211 void __iomem *mmio_base;
1da177e4 1212 unsigned int board_idx = (unsigned int) ent->driver_data;
907f4678 1213 int have_msi, pci_dev_busy = 0;
1da177e4
LT		 1214 int rc;
1215
1216 VPRINTK("ENTER\n");
1217
1218 if (!printed_version++)
a9524a76 1219 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4
LT		 1220
1221 rc = pci_enable_device(pdev);
1222 if (rc)
1223 return rc;
1224
1225 rc = pci_request_regions(pdev, DRV_NAME);
1226 if (rc) {
1227 pci_dev_busy = 1;
1228 goto err_out;
1229 }
1230
907f4678
JG		 1231 if (pci_enable_msi(pdev) == 0)
1232 have_msi = 1;
1233 else {
1234 pci_intx(pdev, 1);
1235 have_msi = 0;
1236 }
1da177e4
LT		 1237
1238 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1239 if (probe_ent == NULL) {
1240 rc = -ENOMEM;
907f4678 1241 goto err_out_msi;
1da177e4
LT		 1242 }
1243
1244 memset(probe_ent, 0, sizeof(*probe_ent));
1245 probe_ent->dev = pci_dev_to_dev(pdev);
1246 INIT_LIST_HEAD(&probe_ent->node);
1247
374b1873 1248 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1da177e4
LT		 1249 if (mmio_base == NULL) {
1250 rc = -ENOMEM;
1251 goto err_out_free_ent;
1252 }
1253 base = (unsigned long) mmio_base;
1254
1255 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1256 if (!hpriv) {
1257 rc = -ENOMEM;
1258 goto err_out_iounmap;
1259 }
1260 memset(hpriv, 0, sizeof(*hpriv));
1261
1262 probe_ent->sht = ahci_port_info[board_idx].sht;
1263 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1264 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1265 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1266 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1267
1268 probe_ent->irq = pdev->irq;
1269 probe_ent->irq_flags = SA_SHIRQ;
1270 probe_ent->mmio_base = mmio_base;
1271 probe_ent->private_data = hpriv;
1272
4b0060f4
JG		 1273 if (have_msi)
1274 hpriv->flags |= AHCI_FLAG_MSI;
907f4678 1275
bd12097c
JG		 1276 /* JMicron-specific fixup: make sure we're in AHCI mode */
1277 if (pdev->vendor == 0x197b)
1278 pci_write_config_byte(pdev, 0x41, 0xa1);
1279
1da177e4
LT		 1280 /* initialize adapter */
1281 rc = ahci_host_init(probe_ent);
1282 if (rc)
1283 goto err_out_hpriv;
1284
1285 ahci_print_info(probe_ent);
1286
1287 /* FIXME: check ata_device_add return value */
1288 ata_device_add(probe_ent);
1289 kfree(probe_ent);
1290
1291 return 0;
1292
1293err_out_hpriv:
1294 kfree(hpriv);
1295err_out_iounmap:
374b1873 1296 pci_iounmap(pdev, mmio_base);
1da177e4
LT		 1297err_out_free_ent:
1298 kfree(probe_ent);
907f4678
JG		 1299err_out_msi:
1300 if (have_msi)
1301 pci_disable_msi(pdev);
1302 else
1303 pci_intx(pdev, 0);
1da177e4
LT		 1304 pci_release_regions(pdev);
1305err_out:
1306 if (!pci_dev_busy)
1307 pci_disable_device(pdev);
1308 return rc;
1309}
1310
907f4678
JG		 1311static void ahci_remove_one (struct pci_dev *pdev)
1312{
1313 struct device *dev = pci_dev_to_dev(pdev);
1314 struct ata_host_set *host_set = dev_get_drvdata(dev);
1315 struct ahci_host_priv *hpriv = host_set->private_data;
1316 struct ata_port *ap;
1317 unsigned int i;
1318 int have_msi;
1319
1320 for (i = 0; i < host_set->n_ports; i++) {
1321 ap = host_set->ports[i];
1322
1323 scsi_remove_host(ap->host);
1324 }
1325
4b0060f4 1326 have_msi = hpriv->flags & AHCI_FLAG_MSI;
907f4678 1327 free_irq(host_set->irq, host_set);
907f4678
JG		 1328
1329 for (i = 0; i < host_set->n_ports; i++) {
1330 ap = host_set->ports[i];
1331
1332 ata_scsi_release(ap->host);
1333 scsi_host_put(ap->host);
1334 }
1335
e005f01d 1336 kfree(hpriv);
374b1873 1337 pci_iounmap(pdev, host_set->mmio_base);
ead5de99
JG		 1338 kfree(host_set);
1339
907f4678
JG		 1340 if (have_msi)
1341 pci_disable_msi(pdev);
1342 else
1343 pci_intx(pdev, 0);
1344 pci_release_regions(pdev);
907f4678
JG		 1345 pci_disable_device(pdev);
1346 dev_set_drvdata(dev, NULL);
1347}
1da177e4
LT		 1348
1349static int __init ahci_init(void)
1350{
1351 return pci_module_init(&ahci_pci_driver);
1352}
1353
1da177e4
LT		 1354static void __exit ahci_exit(void)
1355{
1356 pci_unregister_driver(&ahci_pci_driver);
1357}
1358
1359
1360MODULE_AUTHOR("Jeff Garzik");
1361MODULE_DESCRIPTION("AHCI SATA low-level driver");
1362MODULE_LICENSE("GPL");
1363MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1364MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 1365
1366module_init(ahci_init);
1367module_exit(ahci_exit);
Linux kernel - Deliverables
This page took 0.169309 seconds and 5 git commands to generate.